mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f407xx.h@613:bc40b8d2aec4, 2015-08-20 (annotated)

Committer:
mbed_official
Date:
Thu Aug 20 10:45:13 2015 +0100
Revision:
613:bc40b8d2aec4
Parent:
532:fe11edbda85c 
Synchronized with git revision 92ca8c7b60a283b6bb60eb65b183dac1599f0ade



Full URL: https://github.com/mbedmicro/mbed/commit/92ca8c7b60a283b6bb60eb65b183dac1599f0ade/



Nordic: update application start address in GCC linker script

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 133:d4dda5c437f0 1 /**
mbed_official 133:d4dda5c437f0 2 ******************************************************************************
mbed_official 133:d4dda5c437f0 3 * @file stm32f407xx.h
mbed_official 133:d4dda5c437f0 4 * @author MCD Application Team
mbed_official 613:bc40b8d2aec4 5 * @version V2.3.2
mbed_official 613:bc40b8d2aec4 6 * @date 26-June-2015
mbed_official 133:d4dda5c437f0 7 * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
mbed_official 133:d4dda5c437f0 8 *
mbed_official 133:d4dda5c437f0 9 * This file contains:
mbed_official 133:d4dda5c437f0 10 * - Data structures and the address mapping for all peripherals
mbed_official 133:d4dda5c437f0 11 * - Peripheral's registers declarations and bits definition
mbed_official 133:d4dda5c437f0 12 * - Macros to access peripheral’s registers hardware
mbed_official 133:d4dda5c437f0 13 *
mbed_official 133:d4dda5c437f0 14 ******************************************************************************
mbed_official 133:d4dda5c437f0 15 * @attention
mbed_official 133:d4dda5c437f0 16 *
mbed_official 532:fe11edbda85c 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 133:d4dda5c437f0 18 *
mbed_official 133:d4dda5c437f0 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 133:d4dda5c437f0 20 * are permitted provided that the following conditions are met:
mbed_official 133:d4dda5c437f0 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 133:d4dda5c437f0 22 * this list of conditions and the following disclaimer.
mbed_official 133:d4dda5c437f0 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 133:d4dda5c437f0 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 133:d4dda5c437f0 25 * and/or other materials provided with the distribution.
mbed_official 133:d4dda5c437f0 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 133:d4dda5c437f0 27 * may be used to endorse or promote products derived from this software
mbed_official 133:d4dda5c437f0 28 * without specific prior written permission.
mbed_official 133:d4dda5c437f0 29 *
mbed_official 133:d4dda5c437f0 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 133:d4dda5c437f0 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 133:d4dda5c437f0 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 133:d4dda5c437f0 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 133:d4dda5c437f0 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 133:d4dda5c437f0 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 133:d4dda5c437f0 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 133:d4dda5c437f0 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 133:d4dda5c437f0 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 133:d4dda5c437f0 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 133:d4dda5c437f0 40 *
mbed_official 133:d4dda5c437f0 41 ******************************************************************************
mbed_official 133:d4dda5c437f0 42 */
mbed_official 133:d4dda5c437f0 43
mbed_official 133:d4dda5c437f0 44 /** @addtogroup CMSIS
mbed_official 133:d4dda5c437f0 45 * @{
mbed_official 133:d4dda5c437f0 46 */
mbed_official 133:d4dda5c437f0 47
mbed_official 133:d4dda5c437f0 48 /** @addtogroup stm32f407xx
mbed_official 133:d4dda5c437f0 49 * @{
mbed_official 133:d4dda5c437f0 50 */
mbed_official 133:d4dda5c437f0 51
mbed_official 133:d4dda5c437f0 52 #ifndef __STM32F407xx_H
mbed_official 133:d4dda5c437f0 53 #define __STM32F407xx_H
mbed_official 133:d4dda5c437f0 54
mbed_official 133:d4dda5c437f0 55 #ifdef __cplusplus
mbed_official 133:d4dda5c437f0 56 extern "C" {
mbed_official 133:d4dda5c437f0 57 #endif /* __cplusplus */
mbed_official 133:d4dda5c437f0 58
mbed_official 133:d4dda5c437f0 59
mbed_official 133:d4dda5c437f0 60 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 133:d4dda5c437f0 61 * @{
mbed_official 133:d4dda5c437f0 62 */
mbed_official 133:d4dda5c437f0 63
mbed_official 133:d4dda5c437f0 64 /**
mbed_official 133:d4dda5c437f0 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
mbed_official 133:d4dda5c437f0 66 */
mbed_official 133:d4dda5c437f0 67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
mbed_official 133:d4dda5c437f0 68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
mbed_official 133:d4dda5c437f0 69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
mbed_official 133:d4dda5c437f0 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 133:d4dda5c437f0 71 #define __FPU_PRESENT 1 /*!< FPU present */
mbed_official 133:d4dda5c437f0 72
mbed_official 133:d4dda5c437f0 73 /**
mbed_official 133:d4dda5c437f0 74 * @}
mbed_official 133:d4dda5c437f0 75 */
mbed_official 133:d4dda5c437f0 76
mbed_official 133:d4dda5c437f0 77 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 133:d4dda5c437f0 78 * @{
mbed_official 133:d4dda5c437f0 79 */
mbed_official 133:d4dda5c437f0 80
mbed_official 133:d4dda5c437f0 81 /**
mbed_official 133:d4dda5c437f0 82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
mbed_official 133:d4dda5c437f0 83 * in @ref Library_configuration_section
mbed_official 133:d4dda5c437f0 84 */
mbed_official 133:d4dda5c437f0 85 typedef enum
mbed_official 133:d4dda5c437f0 86 {
mbed_official 133:d4dda5c437f0 87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
mbed_official 133:d4dda5c437f0 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 133:d4dda5c437f0 89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
mbed_official 133:d4dda5c437f0 90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
mbed_official 133:d4dda5c437f0 91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
mbed_official 133:d4dda5c437f0 92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
mbed_official 133:d4dda5c437f0 93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
mbed_official 133:d4dda5c437f0 94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
mbed_official 133:d4dda5c437f0 95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
mbed_official 133:d4dda5c437f0 96 /****** STM32 specific Interrupt Numbers **********************************************************************/
mbed_official 133:d4dda5c437f0 97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 133:d4dda5c437f0 98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 133:d4dda5c437f0 99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
mbed_official 133:d4dda5c437f0 100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
mbed_official 133:d4dda5c437f0 101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 133:d4dda5c437f0 102 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 133:d4dda5c437f0 103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 133:d4dda5c437f0 104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 133:d4dda5c437f0 105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
mbed_official 133:d4dda5c437f0 106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 133:d4dda5c437f0 107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 133:d4dda5c437f0 108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
mbed_official 133:d4dda5c437f0 109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
mbed_official 133:d4dda5c437f0 110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
mbed_official 133:d4dda5c437f0 111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
mbed_official 133:d4dda5c437f0 112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
mbed_official 133:d4dda5c437f0 113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
mbed_official 133:d4dda5c437f0 114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
mbed_official 133:d4dda5c437f0 115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
mbed_official 133:d4dda5c437f0 116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
mbed_official 133:d4dda5c437f0 117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
mbed_official 133:d4dda5c437f0 118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
mbed_official 133:d4dda5c437f0 119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
mbed_official 133:d4dda5c437f0 120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 133:d4dda5c437f0 121 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
mbed_official 133:d4dda5c437f0 122 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
mbed_official 133:d4dda5c437f0 123 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
mbed_official 133:d4dda5c437f0 124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 133:d4dda5c437f0 125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 133:d4dda5c437f0 126 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 133:d4dda5c437f0 127 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
mbed_official 133:d4dda5c437f0 128 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 133:d4dda5c437f0 129 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 133:d4dda5c437f0 130 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 133:d4dda5c437f0 131 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 133:d4dda5c437f0 132 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 133:d4dda5c437f0 133 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 133:d4dda5c437f0 134 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 133:d4dda5c437f0 135 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 133:d4dda5c437f0 136 USART3_IRQn = 39, /*!< USART3 global Interrupt */
mbed_official 133:d4dda5c437f0 137 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 133:d4dda5c437f0 138 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
mbed_official 133:d4dda5c437f0 139 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
mbed_official 133:d4dda5c437f0 140 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
mbed_official 133:d4dda5c437f0 141 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
mbed_official 133:d4dda5c437f0 142 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
mbed_official 133:d4dda5c437f0 143 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
mbed_official 133:d4dda5c437f0 144 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
mbed_official 133:d4dda5c437f0 145 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
mbed_official 133:d4dda5c437f0 146 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
mbed_official 133:d4dda5c437f0 147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
mbed_official 133:d4dda5c437f0 148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
mbed_official 133:d4dda5c437f0 149 UART4_IRQn = 52, /*!< UART4 global Interrupt */
mbed_official 133:d4dda5c437f0 150 UART5_IRQn = 53, /*!< UART5 global Interrupt */
mbed_official 133:d4dda5c437f0 151 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
mbed_official 133:d4dda5c437f0 152 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
mbed_official 133:d4dda5c437f0 153 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
mbed_official 133:d4dda5c437f0 154 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
mbed_official 133:d4dda5c437f0 155 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
mbed_official 133:d4dda5c437f0 156 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
mbed_official 133:d4dda5c437f0 157 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
mbed_official 133:d4dda5c437f0 158 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
mbed_official 133:d4dda5c437f0 159 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
mbed_official 133:d4dda5c437f0 160 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
mbed_official 133:d4dda5c437f0 161 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
mbed_official 133:d4dda5c437f0 162 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
mbed_official 133:d4dda5c437f0 163 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
mbed_official 133:d4dda5c437f0 164 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
mbed_official 133:d4dda5c437f0 165 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
mbed_official 133:d4dda5c437f0 166 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
mbed_official 133:d4dda5c437f0 167 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
mbed_official 133:d4dda5c437f0 168 USART6_IRQn = 71, /*!< USART6 global interrupt */
mbed_official 133:d4dda5c437f0 169 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
mbed_official 133:d4dda5c437f0 170 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
mbed_official 133:d4dda5c437f0 171 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
mbed_official 133:d4dda5c437f0 172 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
mbed_official 133:d4dda5c437f0 173 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
mbed_official 133:d4dda5c437f0 174 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
mbed_official 133:d4dda5c437f0 175 DCMI_IRQn = 78, /*!< DCMI global interrupt */
mbed_official 133:d4dda5c437f0 176 HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
mbed_official 133:d4dda5c437f0 177 FPU_IRQn = 81 /*!< FPU global interrupt */
mbed_official 133:d4dda5c437f0 178 } IRQn_Type;
mbed_official 133:d4dda5c437f0 179
mbed_official 133:d4dda5c437f0 180 /**
mbed_official 133:d4dda5c437f0 181 * @}
mbed_official 133:d4dda5c437f0 182 */
mbed_official 133:d4dda5c437f0 183
mbed_official 133:d4dda5c437f0 184 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
mbed_official 133:d4dda5c437f0 185 #include "system_stm32f4xx.h"
mbed_official 133:d4dda5c437f0 186 #include <stdint.h>
mbed_official 133:d4dda5c437f0 187
mbed_official 133:d4dda5c437f0 188 /** @addtogroup Peripheral_registers_structures
mbed_official 133:d4dda5c437f0 189 * @{
mbed_official 133:d4dda5c437f0 190 */
mbed_official 133:d4dda5c437f0 191
mbed_official 133:d4dda5c437f0 192 /**
mbed_official 133:d4dda5c437f0 193 * @brief Analog to Digital Converter
mbed_official 133:d4dda5c437f0 194 */
mbed_official 133:d4dda5c437f0 195
mbed_official 133:d4dda5c437f0 196 typedef struct
mbed_official 133:d4dda5c437f0 197 {
mbed_official 133:d4dda5c437f0 198 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 199 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 200 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 201 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 202 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
mbed_official 133:d4dda5c437f0 203 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
mbed_official 133:d4dda5c437f0 204 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
mbed_official 133:d4dda5c437f0 205 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
mbed_official 133:d4dda5c437f0 206 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
mbed_official 133:d4dda5c437f0 207 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
mbed_official 133:d4dda5c437f0 208 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
mbed_official 133:d4dda5c437f0 209 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
mbed_official 133:d4dda5c437f0 210 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
mbed_official 133:d4dda5c437f0 211 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
mbed_official 133:d4dda5c437f0 212 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
mbed_official 133:d4dda5c437f0 213 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
mbed_official 133:d4dda5c437f0 214 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
mbed_official 133:d4dda5c437f0 215 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
mbed_official 133:d4dda5c437f0 216 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
mbed_official 133:d4dda5c437f0 217 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
mbed_official 133:d4dda5c437f0 218 } ADC_TypeDef;
mbed_official 133:d4dda5c437f0 219
mbed_official 133:d4dda5c437f0 220 typedef struct
mbed_official 133:d4dda5c437f0 221 {
mbed_official 133:d4dda5c437f0 222 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
mbed_official 133:d4dda5c437f0 223 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
mbed_official 133:d4dda5c437f0 224 __IO uint32_t CDR; /*!< ADC common regular data register for dual
mbed_official 133:d4dda5c437f0 225 AND triple modes, Address offset: ADC1 base address + 0x308 */
mbed_official 133:d4dda5c437f0 226 } ADC_Common_TypeDef;
mbed_official 133:d4dda5c437f0 227
mbed_official 133:d4dda5c437f0 228
mbed_official 133:d4dda5c437f0 229 /**
mbed_official 133:d4dda5c437f0 230 * @brief Controller Area Network TxMailBox
mbed_official 133:d4dda5c437f0 231 */
mbed_official 133:d4dda5c437f0 232
mbed_official 133:d4dda5c437f0 233 typedef struct
mbed_official 133:d4dda5c437f0 234 {
mbed_official 133:d4dda5c437f0 235 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
mbed_official 133:d4dda5c437f0 236 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
mbed_official 133:d4dda5c437f0 237 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
mbed_official 133:d4dda5c437f0 238 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
mbed_official 133:d4dda5c437f0 239 } CAN_TxMailBox_TypeDef;
mbed_official 133:d4dda5c437f0 240
mbed_official 133:d4dda5c437f0 241 /**
mbed_official 133:d4dda5c437f0 242 * @brief Controller Area Network FIFOMailBox
mbed_official 133:d4dda5c437f0 243 */
mbed_official 133:d4dda5c437f0 244
mbed_official 133:d4dda5c437f0 245 typedef struct
mbed_official 133:d4dda5c437f0 246 {
mbed_official 133:d4dda5c437f0 247 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
mbed_official 133:d4dda5c437f0 248 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
mbed_official 133:d4dda5c437f0 249 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
mbed_official 133:d4dda5c437f0 250 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
mbed_official 133:d4dda5c437f0 251 } CAN_FIFOMailBox_TypeDef;
mbed_official 133:d4dda5c437f0 252
mbed_official 133:d4dda5c437f0 253 /**
mbed_official 133:d4dda5c437f0 254 * @brief Controller Area Network FilterRegister
mbed_official 133:d4dda5c437f0 255 */
mbed_official 133:d4dda5c437f0 256
mbed_official 133:d4dda5c437f0 257 typedef struct
mbed_official 133:d4dda5c437f0 258 {
mbed_official 133:d4dda5c437f0 259 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
mbed_official 133:d4dda5c437f0 260 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
mbed_official 133:d4dda5c437f0 261 } CAN_FilterRegister_TypeDef;
mbed_official 133:d4dda5c437f0 262
mbed_official 133:d4dda5c437f0 263 /**
mbed_official 133:d4dda5c437f0 264 * @brief Controller Area Network
mbed_official 133:d4dda5c437f0 265 */
mbed_official 133:d4dda5c437f0 266
mbed_official 133:d4dda5c437f0 267 typedef struct
mbed_official 133:d4dda5c437f0 268 {
mbed_official 133:d4dda5c437f0 269 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 270 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 271 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 272 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 273 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
mbed_official 133:d4dda5c437f0 274 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
mbed_official 133:d4dda5c437f0 275 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
mbed_official 133:d4dda5c437f0 276 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
mbed_official 133:d4dda5c437f0 277 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
mbed_official 133:d4dda5c437f0 278 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
mbed_official 133:d4dda5c437f0 279 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
mbed_official 133:d4dda5c437f0 280 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
mbed_official 133:d4dda5c437f0 281 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
mbed_official 133:d4dda5c437f0 282 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
mbed_official 133:d4dda5c437f0 283 uint32_t RESERVED2; /*!< Reserved, 0x208 */
mbed_official 133:d4dda5c437f0 284 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
mbed_official 133:d4dda5c437f0 285 uint32_t RESERVED3; /*!< Reserved, 0x210 */
mbed_official 133:d4dda5c437f0 286 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
mbed_official 133:d4dda5c437f0 287 uint32_t RESERVED4; /*!< Reserved, 0x218 */
mbed_official 133:d4dda5c437f0 288 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
mbed_official 133:d4dda5c437f0 289 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
mbed_official 133:d4dda5c437f0 290 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
mbed_official 133:d4dda5c437f0 291 } CAN_TypeDef;
mbed_official 133:d4dda5c437f0 292
mbed_official 133:d4dda5c437f0 293 /**
mbed_official 133:d4dda5c437f0 294 * @brief CRC calculation unit
mbed_official 133:d4dda5c437f0 295 */
mbed_official 133:d4dda5c437f0 296
mbed_official 133:d4dda5c437f0 297 typedef struct
mbed_official 133:d4dda5c437f0 298 {
mbed_official 133:d4dda5c437f0 299 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 300 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 301 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 133:d4dda5c437f0 302 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 133:d4dda5c437f0 303 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 304 } CRC_TypeDef;
mbed_official 133:d4dda5c437f0 305
mbed_official 133:d4dda5c437f0 306 /**
mbed_official 133:d4dda5c437f0 307 * @brief Digital to Analog Converter
mbed_official 133:d4dda5c437f0 308 */
mbed_official 133:d4dda5c437f0 309
mbed_official 133:d4dda5c437f0 310 typedef struct
mbed_official 133:d4dda5c437f0 311 {
mbed_official 133:d4dda5c437f0 312 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 313 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 314 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 315 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 316 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 133:d4dda5c437f0 317 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 133:d4dda5c437f0 318 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 133:d4dda5c437f0 319 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 133:d4dda5c437f0 320 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 133:d4dda5c437f0 321 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 133:d4dda5c437f0 322 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 133:d4dda5c437f0 323 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 133:d4dda5c437f0 324 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 133:d4dda5c437f0 325 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 133:d4dda5c437f0 326 } DAC_TypeDef;
mbed_official 133:d4dda5c437f0 327
mbed_official 133:d4dda5c437f0 328 /**
mbed_official 133:d4dda5c437f0 329 * @brief Debug MCU
mbed_official 133:d4dda5c437f0 330 */
mbed_official 133:d4dda5c437f0 331
mbed_official 133:d4dda5c437f0 332 typedef struct
mbed_official 133:d4dda5c437f0 333 {
mbed_official 133:d4dda5c437f0 334 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 335 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 336 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 337 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 338 }DBGMCU_TypeDef;
mbed_official 133:d4dda5c437f0 339
mbed_official 133:d4dda5c437f0 340 /**
mbed_official 133:d4dda5c437f0 341 * @brief DCMI
mbed_official 133:d4dda5c437f0 342 */
mbed_official 133:d4dda5c437f0 343
mbed_official 133:d4dda5c437f0 344 typedef struct
mbed_official 133:d4dda5c437f0 345 {
mbed_official 133:d4dda5c437f0 346 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 347 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 348 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 349 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 350 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
mbed_official 133:d4dda5c437f0 351 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
mbed_official 133:d4dda5c437f0 352 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
mbed_official 133:d4dda5c437f0 353 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
mbed_official 133:d4dda5c437f0 354 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
mbed_official 133:d4dda5c437f0 355 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
mbed_official 133:d4dda5c437f0 356 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
mbed_official 133:d4dda5c437f0 357 } DCMI_TypeDef;
mbed_official 133:d4dda5c437f0 358
mbed_official 133:d4dda5c437f0 359 /**
mbed_official 133:d4dda5c437f0 360 * @brief DMA Controller
mbed_official 133:d4dda5c437f0 361 */
mbed_official 133:d4dda5c437f0 362
mbed_official 133:d4dda5c437f0 363 typedef struct
mbed_official 133:d4dda5c437f0 364 {
mbed_official 133:d4dda5c437f0 365 __IO uint32_t CR; /*!< DMA stream x configuration register */
mbed_official 133:d4dda5c437f0 366 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
mbed_official 133:d4dda5c437f0 367 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
mbed_official 133:d4dda5c437f0 368 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
mbed_official 133:d4dda5c437f0 369 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
mbed_official 133:d4dda5c437f0 370 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
mbed_official 133:d4dda5c437f0 371 } DMA_Stream_TypeDef;
mbed_official 133:d4dda5c437f0 372
mbed_official 133:d4dda5c437f0 373 typedef struct
mbed_official 133:d4dda5c437f0 374 {
mbed_official 133:d4dda5c437f0 375 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 376 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 377 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 378 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 379 } DMA_TypeDef;
mbed_official 133:d4dda5c437f0 380
mbed_official 133:d4dda5c437f0 381
mbed_official 133:d4dda5c437f0 382 /**
mbed_official 133:d4dda5c437f0 383 * @brief Ethernet MAC
mbed_official 133:d4dda5c437f0 384 */
mbed_official 133:d4dda5c437f0 385
mbed_official 133:d4dda5c437f0 386 typedef struct
mbed_official 133:d4dda5c437f0 387 {
mbed_official 133:d4dda5c437f0 388 __IO uint32_t MACCR;
mbed_official 133:d4dda5c437f0 389 __IO uint32_t MACFFR;
mbed_official 133:d4dda5c437f0 390 __IO uint32_t MACHTHR;
mbed_official 133:d4dda5c437f0 391 __IO uint32_t MACHTLR;
mbed_official 133:d4dda5c437f0 392 __IO uint32_t MACMIIAR;
mbed_official 133:d4dda5c437f0 393 __IO uint32_t MACMIIDR;
mbed_official 133:d4dda5c437f0 394 __IO uint32_t MACFCR;
mbed_official 133:d4dda5c437f0 395 __IO uint32_t MACVLANTR; /* 8 */
mbed_official 133:d4dda5c437f0 396 uint32_t RESERVED0[2];
mbed_official 133:d4dda5c437f0 397 __IO uint32_t MACRWUFFR; /* 11 */
mbed_official 133:d4dda5c437f0 398 __IO uint32_t MACPMTCSR;
mbed_official 133:d4dda5c437f0 399 uint32_t RESERVED1[2];
mbed_official 133:d4dda5c437f0 400 __IO uint32_t MACSR; /* 15 */
mbed_official 133:d4dda5c437f0 401 __IO uint32_t MACIMR;
mbed_official 133:d4dda5c437f0 402 __IO uint32_t MACA0HR;
mbed_official 133:d4dda5c437f0 403 __IO uint32_t MACA0LR;
mbed_official 133:d4dda5c437f0 404 __IO uint32_t MACA1HR;
mbed_official 133:d4dda5c437f0 405 __IO uint32_t MACA1LR;
mbed_official 133:d4dda5c437f0 406 __IO uint32_t MACA2HR;
mbed_official 133:d4dda5c437f0 407 __IO uint32_t MACA2LR;
mbed_official 133:d4dda5c437f0 408 __IO uint32_t MACA3HR;
mbed_official 133:d4dda5c437f0 409 __IO uint32_t MACA3LR; /* 24 */
mbed_official 133:d4dda5c437f0 410 uint32_t RESERVED2[40];
mbed_official 133:d4dda5c437f0 411 __IO uint32_t MMCCR; /* 65 */
mbed_official 133:d4dda5c437f0 412 __IO uint32_t MMCRIR;
mbed_official 133:d4dda5c437f0 413 __IO uint32_t MMCTIR;
mbed_official 133:d4dda5c437f0 414 __IO uint32_t MMCRIMR;
mbed_official 133:d4dda5c437f0 415 __IO uint32_t MMCTIMR; /* 69 */
mbed_official 133:d4dda5c437f0 416 uint32_t RESERVED3[14];
mbed_official 133:d4dda5c437f0 417 __IO uint32_t MMCTGFSCCR; /* 84 */
mbed_official 133:d4dda5c437f0 418 __IO uint32_t MMCTGFMSCCR;
mbed_official 133:d4dda5c437f0 419 uint32_t RESERVED4[5];
mbed_official 133:d4dda5c437f0 420 __IO uint32_t MMCTGFCR;
mbed_official 133:d4dda5c437f0 421 uint32_t RESERVED5[10];
mbed_official 133:d4dda5c437f0 422 __IO uint32_t MMCRFCECR;
mbed_official 133:d4dda5c437f0 423 __IO uint32_t MMCRFAECR;
mbed_official 133:d4dda5c437f0 424 uint32_t RESERVED6[10];
mbed_official 133:d4dda5c437f0 425 __IO uint32_t MMCRGUFCR;
mbed_official 133:d4dda5c437f0 426 uint32_t RESERVED7[334];
mbed_official 133:d4dda5c437f0 427 __IO uint32_t PTPTSCR;
mbed_official 133:d4dda5c437f0 428 __IO uint32_t PTPSSIR;
mbed_official 133:d4dda5c437f0 429 __IO uint32_t PTPTSHR;
mbed_official 133:d4dda5c437f0 430 __IO uint32_t PTPTSLR;
mbed_official 133:d4dda5c437f0 431 __IO uint32_t PTPTSHUR;
mbed_official 133:d4dda5c437f0 432 __IO uint32_t PTPTSLUR;
mbed_official 133:d4dda5c437f0 433 __IO uint32_t PTPTSAR;
mbed_official 133:d4dda5c437f0 434 __IO uint32_t PTPTTHR;
mbed_official 133:d4dda5c437f0 435 __IO uint32_t PTPTTLR;
mbed_official 133:d4dda5c437f0 436 __IO uint32_t RESERVED8;
mbed_official 133:d4dda5c437f0 437 __IO uint32_t PTPTSSR;
mbed_official 133:d4dda5c437f0 438 uint32_t RESERVED9[565];
mbed_official 133:d4dda5c437f0 439 __IO uint32_t DMABMR;
mbed_official 133:d4dda5c437f0 440 __IO uint32_t DMATPDR;
mbed_official 133:d4dda5c437f0 441 __IO uint32_t DMARPDR;
mbed_official 133:d4dda5c437f0 442 __IO uint32_t DMARDLAR;
mbed_official 133:d4dda5c437f0 443 __IO uint32_t DMATDLAR;
mbed_official 133:d4dda5c437f0 444 __IO uint32_t DMASR;
mbed_official 133:d4dda5c437f0 445 __IO uint32_t DMAOMR;
mbed_official 133:d4dda5c437f0 446 __IO uint32_t DMAIER;
mbed_official 133:d4dda5c437f0 447 __IO uint32_t DMAMFBOCR;
mbed_official 133:d4dda5c437f0 448 __IO uint32_t DMARSWTR;
mbed_official 133:d4dda5c437f0 449 uint32_t RESERVED10[8];
mbed_official 133:d4dda5c437f0 450 __IO uint32_t DMACHTDR;
mbed_official 133:d4dda5c437f0 451 __IO uint32_t DMACHRDR;
mbed_official 133:d4dda5c437f0 452 __IO uint32_t DMACHTBAR;
mbed_official 133:d4dda5c437f0 453 __IO uint32_t DMACHRBAR;
mbed_official 133:d4dda5c437f0 454 } ETH_TypeDef;
mbed_official 133:d4dda5c437f0 455
mbed_official 133:d4dda5c437f0 456 /**
mbed_official 133:d4dda5c437f0 457 * @brief External Interrupt/Event Controller
mbed_official 133:d4dda5c437f0 458 */
mbed_official 133:d4dda5c437f0 459
mbed_official 133:d4dda5c437f0 460 typedef struct
mbed_official 133:d4dda5c437f0 461 {
mbed_official 133:d4dda5c437f0 462 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 463 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 464 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 465 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 466 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 133:d4dda5c437f0 467 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
mbed_official 133:d4dda5c437f0 468 } EXTI_TypeDef;
mbed_official 133:d4dda5c437f0 469
mbed_official 133:d4dda5c437f0 470 /**
mbed_official 133:d4dda5c437f0 471 * @brief FLASH Registers
mbed_official 133:d4dda5c437f0 472 */
mbed_official 133:d4dda5c437f0 473
mbed_official 133:d4dda5c437f0 474 typedef struct
mbed_official 133:d4dda5c437f0 475 {
mbed_official 133:d4dda5c437f0 476 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 477 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 478 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 479 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 480 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
mbed_official 133:d4dda5c437f0 481 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
mbed_official 133:d4dda5c437f0 482 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
mbed_official 133:d4dda5c437f0 483 } FLASH_TypeDef;
mbed_official 133:d4dda5c437f0 484
mbed_official 133:d4dda5c437f0 485
mbed_official 133:d4dda5c437f0 486 /**
mbed_official 133:d4dda5c437f0 487 * @brief Flexible Static Memory Controller
mbed_official 133:d4dda5c437f0 488 */
mbed_official 133:d4dda5c437f0 489
mbed_official 133:d4dda5c437f0 490 typedef struct
mbed_official 133:d4dda5c437f0 491 {
mbed_official 133:d4dda5c437f0 492 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
mbed_official 133:d4dda5c437f0 493 } FSMC_Bank1_TypeDef;
mbed_official 133:d4dda5c437f0 494
mbed_official 133:d4dda5c437f0 495 /**
mbed_official 133:d4dda5c437f0 496 * @brief Flexible Static Memory Controller Bank1E
mbed_official 133:d4dda5c437f0 497 */
mbed_official 133:d4dda5c437f0 498
mbed_official 133:d4dda5c437f0 499 typedef struct
mbed_official 133:d4dda5c437f0 500 {
mbed_official 133:d4dda5c437f0 501 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
mbed_official 133:d4dda5c437f0 502 } FSMC_Bank1E_TypeDef;
mbed_official 133:d4dda5c437f0 503
mbed_official 133:d4dda5c437f0 504 /**
mbed_official 133:d4dda5c437f0 505 * @brief Flexible Static Memory Controller Bank2
mbed_official 133:d4dda5c437f0 506 */
mbed_official 133:d4dda5c437f0 507
mbed_official 133:d4dda5c437f0 508 typedef struct
mbed_official 133:d4dda5c437f0 509 {
mbed_official 133:d4dda5c437f0 510 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
mbed_official 133:d4dda5c437f0 511 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
mbed_official 133:d4dda5c437f0 512 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
mbed_official 133:d4dda5c437f0 513 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
mbed_official 133:d4dda5c437f0 514 uint32_t RESERVED0; /*!< Reserved, 0x70 */
mbed_official 133:d4dda5c437f0 515 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
mbed_official 133:d4dda5c437f0 516 uint32_t RESERVED1; /*!< Reserved, 0x78 */
mbed_official 133:d4dda5c437f0 517 uint32_t RESERVED2; /*!< Reserved, 0x7C */
mbed_official 133:d4dda5c437f0 518 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
mbed_official 133:d4dda5c437f0 519 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
mbed_official 133:d4dda5c437f0 520 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
mbed_official 133:d4dda5c437f0 521 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
mbed_official 133:d4dda5c437f0 522 uint32_t RESERVED3; /*!< Reserved, 0x90 */
mbed_official 133:d4dda5c437f0 523 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
mbed_official 133:d4dda5c437f0 524 } FSMC_Bank2_3_TypeDef;
mbed_official 133:d4dda5c437f0 525
mbed_official 133:d4dda5c437f0 526 /**
mbed_official 133:d4dda5c437f0 527 * @brief Flexible Static Memory Controller Bank4
mbed_official 133:d4dda5c437f0 528 */
mbed_official 133:d4dda5c437f0 529
mbed_official 133:d4dda5c437f0 530 typedef struct
mbed_official 133:d4dda5c437f0 531 {
mbed_official 133:d4dda5c437f0 532 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
mbed_official 133:d4dda5c437f0 533 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
mbed_official 133:d4dda5c437f0 534 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
mbed_official 133:d4dda5c437f0 535 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
mbed_official 133:d4dda5c437f0 536 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
mbed_official 133:d4dda5c437f0 537 } FSMC_Bank4_TypeDef;
mbed_official 133:d4dda5c437f0 538
mbed_official 133:d4dda5c437f0 539
mbed_official 133:d4dda5c437f0 540 /**
mbed_official 133:d4dda5c437f0 541 * @brief General Purpose I/O
mbed_official 133:d4dda5c437f0 542 */
mbed_official 133:d4dda5c437f0 543
mbed_official 133:d4dda5c437f0 544 typedef struct
mbed_official 133:d4dda5c437f0 545 {
mbed_official 133:d4dda5c437f0 546 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 547 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 548 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 549 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 550 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 133:d4dda5c437f0 551 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 532:fe11edbda85c 552 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
mbed_official 133:d4dda5c437f0 553 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 133:d4dda5c437f0 554 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
mbed_official 133:d4dda5c437f0 555 } GPIO_TypeDef;
mbed_official 133:d4dda5c437f0 556
mbed_official 133:d4dda5c437f0 557 /**
mbed_official 133:d4dda5c437f0 558 * @brief System configuration controller
mbed_official 133:d4dda5c437f0 559 */
mbed_official 133:d4dda5c437f0 560
mbed_official 133:d4dda5c437f0 561 typedef struct
mbed_official 133:d4dda5c437f0 562 {
mbed_official 133:d4dda5c437f0 563 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 564 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 565 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
mbed_official 133:d4dda5c437f0 566 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
mbed_official 133:d4dda5c437f0 567 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
mbed_official 133:d4dda5c437f0 568 } SYSCFG_TypeDef;
mbed_official 133:d4dda5c437f0 569
mbed_official 133:d4dda5c437f0 570 /**
mbed_official 133:d4dda5c437f0 571 * @brief Inter-integrated Circuit Interface
mbed_official 133:d4dda5c437f0 572 */
mbed_official 133:d4dda5c437f0 573
mbed_official 133:d4dda5c437f0 574 typedef struct
mbed_official 133:d4dda5c437f0 575 {
mbed_official 133:d4dda5c437f0 576 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 577 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 578 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 579 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 580 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
mbed_official 133:d4dda5c437f0 581 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
mbed_official 133:d4dda5c437f0 582 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
mbed_official 133:d4dda5c437f0 583 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
mbed_official 133:d4dda5c437f0 584 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
mbed_official 133:d4dda5c437f0 585 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
mbed_official 133:d4dda5c437f0 586 } I2C_TypeDef;
mbed_official 133:d4dda5c437f0 587
mbed_official 133:d4dda5c437f0 588 /**
mbed_official 133:d4dda5c437f0 589 * @brief Independent WATCHDOG
mbed_official 133:d4dda5c437f0 590 */
mbed_official 133:d4dda5c437f0 591
mbed_official 133:d4dda5c437f0 592 typedef struct
mbed_official 133:d4dda5c437f0 593 {
mbed_official 133:d4dda5c437f0 594 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 595 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 596 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 597 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 598 } IWDG_TypeDef;
mbed_official 133:d4dda5c437f0 599
mbed_official 133:d4dda5c437f0 600 /**
mbed_official 133:d4dda5c437f0 601 * @brief Power Control
mbed_official 133:d4dda5c437f0 602 */
mbed_official 133:d4dda5c437f0 603
mbed_official 133:d4dda5c437f0 604 typedef struct
mbed_official 133:d4dda5c437f0 605 {
mbed_official 133:d4dda5c437f0 606 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 607 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 608 } PWR_TypeDef;
mbed_official 133:d4dda5c437f0 609
mbed_official 133:d4dda5c437f0 610 /**
mbed_official 133:d4dda5c437f0 611 * @brief Reset and Clock Control
mbed_official 133:d4dda5c437f0 612 */
mbed_official 133:d4dda5c437f0 613
mbed_official 133:d4dda5c437f0 614 typedef struct
mbed_official 133:d4dda5c437f0 615 {
mbed_official 133:d4dda5c437f0 616 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 617 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 618 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 619 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 620 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
mbed_official 133:d4dda5c437f0 621 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
mbed_official 133:d4dda5c437f0 622 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
mbed_official 133:d4dda5c437f0 623 uint32_t RESERVED0; /*!< Reserved, 0x1C */
mbed_official 133:d4dda5c437f0 624 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
mbed_official 133:d4dda5c437f0 625 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
mbed_official 133:d4dda5c437f0 626 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
mbed_official 133:d4dda5c437f0 627 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
mbed_official 133:d4dda5c437f0 628 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
mbed_official 133:d4dda5c437f0 629 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
mbed_official 133:d4dda5c437f0 630 uint32_t RESERVED2; /*!< Reserved, 0x3C */
mbed_official 133:d4dda5c437f0 631 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
mbed_official 133:d4dda5c437f0 632 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
mbed_official 133:d4dda5c437f0 633 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
mbed_official 133:d4dda5c437f0 634 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
mbed_official 133:d4dda5c437f0 635 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
mbed_official 133:d4dda5c437f0 636 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
mbed_official 133:d4dda5c437f0 637 uint32_t RESERVED4; /*!< Reserved, 0x5C */
mbed_official 133:d4dda5c437f0 638 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
mbed_official 133:d4dda5c437f0 639 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
mbed_official 133:d4dda5c437f0 640 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
mbed_official 133:d4dda5c437f0 641 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
mbed_official 133:d4dda5c437f0 642 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
mbed_official 133:d4dda5c437f0 643 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
mbed_official 133:d4dda5c437f0 644 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
mbed_official 133:d4dda5c437f0 645 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
mbed_official 133:d4dda5c437f0 646
mbed_official 133:d4dda5c437f0 647 } RCC_TypeDef;
mbed_official 133:d4dda5c437f0 648
mbed_official 133:d4dda5c437f0 649 /**
mbed_official 133:d4dda5c437f0 650 * @brief Real-Time Clock
mbed_official 133:d4dda5c437f0 651 */
mbed_official 133:d4dda5c437f0 652
mbed_official 133:d4dda5c437f0 653 typedef struct
mbed_official 133:d4dda5c437f0 654 {
mbed_official 133:d4dda5c437f0 655 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 656 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 657 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 658 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 659 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 133:d4dda5c437f0 660 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 133:d4dda5c437f0 661 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
mbed_official 133:d4dda5c437f0 662 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 133:d4dda5c437f0 663 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 133:d4dda5c437f0 664 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 133:d4dda5c437f0 665 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 133:d4dda5c437f0 666 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 133:d4dda5c437f0 667 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 133:d4dda5c437f0 668 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 133:d4dda5c437f0 669 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 133:d4dda5c437f0 670 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 133:d4dda5c437f0 671 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 133:d4dda5c437f0 672 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 133:d4dda5c437f0 673 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 133:d4dda5c437f0 674 uint32_t RESERVED7; /*!< Reserved, 0x4C */
mbed_official 133:d4dda5c437f0 675 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
mbed_official 133:d4dda5c437f0 676 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 133:d4dda5c437f0 677 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 133:d4dda5c437f0 678 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 133:d4dda5c437f0 679 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 133:d4dda5c437f0 680 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 133:d4dda5c437f0 681 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 133:d4dda5c437f0 682 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 133:d4dda5c437f0 683 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 133:d4dda5c437f0 684 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 133:d4dda5c437f0 685 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 133:d4dda5c437f0 686 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 133:d4dda5c437f0 687 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 133:d4dda5c437f0 688 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 133:d4dda5c437f0 689 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 133:d4dda5c437f0 690 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 133:d4dda5c437f0 691 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
mbed_official 133:d4dda5c437f0 692 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
mbed_official 133:d4dda5c437f0 693 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
mbed_official 133:d4dda5c437f0 694 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
mbed_official 133:d4dda5c437f0 695 } RTC_TypeDef;
mbed_official 133:d4dda5c437f0 696
mbed_official 133:d4dda5c437f0 697
mbed_official 133:d4dda5c437f0 698 /**
mbed_official 133:d4dda5c437f0 699 * @brief SD host Interface
mbed_official 133:d4dda5c437f0 700 */
mbed_official 133:d4dda5c437f0 701
mbed_official 133:d4dda5c437f0 702 typedef struct
mbed_official 133:d4dda5c437f0 703 {
mbed_official 133:d4dda5c437f0 704 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 705 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 706 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 707 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 708 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
mbed_official 133:d4dda5c437f0 709 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
mbed_official 133:d4dda5c437f0 710 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
mbed_official 133:d4dda5c437f0 711 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
mbed_official 133:d4dda5c437f0 712 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
mbed_official 133:d4dda5c437f0 713 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
mbed_official 133:d4dda5c437f0 714 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
mbed_official 133:d4dda5c437f0 715 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
mbed_official 133:d4dda5c437f0 716 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
mbed_official 133:d4dda5c437f0 717 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
mbed_official 133:d4dda5c437f0 718 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
mbed_official 133:d4dda5c437f0 719 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
mbed_official 133:d4dda5c437f0 720 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
mbed_official 133:d4dda5c437f0 721 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
mbed_official 133:d4dda5c437f0 722 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
mbed_official 133:d4dda5c437f0 723 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
mbed_official 133:d4dda5c437f0 724 } SDIO_TypeDef;
mbed_official 133:d4dda5c437f0 725
mbed_official 133:d4dda5c437f0 726 /**
mbed_official 133:d4dda5c437f0 727 * @brief Serial Peripheral Interface
mbed_official 133:d4dda5c437f0 728 */
mbed_official 133:d4dda5c437f0 729
mbed_official 133:d4dda5c437f0 730 typedef struct
mbed_official 133:d4dda5c437f0 731 {
mbed_official 133:d4dda5c437f0 732 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 733 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 734 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 735 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 736 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 133:d4dda5c437f0 737 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 133:d4dda5c437f0 738 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 133:d4dda5c437f0 739 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 133:d4dda5c437f0 740 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 133:d4dda5c437f0 741 } SPI_TypeDef;
mbed_official 133:d4dda5c437f0 742
mbed_official 133:d4dda5c437f0 743 /**
mbed_official 133:d4dda5c437f0 744 * @brief TIM
mbed_official 133:d4dda5c437f0 745 */
mbed_official 133:d4dda5c437f0 746
mbed_official 133:d4dda5c437f0 747 typedef struct
mbed_official 133:d4dda5c437f0 748 {
mbed_official 133:d4dda5c437f0 749 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 750 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 751 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 752 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 753 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 133:d4dda5c437f0 754 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 133:d4dda5c437f0 755 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 133:d4dda5c437f0 756 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 133:d4dda5c437f0 757 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 133:d4dda5c437f0 758 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 133:d4dda5c437f0 759 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
mbed_official 133:d4dda5c437f0 760 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 133:d4dda5c437f0 761 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 133:d4dda5c437f0 762 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 133:d4dda5c437f0 763 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 133:d4dda5c437f0 764 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 133:d4dda5c437f0 765 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 133:d4dda5c437f0 766 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 133:d4dda5c437f0 767 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 133:d4dda5c437f0 768 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 133:d4dda5c437f0 769 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 133:d4dda5c437f0 770 } TIM_TypeDef;
mbed_official 133:d4dda5c437f0 771
mbed_official 133:d4dda5c437f0 772 /**
mbed_official 133:d4dda5c437f0 773 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 133:d4dda5c437f0 774 */
mbed_official 133:d4dda5c437f0 775
mbed_official 133:d4dda5c437f0 776 typedef struct
mbed_official 133:d4dda5c437f0 777 {
mbed_official 133:d4dda5c437f0 778 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 779 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 780 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 781 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
mbed_official 133:d4dda5c437f0 782 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
mbed_official 133:d4dda5c437f0 783 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
mbed_official 133:d4dda5c437f0 784 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
mbed_official 133:d4dda5c437f0 785 } USART_TypeDef;
mbed_official 133:d4dda5c437f0 786
mbed_official 133:d4dda5c437f0 787 /**
mbed_official 133:d4dda5c437f0 788 * @brief Window WATCHDOG
mbed_official 133:d4dda5c437f0 789 */
mbed_official 133:d4dda5c437f0 790
mbed_official 133:d4dda5c437f0 791 typedef struct
mbed_official 133:d4dda5c437f0 792 {
mbed_official 133:d4dda5c437f0 793 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 794 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 795 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 796 } WWDG_TypeDef;
mbed_official 133:d4dda5c437f0 797
mbed_official 133:d4dda5c437f0 798 /**
mbed_official 133:d4dda5c437f0 799 * @brief RNG
mbed_official 133:d4dda5c437f0 800 */
mbed_official 133:d4dda5c437f0 801
mbed_official 133:d4dda5c437f0 802 typedef struct
mbed_official 133:d4dda5c437f0 803 {
mbed_official 133:d4dda5c437f0 804 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
mbed_official 133:d4dda5c437f0 805 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
mbed_official 133:d4dda5c437f0 806 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
mbed_official 133:d4dda5c437f0 807 } RNG_TypeDef;
mbed_official 133:d4dda5c437f0 808
mbed_official 133:d4dda5c437f0 809
mbed_official 133:d4dda5c437f0 810
mbed_official 133:d4dda5c437f0 811 /**
mbed_official 133:d4dda5c437f0 812 * @brief __USB_OTG_Core_register
mbed_official 133:d4dda5c437f0 813 */
mbed_official 133:d4dda5c437f0 814 typedef struct
mbed_official 133:d4dda5c437f0 815 {
mbed_official 133:d4dda5c437f0 816 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
mbed_official 133:d4dda5c437f0 817 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
mbed_official 133:d4dda5c437f0 818 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
mbed_official 133:d4dda5c437f0 819 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
mbed_official 133:d4dda5c437f0 820 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
mbed_official 133:d4dda5c437f0 821 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
mbed_official 133:d4dda5c437f0 822 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
mbed_official 133:d4dda5c437f0 823 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
mbed_official 133:d4dda5c437f0 824 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
mbed_official 133:d4dda5c437f0 825 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
mbed_official 133:d4dda5c437f0 826 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
mbed_official 133:d4dda5c437f0 827 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
mbed_official 133:d4dda5c437f0 828 uint32_t Reserved30[2]; /* Reserved 030h*/
mbed_official 133:d4dda5c437f0 829 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
mbed_official 133:d4dda5c437f0 830 __IO uint32_t CID; /* User ID Register 03Ch*/
mbed_official 133:d4dda5c437f0 831 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
mbed_official 133:d4dda5c437f0 832 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
mbed_official 133:d4dda5c437f0 833 __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
mbed_official 133:d4dda5c437f0 834 }
mbed_official 133:d4dda5c437f0 835 USB_OTG_GlobalTypeDef;
mbed_official 133:d4dda5c437f0 836
mbed_official 133:d4dda5c437f0 837
mbed_official 133:d4dda5c437f0 838
mbed_official 133:d4dda5c437f0 839 /**
mbed_official 133:d4dda5c437f0 840 * @brief __device_Registers
mbed_official 133:d4dda5c437f0 841 */
mbed_official 133:d4dda5c437f0 842 typedef struct
mbed_official 133:d4dda5c437f0 843 {
mbed_official 133:d4dda5c437f0 844 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
mbed_official 133:d4dda5c437f0 845 __IO uint32_t DCTL; /* dev Control Register 804h*/
mbed_official 133:d4dda5c437f0 846 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
mbed_official 133:d4dda5c437f0 847 uint32_t Reserved0C; /* Reserved 80Ch*/
mbed_official 133:d4dda5c437f0 848 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
mbed_official 133:d4dda5c437f0 849 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
mbed_official 133:d4dda5c437f0 850 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
mbed_official 133:d4dda5c437f0 851 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
mbed_official 133:d4dda5c437f0 852 uint32_t Reserved20; /* Reserved 820h*/
mbed_official 133:d4dda5c437f0 853 uint32_t Reserved9; /* Reserved 824h*/
mbed_official 133:d4dda5c437f0 854 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
mbed_official 133:d4dda5c437f0 855 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
mbed_official 133:d4dda5c437f0 856 __IO uint32_t DTHRCTL; /* dev thr 830h*/
mbed_official 133:d4dda5c437f0 857 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
mbed_official 133:d4dda5c437f0 858 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
mbed_official 133:d4dda5c437f0 859 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
mbed_official 133:d4dda5c437f0 860 uint32_t Reserved40; /* dedicated EP mask 840h*/
mbed_official 133:d4dda5c437f0 861 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
mbed_official 133:d4dda5c437f0 862 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
mbed_official 133:d4dda5c437f0 863 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
mbed_official 133:d4dda5c437f0 864 }
mbed_official 133:d4dda5c437f0 865 USB_OTG_DeviceTypeDef;
mbed_official 133:d4dda5c437f0 866
mbed_official 133:d4dda5c437f0 867
mbed_official 133:d4dda5c437f0 868 /**
mbed_official 133:d4dda5c437f0 869 * @brief __IN_Endpoint-Specific_Register
mbed_official 133:d4dda5c437f0 870 */
mbed_official 133:d4dda5c437f0 871 typedef struct
mbed_official 133:d4dda5c437f0 872 {
mbed_official 133:d4dda5c437f0 873 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
mbed_official 133:d4dda5c437f0 874 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
mbed_official 133:d4dda5c437f0 875 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
mbed_official 133:d4dda5c437f0 876 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
mbed_official 133:d4dda5c437f0 877 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
mbed_official 133:d4dda5c437f0 878 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
mbed_official 133:d4dda5c437f0 879 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
mbed_official 133:d4dda5c437f0 880 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
mbed_official 133:d4dda5c437f0 881 }
mbed_official 133:d4dda5c437f0 882 USB_OTG_INEndpointTypeDef;
mbed_official 133:d4dda5c437f0 883
mbed_official 133:d4dda5c437f0 884
mbed_official 133:d4dda5c437f0 885 /**
mbed_official 133:d4dda5c437f0 886 * @brief __OUT_Endpoint-Specific_Registers
mbed_official 133:d4dda5c437f0 887 */
mbed_official 133:d4dda5c437f0 888 typedef struct
mbed_official 133:d4dda5c437f0 889 {
mbed_official 133:d4dda5c437f0 890 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
mbed_official 133:d4dda5c437f0 891 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
mbed_official 133:d4dda5c437f0 892 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
mbed_official 133:d4dda5c437f0 893 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
mbed_official 133:d4dda5c437f0 894 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
mbed_official 133:d4dda5c437f0 895 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
mbed_official 133:d4dda5c437f0 896 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
mbed_official 133:d4dda5c437f0 897 }
mbed_official 133:d4dda5c437f0 898 USB_OTG_OUTEndpointTypeDef;
mbed_official 133:d4dda5c437f0 899
mbed_official 133:d4dda5c437f0 900
mbed_official 133:d4dda5c437f0 901 /**
mbed_official 133:d4dda5c437f0 902 * @brief __Host_Mode_Register_Structures
mbed_official 133:d4dda5c437f0 903 */
mbed_official 133:d4dda5c437f0 904 typedef struct
mbed_official 133:d4dda5c437f0 905 {
mbed_official 133:d4dda5c437f0 906 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
mbed_official 133:d4dda5c437f0 907 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
mbed_official 133:d4dda5c437f0 908 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
mbed_official 133:d4dda5c437f0 909 uint32_t Reserved40C; /* Reserved 40Ch*/
mbed_official 133:d4dda5c437f0 910 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
mbed_official 133:d4dda5c437f0 911 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
mbed_official 133:d4dda5c437f0 912 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
mbed_official 133:d4dda5c437f0 913 }
mbed_official 133:d4dda5c437f0 914 USB_OTG_HostTypeDef;
mbed_official 133:d4dda5c437f0 915
mbed_official 133:d4dda5c437f0 916
mbed_official 133:d4dda5c437f0 917 /**
mbed_official 133:d4dda5c437f0 918 * @brief __Host_Channel_Specific_Registers
mbed_official 133:d4dda5c437f0 919 */
mbed_official 133:d4dda5c437f0 920 typedef struct
mbed_official 133:d4dda5c437f0 921 {
mbed_official 133:d4dda5c437f0 922 __IO uint32_t HCCHAR;
mbed_official 133:d4dda5c437f0 923 __IO uint32_t HCSPLT;
mbed_official 133:d4dda5c437f0 924 __IO uint32_t HCINT;
mbed_official 133:d4dda5c437f0 925 __IO uint32_t HCINTMSK;
mbed_official 133:d4dda5c437f0 926 __IO uint32_t HCTSIZ;
mbed_official 133:d4dda5c437f0 927 __IO uint32_t HCDMA;
mbed_official 133:d4dda5c437f0 928 uint32_t Reserved[2];
mbed_official 133:d4dda5c437f0 929 }
mbed_official 133:d4dda5c437f0 930 USB_OTG_HostChannelTypeDef;
mbed_official 133:d4dda5c437f0 931
mbed_official 133:d4dda5c437f0 932
mbed_official 133:d4dda5c437f0 933 /**
mbed_official 133:d4dda5c437f0 934 * @brief Peripheral_memory_map
mbed_official 133:d4dda5c437f0 935 */
mbed_official 133:d4dda5c437f0 936 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
mbed_official 133:d4dda5c437f0 937 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
mbed_official 133:d4dda5c437f0 938 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
mbed_official 133:d4dda5c437f0 939 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
mbed_official 133:d4dda5c437f0 940 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 133:d4dda5c437f0 941 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
mbed_official 133:d4dda5c437f0 942 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
mbed_official 133:d4dda5c437f0 943 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
mbed_official 613:bc40b8d2aec4 944 #define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
mbed_official 133:d4dda5c437f0 945 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
mbed_official 613:bc40b8d2aec4 946 #define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
mbed_official 242:7074e42da0b2 947 #define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
mbed_official 242:7074e42da0b2 948 #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
mbed_official 133:d4dda5c437f0 949
mbed_official 133:d4dda5c437f0 950 /* Legacy defines */
mbed_official 133:d4dda5c437f0 951 #define SRAM_BASE SRAM1_BASE
mbed_official 133:d4dda5c437f0 952 #define SRAM_BB_BASE SRAM1_BB_BASE
mbed_official 133:d4dda5c437f0 953
mbed_official 133:d4dda5c437f0 954
mbed_official 133:d4dda5c437f0 955 /*!< Peripheral memory map */
mbed_official 133:d4dda5c437f0 956 #define APB1PERIPH_BASE PERIPH_BASE
mbed_official 133:d4dda5c437f0 957 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
mbed_official 133:d4dda5c437f0 958 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 133:d4dda5c437f0 959 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
mbed_official 133:d4dda5c437f0 960
mbed_official 133:d4dda5c437f0 961 /*!< APB1 peripherals */
mbed_official 133:d4dda5c437f0 962 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
mbed_official 133:d4dda5c437f0 963 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
mbed_official 133:d4dda5c437f0 964 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
mbed_official 133:d4dda5c437f0 965 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
mbed_official 133:d4dda5c437f0 966 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
mbed_official 133:d4dda5c437f0 967 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
mbed_official 133:d4dda5c437f0 968 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
mbed_official 133:d4dda5c437f0 969 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
mbed_official 133:d4dda5c437f0 970 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
mbed_official 133:d4dda5c437f0 971 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
mbed_official 133:d4dda5c437f0 972 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
mbed_official 133:d4dda5c437f0 973 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
mbed_official 133:d4dda5c437f0 974 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
mbed_official 133:d4dda5c437f0 975 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
mbed_official 133:d4dda5c437f0 976 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
mbed_official 133:d4dda5c437f0 977 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
mbed_official 133:d4dda5c437f0 978 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
mbed_official 133:d4dda5c437f0 979 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
mbed_official 133:d4dda5c437f0 980 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
mbed_official 133:d4dda5c437f0 981 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
mbed_official 133:d4dda5c437f0 982 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
mbed_official 133:d4dda5c437f0 983 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
mbed_official 133:d4dda5c437f0 984 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
mbed_official 133:d4dda5c437f0 985 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
mbed_official 133:d4dda5c437f0 986 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
mbed_official 133:d4dda5c437f0 987 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
mbed_official 133:d4dda5c437f0 988 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
mbed_official 133:d4dda5c437f0 989
mbed_official 133:d4dda5c437f0 990 /*!< APB2 peripherals */
mbed_official 133:d4dda5c437f0 991 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
mbed_official 133:d4dda5c437f0 992 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
mbed_official 133:d4dda5c437f0 993 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
mbed_official 133:d4dda5c437f0 994 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
mbed_official 133:d4dda5c437f0 995 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
mbed_official 133:d4dda5c437f0 996 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
mbed_official 133:d4dda5c437f0 997 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
mbed_official 133:d4dda5c437f0 998 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
mbed_official 133:d4dda5c437f0 999 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
mbed_official 133:d4dda5c437f0 1000 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
mbed_official 133:d4dda5c437f0 1001 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
mbed_official 133:d4dda5c437f0 1002 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
mbed_official 133:d4dda5c437f0 1003 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
mbed_official 133:d4dda5c437f0 1004 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
mbed_official 133:d4dda5c437f0 1005 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
mbed_official 133:d4dda5c437f0 1006
mbed_official 133:d4dda5c437f0 1007 /*!< AHB1 peripherals */
mbed_official 133:d4dda5c437f0 1008 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
mbed_official 133:d4dda5c437f0 1009 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
mbed_official 133:d4dda5c437f0 1010 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
mbed_official 133:d4dda5c437f0 1011 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
mbed_official 133:d4dda5c437f0 1012 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
mbed_official 133:d4dda5c437f0 1013 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
mbed_official 133:d4dda5c437f0 1014 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
mbed_official 133:d4dda5c437f0 1015 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
mbed_official 133:d4dda5c437f0 1016 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
mbed_official 133:d4dda5c437f0 1017 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
mbed_official 133:d4dda5c437f0 1018 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
mbed_official 133:d4dda5c437f0 1019 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
mbed_official 133:d4dda5c437f0 1020 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
mbed_official 133:d4dda5c437f0 1021 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
mbed_official 133:d4dda5c437f0 1022 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
mbed_official 133:d4dda5c437f0 1023 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
mbed_official 133:d4dda5c437f0 1024 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
mbed_official 133:d4dda5c437f0 1025 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
mbed_official 133:d4dda5c437f0 1026 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
mbed_official 133:d4dda5c437f0 1027 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
mbed_official 133:d4dda5c437f0 1028 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
mbed_official 133:d4dda5c437f0 1029 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
mbed_official 133:d4dda5c437f0 1030 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
mbed_official 133:d4dda5c437f0 1031 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
mbed_official 133:d4dda5c437f0 1032 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
mbed_official 133:d4dda5c437f0 1033 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
mbed_official 133:d4dda5c437f0 1034 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
mbed_official 133:d4dda5c437f0 1035 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
mbed_official 133:d4dda5c437f0 1036 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
mbed_official 133:d4dda5c437f0 1037 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
mbed_official 133:d4dda5c437f0 1038 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
mbed_official 133:d4dda5c437f0 1039 #define ETH_MAC_BASE (ETH_BASE)
mbed_official 133:d4dda5c437f0 1040 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
mbed_official 133:d4dda5c437f0 1041 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
mbed_official 133:d4dda5c437f0 1042 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
mbed_official 133:d4dda5c437f0 1043
mbed_official 133:d4dda5c437f0 1044 /*!< AHB2 peripherals */
mbed_official 133:d4dda5c437f0 1045 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
mbed_official 133:d4dda5c437f0 1046 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
mbed_official 133:d4dda5c437f0 1047
mbed_official 133:d4dda5c437f0 1048 /*!< FSMC Bankx registers base address */
mbed_official 133:d4dda5c437f0 1049 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
mbed_official 133:d4dda5c437f0 1050 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
mbed_official 133:d4dda5c437f0 1051 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060)
mbed_official 133:d4dda5c437f0 1052 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
mbed_official 133:d4dda5c437f0 1053
mbed_official 133:d4dda5c437f0 1054 /* Debug MCU registers base address */
mbed_official 133:d4dda5c437f0 1055 #define DBGMCU_BASE ((uint32_t )0xE0042000)
mbed_official 133:d4dda5c437f0 1056
mbed_official 133:d4dda5c437f0 1057 /*!< USB registers base address */
mbed_official 133:d4dda5c437f0 1058 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
mbed_official 133:d4dda5c437f0 1059 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
mbed_official 133:d4dda5c437f0 1060
mbed_official 133:d4dda5c437f0 1061 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
mbed_official 133:d4dda5c437f0 1062 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
mbed_official 133:d4dda5c437f0 1063 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
mbed_official 133:d4dda5c437f0 1064 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
mbed_official 133:d4dda5c437f0 1065 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
mbed_official 133:d4dda5c437f0 1066 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
mbed_official 133:d4dda5c437f0 1067 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
mbed_official 133:d4dda5c437f0 1068 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
mbed_official 133:d4dda5c437f0 1069 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
mbed_official 133:d4dda5c437f0 1070 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
mbed_official 133:d4dda5c437f0 1071 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
mbed_official 133:d4dda5c437f0 1072 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
mbed_official 133:d4dda5c437f0 1073
mbed_official 133:d4dda5c437f0 1074 /**
mbed_official 133:d4dda5c437f0 1075 * @}
mbed_official 133:d4dda5c437f0 1076 */
mbed_official 133:d4dda5c437f0 1077
mbed_official 133:d4dda5c437f0 1078 /** @addtogroup Peripheral_declaration
mbed_official 133:d4dda5c437f0 1079 * @{
mbed_official 133:d4dda5c437f0 1080 */
mbed_official 133:d4dda5c437f0 1081 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 133:d4dda5c437f0 1082 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 133:d4dda5c437f0 1083 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official 133:d4dda5c437f0 1084 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
mbed_official 133:d4dda5c437f0 1085 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 133:d4dda5c437f0 1086 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 133:d4dda5c437f0 1087 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
mbed_official 133:d4dda5c437f0 1088 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
mbed_official 133:d4dda5c437f0 1089 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
mbed_official 133:d4dda5c437f0 1090 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 133:d4dda5c437f0 1091 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 133:d4dda5c437f0 1092 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 133:d4dda5c437f0 1093 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
mbed_official 133:d4dda5c437f0 1094 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 133:d4dda5c437f0 1095 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
mbed_official 133:d4dda5c437f0 1096 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
mbed_official 133:d4dda5c437f0 1097 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 133:d4dda5c437f0 1098 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 133:d4dda5c437f0 1099 #define UART4 ((USART_TypeDef *) UART4_BASE)
mbed_official 133:d4dda5c437f0 1100 #define UART5 ((USART_TypeDef *) UART5_BASE)
mbed_official 133:d4dda5c437f0 1101 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 133:d4dda5c437f0 1102 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 133:d4dda5c437f0 1103 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
mbed_official 133:d4dda5c437f0 1104 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
mbed_official 133:d4dda5c437f0 1105 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
mbed_official 133:d4dda5c437f0 1106 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 133:d4dda5c437f0 1107 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 133:d4dda5c437f0 1108 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 133:d4dda5c437f0 1109 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
mbed_official 133:d4dda5c437f0 1110 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 133:d4dda5c437f0 1111 #define USART6 ((USART_TypeDef *) USART6_BASE)
mbed_official 133:d4dda5c437f0 1112 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 133:d4dda5c437f0 1113 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 133:d4dda5c437f0 1114 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
mbed_official 133:d4dda5c437f0 1115 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
mbed_official 133:d4dda5c437f0 1116 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
mbed_official 133:d4dda5c437f0 1117 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 133:d4dda5c437f0 1118 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 133:d4dda5c437f0 1119 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 133:d4dda5c437f0 1120 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
mbed_official 133:d4dda5c437f0 1121 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
mbed_official 133:d4dda5c437f0 1122 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
mbed_official 133:d4dda5c437f0 1123 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 133:d4dda5c437f0 1124 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 133:d4dda5c437f0 1125 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 133:d4dda5c437f0 1126 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 133:d4dda5c437f0 1127 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 133:d4dda5c437f0 1128 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 133:d4dda5c437f0 1129 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
mbed_official 133:d4dda5c437f0 1130 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official 133:d4dda5c437f0 1131 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
mbed_official 133:d4dda5c437f0 1132 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 133:d4dda5c437f0 1133 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 133:d4dda5c437f0 1134 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 133:d4dda5c437f0 1135 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 133:d4dda5c437f0 1136 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
mbed_official 133:d4dda5c437f0 1137 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
mbed_official 133:d4dda5c437f0 1138 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
mbed_official 133:d4dda5c437f0 1139 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
mbed_official 133:d4dda5c437f0 1140 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
mbed_official 133:d4dda5c437f0 1141 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
mbed_official 133:d4dda5c437f0 1142 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
mbed_official 133:d4dda5c437f0 1143 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
mbed_official 133:d4dda5c437f0 1144 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 133:d4dda5c437f0 1145 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
mbed_official 133:d4dda5c437f0 1146 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
mbed_official 133:d4dda5c437f0 1147 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
mbed_official 133:d4dda5c437f0 1148 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
mbed_official 133:d4dda5c437f0 1149 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
mbed_official 133:d4dda5c437f0 1150 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
mbed_official 133:d4dda5c437f0 1151 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
mbed_official 133:d4dda5c437f0 1152 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
mbed_official 133:d4dda5c437f0 1153 #define ETH ((ETH_TypeDef *) ETH_BASE)
mbed_official 133:d4dda5c437f0 1154 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
mbed_official 133:d4dda5c437f0 1155 #define RNG ((RNG_TypeDef *) RNG_BASE)
mbed_official 133:d4dda5c437f0 1156 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
mbed_official 133:d4dda5c437f0 1157 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
mbed_official 133:d4dda5c437f0 1158 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
mbed_official 133:d4dda5c437f0 1159 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
mbed_official 133:d4dda5c437f0 1160
mbed_official 133:d4dda5c437f0 1161 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 133:d4dda5c437f0 1162
mbed_official 133:d4dda5c437f0 1163 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
mbed_official 133:d4dda5c437f0 1164 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
mbed_official 133:d4dda5c437f0 1165
mbed_official 133:d4dda5c437f0 1166 /**
mbed_official 133:d4dda5c437f0 1167 * @}
mbed_official 133:d4dda5c437f0 1168 */
mbed_official 133:d4dda5c437f0 1169
mbed_official 133:d4dda5c437f0 1170 /** @addtogroup Exported_constants
mbed_official 133:d4dda5c437f0 1171 * @{
mbed_official 133:d4dda5c437f0 1172 */
mbed_official 133:d4dda5c437f0 1173
mbed_official 133:d4dda5c437f0 1174 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 133:d4dda5c437f0 1175 * @{
mbed_official 133:d4dda5c437f0 1176 */
mbed_official 133:d4dda5c437f0 1177
mbed_official 133:d4dda5c437f0 1178 /******************************************************************************/
mbed_official 133:d4dda5c437f0 1179 /* Peripheral Registers_Bits_Definition */
mbed_official 133:d4dda5c437f0 1180 /******************************************************************************/
mbed_official 133:d4dda5c437f0 1181
mbed_official 133:d4dda5c437f0 1182 /******************************************************************************/
mbed_official 133:d4dda5c437f0 1183 /* */
mbed_official 133:d4dda5c437f0 1184 /* Analog to Digital Converter */
mbed_official 133:d4dda5c437f0 1185 /* */
mbed_official 133:d4dda5c437f0 1186 /******************************************************************************/
mbed_official 133:d4dda5c437f0 1187 /******************** Bit definition for ADC_SR register ********************/
mbed_official 133:d4dda5c437f0 1188 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
mbed_official 133:d4dda5c437f0 1189 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
mbed_official 133:d4dda5c437f0 1190 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
mbed_official 133:d4dda5c437f0 1191 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
mbed_official 133:d4dda5c437f0 1192 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
mbed_official 133:d4dda5c437f0 1193 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
mbed_official 133:d4dda5c437f0 1194
mbed_official 133:d4dda5c437f0 1195 /******************* Bit definition for ADC_CR1 register ********************/
mbed_official 133:d4dda5c437f0 1196 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 133:d4dda5c437f0 1197 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1198 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1199 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1200 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1201 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1202 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
mbed_official 133:d4dda5c437f0 1203 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
mbed_official 133:d4dda5c437f0 1204 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
mbed_official 133:d4dda5c437f0 1205 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
mbed_official 133:d4dda5c437f0 1206 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
mbed_official 133:d4dda5c437f0 1207 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
mbed_official 133:d4dda5c437f0 1208 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
mbed_official 133:d4dda5c437f0 1209 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
mbed_official 133:d4dda5c437f0 1210 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
mbed_official 133:d4dda5c437f0 1211 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1212 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1213 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1214 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
mbed_official 133:d4dda5c437f0 1215 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
mbed_official 133:d4dda5c437f0 1216 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
mbed_official 133:d4dda5c437f0 1217 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1218 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1219 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
mbed_official 133:d4dda5c437f0 1220
mbed_official 133:d4dda5c437f0 1221 /******************* Bit definition for ADC_CR2 register ********************/
mbed_official 133:d4dda5c437f0 1222 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
mbed_official 133:d4dda5c437f0 1223 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
mbed_official 133:d4dda5c437f0 1224 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
mbed_official 133:d4dda5c437f0 1225 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
mbed_official 133:d4dda5c437f0 1226 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
mbed_official 133:d4dda5c437f0 1227 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
mbed_official 133:d4dda5c437f0 1228 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
mbed_official 133:d4dda5c437f0 1229 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1230 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1231 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1232 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1233 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
mbed_official 133:d4dda5c437f0 1234 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1235 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1236 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
mbed_official 133:d4dda5c437f0 1237 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
mbed_official 133:d4dda5c437f0 1238 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1239 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1240 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1241 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1242 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
mbed_official 133:d4dda5c437f0 1243 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1244 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1245 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
mbed_official 133:d4dda5c437f0 1246
mbed_official 133:d4dda5c437f0 1247 /****************** Bit definition for ADC_SMPR1 register *******************/
mbed_official 133:d4dda5c437f0 1248 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
mbed_official 133:d4dda5c437f0 1249 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1250 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1251 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1252 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
mbed_official 133:d4dda5c437f0 1253 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1254 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1255 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1256 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
mbed_official 133:d4dda5c437f0 1257 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1258 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1259 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1260 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
mbed_official 133:d4dda5c437f0 1261 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1262 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1263 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1264 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
mbed_official 133:d4dda5c437f0 1265 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1266 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1267 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1268 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
mbed_official 133:d4dda5c437f0 1269 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1270 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1271 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1272 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
mbed_official 133:d4dda5c437f0 1273 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1274 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1275 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1276 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
mbed_official 133:d4dda5c437f0 1277 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1278 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1279 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1280 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
mbed_official 133:d4dda5c437f0 1281 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1282 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1283 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1284
mbed_official 133:d4dda5c437f0 1285 /****************** Bit definition for ADC_SMPR2 register *******************/
mbed_official 133:d4dda5c437f0 1286 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
mbed_official 133:d4dda5c437f0 1287 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1288 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1289 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1290 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
mbed_official 133:d4dda5c437f0 1291 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1292 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1293 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1294 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
mbed_official 133:d4dda5c437f0 1295 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1296 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1297 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1298 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
mbed_official 133:d4dda5c437f0 1299 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1300 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1301 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1302 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
mbed_official 133:d4dda5c437f0 1303 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1304 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1305 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1306 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
mbed_official 133:d4dda5c437f0 1307 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1308 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1309 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1310 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
mbed_official 133:d4dda5c437f0 1311 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1312 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1313 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1314 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
mbed_official 133:d4dda5c437f0 1315 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1316 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1317 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1318 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
mbed_official 133:d4dda5c437f0 1319 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1320 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1321 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1322 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
mbed_official 133:d4dda5c437f0 1323 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1324 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1325 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1326
mbed_official 133:d4dda5c437f0 1327 /****************** Bit definition for ADC_JOFR1 register *******************/
mbed_official 133:d4dda5c437f0 1328 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
mbed_official 133:d4dda5c437f0 1329
mbed_official 133:d4dda5c437f0 1330 /****************** Bit definition for ADC_JOFR2 register *******************/
mbed_official 133:d4dda5c437f0 1331 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
mbed_official 133:d4dda5c437f0 1332
mbed_official 133:d4dda5c437f0 1333 /****************** Bit definition for ADC_JOFR3 register *******************/
mbed_official 133:d4dda5c437f0 1334 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
mbed_official 133:d4dda5c437f0 1335
mbed_official 133:d4dda5c437f0 1336 /****************** Bit definition for ADC_JOFR4 register *******************/
mbed_official 133:d4dda5c437f0 1337 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
mbed_official 133:d4dda5c437f0 1338
mbed_official 133:d4dda5c437f0 1339 /******************* Bit definition for ADC_HTR register ********************/
mbed_official 133:d4dda5c437f0 1340 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
mbed_official 133:d4dda5c437f0 1341
mbed_official 133:d4dda5c437f0 1342 /******************* Bit definition for ADC_LTR register ********************/
mbed_official 133:d4dda5c437f0 1343 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
mbed_official 133:d4dda5c437f0 1344
mbed_official 133:d4dda5c437f0 1345 /******************* Bit definition for ADC_SQR1 register *******************/
mbed_official 133:d4dda5c437f0 1346 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1347 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1348 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1349 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1350 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1351 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1352 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1353 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1354 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1355 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1356 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1357 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1358 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1359 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1360 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1361 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1362 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1363 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1364 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1365 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1366 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1367 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1368 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1369 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1370 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
mbed_official 133:d4dda5c437f0 1371 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1372 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1373 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1374 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1375
mbed_official 133:d4dda5c437f0 1376 /******************* Bit definition for ADC_SQR2 register *******************/
mbed_official 133:d4dda5c437f0 1377 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1378 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1379 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1380 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1381 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1382 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1383 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1384 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1385 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1386 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1387 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1388 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1389 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1390 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1391 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1392 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1393 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1394 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1395 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1396 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1397 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1398 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1399 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1400 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1401 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1402 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1403 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1404 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1405 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1406 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1407 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1408 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1409 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1410 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1411 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1412 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1413
mbed_official 133:d4dda5c437f0 1414 /******************* Bit definition for ADC_SQR3 register *******************/
mbed_official 133:d4dda5c437f0 1415 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1416 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1417 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1418 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1419 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1420 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1421 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1422 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1423 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1424 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1425 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1426 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1427 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1428 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1429 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1430 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1431 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1432 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1433 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1434 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1435 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1436 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1437 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1438 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1439 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1440 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1441 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1442 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1443 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1444 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1445 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
mbed_official 133:d4dda5c437f0 1446 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1447 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1448 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1449 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1450 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1451
mbed_official 133:d4dda5c437f0 1452 /******************* Bit definition for ADC_JSQR register *******************/
mbed_official 133:d4dda5c437f0 1453 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
mbed_official 133:d4dda5c437f0 1454 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1455 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1456 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1457 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1458 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1459 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
mbed_official 133:d4dda5c437f0 1460 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1461 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1462 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1463 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1464 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1465 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
mbed_official 133:d4dda5c437f0 1466 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1467 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1468 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1469 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1470 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1471 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
mbed_official 133:d4dda5c437f0 1472 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1473 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1474 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1475 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1476 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1477 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
mbed_official 133:d4dda5c437f0 1478 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1479 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1480
mbed_official 133:d4dda5c437f0 1481 /******************* Bit definition for ADC_JDR1 register *******************/
mbed_official 133:d4dda5c437f0 1482 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 133:d4dda5c437f0 1483
mbed_official 133:d4dda5c437f0 1484 /******************* Bit definition for ADC_JDR2 register *******************/
mbed_official 133:d4dda5c437f0 1485 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 133:d4dda5c437f0 1486
mbed_official 133:d4dda5c437f0 1487 /******************* Bit definition for ADC_JDR3 register *******************/
mbed_official 133:d4dda5c437f0 1488 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 133:d4dda5c437f0 1489
mbed_official 133:d4dda5c437f0 1490 /******************* Bit definition for ADC_JDR4 register *******************/
mbed_official 133:d4dda5c437f0 1491 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 133:d4dda5c437f0 1492
mbed_official 133:d4dda5c437f0 1493 /******************** Bit definition for ADC_DR register ********************/
mbed_official 133:d4dda5c437f0 1494 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
mbed_official 133:d4dda5c437f0 1495 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
mbed_official 133:d4dda5c437f0 1496
mbed_official 133:d4dda5c437f0 1497 /******************* Bit definition for ADC_CSR register ********************/
mbed_official 133:d4dda5c437f0 1498 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
mbed_official 133:d4dda5c437f0 1499 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
mbed_official 133:d4dda5c437f0 1500 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
mbed_official 133:d4dda5c437f0 1501 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
mbed_official 133:d4dda5c437f0 1502 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
mbed_official 133:d4dda5c437f0 1503 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
mbed_official 133:d4dda5c437f0 1504 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
mbed_official 133:d4dda5c437f0 1505 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
mbed_official 133:d4dda5c437f0 1506 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
mbed_official 133:d4dda5c437f0 1507 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
mbed_official 133:d4dda5c437f0 1508 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
mbed_official 133:d4dda5c437f0 1509 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
mbed_official 133:d4dda5c437f0 1510 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
mbed_official 133:d4dda5c437f0 1511 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
mbed_official 133:d4dda5c437f0 1512 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
mbed_official 133:d4dda5c437f0 1513 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
mbed_official 133:d4dda5c437f0 1514 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
mbed_official 133:d4dda5c437f0 1515 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
mbed_official 133:d4dda5c437f0 1516
mbed_official 133:d4dda5c437f0 1517 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 133:d4dda5c437f0 1518 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
mbed_official 133:d4dda5c437f0 1519 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1520 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1521 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1522 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1523 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 1524 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
mbed_official 133:d4dda5c437f0 1525 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1526 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1527 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1528 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1529 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
mbed_official 133:d4dda5c437f0 1530 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
mbed_official 133:d4dda5c437f0 1531 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1532 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1533 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
mbed_official 133:d4dda5c437f0 1534 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1535 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1536 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
mbed_official 133:d4dda5c437f0 1537 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
mbed_official 133:d4dda5c437f0 1538
mbed_official 133:d4dda5c437f0 1539 /******************* Bit definition for ADC_CDR register ********************/
mbed_official 133:d4dda5c437f0 1540 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
mbed_official 133:d4dda5c437f0 1541 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
mbed_official 133:d4dda5c437f0 1542
mbed_official 133:d4dda5c437f0 1543 /******************************************************************************/
mbed_official 133:d4dda5c437f0 1544 /* */
mbed_official 133:d4dda5c437f0 1545 /* Controller Area Network */
mbed_official 133:d4dda5c437f0 1546 /* */
mbed_official 133:d4dda5c437f0 1547 /******************************************************************************/
mbed_official 133:d4dda5c437f0 1548 /*!<CAN control and status registers */
mbed_official 133:d4dda5c437f0 1549 /******************* Bit definition for CAN_MCR register ********************/
mbed_official 133:d4dda5c437f0 1550 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
mbed_official 133:d4dda5c437f0 1551 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
mbed_official 133:d4dda5c437f0 1552 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
mbed_official 133:d4dda5c437f0 1553 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
mbed_official 133:d4dda5c437f0 1554 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
mbed_official 133:d4dda5c437f0 1555 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
mbed_official 133:d4dda5c437f0 1556 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
mbed_official 133:d4dda5c437f0 1557 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
mbed_official 133:d4dda5c437f0 1558 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
mbed_official 133:d4dda5c437f0 1559 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
mbed_official 133:d4dda5c437f0 1560 /******************* Bit definition for CAN_MSR register ********************/
mbed_official 133:d4dda5c437f0 1561 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
mbed_official 133:d4dda5c437f0 1562 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
mbed_official 133:d4dda5c437f0 1563 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
mbed_official 133:d4dda5c437f0 1564 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
mbed_official 133:d4dda5c437f0 1565 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
mbed_official 133:d4dda5c437f0 1566 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
mbed_official 133:d4dda5c437f0 1567 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
mbed_official 133:d4dda5c437f0 1568 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
mbed_official 133:d4dda5c437f0 1569 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
mbed_official 133:d4dda5c437f0 1570
mbed_official 133:d4dda5c437f0 1571 /******************* Bit definition for CAN_TSR register ********************/
mbed_official 133:d4dda5c437f0 1572 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
mbed_official 133:d4dda5c437f0 1573 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
mbed_official 133:d4dda5c437f0 1574 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
mbed_official 133:d4dda5c437f0 1575 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
mbed_official 133:d4dda5c437f0 1576 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
mbed_official 133:d4dda5c437f0 1577 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
mbed_official 133:d4dda5c437f0 1578 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
mbed_official 133:d4dda5c437f0 1579 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
mbed_official 133:d4dda5c437f0 1580 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
mbed_official 133:d4dda5c437f0 1581 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
mbed_official 133:d4dda5c437f0 1582 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
mbed_official 133:d4dda5c437f0 1583 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
mbed_official 133:d4dda5c437f0 1584 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
mbed_official 133:d4dda5c437f0 1585 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
mbed_official 133:d4dda5c437f0 1586 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
mbed_official 133:d4dda5c437f0 1587 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
mbed_official 133:d4dda5c437f0 1588
mbed_official 133:d4dda5c437f0 1589 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
mbed_official 133:d4dda5c437f0 1590 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
mbed_official 133:d4dda5c437f0 1591 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
mbed_official 133:d4dda5c437f0 1592 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
mbed_official 133:d4dda5c437f0 1593
mbed_official 133:d4dda5c437f0 1594 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
mbed_official 133:d4dda5c437f0 1595 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
mbed_official 133:d4dda5c437f0 1596 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
mbed_official 133:d4dda5c437f0 1597 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
mbed_official 133:d4dda5c437f0 1598
mbed_official 133:d4dda5c437f0 1599 /******************* Bit definition for CAN_RF0R register *******************/
mbed_official 133:d4dda5c437f0 1600 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
mbed_official 133:d4dda5c437f0 1601 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
mbed_official 133:d4dda5c437f0 1602 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
mbed_official 133:d4dda5c437f0 1603 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
mbed_official 133:d4dda5c437f0 1604
mbed_official 133:d4dda5c437f0 1605 /******************* Bit definition for CAN_RF1R register *******************/
mbed_official 133:d4dda5c437f0 1606 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
mbed_official 133:d4dda5c437f0 1607 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
mbed_official 133:d4dda5c437f0 1608 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
mbed_official 133:d4dda5c437f0 1609 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
mbed_official 133:d4dda5c437f0 1610
mbed_official 133:d4dda5c437f0 1611 /******************** Bit definition for CAN_IER register *******************/
mbed_official 133:d4dda5c437f0 1612 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
mbed_official 133:d4dda5c437f0 1613 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 133:d4dda5c437f0 1614 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
mbed_official 133:d4dda5c437f0 1615 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
mbed_official 133:d4dda5c437f0 1616 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 133:d4dda5c437f0 1617 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
mbed_official 133:d4dda5c437f0 1618 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
mbed_official 133:d4dda5c437f0 1619 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
mbed_official 133:d4dda5c437f0 1620 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
mbed_official 133:d4dda5c437f0 1621 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
mbed_official 133:d4dda5c437f0 1622 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
mbed_official 133:d4dda5c437f0 1623 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
mbed_official 133:d4dda5c437f0 1624 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
mbed_official 133:d4dda5c437f0 1625 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
mbed_official 133:d4dda5c437f0 1626 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
mbed_official 133:d4dda5c437f0 1627 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
mbed_official 133:d4dda5c437f0 1628 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
mbed_official 133:d4dda5c437f0 1629 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
mbed_official 133:d4dda5c437f0 1630 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
mbed_official 133:d4dda5c437f0 1631
mbed_official 133:d4dda5c437f0 1632
mbed_official 133:d4dda5c437f0 1633 /******************** Bit definition for CAN_ESR register *******************/
mbed_official 133:d4dda5c437f0 1634 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
mbed_official 133:d4dda5c437f0 1635 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
mbed_official 133:d4dda5c437f0 1636 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
mbed_official 133:d4dda5c437f0 1637
mbed_official 133:d4dda5c437f0 1638 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
mbed_official 133:d4dda5c437f0 1639 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1640 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1641 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1642
mbed_official 133:d4dda5c437f0 1643 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
mbed_official 133:d4dda5c437f0 1644 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
mbed_official 133:d4dda5c437f0 1645
mbed_official 133:d4dda5c437f0 1646 /******************* Bit definition for CAN_BTR register ********************/
mbed_official 133:d4dda5c437f0 1647 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
mbed_official 133:d4dda5c437f0 1648 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
mbed_official 133:d4dda5c437f0 1649 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1650 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1651 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1652 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 1653 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
mbed_official 133:d4dda5c437f0 1654 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1655 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1656 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 1657 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
mbed_official 133:d4dda5c437f0 1658 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 1659 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 1660 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
mbed_official 133:d4dda5c437f0 1661 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
mbed_official 133:d4dda5c437f0 1662
mbed_official 133:d4dda5c437f0 1663
mbed_official 133:d4dda5c437f0 1664 /*!<Mailbox registers */
mbed_official 133:d4dda5c437f0 1665 /****************** Bit definition for CAN_TI0R register ********************/
mbed_official 133:d4dda5c437f0 1666 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 133:d4dda5c437f0 1667 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 133:d4dda5c437f0 1668 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 133:d4dda5c437f0 1669 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 133:d4dda5c437f0 1670 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 133:d4dda5c437f0 1671
mbed_official 133:d4dda5c437f0 1672 /****************** Bit definition for CAN_TDT0R register *******************/
mbed_official 133:d4dda5c437f0 1673 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 133:d4dda5c437f0 1674 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 133:d4dda5c437f0 1675 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 133:d4dda5c437f0 1676
mbed_official 133:d4dda5c437f0 1677 /****************** Bit definition for CAN_TDL0R register *******************/
mbed_official 133:d4dda5c437f0 1678 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 133:d4dda5c437f0 1679 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 133:d4dda5c437f0 1680 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 133:d4dda5c437f0 1681 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 133:d4dda5c437f0 1682
mbed_official 133:d4dda5c437f0 1683 /****************** Bit definition for CAN_TDH0R register *******************/
mbed_official 133:d4dda5c437f0 1684 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 133:d4dda5c437f0 1685 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 133:d4dda5c437f0 1686 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 133:d4dda5c437f0 1687 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 133:d4dda5c437f0 1688
mbed_official 133:d4dda5c437f0 1689 /******************* Bit definition for CAN_TI1R register *******************/
mbed_official 133:d4dda5c437f0 1690 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 133:d4dda5c437f0 1691 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 133:d4dda5c437f0 1692 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 133:d4dda5c437f0 1693 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 133:d4dda5c437f0 1694 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 133:d4dda5c437f0 1695
mbed_official 133:d4dda5c437f0 1696 /******************* Bit definition for CAN_TDT1R register ******************/
mbed_official 133:d4dda5c437f0 1697 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 133:d4dda5c437f0 1698 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 133:d4dda5c437f0 1699 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 133:d4dda5c437f0 1700
mbed_official 133:d4dda5c437f0 1701 /******************* Bit definition for CAN_TDL1R register ******************/
mbed_official 133:d4dda5c437f0 1702 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 133:d4dda5c437f0 1703 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 133:d4dda5c437f0 1704 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 133:d4dda5c437f0 1705 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 133:d4dda5c437f0 1706
mbed_official 133:d4dda5c437f0 1707 /******************* Bit definition for CAN_TDH1R register ******************/
mbed_official 133:d4dda5c437f0 1708 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 133:d4dda5c437f0 1709 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 133:d4dda5c437f0 1710 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 133:d4dda5c437f0 1711 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 133:d4dda5c437f0 1712
mbed_official 133:d4dda5c437f0 1713 /******************* Bit definition for CAN_TI2R register *******************/
mbed_official 133:d4dda5c437f0 1714 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 133:d4dda5c437f0 1715 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 133:d4dda5c437f0 1716 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 133:d4dda5c437f0 1717 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 133:d4dda5c437f0 1718 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 133:d4dda5c437f0 1719
mbed_official 133:d4dda5c437f0 1720 /******************* Bit definition for CAN_TDT2R register ******************/
mbed_official 133:d4dda5c437f0 1721 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 133:d4dda5c437f0 1722 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 133:d4dda5c437f0 1723 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 133:d4dda5c437f0 1724
mbed_official 133:d4dda5c437f0 1725 /******************* Bit definition for CAN_TDL2R register ******************/
mbed_official 133:d4dda5c437f0 1726 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 133:d4dda5c437f0 1727 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 133:d4dda5c437f0 1728 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 133:d4dda5c437f0 1729 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 133:d4dda5c437f0 1730
mbed_official 133:d4dda5c437f0 1731 /******************* Bit definition for CAN_TDH2R register ******************/
mbed_official 133:d4dda5c437f0 1732 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 133:d4dda5c437f0 1733 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 133:d4dda5c437f0 1734 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 133:d4dda5c437f0 1735 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 133:d4dda5c437f0 1736
mbed_official 133:d4dda5c437f0 1737 /******************* Bit definition for CAN_RI0R register *******************/
mbed_official 133:d4dda5c437f0 1738 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 133:d4dda5c437f0 1739 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 133:d4dda5c437f0 1740 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 133:d4dda5c437f0 1741 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 133:d4dda5c437f0 1742
mbed_official 133:d4dda5c437f0 1743 /******************* Bit definition for CAN_RDT0R register ******************/
mbed_official 133:d4dda5c437f0 1744 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 133:d4dda5c437f0 1745 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 133:d4dda5c437f0 1746 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 133:d4dda5c437f0 1747
mbed_official 133:d4dda5c437f0 1748 /******************* Bit definition for CAN_RDL0R register ******************/
mbed_official 133:d4dda5c437f0 1749 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 133:d4dda5c437f0 1750 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 133:d4dda5c437f0 1751 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 133:d4dda5c437f0 1752 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 133:d4dda5c437f0 1753
mbed_official 133:d4dda5c437f0 1754 /******************* Bit definition for CAN_RDH0R register ******************/
mbed_official 133:d4dda5c437f0 1755 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 133:d4dda5c437f0 1756 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 133:d4dda5c437f0 1757 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 133:d4dda5c437f0 1758 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 133:d4dda5c437f0 1759
mbed_official 133:d4dda5c437f0 1760 /******************* Bit definition for CAN_RI1R register *******************/
mbed_official 133:d4dda5c437f0 1761 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 133:d4dda5c437f0 1762 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 133:d4dda5c437f0 1763 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 133:d4dda5c437f0 1764 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 133:d4dda5c437f0 1765
mbed_official 133:d4dda5c437f0 1766 /******************* Bit definition for CAN_RDT1R register ******************/
mbed_official 133:d4dda5c437f0 1767 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 133:d4dda5c437f0 1768 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 133:d4dda5c437f0 1769 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 133:d4dda5c437f0 1770
mbed_official 133:d4dda5c437f0 1771 /******************* Bit definition for CAN_RDL1R register ******************/
mbed_official 133:d4dda5c437f0 1772 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 133:d4dda5c437f0 1773 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 133:d4dda5c437f0 1774 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 133:d4dda5c437f0 1775 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 133:d4dda5c437f0 1776
mbed_official 133:d4dda5c437f0 1777 /******************* Bit definition for CAN_RDH1R register ******************/
mbed_official 133:d4dda5c437f0 1778 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 133:d4dda5c437f0 1779 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 133:d4dda5c437f0 1780 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 133:d4dda5c437f0 1781 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 133:d4dda5c437f0 1782
mbed_official 133:d4dda5c437f0 1783 /*!<CAN filter registers */
mbed_official 133:d4dda5c437f0 1784 /******************* Bit definition for CAN_FMR register ********************/
mbed_official 133:d4dda5c437f0 1785 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
mbed_official 133:d4dda5c437f0 1786 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
mbed_official 133:d4dda5c437f0 1787
mbed_official 133:d4dda5c437f0 1788 /******************* Bit definition for CAN_FM1R register *******************/
mbed_official 532:fe11edbda85c 1789 #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
mbed_official 532:fe11edbda85c 1790 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
mbed_official 532:fe11edbda85c 1791 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
mbed_official 532:fe11edbda85c 1792 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
mbed_official 532:fe11edbda85c 1793 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
mbed_official 532:fe11edbda85c 1794 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
mbed_official 532:fe11edbda85c 1795 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
mbed_official 532:fe11edbda85c 1796 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
mbed_official 532:fe11edbda85c 1797 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
mbed_official 532:fe11edbda85c 1798 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
mbed_official 532:fe11edbda85c 1799 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
mbed_official 532:fe11edbda85c 1800 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
mbed_official 532:fe11edbda85c 1801 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
mbed_official 532:fe11edbda85c 1802 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
mbed_official 532:fe11edbda85c 1803 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
mbed_official 532:fe11edbda85c 1804 #define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
mbed_official 532:fe11edbda85c 1805 #define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
mbed_official 532:fe11edbda85c 1806 #define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
mbed_official 532:fe11edbda85c 1807 #define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
mbed_official 532:fe11edbda85c 1808 #define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
mbed_official 532:fe11edbda85c 1809 #define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
mbed_official 532:fe11edbda85c 1810 #define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
mbed_official 532:fe11edbda85c 1811 #define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
mbed_official 532:fe11edbda85c 1812 #define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
mbed_official 532:fe11edbda85c 1813 #define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
mbed_official 532:fe11edbda85c 1814 #define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
mbed_official 532:fe11edbda85c 1815 #define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
mbed_official 532:fe11edbda85c 1816 #define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
mbed_official 532:fe11edbda85c 1817 #define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
mbed_official 133:d4dda5c437f0 1818
mbed_official 133:d4dda5c437f0 1819 /******************* Bit definition for CAN_FS1R register *******************/
mbed_official 532:fe11edbda85c 1820 #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
mbed_official 532:fe11edbda85c 1821 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
mbed_official 532:fe11edbda85c 1822 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
mbed_official 532:fe11edbda85c 1823 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
mbed_official 532:fe11edbda85c 1824 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
mbed_official 532:fe11edbda85c 1825 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
mbed_official 532:fe11edbda85c 1826 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
mbed_official 532:fe11edbda85c 1827 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
mbed_official 532:fe11edbda85c 1828 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
mbed_official 532:fe11edbda85c 1829 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
mbed_official 532:fe11edbda85c 1830 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
mbed_official 532:fe11edbda85c 1831 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
mbed_official 532:fe11edbda85c 1832 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
mbed_official 532:fe11edbda85c 1833 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
mbed_official 532:fe11edbda85c 1834 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
mbed_official 532:fe11edbda85c 1835 #define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
mbed_official 532:fe11edbda85c 1836 #define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
mbed_official 532:fe11edbda85c 1837 #define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
mbed_official 532:fe11edbda85c 1838 #define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
mbed_official 532:fe11edbda85c 1839 #define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
mbed_official 532:fe11edbda85c 1840 #define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
mbed_official 532:fe11edbda85c 1841 #define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
mbed_official 532:fe11edbda85c 1842 #define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
mbed_official 532:fe11edbda85c 1843 #define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
mbed_official 532:fe11edbda85c 1844 #define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
mbed_official 532:fe11edbda85c 1845 #define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
mbed_official 532:fe11edbda85c 1846 #define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
mbed_official 532:fe11edbda85c 1847 #define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
mbed_official 532:fe11edbda85c 1848 #define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
mbed_official 133:d4dda5c437f0 1849
mbed_official 133:d4dda5c437f0 1850 /****************** Bit definition for CAN_FFA1R register *******************/
mbed_official 532:fe11edbda85c 1851 #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
mbed_official 532:fe11edbda85c 1852 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
mbed_official 532:fe11edbda85c 1853 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
mbed_official 532:fe11edbda85c 1854 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
mbed_official 532:fe11edbda85c 1855 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
mbed_official 532:fe11edbda85c 1856 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
mbed_official 532:fe11edbda85c 1857 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
mbed_official 532:fe11edbda85c 1858 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
mbed_official 532:fe11edbda85c 1859 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
mbed_official 532:fe11edbda85c 1860 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
mbed_official 532:fe11edbda85c 1861 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
mbed_official 532:fe11edbda85c 1862 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
mbed_official 532:fe11edbda85c 1863 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
mbed_official 532:fe11edbda85c 1864 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
mbed_official 532:fe11edbda85c 1865 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
mbed_official 532:fe11edbda85c 1866 #define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
mbed_official 532:fe11edbda85c 1867 #define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
mbed_official 532:fe11edbda85c 1868 #define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
mbed_official 532:fe11edbda85c 1869 #define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
mbed_official 532:fe11edbda85c 1870 #define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
mbed_official 532:fe11edbda85c 1871 #define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
mbed_official 532:fe11edbda85c 1872 #define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
mbed_official 532:fe11edbda85c 1873 #define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
mbed_official 532:fe11edbda85c 1874 #define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
mbed_official 532:fe11edbda85c 1875 #define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
mbed_official 532:fe11edbda85c 1876 #define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
mbed_official 532:fe11edbda85c 1877 #define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
mbed_official 532:fe11edbda85c 1878 #define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
mbed_official 532:fe11edbda85c 1879 #define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
mbed_official 133:d4dda5c437f0 1880
mbed_official 133:d4dda5c437f0 1881 /******************* Bit definition for CAN_FA1R register *******************/
mbed_official 532:fe11edbda85c 1882 #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
mbed_official 532:fe11edbda85c 1883 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
mbed_official 532:fe11edbda85c 1884 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
mbed_official 532:fe11edbda85c 1885 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
mbed_official 532:fe11edbda85c 1886 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
mbed_official 532:fe11edbda85c 1887 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
mbed_official 532:fe11edbda85c 1888 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
mbed_official 532:fe11edbda85c 1889 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
mbed_official 532:fe11edbda85c 1890 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
mbed_official 532:fe11edbda85c 1891 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
mbed_official 532:fe11edbda85c 1892 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
mbed_official 532:fe11edbda85c 1893 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
mbed_official 532:fe11edbda85c 1894 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
mbed_official 532:fe11edbda85c 1895 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
mbed_official 532:fe11edbda85c 1896 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
mbed_official 532:fe11edbda85c 1897 #define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
mbed_official 532:fe11edbda85c 1898 #define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
mbed_official 532:fe11edbda85c 1899 #define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
mbed_official 532:fe11edbda85c 1900 #define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
mbed_official 532:fe11edbda85c 1901 #define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
mbed_official 532:fe11edbda85c 1902 #define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
mbed_official 532:fe11edbda85c 1903 #define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
mbed_official 532:fe11edbda85c 1904 #define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
mbed_official 532:fe11edbda85c 1905 #define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
mbed_official 532:fe11edbda85c 1906 #define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
mbed_official 532:fe11edbda85c 1907 #define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
mbed_official 532:fe11edbda85c 1908 #define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
mbed_official 532:fe11edbda85c 1909 #define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
mbed_official 532:fe11edbda85c 1910 #define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
mbed_official 133:d4dda5c437f0 1911
mbed_official 133:d4dda5c437f0 1912 /******************* Bit definition for CAN_F0R1 register *******************/
mbed_official 133:d4dda5c437f0 1913 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 1914 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 1915 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 1916 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 1917 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 1918 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 1919 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 1920 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 1921 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 1922 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 1923 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 1924 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 1925 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 1926 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 1927 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 1928 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 1929 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 1930 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 1931 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 1932 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 1933 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 1934 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 1935 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 1936 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 1937 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 1938 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 1939 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 1940 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 1941 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 1942 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 1943 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 1944 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 1945
mbed_official 133:d4dda5c437f0 1946 /******************* Bit definition for CAN_F1R1 register *******************/
mbed_official 133:d4dda5c437f0 1947 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 1948 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 1949 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 1950 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 1951 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 1952 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 1953 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 1954 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 1955 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 1956 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 1957 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 1958 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 1959 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 1960 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 1961 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 1962 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 1963 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 1964 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 1965 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 1966 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 1967 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 1968 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 1969 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 1970 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 1971 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 1972 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 1973 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 1974 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 1975 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 1976 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 1977 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 1978 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 1979
mbed_official 133:d4dda5c437f0 1980 /******************* Bit definition for CAN_F2R1 register *******************/
mbed_official 133:d4dda5c437f0 1981 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 1982 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 1983 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 1984 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 1985 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 1986 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 1987 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 1988 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 1989 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 1990 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 1991 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 1992 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 1993 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 1994 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 1995 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 1996 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 1997 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 1998 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 1999 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2000 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2001 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2002 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2003 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2004 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2005 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2006 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2007 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2008 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2009 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2010 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2011 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2012 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2013
mbed_official 133:d4dda5c437f0 2014 /******************* Bit definition for CAN_F3R1 register *******************/
mbed_official 133:d4dda5c437f0 2015 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2016 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2017 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2018 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2019 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2020 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2021 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2022 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2023 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2024 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2025 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2026 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2027 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2028 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2029 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2030 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2031 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2032 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2033 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2034 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2035 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2036 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2037 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2038 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2039 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2040 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2041 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2042 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2043 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2044 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2045 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2046 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2047
mbed_official 133:d4dda5c437f0 2048 /******************* Bit definition for CAN_F4R1 register *******************/
mbed_official 133:d4dda5c437f0 2049 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2050 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2051 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2052 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2053 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2054 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2055 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2056 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2057 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2058 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2059 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2060 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2061 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2062 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2063 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2064 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2065 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2066 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2067 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2068 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2069 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2070 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2071 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2072 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2073 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2074 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2075 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2076 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2077 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2078 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2079 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2080 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2081
mbed_official 133:d4dda5c437f0 2082 /******************* Bit definition for CAN_F5R1 register *******************/
mbed_official 133:d4dda5c437f0 2083 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2084 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2085 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2086 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2087 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2088 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2089 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2090 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2091 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2092 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2093 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2094 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2095 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2096 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2097 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2098 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2099 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2100 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2101 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2102 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2103 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2104 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2105 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2106 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2107 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2108 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2109 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2110 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2111 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2112 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2113 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2114 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2115
mbed_official 133:d4dda5c437f0 2116 /******************* Bit definition for CAN_F6R1 register *******************/
mbed_official 133:d4dda5c437f0 2117 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2118 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2119 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2120 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2121 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2122 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2123 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2124 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2125 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2126 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2127 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2128 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2129 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2130 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2131 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2132 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2133 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2134 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2135 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2136 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2137 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2138 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2139 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2140 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2141 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2142 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2143 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2144 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2145 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2146 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2147 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2148 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2149
mbed_official 133:d4dda5c437f0 2150 /******************* Bit definition for CAN_F7R1 register *******************/
mbed_official 133:d4dda5c437f0 2151 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2152 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2153 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2154 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2155 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2156 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2157 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2158 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2159 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2160 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2161 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2162 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2163 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2164 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2165 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2166 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2167 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2168 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2169 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2170 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2171 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2172 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2173 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2174 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2175 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2176 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2177 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2178 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2179 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2180 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2181 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2182 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2183
mbed_official 133:d4dda5c437f0 2184 /******************* Bit definition for CAN_F8R1 register *******************/
mbed_official 133:d4dda5c437f0 2185 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2186 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2187 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2188 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2189 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2190 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2191 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2192 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2193 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2194 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2195 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2196 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2197 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2198 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2199 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2200 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2201 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2202 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2203 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2204 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2205 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2206 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2207 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2208 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2209 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2210 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2211 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2212 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2213 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2214 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2215 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2216 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2217
mbed_official 133:d4dda5c437f0 2218 /******************* Bit definition for CAN_F9R1 register *******************/
mbed_official 133:d4dda5c437f0 2219 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2220 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2221 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2222 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2223 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2224 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2225 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2226 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2227 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2228 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2229 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2230 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2231 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2232 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2233 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2234 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2235 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2236 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2237 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2238 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2239 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2240 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2241 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2242 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2243 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2244 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2245 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2246 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2247 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2248 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2249 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2250 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2251
mbed_official 133:d4dda5c437f0 2252 /******************* Bit definition for CAN_F10R1 register ******************/
mbed_official 133:d4dda5c437f0 2253 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2254 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2255 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2256 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2257 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2258 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2259 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2260 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2261 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2262 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2263 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2264 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2265 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2266 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2267 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2268 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2269 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2270 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2271 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2272 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2273 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2274 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2275 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2276 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2277 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2278 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2279 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2280 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2281 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2282 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2283 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2284 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2285
mbed_official 133:d4dda5c437f0 2286 /******************* Bit definition for CAN_F11R1 register ******************/
mbed_official 133:d4dda5c437f0 2287 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2288 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2289 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2290 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2291 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2292 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2293 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2294 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2295 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2296 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2297 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2298 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2299 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2300 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2301 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2302 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2303 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2304 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2305 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2306 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2307 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2308 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2309 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2310 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2311 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2312 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2313 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2314 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2315 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2316 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2317 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2318 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2319
mbed_official 133:d4dda5c437f0 2320 /******************* Bit definition for CAN_F12R1 register ******************/
mbed_official 133:d4dda5c437f0 2321 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2322 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2323 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2324 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2325 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2326 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2327 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2328 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2329 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2330 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2331 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2332 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2333 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2334 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2335 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2336 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2337 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2338 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2339 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2340 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2341 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2342 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2343 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2344 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2345 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2346 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2347 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2348 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2349 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2350 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2351 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2352 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2353
mbed_official 133:d4dda5c437f0 2354 /******************* Bit definition for CAN_F13R1 register ******************/
mbed_official 133:d4dda5c437f0 2355 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2356 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2357 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2358 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2359 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2360 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2361 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2362 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2363 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2364 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2365 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2366 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2367 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2368 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2369 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2370 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2371 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2372 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2373 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2374 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2375 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2376 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2377 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2378 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2379 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2380 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2381 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2382 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2383 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2384 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2385 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2386 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2387
mbed_official 133:d4dda5c437f0 2388 /******************* Bit definition for CAN_F0R2 register *******************/
mbed_official 133:d4dda5c437f0 2389 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2390 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2391 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2392 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2393 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2394 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2395 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2396 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2397 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2398 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2399 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2400 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2401 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2402 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2403 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2404 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2405 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2406 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2407 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2408 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2409 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2410 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2411 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2412 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2413 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2414 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2415 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2416 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2417 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2418 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2419 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2420 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2421
mbed_official 133:d4dda5c437f0 2422 /******************* Bit definition for CAN_F1R2 register *******************/
mbed_official 133:d4dda5c437f0 2423 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2424 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2425 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2426 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2427 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2428 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2429 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2430 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2431 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2432 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2433 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2434 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2435 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2436 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2437 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2438 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2439 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2440 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2441 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2442 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2443 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2444 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2445 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2446 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2447 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2448 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2449 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2450 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2451 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2452 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2453 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2454 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2455
mbed_official 133:d4dda5c437f0 2456 /******************* Bit definition for CAN_F2R2 register *******************/
mbed_official 133:d4dda5c437f0 2457 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2458 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2459 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2460 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2461 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2462 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2463 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2464 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2465 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2466 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2467 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2468 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2469 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2470 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2471 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2472 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2473 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2474 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2475 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2476 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2477 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2478 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2479 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2480 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2481 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2482 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2483 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2484 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2485 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2486 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2487 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2488 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2489
mbed_official 133:d4dda5c437f0 2490 /******************* Bit definition for CAN_F3R2 register *******************/
mbed_official 133:d4dda5c437f0 2491 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2492 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2493 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2494 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2495 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2496 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2497 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2498 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2499 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2500 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2501 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2502 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2503 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2504 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2505 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2506 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2507 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2508 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2509 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2510 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2511 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2512 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2513 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2514 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2515 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2516 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2517 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2518 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2519 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2520 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2521 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2522 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2523
mbed_official 133:d4dda5c437f0 2524 /******************* Bit definition for CAN_F4R2 register *******************/
mbed_official 133:d4dda5c437f0 2525 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2526 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2527 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2528 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2529 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2530 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2531 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2532 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2533 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2534 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2535 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2536 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2537 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2538 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2539 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2540 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2541 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2542 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2543 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2544 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2545 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2546 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2547 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2548 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2549 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2550 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2551 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2552 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2553 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2554 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2555 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2556 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2557
mbed_official 133:d4dda5c437f0 2558 /******************* Bit definition for CAN_F5R2 register *******************/
mbed_official 133:d4dda5c437f0 2559 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2560 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2561 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2562 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2563 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2564 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2565 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2566 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2567 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2568 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2569 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2570 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2571 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2572 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2573 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2574 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2575 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2576 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2577 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2578 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2579 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2580 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2581 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2582 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2583 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2584 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2585 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2586 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2587 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2588 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2589 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2590 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2591
mbed_official 133:d4dda5c437f0 2592 /******************* Bit definition for CAN_F6R2 register *******************/
mbed_official 133:d4dda5c437f0 2593 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2594 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2595 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2596 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2597 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2598 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2599 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2600 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2601 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2602 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2603 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2604 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2605 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2606 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2607 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2608 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2609 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2610 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2611 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2612 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2613 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2614 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2615 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2616 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2617 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2618 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2619 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2620 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2621 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2622 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2623 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2624 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2625
mbed_official 133:d4dda5c437f0 2626 /******************* Bit definition for CAN_F7R2 register *******************/
mbed_official 133:d4dda5c437f0 2627 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2628 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2629 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2630 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2631 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2632 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2633 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2634 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2635 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2636 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2637 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2638 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2639 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2640 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2641 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2642 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2643 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2644 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2645 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2646 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2647 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2648 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2649 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2650 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2651 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2652 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2653 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2654 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2655 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2656 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2657 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2658 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2659
mbed_official 133:d4dda5c437f0 2660 /******************* Bit definition for CAN_F8R2 register *******************/
mbed_official 133:d4dda5c437f0 2661 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2662 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2663 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2664 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2665 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2666 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2667 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2668 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2669 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2670 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2671 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2672 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2673 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2674 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2675 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2676 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2677 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2678 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2679 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2680 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2681 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2682 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2683 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2684 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2685 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2686 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2687 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2688 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2689 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2690 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2691 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2692 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2693
mbed_official 133:d4dda5c437f0 2694 /******************* Bit definition for CAN_F9R2 register *******************/
mbed_official 133:d4dda5c437f0 2695 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2696 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2697 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2698 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2699 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2700 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2701 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2702 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2703 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2704 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2705 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2706 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2707 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2708 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2709 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2710 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2711 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2712 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2713 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2714 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2715 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2716 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2717 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2718 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2719 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2720 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2721 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2722 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2723 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2724 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2725 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2726 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2727
mbed_official 133:d4dda5c437f0 2728 /******************* Bit definition for CAN_F10R2 register ******************/
mbed_official 133:d4dda5c437f0 2729 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2730 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2731 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2732 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2733 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2734 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2735 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2736 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2737 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2738 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2739 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2740 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2741 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2742 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2743 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2744 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2745 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2746 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2747 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2748 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2749 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2750 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2751 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2752 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2753 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2754 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2755 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2756 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2757 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2758 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2759 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2760 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2761
mbed_official 133:d4dda5c437f0 2762 /******************* Bit definition for CAN_F11R2 register ******************/
mbed_official 133:d4dda5c437f0 2763 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2764 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2765 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2766 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2767 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2768 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2769 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2770 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2771 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2772 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2773 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2774 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2775 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2776 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2777 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2778 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2779 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2780 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2781 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2782 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2783 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2784 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2785 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2786 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2787 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2788 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2789 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2790 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2791 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2792 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2793 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2794 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2795
mbed_official 133:d4dda5c437f0 2796 /******************* Bit definition for CAN_F12R2 register ******************/
mbed_official 133:d4dda5c437f0 2797 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2798 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2799 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2800 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2801 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2802 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2803 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2804 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2805 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2806 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2807 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2808 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2809 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2810 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2811 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2812 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2813 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2814 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2815 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2816 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2817 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2818 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2819 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2820 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2821 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2822 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2823 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2824 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2825 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2826 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2827 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2828 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2829
mbed_official 133:d4dda5c437f0 2830 /******************* Bit definition for CAN_F13R2 register ******************/
mbed_official 133:d4dda5c437f0 2831 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 133:d4dda5c437f0 2832 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 133:d4dda5c437f0 2833 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 133:d4dda5c437f0 2834 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 133:d4dda5c437f0 2835 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 133:d4dda5c437f0 2836 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 133:d4dda5c437f0 2837 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 133:d4dda5c437f0 2838 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 133:d4dda5c437f0 2839 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 133:d4dda5c437f0 2840 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 133:d4dda5c437f0 2841 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 133:d4dda5c437f0 2842 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 133:d4dda5c437f0 2843 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 133:d4dda5c437f0 2844 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 133:d4dda5c437f0 2845 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 133:d4dda5c437f0 2846 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 133:d4dda5c437f0 2847 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 133:d4dda5c437f0 2848 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 133:d4dda5c437f0 2849 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 133:d4dda5c437f0 2850 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 133:d4dda5c437f0 2851 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 133:d4dda5c437f0 2852 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 133:d4dda5c437f0 2853 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 133:d4dda5c437f0 2854 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 133:d4dda5c437f0 2855 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 133:d4dda5c437f0 2856 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 133:d4dda5c437f0 2857 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 133:d4dda5c437f0 2858 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 133:d4dda5c437f0 2859 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 133:d4dda5c437f0 2860 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 133:d4dda5c437f0 2861 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 133:d4dda5c437f0 2862 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 133:d4dda5c437f0 2863
mbed_official 133:d4dda5c437f0 2864 /******************************************************************************/
mbed_official 133:d4dda5c437f0 2865 /* */
mbed_official 133:d4dda5c437f0 2866 /* CRC calculation unit */
mbed_official 133:d4dda5c437f0 2867 /* */
mbed_official 133:d4dda5c437f0 2868 /******************************************************************************/
mbed_official 133:d4dda5c437f0 2869 /******************* Bit definition for CRC_DR register *********************/
mbed_official 133:d4dda5c437f0 2870 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 133:d4dda5c437f0 2871
mbed_official 133:d4dda5c437f0 2872
mbed_official 133:d4dda5c437f0 2873 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 133:d4dda5c437f0 2874 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 133:d4dda5c437f0 2875
mbed_official 133:d4dda5c437f0 2876
mbed_official 133:d4dda5c437f0 2877 /******************** Bit definition for CRC_CR register ********************/
mbed_official 133:d4dda5c437f0 2878 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
mbed_official 133:d4dda5c437f0 2879
mbed_official 133:d4dda5c437f0 2880
mbed_official 133:d4dda5c437f0 2881 /******************************************************************************/
mbed_official 133:d4dda5c437f0 2882 /* */
mbed_official 133:d4dda5c437f0 2883 /* Digital to Analog Converter */
mbed_official 133:d4dda5c437f0 2884 /* */
mbed_official 133:d4dda5c437f0 2885 /******************************************************************************/
mbed_official 133:d4dda5c437f0 2886 /******************** Bit definition for DAC_CR register ********************/
mbed_official 133:d4dda5c437f0 2887 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
mbed_official 133:d4dda5c437f0 2888 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
mbed_official 133:d4dda5c437f0 2889 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
mbed_official 133:d4dda5c437f0 2890
mbed_official 133:d4dda5c437f0 2891 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 133:d4dda5c437f0 2892 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 2893 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 2894 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 2895
mbed_official 133:d4dda5c437f0 2896 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 133:d4dda5c437f0 2897 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 2898 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 2899
mbed_official 133:d4dda5c437f0 2900 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 133:d4dda5c437f0 2901 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 2902 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 2903 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 2904 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 2905
mbed_official 133:d4dda5c437f0 2906 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
mbed_official 133:d4dda5c437f0 2907 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
mbed_official 133:d4dda5c437f0 2908 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
mbed_official 133:d4dda5c437f0 2909 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
mbed_official 133:d4dda5c437f0 2910
mbed_official 133:d4dda5c437f0 2911 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 133:d4dda5c437f0 2912 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 2913 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 2914 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 2915
mbed_official 133:d4dda5c437f0 2916 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 133:d4dda5c437f0 2917 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 2918 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 2919
mbed_official 133:d4dda5c437f0 2920 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 133:d4dda5c437f0 2921 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 2922 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 2923 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 2924 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 2925
mbed_official 133:d4dda5c437f0 2926 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
mbed_official 133:d4dda5c437f0 2927
mbed_official 133:d4dda5c437f0 2928 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 133:d4dda5c437f0 2929 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
mbed_official 133:d4dda5c437f0 2930 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
mbed_official 133:d4dda5c437f0 2931
mbed_official 133:d4dda5c437f0 2932 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 133:d4dda5c437f0 2933 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 133:d4dda5c437f0 2934
mbed_official 133:d4dda5c437f0 2935 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 133:d4dda5c437f0 2936 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 133:d4dda5c437f0 2937
mbed_official 133:d4dda5c437f0 2938 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 133:d4dda5c437f0 2939 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 133:d4dda5c437f0 2940
mbed_official 133:d4dda5c437f0 2941 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 133:d4dda5c437f0 2942 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 133:d4dda5c437f0 2943
mbed_official 133:d4dda5c437f0 2944 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 133:d4dda5c437f0 2945 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 133:d4dda5c437f0 2946
mbed_official 133:d4dda5c437f0 2947 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 133:d4dda5c437f0 2948 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 133:d4dda5c437f0 2949
mbed_official 133:d4dda5c437f0 2950 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 133:d4dda5c437f0 2951 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 133:d4dda5c437f0 2952 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 133:d4dda5c437f0 2953
mbed_official 133:d4dda5c437f0 2954 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 133:d4dda5c437f0 2955 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 133:d4dda5c437f0 2956 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 133:d4dda5c437f0 2957
mbed_official 133:d4dda5c437f0 2958 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 133:d4dda5c437f0 2959 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 133:d4dda5c437f0 2960 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 133:d4dda5c437f0 2961
mbed_official 133:d4dda5c437f0 2962 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 133:d4dda5c437f0 2963 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
mbed_official 133:d4dda5c437f0 2964
mbed_official 133:d4dda5c437f0 2965 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 133:d4dda5c437f0 2966 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
mbed_official 133:d4dda5c437f0 2967
mbed_official 133:d4dda5c437f0 2968 /******************** Bit definition for DAC_SR register ********************/
mbed_official 133:d4dda5c437f0 2969 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
mbed_official 133:d4dda5c437f0 2970 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
mbed_official 133:d4dda5c437f0 2971
mbed_official 133:d4dda5c437f0 2972 /******************************************************************************/
mbed_official 133:d4dda5c437f0 2973 /* */
mbed_official 133:d4dda5c437f0 2974 /* Debug MCU */
mbed_official 133:d4dda5c437f0 2975 /* */
mbed_official 133:d4dda5c437f0 2976 /******************************************************************************/
mbed_official 133:d4dda5c437f0 2977
mbed_official 133:d4dda5c437f0 2978 /******************************************************************************/
mbed_official 133:d4dda5c437f0 2979 /* */
mbed_official 133:d4dda5c437f0 2980 /* DCMI */
mbed_official 133:d4dda5c437f0 2981 /* */
mbed_official 133:d4dda5c437f0 2982 /******************************************************************************/
mbed_official 133:d4dda5c437f0 2983 /******************** Bits definition for DCMI_CR register ******************/
mbed_official 133:d4dda5c437f0 2984 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 2985 #define DCMI_CR_CM ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 2986 #define DCMI_CR_CROP ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 2987 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 2988 #define DCMI_CR_ESS ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 2989 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 2990 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 2991 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 2992 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 2993 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 2994 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 2995 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 2996 #define DCMI_CR_CRE ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 2997 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 2998
mbed_official 133:d4dda5c437f0 2999 /******************** Bits definition for DCMI_SR register ******************/
mbed_official 133:d4dda5c437f0 3000 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3001 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 3002 #define DCMI_SR_FNE ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3003
mbed_official 133:d4dda5c437f0 3004 /******************** Bits definition for DCMI_RISR register ****************/
mbed_official 133:d4dda5c437f0 3005 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3006 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 3007 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3008 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 3009 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 3010
mbed_official 133:d4dda5c437f0 3011 /******************** Bits definition for DCMI_IER register *****************/
mbed_official 133:d4dda5c437f0 3012 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3013 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 3014 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3015 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 3016 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 3017
mbed_official 133:d4dda5c437f0 3018 /******************** Bits definition for DCMI_MISR register ****************/
mbed_official 133:d4dda5c437f0 3019 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3020 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 3021 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3022 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 3023 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 3024
mbed_official 133:d4dda5c437f0 3025 /******************** Bits definition for DCMI_ICR register *****************/
mbed_official 133:d4dda5c437f0 3026 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3027 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 3028 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3029 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 3030 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 3031
mbed_official 133:d4dda5c437f0 3032 /******************************************************************************/
mbed_official 133:d4dda5c437f0 3033 /* */
mbed_official 133:d4dda5c437f0 3034 /* DMA Controller */
mbed_official 133:d4dda5c437f0 3035 /* */
mbed_official 133:d4dda5c437f0 3036 /******************************************************************************/
mbed_official 133:d4dda5c437f0 3037 /******************** Bits definition for DMA_SxCR register *****************/
mbed_official 133:d4dda5c437f0 3038 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
mbed_official 133:d4dda5c437f0 3039 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 3040 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 3041 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 3042 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
mbed_official 133:d4dda5c437f0 3043 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 3044 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 3045 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
mbed_official 133:d4dda5c437f0 3046 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 3047 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 3048 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 3049 #define DMA_SxCR_CT ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 3050 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 3051 #define DMA_SxCR_PL ((uint32_t)0x00030000)
mbed_official 133:d4dda5c437f0 3052 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 3053 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 3054 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 3055 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
mbed_official 133:d4dda5c437f0 3056 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 3057 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 3058 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
mbed_official 133:d4dda5c437f0 3059 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 3060 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 3061 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 3062 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 3063 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 3064 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
mbed_official 133:d4dda5c437f0 3065 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 3066 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 3067 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 3068 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 3069 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 3070 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3071 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 3072 #define DMA_SxCR_EN ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3073
mbed_official 133:d4dda5c437f0 3074 /******************** Bits definition for DMA_SxCNDTR register **************/
mbed_official 133:d4dda5c437f0 3075 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
mbed_official 133:d4dda5c437f0 3076 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3077 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 3078 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3079 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 3080 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 3081 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 3082 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 3083 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 3084 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 3085 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 3086 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 3087 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 3088 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 3089 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 3090 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 3091 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 3092
mbed_official 133:d4dda5c437f0 3093 /******************** Bits definition for DMA_SxFCR register ****************/
mbed_official 133:d4dda5c437f0 3094 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 3095 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
mbed_official 133:d4dda5c437f0 3096 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 3097 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 3098 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 3099 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3100 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
mbed_official 133:d4dda5c437f0 3101 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3102 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 3103
mbed_official 133:d4dda5c437f0 3104 /******************** Bits definition for DMA_LISR register *****************/
mbed_official 133:d4dda5c437f0 3105 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 3106 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 3107 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 3108 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 3109 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 3110 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 3111 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 3112 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 3113 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 3114 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 3115 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 3116 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 3117 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 3118 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 3119 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 3120 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 3121 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 3122 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 3123 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3124 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3125
mbed_official 133:d4dda5c437f0 3126 /******************** Bits definition for DMA_HISR register *****************/
mbed_official 133:d4dda5c437f0 3127 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 3128 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 3129 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 3130 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 3131 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 3132 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 3133 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 3134 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 3135 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 3136 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 3137 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 3138 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 3139 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 3140 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 3141 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 3142 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 3143 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 3144 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 3145 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3146 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3147
mbed_official 133:d4dda5c437f0 3148 /******************** Bits definition for DMA_LIFCR register ****************/
mbed_official 133:d4dda5c437f0 3149 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 3150 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 3151 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 3152 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 3153 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 3154 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 3155 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 3156 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 3157 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 3158 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 3159 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 3160 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 3161 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 3162 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 3163 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 3164 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 3165 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 3166 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 3167 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3168 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3169
mbed_official 133:d4dda5c437f0 3170 /******************** Bits definition for DMA_HIFCR register ****************/
mbed_official 133:d4dda5c437f0 3171 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 3172 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 3173 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 3174 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 3175 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 3176 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 3177 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 3178 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 3179 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 3180 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 3181 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 3182 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 3183 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 3184 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 3185 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 3186 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 3187 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 3188 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 3189 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3190 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3191
mbed_official 133:d4dda5c437f0 3192
mbed_official 133:d4dda5c437f0 3193 /******************************************************************************/
mbed_official 133:d4dda5c437f0 3194 /* */
mbed_official 133:d4dda5c437f0 3195 /* External Interrupt/Event Controller */
mbed_official 133:d4dda5c437f0 3196 /* */
mbed_official 133:d4dda5c437f0 3197 /******************************************************************************/
mbed_official 133:d4dda5c437f0 3198 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 133:d4dda5c437f0 3199 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 133:d4dda5c437f0 3200 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 133:d4dda5c437f0 3201 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 133:d4dda5c437f0 3202 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 133:d4dda5c437f0 3203 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 133:d4dda5c437f0 3204 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 133:d4dda5c437f0 3205 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 133:d4dda5c437f0 3206 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 133:d4dda5c437f0 3207 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 133:d4dda5c437f0 3208 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 133:d4dda5c437f0 3209 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 133:d4dda5c437f0 3210 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 133:d4dda5c437f0 3211 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 133:d4dda5c437f0 3212 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 133:d4dda5c437f0 3213 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 133:d4dda5c437f0 3214 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 133:d4dda5c437f0 3215 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 133:d4dda5c437f0 3216 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 133:d4dda5c437f0 3217 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 133:d4dda5c437f0 3218 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 532:fe11edbda85c 3219 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 532:fe11edbda85c 3220 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 532:fe11edbda85c 3221 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 133:d4dda5c437f0 3222
mbed_official 133:d4dda5c437f0 3223 /******************* Bit definition for EXTI_EMR register *******************/
mbed_official 133:d4dda5c437f0 3224 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 133:d4dda5c437f0 3225 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 133:d4dda5c437f0 3226 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 133:d4dda5c437f0 3227 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 133:d4dda5c437f0 3228 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 133:d4dda5c437f0 3229 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 133:d4dda5c437f0 3230 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 133:d4dda5c437f0 3231 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 133:d4dda5c437f0 3232 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 133:d4dda5c437f0 3233 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 133:d4dda5c437f0 3234 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 133:d4dda5c437f0 3235 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 133:d4dda5c437f0 3236 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 133:d4dda5c437f0 3237 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 133:d4dda5c437f0 3238 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 133:d4dda5c437f0 3239 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 133:d4dda5c437f0 3240 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 133:d4dda5c437f0 3241 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 133:d4dda5c437f0 3242 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 133:d4dda5c437f0 3243 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 532:fe11edbda85c 3244 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 532:fe11edbda85c 3245 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 532:fe11edbda85c 3246 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 133:d4dda5c437f0 3247
mbed_official 133:d4dda5c437f0 3248 /****************** Bit definition for EXTI_RTSR register *******************/
mbed_official 133:d4dda5c437f0 3249 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 133:d4dda5c437f0 3250 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 133:d4dda5c437f0 3251 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 133:d4dda5c437f0 3252 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 133:d4dda5c437f0 3253 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 133:d4dda5c437f0 3254 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 133:d4dda5c437f0 3255 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 133:d4dda5c437f0 3256 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 133:d4dda5c437f0 3257 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 133:d4dda5c437f0 3258 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 133:d4dda5c437f0 3259 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 133:d4dda5c437f0 3260 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 133:d4dda5c437f0 3261 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 133:d4dda5c437f0 3262 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 133:d4dda5c437f0 3263 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 133:d4dda5c437f0 3264 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 133:d4dda5c437f0 3265 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 133:d4dda5c437f0 3266 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 133:d4dda5c437f0 3267 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
mbed_official 133:d4dda5c437f0 3268 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 532:fe11edbda85c 3269 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 532:fe11edbda85c 3270 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 532:fe11edbda85c 3271 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 133:d4dda5c437f0 3272
mbed_official 133:d4dda5c437f0 3273 /****************** Bit definition for EXTI_FTSR register *******************/
mbed_official 133:d4dda5c437f0 3274 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 133:d4dda5c437f0 3275 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 133:d4dda5c437f0 3276 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 133:d4dda5c437f0 3277 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 133:d4dda5c437f0 3278 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 133:d4dda5c437f0 3279 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 133:d4dda5c437f0 3280 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 133:d4dda5c437f0 3281 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 133:d4dda5c437f0 3282 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 133:d4dda5c437f0 3283 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 133:d4dda5c437f0 3284 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 133:d4dda5c437f0 3285 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 133:d4dda5c437f0 3286 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 133:d4dda5c437f0 3287 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 133:d4dda5c437f0 3288 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 133:d4dda5c437f0 3289 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 133:d4dda5c437f0 3290 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 133:d4dda5c437f0 3291 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 133:d4dda5c437f0 3292 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
mbed_official 133:d4dda5c437f0 3293 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 532:fe11edbda85c 3294 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 532:fe11edbda85c 3295 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 532:fe11edbda85c 3296 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 133:d4dda5c437f0 3297
mbed_official 133:d4dda5c437f0 3298 /****************** Bit definition for EXTI_SWIER register ******************/
mbed_official 133:d4dda5c437f0 3299 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 133:d4dda5c437f0 3300 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 133:d4dda5c437f0 3301 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 133:d4dda5c437f0 3302 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 133:d4dda5c437f0 3303 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 133:d4dda5c437f0 3304 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 133:d4dda5c437f0 3305 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 133:d4dda5c437f0 3306 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 133:d4dda5c437f0 3307 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 133:d4dda5c437f0 3308 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 133:d4dda5c437f0 3309 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 133:d4dda5c437f0 3310 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 133:d4dda5c437f0 3311 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 133:d4dda5c437f0 3312 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 133:d4dda5c437f0 3313 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 133:d4dda5c437f0 3314 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 133:d4dda5c437f0 3315 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 133:d4dda5c437f0 3316 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 133:d4dda5c437f0 3317 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
mbed_official 133:d4dda5c437f0 3318 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 532:fe11edbda85c 3319 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 532:fe11edbda85c 3320 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 532:fe11edbda85c 3321 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 133:d4dda5c437f0 3322
mbed_official 133:d4dda5c437f0 3323 /******************* Bit definition for EXTI_PR register ********************/
mbed_official 133:d4dda5c437f0 3324 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
mbed_official 133:d4dda5c437f0 3325 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
mbed_official 133:d4dda5c437f0 3326 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
mbed_official 133:d4dda5c437f0 3327 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
mbed_official 133:d4dda5c437f0 3328 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
mbed_official 133:d4dda5c437f0 3329 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
mbed_official 133:d4dda5c437f0 3330 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
mbed_official 133:d4dda5c437f0 3331 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
mbed_official 133:d4dda5c437f0 3332 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
mbed_official 133:d4dda5c437f0 3333 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
mbed_official 133:d4dda5c437f0 3334 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
mbed_official 133:d4dda5c437f0 3335 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
mbed_official 133:d4dda5c437f0 3336 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
mbed_official 133:d4dda5c437f0 3337 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
mbed_official 133:d4dda5c437f0 3338 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
mbed_official 133:d4dda5c437f0 3339 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
mbed_official 133:d4dda5c437f0 3340 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
mbed_official 133:d4dda5c437f0 3341 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
mbed_official 133:d4dda5c437f0 3342 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
mbed_official 133:d4dda5c437f0 3343 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
mbed_official 532:fe11edbda85c 3344 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
mbed_official 532:fe11edbda85c 3345 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
mbed_official 532:fe11edbda85c 3346 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
mbed_official 133:d4dda5c437f0 3347
mbed_official 133:d4dda5c437f0 3348 /******************************************************************************/
mbed_official 133:d4dda5c437f0 3349 /* */
mbed_official 133:d4dda5c437f0 3350 /* FLASH */
mbed_official 133:d4dda5c437f0 3351 /* */
mbed_official 133:d4dda5c437f0 3352 /******************************************************************************/
mbed_official 133:d4dda5c437f0 3353 /******************* Bits definition for FLASH_ACR register *****************/
mbed_official 133:d4dda5c437f0 3354 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
mbed_official 133:d4dda5c437f0 3355 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 3356 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3357 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 3358 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
mbed_official 133:d4dda5c437f0 3359 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3360 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
mbed_official 133:d4dda5c437f0 3361 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
mbed_official 133:d4dda5c437f0 3362 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
mbed_official 133:d4dda5c437f0 3363
mbed_official 133:d4dda5c437f0 3364 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 3365 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 3366 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 3367 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 3368 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 3369 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
mbed_official 133:d4dda5c437f0 3370 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
mbed_official 133:d4dda5c437f0 3371
mbed_official 133:d4dda5c437f0 3372 /******************* Bits definition for FLASH_SR register ******************/
mbed_official 133:d4dda5c437f0 3373 #define FLASH_SR_EOP ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3374 #define FLASH_SR_SOP ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 3375 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 3376 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 3377 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 3378 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 3379 #define FLASH_SR_BSY ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 3380
mbed_official 133:d4dda5c437f0 3381 /******************* Bits definition for FLASH_CR register ******************/
mbed_official 133:d4dda5c437f0 3382 #define FLASH_CR_PG ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3383 #define FLASH_CR_SER ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 3384 #define FLASH_CR_MER ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3385 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
mbed_official 133:d4dda5c437f0 3386 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 3387 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 3388 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 3389 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 3390 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 3391 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
mbed_official 133:d4dda5c437f0 3392 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 3393 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 3394 #define FLASH_CR_STRT ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 3395 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 3396 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
mbed_official 133:d4dda5c437f0 3397
mbed_official 133:d4dda5c437f0 3398 /******************* Bits definition for FLASH_OPTCR register ***************/
mbed_official 133:d4dda5c437f0 3399 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 3400 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 3401 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 3402 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 3403 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
mbed_official 133:d4dda5c437f0 3404
mbed_official 133:d4dda5c437f0 3405 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 3406 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 3407 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 3408 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
mbed_official 133:d4dda5c437f0 3409 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 3410 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 3411 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 3412 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 3413 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 3414 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 3415 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 3416 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 3417 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
mbed_official 133:d4dda5c437f0 3418 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 3419 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 3420 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 3421 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 3422 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 3423 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 3424 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 3425 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 3426 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 3427 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 3428 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 3429 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 3430
mbed_official 133:d4dda5c437f0 3431 /****************** Bits definition for FLASH_OPTCR1 register ***************/
mbed_official 133:d4dda5c437f0 3432 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
mbed_official 133:d4dda5c437f0 3433 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 3434 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 3435 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 3436 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 3437 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 3438 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 3439 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 3440 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 3441 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 3442 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 3443 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 3444 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 3445
mbed_official 133:d4dda5c437f0 3446 /******************************************************************************/
mbed_official 133:d4dda5c437f0 3447 /* */
mbed_official 133:d4dda5c437f0 3448 /* Flexible Static Memory Controller */
mbed_official 133:d4dda5c437f0 3449 /* */
mbed_official 133:d4dda5c437f0 3450 /******************************************************************************/
mbed_official 133:d4dda5c437f0 3451 /****************** Bit definition for FSMC_BCR1 register *******************/
mbed_official 133:d4dda5c437f0 3452 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 133:d4dda5c437f0 3453 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 133:d4dda5c437f0 3454
mbed_official 133:d4dda5c437f0 3455 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 133:d4dda5c437f0 3456 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3457 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3458
mbed_official 133:d4dda5c437f0 3459 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 133:d4dda5c437f0 3460 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3461 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3462
mbed_official 133:d4dda5c437f0 3463 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 133:d4dda5c437f0 3464 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 133:d4dda5c437f0 3465 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 133:d4dda5c437f0 3466 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 133:d4dda5c437f0 3467 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 133:d4dda5c437f0 3468 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 133:d4dda5c437f0 3469 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 133:d4dda5c437f0 3470 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 133:d4dda5c437f0 3471 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 133:d4dda5c437f0 3472 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 133:d4dda5c437f0 3473
mbed_official 133:d4dda5c437f0 3474 /****************** Bit definition for FSMC_BCR2 register *******************/
mbed_official 133:d4dda5c437f0 3475 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 133:d4dda5c437f0 3476 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 133:d4dda5c437f0 3477
mbed_official 133:d4dda5c437f0 3478 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 133:d4dda5c437f0 3479 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3480 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3481
mbed_official 133:d4dda5c437f0 3482 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 133:d4dda5c437f0 3483 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3484 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3485
mbed_official 133:d4dda5c437f0 3486 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 133:d4dda5c437f0 3487 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 133:d4dda5c437f0 3488 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 133:d4dda5c437f0 3489 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 133:d4dda5c437f0 3490 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 133:d4dda5c437f0 3491 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 133:d4dda5c437f0 3492 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 133:d4dda5c437f0 3493 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 133:d4dda5c437f0 3494 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 133:d4dda5c437f0 3495 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 133:d4dda5c437f0 3496
mbed_official 133:d4dda5c437f0 3497 /****************** Bit definition for FSMC_BCR3 register *******************/
mbed_official 133:d4dda5c437f0 3498 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 133:d4dda5c437f0 3499 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 133:d4dda5c437f0 3500
mbed_official 133:d4dda5c437f0 3501 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 133:d4dda5c437f0 3502 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3503 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3504
mbed_official 133:d4dda5c437f0 3505 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 133:d4dda5c437f0 3506 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3507 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3508
mbed_official 133:d4dda5c437f0 3509 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 133:d4dda5c437f0 3510 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 133:d4dda5c437f0 3511 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 133:d4dda5c437f0 3512 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 133:d4dda5c437f0 3513 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 133:d4dda5c437f0 3514 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 133:d4dda5c437f0 3515 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 133:d4dda5c437f0 3516 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 133:d4dda5c437f0 3517 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 133:d4dda5c437f0 3518 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 133:d4dda5c437f0 3519
mbed_official 133:d4dda5c437f0 3520 /****************** Bit definition for FSMC_BCR4 register *******************/
mbed_official 133:d4dda5c437f0 3521 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 133:d4dda5c437f0 3522 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 133:d4dda5c437f0 3523
mbed_official 133:d4dda5c437f0 3524 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 133:d4dda5c437f0 3525 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3526 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3527
mbed_official 133:d4dda5c437f0 3528 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 133:d4dda5c437f0 3529 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3530 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3531
mbed_official 133:d4dda5c437f0 3532 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 133:d4dda5c437f0 3533 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 133:d4dda5c437f0 3534 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 133:d4dda5c437f0 3535 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 133:d4dda5c437f0 3536 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 133:d4dda5c437f0 3537 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 133:d4dda5c437f0 3538 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 133:d4dda5c437f0 3539 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 133:d4dda5c437f0 3540 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 133:d4dda5c437f0 3541 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 133:d4dda5c437f0 3542
mbed_official 133:d4dda5c437f0 3543 /****************** Bit definition for FSMC_BTR1 register ******************/
mbed_official 133:d4dda5c437f0 3544 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 133:d4dda5c437f0 3545 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3546 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3547 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3548 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3549
mbed_official 133:d4dda5c437f0 3550 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 133:d4dda5c437f0 3551 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3552 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3553 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3554 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3555
mbed_official 613:bc40b8d2aec4 3556 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
mbed_official 133:d4dda5c437f0 3557 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3558 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3559 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3560 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3561 #define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3562 #define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3563 #define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3564 #define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 3565
mbed_official 133:d4dda5c437f0 3566 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 133:d4dda5c437f0 3567 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3568 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3569 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3570 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3571
mbed_official 133:d4dda5c437f0 3572 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 133:d4dda5c437f0 3573 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3574 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3575 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3576 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3577
mbed_official 133:d4dda5c437f0 3578 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 133:d4dda5c437f0 3579 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3580 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3581 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3582 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3583
mbed_official 133:d4dda5c437f0 3584 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 133:d4dda5c437f0 3585 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3586 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3587
mbed_official 133:d4dda5c437f0 3588 /****************** Bit definition for FSMC_BTR2 register *******************/
mbed_official 133:d4dda5c437f0 3589 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 133:d4dda5c437f0 3590 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3591 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3592 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3593 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3594
mbed_official 133:d4dda5c437f0 3595 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 133:d4dda5c437f0 3596 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3597 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3598 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3599 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3600
mbed_official 613:bc40b8d2aec4 3601 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
mbed_official 133:d4dda5c437f0 3602 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3603 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3604 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3605 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3606 #define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3607 #define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3608 #define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3609 #define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 3610
mbed_official 133:d4dda5c437f0 3611 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 133:d4dda5c437f0 3612 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3613 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3614 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3615 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3616
mbed_official 133:d4dda5c437f0 3617 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 133:d4dda5c437f0 3618 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3619 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3620 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3621 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3622
mbed_official 133:d4dda5c437f0 3623 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 133:d4dda5c437f0 3624 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3625 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3626 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3627 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3628
mbed_official 133:d4dda5c437f0 3629 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 133:d4dda5c437f0 3630 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3631 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3632
mbed_official 133:d4dda5c437f0 3633 /******************* Bit definition for FSMC_BTR3 register *******************/
mbed_official 133:d4dda5c437f0 3634 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 133:d4dda5c437f0 3635 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3636 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3637 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3638 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3639
mbed_official 133:d4dda5c437f0 3640 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 133:d4dda5c437f0 3641 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3642 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3643 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3644 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3645
mbed_official 613:bc40b8d2aec4 3646 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
mbed_official 133:d4dda5c437f0 3647 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3648 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3649 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3650 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3651 #define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3652 #define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3653 #define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3654 #define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 3655
mbed_official 133:d4dda5c437f0 3656 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 133:d4dda5c437f0 3657 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3658 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3659 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3660 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3661
mbed_official 133:d4dda5c437f0 3662 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 133:d4dda5c437f0 3663 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3664 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3665 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3666 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3667
mbed_official 133:d4dda5c437f0 3668 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 133:d4dda5c437f0 3669 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3670 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3671 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3672 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3673
mbed_official 133:d4dda5c437f0 3674 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 133:d4dda5c437f0 3675 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3676 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3677
mbed_official 133:d4dda5c437f0 3678 /****************** Bit definition for FSMC_BTR4 register *******************/
mbed_official 133:d4dda5c437f0 3679 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 133:d4dda5c437f0 3680 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3681 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3682 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3683 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3684
mbed_official 133:d4dda5c437f0 3685 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 133:d4dda5c437f0 3686 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3687 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3688 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3689 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3690
mbed_official 133:d4dda5c437f0 3691 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 133:d4dda5c437f0 3692 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3693 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3694 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3695 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3696 #define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3697 #define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3698 #define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3699 #define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 3700
mbed_official 133:d4dda5c437f0 3701 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 133:d4dda5c437f0 3702 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3703 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3704 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3705 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3706
mbed_official 133:d4dda5c437f0 3707 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 133:d4dda5c437f0 3708 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3709 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3710 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3711 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3712
mbed_official 133:d4dda5c437f0 3713 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 133:d4dda5c437f0 3714 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3715 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3716 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3717 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3718
mbed_official 133:d4dda5c437f0 3719 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 133:d4dda5c437f0 3720 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3721 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3722
mbed_official 133:d4dda5c437f0 3723 /****************** Bit definition for FSMC_BWTR1 register ******************/
mbed_official 133:d4dda5c437f0 3724 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 133:d4dda5c437f0 3725 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3726 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3727 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3728 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3729
mbed_official 133:d4dda5c437f0 3730 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 133:d4dda5c437f0 3731 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3732 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3733 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3734 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3735
mbed_official 613:bc40b8d2aec4 3736 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
mbed_official 133:d4dda5c437f0 3737 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3738 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3739 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3740 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3741 #define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3742 #define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3743 #define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3744 #define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 3745
mbed_official 532:fe11edbda85c 3746 #define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
mbed_official 532:fe11edbda85c 3747 #define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 532:fe11edbda85c 3748 #define FSMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 532:fe11edbda85c 3749 #define FSMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 532:fe11edbda85c 3750 #define FSMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 532:fe11edbda85c 3751
mbed_official 133:d4dda5c437f0 3752 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 133:d4dda5c437f0 3753 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3754 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3755 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3756 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3757
mbed_official 133:d4dda5c437f0 3758 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 133:d4dda5c437f0 3759 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3760 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3761 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3762 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3763
mbed_official 133:d4dda5c437f0 3764 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 133:d4dda5c437f0 3765 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3766 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3767
mbed_official 133:d4dda5c437f0 3768 /****************** Bit definition for FSMC_BWTR2 register ******************/
mbed_official 133:d4dda5c437f0 3769 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 133:d4dda5c437f0 3770 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3771 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3772 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3773 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3774
mbed_official 133:d4dda5c437f0 3775 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 133:d4dda5c437f0 3776 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3777 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3778 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3779 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3780
mbed_official 613:bc40b8d2aec4 3781 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
mbed_official 133:d4dda5c437f0 3782 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3783 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3784 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3785 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3786 #define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3787 #define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3788 #define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3789 #define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 3790
mbed_official 532:fe11edbda85c 3791 #define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
mbed_official 532:fe11edbda85c 3792 #define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 532:fe11edbda85c 3793 #define FSMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 532:fe11edbda85c 3794 #define FSMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 532:fe11edbda85c 3795 #define FSMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 532:fe11edbda85c 3796
mbed_official 133:d4dda5c437f0 3797 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 133:d4dda5c437f0 3798 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3799 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
mbed_official 133:d4dda5c437f0 3800 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3801 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3802
mbed_official 133:d4dda5c437f0 3803 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 133:d4dda5c437f0 3804 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3805 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3806 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3807 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3808
mbed_official 133:d4dda5c437f0 3809 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 133:d4dda5c437f0 3810 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3811 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3812
mbed_official 133:d4dda5c437f0 3813 /****************** Bit definition for FSMC_BWTR3 register ******************/
mbed_official 133:d4dda5c437f0 3814 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 133:d4dda5c437f0 3815 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3816 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3817 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3818 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3819
mbed_official 133:d4dda5c437f0 3820 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 133:d4dda5c437f0 3821 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3822 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3823 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3824 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3825
mbed_official 613:bc40b8d2aec4 3826 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
mbed_official 133:d4dda5c437f0 3827 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3828 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3829 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3830 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3831 #define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3832 #define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3833 #define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3834 #define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 3835
mbed_official 532:fe11edbda85c 3836 #define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
mbed_official 532:fe11edbda85c 3837 #define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 532:fe11edbda85c 3838 #define FSMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 532:fe11edbda85c 3839 #define FSMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 532:fe11edbda85c 3840 #define FSMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 532:fe11edbda85c 3841
mbed_official 133:d4dda5c437f0 3842 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 133:d4dda5c437f0 3843 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3844 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3845 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3846 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3847
mbed_official 133:d4dda5c437f0 3848 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 133:d4dda5c437f0 3849 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3850 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3851 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3852 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3853
mbed_official 133:d4dda5c437f0 3854 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 133:d4dda5c437f0 3855 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3856 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3857
mbed_official 133:d4dda5c437f0 3858 /****************** Bit definition for FSMC_BWTR4 register ******************/
mbed_official 133:d4dda5c437f0 3859 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 133:d4dda5c437f0 3860 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3861 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3862 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3863 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3864
mbed_official 133:d4dda5c437f0 3865 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 133:d4dda5c437f0 3866 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3867 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3868 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3869 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3870
mbed_official 133:d4dda5c437f0 3871 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 133:d4dda5c437f0 3872 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3873 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3874 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3875 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 613:bc40b8d2aec4 3876 #define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 613:bc40b8d2aec4 3877 #define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 613:bc40b8d2aec4 3878 #define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 613:bc40b8d2aec4 3879 #define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 3880
mbed_official 532:fe11edbda85c 3881 #define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
mbed_official 532:fe11edbda85c 3882 #define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 532:fe11edbda85c 3883 #define FSMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 532:fe11edbda85c 3884 #define FSMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 532:fe11edbda85c 3885 #define FSMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 532:fe11edbda85c 3886
mbed_official 133:d4dda5c437f0 3887 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 133:d4dda5c437f0 3888 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3889 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3890 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3891 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3892
mbed_official 133:d4dda5c437f0 3893 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 133:d4dda5c437f0 3894 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3895 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3896 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3897 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3898
mbed_official 133:d4dda5c437f0 3899 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 133:d4dda5c437f0 3900 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3901 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3902
mbed_official 133:d4dda5c437f0 3903 /****************** Bit definition for FSMC_PCR2 register *******************/
mbed_official 133:d4dda5c437f0 3904 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
mbed_official 133:d4dda5c437f0 3905 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
mbed_official 133:d4dda5c437f0 3906 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
mbed_official 133:d4dda5c437f0 3907
mbed_official 133:d4dda5c437f0 3908 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
mbed_official 133:d4dda5c437f0 3909 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3910 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3911
mbed_official 133:d4dda5c437f0 3912 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
mbed_official 133:d4dda5c437f0 3913
mbed_official 133:d4dda5c437f0 3914 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
mbed_official 133:d4dda5c437f0 3915 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3916 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3917 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3918 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3919
mbed_official 133:d4dda5c437f0 3920 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
mbed_official 133:d4dda5c437f0 3921 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3922 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3923 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3924 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3925
mbed_official 133:d4dda5c437f0 3926 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
mbed_official 133:d4dda5c437f0 3927 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3928 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3929 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3930
mbed_official 133:d4dda5c437f0 3931 /****************** Bit definition for FSMC_PCR3 register *******************/
mbed_official 133:d4dda5c437f0 3932 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
mbed_official 133:d4dda5c437f0 3933 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
mbed_official 133:d4dda5c437f0 3934 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
mbed_official 133:d4dda5c437f0 3935
mbed_official 133:d4dda5c437f0 3936 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
mbed_official 133:d4dda5c437f0 3937 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3938 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3939
mbed_official 133:d4dda5c437f0 3940 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
mbed_official 133:d4dda5c437f0 3941
mbed_official 133:d4dda5c437f0 3942 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
mbed_official 133:d4dda5c437f0 3943 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3944 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3945 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3946 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3947
mbed_official 133:d4dda5c437f0 3948 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
mbed_official 133:d4dda5c437f0 3949 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3950 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3951 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3952 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3953
mbed_official 133:d4dda5c437f0 3954 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
mbed_official 133:d4dda5c437f0 3955 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3956 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3957 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3958
mbed_official 133:d4dda5c437f0 3959 /****************** Bit definition for FSMC_PCR4 register *******************/
mbed_official 133:d4dda5c437f0 3960 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
mbed_official 133:d4dda5c437f0 3961 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
mbed_official 133:d4dda5c437f0 3962 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
mbed_official 133:d4dda5c437f0 3963
mbed_official 133:d4dda5c437f0 3964 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
mbed_official 133:d4dda5c437f0 3965 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3966 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3967
mbed_official 133:d4dda5c437f0 3968 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
mbed_official 133:d4dda5c437f0 3969
mbed_official 133:d4dda5c437f0 3970 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
mbed_official 133:d4dda5c437f0 3971 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3972 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3973 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3974 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3975
mbed_official 133:d4dda5c437f0 3976 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
mbed_official 133:d4dda5c437f0 3977 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3978 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3979 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3980 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 3981
mbed_official 133:d4dda5c437f0 3982 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
mbed_official 133:d4dda5c437f0 3983 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 3984 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 3985 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 3986
mbed_official 133:d4dda5c437f0 3987 /******************* Bit definition for FSMC_SR2 register *******************/
mbed_official 133:d4dda5c437f0 3988 #define FSMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
mbed_official 133:d4dda5c437f0 3989 #define FSMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
mbed_official 133:d4dda5c437f0 3990 #define FSMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
mbed_official 133:d4dda5c437f0 3991 #define FSMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
mbed_official 133:d4dda5c437f0 3992 #define FSMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
mbed_official 133:d4dda5c437f0 3993 #define FSMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
mbed_official 133:d4dda5c437f0 3994 #define FSMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
mbed_official 133:d4dda5c437f0 3995
mbed_official 133:d4dda5c437f0 3996 /******************* Bit definition for FSMC_SR3 register *******************/
mbed_official 133:d4dda5c437f0 3997 #define FSMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
mbed_official 133:d4dda5c437f0 3998 #define FSMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
mbed_official 133:d4dda5c437f0 3999 #define FSMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
mbed_official 133:d4dda5c437f0 4000 #define FSMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
mbed_official 133:d4dda5c437f0 4001 #define FSMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
mbed_official 133:d4dda5c437f0 4002 #define FSMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
mbed_official 133:d4dda5c437f0 4003 #define FSMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
mbed_official 133:d4dda5c437f0 4004
mbed_official 133:d4dda5c437f0 4005 /******************* Bit definition for FSMC_SR4 register *******************/
mbed_official 133:d4dda5c437f0 4006 #define FSMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
mbed_official 133:d4dda5c437f0 4007 #define FSMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
mbed_official 133:d4dda5c437f0 4008 #define FSMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
mbed_official 133:d4dda5c437f0 4009 #define FSMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
mbed_official 133:d4dda5c437f0 4010 #define FSMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
mbed_official 133:d4dda5c437f0 4011 #define FSMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
mbed_official 133:d4dda5c437f0 4012 #define FSMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
mbed_official 133:d4dda5c437f0 4013
mbed_official 133:d4dda5c437f0 4014 /****************** Bit definition for FSMC_PMEM2 register ******************/
mbed_official 133:d4dda5c437f0 4015 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
mbed_official 133:d4dda5c437f0 4016 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4017 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4018 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4019 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4020 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4021 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4022 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4023 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4024
mbed_official 133:d4dda5c437f0 4025 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
mbed_official 133:d4dda5c437f0 4026 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4027 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4028 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4029 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4030 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4031 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4032 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4033 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4034
mbed_official 133:d4dda5c437f0 4035 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
mbed_official 133:d4dda5c437f0 4036 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4037 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4038 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4039 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4040 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4041 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4042 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4043 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4044
mbed_official 133:d4dda5c437f0 4045 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
mbed_official 133:d4dda5c437f0 4046 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4047 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4048 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4049 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4050 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4051 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4052 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4053 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4054
mbed_official 133:d4dda5c437f0 4055 /****************** Bit definition for FSMC_PMEM3 register ******************/
mbed_official 133:d4dda5c437f0 4056 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
mbed_official 133:d4dda5c437f0 4057 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4058 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4059 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4060 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4061 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4062 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4063 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4064 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4065
mbed_official 133:d4dda5c437f0 4066 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
mbed_official 133:d4dda5c437f0 4067 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4068 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4069 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4070 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4071 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4072 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4073 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4074 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4075
mbed_official 133:d4dda5c437f0 4076 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
mbed_official 133:d4dda5c437f0 4077 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4078 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4079 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4080 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4081 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4082 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4083 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4084 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4085
mbed_official 133:d4dda5c437f0 4086 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
mbed_official 133:d4dda5c437f0 4087 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4088 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4089 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4090 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4091 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4092 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4093 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4094 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4095
mbed_official 133:d4dda5c437f0 4096 /****************** Bit definition for FSMC_PMEM4 register ******************/
mbed_official 133:d4dda5c437f0 4097 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
mbed_official 133:d4dda5c437f0 4098 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4099 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4100 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4101 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4102 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4103 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4104 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4105 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4106
mbed_official 133:d4dda5c437f0 4107 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
mbed_official 133:d4dda5c437f0 4108 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4109 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4110 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4111 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4112 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4113 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4114 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4115 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4116
mbed_official 133:d4dda5c437f0 4117 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
mbed_official 133:d4dda5c437f0 4118 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4119 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4120 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4121 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4122 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4123 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4124 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4125 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4126
mbed_official 133:d4dda5c437f0 4127 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
mbed_official 133:d4dda5c437f0 4128 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4129 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4130 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4131 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4132 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4133 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4134 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4135 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4136
mbed_official 133:d4dda5c437f0 4137 /****************** Bit definition for FSMC_PATT2 register ******************/
mbed_official 133:d4dda5c437f0 4138 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
mbed_official 133:d4dda5c437f0 4139 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4140 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4141 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4142 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4143 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4144 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4145 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4146 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4147
mbed_official 133:d4dda5c437f0 4148 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
mbed_official 133:d4dda5c437f0 4149 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4150 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4151 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4152 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4153 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4154 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4155 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4156 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4157
mbed_official 133:d4dda5c437f0 4158 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
mbed_official 133:d4dda5c437f0 4159 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4160 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4161 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4162 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4163 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4164 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4165 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4166 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4167
mbed_official 133:d4dda5c437f0 4168 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
mbed_official 133:d4dda5c437f0 4169 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4170 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4171 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4172 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4173 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4174 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4175 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4176 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4177
mbed_official 133:d4dda5c437f0 4178 /****************** Bit definition for FSMC_PATT3 register ******************/
mbed_official 133:d4dda5c437f0 4179 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
mbed_official 133:d4dda5c437f0 4180 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4181 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4182 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4183 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4184 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4185 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4186 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4187 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4188
mbed_official 133:d4dda5c437f0 4189 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
mbed_official 133:d4dda5c437f0 4190 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4191 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4192 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4193 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4194 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4195 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4196 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4197 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4198
mbed_official 133:d4dda5c437f0 4199 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
mbed_official 133:d4dda5c437f0 4200 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4201 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4202 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4203 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4204 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4205 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4206 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4207 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4208
mbed_official 133:d4dda5c437f0 4209 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
mbed_official 133:d4dda5c437f0 4210 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4211 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4212 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4213 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4214 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4215 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4216 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4217 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4218
mbed_official 133:d4dda5c437f0 4219 /****************** Bit definition for FSMC_PATT4 register ******************/
mbed_official 133:d4dda5c437f0 4220 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
mbed_official 133:d4dda5c437f0 4221 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4222 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4223 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4224 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4225 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4226 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4227 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4228 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4229
mbed_official 133:d4dda5c437f0 4230 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
mbed_official 133:d4dda5c437f0 4231 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4232 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4233 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4234 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4235 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4236 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4237 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4238 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4239
mbed_official 133:d4dda5c437f0 4240 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
mbed_official 133:d4dda5c437f0 4241 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4242 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4243 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4244 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4245 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4246 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4247 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4248 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4249
mbed_official 133:d4dda5c437f0 4250 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
mbed_official 133:d4dda5c437f0 4251 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4252 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4253 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4254 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4255 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4256 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4257 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4258 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4259
mbed_official 133:d4dda5c437f0 4260 /****************** Bit definition for FSMC_PIO4 register *******************/
mbed_official 133:d4dda5c437f0 4261 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
mbed_official 133:d4dda5c437f0 4262 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4263 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4264 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4265 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4266 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4267 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4268 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4269 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4270
mbed_official 133:d4dda5c437f0 4271 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
mbed_official 133:d4dda5c437f0 4272 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4273 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4274 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4275 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4276 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4277 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4278 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4279 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4280
mbed_official 133:d4dda5c437f0 4281 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
mbed_official 133:d4dda5c437f0 4282 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4283 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4284 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4285 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4286 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4287 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4288 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4289 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4290
mbed_official 133:d4dda5c437f0 4291 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
mbed_official 133:d4dda5c437f0 4292 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4293 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4294 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4295 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4296 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4297 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4298 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4299 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4300
mbed_official 133:d4dda5c437f0 4301 /****************** Bit definition for FSMC_ECCR2 register ******************/
mbed_official 133:d4dda5c437f0 4302 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
mbed_official 133:d4dda5c437f0 4303
mbed_official 133:d4dda5c437f0 4304 /****************** Bit definition for FSMC_ECCR3 register ******************/
mbed_official 133:d4dda5c437f0 4305 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
mbed_official 133:d4dda5c437f0 4306
mbed_official 133:d4dda5c437f0 4307 /******************************************************************************/
mbed_official 133:d4dda5c437f0 4308 /* */
mbed_official 133:d4dda5c437f0 4309 /* General Purpose I/O */
mbed_official 133:d4dda5c437f0 4310 /* */
mbed_official 133:d4dda5c437f0 4311 /******************************************************************************/
mbed_official 133:d4dda5c437f0 4312 /****************** Bits definition for GPIO_MODER register *****************/
mbed_official 133:d4dda5c437f0 4313 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 133:d4dda5c437f0 4314 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 4315 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 4316
mbed_official 133:d4dda5c437f0 4317 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 133:d4dda5c437f0 4318 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 4319 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 4320
mbed_official 133:d4dda5c437f0 4321 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 133:d4dda5c437f0 4322 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 4323 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 4324
mbed_official 133:d4dda5c437f0 4325 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 133:d4dda5c437f0 4326 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 4327 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 4328
mbed_official 133:d4dda5c437f0 4329 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 133:d4dda5c437f0 4330 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 4331 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 4332
mbed_official 133:d4dda5c437f0 4333 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 133:d4dda5c437f0 4334 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 4335 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 4336
mbed_official 133:d4dda5c437f0 4337 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 133:d4dda5c437f0 4338 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 4339 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 4340
mbed_official 133:d4dda5c437f0 4341 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 133:d4dda5c437f0 4342 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 4343 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 4344
mbed_official 133:d4dda5c437f0 4345 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 133:d4dda5c437f0 4346 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 4347 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 4348
mbed_official 133:d4dda5c437f0 4349 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 133:d4dda5c437f0 4350 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 4351 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 4352
mbed_official 133:d4dda5c437f0 4353 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 133:d4dda5c437f0 4354 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 4355 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 4356
mbed_official 133:d4dda5c437f0 4357 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 133:d4dda5c437f0 4358 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 4359 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 4360
mbed_official 133:d4dda5c437f0 4361 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 133:d4dda5c437f0 4362 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 4363 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 4364
mbed_official 133:d4dda5c437f0 4365 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 133:d4dda5c437f0 4366 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 4367 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 4368
mbed_official 133:d4dda5c437f0 4369 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 133:d4dda5c437f0 4370 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 133:d4dda5c437f0 4371 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 4372
mbed_official 133:d4dda5c437f0 4373 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 133:d4dda5c437f0 4374 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 133:d4dda5c437f0 4375 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 133:d4dda5c437f0 4376
mbed_official 133:d4dda5c437f0 4377 /****************** Bits definition for GPIO_OTYPER register ****************/
mbed_official 133:d4dda5c437f0 4378 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 4379 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 4380 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 4381 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 4382 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 4383 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 4384 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 4385 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 4386 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 4387 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 4388 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 4389 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 4390 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 4391 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 4392 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 4393 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 4394
mbed_official 133:d4dda5c437f0 4395 /****************** Bits definition for GPIO_OSPEEDR register ***************/
mbed_official 133:d4dda5c437f0 4396 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 133:d4dda5c437f0 4397 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 4398 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 4399
mbed_official 133:d4dda5c437f0 4400 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 133:d4dda5c437f0 4401 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 4402 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 4403
mbed_official 133:d4dda5c437f0 4404 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 133:d4dda5c437f0 4405 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 4406 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 4407
mbed_official 133:d4dda5c437f0 4408 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 133:d4dda5c437f0 4409 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 4410 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 4411
mbed_official 133:d4dda5c437f0 4412 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 133:d4dda5c437f0 4413 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 4414 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 4415
mbed_official 133:d4dda5c437f0 4416 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 133:d4dda5c437f0 4417 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 4418 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 4419
mbed_official 133:d4dda5c437f0 4420 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 133:d4dda5c437f0 4421 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 4422 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 4423
mbed_official 133:d4dda5c437f0 4424 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 133:d4dda5c437f0 4425 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 4426 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 4427
mbed_official 133:d4dda5c437f0 4428 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 133:d4dda5c437f0 4429 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 4430 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 4431
mbed_official 133:d4dda5c437f0 4432 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 133:d4dda5c437f0 4433 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 4434 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 4435
mbed_official 133:d4dda5c437f0 4436 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 133:d4dda5c437f0 4437 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 4438 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 4439
mbed_official 133:d4dda5c437f0 4440 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 133:d4dda5c437f0 4441 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 4442 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 4443
mbed_official 133:d4dda5c437f0 4444 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 133:d4dda5c437f0 4445 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 4446 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 4447
mbed_official 133:d4dda5c437f0 4448 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 133:d4dda5c437f0 4449 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 4450 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 4451
mbed_official 133:d4dda5c437f0 4452 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 133:d4dda5c437f0 4453 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 133:d4dda5c437f0 4454 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 4455
mbed_official 133:d4dda5c437f0 4456 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 133:d4dda5c437f0 4457 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 133:d4dda5c437f0 4458 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 133:d4dda5c437f0 4459
mbed_official 133:d4dda5c437f0 4460 /****************** Bits definition for GPIO_PUPDR register *****************/
mbed_official 133:d4dda5c437f0 4461 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 133:d4dda5c437f0 4462 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 4463 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 4464
mbed_official 133:d4dda5c437f0 4465 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 133:d4dda5c437f0 4466 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 4467 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 4468
mbed_official 133:d4dda5c437f0 4469 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 133:d4dda5c437f0 4470 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 4471 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 4472
mbed_official 133:d4dda5c437f0 4473 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 133:d4dda5c437f0 4474 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 4475 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 4476
mbed_official 133:d4dda5c437f0 4477 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 133:d4dda5c437f0 4478 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 4479 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 4480
mbed_official 133:d4dda5c437f0 4481 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 133:d4dda5c437f0 4482 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 4483 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 4484
mbed_official 133:d4dda5c437f0 4485 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 133:d4dda5c437f0 4486 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 4487 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 4488
mbed_official 133:d4dda5c437f0 4489 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 133:d4dda5c437f0 4490 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 4491 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 4492
mbed_official 133:d4dda5c437f0 4493 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 133:d4dda5c437f0 4494 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 4495 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 4496
mbed_official 133:d4dda5c437f0 4497 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 133:d4dda5c437f0 4498 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 4499 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 4500
mbed_official 133:d4dda5c437f0 4501 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 133:d4dda5c437f0 4502 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 4503 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 4504
mbed_official 133:d4dda5c437f0 4505 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 133:d4dda5c437f0 4506 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 4507 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 4508
mbed_official 133:d4dda5c437f0 4509 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 133:d4dda5c437f0 4510 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 4511 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 4512
mbed_official 133:d4dda5c437f0 4513 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 133:d4dda5c437f0 4514 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 4515 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 4516
mbed_official 133:d4dda5c437f0 4517 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 133:d4dda5c437f0 4518 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 133:d4dda5c437f0 4519 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 4520
mbed_official 133:d4dda5c437f0 4521 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 133:d4dda5c437f0 4522 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 133:d4dda5c437f0 4523 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 133:d4dda5c437f0 4524
mbed_official 133:d4dda5c437f0 4525 /****************** Bits definition for GPIO_IDR register *******************/
mbed_official 133:d4dda5c437f0 4526 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 4527 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 4528 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 4529 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 4530 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 4531 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 4532 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 4533 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 4534 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 4535 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 4536 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 4537 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 4538 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 4539 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 4540 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 4541 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 4542 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
mbed_official 133:d4dda5c437f0 4543 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
mbed_official 133:d4dda5c437f0 4544 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
mbed_official 133:d4dda5c437f0 4545 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
mbed_official 133:d4dda5c437f0 4546 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
mbed_official 133:d4dda5c437f0 4547 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
mbed_official 133:d4dda5c437f0 4548 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
mbed_official 133:d4dda5c437f0 4549 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
mbed_official 133:d4dda5c437f0 4550 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
mbed_official 133:d4dda5c437f0 4551 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
mbed_official 133:d4dda5c437f0 4552 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
mbed_official 133:d4dda5c437f0 4553 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
mbed_official 133:d4dda5c437f0 4554 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
mbed_official 133:d4dda5c437f0 4555 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
mbed_official 133:d4dda5c437f0 4556 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
mbed_official 133:d4dda5c437f0 4557 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
mbed_official 133:d4dda5c437f0 4558 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
mbed_official 133:d4dda5c437f0 4559
mbed_official 133:d4dda5c437f0 4560 /****************** Bits definition for GPIO_ODR register *******************/
mbed_official 133:d4dda5c437f0 4561 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 4562 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 4563 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 4564 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 4565 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 4566 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 4567 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 4568 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 4569 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 4570 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 4571 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 4572 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 4573 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 4574 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 4575 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 4576 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 4577 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
mbed_official 133:d4dda5c437f0 4578 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
mbed_official 133:d4dda5c437f0 4579 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
mbed_official 133:d4dda5c437f0 4580 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
mbed_official 133:d4dda5c437f0 4581 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
mbed_official 133:d4dda5c437f0 4582 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
mbed_official 133:d4dda5c437f0 4583 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
mbed_official 133:d4dda5c437f0 4584 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
mbed_official 133:d4dda5c437f0 4585 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
mbed_official 133:d4dda5c437f0 4586 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
mbed_official 133:d4dda5c437f0 4587 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
mbed_official 133:d4dda5c437f0 4588 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
mbed_official 133:d4dda5c437f0 4589 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
mbed_official 133:d4dda5c437f0 4590 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
mbed_official 133:d4dda5c437f0 4591 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
mbed_official 133:d4dda5c437f0 4592 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
mbed_official 133:d4dda5c437f0 4593 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
mbed_official 133:d4dda5c437f0 4594
mbed_official 133:d4dda5c437f0 4595 /****************** Bits definition for GPIO_BSRR register ******************/
mbed_official 133:d4dda5c437f0 4596 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 4597 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 4598 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 4599 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 4600 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 4601 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 4602 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 4603 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 4604 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 4605 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 4606 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 4607 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 4608 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 4609 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 4610 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 4611 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 4612 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 4613 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 4614 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 4615 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 4616 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 4617 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 4618 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 4619 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 4620 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 4621 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 4622 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 4623 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 4624 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 133:d4dda5c437f0 4625 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 4626 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 133:d4dda5c437f0 4627 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 133:d4dda5c437f0 4628
mbed_official 242:7074e42da0b2 4629 /****************** Bit definition for GPIO_LCKR register *********************/
mbed_official 242:7074e42da0b2 4630 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 242:7074e42da0b2 4631 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 242:7074e42da0b2 4632 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 242:7074e42da0b2 4633 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 242:7074e42da0b2 4634 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 242:7074e42da0b2 4635 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 242:7074e42da0b2 4636 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 242:7074e42da0b2 4637 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 242:7074e42da0b2 4638 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 242:7074e42da0b2 4639 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 242:7074e42da0b2 4640 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 242:7074e42da0b2 4641 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 242:7074e42da0b2 4642 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 242:7074e42da0b2 4643 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 242:7074e42da0b2 4644 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 242:7074e42da0b2 4645 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 242:7074e42da0b2 4646 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 242:7074e42da0b2 4647
mbed_official 133:d4dda5c437f0 4648 /******************************************************************************/
mbed_official 133:d4dda5c437f0 4649 /* */
mbed_official 133:d4dda5c437f0 4650 /* Inter-integrated Circuit Interface */
mbed_official 133:d4dda5c437f0 4651 /* */
mbed_official 133:d4dda5c437f0 4652 /******************************************************************************/
mbed_official 133:d4dda5c437f0 4653 /******************* Bit definition for I2C_CR1 register ********************/
mbed_official 133:d4dda5c437f0 4654 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
mbed_official 133:d4dda5c437f0 4655 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
mbed_official 133:d4dda5c437f0 4656 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
mbed_official 133:d4dda5c437f0 4657 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
mbed_official 133:d4dda5c437f0 4658 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
mbed_official 133:d4dda5c437f0 4659 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
mbed_official 133:d4dda5c437f0 4660 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
mbed_official 133:d4dda5c437f0 4661 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
mbed_official 133:d4dda5c437f0 4662 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
mbed_official 133:d4dda5c437f0 4663 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
mbed_official 133:d4dda5c437f0 4664 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
mbed_official 133:d4dda5c437f0 4665 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
mbed_official 133:d4dda5c437f0 4666 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
mbed_official 133:d4dda5c437f0 4667 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
mbed_official 133:d4dda5c437f0 4668
mbed_official 133:d4dda5c437f0 4669 /******************* Bit definition for I2C_CR2 register ********************/
mbed_official 133:d4dda5c437f0 4670 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
mbed_official 133:d4dda5c437f0 4671 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4672 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4673 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4674 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4675 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4676 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4677
mbed_official 133:d4dda5c437f0 4678 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
mbed_official 133:d4dda5c437f0 4679 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
mbed_official 133:d4dda5c437f0 4680 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
mbed_official 133:d4dda5c437f0 4681 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
mbed_official 133:d4dda5c437f0 4682 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
mbed_official 133:d4dda5c437f0 4683
mbed_official 133:d4dda5c437f0 4684 /******************* Bit definition for I2C_OAR1 register *******************/
mbed_official 133:d4dda5c437f0 4685 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
mbed_official 133:d4dda5c437f0 4686 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
mbed_official 133:d4dda5c437f0 4687
mbed_official 133:d4dda5c437f0 4688 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4689 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4690 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4691 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4692 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4693 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4694 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4695 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4696 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
mbed_official 133:d4dda5c437f0 4697 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
mbed_official 133:d4dda5c437f0 4698
mbed_official 133:d4dda5c437f0 4699 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
mbed_official 133:d4dda5c437f0 4700
mbed_official 133:d4dda5c437f0 4701 /******************* Bit definition for I2C_OAR2 register *******************/
mbed_official 133:d4dda5c437f0 4702 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
mbed_official 133:d4dda5c437f0 4703 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
mbed_official 133:d4dda5c437f0 4704
mbed_official 133:d4dda5c437f0 4705 /******************** Bit definition for I2C_DR register ********************/
mbed_official 133:d4dda5c437f0 4706 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
mbed_official 133:d4dda5c437f0 4707
mbed_official 133:d4dda5c437f0 4708 /******************* Bit definition for I2C_SR1 register ********************/
mbed_official 133:d4dda5c437f0 4709 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
mbed_official 133:d4dda5c437f0 4710 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
mbed_official 133:d4dda5c437f0 4711 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
mbed_official 133:d4dda5c437f0 4712 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
mbed_official 133:d4dda5c437f0 4713 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
mbed_official 133:d4dda5c437f0 4714 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
mbed_official 133:d4dda5c437f0 4715 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
mbed_official 133:d4dda5c437f0 4716 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
mbed_official 133:d4dda5c437f0 4717 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
mbed_official 133:d4dda5c437f0 4718 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
mbed_official 133:d4dda5c437f0 4719 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
mbed_official 133:d4dda5c437f0 4720 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
mbed_official 133:d4dda5c437f0 4721 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
mbed_official 133:d4dda5c437f0 4722 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
mbed_official 133:d4dda5c437f0 4723
mbed_official 133:d4dda5c437f0 4724 /******************* Bit definition for I2C_SR2 register ********************/
mbed_official 133:d4dda5c437f0 4725 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
mbed_official 133:d4dda5c437f0 4726 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
mbed_official 133:d4dda5c437f0 4727 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
mbed_official 133:d4dda5c437f0 4728 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
mbed_official 133:d4dda5c437f0 4729 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
mbed_official 133:d4dda5c437f0 4730 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
mbed_official 133:d4dda5c437f0 4731 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
mbed_official 133:d4dda5c437f0 4732 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
mbed_official 133:d4dda5c437f0 4733
mbed_official 133:d4dda5c437f0 4734 /******************* Bit definition for I2C_CCR register ********************/
mbed_official 133:d4dda5c437f0 4735 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
mbed_official 133:d4dda5c437f0 4736 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
mbed_official 133:d4dda5c437f0 4737 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
mbed_official 133:d4dda5c437f0 4738
mbed_official 133:d4dda5c437f0 4739 /****************** Bit definition for I2C_TRISE register *******************/
mbed_official 133:d4dda5c437f0 4740 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
mbed_official 133:d4dda5c437f0 4741
mbed_official 133:d4dda5c437f0 4742 /****************** Bit definition for I2C_FLTR register *******************/
mbed_official 133:d4dda5c437f0 4743 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
mbed_official 133:d4dda5c437f0 4744 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
mbed_official 133:d4dda5c437f0 4745
mbed_official 133:d4dda5c437f0 4746 /******************************************************************************/
mbed_official 133:d4dda5c437f0 4747 /* */
mbed_official 133:d4dda5c437f0 4748 /* Independent WATCHDOG */
mbed_official 133:d4dda5c437f0 4749 /* */
mbed_official 133:d4dda5c437f0 4750 /******************************************************************************/
mbed_official 133:d4dda5c437f0 4751 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 133:d4dda5c437f0 4752 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
mbed_official 133:d4dda5c437f0 4753
mbed_official 133:d4dda5c437f0 4754 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 133:d4dda5c437f0 4755 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
mbed_official 133:d4dda5c437f0 4756 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4757 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4758 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4759
mbed_official 133:d4dda5c437f0 4760 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 133:d4dda5c437f0 4761 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
mbed_official 133:d4dda5c437f0 4762
mbed_official 133:d4dda5c437f0 4763 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 133:d4dda5c437f0 4764 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
mbed_official 133:d4dda5c437f0 4765 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
mbed_official 133:d4dda5c437f0 4766
mbed_official 133:d4dda5c437f0 4767
mbed_official 133:d4dda5c437f0 4768 /******************************************************************************/
mbed_official 133:d4dda5c437f0 4769 /* */
mbed_official 133:d4dda5c437f0 4770 /* Power Control */
mbed_official 133:d4dda5c437f0 4771 /* */
mbed_official 133:d4dda5c437f0 4772 /******************************************************************************/
mbed_official 133:d4dda5c437f0 4773 /******************** Bit definition for PWR_CR register ********************/
mbed_official 133:d4dda5c437f0 4774 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
mbed_official 133:d4dda5c437f0 4775 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 133:d4dda5c437f0 4776 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 133:d4dda5c437f0 4777 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 133:d4dda5c437f0 4778 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 133:d4dda5c437f0 4779
mbed_official 133:d4dda5c437f0 4780 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 133:d4dda5c437f0 4781 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 133:d4dda5c437f0 4782 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 133:d4dda5c437f0 4783 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 133:d4dda5c437f0 4784
mbed_official 133:d4dda5c437f0 4785 /*!< PVD level configuration */
mbed_official 133:d4dda5c437f0 4786 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 133:d4dda5c437f0 4787 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 133:d4dda5c437f0 4788 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 133:d4dda5c437f0 4789 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 133:d4dda5c437f0 4790 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 133:d4dda5c437f0 4791 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 133:d4dda5c437f0 4792 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 133:d4dda5c437f0 4793 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 133:d4dda5c437f0 4794
mbed_official 532:fe11edbda85c 4795 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 532:fe11edbda85c 4796 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
mbed_official 532:fe11edbda85c 4797 #define PWR_CR_VOS ((uint32_t)0x00004000) /*!< VOS bit (Regulator voltage scaling output selection) */
mbed_official 133:d4dda5c437f0 4798
mbed_official 133:d4dda5c437f0 4799 /* Legacy define */
mbed_official 133:d4dda5c437f0 4800 #define PWR_CR_PMODE PWR_CR_VOS
mbed_official 133:d4dda5c437f0 4801
mbed_official 133:d4dda5c437f0 4802 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 133:d4dda5c437f0 4803 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 133:d4dda5c437f0 4804 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 133:d4dda5c437f0 4805 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 133:d4dda5c437f0 4806 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
mbed_official 133:d4dda5c437f0 4807 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
mbed_official 133:d4dda5c437f0 4808 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
mbed_official 133:d4dda5c437f0 4809 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
mbed_official 133:d4dda5c437f0 4810
mbed_official 133:d4dda5c437f0 4811 /* Legacy define */
mbed_official 133:d4dda5c437f0 4812 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
mbed_official 133:d4dda5c437f0 4813
mbed_official 133:d4dda5c437f0 4814 /******************************************************************************/
mbed_official 133:d4dda5c437f0 4815 /* */
mbed_official 133:d4dda5c437f0 4816 /* Reset and Clock Control */
mbed_official 133:d4dda5c437f0 4817 /* */
mbed_official 133:d4dda5c437f0 4818 /******************************************************************************/
mbed_official 133:d4dda5c437f0 4819 /******************** Bit definition for RCC_CR register ********************/
mbed_official 133:d4dda5c437f0 4820 #define RCC_CR_HSION ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 4821 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 4822
mbed_official 133:d4dda5c437f0 4823 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
mbed_official 133:d4dda5c437f0 4824 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4825 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4826 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4827 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4828 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4829
mbed_official 133:d4dda5c437f0 4830 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
mbed_official 133:d4dda5c437f0 4831 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
mbed_official 133:d4dda5c437f0 4832 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
mbed_official 133:d4dda5c437f0 4833 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
mbed_official 133:d4dda5c437f0 4834 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
mbed_official 133:d4dda5c437f0 4835 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
mbed_official 133:d4dda5c437f0 4836 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
mbed_official 133:d4dda5c437f0 4837 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
mbed_official 133:d4dda5c437f0 4838 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
mbed_official 133:d4dda5c437f0 4839
mbed_official 133:d4dda5c437f0 4840 #define RCC_CR_HSEON ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 4841 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 4842 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 4843 #define RCC_CR_CSSON ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 4844 #define RCC_CR_PLLON ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 4845 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 4846 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 4847 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 4848
mbed_official 133:d4dda5c437f0 4849 /******************** Bit definition for RCC_PLLCFGR register ***************/
mbed_official 133:d4dda5c437f0 4850 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
mbed_official 133:d4dda5c437f0 4851 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 4852 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 4853 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 4854 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 4855 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 4856 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 4857
mbed_official 133:d4dda5c437f0 4858 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
mbed_official 133:d4dda5c437f0 4859 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 4860 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 4861 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 4862 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 4863 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 4864 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 4865 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 4866 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 4867 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 4868
mbed_official 133:d4dda5c437f0 4869 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
mbed_official 133:d4dda5c437f0 4870 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 4871 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 4872
mbed_official 133:d4dda5c437f0 4873 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 4874 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 4875 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 4876
mbed_official 133:d4dda5c437f0 4877 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
mbed_official 133:d4dda5c437f0 4878 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 4879 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 4880 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 4881 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 4882
mbed_official 133:d4dda5c437f0 4883 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 133:d4dda5c437f0 4884 /*!< SW configuration */
mbed_official 133:d4dda5c437f0 4885 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 133:d4dda5c437f0 4886 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 133:d4dda5c437f0 4887 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 133:d4dda5c437f0 4888
mbed_official 133:d4dda5c437f0 4889 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 133:d4dda5c437f0 4890 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 133:d4dda5c437f0 4891 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 133:d4dda5c437f0 4892
mbed_official 133:d4dda5c437f0 4893 /*!< SWS configuration */
mbed_official 133:d4dda5c437f0 4894 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 133:d4dda5c437f0 4895 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 133:d4dda5c437f0 4896 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 133:d4dda5c437f0 4897
mbed_official 133:d4dda5c437f0 4898 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 133:d4dda5c437f0 4899 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 133:d4dda5c437f0 4900 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 133:d4dda5c437f0 4901
mbed_official 133:d4dda5c437f0 4902 /*!< HPRE configuration */
mbed_official 133:d4dda5c437f0 4903 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 133:d4dda5c437f0 4904 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 133:d4dda5c437f0 4905 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 133:d4dda5c437f0 4906 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 133:d4dda5c437f0 4907 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 133:d4dda5c437f0 4908
mbed_official 133:d4dda5c437f0 4909 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 133:d4dda5c437f0 4910 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 133:d4dda5c437f0 4911 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 133:d4dda5c437f0 4912 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 133:d4dda5c437f0 4913 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 133:d4dda5c437f0 4914 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 133:d4dda5c437f0 4915 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 133:d4dda5c437f0 4916 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 133:d4dda5c437f0 4917 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 133:d4dda5c437f0 4918
mbed_official 133:d4dda5c437f0 4919 /*!< PPRE1 configuration */
mbed_official 133:d4dda5c437f0 4920 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 133:d4dda5c437f0 4921 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 133:d4dda5c437f0 4922 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 133:d4dda5c437f0 4923 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 133:d4dda5c437f0 4924
mbed_official 133:d4dda5c437f0 4925 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 133:d4dda5c437f0 4926 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
mbed_official 133:d4dda5c437f0 4927 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
mbed_official 133:d4dda5c437f0 4928 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
mbed_official 133:d4dda5c437f0 4929 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
mbed_official 133:d4dda5c437f0 4930
mbed_official 133:d4dda5c437f0 4931 /*!< PPRE2 configuration */
mbed_official 133:d4dda5c437f0 4932 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 133:d4dda5c437f0 4933 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
mbed_official 133:d4dda5c437f0 4934 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
mbed_official 133:d4dda5c437f0 4935 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
mbed_official 133:d4dda5c437f0 4936
mbed_official 133:d4dda5c437f0 4937 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 133:d4dda5c437f0 4938 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
mbed_official 133:d4dda5c437f0 4939 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
mbed_official 133:d4dda5c437f0 4940 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
mbed_official 133:d4dda5c437f0 4941 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
mbed_official 133:d4dda5c437f0 4942
mbed_official 133:d4dda5c437f0 4943 /*!< RTCPRE configuration */
mbed_official 133:d4dda5c437f0 4944 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
mbed_official 133:d4dda5c437f0 4945 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 4946 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 4947 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 4948 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 4949 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 4950
mbed_official 133:d4dda5c437f0 4951 /*!< MCO1 configuration */
mbed_official 133:d4dda5c437f0 4952 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
mbed_official 133:d4dda5c437f0 4953 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 4954 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 4955
mbed_official 133:d4dda5c437f0 4956 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 4957
mbed_official 133:d4dda5c437f0 4958 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
mbed_official 133:d4dda5c437f0 4959 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 4960 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 4961 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 4962
mbed_official 133:d4dda5c437f0 4963 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
mbed_official 133:d4dda5c437f0 4964 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 4965 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
mbed_official 133:d4dda5c437f0 4966 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 4967
mbed_official 133:d4dda5c437f0 4968 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
mbed_official 133:d4dda5c437f0 4969 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
mbed_official 133:d4dda5c437f0 4970 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
mbed_official 133:d4dda5c437f0 4971
mbed_official 133:d4dda5c437f0 4972 /******************** Bit definition for RCC_CIR register *******************/
mbed_official 133:d4dda5c437f0 4973 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 4974 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 4975 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 4976 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 4977 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 4978 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 4979
mbed_official 133:d4dda5c437f0 4980 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 4981 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 4982 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 4983 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 4984 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 4985 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 4986 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 4987
mbed_official 133:d4dda5c437f0 4988 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 4989 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 4990 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 4991 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 4992 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 4993 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 4994
mbed_official 133:d4dda5c437f0 4995 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 4996
mbed_official 133:d4dda5c437f0 4997 /******************** Bit definition for RCC_AHB1RSTR register **************/
mbed_official 133:d4dda5c437f0 4998 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 4999 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5000 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5001 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5002 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5003 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5004 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5005 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5006 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5007 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5008 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 5009 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 5010 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
mbed_official 532:fe11edbda85c 5011 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 5012
mbed_official 133:d4dda5c437f0 5013 /******************** Bit definition for RCC_AHB2RSTR register **************/
mbed_official 133:d4dda5c437f0 5014 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5015 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5016 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5017
mbed_official 133:d4dda5c437f0 5018 /******************** Bit definition for RCC_AHB3RSTR register **************/
mbed_official 133:d4dda5c437f0 5019
mbed_official 133:d4dda5c437f0 5020 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5021
mbed_official 133:d4dda5c437f0 5022 /******************** Bit definition for RCC_APB1RSTR register **************/
mbed_official 133:d4dda5c437f0 5023 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5024 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5025 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5026 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5027 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5028 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5029 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5030 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5031 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5032 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5033 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5034 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 5035 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 5036 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5037 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 5038 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 5039 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 5040 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 5041 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 5042 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 5043 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 5044 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
mbed_official 133:d4dda5c437f0 5045 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 5046
mbed_official 133:d4dda5c437f0 5047 /******************** Bit definition for RCC_APB2RSTR register **************/
mbed_official 133:d4dda5c437f0 5048 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5049 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5050 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5051 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5052 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5053 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5054 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5055 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5056 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 5057 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 5058 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5059
mbed_official 133:d4dda5c437f0 5060 /* Old SPI1RST bit definition, maintained for legacy purpose */
mbed_official 133:d4dda5c437f0 5061 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
mbed_official 133:d4dda5c437f0 5062
mbed_official 133:d4dda5c437f0 5063 /******************** Bit definition for RCC_AHB1ENR register ***************/
mbed_official 133:d4dda5c437f0 5064 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5065 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5066 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5067 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5068 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5069 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5070 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5071 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5072 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5073 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5074 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5075 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 5076 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 5077 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 5078
mbed_official 133:d4dda5c437f0 5079 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 5080 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 5081 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 5082 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
mbed_official 133:d4dda5c437f0 5083 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 5084 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
mbed_official 133:d4dda5c437f0 5085
mbed_official 133:d4dda5c437f0 5086 /******************** Bit definition for RCC_AHB2ENR register ***************/
mbed_official 133:d4dda5c437f0 5087 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5088 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5089 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5090
mbed_official 133:d4dda5c437f0 5091 /******************** Bit definition for RCC_AHB3ENR register ***************/
mbed_official 133:d4dda5c437f0 5092
mbed_official 133:d4dda5c437f0 5093 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5094
mbed_official 133:d4dda5c437f0 5095 /******************** Bit definition for RCC_APB1ENR register ***************/
mbed_official 133:d4dda5c437f0 5096 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5097 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5098 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5099 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5100 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5101 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5102 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5103 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5104 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5105 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5106 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5107 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 5108 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 5109 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5110 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 5111 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 5112 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 5113 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 5114 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 5115 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 5116 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 5117 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
mbed_official 133:d4dda5c437f0 5118 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 5119
mbed_official 133:d4dda5c437f0 5120 /******************** Bit definition for RCC_APB2ENR register ***************/
mbed_official 133:d4dda5c437f0 5121 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5122 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5123 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5124 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5125 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5126 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 5127 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 5128 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5129 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5130 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5131 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 5132 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 5133 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5134 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 5135 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 5136
mbed_official 133:d4dda5c437f0 5137 /******************** Bit definition for RCC_AHB1LPENR register *************/
mbed_official 133:d4dda5c437f0 5138 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5139 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5140 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5141 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5142 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5143 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5144 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5145 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5146 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5147 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5148 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 5149 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 5150 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 5151 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5152 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 5153 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 5154 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 5155 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 5156 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 5157 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
mbed_official 133:d4dda5c437f0 5158 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 5159 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
mbed_official 133:d4dda5c437f0 5160
mbed_official 133:d4dda5c437f0 5161 /******************** Bit definition for RCC_AHB2LPENR register *************/
mbed_official 133:d4dda5c437f0 5162 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5163 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5164 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5165
mbed_official 133:d4dda5c437f0 5166 /******************** Bit definition for RCC_AHB3LPENR register *************/
mbed_official 133:d4dda5c437f0 5167
mbed_official 133:d4dda5c437f0 5168 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5169
mbed_official 133:d4dda5c437f0 5170 /******************** Bit definition for RCC_APB1LPENR register *************/
mbed_official 133:d4dda5c437f0 5171 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5172 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5173 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5174 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5175 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5176 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5177 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5178 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5179 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5180 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5181 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5182 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 5183 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 5184 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5185 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 5186 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 5187 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 5188 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 5189 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 5190 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 5191 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 5192 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
mbed_official 133:d4dda5c437f0 5193 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 5194
mbed_official 133:d4dda5c437f0 5195 /******************** Bit definition for RCC_APB2LPENR register *************/
mbed_official 133:d4dda5c437f0 5196 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5197 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5198 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5199 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5200 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5201 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 5202 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 5203 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5204 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5205 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5206 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 5207 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 5208 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5209
mbed_official 133:d4dda5c437f0 5210 /******************** Bit definition for RCC_BDCR register ******************/
mbed_official 133:d4dda5c437f0 5211 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5212 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5213 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5214
mbed_official 133:d4dda5c437f0 5215 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
mbed_official 133:d4dda5c437f0 5216 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5217 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 5218
mbed_official 133:d4dda5c437f0 5219 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 5220 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 5221
mbed_official 133:d4dda5c437f0 5222 /******************** Bit definition for RCC_CSR register *******************/
mbed_official 133:d4dda5c437f0 5223 #define RCC_CSR_LSION ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5224 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5225 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 5226 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 5227 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 5228 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 5229 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
mbed_official 133:d4dda5c437f0 5230 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 5231 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
mbed_official 133:d4dda5c437f0 5232 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
mbed_official 133:d4dda5c437f0 5233
mbed_official 133:d4dda5c437f0 5234 /******************** Bit definition for RCC_SSCGR register *****************/
mbed_official 133:d4dda5c437f0 5235 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
mbed_official 133:d4dda5c437f0 5236 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
mbed_official 133:d4dda5c437f0 5237 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
mbed_official 133:d4dda5c437f0 5238 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
mbed_official 133:d4dda5c437f0 5239
mbed_official 133:d4dda5c437f0 5240 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
mbed_official 133:d4dda5c437f0 5241 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
mbed_official 133:d4dda5c437f0 5242 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5243 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5244 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5245 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 5246 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 5247 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5248 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5249 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 5250 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5251
mbed_official 133:d4dda5c437f0 5252 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
mbed_official 133:d4dda5c437f0 5253 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
mbed_official 133:d4dda5c437f0 5254 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 5255 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
mbed_official 133:d4dda5c437f0 5256
mbed_official 133:d4dda5c437f0 5257 /******************************************************************************/
mbed_official 133:d4dda5c437f0 5258 /* */
mbed_official 133:d4dda5c437f0 5259 /* RNG */
mbed_official 133:d4dda5c437f0 5260 /* */
mbed_official 133:d4dda5c437f0 5261 /******************************************************************************/
mbed_official 133:d4dda5c437f0 5262 /******************** Bits definition for RNG_CR register *******************/
mbed_official 133:d4dda5c437f0 5263 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5264 #define RNG_CR_IE ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5265
mbed_official 133:d4dda5c437f0 5266 /******************** Bits definition for RNG_SR register *******************/
mbed_official 133:d4dda5c437f0 5267 #define RNG_SR_DRDY ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5268 #define RNG_SR_CECS ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5269 #define RNG_SR_SECS ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5270 #define RNG_SR_CEIS ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5271 #define RNG_SR_SEIS ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5272
mbed_official 133:d4dda5c437f0 5273 /******************************************************************************/
mbed_official 133:d4dda5c437f0 5274 /* */
mbed_official 133:d4dda5c437f0 5275 /* Real-Time Clock (RTC) */
mbed_official 133:d4dda5c437f0 5276 /* */
mbed_official 133:d4dda5c437f0 5277 /******************************************************************************/
mbed_official 133:d4dda5c437f0 5278 /******************** Bits definition for RTC_TR register *******************/
mbed_official 133:d4dda5c437f0 5279 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 5280 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 133:d4dda5c437f0 5281 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 5282 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 5283 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 133:d4dda5c437f0 5284 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 5285 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 5286 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5287 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 5288 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 133:d4dda5c437f0 5289 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5290 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 5291 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5292 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 133:d4dda5c437f0 5293 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5294 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 5295 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 5296 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5297 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 133:d4dda5c437f0 5298 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5299 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5300 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5301 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 133:d4dda5c437f0 5302 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5303 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5304 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5305 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5306
mbed_official 133:d4dda5c437f0 5307 /******************** Bits definition for RTC_DR register *******************/
mbed_official 133:d4dda5c437f0 5308 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 133:d4dda5c437f0 5309 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 5310 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 5311 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 5312 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 5313 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 133:d4dda5c437f0 5314 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 5315 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 5316 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5317 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 5318 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 133:d4dda5c437f0 5319 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 5320 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5321 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 5322 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5323 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 133:d4dda5c437f0 5324 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5325 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 5326 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 5327 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5328 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 133:d4dda5c437f0 5329 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5330 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5331 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 133:d4dda5c437f0 5332 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5333 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5334 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5335 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5336
mbed_official 133:d4dda5c437f0 5337 /******************** Bits definition for RTC_CR register *******************/
mbed_official 133:d4dda5c437f0 5338 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 5339 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 133:d4dda5c437f0 5340 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 5341 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 5342 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 5343 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 5344 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5345 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 5346 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 5347 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 5348 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5349 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 5350 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5351 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5352 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 5353 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 5354 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5355 #define RTC_CR_DCE ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5356 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5357 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5358 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5359 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5360 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 133:d4dda5c437f0 5361 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5362 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5363 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5364
mbed_official 133:d4dda5c437f0 5365 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 133:d4dda5c437f0 5366 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 5367 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 5368 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5369 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5370 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5371 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 5372 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 5373 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5374 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5375 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5376 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5377 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5378 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5379 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5380 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5381 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5382
mbed_official 133:d4dda5c437f0 5383 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 133:d4dda5c437f0 5384 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 613:bc40b8d2aec4 5385 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 133:d4dda5c437f0 5386
mbed_official 133:d4dda5c437f0 5387 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 133:d4dda5c437f0 5388 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 133:d4dda5c437f0 5389
mbed_official 133:d4dda5c437f0 5390 /******************** Bits definition for RTC_CALIBR register ***************/
mbed_official 133:d4dda5c437f0 5391 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5392 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
mbed_official 133:d4dda5c437f0 5393
mbed_official 133:d4dda5c437f0 5394 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 133:d4dda5c437f0 5395 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 133:d4dda5c437f0 5396 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 133:d4dda5c437f0 5397 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 133:d4dda5c437f0 5398 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 133:d4dda5c437f0 5399 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 5400 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 133:d4dda5c437f0 5401 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 5402 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 5403 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 5404 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 5405 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 5406 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 5407 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 133:d4dda5c437f0 5408 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 5409 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 5410 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 133:d4dda5c437f0 5411 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 5412 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 5413 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5414 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 5415 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 5416 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 133:d4dda5c437f0 5417 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5418 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 5419 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5420 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 133:d4dda5c437f0 5421 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5422 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 5423 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 5424 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5425 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5426 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 133:d4dda5c437f0 5427 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5428 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5429 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5430 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 133:d4dda5c437f0 5431 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5432 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5433 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5434 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5435
mbed_official 133:d4dda5c437f0 5436 /******************** Bits definition for RTC_ALRMBR register ***************/
mbed_official 133:d4dda5c437f0 5437 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
mbed_official 133:d4dda5c437f0 5438 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
mbed_official 133:d4dda5c437f0 5439 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
mbed_official 133:d4dda5c437f0 5440 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
mbed_official 133:d4dda5c437f0 5441 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
mbed_official 133:d4dda5c437f0 5442 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
mbed_official 133:d4dda5c437f0 5443 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 5444 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 5445 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 5446 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 5447 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 5448 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 5449 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
mbed_official 133:d4dda5c437f0 5450 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 5451 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 5452 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
mbed_official 133:d4dda5c437f0 5453 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 5454 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 5455 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5456 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 5457 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 5458 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
mbed_official 133:d4dda5c437f0 5459 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5460 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 5461 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5462 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
mbed_official 133:d4dda5c437f0 5463 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5464 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 5465 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 5466 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5467 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5468 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
mbed_official 133:d4dda5c437f0 5469 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5470 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5471 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5472 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
mbed_official 133:d4dda5c437f0 5473 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5474 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5475 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5476 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5477
mbed_official 133:d4dda5c437f0 5478 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 133:d4dda5c437f0 5479 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 133:d4dda5c437f0 5480
mbed_official 133:d4dda5c437f0 5481 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 133:d4dda5c437f0 5482 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 133:d4dda5c437f0 5483
mbed_official 133:d4dda5c437f0 5484 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 133:d4dda5c437f0 5485 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 133:d4dda5c437f0 5486 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 133:d4dda5c437f0 5487
mbed_official 133:d4dda5c437f0 5488 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 133:d4dda5c437f0 5489 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 5490 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 133:d4dda5c437f0 5491 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 5492 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 5493 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 133:d4dda5c437f0 5494 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 5495 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 5496 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5497 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 5498 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 133:d4dda5c437f0 5499 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5500 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 5501 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5502 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 133:d4dda5c437f0 5503 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5504 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 5505 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 5506 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5507 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 133:d4dda5c437f0 5508 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5509 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5510 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5511 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 133:d4dda5c437f0 5512 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5513 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5514 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5515 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5516
mbed_official 133:d4dda5c437f0 5517 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 133:d4dda5c437f0 5518 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 133:d4dda5c437f0 5519 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 5520 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5521 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 5522 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5523 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 133:d4dda5c437f0 5524 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5525 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 5526 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 5527 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5528 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 133:d4dda5c437f0 5529 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5530 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5531 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 133:d4dda5c437f0 5532 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5533 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5534 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5535 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5536
mbed_official 133:d4dda5c437f0 5537 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 133:d4dda5c437f0 5538 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 133:d4dda5c437f0 5539
mbed_official 133:d4dda5c437f0 5540 /******************** Bits definition for RTC_CAL register *****************/
mbed_official 133:d4dda5c437f0 5541 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 5542 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5543 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 5544 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 133:d4dda5c437f0 5545 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5546 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5547 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5548 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5549 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5550 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 5551 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 5552 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5553 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5554
mbed_official 133:d4dda5c437f0 5555 /******************** Bits definition for RTC_TAFCR register ****************/
mbed_official 133:d4dda5c437f0 5556 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 5557 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 5558 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 5559 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 133:d4dda5c437f0 5560 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 133:d4dda5c437f0 5561 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 133:d4dda5c437f0 5562 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 133:d4dda5c437f0 5563 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 133:d4dda5c437f0 5564 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 5565 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 5566 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 133:d4dda5c437f0 5567 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 5568 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 5569 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 5570 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 5571 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 5572 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 5573 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5574 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5575 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5576
mbed_official 133:d4dda5c437f0 5577 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 133:d4dda5c437f0 5578 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 133:d4dda5c437f0 5579 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 5580 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 5581 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 5582 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 5583 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 133:d4dda5c437f0 5584
mbed_official 133:d4dda5c437f0 5585 /******************** Bits definition for RTC_ALRMBSSR register *************/
mbed_official 133:d4dda5c437f0 5586 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 133:d4dda5c437f0 5587 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 5588 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 5589 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 5590 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 5591 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
mbed_official 133:d4dda5c437f0 5592
mbed_official 133:d4dda5c437f0 5593 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 133:d4dda5c437f0 5594 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5595
mbed_official 133:d4dda5c437f0 5596 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 133:d4dda5c437f0 5597 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5598
mbed_official 133:d4dda5c437f0 5599 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 133:d4dda5c437f0 5600 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5601
mbed_official 133:d4dda5c437f0 5602 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 133:d4dda5c437f0 5603 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5604
mbed_official 133:d4dda5c437f0 5605 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 133:d4dda5c437f0 5606 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5607
mbed_official 133:d4dda5c437f0 5608 /******************** Bits definition for RTC_BKP5R register ****************/
mbed_official 133:d4dda5c437f0 5609 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5610
mbed_official 133:d4dda5c437f0 5611 /******************** Bits definition for RTC_BKP6R register ****************/
mbed_official 133:d4dda5c437f0 5612 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5613
mbed_official 133:d4dda5c437f0 5614 /******************** Bits definition for RTC_BKP7R register ****************/
mbed_official 133:d4dda5c437f0 5615 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5616
mbed_official 133:d4dda5c437f0 5617 /******************** Bits definition for RTC_BKP8R register ****************/
mbed_official 133:d4dda5c437f0 5618 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5619
mbed_official 133:d4dda5c437f0 5620 /******************** Bits definition for RTC_BKP9R register ****************/
mbed_official 133:d4dda5c437f0 5621 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5622
mbed_official 133:d4dda5c437f0 5623 /******************** Bits definition for RTC_BKP10R register ***************/
mbed_official 133:d4dda5c437f0 5624 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5625
mbed_official 133:d4dda5c437f0 5626 /******************** Bits definition for RTC_BKP11R register ***************/
mbed_official 133:d4dda5c437f0 5627 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5628
mbed_official 133:d4dda5c437f0 5629 /******************** Bits definition for RTC_BKP12R register ***************/
mbed_official 133:d4dda5c437f0 5630 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5631
mbed_official 133:d4dda5c437f0 5632 /******************** Bits definition for RTC_BKP13R register ***************/
mbed_official 133:d4dda5c437f0 5633 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5634
mbed_official 133:d4dda5c437f0 5635 /******************** Bits definition for RTC_BKP14R register ***************/
mbed_official 133:d4dda5c437f0 5636 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5637
mbed_official 133:d4dda5c437f0 5638 /******************** Bits definition for RTC_BKP15R register ***************/
mbed_official 133:d4dda5c437f0 5639 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5640
mbed_official 133:d4dda5c437f0 5641 /******************** Bits definition for RTC_BKP16R register ***************/
mbed_official 133:d4dda5c437f0 5642 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5643
mbed_official 133:d4dda5c437f0 5644 /******************** Bits definition for RTC_BKP17R register ***************/
mbed_official 133:d4dda5c437f0 5645 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5646
mbed_official 133:d4dda5c437f0 5647 /******************** Bits definition for RTC_BKP18R register ***************/
mbed_official 133:d4dda5c437f0 5648 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5649
mbed_official 133:d4dda5c437f0 5650 /******************** Bits definition for RTC_BKP19R register ***************/
mbed_official 133:d4dda5c437f0 5651 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
mbed_official 133:d4dda5c437f0 5652
mbed_official 133:d4dda5c437f0 5653
mbed_official 133:d4dda5c437f0 5654
mbed_official 133:d4dda5c437f0 5655 /******************************************************************************/
mbed_official 133:d4dda5c437f0 5656 /* */
mbed_official 133:d4dda5c437f0 5657 /* SD host Interface */
mbed_official 133:d4dda5c437f0 5658 /* */
mbed_official 133:d4dda5c437f0 5659 /******************************************************************************/
mbed_official 133:d4dda5c437f0 5660 /****************** Bit definition for SDIO_POWER register ******************/
mbed_official 133:d4dda5c437f0 5661 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
mbed_official 133:d4dda5c437f0 5662 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 5663 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 5664
mbed_official 133:d4dda5c437f0 5665 /****************** Bit definition for SDIO_CLKCR register ******************/
mbed_official 133:d4dda5c437f0 5666 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
mbed_official 133:d4dda5c437f0 5667 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
mbed_official 133:d4dda5c437f0 5668 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
mbed_official 133:d4dda5c437f0 5669 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
mbed_official 133:d4dda5c437f0 5670
mbed_official 133:d4dda5c437f0 5671 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
mbed_official 133:d4dda5c437f0 5672 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 5673 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 5674
mbed_official 133:d4dda5c437f0 5675 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
mbed_official 133:d4dda5c437f0 5676 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
mbed_official 133:d4dda5c437f0 5677
mbed_official 133:d4dda5c437f0 5678 /******************* Bit definition for SDIO_ARG register *******************/
mbed_official 133:d4dda5c437f0 5679 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
mbed_official 133:d4dda5c437f0 5680
mbed_official 133:d4dda5c437f0 5681 /******************* Bit definition for SDIO_CMD register *******************/
mbed_official 133:d4dda5c437f0 5682 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
mbed_official 133:d4dda5c437f0 5683
mbed_official 133:d4dda5c437f0 5684 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
mbed_official 133:d4dda5c437f0 5685 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
mbed_official 133:d4dda5c437f0 5686 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
mbed_official 133:d4dda5c437f0 5687
mbed_official 133:d4dda5c437f0 5688 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
mbed_official 133:d4dda5c437f0 5689 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
mbed_official 133:d4dda5c437f0 5690 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
mbed_official 133:d4dda5c437f0 5691 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
mbed_official 133:d4dda5c437f0 5692 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
mbed_official 133:d4dda5c437f0 5693 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
mbed_official 133:d4dda5c437f0 5694 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
mbed_official 133:d4dda5c437f0 5695
mbed_official 133:d4dda5c437f0 5696 /***************** Bit definition for SDIO_RESPCMD register *****************/
mbed_official 133:d4dda5c437f0 5697 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
mbed_official 133:d4dda5c437f0 5698
mbed_official 133:d4dda5c437f0 5699 /****************** Bit definition for SDIO_RESP0 register ******************/
mbed_official 133:d4dda5c437f0 5700 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 133:d4dda5c437f0 5701
mbed_official 133:d4dda5c437f0 5702 /****************** Bit definition for SDIO_RESP1 register ******************/
mbed_official 133:d4dda5c437f0 5703 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 133:d4dda5c437f0 5704
mbed_official 133:d4dda5c437f0 5705 /****************** Bit definition for SDIO_RESP2 register ******************/
mbed_official 133:d4dda5c437f0 5706 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 133:d4dda5c437f0 5707
mbed_official 133:d4dda5c437f0 5708 /****************** Bit definition for SDIO_RESP3 register ******************/
mbed_official 133:d4dda5c437f0 5709 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 133:d4dda5c437f0 5710
mbed_official 133:d4dda5c437f0 5711 /****************** Bit definition for SDIO_RESP4 register ******************/
mbed_official 133:d4dda5c437f0 5712 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 133:d4dda5c437f0 5713
mbed_official 133:d4dda5c437f0 5714 /****************** Bit definition for SDIO_DTIMER register *****************/
mbed_official 133:d4dda5c437f0 5715 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
mbed_official 133:d4dda5c437f0 5716
mbed_official 133:d4dda5c437f0 5717 /****************** Bit definition for SDIO_DLEN register *******************/
mbed_official 133:d4dda5c437f0 5718 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
mbed_official 133:d4dda5c437f0 5719
mbed_official 133:d4dda5c437f0 5720 /****************** Bit definition for SDIO_DCTRL register ******************/
mbed_official 133:d4dda5c437f0 5721 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
mbed_official 133:d4dda5c437f0 5722 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
mbed_official 133:d4dda5c437f0 5723 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
mbed_official 133:d4dda5c437f0 5724 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
mbed_official 133:d4dda5c437f0 5725
mbed_official 133:d4dda5c437f0 5726 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
mbed_official 133:d4dda5c437f0 5727 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 5728 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 5729 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 5730 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 5731
mbed_official 133:d4dda5c437f0 5732 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
mbed_official 133:d4dda5c437f0 5733 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
mbed_official 133:d4dda5c437f0 5734 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
mbed_official 133:d4dda5c437f0 5735 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
mbed_official 133:d4dda5c437f0 5736
mbed_official 133:d4dda5c437f0 5737 /****************** Bit definition for SDIO_DCOUNT register *****************/
mbed_official 133:d4dda5c437f0 5738 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
mbed_official 133:d4dda5c437f0 5739
mbed_official 133:d4dda5c437f0 5740 /****************** Bit definition for SDIO_STA register ********************/
mbed_official 133:d4dda5c437f0 5741 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
mbed_official 133:d4dda5c437f0 5742 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
mbed_official 133:d4dda5c437f0 5743 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
mbed_official 133:d4dda5c437f0 5744 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
mbed_official 133:d4dda5c437f0 5745 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
mbed_official 133:d4dda5c437f0 5746 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
mbed_official 133:d4dda5c437f0 5747 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
mbed_official 133:d4dda5c437f0 5748 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
mbed_official 133:d4dda5c437f0 5749 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
mbed_official 133:d4dda5c437f0 5750 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
mbed_official 133:d4dda5c437f0 5751 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
mbed_official 133:d4dda5c437f0 5752 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
mbed_official 133:d4dda5c437f0 5753 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
mbed_official 133:d4dda5c437f0 5754 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
mbed_official 133:d4dda5c437f0 5755 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
mbed_official 133:d4dda5c437f0 5756 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
mbed_official 133:d4dda5c437f0 5757 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
mbed_official 133:d4dda5c437f0 5758 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
mbed_official 133:d4dda5c437f0 5759 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
mbed_official 133:d4dda5c437f0 5760 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
mbed_official 133:d4dda5c437f0 5761 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
mbed_official 133:d4dda5c437f0 5762 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
mbed_official 133:d4dda5c437f0 5763 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
mbed_official 133:d4dda5c437f0 5764 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
mbed_official 133:d4dda5c437f0 5765
mbed_official 133:d4dda5c437f0 5766 /******************* Bit definition for SDIO_ICR register *******************/
mbed_official 133:d4dda5c437f0 5767 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
mbed_official 133:d4dda5c437f0 5768 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
mbed_official 133:d4dda5c437f0 5769 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
mbed_official 133:d4dda5c437f0 5770 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
mbed_official 133:d4dda5c437f0 5771 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
mbed_official 133:d4dda5c437f0 5772 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
mbed_official 133:d4dda5c437f0 5773 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
mbed_official 133:d4dda5c437f0 5774 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
mbed_official 133:d4dda5c437f0 5775 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
mbed_official 133:d4dda5c437f0 5776 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
mbed_official 133:d4dda5c437f0 5777 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
mbed_official 133:d4dda5c437f0 5778 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
mbed_official 133:d4dda5c437f0 5779 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
mbed_official 133:d4dda5c437f0 5780
mbed_official 133:d4dda5c437f0 5781 /****************** Bit definition for SDIO_MASK register *******************/
mbed_official 133:d4dda5c437f0 5782 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
mbed_official 133:d4dda5c437f0 5783 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
mbed_official 133:d4dda5c437f0 5784 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
mbed_official 133:d4dda5c437f0 5785 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
mbed_official 133:d4dda5c437f0 5786 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
mbed_official 133:d4dda5c437f0 5787 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
mbed_official 133:d4dda5c437f0 5788 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
mbed_official 133:d4dda5c437f0 5789 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
mbed_official 133:d4dda5c437f0 5790 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
mbed_official 133:d4dda5c437f0 5791 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
mbed_official 133:d4dda5c437f0 5792 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
mbed_official 133:d4dda5c437f0 5793 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
mbed_official 133:d4dda5c437f0 5794 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
mbed_official 133:d4dda5c437f0 5795 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
mbed_official 133:d4dda5c437f0 5796 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
mbed_official 133:d4dda5c437f0 5797 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
mbed_official 133:d4dda5c437f0 5798 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
mbed_official 133:d4dda5c437f0 5799 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
mbed_official 133:d4dda5c437f0 5800 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
mbed_official 133:d4dda5c437f0 5801 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
mbed_official 133:d4dda5c437f0 5802 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
mbed_official 133:d4dda5c437f0 5803 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
mbed_official 133:d4dda5c437f0 5804 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
mbed_official 133:d4dda5c437f0 5805 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
mbed_official 133:d4dda5c437f0 5806
mbed_official 133:d4dda5c437f0 5807 /***************** Bit definition for SDIO_FIFOCNT register *****************/
mbed_official 133:d4dda5c437f0 5808 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
mbed_official 133:d4dda5c437f0 5809
mbed_official 133:d4dda5c437f0 5810 /****************** Bit definition for SDIO_FIFO register *******************/
mbed_official 133:d4dda5c437f0 5811 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
mbed_official 133:d4dda5c437f0 5812
mbed_official 133:d4dda5c437f0 5813 /******************************************************************************/
mbed_official 133:d4dda5c437f0 5814 /* */
mbed_official 133:d4dda5c437f0 5815 /* Serial Peripheral Interface */
mbed_official 133:d4dda5c437f0 5816 /* */
mbed_official 133:d4dda5c437f0 5817 /******************************************************************************/
mbed_official 133:d4dda5c437f0 5818 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 133:d4dda5c437f0 5819 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
mbed_official 133:d4dda5c437f0 5820 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
mbed_official 133:d4dda5c437f0 5821 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
mbed_official 133:d4dda5c437f0 5822
mbed_official 133:d4dda5c437f0 5823 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
mbed_official 133:d4dda5c437f0 5824 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 5825 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 5826 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 5827
mbed_official 133:d4dda5c437f0 5828 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
mbed_official 133:d4dda5c437f0 5829 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
mbed_official 133:d4dda5c437f0 5830 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
mbed_official 133:d4dda5c437f0 5831 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
mbed_official 133:d4dda5c437f0 5832 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
mbed_official 133:d4dda5c437f0 5833 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
mbed_official 133:d4dda5c437f0 5834 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
mbed_official 133:d4dda5c437f0 5835 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
mbed_official 133:d4dda5c437f0 5836 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
mbed_official 133:d4dda5c437f0 5837 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
mbed_official 133:d4dda5c437f0 5838
mbed_official 133:d4dda5c437f0 5839 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 133:d4dda5c437f0 5840 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
mbed_official 133:d4dda5c437f0 5841 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
mbed_official 133:d4dda5c437f0 5842 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
mbed_official 133:d4dda5c437f0 5843 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
mbed_official 133:d4dda5c437f0 5844 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
mbed_official 133:d4dda5c437f0 5845 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
mbed_official 133:d4dda5c437f0 5846 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
mbed_official 133:d4dda5c437f0 5847
mbed_official 133:d4dda5c437f0 5848 /******************** Bit definition for SPI_SR register ********************/
mbed_official 133:d4dda5c437f0 5849 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
mbed_official 133:d4dda5c437f0 5850 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
mbed_official 133:d4dda5c437f0 5851 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
mbed_official 133:d4dda5c437f0 5852 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
mbed_official 133:d4dda5c437f0 5853 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
mbed_official 133:d4dda5c437f0 5854 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
mbed_official 133:d4dda5c437f0 5855 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
mbed_official 133:d4dda5c437f0 5856 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
mbed_official 133:d4dda5c437f0 5857 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
mbed_official 133:d4dda5c437f0 5858
mbed_official 133:d4dda5c437f0 5859 /******************** Bit definition for SPI_DR register ********************/
mbed_official 133:d4dda5c437f0 5860 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
mbed_official 133:d4dda5c437f0 5861
mbed_official 133:d4dda5c437f0 5862 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 133:d4dda5c437f0 5863 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
mbed_official 133:d4dda5c437f0 5864
mbed_official 133:d4dda5c437f0 5865 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 133:d4dda5c437f0 5866 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
mbed_official 133:d4dda5c437f0 5867
mbed_official 133:d4dda5c437f0 5868 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 133:d4dda5c437f0 5869 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
mbed_official 133:d4dda5c437f0 5870
mbed_official 133:d4dda5c437f0 5871 /****************** Bit definition for SPI_I2SCFGR register *****************/
mbed_official 133:d4dda5c437f0 5872 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
mbed_official 133:d4dda5c437f0 5873
mbed_official 133:d4dda5c437f0 5874 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 133:d4dda5c437f0 5875 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 5876 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 5877
mbed_official 133:d4dda5c437f0 5878 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
mbed_official 133:d4dda5c437f0 5879
mbed_official 133:d4dda5c437f0 5880 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 133:d4dda5c437f0 5881 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 5882 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 5883
mbed_official 133:d4dda5c437f0 5884 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
mbed_official 133:d4dda5c437f0 5885
mbed_official 133:d4dda5c437f0 5886 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 133:d4dda5c437f0 5887 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 5888 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 5889
mbed_official 133:d4dda5c437f0 5890 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
mbed_official 133:d4dda5c437f0 5891 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
mbed_official 133:d4dda5c437f0 5892
mbed_official 133:d4dda5c437f0 5893 /****************** Bit definition for SPI_I2SPR register *******************/
mbed_official 133:d4dda5c437f0 5894 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
mbed_official 133:d4dda5c437f0 5895 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
mbed_official 133:d4dda5c437f0 5896 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
mbed_official 133:d4dda5c437f0 5897
mbed_official 133:d4dda5c437f0 5898 /******************************************************************************/
mbed_official 133:d4dda5c437f0 5899 /* */
mbed_official 133:d4dda5c437f0 5900 /* SYSCFG */
mbed_official 133:d4dda5c437f0 5901 /* */
mbed_official 133:d4dda5c437f0 5902 /******************************************************************************/
mbed_official 133:d4dda5c437f0 5903 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
mbed_official 133:d4dda5c437f0 5904 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
mbed_official 133:d4dda5c437f0 5905 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 5906 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 5907 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 5908
mbed_official 133:d4dda5c437f0 5909 /****************** Bit definition for SYSCFG_PMC register ******************/
mbed_official 133:d4dda5c437f0 5910 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
mbed_official 133:d4dda5c437f0 5911 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
mbed_official 133:d4dda5c437f0 5912 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
mbed_official 133:d4dda5c437f0 5913
mbed_official 133:d4dda5c437f0 5914 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 133:d4dda5c437f0 5915 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
mbed_official 133:d4dda5c437f0 5916 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
mbed_official 133:d4dda5c437f0 5917 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
mbed_official 133:d4dda5c437f0 5918 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
mbed_official 133:d4dda5c437f0 5919 /**
mbed_official 133:d4dda5c437f0 5920 * @brief EXTI0 configuration
mbed_official 133:d4dda5c437f0 5921 */
mbed_official 133:d4dda5c437f0 5922 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
mbed_official 133:d4dda5c437f0 5923 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
mbed_official 133:d4dda5c437f0 5924 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
mbed_official 133:d4dda5c437f0 5925 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
mbed_official 133:d4dda5c437f0 5926 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
mbed_official 133:d4dda5c437f0 5927 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
mbed_official 133:d4dda5c437f0 5928 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
mbed_official 133:d4dda5c437f0 5929 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
mbed_official 133:d4dda5c437f0 5930 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
mbed_official 133:d4dda5c437f0 5931
mbed_official 133:d4dda5c437f0 5932 /**
mbed_official 133:d4dda5c437f0 5933 * @brief EXTI1 configuration
mbed_official 133:d4dda5c437f0 5934 */
mbed_official 133:d4dda5c437f0 5935 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
mbed_official 133:d4dda5c437f0 5936 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
mbed_official 133:d4dda5c437f0 5937 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
mbed_official 133:d4dda5c437f0 5938 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
mbed_official 133:d4dda5c437f0 5939 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
mbed_official 133:d4dda5c437f0 5940 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
mbed_official 133:d4dda5c437f0 5941 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
mbed_official 133:d4dda5c437f0 5942 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
mbed_official 133:d4dda5c437f0 5943 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
mbed_official 133:d4dda5c437f0 5944
mbed_official 133:d4dda5c437f0 5945 /**
mbed_official 133:d4dda5c437f0 5946 * @brief EXTI2 configuration
mbed_official 133:d4dda5c437f0 5947 */
mbed_official 133:d4dda5c437f0 5948 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
mbed_official 133:d4dda5c437f0 5949 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
mbed_official 133:d4dda5c437f0 5950 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
mbed_official 133:d4dda5c437f0 5951 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
mbed_official 133:d4dda5c437f0 5952 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
mbed_official 133:d4dda5c437f0 5953 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
mbed_official 133:d4dda5c437f0 5954 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
mbed_official 133:d4dda5c437f0 5955 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
mbed_official 133:d4dda5c437f0 5956 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
mbed_official 133:d4dda5c437f0 5957
mbed_official 133:d4dda5c437f0 5958 /**
mbed_official 133:d4dda5c437f0 5959 * @brief EXTI3 configuration
mbed_official 133:d4dda5c437f0 5960 */
mbed_official 133:d4dda5c437f0 5961 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
mbed_official 133:d4dda5c437f0 5962 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
mbed_official 133:d4dda5c437f0 5963 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
mbed_official 133:d4dda5c437f0 5964 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
mbed_official 133:d4dda5c437f0 5965 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
mbed_official 133:d4dda5c437f0 5966 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
mbed_official 133:d4dda5c437f0 5967 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
mbed_official 133:d4dda5c437f0 5968 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
mbed_official 133:d4dda5c437f0 5969 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
mbed_official 133:d4dda5c437f0 5970
mbed_official 133:d4dda5c437f0 5971 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
mbed_official 133:d4dda5c437f0 5972 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
mbed_official 133:d4dda5c437f0 5973 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
mbed_official 133:d4dda5c437f0 5974 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
mbed_official 133:d4dda5c437f0 5975 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
mbed_official 133:d4dda5c437f0 5976 /**
mbed_official 133:d4dda5c437f0 5977 * @brief EXTI4 configuration
mbed_official 133:d4dda5c437f0 5978 */
mbed_official 133:d4dda5c437f0 5979 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
mbed_official 133:d4dda5c437f0 5980 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
mbed_official 133:d4dda5c437f0 5981 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
mbed_official 133:d4dda5c437f0 5982 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
mbed_official 133:d4dda5c437f0 5983 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
mbed_official 133:d4dda5c437f0 5984 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
mbed_official 133:d4dda5c437f0 5985 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
mbed_official 133:d4dda5c437f0 5986 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
mbed_official 133:d4dda5c437f0 5987 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
mbed_official 133:d4dda5c437f0 5988
mbed_official 133:d4dda5c437f0 5989 /**
mbed_official 133:d4dda5c437f0 5990 * @brief EXTI5 configuration
mbed_official 133:d4dda5c437f0 5991 */
mbed_official 133:d4dda5c437f0 5992 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
mbed_official 133:d4dda5c437f0 5993 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
mbed_official 133:d4dda5c437f0 5994 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
mbed_official 133:d4dda5c437f0 5995 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
mbed_official 133:d4dda5c437f0 5996 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
mbed_official 133:d4dda5c437f0 5997 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
mbed_official 133:d4dda5c437f0 5998 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
mbed_official 133:d4dda5c437f0 5999 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
mbed_official 133:d4dda5c437f0 6000 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
mbed_official 133:d4dda5c437f0 6001
mbed_official 133:d4dda5c437f0 6002 /**
mbed_official 133:d4dda5c437f0 6003 * @brief EXTI6 configuration
mbed_official 133:d4dda5c437f0 6004 */
mbed_official 133:d4dda5c437f0 6005 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
mbed_official 133:d4dda5c437f0 6006 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
mbed_official 133:d4dda5c437f0 6007 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
mbed_official 133:d4dda5c437f0 6008 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
mbed_official 133:d4dda5c437f0 6009 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
mbed_official 133:d4dda5c437f0 6010 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
mbed_official 133:d4dda5c437f0 6011 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
mbed_official 133:d4dda5c437f0 6012 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
mbed_official 133:d4dda5c437f0 6013 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
mbed_official 133:d4dda5c437f0 6014
mbed_official 133:d4dda5c437f0 6015 /**
mbed_official 133:d4dda5c437f0 6016 * @brief EXTI7 configuration
mbed_official 133:d4dda5c437f0 6017 */
mbed_official 133:d4dda5c437f0 6018 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
mbed_official 133:d4dda5c437f0 6019 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
mbed_official 133:d4dda5c437f0 6020 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
mbed_official 133:d4dda5c437f0 6021 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
mbed_official 133:d4dda5c437f0 6022 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
mbed_official 133:d4dda5c437f0 6023 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
mbed_official 133:d4dda5c437f0 6024 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
mbed_official 133:d4dda5c437f0 6025 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
mbed_official 133:d4dda5c437f0 6026 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
mbed_official 133:d4dda5c437f0 6027
mbed_official 133:d4dda5c437f0 6028
mbed_official 133:d4dda5c437f0 6029 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
mbed_official 133:d4dda5c437f0 6030 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
mbed_official 133:d4dda5c437f0 6031 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
mbed_official 133:d4dda5c437f0 6032 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
mbed_official 133:d4dda5c437f0 6033 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
mbed_official 133:d4dda5c437f0 6034
mbed_official 133:d4dda5c437f0 6035 /**
mbed_official 133:d4dda5c437f0 6036 * @brief EXTI8 configuration
mbed_official 133:d4dda5c437f0 6037 */
mbed_official 133:d4dda5c437f0 6038 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
mbed_official 133:d4dda5c437f0 6039 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
mbed_official 133:d4dda5c437f0 6040 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
mbed_official 133:d4dda5c437f0 6041 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
mbed_official 133:d4dda5c437f0 6042 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
mbed_official 133:d4dda5c437f0 6043 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
mbed_official 133:d4dda5c437f0 6044 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
mbed_official 133:d4dda5c437f0 6045 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
mbed_official 133:d4dda5c437f0 6046 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
mbed_official 133:d4dda5c437f0 6047
mbed_official 133:d4dda5c437f0 6048 /**
mbed_official 133:d4dda5c437f0 6049 * @brief EXTI9 configuration
mbed_official 133:d4dda5c437f0 6050 */
mbed_official 133:d4dda5c437f0 6051 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
mbed_official 133:d4dda5c437f0 6052 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
mbed_official 133:d4dda5c437f0 6053 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
mbed_official 133:d4dda5c437f0 6054 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
mbed_official 133:d4dda5c437f0 6055 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
mbed_official 133:d4dda5c437f0 6056 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
mbed_official 133:d4dda5c437f0 6057 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
mbed_official 133:d4dda5c437f0 6058 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
mbed_official 133:d4dda5c437f0 6059 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
mbed_official 133:d4dda5c437f0 6060
mbed_official 133:d4dda5c437f0 6061 /**
mbed_official 133:d4dda5c437f0 6062 * @brief EXTI10 configuration
mbed_official 133:d4dda5c437f0 6063 */
mbed_official 133:d4dda5c437f0 6064 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
mbed_official 133:d4dda5c437f0 6065 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
mbed_official 133:d4dda5c437f0 6066 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
mbed_official 133:d4dda5c437f0 6067 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
mbed_official 133:d4dda5c437f0 6068 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
mbed_official 133:d4dda5c437f0 6069 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
mbed_official 133:d4dda5c437f0 6070 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
mbed_official 133:d4dda5c437f0 6071 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
mbed_official 133:d4dda5c437f0 6072 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
mbed_official 133:d4dda5c437f0 6073
mbed_official 133:d4dda5c437f0 6074 /**
mbed_official 133:d4dda5c437f0 6075 * @brief EXTI11 configuration
mbed_official 133:d4dda5c437f0 6076 */
mbed_official 133:d4dda5c437f0 6077 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
mbed_official 133:d4dda5c437f0 6078 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
mbed_official 133:d4dda5c437f0 6079 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
mbed_official 133:d4dda5c437f0 6080 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
mbed_official 133:d4dda5c437f0 6081 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
mbed_official 133:d4dda5c437f0 6082 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
mbed_official 133:d4dda5c437f0 6083 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
mbed_official 133:d4dda5c437f0 6084 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
mbed_official 133:d4dda5c437f0 6085 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
mbed_official 133:d4dda5c437f0 6086
mbed_official 133:d4dda5c437f0 6087 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
mbed_official 133:d4dda5c437f0 6088 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
mbed_official 133:d4dda5c437f0 6089 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
mbed_official 133:d4dda5c437f0 6090 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
mbed_official 133:d4dda5c437f0 6091 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
mbed_official 133:d4dda5c437f0 6092 /**
mbed_official 133:d4dda5c437f0 6093 * @brief EXTI12 configuration
mbed_official 133:d4dda5c437f0 6094 */
mbed_official 133:d4dda5c437f0 6095 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
mbed_official 133:d4dda5c437f0 6096 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
mbed_official 133:d4dda5c437f0 6097 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
mbed_official 133:d4dda5c437f0 6098 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
mbed_official 133:d4dda5c437f0 6099 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
mbed_official 133:d4dda5c437f0 6100 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
mbed_official 133:d4dda5c437f0 6101 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
mbed_official 133:d4dda5c437f0 6102 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
mbed_official 133:d4dda5c437f0 6103
mbed_official 133:d4dda5c437f0 6104 /**
mbed_official 133:d4dda5c437f0 6105 * @brief EXTI13 configuration
mbed_official 133:d4dda5c437f0 6106 */
mbed_official 133:d4dda5c437f0 6107 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
mbed_official 133:d4dda5c437f0 6108 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
mbed_official 133:d4dda5c437f0 6109 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
mbed_official 133:d4dda5c437f0 6110 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
mbed_official 133:d4dda5c437f0 6111 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
mbed_official 133:d4dda5c437f0 6112 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
mbed_official 133:d4dda5c437f0 6113 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
mbed_official 133:d4dda5c437f0 6114 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
mbed_official 133:d4dda5c437f0 6115
mbed_official 133:d4dda5c437f0 6116 /**
mbed_official 133:d4dda5c437f0 6117 * @brief EXTI14 configuration
mbed_official 133:d4dda5c437f0 6118 */
mbed_official 133:d4dda5c437f0 6119 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
mbed_official 133:d4dda5c437f0 6120 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
mbed_official 133:d4dda5c437f0 6121 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
mbed_official 133:d4dda5c437f0 6122 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
mbed_official 133:d4dda5c437f0 6123 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
mbed_official 133:d4dda5c437f0 6124 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
mbed_official 133:d4dda5c437f0 6125 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
mbed_official 133:d4dda5c437f0 6126 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
mbed_official 133:d4dda5c437f0 6127
mbed_official 133:d4dda5c437f0 6128 /**
mbed_official 133:d4dda5c437f0 6129 * @brief EXTI15 configuration
mbed_official 133:d4dda5c437f0 6130 */
mbed_official 133:d4dda5c437f0 6131 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
mbed_official 133:d4dda5c437f0 6132 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
mbed_official 133:d4dda5c437f0 6133 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
mbed_official 133:d4dda5c437f0 6134 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
mbed_official 133:d4dda5c437f0 6135 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
mbed_official 133:d4dda5c437f0 6136 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
mbed_official 133:d4dda5c437f0 6137 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
mbed_official 133:d4dda5c437f0 6138 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
mbed_official 133:d4dda5c437f0 6139
mbed_official 133:d4dda5c437f0 6140 /****************** Bit definition for SYSCFG_CMPCR register ****************/
mbed_official 133:d4dda5c437f0 6141 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
mbed_official 133:d4dda5c437f0 6142 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
mbed_official 133:d4dda5c437f0 6143
mbed_official 133:d4dda5c437f0 6144 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6145 /* */
mbed_official 133:d4dda5c437f0 6146 /* TIM */
mbed_official 133:d4dda5c437f0 6147 /* */
mbed_official 133:d4dda5c437f0 6148 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6149 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 133:d4dda5c437f0 6150 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
mbed_official 133:d4dda5c437f0 6151 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
mbed_official 133:d4dda5c437f0 6152 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
mbed_official 133:d4dda5c437f0 6153 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
mbed_official 133:d4dda5c437f0 6154 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
mbed_official 133:d4dda5c437f0 6155
mbed_official 133:d4dda5c437f0 6156 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 133:d4dda5c437f0 6157 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6158 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6159
mbed_official 133:d4dda5c437f0 6160 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
mbed_official 133:d4dda5c437f0 6161
mbed_official 133:d4dda5c437f0 6162 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
mbed_official 133:d4dda5c437f0 6163 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6164 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6165
mbed_official 133:d4dda5c437f0 6166 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 133:d4dda5c437f0 6167 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
mbed_official 133:d4dda5c437f0 6168 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
mbed_official 133:d4dda5c437f0 6169 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
mbed_official 133:d4dda5c437f0 6170
mbed_official 133:d4dda5c437f0 6171 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 133:d4dda5c437f0 6172 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6173 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6174 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6175
mbed_official 133:d4dda5c437f0 6176 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
mbed_official 133:d4dda5c437f0 6177 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 133:d4dda5c437f0 6178 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 133:d4dda5c437f0 6179 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 133:d4dda5c437f0 6180 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 133:d4dda5c437f0 6181 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 133:d4dda5c437f0 6182 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 133:d4dda5c437f0 6183 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 133:d4dda5c437f0 6184
mbed_official 133:d4dda5c437f0 6185 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 133:d4dda5c437f0 6186 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 133:d4dda5c437f0 6187 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6188 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6189 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6190
mbed_official 133:d4dda5c437f0 6191 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 133:d4dda5c437f0 6192 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6193 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6194 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6195
mbed_official 133:d4dda5c437f0 6196 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
mbed_official 133:d4dda5c437f0 6197
mbed_official 133:d4dda5c437f0 6198 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 133:d4dda5c437f0 6199 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6200 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6201 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6202 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 6203
mbed_official 133:d4dda5c437f0 6204 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 133:d4dda5c437f0 6205 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6206 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6207
mbed_official 133:d4dda5c437f0 6208 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
mbed_official 133:d4dda5c437f0 6209 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
mbed_official 133:d4dda5c437f0 6210
mbed_official 133:d4dda5c437f0 6211 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 133:d4dda5c437f0 6212 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
mbed_official 133:d4dda5c437f0 6213 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 133:d4dda5c437f0 6214 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 133:d4dda5c437f0 6215 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 133:d4dda5c437f0 6216 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 133:d4dda5c437f0 6217 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
mbed_official 133:d4dda5c437f0 6218 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
mbed_official 133:d4dda5c437f0 6219 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
mbed_official 133:d4dda5c437f0 6220 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
mbed_official 133:d4dda5c437f0 6221 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 133:d4dda5c437f0 6222 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 133:d4dda5c437f0 6223 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 133:d4dda5c437f0 6224 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 133:d4dda5c437f0 6225 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
mbed_official 133:d4dda5c437f0 6226 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
mbed_official 133:d4dda5c437f0 6227
mbed_official 133:d4dda5c437f0 6228 /******************** Bit definition for TIM_SR register ********************/
mbed_official 133:d4dda5c437f0 6229 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
mbed_official 133:d4dda5c437f0 6230 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 133:d4dda5c437f0 6231 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 133:d4dda5c437f0 6232 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 133:d4dda5c437f0 6233 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 133:d4dda5c437f0 6234 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
mbed_official 133:d4dda5c437f0 6235 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
mbed_official 133:d4dda5c437f0 6236 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
mbed_official 133:d4dda5c437f0 6237 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 133:d4dda5c437f0 6238 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 133:d4dda5c437f0 6239 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 133:d4dda5c437f0 6240 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 133:d4dda5c437f0 6241
mbed_official 133:d4dda5c437f0 6242 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 133:d4dda5c437f0 6243 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
mbed_official 133:d4dda5c437f0 6244 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
mbed_official 133:d4dda5c437f0 6245 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
mbed_official 133:d4dda5c437f0 6246 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
mbed_official 133:d4dda5c437f0 6247 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
mbed_official 133:d4dda5c437f0 6248 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
mbed_official 133:d4dda5c437f0 6249 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
mbed_official 133:d4dda5c437f0 6250 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
mbed_official 133:d4dda5c437f0 6251
mbed_official 133:d4dda5c437f0 6252 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 133:d4dda5c437f0 6253 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 133:d4dda5c437f0 6254 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6255 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6256
mbed_official 133:d4dda5c437f0 6257 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
mbed_official 133:d4dda5c437f0 6258 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
mbed_official 133:d4dda5c437f0 6259
mbed_official 133:d4dda5c437f0 6260 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 133:d4dda5c437f0 6261 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6262 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6263 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6264
mbed_official 133:d4dda5c437f0 6265 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
mbed_official 133:d4dda5c437f0 6266
mbed_official 133:d4dda5c437f0 6267 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 133:d4dda5c437f0 6268 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6269 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6270
mbed_official 133:d4dda5c437f0 6271 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
mbed_official 133:d4dda5c437f0 6272 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
mbed_official 133:d4dda5c437f0 6273
mbed_official 133:d4dda5c437f0 6274 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 133:d4dda5c437f0 6275 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6276 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6277 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6278
mbed_official 133:d4dda5c437f0 6279 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
mbed_official 133:d4dda5c437f0 6280
mbed_official 133:d4dda5c437f0 6281 /*----------------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 6282
mbed_official 133:d4dda5c437f0 6283 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 133:d4dda5c437f0 6284 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6285 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6286
mbed_official 133:d4dda5c437f0 6287 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 133:d4dda5c437f0 6288 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6289 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6290 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6291 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 6292
mbed_official 133:d4dda5c437f0 6293 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 133:d4dda5c437f0 6294 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6295 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6296
mbed_official 133:d4dda5c437f0 6297 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 133:d4dda5c437f0 6298 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6299 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6300 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6301 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 6302
mbed_official 133:d4dda5c437f0 6303 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 133:d4dda5c437f0 6304 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 133:d4dda5c437f0 6305 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6306 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6307
mbed_official 133:d4dda5c437f0 6308 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
mbed_official 133:d4dda5c437f0 6309 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
mbed_official 133:d4dda5c437f0 6310
mbed_official 133:d4dda5c437f0 6311 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 133:d4dda5c437f0 6312 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6313 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6314 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6315
mbed_official 133:d4dda5c437f0 6316 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
mbed_official 133:d4dda5c437f0 6317
mbed_official 133:d4dda5c437f0 6318 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 133:d4dda5c437f0 6319 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6320 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6321
mbed_official 133:d4dda5c437f0 6322 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
mbed_official 133:d4dda5c437f0 6323 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
mbed_official 133:d4dda5c437f0 6324
mbed_official 133:d4dda5c437f0 6325 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 133:d4dda5c437f0 6326 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6327 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6328 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6329
mbed_official 133:d4dda5c437f0 6330 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
mbed_official 133:d4dda5c437f0 6331
mbed_official 133:d4dda5c437f0 6332 /*----------------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 6333
mbed_official 133:d4dda5c437f0 6334 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 133:d4dda5c437f0 6335 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6336 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6337
mbed_official 133:d4dda5c437f0 6338 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 133:d4dda5c437f0 6339 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6340 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6341 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6342 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 6343
mbed_official 133:d4dda5c437f0 6344 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 133:d4dda5c437f0 6345 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6346 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6347
mbed_official 133:d4dda5c437f0 6348 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 133:d4dda5c437f0 6349 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6350 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6351 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6352 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 6353
mbed_official 133:d4dda5c437f0 6354 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 133:d4dda5c437f0 6355 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
mbed_official 133:d4dda5c437f0 6356 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
mbed_official 133:d4dda5c437f0 6357 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 133:d4dda5c437f0 6358 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 133:d4dda5c437f0 6359 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
mbed_official 133:d4dda5c437f0 6360 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
mbed_official 133:d4dda5c437f0 6361 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 133:d4dda5c437f0 6362 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 133:d4dda5c437f0 6363 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
mbed_official 133:d4dda5c437f0 6364 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
mbed_official 133:d4dda5c437f0 6365 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 133:d4dda5c437f0 6366 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 133:d4dda5c437f0 6367 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
mbed_official 133:d4dda5c437f0 6368 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
mbed_official 133:d4dda5c437f0 6369 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 133:d4dda5c437f0 6370
mbed_official 133:d4dda5c437f0 6371 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 133:d4dda5c437f0 6372 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
mbed_official 133:d4dda5c437f0 6373
mbed_official 133:d4dda5c437f0 6374 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 133:d4dda5c437f0 6375 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
mbed_official 133:d4dda5c437f0 6376
mbed_official 133:d4dda5c437f0 6377 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 133:d4dda5c437f0 6378 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
mbed_official 133:d4dda5c437f0 6379
mbed_official 133:d4dda5c437f0 6380 /******************* Bit definition for TIM_RCR register ********************/
mbed_official 133:d4dda5c437f0 6381 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
mbed_official 133:d4dda5c437f0 6382
mbed_official 133:d4dda5c437f0 6383 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 133:d4dda5c437f0 6384 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
mbed_official 133:d4dda5c437f0 6385
mbed_official 133:d4dda5c437f0 6386 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 133:d4dda5c437f0 6387 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
mbed_official 133:d4dda5c437f0 6388
mbed_official 133:d4dda5c437f0 6389 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 133:d4dda5c437f0 6390 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
mbed_official 133:d4dda5c437f0 6391
mbed_official 133:d4dda5c437f0 6392 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 133:d4dda5c437f0 6393 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
mbed_official 133:d4dda5c437f0 6394
mbed_official 133:d4dda5c437f0 6395 /******************* Bit definition for TIM_BDTR register *******************/
mbed_official 133:d4dda5c437f0 6396 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 133:d4dda5c437f0 6397 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6398 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6399 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6400 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 6401 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 6402 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 6403 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 6404 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 6405
mbed_official 133:d4dda5c437f0 6406 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 133:d4dda5c437f0 6407 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6408 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6409
mbed_official 133:d4dda5c437f0 6410 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
mbed_official 133:d4dda5c437f0 6411 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
mbed_official 133:d4dda5c437f0 6412 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
mbed_official 133:d4dda5c437f0 6413 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
mbed_official 133:d4dda5c437f0 6414 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
mbed_official 133:d4dda5c437f0 6415 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
mbed_official 133:d4dda5c437f0 6416
mbed_official 133:d4dda5c437f0 6417 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 133:d4dda5c437f0 6418 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 133:d4dda5c437f0 6419 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6420 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6421 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6422 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 6423 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 6424
mbed_official 133:d4dda5c437f0 6425 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 133:d4dda5c437f0 6426 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6427 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6428 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6429 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 6430 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 6431
mbed_official 133:d4dda5c437f0 6432 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 133:d4dda5c437f0 6433 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
mbed_official 133:d4dda5c437f0 6434
mbed_official 133:d4dda5c437f0 6435 /******************* Bit definition for TIM_OR register *********************/
mbed_official 133:d4dda5c437f0 6436 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
mbed_official 133:d4dda5c437f0 6437 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6438 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6439 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
mbed_official 133:d4dda5c437f0 6440 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6441 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6442
mbed_official 133:d4dda5c437f0 6443
mbed_official 133:d4dda5c437f0 6444 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6445 /* */
mbed_official 133:d4dda5c437f0 6446 /* Universal Synchronous Asynchronous Receiver Transmitter */
mbed_official 133:d4dda5c437f0 6447 /* */
mbed_official 133:d4dda5c437f0 6448 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6449 /******************* Bit definition for USART_SR register *******************/
mbed_official 133:d4dda5c437f0 6450 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
mbed_official 133:d4dda5c437f0 6451 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
mbed_official 133:d4dda5c437f0 6452 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
mbed_official 133:d4dda5c437f0 6453 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
mbed_official 133:d4dda5c437f0 6454 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
mbed_official 133:d4dda5c437f0 6455 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
mbed_official 133:d4dda5c437f0 6456 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
mbed_official 133:d4dda5c437f0 6457 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
mbed_official 133:d4dda5c437f0 6458 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
mbed_official 133:d4dda5c437f0 6459 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
mbed_official 133:d4dda5c437f0 6460
mbed_official 133:d4dda5c437f0 6461 /******************* Bit definition for USART_DR register *******************/
mbed_official 133:d4dda5c437f0 6462 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
mbed_official 133:d4dda5c437f0 6463
mbed_official 133:d4dda5c437f0 6464 /****************** Bit definition for USART_BRR register *******************/
mbed_official 133:d4dda5c437f0 6465 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
mbed_official 133:d4dda5c437f0 6466 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
mbed_official 133:d4dda5c437f0 6467
mbed_official 133:d4dda5c437f0 6468 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 133:d4dda5c437f0 6469 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
mbed_official 133:d4dda5c437f0 6470 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
mbed_official 133:d4dda5c437f0 6471 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
mbed_official 133:d4dda5c437f0 6472 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
mbed_official 133:d4dda5c437f0 6473 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
mbed_official 133:d4dda5c437f0 6474 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
mbed_official 133:d4dda5c437f0 6475 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
mbed_official 133:d4dda5c437f0 6476 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
mbed_official 133:d4dda5c437f0 6477 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
mbed_official 133:d4dda5c437f0 6478 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
mbed_official 133:d4dda5c437f0 6479 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
mbed_official 133:d4dda5c437f0 6480 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
mbed_official 133:d4dda5c437f0 6481 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
mbed_official 133:d4dda5c437f0 6482 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
mbed_official 133:d4dda5c437f0 6483 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
mbed_official 133:d4dda5c437f0 6484
mbed_official 133:d4dda5c437f0 6485 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 133:d4dda5c437f0 6486 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
mbed_official 133:d4dda5c437f0 6487 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
mbed_official 133:d4dda5c437f0 6488 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
mbed_official 133:d4dda5c437f0 6489 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
mbed_official 133:d4dda5c437f0 6490 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
mbed_official 133:d4dda5c437f0 6491 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
mbed_official 133:d4dda5c437f0 6492 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
mbed_official 133:d4dda5c437f0 6493
mbed_official 133:d4dda5c437f0 6494 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
mbed_official 133:d4dda5c437f0 6495 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6496 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6497
mbed_official 133:d4dda5c437f0 6498 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
mbed_official 133:d4dda5c437f0 6499
mbed_official 133:d4dda5c437f0 6500 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 133:d4dda5c437f0 6501 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
mbed_official 133:d4dda5c437f0 6502 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
mbed_official 133:d4dda5c437f0 6503 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
mbed_official 133:d4dda5c437f0 6504 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
mbed_official 133:d4dda5c437f0 6505 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
mbed_official 133:d4dda5c437f0 6506 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
mbed_official 133:d4dda5c437f0 6507 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
mbed_official 133:d4dda5c437f0 6508 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
mbed_official 133:d4dda5c437f0 6509 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
mbed_official 133:d4dda5c437f0 6510 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
mbed_official 133:d4dda5c437f0 6511 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
mbed_official 133:d4dda5c437f0 6512 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
mbed_official 133:d4dda5c437f0 6513
mbed_official 133:d4dda5c437f0 6514 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 133:d4dda5c437f0 6515 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
mbed_official 133:d4dda5c437f0 6516 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6517 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6518 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6519 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 6520 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 6521 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 6522 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 6523 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 6524
mbed_official 133:d4dda5c437f0 6525 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
mbed_official 133:d4dda5c437f0 6526
mbed_official 133:d4dda5c437f0 6527 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6528 /* */
mbed_official 133:d4dda5c437f0 6529 /* Window WATCHDOG */
mbed_official 133:d4dda5c437f0 6530 /* */
mbed_official 133:d4dda5c437f0 6531 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6532 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 133:d4dda5c437f0 6533 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 133:d4dda5c437f0 6534 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6535 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6536 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6537 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 6538 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 6539 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 6540 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 6541
mbed_official 133:d4dda5c437f0 6542 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
mbed_official 133:d4dda5c437f0 6543
mbed_official 133:d4dda5c437f0 6544 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 133:d4dda5c437f0 6545 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 133:d4dda5c437f0 6546 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6547 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6548 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 6549 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 6550 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 6551 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 6552 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 6553
mbed_official 133:d4dda5c437f0 6554 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 133:d4dda5c437f0 6555 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6556 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6557
mbed_official 133:d4dda5c437f0 6558 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
mbed_official 133:d4dda5c437f0 6559
mbed_official 133:d4dda5c437f0 6560 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 133:d4dda5c437f0 6561 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
mbed_official 133:d4dda5c437f0 6562
mbed_official 133:d4dda5c437f0 6563
mbed_official 133:d4dda5c437f0 6564 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6565 /* */
mbed_official 133:d4dda5c437f0 6566 /* DBG */
mbed_official 133:d4dda5c437f0 6567 /* */
mbed_official 133:d4dda5c437f0 6568 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6569 /******************** Bit definition for DBGMCU_IDCODE register *************/
mbed_official 133:d4dda5c437f0 6570 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
mbed_official 133:d4dda5c437f0 6571 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
mbed_official 133:d4dda5c437f0 6572
mbed_official 133:d4dda5c437f0 6573 /******************** Bit definition for DBGMCU_CR register *****************/
mbed_official 133:d4dda5c437f0 6574 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 6575 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 6576 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 6577 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 6578
mbed_official 133:d4dda5c437f0 6579 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
mbed_official 133:d4dda5c437f0 6580 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
mbed_official 133:d4dda5c437f0 6581 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
mbed_official 133:d4dda5c437f0 6582
mbed_official 133:d4dda5c437f0 6583 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official 133:d4dda5c437f0 6584 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 6585 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 6586 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
mbed_official 133:d4dda5c437f0 6587 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 6588 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 6589 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 6590 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 6591 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 6592 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 6593 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 6594 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 6595 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
mbed_official 133:d4dda5c437f0 6596 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 6597 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 6598 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
mbed_official 133:d4dda5c437f0 6599 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 6600 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 6601 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
mbed_official 133:d4dda5c437f0 6602 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
mbed_official 133:d4dda5c437f0 6603
mbed_official 133:d4dda5c437f0 6604 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official 133:d4dda5c437f0 6605 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
mbed_official 133:d4dda5c437f0 6606 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
mbed_official 133:d4dda5c437f0 6607 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 6608 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
mbed_official 133:d4dda5c437f0 6609 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 6610
mbed_official 133:d4dda5c437f0 6611 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6612 /* */
mbed_official 133:d4dda5c437f0 6613 /* Ethernet MAC Registers bits definitions */
mbed_official 133:d4dda5c437f0 6614 /* */
mbed_official 133:d4dda5c437f0 6615 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6616 /* Bit definition for Ethernet MAC Control Register register */
mbed_official 133:d4dda5c437f0 6617 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
mbed_official 133:d4dda5c437f0 6618 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
mbed_official 133:d4dda5c437f0 6619 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
mbed_official 133:d4dda5c437f0 6620 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
mbed_official 133:d4dda5c437f0 6621 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
mbed_official 133:d4dda5c437f0 6622 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
mbed_official 133:d4dda5c437f0 6623 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
mbed_official 133:d4dda5c437f0 6624 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
mbed_official 133:d4dda5c437f0 6625 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
mbed_official 133:d4dda5c437f0 6626 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
mbed_official 133:d4dda5c437f0 6627 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
mbed_official 133:d4dda5c437f0 6628 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
mbed_official 133:d4dda5c437f0 6629 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
mbed_official 133:d4dda5c437f0 6630 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
mbed_official 133:d4dda5c437f0 6631 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
mbed_official 133:d4dda5c437f0 6632 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
mbed_official 133:d4dda5c437f0 6633 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
mbed_official 133:d4dda5c437f0 6634 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
mbed_official 133:d4dda5c437f0 6635 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
mbed_official 133:d4dda5c437f0 6636 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
mbed_official 133:d4dda5c437f0 6637 a transmission attempt during retries after a collision: 0 =< r <2^k */
mbed_official 133:d4dda5c437f0 6638 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
mbed_official 133:d4dda5c437f0 6639 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
mbed_official 133:d4dda5c437f0 6640 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
mbed_official 133:d4dda5c437f0 6641 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
mbed_official 133:d4dda5c437f0 6642 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
mbed_official 133:d4dda5c437f0 6643 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
mbed_official 133:d4dda5c437f0 6644 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
mbed_official 133:d4dda5c437f0 6645
mbed_official 133:d4dda5c437f0 6646 /* Bit definition for Ethernet MAC Frame Filter Register */
mbed_official 133:d4dda5c437f0 6647 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
mbed_official 133:d4dda5c437f0 6648 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
mbed_official 133:d4dda5c437f0 6649 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
mbed_official 133:d4dda5c437f0 6650 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
mbed_official 133:d4dda5c437f0 6651 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
mbed_official 133:d4dda5c437f0 6652 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
mbed_official 133:d4dda5c437f0 6653 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
mbed_official 133:d4dda5c437f0 6654 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
mbed_official 133:d4dda5c437f0 6655 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
mbed_official 133:d4dda5c437f0 6656 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
mbed_official 133:d4dda5c437f0 6657 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
mbed_official 133:d4dda5c437f0 6658 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
mbed_official 133:d4dda5c437f0 6659 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
mbed_official 133:d4dda5c437f0 6660 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
mbed_official 133:d4dda5c437f0 6661
mbed_official 133:d4dda5c437f0 6662 /* Bit definition for Ethernet MAC Hash Table High Register */
mbed_official 133:d4dda5c437f0 6663 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
mbed_official 133:d4dda5c437f0 6664
mbed_official 133:d4dda5c437f0 6665 /* Bit definition for Ethernet MAC Hash Table Low Register */
mbed_official 133:d4dda5c437f0 6666 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
mbed_official 133:d4dda5c437f0 6667
mbed_official 133:d4dda5c437f0 6668 /* Bit definition for Ethernet MAC MII Address Register */
mbed_official 133:d4dda5c437f0 6669 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
mbed_official 133:d4dda5c437f0 6670 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
mbed_official 133:d4dda5c437f0 6671 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
mbed_official 133:d4dda5c437f0 6672 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
mbed_official 133:d4dda5c437f0 6673 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
mbed_official 133:d4dda5c437f0 6674 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
mbed_official 133:d4dda5c437f0 6675 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
mbed_official 133:d4dda5c437f0 6676 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
mbed_official 133:d4dda5c437f0 6677 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
mbed_official 133:d4dda5c437f0 6678 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
mbed_official 133:d4dda5c437f0 6679
mbed_official 133:d4dda5c437f0 6680 /* Bit definition for Ethernet MAC MII Data Register */
mbed_official 133:d4dda5c437f0 6681 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
mbed_official 133:d4dda5c437f0 6682
mbed_official 133:d4dda5c437f0 6683 /* Bit definition for Ethernet MAC Flow Control Register */
mbed_official 133:d4dda5c437f0 6684 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
mbed_official 133:d4dda5c437f0 6685 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
mbed_official 133:d4dda5c437f0 6686 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
mbed_official 133:d4dda5c437f0 6687 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
mbed_official 133:d4dda5c437f0 6688 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
mbed_official 133:d4dda5c437f0 6689 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
mbed_official 133:d4dda5c437f0 6690 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
mbed_official 133:d4dda5c437f0 6691 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
mbed_official 133:d4dda5c437f0 6692 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
mbed_official 133:d4dda5c437f0 6693 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
mbed_official 133:d4dda5c437f0 6694 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
mbed_official 133:d4dda5c437f0 6695
mbed_official 133:d4dda5c437f0 6696 /* Bit definition for Ethernet MAC VLAN Tag Register */
mbed_official 133:d4dda5c437f0 6697 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
mbed_official 133:d4dda5c437f0 6698 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
mbed_official 133:d4dda5c437f0 6699
mbed_official 133:d4dda5c437f0 6700 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
mbed_official 133:d4dda5c437f0 6701 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
mbed_official 133:d4dda5c437f0 6702 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
mbed_official 133:d4dda5c437f0 6703 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
mbed_official 133:d4dda5c437f0 6704 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
mbed_official 133:d4dda5c437f0 6705 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
mbed_official 133:d4dda5c437f0 6706 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
mbed_official 133:d4dda5c437f0 6707 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
mbed_official 133:d4dda5c437f0 6708 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
mbed_official 133:d4dda5c437f0 6709 RSVD - Filter1 Command - RSVD - Filter0 Command
mbed_official 133:d4dda5c437f0 6710 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
mbed_official 133:d4dda5c437f0 6711 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
mbed_official 133:d4dda5c437f0 6712 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
mbed_official 133:d4dda5c437f0 6713
mbed_official 133:d4dda5c437f0 6714 /* Bit definition for Ethernet MAC PMT Control and Status Register */
mbed_official 133:d4dda5c437f0 6715 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
mbed_official 133:d4dda5c437f0 6716 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
mbed_official 133:d4dda5c437f0 6717 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
mbed_official 133:d4dda5c437f0 6718 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
mbed_official 133:d4dda5c437f0 6719 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
mbed_official 133:d4dda5c437f0 6720 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
mbed_official 133:d4dda5c437f0 6721 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
mbed_official 133:d4dda5c437f0 6722
mbed_official 133:d4dda5c437f0 6723 /* Bit definition for Ethernet MAC Status Register */
mbed_official 133:d4dda5c437f0 6724 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
mbed_official 133:d4dda5c437f0 6725 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
mbed_official 133:d4dda5c437f0 6726 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
mbed_official 133:d4dda5c437f0 6727 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
mbed_official 133:d4dda5c437f0 6728 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
mbed_official 133:d4dda5c437f0 6729
mbed_official 133:d4dda5c437f0 6730 /* Bit definition for Ethernet MAC Interrupt Mask Register */
mbed_official 133:d4dda5c437f0 6731 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
mbed_official 133:d4dda5c437f0 6732 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
mbed_official 133:d4dda5c437f0 6733
mbed_official 133:d4dda5c437f0 6734 /* Bit definition for Ethernet MAC Address0 High Register */
mbed_official 133:d4dda5c437f0 6735 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
mbed_official 133:d4dda5c437f0 6736
mbed_official 133:d4dda5c437f0 6737 /* Bit definition for Ethernet MAC Address0 Low Register */
mbed_official 133:d4dda5c437f0 6738 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
mbed_official 133:d4dda5c437f0 6739
mbed_official 133:d4dda5c437f0 6740 /* Bit definition for Ethernet MAC Address1 High Register */
mbed_official 133:d4dda5c437f0 6741 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
mbed_official 133:d4dda5c437f0 6742 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
mbed_official 133:d4dda5c437f0 6743 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
mbed_official 133:d4dda5c437f0 6744 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
mbed_official 133:d4dda5c437f0 6745 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
mbed_official 133:d4dda5c437f0 6746 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
mbed_official 133:d4dda5c437f0 6747 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
mbed_official 133:d4dda5c437f0 6748 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
mbed_official 133:d4dda5c437f0 6749 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
mbed_official 133:d4dda5c437f0 6750 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
mbed_official 133:d4dda5c437f0 6751
mbed_official 133:d4dda5c437f0 6752 /* Bit definition for Ethernet MAC Address1 Low Register */
mbed_official 133:d4dda5c437f0 6753 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
mbed_official 133:d4dda5c437f0 6754
mbed_official 133:d4dda5c437f0 6755 /* Bit definition for Ethernet MAC Address2 High Register */
mbed_official 133:d4dda5c437f0 6756 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
mbed_official 133:d4dda5c437f0 6757 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
mbed_official 133:d4dda5c437f0 6758 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
mbed_official 133:d4dda5c437f0 6759 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
mbed_official 133:d4dda5c437f0 6760 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
mbed_official 133:d4dda5c437f0 6761 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
mbed_official 133:d4dda5c437f0 6762 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
mbed_official 133:d4dda5c437f0 6763 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
mbed_official 133:d4dda5c437f0 6764 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
mbed_official 133:d4dda5c437f0 6765 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
mbed_official 133:d4dda5c437f0 6766
mbed_official 133:d4dda5c437f0 6767 /* Bit definition for Ethernet MAC Address2 Low Register */
mbed_official 133:d4dda5c437f0 6768 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
mbed_official 133:d4dda5c437f0 6769
mbed_official 133:d4dda5c437f0 6770 /* Bit definition for Ethernet MAC Address3 High Register */
mbed_official 133:d4dda5c437f0 6771 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
mbed_official 133:d4dda5c437f0 6772 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
mbed_official 133:d4dda5c437f0 6773 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
mbed_official 133:d4dda5c437f0 6774 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
mbed_official 133:d4dda5c437f0 6775 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
mbed_official 133:d4dda5c437f0 6776 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
mbed_official 133:d4dda5c437f0 6777 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
mbed_official 133:d4dda5c437f0 6778 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
mbed_official 133:d4dda5c437f0 6779 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
mbed_official 133:d4dda5c437f0 6780 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
mbed_official 133:d4dda5c437f0 6781
mbed_official 133:d4dda5c437f0 6782 /* Bit definition for Ethernet MAC Address3 Low Register */
mbed_official 133:d4dda5c437f0 6783 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
mbed_official 133:d4dda5c437f0 6784
mbed_official 133:d4dda5c437f0 6785 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6786 /* Ethernet MMC Registers bits definition */
mbed_official 133:d4dda5c437f0 6787 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6788
mbed_official 133:d4dda5c437f0 6789 /* Bit definition for Ethernet MMC Contol Register */
mbed_official 133:d4dda5c437f0 6790 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
mbed_official 133:d4dda5c437f0 6791 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
mbed_official 133:d4dda5c437f0 6792 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
mbed_official 133:d4dda5c437f0 6793 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
mbed_official 133:d4dda5c437f0 6794 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
mbed_official 133:d4dda5c437f0 6795 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
mbed_official 133:d4dda5c437f0 6796
mbed_official 133:d4dda5c437f0 6797 /* Bit definition for Ethernet MMC Receive Interrupt Register */
mbed_official 133:d4dda5c437f0 6798 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
mbed_official 133:d4dda5c437f0 6799 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
mbed_official 133:d4dda5c437f0 6800 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
mbed_official 133:d4dda5c437f0 6801
mbed_official 133:d4dda5c437f0 6802 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
mbed_official 133:d4dda5c437f0 6803 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
mbed_official 133:d4dda5c437f0 6804 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
mbed_official 133:d4dda5c437f0 6805 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
mbed_official 133:d4dda5c437f0 6806
mbed_official 133:d4dda5c437f0 6807 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
mbed_official 133:d4dda5c437f0 6808 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
mbed_official 133:d4dda5c437f0 6809 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
mbed_official 133:d4dda5c437f0 6810 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
mbed_official 133:d4dda5c437f0 6811
mbed_official 133:d4dda5c437f0 6812 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
mbed_official 133:d4dda5c437f0 6813 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
mbed_official 133:d4dda5c437f0 6814 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
mbed_official 133:d4dda5c437f0 6815 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
mbed_official 133:d4dda5c437f0 6816
mbed_official 133:d4dda5c437f0 6817 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
mbed_official 133:d4dda5c437f0 6818 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
mbed_official 133:d4dda5c437f0 6819
mbed_official 133:d4dda5c437f0 6820 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
mbed_official 133:d4dda5c437f0 6821 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
mbed_official 133:d4dda5c437f0 6822
mbed_official 133:d4dda5c437f0 6823 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
mbed_official 133:d4dda5c437f0 6824 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
mbed_official 133:d4dda5c437f0 6825
mbed_official 133:d4dda5c437f0 6826 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
mbed_official 133:d4dda5c437f0 6827 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
mbed_official 133:d4dda5c437f0 6828
mbed_official 133:d4dda5c437f0 6829 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
mbed_official 133:d4dda5c437f0 6830 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
mbed_official 133:d4dda5c437f0 6831
mbed_official 133:d4dda5c437f0 6832 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
mbed_official 133:d4dda5c437f0 6833 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
mbed_official 133:d4dda5c437f0 6834
mbed_official 133:d4dda5c437f0 6835 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6836 /* Ethernet PTP Registers bits definition */
mbed_official 133:d4dda5c437f0 6837 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6838
mbed_official 133:d4dda5c437f0 6839 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
mbed_official 133:d4dda5c437f0 6840 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
mbed_official 133:d4dda5c437f0 6841 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
mbed_official 133:d4dda5c437f0 6842 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
mbed_official 133:d4dda5c437f0 6843 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
mbed_official 133:d4dda5c437f0 6844 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
mbed_official 133:d4dda5c437f0 6845 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
mbed_official 133:d4dda5c437f0 6846 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
mbed_official 133:d4dda5c437f0 6847 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
mbed_official 133:d4dda5c437f0 6848 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
mbed_official 133:d4dda5c437f0 6849
mbed_official 133:d4dda5c437f0 6850 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
mbed_official 133:d4dda5c437f0 6851 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
mbed_official 133:d4dda5c437f0 6852 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
mbed_official 133:d4dda5c437f0 6853 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
mbed_official 133:d4dda5c437f0 6854 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
mbed_official 133:d4dda5c437f0 6855 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
mbed_official 133:d4dda5c437f0 6856
mbed_official 133:d4dda5c437f0 6857 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
mbed_official 133:d4dda5c437f0 6858 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
mbed_official 133:d4dda5c437f0 6859
mbed_official 133:d4dda5c437f0 6860 /* Bit definition for Ethernet PTP Time Stamp High Register */
mbed_official 133:d4dda5c437f0 6861 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
mbed_official 133:d4dda5c437f0 6862
mbed_official 133:d4dda5c437f0 6863 /* Bit definition for Ethernet PTP Time Stamp Low Register */
mbed_official 133:d4dda5c437f0 6864 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
mbed_official 133:d4dda5c437f0 6865 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
mbed_official 133:d4dda5c437f0 6866
mbed_official 133:d4dda5c437f0 6867 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
mbed_official 133:d4dda5c437f0 6868 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
mbed_official 133:d4dda5c437f0 6869
mbed_official 133:d4dda5c437f0 6870 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
mbed_official 133:d4dda5c437f0 6871 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
mbed_official 133:d4dda5c437f0 6872 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
mbed_official 133:d4dda5c437f0 6873
mbed_official 133:d4dda5c437f0 6874 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
mbed_official 133:d4dda5c437f0 6875 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
mbed_official 133:d4dda5c437f0 6876
mbed_official 133:d4dda5c437f0 6877 /* Bit definition for Ethernet PTP Target Time High Register */
mbed_official 133:d4dda5c437f0 6878 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
mbed_official 133:d4dda5c437f0 6879
mbed_official 133:d4dda5c437f0 6880 /* Bit definition for Ethernet PTP Target Time Low Register */
mbed_official 133:d4dda5c437f0 6881 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
mbed_official 133:d4dda5c437f0 6882
mbed_official 133:d4dda5c437f0 6883 /* Bit definition for Ethernet PTP Time Stamp Status Register */
mbed_official 133:d4dda5c437f0 6884 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
mbed_official 133:d4dda5c437f0 6885 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
mbed_official 133:d4dda5c437f0 6886
mbed_official 133:d4dda5c437f0 6887 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6888 /* Ethernet DMA Registers bits definition */
mbed_official 133:d4dda5c437f0 6889 /******************************************************************************/
mbed_official 133:d4dda5c437f0 6890
mbed_official 133:d4dda5c437f0 6891 /* Bit definition for Ethernet DMA Bus Mode Register */
mbed_official 133:d4dda5c437f0 6892 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
mbed_official 133:d4dda5c437f0 6893 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
mbed_official 133:d4dda5c437f0 6894 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
mbed_official 133:d4dda5c437f0 6895 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
mbed_official 133:d4dda5c437f0 6896 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
mbed_official 133:d4dda5c437f0 6897 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
mbed_official 133:d4dda5c437f0 6898 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
mbed_official 133:d4dda5c437f0 6899 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
mbed_official 133:d4dda5c437f0 6900 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
mbed_official 133:d4dda5c437f0 6901 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
mbed_official 133:d4dda5c437f0 6902 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
mbed_official 133:d4dda5c437f0 6903 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
mbed_official 133:d4dda5c437f0 6904 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
mbed_official 133:d4dda5c437f0 6905 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
mbed_official 133:d4dda5c437f0 6906 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
mbed_official 133:d4dda5c437f0 6907 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
mbed_official 133:d4dda5c437f0 6908 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
mbed_official 133:d4dda5c437f0 6909 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
mbed_official 133:d4dda5c437f0 6910 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
mbed_official 133:d4dda5c437f0 6911 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
mbed_official 133:d4dda5c437f0 6912 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
mbed_official 133:d4dda5c437f0 6913 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
mbed_official 133:d4dda5c437f0 6914 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
mbed_official 133:d4dda5c437f0 6915 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
mbed_official 133:d4dda5c437f0 6916 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
mbed_official 133:d4dda5c437f0 6917 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
mbed_official 133:d4dda5c437f0 6918 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
mbed_official 133:d4dda5c437f0 6919 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
mbed_official 133:d4dda5c437f0 6920 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
mbed_official 133:d4dda5c437f0 6921 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
mbed_official 133:d4dda5c437f0 6922 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
mbed_official 133:d4dda5c437f0 6923 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
mbed_official 133:d4dda5c437f0 6924 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
mbed_official 133:d4dda5c437f0 6925 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
mbed_official 133:d4dda5c437f0 6926 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
mbed_official 133:d4dda5c437f0 6927 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
mbed_official 133:d4dda5c437f0 6928 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
mbed_official 133:d4dda5c437f0 6929 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
mbed_official 133:d4dda5c437f0 6930 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
mbed_official 133:d4dda5c437f0 6931
mbed_official 133:d4dda5c437f0 6932 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
mbed_official 133:d4dda5c437f0 6933 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
mbed_official 133:d4dda5c437f0 6934
mbed_official 133:d4dda5c437f0 6935 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
mbed_official 133:d4dda5c437f0 6936 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
mbed_official 133:d4dda5c437f0 6937
mbed_official 133:d4dda5c437f0 6938 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
mbed_official 133:d4dda5c437f0 6939 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
mbed_official 133:d4dda5c437f0 6940
mbed_official 133:d4dda5c437f0 6941 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
mbed_official 133:d4dda5c437f0 6942 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
mbed_official 133:d4dda5c437f0 6943
mbed_official 133:d4dda5c437f0 6944 /* Bit definition for Ethernet DMA Status Register */
mbed_official 133:d4dda5c437f0 6945 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
mbed_official 133:d4dda5c437f0 6946 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
mbed_official 133:d4dda5c437f0 6947 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
mbed_official 133:d4dda5c437f0 6948 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
mbed_official 133:d4dda5c437f0 6949 /* combination with EBS[2:0] for GetFlagStatus function */
mbed_official 133:d4dda5c437f0 6950 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
mbed_official 133:d4dda5c437f0 6951 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
mbed_official 133:d4dda5c437f0 6952 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
mbed_official 133:d4dda5c437f0 6953 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
mbed_official 133:d4dda5c437f0 6954 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
mbed_official 133:d4dda5c437f0 6955 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
mbed_official 133:d4dda5c437f0 6956 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
mbed_official 133:d4dda5c437f0 6957 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
mbed_official 133:d4dda5c437f0 6958 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
mbed_official 133:d4dda5c437f0 6959 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
mbed_official 133:d4dda5c437f0 6960 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
mbed_official 133:d4dda5c437f0 6961 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
mbed_official 133:d4dda5c437f0 6962 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
mbed_official 133:d4dda5c437f0 6963 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
mbed_official 133:d4dda5c437f0 6964 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
mbed_official 133:d4dda5c437f0 6965 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
mbed_official 133:d4dda5c437f0 6966 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
mbed_official 133:d4dda5c437f0 6967 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
mbed_official 133:d4dda5c437f0 6968 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
mbed_official 133:d4dda5c437f0 6969 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
mbed_official 133:d4dda5c437f0 6970 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
mbed_official 133:d4dda5c437f0 6971 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
mbed_official 133:d4dda5c437f0 6972 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
mbed_official 133:d4dda5c437f0 6973 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
mbed_official 133:d4dda5c437f0 6974 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
mbed_official 133:d4dda5c437f0 6975 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
mbed_official 133:d4dda5c437f0 6976 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
mbed_official 133:d4dda5c437f0 6977 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
mbed_official 133:d4dda5c437f0 6978 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
mbed_official 133:d4dda5c437f0 6979 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
mbed_official 133:d4dda5c437f0 6980 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
mbed_official 133:d4dda5c437f0 6981 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
mbed_official 133:d4dda5c437f0 6982
mbed_official 133:d4dda5c437f0 6983 /* Bit definition for Ethernet DMA Operation Mode Register */
mbed_official 133:d4dda5c437f0 6984 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
mbed_official 133:d4dda5c437f0 6985 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
mbed_official 133:d4dda5c437f0 6986 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
mbed_official 133:d4dda5c437f0 6987 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
mbed_official 133:d4dda5c437f0 6988 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
mbed_official 133:d4dda5c437f0 6989 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
mbed_official 133:d4dda5c437f0 6990 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
mbed_official 133:d4dda5c437f0 6991 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
mbed_official 133:d4dda5c437f0 6992 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
mbed_official 133:d4dda5c437f0 6993 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
mbed_official 133:d4dda5c437f0 6994 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
mbed_official 133:d4dda5c437f0 6995 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
mbed_official 133:d4dda5c437f0 6996 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
mbed_official 133:d4dda5c437f0 6997 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
mbed_official 133:d4dda5c437f0 6998 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
mbed_official 133:d4dda5c437f0 6999 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
mbed_official 133:d4dda5c437f0 7000 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
mbed_official 133:d4dda5c437f0 7001 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
mbed_official 133:d4dda5c437f0 7002 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
mbed_official 133:d4dda5c437f0 7003 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
mbed_official 133:d4dda5c437f0 7004 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
mbed_official 133:d4dda5c437f0 7005 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
mbed_official 133:d4dda5c437f0 7006 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
mbed_official 133:d4dda5c437f0 7007 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
mbed_official 133:d4dda5c437f0 7008
mbed_official 133:d4dda5c437f0 7009 /* Bit definition for Ethernet DMA Interrupt Enable Register */
mbed_official 133:d4dda5c437f0 7010 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
mbed_official 133:d4dda5c437f0 7011 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
mbed_official 133:d4dda5c437f0 7012 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
mbed_official 133:d4dda5c437f0 7013 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
mbed_official 133:d4dda5c437f0 7014 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
mbed_official 133:d4dda5c437f0 7015 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
mbed_official 133:d4dda5c437f0 7016 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
mbed_official 133:d4dda5c437f0 7017 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
mbed_official 133:d4dda5c437f0 7018 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
mbed_official 133:d4dda5c437f0 7019 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
mbed_official 133:d4dda5c437f0 7020 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
mbed_official 133:d4dda5c437f0 7021 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
mbed_official 133:d4dda5c437f0 7022 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
mbed_official 133:d4dda5c437f0 7023 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
mbed_official 133:d4dda5c437f0 7024 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
mbed_official 133:d4dda5c437f0 7025
mbed_official 133:d4dda5c437f0 7026 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
mbed_official 133:d4dda5c437f0 7027 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
mbed_official 133:d4dda5c437f0 7028 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
mbed_official 133:d4dda5c437f0 7029 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
mbed_official 133:d4dda5c437f0 7030 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
mbed_official 133:d4dda5c437f0 7031
mbed_official 133:d4dda5c437f0 7032 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
mbed_official 133:d4dda5c437f0 7033 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
mbed_official 133:d4dda5c437f0 7034
mbed_official 133:d4dda5c437f0 7035 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
mbed_official 133:d4dda5c437f0 7036 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
mbed_official 133:d4dda5c437f0 7037
mbed_official 133:d4dda5c437f0 7038 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
mbed_official 133:d4dda5c437f0 7039 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
mbed_official 133:d4dda5c437f0 7040
mbed_official 133:d4dda5c437f0 7041 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
mbed_official 133:d4dda5c437f0 7042 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
mbed_official 133:d4dda5c437f0 7043
mbed_official 133:d4dda5c437f0 7044 /******************************************************************************/
mbed_official 133:d4dda5c437f0 7045 /* */
mbed_official 133:d4dda5c437f0 7046 /* USB_OTG */
mbed_official 133:d4dda5c437f0 7047 /* */
mbed_official 133:d4dda5c437f0 7048 /******************************************************************************/
mbed_official 133:d4dda5c437f0 7049 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
mbed_official 133:d4dda5c437f0 7050 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
mbed_official 133:d4dda5c437f0 7051 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
mbed_official 133:d4dda5c437f0 7052 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
mbed_official 133:d4dda5c437f0 7053 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
mbed_official 133:d4dda5c437f0 7054 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
mbed_official 133:d4dda5c437f0 7055 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
mbed_official 133:d4dda5c437f0 7056 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
mbed_official 133:d4dda5c437f0 7057 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
mbed_official 133:d4dda5c437f0 7058 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
mbed_official 133:d4dda5c437f0 7059 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
mbed_official 133:d4dda5c437f0 7060
mbed_official 133:d4dda5c437f0 7061 /******************** Bit definition forUSB_OTG_HCFG register ********************/
mbed_official 133:d4dda5c437f0 7062
mbed_official 133:d4dda5c437f0 7063 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
mbed_official 133:d4dda5c437f0 7064 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7065 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7066 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
mbed_official 133:d4dda5c437f0 7067
mbed_official 133:d4dda5c437f0 7068 /******************** Bit definition forUSB_OTG_DCFG register ********************/
mbed_official 133:d4dda5c437f0 7069
mbed_official 133:d4dda5c437f0 7070 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
mbed_official 133:d4dda5c437f0 7071 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7072 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7073 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
mbed_official 133:d4dda5c437f0 7074
mbed_official 133:d4dda5c437f0 7075 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
mbed_official 133:d4dda5c437f0 7076 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7077 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7078 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7079 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7080 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 7081 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 7082 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 7083
mbed_official 133:d4dda5c437f0 7084 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
mbed_official 133:d4dda5c437f0 7085 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7086 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7087
mbed_official 133:d4dda5c437f0 7088 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
mbed_official 133:d4dda5c437f0 7089 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7090 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7091
mbed_official 133:d4dda5c437f0 7092 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
mbed_official 133:d4dda5c437f0 7093 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
mbed_official 133:d4dda5c437f0 7094 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
mbed_official 133:d4dda5c437f0 7095 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
mbed_official 133:d4dda5c437f0 7096
mbed_official 133:d4dda5c437f0 7097 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
mbed_official 133:d4dda5c437f0 7098 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
mbed_official 133:d4dda5c437f0 7099 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
mbed_official 133:d4dda5c437f0 7100 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
mbed_official 133:d4dda5c437f0 7101 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
mbed_official 133:d4dda5c437f0 7102 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
mbed_official 133:d4dda5c437f0 7103 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
mbed_official 133:d4dda5c437f0 7104
mbed_official 133:d4dda5c437f0 7105 /******************** Bit definition forUSB_OTG_DCTL register ********************/
mbed_official 133:d4dda5c437f0 7106 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
mbed_official 133:d4dda5c437f0 7107 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
mbed_official 133:d4dda5c437f0 7108 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
mbed_official 133:d4dda5c437f0 7109 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
mbed_official 133:d4dda5c437f0 7110
mbed_official 133:d4dda5c437f0 7111 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
mbed_official 133:d4dda5c437f0 7112 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7113 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7114 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7115 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
mbed_official 133:d4dda5c437f0 7116 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
mbed_official 133:d4dda5c437f0 7117 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
mbed_official 133:d4dda5c437f0 7118 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
mbed_official 133:d4dda5c437f0 7119 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
mbed_official 133:d4dda5c437f0 7120
mbed_official 133:d4dda5c437f0 7121 /******************** Bit definition forUSB_OTG_HFIR register ********************/
mbed_official 133:d4dda5c437f0 7122 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
mbed_official 133:d4dda5c437f0 7123
mbed_official 133:d4dda5c437f0 7124 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
mbed_official 133:d4dda5c437f0 7125 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
mbed_official 133:d4dda5c437f0 7126 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
mbed_official 133:d4dda5c437f0 7127
mbed_official 133:d4dda5c437f0 7128 /******************** Bit definition forUSB_OTG_DSTS register ********************/
mbed_official 133:d4dda5c437f0 7129 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
mbed_official 133:d4dda5c437f0 7130
mbed_official 133:d4dda5c437f0 7131 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
mbed_official 133:d4dda5c437f0 7132 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7133 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7134 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
mbed_official 133:d4dda5c437f0 7135 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
mbed_official 133:d4dda5c437f0 7136
mbed_official 133:d4dda5c437f0 7137 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
mbed_official 133:d4dda5c437f0 7138 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
mbed_official 133:d4dda5c437f0 7139
mbed_official 133:d4dda5c437f0 7140 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
mbed_official 133:d4dda5c437f0 7141 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7142 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7143 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7144 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7145 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
mbed_official 133:d4dda5c437f0 7146 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
mbed_official 133:d4dda5c437f0 7147 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
mbed_official 133:d4dda5c437f0 7148
mbed_official 133:d4dda5c437f0 7149 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
mbed_official 133:d4dda5c437f0 7150
mbed_official 133:d4dda5c437f0 7151 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
mbed_official 133:d4dda5c437f0 7152 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7153 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7154 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7155 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
mbed_official 133:d4dda5c437f0 7156 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
mbed_official 133:d4dda5c437f0 7157 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
mbed_official 133:d4dda5c437f0 7158
mbed_official 133:d4dda5c437f0 7159 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
mbed_official 133:d4dda5c437f0 7160 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7161 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7162 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7163 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7164 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
mbed_official 133:d4dda5c437f0 7165 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
mbed_official 133:d4dda5c437f0 7166 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
mbed_official 133:d4dda5c437f0 7167 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
mbed_official 133:d4dda5c437f0 7168 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
mbed_official 133:d4dda5c437f0 7169 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
mbed_official 133:d4dda5c437f0 7170 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
mbed_official 133:d4dda5c437f0 7171 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
mbed_official 133:d4dda5c437f0 7172 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
mbed_official 133:d4dda5c437f0 7173 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
mbed_official 133:d4dda5c437f0 7174 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
mbed_official 133:d4dda5c437f0 7175 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
mbed_official 133:d4dda5c437f0 7176 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
mbed_official 133:d4dda5c437f0 7177
mbed_official 133:d4dda5c437f0 7178 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
mbed_official 133:d4dda5c437f0 7179 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
mbed_official 133:d4dda5c437f0 7180 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
mbed_official 133:d4dda5c437f0 7181 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
mbed_official 133:d4dda5c437f0 7182 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
mbed_official 133:d4dda5c437f0 7183 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
mbed_official 133:d4dda5c437f0 7184
mbed_official 133:d4dda5c437f0 7185 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
mbed_official 133:d4dda5c437f0 7186 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7187 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7188 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7189 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7190 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 7191 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
mbed_official 133:d4dda5c437f0 7192 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
mbed_official 133:d4dda5c437f0 7193
mbed_official 133:d4dda5c437f0 7194 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
mbed_official 133:d4dda5c437f0 7195 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 133:d4dda5c437f0 7196 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 133:d4dda5c437f0 7197 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
mbed_official 133:d4dda5c437f0 7198 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 133:d4dda5c437f0 7199 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 133:d4dda5c437f0 7200 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 133:d4dda5c437f0 7201 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
mbed_official 133:d4dda5c437f0 7202 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 133:d4dda5c437f0 7203
mbed_official 133:d4dda5c437f0 7204 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
mbed_official 133:d4dda5c437f0 7205 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
mbed_official 133:d4dda5c437f0 7206
mbed_official 133:d4dda5c437f0 7207 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
mbed_official 133:d4dda5c437f0 7208 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7209 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7210 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7211 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7212 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 7213 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 7214 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 7215 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 7216
mbed_official 133:d4dda5c437f0 7217 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
mbed_official 133:d4dda5c437f0 7218 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7219 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7220 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7221 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7222 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 7223 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 7224 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 7225 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 7226
mbed_official 133:d4dda5c437f0 7227 /******************** Bit definition forUSB_OTG_HAINT register ********************/
mbed_official 133:d4dda5c437f0 7228 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
mbed_official 133:d4dda5c437f0 7229
mbed_official 133:d4dda5c437f0 7230 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
mbed_official 133:d4dda5c437f0 7231 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 133:d4dda5c437f0 7232 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 133:d4dda5c437f0 7233 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
mbed_official 133:d4dda5c437f0 7234 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
mbed_official 133:d4dda5c437f0 7235 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
mbed_official 133:d4dda5c437f0 7236 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
mbed_official 133:d4dda5c437f0 7237 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 133:d4dda5c437f0 7238
mbed_official 133:d4dda5c437f0 7239 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
mbed_official 133:d4dda5c437f0 7240 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
mbed_official 133:d4dda5c437f0 7241 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
mbed_official 133:d4dda5c437f0 7242 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
mbed_official 133:d4dda5c437f0 7243 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
mbed_official 133:d4dda5c437f0 7244 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
mbed_official 133:d4dda5c437f0 7245 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
mbed_official 133:d4dda5c437f0 7246 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
mbed_official 133:d4dda5c437f0 7247 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
mbed_official 133:d4dda5c437f0 7248 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
mbed_official 133:d4dda5c437f0 7249 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
mbed_official 133:d4dda5c437f0 7250 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
mbed_official 133:d4dda5c437f0 7251 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
mbed_official 133:d4dda5c437f0 7252 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
mbed_official 133:d4dda5c437f0 7253 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
mbed_official 133:d4dda5c437f0 7254 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
mbed_official 133:d4dda5c437f0 7255 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
mbed_official 133:d4dda5c437f0 7256 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
mbed_official 133:d4dda5c437f0 7257 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
mbed_official 133:d4dda5c437f0 7258 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
mbed_official 133:d4dda5c437f0 7259 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
mbed_official 133:d4dda5c437f0 7260 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
mbed_official 133:d4dda5c437f0 7261 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
mbed_official 133:d4dda5c437f0 7262 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
mbed_official 133:d4dda5c437f0 7263 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
mbed_official 133:d4dda5c437f0 7264 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
mbed_official 133:d4dda5c437f0 7265 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
mbed_official 133:d4dda5c437f0 7266
mbed_official 133:d4dda5c437f0 7267 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
mbed_official 133:d4dda5c437f0 7268 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
mbed_official 133:d4dda5c437f0 7269 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
mbed_official 133:d4dda5c437f0 7270 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
mbed_official 133:d4dda5c437f0 7271 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
mbed_official 133:d4dda5c437f0 7272 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
mbed_official 133:d4dda5c437f0 7273 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
mbed_official 133:d4dda5c437f0 7274 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
mbed_official 133:d4dda5c437f0 7275 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
mbed_official 133:d4dda5c437f0 7276 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
mbed_official 133:d4dda5c437f0 7277 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
mbed_official 133:d4dda5c437f0 7278 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
mbed_official 133:d4dda5c437f0 7279 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
mbed_official 133:d4dda5c437f0 7280 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
mbed_official 133:d4dda5c437f0 7281 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
mbed_official 133:d4dda5c437f0 7282 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
mbed_official 133:d4dda5c437f0 7283 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
mbed_official 133:d4dda5c437f0 7284 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
mbed_official 133:d4dda5c437f0 7285 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
mbed_official 133:d4dda5c437f0 7286 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
mbed_official 133:d4dda5c437f0 7287 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
mbed_official 133:d4dda5c437f0 7288 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
mbed_official 133:d4dda5c437f0 7289 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
mbed_official 133:d4dda5c437f0 7290 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
mbed_official 133:d4dda5c437f0 7291 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
mbed_official 133:d4dda5c437f0 7292 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
mbed_official 133:d4dda5c437f0 7293 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
mbed_official 133:d4dda5c437f0 7294
mbed_official 133:d4dda5c437f0 7295 /******************** Bit definition forUSB_OTG_DAINT register ********************/
mbed_official 133:d4dda5c437f0 7296 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
mbed_official 133:d4dda5c437f0 7297 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
mbed_official 133:d4dda5c437f0 7298
mbed_official 133:d4dda5c437f0 7299 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
mbed_official 133:d4dda5c437f0 7300 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
mbed_official 133:d4dda5c437f0 7301
mbed_official 133:d4dda5c437f0 7302 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
mbed_official 133:d4dda5c437f0 7303 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
mbed_official 133:d4dda5c437f0 7304 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
mbed_official 133:d4dda5c437f0 7305 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
mbed_official 133:d4dda5c437f0 7306 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
mbed_official 133:d4dda5c437f0 7307
mbed_official 133:d4dda5c437f0 7308 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
mbed_official 133:d4dda5c437f0 7309 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
mbed_official 133:d4dda5c437f0 7310 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
mbed_official 133:d4dda5c437f0 7311
mbed_official 133:d4dda5c437f0 7312 /******************** Bit definition for OTG register ********************/
mbed_official 133:d4dda5c437f0 7313
mbed_official 133:d4dda5c437f0 7314 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
mbed_official 133:d4dda5c437f0 7315 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7316 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7317 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7318 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7319 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
mbed_official 133:d4dda5c437f0 7320
mbed_official 133:d4dda5c437f0 7321 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
mbed_official 133:d4dda5c437f0 7322 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7323 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7324
mbed_official 133:d4dda5c437f0 7325 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
mbed_official 133:d4dda5c437f0 7326 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7327 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7328 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7329 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7330
mbed_official 133:d4dda5c437f0 7331 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
mbed_official 133:d4dda5c437f0 7332 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7333 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7334 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7335 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7336
mbed_official 133:d4dda5c437f0 7337 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
mbed_official 133:d4dda5c437f0 7338 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7339 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7340 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7341 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7342
mbed_official 133:d4dda5c437f0 7343 /******************** Bit definition for OTG register ********************/
mbed_official 133:d4dda5c437f0 7344
mbed_official 133:d4dda5c437f0 7345 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
mbed_official 133:d4dda5c437f0 7346 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7347 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7348 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7349 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7350 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
mbed_official 133:d4dda5c437f0 7351
mbed_official 133:d4dda5c437f0 7352 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
mbed_official 133:d4dda5c437f0 7353 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7354 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7355
mbed_official 133:d4dda5c437f0 7356 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
mbed_official 133:d4dda5c437f0 7357 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7358 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7359 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7360 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7361
mbed_official 133:d4dda5c437f0 7362 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
mbed_official 133:d4dda5c437f0 7363 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7364 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7365 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7366 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7367
mbed_official 133:d4dda5c437f0 7368 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
mbed_official 133:d4dda5c437f0 7369 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7370 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7371 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7372 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7373
mbed_official 133:d4dda5c437f0 7374 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
mbed_official 133:d4dda5c437f0 7375 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
mbed_official 133:d4dda5c437f0 7376
mbed_official 133:d4dda5c437f0 7377 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
mbed_official 133:d4dda5c437f0 7378 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
mbed_official 133:d4dda5c437f0 7379
mbed_official 133:d4dda5c437f0 7380 /******************** Bit definition for OTG register ********************/
mbed_official 133:d4dda5c437f0 7381 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
mbed_official 133:d4dda5c437f0 7382 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
mbed_official 133:d4dda5c437f0 7383 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
mbed_official 133:d4dda5c437f0 7384 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
mbed_official 133:d4dda5c437f0 7385
mbed_official 133:d4dda5c437f0 7386 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
mbed_official 133:d4dda5c437f0 7387 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
mbed_official 133:d4dda5c437f0 7388
mbed_official 133:d4dda5c437f0 7389 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
mbed_official 133:d4dda5c437f0 7390 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
mbed_official 133:d4dda5c437f0 7391
mbed_official 133:d4dda5c437f0 7392 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
mbed_official 133:d4dda5c437f0 7393 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7394 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7395 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7396 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7397 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 7398 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 7399 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 7400 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 7401
mbed_official 133:d4dda5c437f0 7402 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
mbed_official 133:d4dda5c437f0 7403 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7404 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7405 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7406 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7407 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 7408 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 7409 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 7410
mbed_official 133:d4dda5c437f0 7411 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
mbed_official 133:d4dda5c437f0 7412 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
mbed_official 133:d4dda5c437f0 7413 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
mbed_official 133:d4dda5c437f0 7414
mbed_official 133:d4dda5c437f0 7415 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
mbed_official 133:d4dda5c437f0 7416 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7417 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7418 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7419 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7420 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 7421 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 7422 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 7423 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 7424 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
mbed_official 133:d4dda5c437f0 7425 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
mbed_official 133:d4dda5c437f0 7426
mbed_official 133:d4dda5c437f0 7427 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
mbed_official 133:d4dda5c437f0 7428 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7429 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7430 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7431 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7432 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 7433 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 7434 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 7435 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
mbed_official 133:d4dda5c437f0 7436 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
mbed_official 133:d4dda5c437f0 7437 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
mbed_official 133:d4dda5c437f0 7438
mbed_official 133:d4dda5c437f0 7439 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
mbed_official 133:d4dda5c437f0 7440 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
mbed_official 133:d4dda5c437f0 7441
mbed_official 133:d4dda5c437f0 7442 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
mbed_official 133:d4dda5c437f0 7443 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
mbed_official 133:d4dda5c437f0 7444 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
mbed_official 133:d4dda5c437f0 7445
mbed_official 133:d4dda5c437f0 7446 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
mbed_official 133:d4dda5c437f0 7447 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
mbed_official 133:d4dda5c437f0 7448 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
mbed_official 133:d4dda5c437f0 7449 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
mbed_official 133:d4dda5c437f0 7450 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
mbed_official 133:d4dda5c437f0 7451 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
mbed_official 133:d4dda5c437f0 7452 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
mbed_official 133:d4dda5c437f0 7453
mbed_official 133:d4dda5c437f0 7454 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
mbed_official 133:d4dda5c437f0 7455 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
mbed_official 133:d4dda5c437f0 7456 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
mbed_official 133:d4dda5c437f0 7457
mbed_official 133:d4dda5c437f0 7458 /******************** Bit definition forUSB_OTG_CID register ********************/
mbed_official 133:d4dda5c437f0 7459 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
mbed_official 133:d4dda5c437f0 7460
mbed_official 133:d4dda5c437f0 7461 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
mbed_official 133:d4dda5c437f0 7462 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 133:d4dda5c437f0 7463 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 133:d4dda5c437f0 7464 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
mbed_official 133:d4dda5c437f0 7465 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 133:d4dda5c437f0 7466 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 133:d4dda5c437f0 7467 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 133:d4dda5c437f0 7468 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
mbed_official 133:d4dda5c437f0 7469 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 133:d4dda5c437f0 7470 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
mbed_official 133:d4dda5c437f0 7471
mbed_official 133:d4dda5c437f0 7472 /******************** Bit definition forUSB_OTG_HPRT register ********************/
mbed_official 133:d4dda5c437f0 7473 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
mbed_official 133:d4dda5c437f0 7474 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
mbed_official 133:d4dda5c437f0 7475 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
mbed_official 133:d4dda5c437f0 7476 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
mbed_official 133:d4dda5c437f0 7477 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
mbed_official 133:d4dda5c437f0 7478 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
mbed_official 133:d4dda5c437f0 7479 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
mbed_official 133:d4dda5c437f0 7480 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
mbed_official 133:d4dda5c437f0 7481 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
mbed_official 133:d4dda5c437f0 7482
mbed_official 133:d4dda5c437f0 7483 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
mbed_official 133:d4dda5c437f0 7484 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7485 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7486 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
mbed_official 133:d4dda5c437f0 7487
mbed_official 133:d4dda5c437f0 7488 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
mbed_official 133:d4dda5c437f0 7489 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7490 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7491 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7492 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7493
mbed_official 133:d4dda5c437f0 7494 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
mbed_official 133:d4dda5c437f0 7495 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7496 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7497
mbed_official 133:d4dda5c437f0 7498 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
mbed_official 133:d4dda5c437f0 7499 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 133:d4dda5c437f0 7500 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 133:d4dda5c437f0 7501 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
mbed_official 133:d4dda5c437f0 7502 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 133:d4dda5c437f0 7503 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 133:d4dda5c437f0 7504 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 133:d4dda5c437f0 7505 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
mbed_official 133:d4dda5c437f0 7506 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 133:d4dda5c437f0 7507 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
mbed_official 133:d4dda5c437f0 7508 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
mbed_official 133:d4dda5c437f0 7509 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
mbed_official 133:d4dda5c437f0 7510
mbed_official 133:d4dda5c437f0 7511 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
mbed_official 133:d4dda5c437f0 7512 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
mbed_official 133:d4dda5c437f0 7513 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
mbed_official 133:d4dda5c437f0 7514
mbed_official 133:d4dda5c437f0 7515 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
mbed_official 133:d4dda5c437f0 7516 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
mbed_official 133:d4dda5c437f0 7517 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
mbed_official 133:d4dda5c437f0 7518 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
mbed_official 133:d4dda5c437f0 7519 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
mbed_official 133:d4dda5c437f0 7520
mbed_official 133:d4dda5c437f0 7521 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 133:d4dda5c437f0 7522 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7523 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7524 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
mbed_official 133:d4dda5c437f0 7525
mbed_official 133:d4dda5c437f0 7526 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
mbed_official 133:d4dda5c437f0 7527 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7528 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7529 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7530 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7531 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
mbed_official 133:d4dda5c437f0 7532 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
mbed_official 133:d4dda5c437f0 7533 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
mbed_official 133:d4dda5c437f0 7534 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
mbed_official 133:d4dda5c437f0 7535 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
mbed_official 133:d4dda5c437f0 7536 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
mbed_official 133:d4dda5c437f0 7537
mbed_official 133:d4dda5c437f0 7538 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
mbed_official 133:d4dda5c437f0 7539 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
mbed_official 133:d4dda5c437f0 7540
mbed_official 133:d4dda5c437f0 7541 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
mbed_official 133:d4dda5c437f0 7542 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7543 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7544 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7545 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7546 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
mbed_official 133:d4dda5c437f0 7547 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
mbed_official 133:d4dda5c437f0 7548
mbed_official 133:d4dda5c437f0 7549 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 133:d4dda5c437f0 7550 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7551 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7552
mbed_official 133:d4dda5c437f0 7553 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
mbed_official 133:d4dda5c437f0 7554 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7555 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7556
mbed_official 133:d4dda5c437f0 7557 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
mbed_official 133:d4dda5c437f0 7558 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7559 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7560 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7561 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7562 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 7563 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 7564 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 7565 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
mbed_official 133:d4dda5c437f0 7566 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
mbed_official 133:d4dda5c437f0 7567 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
mbed_official 133:d4dda5c437f0 7568
mbed_official 133:d4dda5c437f0 7569 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
mbed_official 133:d4dda5c437f0 7570
mbed_official 133:d4dda5c437f0 7571 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
mbed_official 133:d4dda5c437f0 7572 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7573 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7574 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7575 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7576 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 7577 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 7578 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 7579
mbed_official 133:d4dda5c437f0 7580 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
mbed_official 133:d4dda5c437f0 7581 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7582 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7583 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
mbed_official 133:d4dda5c437f0 7584 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
mbed_official 133:d4dda5c437f0 7585 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
mbed_official 133:d4dda5c437f0 7586 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
mbed_official 133:d4dda5c437f0 7587 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
mbed_official 133:d4dda5c437f0 7588
mbed_official 133:d4dda5c437f0 7589 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
mbed_official 133:d4dda5c437f0 7590 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7591 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7592 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
mbed_official 133:d4dda5c437f0 7593 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
mbed_official 133:d4dda5c437f0 7594
mbed_official 133:d4dda5c437f0 7595 /******************** Bit definition forUSB_OTG_HCINT register ********************/
mbed_official 133:d4dda5c437f0 7596 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
mbed_official 133:d4dda5c437f0 7597 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
mbed_official 133:d4dda5c437f0 7598 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
mbed_official 133:d4dda5c437f0 7599 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
mbed_official 133:d4dda5c437f0 7600 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
mbed_official 133:d4dda5c437f0 7601 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
mbed_official 133:d4dda5c437f0 7602 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
mbed_official 133:d4dda5c437f0 7603 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
mbed_official 133:d4dda5c437f0 7604 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
mbed_official 133:d4dda5c437f0 7605 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
mbed_official 133:d4dda5c437f0 7606 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
mbed_official 133:d4dda5c437f0 7607
mbed_official 133:d4dda5c437f0 7608 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
mbed_official 133:d4dda5c437f0 7609 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
mbed_official 133:d4dda5c437f0 7610 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
mbed_official 133:d4dda5c437f0 7611 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
mbed_official 133:d4dda5c437f0 7612 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
mbed_official 133:d4dda5c437f0 7613 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
mbed_official 133:d4dda5c437f0 7614 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
mbed_official 133:d4dda5c437f0 7615 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
mbed_official 133:d4dda5c437f0 7616 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
mbed_official 133:d4dda5c437f0 7617 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
mbed_official 133:d4dda5c437f0 7618 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
mbed_official 133:d4dda5c437f0 7619 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
mbed_official 133:d4dda5c437f0 7620
mbed_official 133:d4dda5c437f0 7621 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
mbed_official 133:d4dda5c437f0 7622 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
mbed_official 133:d4dda5c437f0 7623 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
mbed_official 133:d4dda5c437f0 7624 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
mbed_official 133:d4dda5c437f0 7625 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
mbed_official 133:d4dda5c437f0 7626 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
mbed_official 133:d4dda5c437f0 7627 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
mbed_official 133:d4dda5c437f0 7628 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
mbed_official 133:d4dda5c437f0 7629 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
mbed_official 133:d4dda5c437f0 7630 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
mbed_official 133:d4dda5c437f0 7631 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
mbed_official 133:d4dda5c437f0 7632 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
mbed_official 133:d4dda5c437f0 7633
mbed_official 133:d4dda5c437f0 7634 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
mbed_official 133:d4dda5c437f0 7635
mbed_official 133:d4dda5c437f0 7636 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 133:d4dda5c437f0 7637 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 133:d4dda5c437f0 7638 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
mbed_official 133:d4dda5c437f0 7639 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
mbed_official 133:d4dda5c437f0 7640 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 133:d4dda5c437f0 7641 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 133:d4dda5c437f0 7642 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
mbed_official 133:d4dda5c437f0 7643 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
mbed_official 133:d4dda5c437f0 7644 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7645 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7646
mbed_official 133:d4dda5c437f0 7647 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
mbed_official 133:d4dda5c437f0 7648 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
mbed_official 133:d4dda5c437f0 7649
mbed_official 133:d4dda5c437f0 7650 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
mbed_official 133:d4dda5c437f0 7651 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
mbed_official 133:d4dda5c437f0 7652
mbed_official 133:d4dda5c437f0 7653 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
mbed_official 133:d4dda5c437f0 7654 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
mbed_official 133:d4dda5c437f0 7655
mbed_official 133:d4dda5c437f0 7656 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
mbed_official 133:d4dda5c437f0 7657 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
mbed_official 133:d4dda5c437f0 7658 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
mbed_official 133:d4dda5c437f0 7659
mbed_official 133:d4dda5c437f0 7660 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
mbed_official 133:d4dda5c437f0 7661
mbed_official 133:d4dda5c437f0 7662 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7663 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
mbed_official 133:d4dda5c437f0 7664 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
mbed_official 133:d4dda5c437f0 7665 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
mbed_official 133:d4dda5c437f0 7666 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
mbed_official 133:d4dda5c437f0 7667 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 133:d4dda5c437f0 7668 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7669 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7670 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
mbed_official 133:d4dda5c437f0 7671 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
mbed_official 133:d4dda5c437f0 7672 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
mbed_official 133:d4dda5c437f0 7673 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
mbed_official 133:d4dda5c437f0 7674 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
mbed_official 133:d4dda5c437f0 7675 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
mbed_official 133:d4dda5c437f0 7676
mbed_official 133:d4dda5c437f0 7677 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
mbed_official 133:d4dda5c437f0 7678 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
mbed_official 133:d4dda5c437f0 7679 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
mbed_official 133:d4dda5c437f0 7680 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
mbed_official 133:d4dda5c437f0 7681 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
mbed_official 133:d4dda5c437f0 7682 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
mbed_official 133:d4dda5c437f0 7683 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
mbed_official 133:d4dda5c437f0 7684
mbed_official 133:d4dda5c437f0 7685 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
mbed_official 133:d4dda5c437f0 7686
mbed_official 133:d4dda5c437f0 7687 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 133:d4dda5c437f0 7688 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 133:d4dda5c437f0 7689
mbed_official 133:d4dda5c437f0 7690 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
mbed_official 133:d4dda5c437f0 7691 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7692 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7693
mbed_official 133:d4dda5c437f0 7694 /******************** Bit definition for PCGCCTL register ********************/
mbed_official 133:d4dda5c437f0 7695 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
mbed_official 133:d4dda5c437f0 7696 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 133:d4dda5c437f0 7697 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 133:d4dda5c437f0 7698
mbed_official 133:d4dda5c437f0 7699 /**
mbed_official 133:d4dda5c437f0 7700 * @}
mbed_official 133:d4dda5c437f0 7701 */
mbed_official 133:d4dda5c437f0 7702
mbed_official 133:d4dda5c437f0 7703 /**
mbed_official 133:d4dda5c437f0 7704 * @}
mbed_official 133:d4dda5c437f0 7705 */
mbed_official 133:d4dda5c437f0 7706
mbed_official 133:d4dda5c437f0 7707 /** @addtogroup Exported_macros
mbed_official 133:d4dda5c437f0 7708 * @{
mbed_official 133:d4dda5c437f0 7709 */
mbed_official 133:d4dda5c437f0 7710
mbed_official 133:d4dda5c437f0 7711 /******************************* ADC Instances ********************************/
mbed_official 133:d4dda5c437f0 7712 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
mbed_official 133:d4dda5c437f0 7713 ((INSTANCE) == ADC2) || \
mbed_official 133:d4dda5c437f0 7714 ((INSTANCE) == ADC3))
mbed_official 133:d4dda5c437f0 7715
mbed_official 133:d4dda5c437f0 7716 /******************************* CAN Instances ********************************/
mbed_official 133:d4dda5c437f0 7717 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
mbed_official 133:d4dda5c437f0 7718 ((INSTANCE) == CAN2))
mbed_official 133:d4dda5c437f0 7719
mbed_official 133:d4dda5c437f0 7720 /******************************* CRC Instances ********************************/
mbed_official 133:d4dda5c437f0 7721 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 133:d4dda5c437f0 7722
mbed_official 133:d4dda5c437f0 7723 /******************************* DAC Instances ********************************/
mbed_official 133:d4dda5c437f0 7724 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
mbed_official 133:d4dda5c437f0 7725
mbed_official 133:d4dda5c437f0 7726 /******************************* DCMI Instances *******************************/
mbed_official 133:d4dda5c437f0 7727 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
mbed_official 133:d4dda5c437f0 7728
mbed_official 133:d4dda5c437f0 7729 /******************************** DMA Instances *******************************/
mbed_official 133:d4dda5c437f0 7730 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
mbed_official 133:d4dda5c437f0 7731 ((INSTANCE) == DMA1_Stream1) || \
mbed_official 133:d4dda5c437f0 7732 ((INSTANCE) == DMA1_Stream2) || \
mbed_official 133:d4dda5c437f0 7733 ((INSTANCE) == DMA1_Stream3) || \
mbed_official 133:d4dda5c437f0 7734 ((INSTANCE) == DMA1_Stream4) || \
mbed_official 133:d4dda5c437f0 7735 ((INSTANCE) == DMA1_Stream5) || \
mbed_official 133:d4dda5c437f0 7736 ((INSTANCE) == DMA1_Stream6) || \
mbed_official 133:d4dda5c437f0 7737 ((INSTANCE) == DMA1_Stream7) || \
mbed_official 133:d4dda5c437f0 7738 ((INSTANCE) == DMA2_Stream0) || \
mbed_official 133:d4dda5c437f0 7739 ((INSTANCE) == DMA2_Stream1) || \
mbed_official 133:d4dda5c437f0 7740 ((INSTANCE) == DMA2_Stream2) || \
mbed_official 133:d4dda5c437f0 7741 ((INSTANCE) == DMA2_Stream3) || \
mbed_official 133:d4dda5c437f0 7742 ((INSTANCE) == DMA2_Stream4) || \
mbed_official 133:d4dda5c437f0 7743 ((INSTANCE) == DMA2_Stream5) || \
mbed_official 133:d4dda5c437f0 7744 ((INSTANCE) == DMA2_Stream6) || \
mbed_official 133:d4dda5c437f0 7745 ((INSTANCE) == DMA2_Stream7))
mbed_official 133:d4dda5c437f0 7746
mbed_official 133:d4dda5c437f0 7747 /******************************* GPIO Instances *******************************/
mbed_official 133:d4dda5c437f0 7748 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 133:d4dda5c437f0 7749 ((INSTANCE) == GPIOB) || \
mbed_official 133:d4dda5c437f0 7750 ((INSTANCE) == GPIOC) || \
mbed_official 133:d4dda5c437f0 7751 ((INSTANCE) == GPIOD) || \
mbed_official 133:d4dda5c437f0 7752 ((INSTANCE) == GPIOE) || \
mbed_official 133:d4dda5c437f0 7753 ((INSTANCE) == GPIOF) || \
mbed_official 133:d4dda5c437f0 7754 ((INSTANCE) == GPIOG) || \
mbed_official 133:d4dda5c437f0 7755 ((INSTANCE) == GPIOH) || \
mbed_official 133:d4dda5c437f0 7756 ((INSTANCE) == GPIOI))
mbed_official 133:d4dda5c437f0 7757
mbed_official 133:d4dda5c437f0 7758 /******************************** I2C Instances *******************************/
mbed_official 133:d4dda5c437f0 7759 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 133:d4dda5c437f0 7760 ((INSTANCE) == I2C2) || \
mbed_official 133:d4dda5c437f0 7761 ((INSTANCE) == I2C3))
mbed_official 133:d4dda5c437f0 7762
mbed_official 133:d4dda5c437f0 7763 /******************************** I2S Instances *******************************/
mbed_official 532:fe11edbda85c 7764 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
mbed_official 532:fe11edbda85c 7765 ((INSTANCE) == SPI3))
mbed_official 133:d4dda5c437f0 7766
mbed_official 133:d4dda5c437f0 7767 /*************************** I2S Extended Instances ***************************/
mbed_official 532:fe11edbda85c 7768 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
mbed_official 532:fe11edbda85c 7769 ((INSTANCE) == SPI3) || \
mbed_official 532:fe11edbda85c 7770 ((INSTANCE) == I2S2ext) || \
mbed_official 532:fe11edbda85c 7771 ((INSTANCE) == I2S3ext))
mbed_official 133:d4dda5c437f0 7772
mbed_official 133:d4dda5c437f0 7773 /******************************* RNG Instances ********************************/
mbed_official 133:d4dda5c437f0 7774 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
mbed_official 133:d4dda5c437f0 7775
mbed_official 133:d4dda5c437f0 7776 /****************************** RTC Instances *********************************/
mbed_official 133:d4dda5c437f0 7777 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 133:d4dda5c437f0 7778
mbed_official 133:d4dda5c437f0 7779 /******************************** SPI Instances *******************************/
mbed_official 133:d4dda5c437f0 7780 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 133:d4dda5c437f0 7781 ((INSTANCE) == SPI2) || \
mbed_official 133:d4dda5c437f0 7782 ((INSTANCE) == SPI3))
mbed_official 133:d4dda5c437f0 7783
mbed_official 133:d4dda5c437f0 7784 /*************************** SPI Extended Instances ***************************/
mbed_official 133:d4dda5c437f0 7785 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 133:d4dda5c437f0 7786 ((INSTANCE) == SPI2) || \
mbed_official 133:d4dda5c437f0 7787 ((INSTANCE) == SPI3) || \
mbed_official 133:d4dda5c437f0 7788 ((INSTANCE) == I2S2ext) || \
mbed_official 133:d4dda5c437f0 7789 ((INSTANCE) == I2S3ext))
mbed_official 133:d4dda5c437f0 7790
mbed_official 133:d4dda5c437f0 7791 /****************** TIM Instances : All supported instances *******************/
mbed_official 133:d4dda5c437f0 7792 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 133:d4dda5c437f0 7793 ((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7794 ((INSTANCE) == TIM3) || \
mbed_official 133:d4dda5c437f0 7795 ((INSTANCE) == TIM4) || \
mbed_official 133:d4dda5c437f0 7796 ((INSTANCE) == TIM5) || \
mbed_official 133:d4dda5c437f0 7797 ((INSTANCE) == TIM6) || \
mbed_official 133:d4dda5c437f0 7798 ((INSTANCE) == TIM7) || \
mbed_official 133:d4dda5c437f0 7799 ((INSTANCE) == TIM8) || \
mbed_official 133:d4dda5c437f0 7800 ((INSTANCE) == TIM9) || \
mbed_official 133:d4dda5c437f0 7801 ((INSTANCE) == TIM10) || \
mbed_official 133:d4dda5c437f0 7802 ((INSTANCE) == TIM11) || \
mbed_official 133:d4dda5c437f0 7803 ((INSTANCE) == TIM12) || \
mbed_official 133:d4dda5c437f0 7804 ((INSTANCE) == TIM13) || \
mbed_official 133:d4dda5c437f0 7805 ((INSTANCE) == TIM14))
mbed_official 133:d4dda5c437f0 7806
mbed_official 133:d4dda5c437f0 7807 /************* TIM Instances : at least 1 capture/compare channel *************/
mbed_official 133:d4dda5c437f0 7808 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 133:d4dda5c437f0 7809 ((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7810 ((INSTANCE) == TIM3) || \
mbed_official 133:d4dda5c437f0 7811 ((INSTANCE) == TIM4) || \
mbed_official 133:d4dda5c437f0 7812 ((INSTANCE) == TIM5) || \
mbed_official 133:d4dda5c437f0 7813 ((INSTANCE) == TIM8) || \
mbed_official 133:d4dda5c437f0 7814 ((INSTANCE) == TIM9) || \
mbed_official 133:d4dda5c437f0 7815 ((INSTANCE) == TIM10) || \
mbed_official 133:d4dda5c437f0 7816 ((INSTANCE) == TIM11) || \
mbed_official 133:d4dda5c437f0 7817 ((INSTANCE) == TIM12) || \
mbed_official 133:d4dda5c437f0 7818 ((INSTANCE) == TIM13) || \
mbed_official 133:d4dda5c437f0 7819 ((INSTANCE) == TIM14))
mbed_official 133:d4dda5c437f0 7820
mbed_official 133:d4dda5c437f0 7821 /************ TIM Instances : at least 2 capture/compare channels *************/
mbed_official 133:d4dda5c437f0 7822 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 133:d4dda5c437f0 7823 ((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7824 ((INSTANCE) == TIM3) || \
mbed_official 133:d4dda5c437f0 7825 ((INSTANCE) == TIM4) || \
mbed_official 133:d4dda5c437f0 7826 ((INSTANCE) == TIM5) || \
mbed_official 133:d4dda5c437f0 7827 ((INSTANCE) == TIM8) || \
mbed_official 133:d4dda5c437f0 7828 ((INSTANCE) == TIM9) || \
mbed_official 133:d4dda5c437f0 7829 ((INSTANCE) == TIM12))
mbed_official 133:d4dda5c437f0 7830
mbed_official 133:d4dda5c437f0 7831 /************ TIM Instances : at least 3 capture/compare channels *************/
mbed_official 133:d4dda5c437f0 7832 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 133:d4dda5c437f0 7833 ((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7834 ((INSTANCE) == TIM3) || \
mbed_official 133:d4dda5c437f0 7835 ((INSTANCE) == TIM4) || \
mbed_official 133:d4dda5c437f0 7836 ((INSTANCE) == TIM5) || \
mbed_official 133:d4dda5c437f0 7837 ((INSTANCE) == TIM8))
mbed_official 133:d4dda5c437f0 7838
mbed_official 133:d4dda5c437f0 7839 /************ TIM Instances : at least 4 capture/compare channels *************/
mbed_official 133:d4dda5c437f0 7840 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 133:d4dda5c437f0 7841 ((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7842 ((INSTANCE) == TIM3) || \
mbed_official 133:d4dda5c437f0 7843 ((INSTANCE) == TIM4) || \
mbed_official 133:d4dda5c437f0 7844 ((INSTANCE) == TIM5) || \
mbed_official 133:d4dda5c437f0 7845 ((INSTANCE) == TIM8))
mbed_official 133:d4dda5c437f0 7846
mbed_official 133:d4dda5c437f0 7847 /******************** TIM Instances : Advanced-control timers *****************/
mbed_official 133:d4dda5c437f0 7848 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 133:d4dda5c437f0 7849 ((INSTANCE) == TIM8))
mbed_official 133:d4dda5c437f0 7850
mbed_official 133:d4dda5c437f0 7851 /******************* TIM Instances : Timer input XOR function *****************/
mbed_official 133:d4dda5c437f0 7852 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 133:d4dda5c437f0 7853 ((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7854 ((INSTANCE) == TIM3) || \
mbed_official 133:d4dda5c437f0 7855 ((INSTANCE) == TIM4) || \
mbed_official 133:d4dda5c437f0 7856 ((INSTANCE) == TIM5) || \
mbed_official 133:d4dda5c437f0 7857 ((INSTANCE) == TIM8))
mbed_official 133:d4dda5c437f0 7858
mbed_official 133:d4dda5c437f0 7859 /****************** TIM Instances : DMA requests generation (UDE) *************/
mbed_official 133:d4dda5c437f0 7860 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 133:d4dda5c437f0 7861 ((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7862 ((INSTANCE) == TIM3) || \
mbed_official 133:d4dda5c437f0 7863 ((INSTANCE) == TIM4) || \
mbed_official 133:d4dda5c437f0 7864 ((INSTANCE) == TIM5) || \
mbed_official 133:d4dda5c437f0 7865 ((INSTANCE) == TIM6) || \
mbed_official 133:d4dda5c437f0 7866 ((INSTANCE) == TIM7) || \
mbed_official 133:d4dda5c437f0 7867 ((INSTANCE) == TIM8))
mbed_official 133:d4dda5c437f0 7868
mbed_official 133:d4dda5c437f0 7869 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
mbed_official 133:d4dda5c437f0 7870 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 133:d4dda5c437f0 7871 ((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7872 ((INSTANCE) == TIM3) || \
mbed_official 133:d4dda5c437f0 7873 ((INSTANCE) == TIM4) || \
mbed_official 133:d4dda5c437f0 7874 ((INSTANCE) == TIM5) || \
mbed_official 133:d4dda5c437f0 7875 ((INSTANCE) == TIM8))
mbed_official 133:d4dda5c437f0 7876
mbed_official 133:d4dda5c437f0 7877 /************ TIM Instances : DMA requests generation (COMDE) *****************/
mbed_official 133:d4dda5c437f0 7878 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 133:d4dda5c437f0 7879 ((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7880 ((INSTANCE) == TIM3) || \
mbed_official 133:d4dda5c437f0 7881 ((INSTANCE) == TIM4) || \
mbed_official 133:d4dda5c437f0 7882 ((INSTANCE) == TIM5) || \
mbed_official 133:d4dda5c437f0 7883 ((INSTANCE) == TIM8))
mbed_official 133:d4dda5c437f0 7884
mbed_official 133:d4dda5c437f0 7885 /******************** TIM Instances : DMA burst feature ***********************/
mbed_official 133:d4dda5c437f0 7886 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 133:d4dda5c437f0 7887 ((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7888 ((INSTANCE) == TIM3) || \
mbed_official 133:d4dda5c437f0 7889 ((INSTANCE) == TIM4) || \
mbed_official 133:d4dda5c437f0 7890 ((INSTANCE) == TIM5) || \
mbed_official 133:d4dda5c437f0 7891 ((INSTANCE) == TIM8))
mbed_official 133:d4dda5c437f0 7892
mbed_official 133:d4dda5c437f0 7893 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
mbed_official 133:d4dda5c437f0 7894 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 133:d4dda5c437f0 7895 ((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7896 ((INSTANCE) == TIM3) || \
mbed_official 133:d4dda5c437f0 7897 ((INSTANCE) == TIM4) || \
mbed_official 133:d4dda5c437f0 7898 ((INSTANCE) == TIM5) || \
mbed_official 133:d4dda5c437f0 7899 ((INSTANCE) == TIM6) || \
mbed_official 133:d4dda5c437f0 7900 ((INSTANCE) == TIM7) || \
mbed_official 133:d4dda5c437f0 7901 ((INSTANCE) == TIM8) || \
mbed_official 133:d4dda5c437f0 7902 ((INSTANCE) == TIM9) || \
mbed_official 133:d4dda5c437f0 7903 ((INSTANCE) == TIM12))
mbed_official 133:d4dda5c437f0 7904
mbed_official 133:d4dda5c437f0 7905 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
mbed_official 133:d4dda5c437f0 7906 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 133:d4dda5c437f0 7907 ((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7908 ((INSTANCE) == TIM3) || \
mbed_official 133:d4dda5c437f0 7909 ((INSTANCE) == TIM4) || \
mbed_official 133:d4dda5c437f0 7910 ((INSTANCE) == TIM5) || \
mbed_official 133:d4dda5c437f0 7911 ((INSTANCE) == TIM8) || \
mbed_official 133:d4dda5c437f0 7912 ((INSTANCE) == TIM9) || \
mbed_official 133:d4dda5c437f0 7913 ((INSTANCE) == TIM12))
mbed_official 133:d4dda5c437f0 7914
mbed_official 133:d4dda5c437f0 7915 /********************** TIM Instances : 32 bit Counter ************************/
mbed_official 133:d4dda5c437f0 7916 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7917 ((INSTANCE) == TIM5))
mbed_official 133:d4dda5c437f0 7918
mbed_official 133:d4dda5c437f0 7919 /***************** TIM Instances : external trigger input availabe ************/
mbed_official 133:d4dda5c437f0 7920 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 133:d4dda5c437f0 7921 ((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7922 ((INSTANCE) == TIM3) || \
mbed_official 133:d4dda5c437f0 7923 ((INSTANCE) == TIM4) || \
mbed_official 133:d4dda5c437f0 7924 ((INSTANCE) == TIM5) || \
mbed_official 133:d4dda5c437f0 7925 ((INSTANCE) == TIM8))
mbed_official 133:d4dda5c437f0 7926
mbed_official 133:d4dda5c437f0 7927 /****************** TIM Instances : remapping capability **********************/
mbed_official 133:d4dda5c437f0 7928 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 133:d4dda5c437f0 7929 ((INSTANCE) == TIM5) || \
mbed_official 133:d4dda5c437f0 7930 ((INSTANCE) == TIM11))
mbed_official 133:d4dda5c437f0 7931
mbed_official 133:d4dda5c437f0 7932 /******************* TIM Instances : output(s) available **********************/
mbed_official 133:d4dda5c437f0 7933 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 133:d4dda5c437f0 7934 ((((INSTANCE) == TIM1) && \
mbed_official 133:d4dda5c437f0 7935 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 133:d4dda5c437f0 7936 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 133:d4dda5c437f0 7937 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 133:d4dda5c437f0 7938 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 133:d4dda5c437f0 7939 || \
mbed_official 133:d4dda5c437f0 7940 (((INSTANCE) == TIM2) && \
mbed_official 133:d4dda5c437f0 7941 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 133:d4dda5c437f0 7942 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 133:d4dda5c437f0 7943 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 133:d4dda5c437f0 7944 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 133:d4dda5c437f0 7945 || \
mbed_official 133:d4dda5c437f0 7946 (((INSTANCE) == TIM3) && \
mbed_official 133:d4dda5c437f0 7947 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 133:d4dda5c437f0 7948 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 133:d4dda5c437f0 7949 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 133:d4dda5c437f0 7950 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 133:d4dda5c437f0 7951 || \
mbed_official 133:d4dda5c437f0 7952 (((INSTANCE) == TIM4) && \
mbed_official 133:d4dda5c437f0 7953 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 133:d4dda5c437f0 7954 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 133:d4dda5c437f0 7955 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 133:d4dda5c437f0 7956 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 133:d4dda5c437f0 7957 || \
mbed_official 133:d4dda5c437f0 7958 (((INSTANCE) == TIM5) && \
mbed_official 133:d4dda5c437f0 7959 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 133:d4dda5c437f0 7960 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 133:d4dda5c437f0 7961 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 133:d4dda5c437f0 7962 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 133:d4dda5c437f0 7963 || \
mbed_official 133:d4dda5c437f0 7964 (((INSTANCE) == TIM8) && \
mbed_official 133:d4dda5c437f0 7965 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 133:d4dda5c437f0 7966 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 133:d4dda5c437f0 7967 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 133:d4dda5c437f0 7968 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 133:d4dda5c437f0 7969 || \
mbed_official 133:d4dda5c437f0 7970 (((INSTANCE) == TIM9) && \
mbed_official 133:d4dda5c437f0 7971 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 133:d4dda5c437f0 7972 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 133:d4dda5c437f0 7973 || \
mbed_official 133:d4dda5c437f0 7974 (((INSTANCE) == TIM10) && \
mbed_official 133:d4dda5c437f0 7975 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 133:d4dda5c437f0 7976 || \
mbed_official 133:d4dda5c437f0 7977 (((INSTANCE) == TIM11) && \
mbed_official 133:d4dda5c437f0 7978 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 133:d4dda5c437f0 7979 || \
mbed_official 133:d4dda5c437f0 7980 (((INSTANCE) == TIM12) && \
mbed_official 133:d4dda5c437f0 7981 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 133:d4dda5c437f0 7982 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 133:d4dda5c437f0 7983 || \
mbed_official 133:d4dda5c437f0 7984 (((INSTANCE) == TIM13) && \
mbed_official 133:d4dda5c437f0 7985 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 133:d4dda5c437f0 7986 || \
mbed_official 133:d4dda5c437f0 7987 (((INSTANCE) == TIM14) && \
mbed_official 133:d4dda5c437f0 7988 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 133:d4dda5c437f0 7989
mbed_official 133:d4dda5c437f0 7990 /************ TIM Instances : complementary output(s) available ***************/
mbed_official 133:d4dda5c437f0 7991 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 133:d4dda5c437f0 7992 ((((INSTANCE) == TIM1) && \
mbed_official 133:d4dda5c437f0 7993 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 133:d4dda5c437f0 7994 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 133:d4dda5c437f0 7995 ((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official 133:d4dda5c437f0 7996 || \
mbed_official 133:d4dda5c437f0 7997 (((INSTANCE) == TIM8) && \
mbed_official 133:d4dda5c437f0 7998 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 133:d4dda5c437f0 7999 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 133:d4dda5c437f0 8000 ((CHANNEL) == TIM_CHANNEL_3))))
mbed_official 133:d4dda5c437f0 8001
mbed_official 133:d4dda5c437f0 8002 /******************** USART Instances : Synchronous mode **********************/
mbed_official 133:d4dda5c437f0 8003 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 133:d4dda5c437f0 8004 ((INSTANCE) == USART2) || \
mbed_official 133:d4dda5c437f0 8005 ((INSTANCE) == USART3) || \
mbed_official 133:d4dda5c437f0 8006 ((INSTANCE) == USART6))
mbed_official 133:d4dda5c437f0 8007
mbed_official 133:d4dda5c437f0 8008 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 133:d4dda5c437f0 8009 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 133:d4dda5c437f0 8010 ((INSTANCE) == USART2) || \
mbed_official 133:d4dda5c437f0 8011 ((INSTANCE) == USART3) || \
mbed_official 133:d4dda5c437f0 8012 ((INSTANCE) == UART4) || \
mbed_official 133:d4dda5c437f0 8013 ((INSTANCE) == UART5) || \
mbed_official 133:d4dda5c437f0 8014 ((INSTANCE) == USART6))
mbed_official 133:d4dda5c437f0 8015
mbed_official 133:d4dda5c437f0 8016 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 133:d4dda5c437f0 8017 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 133:d4dda5c437f0 8018 ((INSTANCE) == USART2) || \
mbed_official 133:d4dda5c437f0 8019 ((INSTANCE) == USART3) || \
mbed_official 133:d4dda5c437f0 8020 ((INSTANCE) == USART6))
mbed_official 133:d4dda5c437f0 8021
mbed_official 133:d4dda5c437f0 8022 /********************* UART Instances : Smard card mode ***********************/
mbed_official 133:d4dda5c437f0 8023 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 133:d4dda5c437f0 8024 ((INSTANCE) == USART2) || \
mbed_official 133:d4dda5c437f0 8025 ((INSTANCE) == USART3) || \
mbed_official 133:d4dda5c437f0 8026 ((INSTANCE) == USART6))
mbed_official 133:d4dda5c437f0 8027
mbed_official 133:d4dda5c437f0 8028 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 133:d4dda5c437f0 8029 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 133:d4dda5c437f0 8030 ((INSTANCE) == USART2) || \
mbed_official 133:d4dda5c437f0 8031 ((INSTANCE) == USART3) || \
mbed_official 133:d4dda5c437f0 8032 ((INSTANCE) == UART4) || \
mbed_official 133:d4dda5c437f0 8033 ((INSTANCE) == UART5) || \
mbed_official 133:d4dda5c437f0 8034 ((INSTANCE) == USART6))
mbed_official 133:d4dda5c437f0 8035
mbed_official 133:d4dda5c437f0 8036 /****************************** IWDG Instances ********************************/
mbed_official 133:d4dda5c437f0 8037 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 133:d4dda5c437f0 8038
mbed_official 133:d4dda5c437f0 8039 /****************************** WWDG Instances ********************************/
mbed_official 133:d4dda5c437f0 8040 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 133:d4dda5c437f0 8041
mbed_official 532:fe11edbda85c 8042 /****************************** SDIO Instances ********************************/
mbed_official 532:fe11edbda85c 8043 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
mbed_official 532:fe11edbda85c 8044
mbed_official 532:fe11edbda85c 8045 /****************************** USB Exported Constants ************************/
mbed_official 532:fe11edbda85c 8046 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
mbed_official 532:fe11edbda85c 8047 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
mbed_official 532:fe11edbda85c 8048 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
mbed_official 532:fe11edbda85c 8049 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
mbed_official 532:fe11edbda85c 8050
mbed_official 532:fe11edbda85c 8051 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
mbed_official 532:fe11edbda85c 8052 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
mbed_official 532:fe11edbda85c 8053 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
mbed_official 532:fe11edbda85c 8054 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
mbed_official 532:fe11edbda85c 8055
mbed_official 242:7074e42da0b2 8056 /******************************************************************************/
mbed_official 242:7074e42da0b2 8057 /* For a painless codes migration between the STM32F4xx device product */
mbed_official 242:7074e42da0b2 8058 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 242:7074e42da0b2 8059 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 242:7074e42da0b2 8060 /* No need to update developed interrupt code when moving across */
mbed_official 242:7074e42da0b2 8061 /* product lines within the same STM32F4 Family */
mbed_official 242:7074e42da0b2 8062 /******************************************************************************/
mbed_official 242:7074e42da0b2 8063
mbed_official 242:7074e42da0b2 8064 /* Aliases for __IRQn */
mbed_official 242:7074e42da0b2 8065 #define FMC_IRQn FSMC_IRQn
mbed_official 242:7074e42da0b2 8066
mbed_official 242:7074e42da0b2 8067 /* Aliases for __IRQHandler */
mbed_official 242:7074e42da0b2 8068 #define FMC_IRQHandler FSMC_IRQHandler
mbed_official 133:d4dda5c437f0 8069
mbed_official 133:d4dda5c437f0 8070 /**
mbed_official 133:d4dda5c437f0 8071 * @}
mbed_official 133:d4dda5c437f0 8072 */
mbed_official 133:d4dda5c437f0 8073
mbed_official 133:d4dda5c437f0 8074 /**
mbed_official 133:d4dda5c437f0 8075 * @}
mbed_official 133:d4dda5c437f0 8076 */
mbed_official 133:d4dda5c437f0 8077
mbed_official 133:d4dda5c437f0 8078 /**
mbed_official 133:d4dda5c437f0 8079 * @}
mbed_official 133:d4dda5c437f0 8080 */
mbed_official 133:d4dda5c437f0 8081
mbed_official 133:d4dda5c437f0 8082 #ifdef __cplusplus
mbed_official 133:d4dda5c437f0 8083 }
mbed_official 133:d4dda5c437f0 8084 #endif /* __cplusplus */
mbed_official 133:d4dda5c437f0 8085
mbed_official 133:d4dda5c437f0 8086 #endif /* __STM32F407xx_H */
mbed_official 133:d4dda5c437f0 8087
mbed_official 133:d4dda5c437f0 8088
mbed_official 133:d4dda5c437f0 8089
mbed_official 133:d4dda5c437f0 8090 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/