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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc0.h@592:a274ee790e56, 2015-07-17 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 17 09:15:10 2015 +0100
- Revision:
- 592:a274ee790e56
- Parent:
- 579:53297373a894
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6
Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/
More API implementation for SAMR21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 579:53297373a894 | 1 | #ifndef _SAMD21_TCC0_INSTANCE_ |
| mbed_official | 579:53297373a894 | 2 | #define _SAMD21_TCC0_INSTANCE_ |
| mbed_official | 579:53297373a894 | 3 | |
| mbed_official | 579:53297373a894 | 4 | /* ========== Register definition for TCC0 peripheral ========== */ |
| mbed_official | 579:53297373a894 | 5 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 6 | #define REG_TCC0_CTRLA (0x42002000U) /**< \brief (TCC0) Control A */ |
| mbed_official | 579:53297373a894 | 7 | #define REG_TCC0_CTRLBCLR (0x42002004U) /**< \brief (TCC0) Control B Clear */ |
| mbed_official | 579:53297373a894 | 8 | #define REG_TCC0_CTRLBSET (0x42002005U) /**< \brief (TCC0) Control B Set */ |
| mbed_official | 579:53297373a894 | 9 | #define REG_TCC0_SYNCBUSY (0x42002008U) /**< \brief (TCC0) Synchronization Busy */ |
| mbed_official | 579:53297373a894 | 10 | #define REG_TCC0_FCTRLA (0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ |
| mbed_official | 579:53297373a894 | 11 | #define REG_TCC0_FCTRLB (0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */ |
| mbed_official | 579:53297373a894 | 12 | #define REG_TCC0_WEXCTRL (0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */ |
| mbed_official | 579:53297373a894 | 13 | #define REG_TCC0_DRVCTRL (0x42002018U) /**< \brief (TCC0) Driver Control */ |
| mbed_official | 579:53297373a894 | 14 | #define REG_TCC0_DBGCTRL (0x4200201EU) /**< \brief (TCC0) Debug Control */ |
| mbed_official | 579:53297373a894 | 15 | #define REG_TCC0_EVCTRL (0x42002020U) /**< \brief (TCC0) Event Control */ |
| mbed_official | 579:53297373a894 | 16 | #define REG_TCC0_INTENCLR (0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 17 | #define REG_TCC0_INTENSET (0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 18 | #define REG_TCC0_INTFLAG (0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 19 | #define REG_TCC0_STATUS (0x42002030U) /**< \brief (TCC0) Status */ |
| mbed_official | 579:53297373a894 | 20 | #define REG_TCC0_COUNT (0x42002034U) /**< \brief (TCC0) Count */ |
| mbed_official | 579:53297373a894 | 21 | #define REG_TCC0_PATT (0x42002038U) /**< \brief (TCC0) Pattern */ |
| mbed_official | 579:53297373a894 | 22 | #define REG_TCC0_WAVE (0x4200203CU) /**< \brief (TCC0) Waveform Control */ |
| mbed_official | 579:53297373a894 | 23 | #define REG_TCC0_PER (0x42002040U) /**< \brief (TCC0) Period */ |
| mbed_official | 579:53297373a894 | 24 | #define REG_TCC0_CC0 (0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */ |
| mbed_official | 579:53297373a894 | 25 | #define REG_TCC0_CC1 (0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */ |
| mbed_official | 579:53297373a894 | 26 | #define REG_TCC0_CC2 (0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */ |
| mbed_official | 579:53297373a894 | 27 | #define REG_TCC0_CC3 (0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */ |
| mbed_official | 579:53297373a894 | 28 | #define REG_TCC0_PATTB (0x42002064U) /**< \brief (TCC0) Pattern Buffer */ |
| mbed_official | 579:53297373a894 | 29 | #define REG_TCC0_WAVEB (0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */ |
| mbed_official | 579:53297373a894 | 30 | #define REG_TCC0_PERB (0x4200206CU) /**< \brief (TCC0) Period Buffer */ |
| mbed_official | 579:53297373a894 | 31 | #define REG_TCC0_CCB0 (0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ |
| mbed_official | 579:53297373a894 | 32 | #define REG_TCC0_CCB1 (0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ |
| mbed_official | 579:53297373a894 | 33 | #define REG_TCC0_CCB2 (0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ |
| mbed_official | 579:53297373a894 | 34 | #define REG_TCC0_CCB3 (0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ |
| mbed_official | 579:53297373a894 | 35 | #else |
| mbed_official | 579:53297373a894 | 36 | #define REG_TCC0_CTRLA (*(RwReg *)0x42002000U) /**< \brief (TCC0) Control A */ |
| mbed_official | 579:53297373a894 | 37 | #define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TCC0) Control B Clear */ |
| mbed_official | 579:53297373a894 | 38 | #define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TCC0) Control B Set */ |
| mbed_official | 579:53297373a894 | 39 | #define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002008U) /**< \brief (TCC0) Synchronization Busy */ |
| mbed_official | 579:53297373a894 | 40 | #define REG_TCC0_FCTRLA (*(RwReg *)0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ |
| mbed_official | 579:53297373a894 | 41 | #define REG_TCC0_FCTRLB (*(RwReg *)0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */ |
| mbed_official | 579:53297373a894 | 42 | #define REG_TCC0_WEXCTRL (*(RwReg *)0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */ |
| mbed_official | 579:53297373a894 | 43 | #define REG_TCC0_DRVCTRL (*(RwReg *)0x42002018U) /**< \brief (TCC0) Driver Control */ |
| mbed_official | 579:53297373a894 | 44 | #define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200201EU) /**< \brief (TCC0) Debug Control */ |
| mbed_official | 579:53297373a894 | 45 | #define REG_TCC0_EVCTRL (*(RwReg *)0x42002020U) /**< \brief (TCC0) Event Control */ |
| mbed_official | 579:53297373a894 | 46 | #define REG_TCC0_INTENCLR (*(RwReg *)0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 47 | #define REG_TCC0_INTENSET (*(RwReg *)0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 48 | #define REG_TCC0_INTFLAG (*(RwReg *)0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 49 | #define REG_TCC0_STATUS (*(RwReg *)0x42002030U) /**< \brief (TCC0) Status */ |
| mbed_official | 579:53297373a894 | 50 | #define REG_TCC0_COUNT (*(RwReg *)0x42002034U) /**< \brief (TCC0) Count */ |
| mbed_official | 579:53297373a894 | 51 | #define REG_TCC0_PATT (*(RwReg16*)0x42002038U) /**< \brief (TCC0) Pattern */ |
| mbed_official | 579:53297373a894 | 52 | #define REG_TCC0_WAVE (*(RwReg *)0x4200203CU) /**< \brief (TCC0) Waveform Control */ |
| mbed_official | 579:53297373a894 | 53 | #define REG_TCC0_PER (*(RwReg *)0x42002040U) /**< \brief (TCC0) Period */ |
| mbed_official | 579:53297373a894 | 54 | #define REG_TCC0_CC0 (*(RwReg *)0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */ |
| mbed_official | 579:53297373a894 | 55 | #define REG_TCC0_CC1 (*(RwReg *)0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */ |
| mbed_official | 579:53297373a894 | 56 | #define REG_TCC0_CC2 (*(RwReg *)0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */ |
| mbed_official | 579:53297373a894 | 57 | #define REG_TCC0_CC3 (*(RwReg *)0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */ |
| mbed_official | 579:53297373a894 | 58 | #define REG_TCC0_PATTB (*(RwReg16*)0x42002064U) /**< \brief (TCC0) Pattern Buffer */ |
| mbed_official | 579:53297373a894 | 59 | #define REG_TCC0_WAVEB (*(RwReg *)0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */ |
| mbed_official | 579:53297373a894 | 60 | #define REG_TCC0_PERB (*(RwReg *)0x4200206CU) /**< \brief (TCC0) Period Buffer */ |
| mbed_official | 579:53297373a894 | 61 | #define REG_TCC0_CCB0 (*(RwReg *)0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ |
| mbed_official | 579:53297373a894 | 62 | #define REG_TCC0_CCB1 (*(RwReg *)0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ |
| mbed_official | 579:53297373a894 | 63 | #define REG_TCC0_CCB2 (*(RwReg *)0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ |
| mbed_official | 579:53297373a894 | 64 | #define REG_TCC0_CCB3 (*(RwReg *)0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ |
| mbed_official | 579:53297373a894 | 65 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 66 | |
| mbed_official | 579:53297373a894 | 67 | /* ========== Instance parameters for TCC0 peripheral ========== */ |
| mbed_official | 579:53297373a894 | 68 | #define TCC0_CC_NUM 4 // Number of Compare/Capture units |
| mbed_official | 579:53297373a894 | 69 | #define TCC0_DITHERING 1 // Dithering feature implemented |
| mbed_official | 579:53297373a894 | 70 | #define TCC0_DMAC_ID_MC_0 14 |
| mbed_official | 579:53297373a894 | 71 | #define TCC0_DMAC_ID_MC_1 15 |
| mbed_official | 579:53297373a894 | 72 | #define TCC0_DMAC_ID_MC_2 16 |
| mbed_official | 579:53297373a894 | 73 | #define TCC0_DMAC_ID_MC_3 17 |
| mbed_official | 579:53297373a894 | 74 | #define TCC0_DMAC_ID_MC_LSB 14 |
| mbed_official | 579:53297373a894 | 75 | #define TCC0_DMAC_ID_MC_MSB 17 |
| mbed_official | 579:53297373a894 | 76 | #define TCC0_DMAC_ID_MC_SIZE 4 |
| mbed_official | 579:53297373a894 | 77 | #define TCC0_DMAC_ID_OVF 13 // DMA overflow/underflow/retrigger trigger |
| mbed_official | 579:53297373a894 | 78 | #define TCC0_DTI 1 // Dead-Time-Insertion feature implemented |
| mbed_official | 579:53297373a894 | 79 | #define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1) |
| mbed_official | 579:53297373a894 | 80 | #define TCC0_GCLK_ID 26 // Index of Generic Clock |
| mbed_official | 579:53297373a894 | 81 | #define TCC0_OTMX 1 // Output Matrix feature implemented |
| mbed_official | 579:53297373a894 | 82 | #define TCC0_OW_NUM 8 // Number of Output Waveforms |
| mbed_official | 579:53297373a894 | 83 | #define TCC0_PG 1 // Pattern Generation feature implemented |
| mbed_official | 579:53297373a894 | 84 | #define TCC0_SIZE 24 |
| mbed_official | 579:53297373a894 | 85 | #define TCC0_SWAP 1 // DTI outputs swap feature implemented |
| mbed_official | 579:53297373a894 | 86 | #define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave |
| mbed_official | 579:53297373a894 | 87 | |
| mbed_official | 579:53297373a894 | 88 | #endif /* _SAMD21_TCC0_INSTANCE_ */ |
