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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_features.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Parent:
149:1fb5f62b92bd 
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Version: rev. 1.0, 2014-05-14
mbed_official 324:406fd2029f23 4 ** Build: b140515
mbed_official 324:406fd2029f23 5 **
mbed_official 324:406fd2029f23 6 ** Abstract:
mbed_official 324:406fd2029f23 7 ** Chip specific module features.
mbed_official 324:406fd2029f23 8 **
mbed_official 324:406fd2029f23 9 ** Copyright: 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 10 ** All rights reserved.
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 13 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 16 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 19 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 20 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 21 **
mbed_official 324:406fd2029f23 22 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 23 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 24 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 25 **
mbed_official 324:406fd2029f23 26 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 27 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 28 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 29 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 30 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 31 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 32 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 33 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 34 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 35 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 36 **
mbed_official 324:406fd2029f23 37 ** http: www.freescale.com
mbed_official 324:406fd2029f23 38 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 39 **
mbed_official 324:406fd2029f23 40 ** Revisions:
mbed_official 324:406fd2029f23 41 ** - rev. 1.0 (2014-05-14)
mbed_official 324:406fd2029f23 42 ** Customer release.
mbed_official 324:406fd2029f23 43 **
mbed_official 324:406fd2029f23 44 ** ###################################################################
mbed_official 324:406fd2029f23 45 */
mbed_official 324:406fd2029f23 46
mbed_official 146:f64d43ff0c18 47 #if !defined(__FSL_PORT_FEATURES_H__)
mbed_official 146:f64d43ff0c18 48 #define __FSL_PORT_FEATURES_H__
mbed_official 146:f64d43ff0c18 49
mbed_official 324:406fd2029f23 50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
mbed_official 324:406fd2029f23 51 defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \
mbed_official 324:406fd2029f23 52 defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
mbed_official 324:406fd2029f23 53 defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \
mbed_official 324:406fd2029f23 54 defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \
mbed_official 324:406fd2029f23 55 defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
mbed_official 324:406fd2029f23 56 defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \
mbed_official 324:406fd2029f23 57 defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \
mbed_official 324:406fd2029f23 58 defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \
mbed_official 324:406fd2029f23 59 defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \
mbed_official 324:406fd2029f23 60 defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
mbed_official 324:406fd2029f23 61 defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \
mbed_official 324:406fd2029f23 62 defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \
mbed_official 324:406fd2029f23 63 defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
mbed_official 324:406fd2029f23 64 defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \
mbed_official 324:406fd2029f23 65 defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
mbed_official 146:f64d43ff0c18 66 defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
mbed_official 324:406fd2029f23 67 defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
mbed_official 324:406fd2029f23 68 defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \
mbed_official 324:406fd2029f23 69 defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \
mbed_official 324:406fd2029f23 70 defined(CPU_MKV31F512VLL12) || defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
mbed_official 324:406fd2029f23 71 defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || \
mbed_official 324:406fd2029f23 72 defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || \
mbed_official 324:406fd2029f23 73 defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || \
mbed_official 324:406fd2029f23 74 defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15)
mbed_official 324:406fd2029f23 75 /* @brief Has control lock (register bit PCR[LK]). */
mbed_official 146:f64d43ff0c18 76 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
mbed_official 324:406fd2029f23 77 /* @brief Has open drain control (register bit PCR[ODE]). */
mbed_official 146:f64d43ff0c18 78 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
mbed_official 324:406fd2029f23 79 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
mbed_official 146:f64d43ff0c18 80 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
mbed_official 146:f64d43ff0c18 81 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
mbed_official 146:f64d43ff0c18 82 ((x) == 0 ? (0) : \
mbed_official 146:f64d43ff0c18 83 ((x) == 1 ? (0) : \
mbed_official 146:f64d43ff0c18 84 ((x) == 2 ? (0) : \
mbed_official 146:f64d43ff0c18 85 ((x) == 3 ? (1) : \
mbed_official 146:f64d43ff0c18 86 ((x) == 4 ? (0) : (-1))))))
mbed_official 324:406fd2029f23 87 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
mbed_official 146:f64d43ff0c18 88 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
mbed_official 324:406fd2029f23 89 /* @brief Has pull resistor selection (register bit PCR[PS]). */
mbed_official 146:f64d43ff0c18 90 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
mbed_official 324:406fd2029f23 91 /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
mbed_official 146:f64d43ff0c18 92 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
mbed_official 324:406fd2029f23 93 /* @brief Has slew rate control (register bit PCR[SRE]). */
mbed_official 146:f64d43ff0c18 94 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
mbed_official 324:406fd2029f23 95 /* @brief Has passive filter (register bit field PCR[PFE]). */
mbed_official 146:f64d43ff0c18 96 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
mbed_official 146:f64d43ff0c18 97 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
mbed_official 146:f64d43ff0c18 98 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 99 ((x) == 1 ? (1) : \
mbed_official 146:f64d43ff0c18 100 ((x) == 2 ? (1) : \
mbed_official 146:f64d43ff0c18 101 ((x) == 3 ? (1) : \
mbed_official 146:f64d43ff0c18 102 ((x) == 4 ? (1) : (-1))))))
mbed_official 324:406fd2029f23 103 /* @brief Has drive strength control (register bit PCR[DSE]). */
mbed_official 146:f64d43ff0c18 104 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
mbed_official 324:406fd2029f23 105 /* @brief Has separate drive strength register (HDRVE). */
mbed_official 146:f64d43ff0c18 106 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
mbed_official 324:406fd2029f23 107 /* @brief Has glitch filter (register IOFLT). */
mbed_official 146:f64d43ff0c18 108 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
mbed_official 146:f64d43ff0c18 109 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
mbed_official 146:f64d43ff0c18 110 defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
mbed_official 324:406fd2029f23 111 /* @brief Has control lock (register bit PCR[LK]). */
mbed_official 146:f64d43ff0c18 112 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
mbed_official 324:406fd2029f23 113 /* @brief Has open drain control (register bit PCR[ODE]). */
mbed_official 146:f64d43ff0c18 114 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
mbed_official 324:406fd2029f23 115 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
mbed_official 146:f64d43ff0c18 116 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
mbed_official 146:f64d43ff0c18 117 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
mbed_official 146:f64d43ff0c18 118 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 119 ((x) == 1 ? (1) : \
mbed_official 146:f64d43ff0c18 120 ((x) == 2 ? (1) : \
mbed_official 146:f64d43ff0c18 121 ((x) == 3 ? (1) : \
mbed_official 146:f64d43ff0c18 122 ((x) == 4 ? (1) : \
mbed_official 146:f64d43ff0c18 123 ((x) == 5 ? (1) : (-1)))))))
mbed_official 324:406fd2029f23 124 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
mbed_official 146:f64d43ff0c18 125 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
mbed_official 324:406fd2029f23 126 /* @brief Has pull resistor selection (register bit PCR[PS]). */
mbed_official 146:f64d43ff0c18 127 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
mbed_official 324:406fd2029f23 128 /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
mbed_official 146:f64d43ff0c18 129 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
mbed_official 324:406fd2029f23 130 /* @brief Has slew rate control (register bit PCR[SRE]). */
mbed_official 146:f64d43ff0c18 131 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
mbed_official 324:406fd2029f23 132 /* @brief Has passive filter (register bit field PCR[PFE]). */
mbed_official 146:f64d43ff0c18 133 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
mbed_official 146:f64d43ff0c18 134 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
mbed_official 146:f64d43ff0c18 135 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 136 ((x) == 1 ? (1) : \
mbed_official 146:f64d43ff0c18 137 ((x) == 2 ? (1) : \
mbed_official 146:f64d43ff0c18 138 ((x) == 3 ? (1) : \
mbed_official 146:f64d43ff0c18 139 ((x) == 4 ? (1) : \
mbed_official 146:f64d43ff0c18 140 ((x) == 5 ? (1) : (-1)))))))
mbed_official 324:406fd2029f23 141 /* @brief Has drive strength control (register bit PCR[DSE]). */
mbed_official 146:f64d43ff0c18 142 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
mbed_official 324:406fd2029f23 143 /* @brief Has separate drive strength register (HDRVE). */
mbed_official 146:f64d43ff0c18 144 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
mbed_official 324:406fd2029f23 145 /* @brief Has glitch filter (register IOFLT). */
mbed_official 146:f64d43ff0c18 146 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
mbed_official 324:406fd2029f23 147 #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
mbed_official 324:406fd2029f23 148 defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4)
mbed_official 324:406fd2029f23 149 /* @brief Has control lock (register bit PCR[LK]). */
mbed_official 146:f64d43ff0c18 150 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
mbed_official 324:406fd2029f23 151 /* @brief Has open drain control (register bit PCR[ODE]). */
mbed_official 146:f64d43ff0c18 152 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
mbed_official 324:406fd2029f23 153 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
mbed_official 146:f64d43ff0c18 154 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
mbed_official 146:f64d43ff0c18 155 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
mbed_official 146:f64d43ff0c18 156 ((x) == 0 ? (0) : \
mbed_official 146:f64d43ff0c18 157 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 158 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
mbed_official 324:406fd2029f23 159 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0)
mbed_official 324:406fd2029f23 160 /* @brief Has pull resistor selection (register bit PCR[PS]). */
mbed_official 146:f64d43ff0c18 161 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
mbed_official 324:406fd2029f23 162 /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
mbed_official 146:f64d43ff0c18 163 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
mbed_official 324:406fd2029f23 164 /* @brief Has slew rate control (register bit PCR[SRE]). */
mbed_official 146:f64d43ff0c18 165 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
mbed_official 324:406fd2029f23 166 /* @brief Has passive filter (register bit field PCR[PFE]). */
mbed_official 146:f64d43ff0c18 167 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
mbed_official 146:f64d43ff0c18 168 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
mbed_official 146:f64d43ff0c18 169 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 170 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 171 /* @brief Has drive strength control (register bit PCR[DSE]). */
mbed_official 146:f64d43ff0c18 172 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
mbed_official 324:406fd2029f23 173 /* @brief Has separate drive strength register (HDRVE). */
mbed_official 146:f64d43ff0c18 174 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
mbed_official 324:406fd2029f23 175 /* @brief Has glitch filter (register IOFLT). */
mbed_official 146:f64d43ff0c18 176 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
mbed_official 324:406fd2029f23 177 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
mbed_official 324:406fd2029f23 178 defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
mbed_official 324:406fd2029f23 179 defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)
mbed_official 324:406fd2029f23 180 /* @brief Has control lock (register bit PCR[LK]). */
mbed_official 146:f64d43ff0c18 181 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
mbed_official 324:406fd2029f23 182 /* @brief Has open drain control (register bit PCR[ODE]). */
mbed_official 146:f64d43ff0c18 183 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
mbed_official 324:406fd2029f23 184 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
mbed_official 324:406fd2029f23 185 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
mbed_official 324:406fd2029f23 186 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
mbed_official 324:406fd2029f23 187 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 188 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 189 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
mbed_official 324:406fd2029f23 190 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
mbed_official 324:406fd2029f23 191 /* @brief Has pull resistor selection (register bit PCR[PS]). */
mbed_official 324:406fd2029f23 192 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
mbed_official 324:406fd2029f23 193 /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
mbed_official 324:406fd2029f23 194 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
mbed_official 324:406fd2029f23 195 /* @brief Has slew rate control (register bit PCR[SRE]). */
mbed_official 324:406fd2029f23 196 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
mbed_official 324:406fd2029f23 197 /* @brief Has passive filter (register bit field PCR[PFE]). */
mbed_official 324:406fd2029f23 198 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
mbed_official 324:406fd2029f23 199 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
mbed_official 324:406fd2029f23 200 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 201 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 202 /* @brief Has drive strength control (register bit PCR[DSE]). */
mbed_official 324:406fd2029f23 203 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
mbed_official 324:406fd2029f23 204 /* @brief Has separate drive strength register (HDRVE). */
mbed_official 324:406fd2029f23 205 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
mbed_official 324:406fd2029f23 206 /* @brief Has glitch filter (register IOFLT). */
mbed_official 324:406fd2029f23 207 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
mbed_official 324:406fd2029f23 208 #elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \
mbed_official 324:406fd2029f23 209 defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \
mbed_official 324:406fd2029f23 210 defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \
mbed_official 324:406fd2029f23 211 defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \
mbed_official 324:406fd2029f23 212 defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \
mbed_official 324:406fd2029f23 213 defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \
mbed_official 324:406fd2029f23 214 defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
mbed_official 324:406fd2029f23 215 defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
mbed_official 324:406fd2029f23 216 defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)
mbed_official 324:406fd2029f23 217 /* @brief Has control lock (register bit PCR[LK]). */
mbed_official 324:406fd2029f23 218 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
mbed_official 324:406fd2029f23 219 /* @brief Has open drain control (register bit PCR[ODE]). */
mbed_official 324:406fd2029f23 220 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
mbed_official 324:406fd2029f23 221 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
mbed_official 146:f64d43ff0c18 222 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
mbed_official 146:f64d43ff0c18 223 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
mbed_official 146:f64d43ff0c18 224 ((x) == 0 ? (0) : \
mbed_official 146:f64d43ff0c18 225 ((x) == 1 ? (0) : \
mbed_official 146:f64d43ff0c18 226 ((x) == 2 ? (0) : \
mbed_official 146:f64d43ff0c18 227 ((x) == 3 ? (0) : \
mbed_official 146:f64d43ff0c18 228 ((x) == 4 ? (0) : (-1))))))
mbed_official 324:406fd2029f23 229 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
mbed_official 146:f64d43ff0c18 230 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
mbed_official 324:406fd2029f23 231 /* @brief Has pull resistor selection (register bit PCR[PS]). */
mbed_official 324:406fd2029f23 232 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
mbed_official 324:406fd2029f23 233 /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
mbed_official 324:406fd2029f23 234 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
mbed_official 324:406fd2029f23 235 /* @brief Has slew rate control (register bit PCR[SRE]). */
mbed_official 324:406fd2029f23 236 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
mbed_official 324:406fd2029f23 237 /* @brief Has passive filter (register bit field PCR[PFE]). */
mbed_official 324:406fd2029f23 238 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
mbed_official 324:406fd2029f23 239 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
mbed_official 324:406fd2029f23 240 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 241 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 242 ((x) == 2 ? (1) : \
mbed_official 324:406fd2029f23 243 ((x) == 3 ? (1) : \
mbed_official 324:406fd2029f23 244 ((x) == 4 ? (1) : (-1))))))
mbed_official 324:406fd2029f23 245 /* @brief Has drive strength control (register bit PCR[DSE]). */
mbed_official 324:406fd2029f23 246 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
mbed_official 324:406fd2029f23 247 /* @brief Has separate drive strength register (HDRVE). */
mbed_official 324:406fd2029f23 248 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
mbed_official 324:406fd2029f23 249 /* @brief Has glitch filter (register IOFLT). */
mbed_official 324:406fd2029f23 250 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
mbed_official 324:406fd2029f23 251 #elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \
mbed_official 324:406fd2029f23 252 defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \
mbed_official 324:406fd2029f23 253 defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)
mbed_official 324:406fd2029f23 254 /* @brief Has control lock (register bit PCR[LK]). */
mbed_official 324:406fd2029f23 255 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
mbed_official 324:406fd2029f23 256 /* @brief Has open drain control (register bit PCR[ODE]). */
mbed_official 324:406fd2029f23 257 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
mbed_official 324:406fd2029f23 258 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
mbed_official 324:406fd2029f23 259 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
mbed_official 324:406fd2029f23 260 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
mbed_official 324:406fd2029f23 261 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 262 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 263 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 264 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 265 ((x) == 4 ? (0) : (-1))))))
mbed_official 324:406fd2029f23 266 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
mbed_official 324:406fd2029f23 267 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
mbed_official 324:406fd2029f23 268 /* @brief Has pull resistor selection (register bit PCR[PS]). */
mbed_official 146:f64d43ff0c18 269 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (0)
mbed_official 324:406fd2029f23 270 /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
mbed_official 146:f64d43ff0c18 271 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
mbed_official 324:406fd2029f23 272 /* @brief Has slew rate control (register bit PCR[SRE]). */
mbed_official 146:f64d43ff0c18 273 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
mbed_official 324:406fd2029f23 274 /* @brief Has passive filter (register bit field PCR[PFE]). */
mbed_official 146:f64d43ff0c18 275 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
mbed_official 146:f64d43ff0c18 276 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
mbed_official 146:f64d43ff0c18 277 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 278 ((x) == 1 ? (0) : \
mbed_official 146:f64d43ff0c18 279 ((x) == 2 ? (0) : \
mbed_official 146:f64d43ff0c18 280 ((x) == 3 ? (0) : \
mbed_official 146:f64d43ff0c18 281 ((x) == 4 ? (0) : (-1))))))
mbed_official 324:406fd2029f23 282 /* @brief Has drive strength control (register bit PCR[DSE]). */
mbed_official 146:f64d43ff0c18 283 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
mbed_official 324:406fd2029f23 284 /* @brief Has separate drive strength register (HDRVE). */
mbed_official 146:f64d43ff0c18 285 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
mbed_official 324:406fd2029f23 286 /* @brief Has glitch filter (register IOFLT). */
mbed_official 146:f64d43ff0c18 287 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
mbed_official 324:406fd2029f23 288 #elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \
mbed_official 324:406fd2029f23 289 defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
mbed_official 324:406fd2029f23 290 defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
mbed_official 324:406fd2029f23 291 /* @brief Has control lock (register bit PCR[LK]). */
mbed_official 146:f64d43ff0c18 292 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
mbed_official 324:406fd2029f23 293 /* @brief Has open drain control (register bit PCR[ODE]). */
mbed_official 146:f64d43ff0c18 294 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
mbed_official 324:406fd2029f23 295 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
mbed_official 146:f64d43ff0c18 296 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
mbed_official 146:f64d43ff0c18 297 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
mbed_official 146:f64d43ff0c18 298 ((x) == 0 ? (0) : \
mbed_official 146:f64d43ff0c18 299 ((x) == 1 ? (0) : \
mbed_official 146:f64d43ff0c18 300 ((x) == 2 ? (0) : \
mbed_official 146:f64d43ff0c18 301 ((x) == 3 ? (0) : \
mbed_official 146:f64d43ff0c18 302 ((x) == 4 ? (0) : (-1))))))
mbed_official 324:406fd2029f23 303 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
mbed_official 146:f64d43ff0c18 304 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
mbed_official 324:406fd2029f23 305 /* @brief Has pull resistor selection (register bit PCR[PS]). */
mbed_official 146:f64d43ff0c18 306 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
mbed_official 324:406fd2029f23 307 /* @brief Has separate pull resistor enable registers (PUEL and PUEH). */
mbed_official 146:f64d43ff0c18 308 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
mbed_official 324:406fd2029f23 309 /* @brief Has slew rate control (register bit PCR[SRE]). */
mbed_official 146:f64d43ff0c18 310 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
mbed_official 324:406fd2029f23 311 /* @brief Has passive filter (register bit field PCR[PFE]). */
mbed_official 146:f64d43ff0c18 312 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
mbed_official 146:f64d43ff0c18 313 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
mbed_official 146:f64d43ff0c18 314 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 315 ((x) == 1 ? (0) : \
mbed_official 146:f64d43ff0c18 316 ((x) == 2 ? (0) : \
mbed_official 146:f64d43ff0c18 317 ((x) == 3 ? (0) : \
mbed_official 146:f64d43ff0c18 318 ((x) == 4 ? (0) : (-1))))))
mbed_official 324:406fd2029f23 319 /* @brief Has drive strength control (register bit PCR[DSE]). */
mbed_official 146:f64d43ff0c18 320 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
mbed_official 324:406fd2029f23 321 /* @brief Has separate drive strength register (HDRVE). */
mbed_official 146:f64d43ff0c18 322 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
mbed_official 324:406fd2029f23 323 /* @brief Has glitch filter (register IOFLT). */
mbed_official 146:f64d43ff0c18 324 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
mbed_official 146:f64d43ff0c18 325 #else
mbed_official 146:f64d43ff0c18 326 #error "No valid CPU defined!"
mbed_official 146:f64d43ff0c18 327 #endif
mbed_official 146:f64d43ff0c18 328
mbed_official 324:406fd2029f23 329 #endif /* __FSL_PORT_FEATURES_H__ */
mbed_official 324:406fd2029f23 330
mbed_official 146:f64d43ff0c18 331 /*******************************************************************************
mbed_official 146:f64d43ff0c18 332 * EOF
mbed_official 146:f64d43ff0c18 333 ******************************************************************************/