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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_features.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:
mbed_official
Date:
Thu Apr 03 11:45:06 2014 +0100
Revision:
149:1fb5f62b92bd
Parent:
targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_KSDK_CODE/hal/port/fsl_port_features.h@146:f64d43ff0c18
Child:
324:406fd2029f23
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 146:f64d43ff0c18 6 * are permitted provided that the following conditions are met:
mbed_official 146:f64d43ff0c18 7 *
mbed_official 146:f64d43ff0c18 8 * o Redistributions of source code must retain the above copyright notice, this list
mbed_official 146:f64d43ff0c18 9 * of conditions and the following disclaimer.
mbed_official 146:f64d43ff0c18 10 *
mbed_official 146:f64d43ff0c18 11 * o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 146:f64d43ff0c18 12 * list of conditions and the following disclaimer in the documentation and/or
mbed_official 146:f64d43ff0c18 13 * other materials provided with the distribution.
mbed_official 146:f64d43ff0c18 14 *
mbed_official 146:f64d43ff0c18 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 146:f64d43ff0c18 16 * contributors may be used to endorse or promote products derived from this
mbed_official 146:f64d43ff0c18 17 * software without specific prior written permission.
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 146:f64d43ff0c18 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 146:f64d43ff0c18 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 146:f64d43ff0c18 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 146:f64d43ff0c18 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 146:f64d43ff0c18 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 146:f64d43ff0c18 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 146:f64d43ff0c18 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 146:f64d43ff0c18 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 146:f64d43ff0c18 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 29 */
mbed_official 146:f64d43ff0c18 30 #if !defined(__FSL_PORT_FEATURES_H__)
mbed_official 146:f64d43ff0c18 31 #define __FSL_PORT_FEATURES_H__
mbed_official 146:f64d43ff0c18 32
mbed_official 146:f64d43ff0c18 33 #if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
mbed_official 146:f64d43ff0c18 34 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
mbed_official 146:f64d43ff0c18 35 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
mbed_official 146:f64d43ff0c18 36 defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
mbed_official 146:f64d43ff0c18 37 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
mbed_official 146:f64d43ff0c18 38 defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
mbed_official 146:f64d43ff0c18 39 defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
mbed_official 146:f64d43ff0c18 40 defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \
mbed_official 146:f64d43ff0c18 41 defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
mbed_official 146:f64d43ff0c18 42 defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || \
mbed_official 146:f64d43ff0c18 43 defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || \
mbed_official 146:f64d43ff0c18 44 defined(CPU_MK64FX512VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
mbed_official 146:f64d43ff0c18 45 defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
mbed_official 146:f64d43ff0c18 46 defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31FN512VLH12) || \
mbed_official 146:f64d43ff0c18 47 defined(CPU_MKV31F512VLL12)
mbed_official 146:f64d43ff0c18 48 /* @brief Has control lock (register bit PCR[LK]).*/
mbed_official 146:f64d43ff0c18 49 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
mbed_official 146:f64d43ff0c18 50 /* @brief Has open drain control (register bit PCR[ODE]).*/
mbed_official 146:f64d43ff0c18 51 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
mbed_official 146:f64d43ff0c18 52 /* @brief Has digital filter (registers DFER, DFCR and DFWR).*/
mbed_official 146:f64d43ff0c18 53 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
mbed_official 146:f64d43ff0c18 54 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
mbed_official 146:f64d43ff0c18 55 ((x) == 0 ? (0) : \
mbed_official 146:f64d43ff0c18 56 ((x) == 1 ? (0) : \
mbed_official 146:f64d43ff0c18 57 ((x) == 2 ? (0) : \
mbed_official 146:f64d43ff0c18 58 ((x) == 3 ? (1) : \
mbed_official 146:f64d43ff0c18 59 ((x) == 4 ? (0) : (-1))))))
mbed_official 146:f64d43ff0c18 60 /* @brief Has DMA request (register bit field PCR[IRQC] values).*/
mbed_official 146:f64d43ff0c18 61 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
mbed_official 146:f64d43ff0c18 62 /* @brief Has pull resistor selection (register bit PCR[PS]).*/
mbed_official 146:f64d43ff0c18 63 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
mbed_official 146:f64d43ff0c18 64 /* @brief Has separate pull resistor enable registers (PUEL and PUEH).*/
mbed_official 146:f64d43ff0c18 65 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
mbed_official 146:f64d43ff0c18 66 /* @brief Has slew rate control (register bit PCR[SRE]).*/
mbed_official 146:f64d43ff0c18 67 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
mbed_official 146:f64d43ff0c18 68 /* @brief Has passive filter (register bit field PCR[PFE]).*/
mbed_official 146:f64d43ff0c18 69 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
mbed_official 146:f64d43ff0c18 70 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
mbed_official 146:f64d43ff0c18 71 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 72 ((x) == 1 ? (1) : \
mbed_official 146:f64d43ff0c18 73 ((x) == 2 ? (1) : \
mbed_official 146:f64d43ff0c18 74 ((x) == 3 ? (1) : \
mbed_official 146:f64d43ff0c18 75 ((x) == 4 ? (1) : (-1))))))
mbed_official 146:f64d43ff0c18 76 /* @brief Has drive strength control (register bit PCR[DSE]).*/
mbed_official 146:f64d43ff0c18 77 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
mbed_official 146:f64d43ff0c18 78 /* @brief Has separate drive strength register (HDRVE).*/
mbed_official 146:f64d43ff0c18 79 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
mbed_official 146:f64d43ff0c18 80 /* @brief Has glitch filter (register IOFLT).*/
mbed_official 146:f64d43ff0c18 81 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
mbed_official 146:f64d43ff0c18 82 #elif defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VMD12)
mbed_official 146:f64d43ff0c18 83 /* @brief Has control lock (register bit PCR[LK]).*/
mbed_official 146:f64d43ff0c18 84 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
mbed_official 146:f64d43ff0c18 85 /* @brief Has open drain control (register bit PCR[ODE]).*/
mbed_official 146:f64d43ff0c18 86 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
mbed_official 146:f64d43ff0c18 87 /* @brief Has digital filter (registers DFER, DFCR and DFWR).*/
mbed_official 146:f64d43ff0c18 88 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
mbed_official 146:f64d43ff0c18 89 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
mbed_official 146:f64d43ff0c18 90 ((x) == 0 ? (0) : \
mbed_official 146:f64d43ff0c18 91 ((x) == 1 ? (0) : \
mbed_official 146:f64d43ff0c18 92 ((x) == 2 ? (0) : \
mbed_official 146:f64d43ff0c18 93 ((x) == 3 ? (1) : \
mbed_official 146:f64d43ff0c18 94 ((x) == 4 ? (0) : (-1))))))
mbed_official 146:f64d43ff0c18 95 /* @brief Has DMA request (register bit field PCR[IRQC] values).*/
mbed_official 146:f64d43ff0c18 96 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
mbed_official 146:f64d43ff0c18 97 /* @brief Has pull resistor selection (register bit PCR[PS]).*/
mbed_official 146:f64d43ff0c18 98 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
mbed_official 146:f64d43ff0c18 99 /* @brief Has separate pull resistor enable registers (PUEL and PUEH).*/
mbed_official 146:f64d43ff0c18 100 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
mbed_official 146:f64d43ff0c18 101 /* @brief Has slew rate control (register bit PCR[SRE]).*/
mbed_official 146:f64d43ff0c18 102 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
mbed_official 146:f64d43ff0c18 103 /* @brief Has passive filter (register bit field PCR[PFE]).*/
mbed_official 146:f64d43ff0c18 104 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
mbed_official 146:f64d43ff0c18 105 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
mbed_official 146:f64d43ff0c18 106 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 107 ((x) == 1 ? (1) : \
mbed_official 146:f64d43ff0c18 108 ((x) == 2 ? (1) : \
mbed_official 146:f64d43ff0c18 109 ((x) == 3 ? (1) : \
mbed_official 146:f64d43ff0c18 110 ((x) == 4 ? (1) : (-1))))))
mbed_official 146:f64d43ff0c18 111 /* @brief Has drive strength control (register bit PCR[DSE]).*/
mbed_official 146:f64d43ff0c18 112 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
mbed_official 146:f64d43ff0c18 113 /* @brief Has separate drive strength register (HDRVE).*/
mbed_official 146:f64d43ff0c18 114 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
mbed_official 146:f64d43ff0c18 115 /* @brief Has glitch filter (register IOFLT).*/
mbed_official 146:f64d43ff0c18 116 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
mbed_official 146:f64d43ff0c18 117 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
mbed_official 146:f64d43ff0c18 118 defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
mbed_official 146:f64d43ff0c18 119 /* @brief Has control lock (register bit PCR[LK]).*/
mbed_official 146:f64d43ff0c18 120 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
mbed_official 146:f64d43ff0c18 121 /* @brief Has open drain control (register bit PCR[ODE]).*/
mbed_official 146:f64d43ff0c18 122 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
mbed_official 146:f64d43ff0c18 123 /* @brief Has digital filter (registers DFER, DFCR and DFWR).*/
mbed_official 146:f64d43ff0c18 124 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
mbed_official 146:f64d43ff0c18 125 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
mbed_official 146:f64d43ff0c18 126 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 127 ((x) == 1 ? (1) : \
mbed_official 146:f64d43ff0c18 128 ((x) == 2 ? (1) : \
mbed_official 146:f64d43ff0c18 129 ((x) == 3 ? (1) : \
mbed_official 146:f64d43ff0c18 130 ((x) == 4 ? (1) : \
mbed_official 146:f64d43ff0c18 131 ((x) == 5 ? (1) : (-1)))))))
mbed_official 146:f64d43ff0c18 132 /* @brief Has DMA request (register bit field PCR[IRQC] values).*/
mbed_official 146:f64d43ff0c18 133 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
mbed_official 146:f64d43ff0c18 134 /* @brief Has pull resistor selection (register bit PCR[PS]).*/
mbed_official 146:f64d43ff0c18 135 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
mbed_official 146:f64d43ff0c18 136 /* @brief Has separate pull resistor enable registers (PUEL and PUEH).*/
mbed_official 146:f64d43ff0c18 137 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
mbed_official 146:f64d43ff0c18 138 /* @brief Has slew rate control (register bit PCR[SRE]).*/
mbed_official 146:f64d43ff0c18 139 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
mbed_official 146:f64d43ff0c18 140 /* @brief Has passive filter (register bit field PCR[PFE]).*/
mbed_official 146:f64d43ff0c18 141 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
mbed_official 146:f64d43ff0c18 142 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
mbed_official 146:f64d43ff0c18 143 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 144 ((x) == 1 ? (1) : \
mbed_official 146:f64d43ff0c18 145 ((x) == 2 ? (1) : \
mbed_official 146:f64d43ff0c18 146 ((x) == 3 ? (1) : \
mbed_official 146:f64d43ff0c18 147 ((x) == 4 ? (1) : \
mbed_official 146:f64d43ff0c18 148 ((x) == 5 ? (1) : (-1)))))))
mbed_official 146:f64d43ff0c18 149 /* @brief Has drive strength control (register bit PCR[DSE]).*/
mbed_official 146:f64d43ff0c18 150 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
mbed_official 146:f64d43ff0c18 151 /* @brief Has separate drive strength register (HDRVE).*/
mbed_official 146:f64d43ff0c18 152 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
mbed_official 146:f64d43ff0c18 153 /* @brief Has glitch filter (register IOFLT).*/
mbed_official 146:f64d43ff0c18 154 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
mbed_official 146:f64d43ff0c18 155 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
mbed_official 146:f64d43ff0c18 156 defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
mbed_official 146:f64d43ff0c18 157 defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)
mbed_official 146:f64d43ff0c18 158 /* @brief Has control lock (register bit PCR[LK]).*/
mbed_official 146:f64d43ff0c18 159 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
mbed_official 146:f64d43ff0c18 160 /* @brief Has open drain control (register bit PCR[ODE]).*/
mbed_official 146:f64d43ff0c18 161 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
mbed_official 146:f64d43ff0c18 162 /* @brief Has digital filter (registers DFER, DFCR and DFWR).*/
mbed_official 146:f64d43ff0c18 163 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
mbed_official 146:f64d43ff0c18 164 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
mbed_official 146:f64d43ff0c18 165 ((x) == 0 ? (0) : \
mbed_official 146:f64d43ff0c18 166 ((x) == 1 ? (0) : (-1)))
mbed_official 146:f64d43ff0c18 167 /* @brief Has DMA request (register bit field PCR[IRQC] values).*/
mbed_official 146:f64d43ff0c18 168 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
mbed_official 146:f64d43ff0c18 169 /* @brief Has pull resistor selection (register bit PCR[PS]).*/
mbed_official 146:f64d43ff0c18 170 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
mbed_official 146:f64d43ff0c18 171 /* @brief Has separate pull resistor enable registers (PUEL and PUEH).*/
mbed_official 146:f64d43ff0c18 172 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
mbed_official 146:f64d43ff0c18 173 /* @brief Has slew rate control (register bit PCR[SRE]).*/
mbed_official 146:f64d43ff0c18 174 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
mbed_official 146:f64d43ff0c18 175 /* @brief Has passive filter (register bit field PCR[PFE]).*/
mbed_official 146:f64d43ff0c18 176 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
mbed_official 146:f64d43ff0c18 177 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
mbed_official 146:f64d43ff0c18 178 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 179 ((x) == 1 ? (1) : (-1)))
mbed_official 146:f64d43ff0c18 180 /* @brief Has drive strength control (register bit PCR[DSE]).*/
mbed_official 146:f64d43ff0c18 181 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
mbed_official 146:f64d43ff0c18 182 /* @brief Has separate drive strength register (HDRVE).*/
mbed_official 146:f64d43ff0c18 183 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
mbed_official 146:f64d43ff0c18 184 /* @brief Has glitch filter (register IOFLT).*/
mbed_official 146:f64d43ff0c18 185 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
mbed_official 146:f64d43ff0c18 186 #elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \
mbed_official 146:f64d43ff0c18 187 defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \
mbed_official 146:f64d43ff0c18 188 defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)
mbed_official 146:f64d43ff0c18 189 /* @brief Has control lock (register bit PCR[LK]).*/
mbed_official 146:f64d43ff0c18 190 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
mbed_official 146:f64d43ff0c18 191 /* @brief Has open drain control (register bit PCR[ODE]).*/
mbed_official 146:f64d43ff0c18 192 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
mbed_official 146:f64d43ff0c18 193 /* @brief Has digital filter (registers DFER, DFCR and DFWR).*/
mbed_official 146:f64d43ff0c18 194 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
mbed_official 146:f64d43ff0c18 195 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
mbed_official 146:f64d43ff0c18 196 ((x) == 0 ? (0) : \
mbed_official 146:f64d43ff0c18 197 ((x) == 1 ? (0) : \
mbed_official 146:f64d43ff0c18 198 ((x) == 2 ? (0) : \
mbed_official 146:f64d43ff0c18 199 ((x) == 3 ? (0) : \
mbed_official 146:f64d43ff0c18 200 ((x) == 4 ? (0) : (-1))))))
mbed_official 146:f64d43ff0c18 201 /* @brief Has DMA request (register bit field PCR[IRQC] values).*/
mbed_official 146:f64d43ff0c18 202 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
mbed_official 146:f64d43ff0c18 203 /* @brief Has pull resistor selection (register bit PCR[PS]).*/
mbed_official 146:f64d43ff0c18 204 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (0)
mbed_official 146:f64d43ff0c18 205 /* @brief Has separate pull resistor enable registers (PUEL and PUEH).*/
mbed_official 146:f64d43ff0c18 206 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
mbed_official 146:f64d43ff0c18 207 /* @brief Has slew rate control (register bit PCR[SRE]).*/
mbed_official 146:f64d43ff0c18 208 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
mbed_official 146:f64d43ff0c18 209 /* @brief Has passive filter (register bit field PCR[PFE]).*/
mbed_official 146:f64d43ff0c18 210 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
mbed_official 146:f64d43ff0c18 211 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
mbed_official 146:f64d43ff0c18 212 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 213 ((x) == 1 ? (0) : \
mbed_official 146:f64d43ff0c18 214 ((x) == 2 ? (0) : \
mbed_official 146:f64d43ff0c18 215 ((x) == 3 ? (0) : \
mbed_official 146:f64d43ff0c18 216 ((x) == 4 ? (0) : (-1))))))
mbed_official 146:f64d43ff0c18 217 /* @brief Has drive strength control (register bit PCR[DSE]).*/
mbed_official 146:f64d43ff0c18 218 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
mbed_official 146:f64d43ff0c18 219 /* @brief Has separate drive strength register (HDRVE).*/
mbed_official 146:f64d43ff0c18 220 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
mbed_official 146:f64d43ff0c18 221 /* @brief Has glitch filter (register IOFLT).*/
mbed_official 146:f64d43ff0c18 222 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
mbed_official 146:f64d43ff0c18 223 #elif defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || \
mbed_official 146:f64d43ff0c18 224 defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
mbed_official 146:f64d43ff0c18 225 /* @brief Has control lock (register bit PCR[LK]).*/
mbed_official 146:f64d43ff0c18 226 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
mbed_official 146:f64d43ff0c18 227 /* @brief Has open drain control (register bit PCR[ODE]).*/
mbed_official 146:f64d43ff0c18 228 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
mbed_official 146:f64d43ff0c18 229 /* @brief Has digital filter (registers DFER, DFCR and DFWR).*/
mbed_official 146:f64d43ff0c18 230 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
mbed_official 146:f64d43ff0c18 231 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
mbed_official 146:f64d43ff0c18 232 ((x) == 0 ? (0) : \
mbed_official 146:f64d43ff0c18 233 ((x) == 1 ? (0) : \
mbed_official 146:f64d43ff0c18 234 ((x) == 2 ? (0) : \
mbed_official 146:f64d43ff0c18 235 ((x) == 3 ? (0) : \
mbed_official 146:f64d43ff0c18 236 ((x) == 4 ? (0) : (-1))))))
mbed_official 146:f64d43ff0c18 237 /* @brief Has DMA request (register bit field PCR[IRQC] values).*/
mbed_official 146:f64d43ff0c18 238 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
mbed_official 146:f64d43ff0c18 239 /* @brief Has pull resistor selection (register bit PCR[PS]).*/
mbed_official 146:f64d43ff0c18 240 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
mbed_official 146:f64d43ff0c18 241 /* @brief Has separate pull resistor enable registers (PUEL and PUEH).*/
mbed_official 146:f64d43ff0c18 242 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
mbed_official 146:f64d43ff0c18 243 /* @brief Has slew rate control (register bit PCR[SRE]).*/
mbed_official 146:f64d43ff0c18 244 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
mbed_official 146:f64d43ff0c18 245 /* @brief Has passive filter (register bit field PCR[PFE]).*/
mbed_official 146:f64d43ff0c18 246 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
mbed_official 146:f64d43ff0c18 247 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
mbed_official 146:f64d43ff0c18 248 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 249 ((x) == 1 ? (0) : \
mbed_official 146:f64d43ff0c18 250 ((x) == 2 ? (0) : \
mbed_official 146:f64d43ff0c18 251 ((x) == 3 ? (0) : \
mbed_official 146:f64d43ff0c18 252 ((x) == 4 ? (0) : (-1))))))
mbed_official 146:f64d43ff0c18 253 /* @brief Has drive strength control (register bit PCR[DSE]).*/
mbed_official 146:f64d43ff0c18 254 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
mbed_official 146:f64d43ff0c18 255 /* @brief Has separate drive strength register (HDRVE).*/
mbed_official 146:f64d43ff0c18 256 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
mbed_official 146:f64d43ff0c18 257 /* @brief Has glitch filter (register IOFLT).*/
mbed_official 146:f64d43ff0c18 258 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
mbed_official 146:f64d43ff0c18 259 #else
mbed_official 146:f64d43ff0c18 260 #error "No valid CPU defined!"
mbed_official 146:f64d43ff0c18 261 #endif
mbed_official 146:f64d43ff0c18 262
mbed_official 146:f64d43ff0c18 263 #endif /* __FSL_PORT_FEATURES_H__*/
mbed_official 146:f64d43ff0c18 264 /*******************************************************************************
mbed_official 146:f64d43ff0c18 265 * EOF
mbed_official 146:f64d43ff0c18 266 ******************************************************************************/
mbed_official 146:f64d43ff0c18 267