mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Parent:
149:1fb5f62b92bd 
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 146:f64d43ff0c18 6 * are permitted provided that the following conditions are met:
mbed_official 146:f64d43ff0c18 7 *
mbed_official 146:f64d43ff0c18 8 * o Redistributions of source code must retain the above copyright notice, this list
mbed_official 146:f64d43ff0c18 9 * of conditions and the following disclaimer.
mbed_official 146:f64d43ff0c18 10 *
mbed_official 146:f64d43ff0c18 11 * o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 146:f64d43ff0c18 12 * list of conditions and the following disclaimer in the documentation and/or
mbed_official 146:f64d43ff0c18 13 * other materials provided with the distribution.
mbed_official 146:f64d43ff0c18 14 *
mbed_official 146:f64d43ff0c18 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 146:f64d43ff0c18 16 * contributors may be used to endorse or promote products derived from this
mbed_official 146:f64d43ff0c18 17 * software without specific prior written permission.
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 146:f64d43ff0c18 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 146:f64d43ff0c18 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 146:f64d43ff0c18 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 146:f64d43ff0c18 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 146:f64d43ff0c18 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 146:f64d43ff0c18 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 146:f64d43ff0c18 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 146:f64d43ff0c18 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 146:f64d43ff0c18 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 29 */
mbed_official 146:f64d43ff0c18 30 #if !defined(__FSL_DSPI_HAL_H__)
mbed_official 146:f64d43ff0c18 31 #define __FSL_DSPI_HAL_H__
mbed_official 146:f64d43ff0c18 32
mbed_official 146:f64d43ff0c18 33 #include <stdint.h>
mbed_official 146:f64d43ff0c18 34 #include <stdbool.h>
mbed_official 146:f64d43ff0c18 35 #include "fsl_dspi_features.h"
mbed_official 146:f64d43ff0c18 36 #include "fsl_device_registers.h"
mbed_official 146:f64d43ff0c18 37
mbed_official 146:f64d43ff0c18 38 /*!
mbed_official 146:f64d43ff0c18 39 * @addtogroup dspi_hal
mbed_official 146:f64d43ff0c18 40 * @{
mbed_official 146:f64d43ff0c18 41 */
mbed_official 146:f64d43ff0c18 42
mbed_official 146:f64d43ff0c18 43 /*! @file*/
mbed_official 146:f64d43ff0c18 44
mbed_official 146:f64d43ff0c18 45 /*******************************************************************************
mbed_official 146:f64d43ff0c18 46 * Definitions
mbed_official 146:f64d43ff0c18 47 ******************************************************************************/
mbed_official 146:f64d43ff0c18 48
mbed_official 146:f64d43ff0c18 49 /* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/
mbed_official 146:f64d43ff0c18 50 static const uint32_t s_baudratePrescaler[] = { 2, 3, 5, 7 };
mbed_official 146:f64d43ff0c18 51 static const uint32_t s_baudrateScaler[] = { 2, 4, 6, 8, 16, 32, 64, 128, 256, 512, 1024, 2048,
mbed_official 146:f64d43ff0c18 52 4096, 8192, 16384, 32768 };
mbed_official 146:f64d43ff0c18 53
mbed_official 324:406fd2029f23 54 static const uint32_t s_delayPrescaler[] = { 1, 3, 5, 7 };
mbed_official 324:406fd2029f23 55 static const uint32_t s_delayScaler[] = { 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048,
mbed_official 324:406fd2029f23 56 4096, 8192, 16384, 32768, 65536 };
mbed_official 324:406fd2029f23 57
mbed_official 324:406fd2029f23 58
mbed_official 146:f64d43ff0c18 59 /*! @brief Error codes for the DSPI driver.*/
mbed_official 146:f64d43ff0c18 60 typedef enum _dspi_status
mbed_official 146:f64d43ff0c18 61 {
mbed_official 146:f64d43ff0c18 62 kStatus_DSPI_Success = 0,
mbed_official 146:f64d43ff0c18 63 kStatus_DSPI_SlaveTxUnderrun, /*!< DSPI Slave Tx Under run error*/
mbed_official 146:f64d43ff0c18 64 kStatus_DSPI_SlaveRxOverrun, /*!< DSPI Slave Rx Overrun error*/
mbed_official 146:f64d43ff0c18 65 kStatus_DSPI_Timeout, /*!< DSPI transfer timed out*/
mbed_official 146:f64d43ff0c18 66 kStatus_DSPI_Busy, /*!< DSPI instance is already busy performing a
mbed_official 146:f64d43ff0c18 67 transfer.*/
mbed_official 146:f64d43ff0c18 68 kStatus_DSPI_NoTransferInProgress, /*!< Attempt to abort a transfer when no transfer
mbed_official 146:f64d43ff0c18 69 was in progress*/
mbed_official 324:406fd2029f23 70 kStatus_DSPI_InvalidBitCount, /*!< bits-per-frame value not valid*/
mbed_official 324:406fd2029f23 71 kStatus_DSPI_InvalidInstanceNumber, /*!< DSPI instance number does not match current count*/
mbed_official 324:406fd2029f23 72 kStatus_DSPI_OutOfRange /*!< DSPI out-of-range error used in slave callback */
mbed_official 146:f64d43ff0c18 73 } dspi_status_t;
mbed_official 146:f64d43ff0c18 74
mbed_official 146:f64d43ff0c18 75 /*! @brief DSPI master or slave configuration*/
mbed_official 146:f64d43ff0c18 76 typedef enum _dspi_master_slave_mode {
mbed_official 146:f64d43ff0c18 77 kDspiMaster = 1, /*!< DSPI peripheral operates in master mode*/
mbed_official 146:f64d43ff0c18 78 kDspiSlave = 0 /*!< DSPI peripheral operates in slave mode*/
mbed_official 146:f64d43ff0c18 79 } dspi_master_slave_mode_t;
mbed_official 146:f64d43ff0c18 80
mbed_official 146:f64d43ff0c18 81 /*! @brief DSPI clock polarity configuration for a given CTAR*/
mbed_official 146:f64d43ff0c18 82 typedef enum _dspi_clock_polarity {
mbed_official 146:f64d43ff0c18 83 kDspiClockPolarity_ActiveHigh = 0, /*!< Active-high DSPI clock (idles low)*/
mbed_official 146:f64d43ff0c18 84 kDspiClockPolarity_ActiveLow = 1 /*!< Active-low DSPI clock (idles high)*/
mbed_official 146:f64d43ff0c18 85 } dspi_clock_polarity_t;
mbed_official 146:f64d43ff0c18 86
mbed_official 146:f64d43ff0c18 87 /*! @brief DSPI clock phase configuration for a given CTAR*/
mbed_official 146:f64d43ff0c18 88 typedef enum _dspi_clock_phase {
mbed_official 146:f64d43ff0c18 89 kDspiClockPhase_FirstEdge = 0, /*!< Data is captured on the leading edge of the SCK and
mbed_official 146:f64d43ff0c18 90 changed on the following edge.*/
mbed_official 146:f64d43ff0c18 91 kDspiClockPhase_SecondEdge = 1 /*!< Data is changed on the leading edge of the SCK and
mbed_official 146:f64d43ff0c18 92 captured on the following edge.*/
mbed_official 146:f64d43ff0c18 93 } dspi_clock_phase_t;
mbed_official 146:f64d43ff0c18 94
mbed_official 146:f64d43ff0c18 95 /*! @brief DSPI data shifter direction options for a given CTAR*/
mbed_official 146:f64d43ff0c18 96 typedef enum _dspi_shift_direction {
mbed_official 146:f64d43ff0c18 97 kDspiMsbFirst = 0, /*!< Data transfers start with most significant bit.*/
mbed_official 146:f64d43ff0c18 98 kDspiLsbFirst = 1 /*!< Data transfers start with least significant bit.*/
mbed_official 146:f64d43ff0c18 99 } dspi_shift_direction_t;
mbed_official 146:f64d43ff0c18 100
mbed_official 146:f64d43ff0c18 101 /*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection*/
mbed_official 146:f64d43ff0c18 102 typedef enum _dspi_ctar_selection {
mbed_official 146:f64d43ff0c18 103 kDspiCtar0 = 0, /*!< CTAR0 selection option for master or slave mode*/
mbed_official 146:f64d43ff0c18 104 kDspiCtar1 = 1 /*!< CTAR1 selection option for master mode only*/
mbed_official 146:f64d43ff0c18 105 } dspi_ctar_selection_t;
mbed_official 146:f64d43ff0c18 106
mbed_official 146:f64d43ff0c18 107 /*! @brief DSPI Peripheral Chip Select (PCS) Polarity configuration.*/
mbed_official 146:f64d43ff0c18 108 typedef enum _dspi_pcs_polarity_config {
mbed_official 146:f64d43ff0c18 109 kDspiPcs_ActiveHigh = 0, /*!< PCS Active High (idles low)*/
mbed_official 146:f64d43ff0c18 110 kDspiPcs_ActiveLow = 1 /*!< PCS Active Low (idles high)*/
mbed_official 146:f64d43ff0c18 111 } dspi_pcs_polarity_config_t;
mbed_official 146:f64d43ff0c18 112
mbed_official 146:f64d43ff0c18 113 /*! @brief DSPI Peripheral Chip Select (PCS) configuration (which PCS to configure)*/
mbed_official 146:f64d43ff0c18 114 typedef enum _dspi_which_pcs_config {
mbed_official 146:f64d43ff0c18 115 kDspiPcs0 = 1 << 0, /*!< PCS[0] */
mbed_official 146:f64d43ff0c18 116 kDspiPcs1 = 1 << 1, /*!< PCS[1] */
mbed_official 146:f64d43ff0c18 117 kDspiPcs2 = 1 << 2, /*!< PCS[2] */
mbed_official 146:f64d43ff0c18 118 kDspiPcs3 = 1 << 3, /*!< PCS[3] */
mbed_official 146:f64d43ff0c18 119 kDspiPcs4 = 1 << 4, /*!< PCS[4] */
mbed_official 146:f64d43ff0c18 120 kDspiPcs5 = 1 << 5 /*!< PCS[5] */
mbed_official 146:f64d43ff0c18 121 } dspi_which_pcs_config_t;
mbed_official 146:f64d43ff0c18 122
mbed_official 146:f64d43ff0c18 123 /*!
mbed_official 146:f64d43ff0c18 124 * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer
mbed_official 146:f64d43ff0c18 125 * Format. This field is valid only when CPHA bit in CTAR register is 0.
mbed_official 146:f64d43ff0c18 126 */
mbed_official 146:f64d43ff0c18 127 typedef enum _dspi_master_sample_point {
mbed_official 146:f64d43ff0c18 128 kDspiSckToSin_0Clock = 0, /*!< 0 system clocks between SCK edge and SIN sample*/
mbed_official 146:f64d43ff0c18 129 kDspiSckToSin_1Clock = 1, /*!< 1 system clock between SCK edge and SIN sample*/
mbed_official 146:f64d43ff0c18 130 kDspiSckToSin_2Clock = 2 /*!< 2 system clocks between SCK edge and SIN sample*/
mbed_official 146:f64d43ff0c18 131 } dspi_master_sample_point_t;
mbed_official 146:f64d43ff0c18 132
mbed_official 146:f64d43ff0c18 133 /*! @brief DSPI FIFO selects*/
mbed_official 146:f64d43ff0c18 134 typedef enum _dspi_fifo {
mbed_official 146:f64d43ff0c18 135 kDspiTxFifo = 0, /*!< DSPI Tx FIFO*/
mbed_official 146:f64d43ff0c18 136 kDspiRxFifo = 1 /*!< DSPI Rx FIFO.*/
mbed_official 146:f64d43ff0c18 137 } dspi_fifo_t;
mbed_official 146:f64d43ff0c18 138
mbed_official 324:406fd2029f23 139 /*! @brief DSPI Tx FIFO Fill and Rx FIFO Drain DMA or Interrupt configuration */
mbed_official 324:406fd2029f23 140 typedef enum _dspi_dma_or_int_mode {
mbed_official 324:406fd2029f23 141 kDspiGenerateIntReq = 0, /*!< Desired flag generates an Interrupt request */
mbed_official 324:406fd2029f23 142 kDspiGenerateDmaReq = 1 /*!< Desired flag generates a DMA request */
mbed_official 324:406fd2029f23 143 } dspi_dma_or_int_mode_t;
mbed_official 324:406fd2029f23 144
mbed_official 146:f64d43ff0c18 145 /*! @brief DSPI status flags and interrupt request enable*/
mbed_official 146:f64d43ff0c18 146 typedef enum _dspi_status_and_interrupt_request {
mbed_official 146:f64d43ff0c18 147 kDspiTxComplete = BP_SPI_RSER_TCF_RE, /*!< TCF status/interrupt enable */
mbed_official 146:f64d43ff0c18 148 kDspiTxAndRxStatus = BP_SPI_SR_TXRXS, /*!< TXRXS status only, no interrupt*/
mbed_official 146:f64d43ff0c18 149 kDspiEndOfQueue = BP_SPI_RSER_EOQF_RE, /*!< EOQF status/interrupt enable*/
mbed_official 146:f64d43ff0c18 150 kDspiTxFifoUnderflow = BP_SPI_RSER_TFUF_RE, /*!< TFUF status/interrupt enable*/
mbed_official 146:f64d43ff0c18 151 kDspiTxFifoFillRequest = BP_SPI_RSER_TFFF_RE, /*!< TFFF status/interrupt enable*/
mbed_official 146:f64d43ff0c18 152 kDspiRxFifoOverflow = BP_SPI_RSER_RFOF_RE, /*!< RFOF status/interrupt enable*/
mbed_official 146:f64d43ff0c18 153 kDspiRxFifoDrainRequest = BP_SPI_RSER_RFDF_RE /*!< RFDF status/interrupt enable*/
mbed_official 146:f64d43ff0c18 154 } dspi_status_and_interrupt_request_t;
mbed_official 146:f64d43ff0c18 155
mbed_official 146:f64d43ff0c18 156 /*! @brief DSPI FIFO counter or pointer defines based on bit positions*/
mbed_official 146:f64d43ff0c18 157 typedef enum _dspi_fifo_counter_pointer {
mbed_official 146:f64d43ff0c18 158 kDspiRxFifoPointer = BP_SPI_SR_POPNXTPTR, /*!< Rx FIFO pointer*/
mbed_official 146:f64d43ff0c18 159 kDspiRxFifoCounter = BP_SPI_SR_RXCTR, /*!< Rx FIFO counter*/
mbed_official 146:f64d43ff0c18 160 kDspiTxFifoPointer = BP_SPI_SR_TXNXTPTR, /*!< Tx FIFO pointer*/
mbed_official 146:f64d43ff0c18 161 kDspiTxFifoCounter = BP_SPI_SR_TXCTR /*!< Tx FIFO counter*/
mbed_official 146:f64d43ff0c18 162 } dspi_fifo_counter_pointer_t;
mbed_official 146:f64d43ff0c18 163
mbed_official 324:406fd2029f23 164 /*! @brief DSPI delay type selection*/
mbed_official 324:406fd2029f23 165 typedef enum _dspi_delay_type {
mbed_official 324:406fd2029f23 166 kDspiPcsToSck = 1, /*!< PCS-to-SCK delay */
mbed_official 324:406fd2029f23 167 kDspiLastSckToPcs = 2, /*!< Last SCK edge to PCS delay */
mbed_official 324:406fd2029f23 168 kDspiAfterTransfer = 3, /*!< Delay between transfers */
mbed_official 324:406fd2029f23 169 } dspi_delay_type_t;
mbed_official 324:406fd2029f23 170
mbed_official 146:f64d43ff0c18 171 /*!
mbed_official 146:f64d43ff0c18 172 * @brief DSPI data format settings configuration structure
mbed_official 146:f64d43ff0c18 173 *
mbed_official 146:f64d43ff0c18 174 * This structure contains the data format settings. These settings apply to a specific
mbed_official 146:f64d43ff0c18 175 * CTARn register, which the user must provide in this structure.
mbed_official 146:f64d43ff0c18 176 */
mbed_official 146:f64d43ff0c18 177 typedef struct DspiDataFormatConfig {
mbed_official 146:f64d43ff0c18 178 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16 (master), 32 (slave) */
mbed_official 146:f64d43ff0c18 179 dspi_clock_polarity_t clkPolarity; /*!< Active high or low clock polarity*/
mbed_official 146:f64d43ff0c18 180 dspi_clock_phase_t clkPhase; /*!< Clock phase setting to change and capture data*/
mbed_official 146:f64d43ff0c18 181 dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction
mbed_official 146:f64d43ff0c18 182 This setting relevant only in master mode and
mbed_official 146:f64d43ff0c18 183 can be ignored in slave mode */
mbed_official 146:f64d43ff0c18 184 } dspi_data_format_config_t;
mbed_official 146:f64d43ff0c18 185
mbed_official 146:f64d43ff0c18 186 /*!
mbed_official 146:f64d43ff0c18 187 * @brief DSPI hardware configuration settings for slave mode.
mbed_official 146:f64d43ff0c18 188 *
mbed_official 324:406fd2029f23 189 * Use an instance of this structure with the DSPI_HAL_SlaveInit() to configure the
mbed_official 146:f64d43ff0c18 190 * most common settings of the DSPI peripheral in slave mode with a single function call.
mbed_official 146:f64d43ff0c18 191 */
mbed_official 146:f64d43ff0c18 192 typedef struct DspiSlaveConfig {
mbed_official 146:f64d43ff0c18 193 bool isEnabled; /*!< Set to true to enable the DSPI peripheral. */
mbed_official 146:f64d43ff0c18 194 dspi_data_format_config_t dataConfig; /*!< Data format configuration structure */
mbed_official 146:f64d43ff0c18 195 bool isTxFifoDisabled; /*!< Disable(1) or Enable(0) Tx FIFO */
mbed_official 146:f64d43ff0c18 196 bool isRxFifoDisabled; /*!< Disable(1) or Enable(0) Rx FIFO */
mbed_official 146:f64d43ff0c18 197 } dspi_slave_config_t;
mbed_official 146:f64d43ff0c18 198
mbed_official 146:f64d43ff0c18 199 /*!
mbed_official 146:f64d43ff0c18 200 * @brief DSPI baud rate divisors settings configuration structure.
mbed_official 146:f64d43ff0c18 201 *
mbed_official 146:f64d43ff0c18 202 * Note: These settings are relevant only in master mode.
mbed_official 324:406fd2029f23 203 * This structure contains the baud rate divisor settings, which provides the user with the option
mbed_official 324:406fd2029f23 204 * to explicitly set these baud rate divisors. In addition, the user must also set the
mbed_official 146:f64d43ff0c18 205 * CTARn register with the divisor settings.
mbed_official 146:f64d43ff0c18 206 */
mbed_official 146:f64d43ff0c18 207 typedef struct DspiBaudRateDivisors {
mbed_official 146:f64d43ff0c18 208 bool doubleBaudRate; /*!< Double Baud rate parameter setting */
mbed_official 146:f64d43ff0c18 209 uint32_t prescaleDivisor; /*!< Baud Rate Pre-scalar parameter setting*/
mbed_official 146:f64d43ff0c18 210 uint32_t baudRateDivisor; /*!< Baud Rate scaler parameter setting */
mbed_official 146:f64d43ff0c18 211 } dspi_baud_rate_divisors_t;
mbed_official 146:f64d43ff0c18 212
mbed_official 146:f64d43ff0c18 213 /*!
mbed_official 146:f64d43ff0c18 214 * @brief DSPI command and data configuration structure
mbed_official 146:f64d43ff0c18 215 *
mbed_official 146:f64d43ff0c18 216 * Note: This structure is used with the PUSHR register, which
mbed_official 146:f64d43ff0c18 217 * provides the means to write to the Tx FIFO. Data written to this register is
mbed_official 146:f64d43ff0c18 218 * transferred to the Tx FIFO. Eight or sixteen-bit write accesses to the PUSHR transfer all
mbed_official 146:f64d43ff0c18 219 * 32 register bits to the Tx FIFO. The register structure is different in master and slave
mbed_official 146:f64d43ff0c18 220 * modes. In master mode, the register provides 16-bit command and 16-bit data to the Tx
mbed_official 146:f64d43ff0c18 221 * FIFO. In slave mode all 32 register bits can be used as data, supporting up to 32-bit SPI
mbed_official 146:f64d43ff0c18 222 * frame operation.
mbed_official 146:f64d43ff0c18 223 */
mbed_official 146:f64d43ff0c18 224 typedef struct DspiCommandDataConfig {
mbed_official 146:f64d43ff0c18 225 bool isChipSelectContinuous; /*!< Option to enable the continuous assertion of chip select
mbed_official 146:f64d43ff0c18 226 between transfers*/
mbed_official 146:f64d43ff0c18 227 dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes
mbed_official 146:f64d43ff0c18 228 Register (CTAR) to use for CTAS*/
mbed_official 146:f64d43ff0c18 229 dspi_which_pcs_config_t whichPcs; /*!< The desired PCS signal to use for the data transfer*/
mbed_official 146:f64d43ff0c18 230 bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue*/
mbed_official 146:f64d43ff0c18 231 bool clearTransferCount; /*!< Clears SPI_TCNT field; cleared before transmission starts*/
mbed_official 146:f64d43ff0c18 232 } dspi_command_config_t;
mbed_official 146:f64d43ff0c18 233
mbed_official 146:f64d43ff0c18 234 /*******************************************************************************
mbed_official 324:406fd2029f23 235 * Variables
mbed_official 324:406fd2029f23 236 ******************************************************************************/
mbed_official 324:406fd2029f23 237
mbed_official 324:406fd2029f23 238 extern const uint32_t spi_base_addr[];
mbed_official 324:406fd2029f23 239
mbed_official 324:406fd2029f23 240 /*******************************************************************************
mbed_official 146:f64d43ff0c18 241 * API
mbed_official 146:f64d43ff0c18 242 ******************************************************************************/
mbed_official 146:f64d43ff0c18 243
mbed_official 146:f64d43ff0c18 244 #if defined(__cplusplus)
mbed_official 146:f64d43ff0c18 245 extern "C" {
mbed_official 146:f64d43ff0c18 246 #endif
mbed_official 146:f64d43ff0c18 247
mbed_official 146:f64d43ff0c18 248 /*!
mbed_official 146:f64d43ff0c18 249 * @name Configuration
mbed_official 146:f64d43ff0c18 250 * @{
mbed_official 146:f64d43ff0c18 251 */
mbed_official 146:f64d43ff0c18 252
mbed_official 146:f64d43ff0c18 253 /*!
mbed_official 146:f64d43ff0c18 254 * @brief Restores the DSPI to reset the configuration.
mbed_official 146:f64d43ff0c18 255 *
mbed_official 146:f64d43ff0c18 256 * This function basically resets all of the DSPI registers to their default setting including
mbed_official 146:f64d43ff0c18 257 * disabling the module.
mbed_official 146:f64d43ff0c18 258 *
mbed_official 324:406fd2029f23 259 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 260 */
mbed_official 324:406fd2029f23 261 void DSPI_HAL_Init(uint32_t baseAddr);
mbed_official 146:f64d43ff0c18 262
mbed_official 146:f64d43ff0c18 263 /*!
mbed_official 324:406fd2029f23 264 * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0.
mbed_official 146:f64d43ff0c18 265 *
mbed_official 324:406fd2029f23 266 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 267 */
mbed_official 324:406fd2029f23 268 static inline void DSPI_HAL_Enable(uint32_t baseAddr)
mbed_official 146:f64d43ff0c18 269 {
mbed_official 324:406fd2029f23 270 BW_SPI_MCR_MDIS(baseAddr, 0);
mbed_official 146:f64d43ff0c18 271 }
mbed_official 146:f64d43ff0c18 272
mbed_official 146:f64d43ff0c18 273 /*!
mbed_official 146:f64d43ff0c18 274 * @brief Disables the DSPI peripheral, sets MCR MDIS to 1.
mbed_official 146:f64d43ff0c18 275 *
mbed_official 324:406fd2029f23 276 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 277 */
mbed_official 324:406fd2029f23 278 static inline void DSPI_HAL_Disable(uint32_t baseAddr)
mbed_official 146:f64d43ff0c18 279 {
mbed_official 324:406fd2029f23 280 BW_SPI_MCR_MDIS(baseAddr, 1);
mbed_official 146:f64d43ff0c18 281 }
mbed_official 146:f64d43ff0c18 282
mbed_official 146:f64d43ff0c18 283 /*!
mbed_official 146:f64d43ff0c18 284 * @brief Sets the DSPI baud rate in bits per second.
mbed_official 146:f64d43ff0c18 285 *
mbed_official 146:f64d43ff0c18 286 * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest
mbed_official 146:f64d43ff0c18 287 * possible baud rate without exceeding the desired baud rate, and returns the calculated
mbed_official 146:f64d43ff0c18 288 * baud rate in bits-per-second. It requires that the caller also provide the frequency of the
mbed_official 146:f64d43ff0c18 289 * module source clock (in Hertz).
mbed_official 146:f64d43ff0c18 290 *
mbed_official 324:406fd2029f23 291 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 292 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type
mbed_official 146:f64d43ff0c18 293 * dspi_ctar_selection_t
mbed_official 146:f64d43ff0c18 294 * @param bitsPerSec The desired baud rate in bits per second
mbed_official 146:f64d43ff0c18 295 * @param sourceClockInHz Module source input clock in Hertz
mbed_official 146:f64d43ff0c18 296 * @return The actual calculated baud rate
mbed_official 146:f64d43ff0c18 297 */
mbed_official 324:406fd2029f23 298 uint32_t DSPI_HAL_SetBaudRate(uint32_t baseAddr, dspi_ctar_selection_t whichCtar,
mbed_official 324:406fd2029f23 299 uint32_t bitsPerSec, uint32_t sourceClockInHz);
mbed_official 146:f64d43ff0c18 300
mbed_official 146:f64d43ff0c18 301 /*!
mbed_official 146:f64d43ff0c18 302 * @brief Configures the baud rate divisors manually.
mbed_official 146:f64d43ff0c18 303 *
mbed_official 146:f64d43ff0c18 304 * This function allows the caller to manually set the baud rate divisors in the event that
mbed_official 324:406fd2029f23 305 * these dividers are known and the caller does not wish to call the DSPI_HAL_SetBaudRate function.
mbed_official 146:f64d43ff0c18 306 *
mbed_official 324:406fd2029f23 307 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 308 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
mbed_official 146:f64d43ff0c18 309 * dspi_ctar_selection_t
mbed_official 146:f64d43ff0c18 310 * @param divisors Pointer to a structure containing the user defined baud rate divisor settings
mbed_official 146:f64d43ff0c18 311 */
mbed_official 324:406fd2029f23 312 void DSPI_HAL_SetBaudDivisors(uint32_t baseAddr,
mbed_official 324:406fd2029f23 313 dspi_ctar_selection_t whichCtar,
mbed_official 324:406fd2029f23 314 const dspi_baud_rate_divisors_t * divisors);
mbed_official 146:f64d43ff0c18 315
mbed_official 146:f64d43ff0c18 316 /*!
mbed_official 146:f64d43ff0c18 317 * @brief Configures the DSPI for master or slave.
mbed_official 146:f64d43ff0c18 318 *
mbed_official 324:406fd2029f23 319 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 320 * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t
mbed_official 146:f64d43ff0c18 321 */
mbed_official 324:406fd2029f23 322 static inline void DSPI_HAL_SetMasterSlaveMode(uint32_t baseAddr, dspi_master_slave_mode_t mode)
mbed_official 146:f64d43ff0c18 323 {
mbed_official 324:406fd2029f23 324 BW_SPI_MCR_MSTR(baseAddr, (uint32_t)mode);
mbed_official 324:406fd2029f23 325 }
mbed_official 324:406fd2029f23 326
mbed_official 324:406fd2029f23 327 /*!
mbed_official 324:406fd2029f23 328 * @brief Returns whether the DSPI module is in master mode.
mbed_official 324:406fd2029f23 329 *
mbed_official 324:406fd2029f23 330 * @param baseAddr Module base address
mbed_official 324:406fd2029f23 331 * @retval true The module is in master mode.
mbed_official 324:406fd2029f23 332 * @retval false The module is in slave mode.
mbed_official 324:406fd2029f23 333 */
mbed_official 324:406fd2029f23 334 static inline bool DSPI_HAL_IsMaster(uint32_t baseAddr)
mbed_official 324:406fd2029f23 335 {
mbed_official 324:406fd2029f23 336 return (bool)BR_SPI_MCR_MSTR(baseAddr);
mbed_official 146:f64d43ff0c18 337 }
mbed_official 146:f64d43ff0c18 338
mbed_official 146:f64d43ff0c18 339 /*!
mbed_official 146:f64d43ff0c18 340 * @brief Configures the DSPI for the continuous SCK operation.
mbed_official 146:f64d43ff0c18 341 *
mbed_official 324:406fd2029f23 342 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 343 * @param enable Enables (true) or disables(false) continuous SCK operation.
mbed_official 146:f64d43ff0c18 344 */
mbed_official 324:406fd2029f23 345 static inline void DSPI_HAL_SetContinuousSckCmd(uint32_t baseAddr, bool enable)
mbed_official 146:f64d43ff0c18 346 {
mbed_official 324:406fd2029f23 347 BW_SPI_MCR_CONT_SCKE(baseAddr, (enable == true));
mbed_official 146:f64d43ff0c18 348 }
mbed_official 146:f64d43ff0c18 349
mbed_official 146:f64d43ff0c18 350 /*!
mbed_official 146:f64d43ff0c18 351 * @brief Configures the DSPI to enable modified timing format.
mbed_official 146:f64d43ff0c18 352 *
mbed_official 324:406fd2029f23 353 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 354 * @param enable Enables (true) or disables(false) modified timing format.
mbed_official 146:f64d43ff0c18 355 */
mbed_official 324:406fd2029f23 356 static inline void DSPI_HAL_SetModifiedTimingFormatCmd(uint32_t baseAddr, bool enable)
mbed_official 146:f64d43ff0c18 357 {
mbed_official 324:406fd2029f23 358 BW_SPI_MCR_MTFE(baseAddr, (enable == true));
mbed_official 146:f64d43ff0c18 359 }
mbed_official 146:f64d43ff0c18 360
mbed_official 146:f64d43ff0c18 361 /*!
mbed_official 146:f64d43ff0c18 362 * @brief Configures the DSPI peripheral chip select strobe enable. Configures the PCS[5] to be the
mbed_official 146:f64d43ff0c18 363 * active-low PCS Strobe output.
mbed_official 146:f64d43ff0c18 364 *
mbed_official 146:f64d43ff0c18 365 * PCS[5] is a special case that can be configured as an active low PCS strobe or as a Peripheral
mbed_official 146:f64d43ff0c18 366 * Chip Select in master mode. When configured as a strobe, it provides a signal to an external
mbed_official 146:f64d43ff0c18 367 * demultiplexer to decode PCS[0] to PCS[4] signals into as many as 128 glitch-free PCS signals.
mbed_official 146:f64d43ff0c18 368 *
mbed_official 324:406fd2029f23 369 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 370 * @param enable Enable (true) PCS[5] to operate as the peripheral chip select (PCS) strobe
mbed_official 146:f64d43ff0c18 371 * If disable (false), PCS[5] operates as a peripheral chip select
mbed_official 146:f64d43ff0c18 372 */
mbed_official 324:406fd2029f23 373 static inline void DSPI_HAL_SetPcsStrobeCmd(uint32_t baseAddr, bool enable)
mbed_official 146:f64d43ff0c18 374 {
mbed_official 324:406fd2029f23 375 BW_SPI_MCR_PCSSE(baseAddr, (enable == true));
mbed_official 146:f64d43ff0c18 376 }
mbed_official 146:f64d43ff0c18 377
mbed_official 146:f64d43ff0c18 378 /*!
mbed_official 146:f64d43ff0c18 379 * @brief Configures the DSPI received FIFO overflow overwrite enable.
mbed_official 146:f64d43ff0c18 380 *
mbed_official 146:f64d43ff0c18 381 * When enabled, this function allows incoming receive data to overwrite the existing data in the
mbed_official 146:f64d43ff0c18 382 * receive shift register when the Rx FIFO is full. Otherwise when disabled, the incoming data
mbed_official 146:f64d43ff0c18 383 * is ignored when the RX FIFO is full.
mbed_official 146:f64d43ff0c18 384 *
mbed_official 324:406fd2029f23 385 * @param baseAddr Module base address.
mbed_official 146:f64d43ff0c18 386 * @param enable If enabled (true), allows incoming data to overwrite Rx FIFO contents when full,
mbed_official 146:f64d43ff0c18 387 * else incoming data is ignored.
mbed_official 146:f64d43ff0c18 388 */
mbed_official 324:406fd2029f23 389 static inline void DSPI_HAL_SetRxFifoOverwriteCmd(uint32_t baseAddr, bool enable)
mbed_official 146:f64d43ff0c18 390 {
mbed_official 324:406fd2029f23 391 BW_SPI_MCR_ROOE(baseAddr, (enable == true));
mbed_official 146:f64d43ff0c18 392 }
mbed_official 146:f64d43ff0c18 393
mbed_official 146:f64d43ff0c18 394 /*!
mbed_official 146:f64d43ff0c18 395 * @brief Configures the DSPI peripheral chip select polarity.
mbed_official 146:f64d43ff0c18 396 *
mbed_official 146:f64d43ff0c18 397 * This function takes in the desired peripheral chip select (PCS) and it's
mbed_official 146:f64d43ff0c18 398 * corresponding desired polarity and configures the PCS signal to operate with the
mbed_official 146:f64d43ff0c18 399 * desired characteristic.
mbed_official 146:f64d43ff0c18 400 *
mbed_official 324:406fd2029f23 401 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 402 * @param pcs The particular peripheral chip select (parameter value is of type
mbed_official 146:f64d43ff0c18 403 * dspi_which_pcs_config_t) for which we wish to apply the active high or active
mbed_official 146:f64d43ff0c18 404 * low characteristic.
mbed_official 146:f64d43ff0c18 405 * @param activeLowOrHigh The setting for either "active high, inactive low (0)" or
mbed_official 146:f64d43ff0c18 406 * "active low, inactive high(1)" of type dspi_pcs_polarity_config_t.
mbed_official 146:f64d43ff0c18 407 */
mbed_official 324:406fd2029f23 408 void DSPI_HAL_SetPcsPolarityMode(uint32_t baseAddr, dspi_which_pcs_config_t pcs,
mbed_official 324:406fd2029f23 409 dspi_pcs_polarity_config_t activeLowOrHigh);
mbed_official 146:f64d43ff0c18 410
mbed_official 146:f64d43ff0c18 411 /*!
mbed_official 324:406fd2029f23 412 * @brief Enables (or disables) the DSPI FIFOs.
mbed_official 146:f64d43ff0c18 413 *
mbed_official 146:f64d43ff0c18 414 * This function allows the caller to disable/enable the Tx and Rx FIFOs (independently).
mbed_official 324:406fd2029f23 415 * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO
mbed_official 324:406fd2029f23 416 * configuration. To enable, the caller must pass in a logic 1 (true).
mbed_official 146:f64d43ff0c18 417 *
mbed_official 324:406fd2029f23 418 * @param baseAddr Module instance number
mbed_official 324:406fd2029f23 419 * @param enableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO
mbed_official 324:406fd2029f23 420 * @param enableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO
mbed_official 146:f64d43ff0c18 421 */
mbed_official 324:406fd2029f23 422 void DSPI_HAL_SetFifoCmd(uint32_t baseAddr, bool enableTxFifo, bool enableRxFifo);
mbed_official 146:f64d43ff0c18 423
mbed_official 146:f64d43ff0c18 424 /*!
mbed_official 146:f64d43ff0c18 425 * @brief Flushes the DSPI FIFOs.
mbed_official 146:f64d43ff0c18 426 *
mbed_official 324:406fd2029f23 427 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 428 * @param enableFlushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO
mbed_official 146:f64d43ff0c18 429 * @param enableFlushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO
mbed_official 146:f64d43ff0c18 430 */
mbed_official 324:406fd2029f23 431 void DSPI_HAL_SetFlushFifoCmd(uint32_t baseAddr, bool enableFlushTxFifo, bool enableFlushRxFifo);
mbed_official 146:f64d43ff0c18 432
mbed_official 146:f64d43ff0c18 433
mbed_official 146:f64d43ff0c18 434 /*!
mbed_official 324:406fd2029f23 435 * @brief Configures the time when the DSPI master samples SIN in the Modified Transfer Format.
mbed_official 146:f64d43ff0c18 436 *
mbed_official 146:f64d43ff0c18 437 * This function controls when the DSPI master samples SIN (data in) in the Modified Transfer
mbed_official 146:f64d43ff0c18 438 * Format. Note that this is valid only when the CPHA bit in the CTAR register is 0.
mbed_official 146:f64d43ff0c18 439 *
mbed_official 324:406fd2029f23 440 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 441 * @param samplePnt selects when the data in (SIN) is sampled, of type dspi_master_sample_point_t.
mbed_official 146:f64d43ff0c18 442 * This value selects either 0, 1, or 2 system clocks between the SCK edge
mbed_official 146:f64d43ff0c18 443 * and the SIN (data in) sample.
mbed_official 146:f64d43ff0c18 444 */
mbed_official 324:406fd2029f23 445 static inline void DSPI_HAL_SetDatainSamplepointMode(uint32_t baseAddr,
mbed_official 146:f64d43ff0c18 446 dspi_master_sample_point_t samplePnt)
mbed_official 146:f64d43ff0c18 447 {
mbed_official 324:406fd2029f23 448 BW_SPI_MCR_SMPL_PT(baseAddr, samplePnt);
mbed_official 146:f64d43ff0c18 449 }
mbed_official 146:f64d43ff0c18 450
mbed_official 146:f64d43ff0c18 451
mbed_official 146:f64d43ff0c18 452 /*!
mbed_official 146:f64d43ff0c18 453 * @brief Starts the DSPI transfers, clears HALT bit in MCR.
mbed_official 146:f64d43ff0c18 454 *
mbed_official 146:f64d43ff0c18 455 * This function call called whenever the module is ready to begin data transfers in either master
mbed_official 146:f64d43ff0c18 456 * or slave mode.
mbed_official 146:f64d43ff0c18 457 *
mbed_official 324:406fd2029f23 458 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 459 */
mbed_official 324:406fd2029f23 460 static inline void DSPI_HAL_StartTransfer(uint32_t baseAddr)
mbed_official 146:f64d43ff0c18 461 {
mbed_official 324:406fd2029f23 462 BW_SPI_MCR_HALT(baseAddr, 0);
mbed_official 146:f64d43ff0c18 463 }
mbed_official 146:f64d43ff0c18 464
mbed_official 146:f64d43ff0c18 465 /*!
mbed_official 146:f64d43ff0c18 466 * @brief Stops (halts) DSPI transfers, sets HALT bit in MCR.
mbed_official 146:f64d43ff0c18 467 *
mbed_official 146:f64d43ff0c18 468 * This function call stops data transfers in either master or slave mode.
mbed_official 146:f64d43ff0c18 469 *
mbed_official 324:406fd2029f23 470 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 471 */
mbed_official 324:406fd2029f23 472 static inline void DSPI_HAL_StopTransfer(uint32_t baseAddr)
mbed_official 146:f64d43ff0c18 473 {
mbed_official 324:406fd2029f23 474 BW_SPI_MCR_HALT(baseAddr, 1);
mbed_official 146:f64d43ff0c18 475 }
mbed_official 146:f64d43ff0c18 476
mbed_official 146:f64d43ff0c18 477 /*!
mbed_official 146:f64d43ff0c18 478 * @brief Configures the data format for a particular CTAR.
mbed_official 146:f64d43ff0c18 479 *
mbed_official 146:f64d43ff0c18 480 * This function configures the bits-per-frame, polarity, phase, and shift direction for a
mbed_official 146:f64d43ff0c18 481 * particular CTAR. An example use case is as follows:
mbed_official 146:f64d43ff0c18 482 @code
mbed_official 146:f64d43ff0c18 483 dspi_data_format_config_t dataFormat;
mbed_official 146:f64d43ff0c18 484 dataFormat.bitsPerFrame = 16;
mbed_official 146:f64d43ff0c18 485 dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow;
mbed_official 146:f64d43ff0c18 486 dataFormat.clkPhase = kDspiClockPhase_FirstEdge;
mbed_official 146:f64d43ff0c18 487 dataFormat.direction = kDspiMsbFirst;
mbed_official 324:406fd2029f23 488 DSPI_HAL_SetDataFormat(instance, kDspiCtar0, &dataFormat);
mbed_official 146:f64d43ff0c18 489 @endcode
mbed_official 146:f64d43ff0c18 490 *
mbed_official 324:406fd2029f23 491 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 492 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
mbed_official 146:f64d43ff0c18 493 * dspi_ctar_selection_t.
mbed_official 324:406fd2029f23 494 * @param config Pointer to structure containing user defined data format configuration settings.
mbed_official 146:f64d43ff0c18 495 * @return An error code or kStatus_DSPI_Success
mbed_official 146:f64d43ff0c18 496 */
mbed_official 324:406fd2029f23 497 dspi_status_t DSPI_HAL_SetDataFormat(uint32_t baseAddr,
mbed_official 324:406fd2029f23 498 dspi_ctar_selection_t whichCtar,
mbed_official 324:406fd2029f23 499 const dspi_data_format_config_t * config);
mbed_official 146:f64d43ff0c18 500
mbed_official 146:f64d43ff0c18 501 /*!
mbed_official 324:406fd2029f23 502 * @brief Manually configures the delay prescaler and scaler for a particular CTAR.
mbed_official 324:406fd2029f23 503 *
mbed_official 324:406fd2029f23 504 * This function configures the PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK),
mbed_official 324:406fd2029f23 505 * after SCK delay pre-scalar (PASC) and scalar (ASC), and the delay
mbed_official 324:406fd2029f23 506 * after transfer pre-scalar (PDT)and scalar (DT).
mbed_official 146:f64d43ff0c18 507 *
mbed_official 324:406fd2029f23 508 * These delay names are available in type dspi_delay_type_t.
mbed_official 146:f64d43ff0c18 509 *
mbed_official 324:406fd2029f23 510 * The user passes which delay they want to configure along with the prescaler and scaler value.
mbed_official 324:406fd2029f23 511 * This allows the user to directly set the prescaler/scaler values if they have
mbed_official 324:406fd2029f23 512 * pre-calculated them or if they simply wish to manually increment either value.
mbed_official 324:406fd2029f23 513 *
mbed_official 324:406fd2029f23 514 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 515 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
mbed_official 146:f64d43ff0c18 516 * dspi_ctar_selection_t.
mbed_official 324:406fd2029f23 517 * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3).
mbed_official 324:406fd2029f23 518 * @param prescaler The scaler delay value (can be any integer between 0 to 15).
mbed_official 324:406fd2029f23 519 * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
mbed_official 146:f64d43ff0c18 520 */
mbed_official 324:406fd2029f23 521 void DSPI_HAL_SetDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar, uint32_t prescaler,
mbed_official 324:406fd2029f23 522 uint32_t scaler, dspi_delay_type_t whichDelay);
mbed_official 146:f64d43ff0c18 523
mbed_official 146:f64d43ff0c18 524
mbed_official 146:f64d43ff0c18 525 /*!
mbed_official 324:406fd2029f23 526 * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds.
mbed_official 324:406fd2029f23 527 *
mbed_official 324:406fd2029f23 528 * This function calculates the values for:
mbed_official 324:406fd2029f23 529 * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
mbed_official 324:406fd2029f23 530 * After SCK delay pre-scalar (PASC) and scalar (ASC), or
mbed_official 324:406fd2029f23 531 * Delay after transfer pre-scalar (PDT)and scalar (DT).
mbed_official 324:406fd2029f23 532 *
mbed_official 324:406fd2029f23 533 * These delay names are available in type dspi_delay_type_t.
mbed_official 146:f64d43ff0c18 534 *
mbed_official 324:406fd2029f23 535 * The user passes which delay they want to configure along with the desired delay value in
mbed_official 324:406fd2029f23 536 * nano-seconds. The function calculates the values needed for the prescaler and scaler and
mbed_official 324:406fd2029f23 537 * returning the actual calculated delay as an exact delay match may not be possible. In this
mbed_official 324:406fd2029f23 538 * case, the closest match is calculated without going below the desired delay value input.
mbed_official 324:406fd2029f23 539 * It is possible to input a very large delay value that exceeds the capability of the part, in
mbed_official 324:406fd2029f23 540 * which case the maximum supported delay will be returned. It is to the higher level
mbed_official 324:406fd2029f23 541 * peripheral driver to alert the user of an out of range delay input.
mbed_official 146:f64d43ff0c18 542 *
mbed_official 324:406fd2029f23 543 * @param baseAddr Module base address
mbed_official 324:406fd2029f23 544 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type
mbed_official 324:406fd2029f23 545 * dspi_ctar_selection_t.
mbed_official 324:406fd2029f23 546 * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
mbed_official 324:406fd2029f23 547 * @param sourceClockInHz Module source input clock in Hertz
mbed_official 324:406fd2029f23 548 * @param delayInNanoSec The desired delay value in nano-seconds.
mbed_official 324:406fd2029f23 549 * @return The actual calculated delay value.
mbed_official 146:f64d43ff0c18 550 */
mbed_official 324:406fd2029f23 551 uint32_t DSPI_HAL_CalculateDelay(uint32_t baseAddr, dspi_ctar_selection_t whichCtar,
mbed_official 324:406fd2029f23 552 dspi_delay_type_t whichDelay, uint32_t sourceClockInHz,
mbed_official 324:406fd2029f23 553 uint32_t delayInNanoSec);
mbed_official 146:f64d43ff0c18 554
mbed_official 146:f64d43ff0c18 555 /*@}*/
mbed_official 146:f64d43ff0c18 556
mbed_official 146:f64d43ff0c18 557 /*!
mbed_official 146:f64d43ff0c18 558 * @name Low power
mbed_official 146:f64d43ff0c18 559 * @{
mbed_official 146:f64d43ff0c18 560 */
mbed_official 146:f64d43ff0c18 561
mbed_official 146:f64d43ff0c18 562 /*!
mbed_official 146:f64d43ff0c18 563 * @brief Configures the DSPI operation during doze mode.
mbed_official 146:f64d43ff0c18 564 *
mbed_official 146:f64d43ff0c18 565 * This function provides support for an externally controlled doze mode, power-saving, mechanism.
mbed_official 146:f64d43ff0c18 566 * When disabled, the doze mode has no effect on the DSPI, and when enabled, the Doze mode
mbed_official 146:f64d43ff0c18 567 * disables the DSPI.
mbed_official 146:f64d43ff0c18 568 *
mbed_official 324:406fd2029f23 569 * @param baseAddr Module base address
mbed_official 324:406fd2029f23 570 * @param enable If disabled (false), the doze mode has no effect on the DSPI, if enabled (true),
mbed_official 324:406fd2029f23 571 * the doze mode disables the DSPI.
mbed_official 146:f64d43ff0c18 572 */
mbed_official 324:406fd2029f23 573 static inline void DSPI_HAL_SetDozemodeCmd(uint32_t baseAddr, bool enable)
mbed_official 146:f64d43ff0c18 574 {
mbed_official 324:406fd2029f23 575 BW_SPI_MCR_DOZE(baseAddr, (enable == true));
mbed_official 146:f64d43ff0c18 576 }
mbed_official 146:f64d43ff0c18 577
mbed_official 146:f64d43ff0c18 578 /*@}*/
mbed_official 146:f64d43ff0c18 579
mbed_official 146:f64d43ff0c18 580 /*!
mbed_official 146:f64d43ff0c18 581 * @name Interrupts
mbed_official 146:f64d43ff0c18 582 * @{
mbed_official 146:f64d43ff0c18 583 */
mbed_official 146:f64d43ff0c18 584
mbed_official 146:f64d43ff0c18 585 /*!
mbed_official 324:406fd2029f23 586 * @brief Configures the DSPI Tx FIFO fill request to generate DMA or interrupt requests.
mbed_official 324:406fd2029f23 587 *
mbed_official 324:406fd2029f23 588 * This function configures the DSPI Tx FIFO Fill flag to generate either
mbed_official 324:406fd2029f23 589 * an interrupt or DMA request. The user passes in which request they'd like to generate
mbed_official 324:406fd2029f23 590 * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
mbed_official 324:406fd2029f23 591 * Note, when disabling the request, the request type is don't care.
mbed_official 324:406fd2029f23 592 @code
mbed_official 324:406fd2029f23 593 DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA
mbed_official 324:406fd2029f23 594 DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt
mbed_official 324:406fd2029f23 595 DSPI_HAL_SetTxFifoFillDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable
mbed_official 324:406fd2029f23 596 @endcode
mbed_official 324:406fd2029f23 597 * @param baseAddr Module base address
mbed_official 324:406fd2029f23 598 * @param mode Configures the DSPI Tx FIFO Fill to generate an interrupt or DMA request
mbed_official 324:406fd2029f23 599 * @param enable Enable (true) or disable (false) the DSPI Tx FIFO Fill flag to generate requests
mbed_official 324:406fd2029f23 600 */
mbed_official 324:406fd2029f23 601 void DSPI_HAL_SetTxFifoFillDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable);
mbed_official 324:406fd2029f23 602
mbed_official 324:406fd2029f23 603 /*!
mbed_official 324:406fd2029f23 604 * @brief Configures the DSPI Rx FIFO Drain request to generate DMA or interrupt requests.
mbed_official 324:406fd2029f23 605 *
mbed_official 324:406fd2029f23 606 * This function configures the DSPI Rx FIFO Drain flag to generate either
mbed_official 324:406fd2029f23 607 * an interrupt or a DMA request. The user passes in which request they'd like to generate
mbed_official 324:406fd2029f23 608 * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request.
mbed_official 324:406fd2029f23 609 * Note, when disabling the request, the request type is don't care.
mbed_official 324:406fd2029f23 610 @code
mbed_official 324:406fd2029f23 611 DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateDmaReq, true); <- to enable DMA
mbed_official 324:406fd2029f23 612 DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, true); <- to enable Interrupt
mbed_official 324:406fd2029f23 613 DSPI_HAL_SetRxFifoDrainDmaIntMode(baseAddr, kDspiGenerateIntReq, false); <- to disable
mbed_official 324:406fd2029f23 614 @endcode
mbed_official 324:406fd2029f23 615 * @param baseAddr Module base address
mbed_official 324:406fd2029f23 616 * @param mode Configures the Rx FIFO Drain to generate an interrupt or DMA request
mbed_official 324:406fd2029f23 617 * @param enable Enable (true) or disable (false) the Rx FIFO Drain flag to generate requests
mbed_official 324:406fd2029f23 618 */
mbed_official 324:406fd2029f23 619 void DSPI_HAL_SetRxFifoDrainDmaIntMode(uint32_t baseAddr, dspi_dma_or_int_mode_t mode, bool enable);
mbed_official 324:406fd2029f23 620
mbed_official 324:406fd2029f23 621
mbed_official 324:406fd2029f23 622
mbed_official 324:406fd2029f23 623 /*!
mbed_official 146:f64d43ff0c18 624 * @brief Configures the DSPI interrupts.
mbed_official 146:f64d43ff0c18 625 *
mbed_official 324:406fd2029f23 626 * This function configures the various interrupt sources of the DSPI. The parameters are
mbed_official 324:406fd2029f23 627 * baseAddr, interrupt source, and enable/disable setting.
mbed_official 324:406fd2029f23 628 * The interrupt source is a typedef enumeration whose value is the bit position of the
mbed_official 146:f64d43ff0c18 629 * interrupt source setting within the RSER register. In the DSPI, all interrupt
mbed_official 146:f64d43ff0c18 630 * configuration settings are in one register. The typedef enum equates each
mbed_official 146:f64d43ff0c18 631 * interrupt source to the bit position defined in the device header file.
mbed_official 146:f64d43ff0c18 632 * The function uses these bit positions in its algorithm to enable/disable the
mbed_official 146:f64d43ff0c18 633 * interrupt source, where interrupt source is the dspi_status_and_interrupt_request_t type.
mbed_official 324:406fd2029f23 634 * Note, for Tx FIFO Fill and Rx FIFO Drain requests, use the functions:
mbed_official 324:406fd2029f23 635 * DSPI_HAL_SetTxFifoFillDmaIntMode and DSPI_HAL_SetRxFifoDrainDmaIntMode respectively as
mbed_official 324:406fd2029f23 636 * these requests can generate either an interrupt or DMA request.
mbed_official 324:406fd2029f23 637 @code
mbed_official 324:406fd2029f23 638 DSPI_HAL_SetIntMode(baseAddr, kDspiTxComplete, true); <- example use-case
mbed_official 324:406fd2029f23 639 @endcode
mbed_official 146:f64d43ff0c18 640 *
mbed_official 324:406fd2029f23 641 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 642 * @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t
mbed_official 146:f64d43ff0c18 643 * @param enable Enable (true) or disable (false) the interrupt source to generate requests
mbed_official 146:f64d43ff0c18 644 */
mbed_official 324:406fd2029f23 645 void DSPI_HAL_SetIntMode(uint32_t baseAddr,
mbed_official 146:f64d43ff0c18 646 dspi_status_and_interrupt_request_t interruptSrc,
mbed_official 146:f64d43ff0c18 647 bool enable);
mbed_official 146:f64d43ff0c18 648
mbed_official 146:f64d43ff0c18 649
mbed_official 146:f64d43ff0c18 650 /*!
mbed_official 324:406fd2029f23 651 * @brief Gets DSPI interrupt configuration, returns if interrupt request is enabled or disabled.
mbed_official 146:f64d43ff0c18 652 *
mbed_official 146:f64d43ff0c18 653 * This function returns the requested interrupt source setting (enabled or disabled, of
mbed_official 324:406fd2029f23 654 * type bool). The parameters to pass in are baseAddr and interrupt source. It utilizes the
mbed_official 324:406fd2029f23 655 * same enumeration definitions for the interrupt sources as described in the "interrupt configuration"
mbed_official 146:f64d43ff0c18 656 * function. The function uses these bit positions in its algorithm to obtain the desired
mbed_official 146:f64d43ff0c18 657 * interrupt source setting.
mbed_official 324:406fd2029f23 658 * Note, for Tx FIFO Fill and Rx FIFO Drain requests, this returns whether or not their
mbed_official 324:406fd2029f23 659 * requests are enabled.
mbed_official 324:406fd2029f23 660 @code
mbed_official 324:406fd2029f23 661 getInterruptSetting = DSPI_HAL_GetIntMode(baseAddr, kDspiTxComplete);
mbed_official 324:406fd2029f23 662 @endcode
mbed_official 146:f64d43ff0c18 663 *
mbed_official 324:406fd2029f23 664 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 665 * @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t
mbed_official 146:f64d43ff0c18 666 * @return Configuration of interrupt request: enable (true) or disable (false).
mbed_official 146:f64d43ff0c18 667 */
mbed_official 324:406fd2029f23 668 static inline bool DSPI_HAL_GetIntMode(uint32_t baseAddr,
mbed_official 146:f64d43ff0c18 669 dspi_status_and_interrupt_request_t interruptSrc)
mbed_official 146:f64d43ff0c18 670 {
mbed_official 324:406fd2029f23 671 return ((HW_SPI_RSER_RD(baseAddr) >> interruptSrc) & 0x1);
mbed_official 146:f64d43ff0c18 672 }
mbed_official 146:f64d43ff0c18 673
mbed_official 146:f64d43ff0c18 674 /*@}*/
mbed_official 146:f64d43ff0c18 675
mbed_official 146:f64d43ff0c18 676 /*!
mbed_official 146:f64d43ff0c18 677 * @name Status
mbed_official 146:f64d43ff0c18 678 * @{
mbed_official 146:f64d43ff0c18 679 */
mbed_official 146:f64d43ff0c18 680
mbed_official 146:f64d43ff0c18 681 /*!
mbed_official 146:f64d43ff0c18 682 * @brief Gets the DSPI status flag state.
mbed_official 146:f64d43ff0c18 683 *
mbed_official 324:406fd2029f23 684 * The status flag is defined in the same enumeration as the interrupt source enable because the bit
mbed_official 146:f64d43ff0c18 685 * position of the interrupt source and corresponding status flag are the same in the RSER and
mbed_official 146:f64d43ff0c18 686 * SR registers. The function uses these bit positions in its algorithm to obtain the desired
mbed_official 146:f64d43ff0c18 687 * flag state, similar to the dspi_get_interrupt_config function.
mbed_official 324:406fd2029f23 688 @code
mbed_official 324:406fd2029f23 689 getStatus = DSPI_HAL_GetStatusFlag(baseAddr, kDspiTxComplete);
mbed_official 324:406fd2029f23 690 @endcode
mbed_official 146:f64d43ff0c18 691 *
mbed_official 324:406fd2029f23 692 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 693 * @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t
mbed_official 146:f64d43ff0c18 694 * @return State of the status flag: asserted (true) or not-asserted (false)
mbed_official 146:f64d43ff0c18 695 */
mbed_official 324:406fd2029f23 696 static inline bool DSPI_HAL_GetStatusFlag(uint32_t baseAddr,
mbed_official 146:f64d43ff0c18 697 dspi_status_and_interrupt_request_t statusFlag)
mbed_official 146:f64d43ff0c18 698 {
mbed_official 324:406fd2029f23 699 return ((HW_SPI_SR_RD(baseAddr) >> statusFlag) & 0x1);
mbed_official 146:f64d43ff0c18 700 }
mbed_official 146:f64d43ff0c18 701
mbed_official 146:f64d43ff0c18 702 /*!
mbed_official 146:f64d43ff0c18 703 * @brief Clears the DSPI status flag.
mbed_official 146:f64d43ff0c18 704 *
mbed_official 146:f64d43ff0c18 705 * This function clears the desired status bit by using a write-1-to-clear. The user passes in
mbed_official 324:406fd2029f23 706 * the baseAddr and the desired status bit to clear. The list of status bits is defined in the
mbed_official 146:f64d43ff0c18 707 * dspi_status_and_interrupt_request_t. The function uses these bit positions in its algorithm
mbed_official 324:406fd2029f23 708 * to clear the desired flag state. Example usage:
mbed_official 324:406fd2029f23 709 @code
mbed_official 324:406fd2029f23 710 DSPI_HAL_ClearStatusFlag(baseAddr, kDspiTxComplete);
mbed_official 324:406fd2029f23 711 @endcode
mbed_official 146:f64d43ff0c18 712 *
mbed_official 324:406fd2029f23 713 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 714 * @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t
mbed_official 146:f64d43ff0c18 715 */
mbed_official 324:406fd2029f23 716 static inline void DSPI_HAL_ClearStatusFlag(uint32_t baseAddr,
mbed_official 146:f64d43ff0c18 717 dspi_status_and_interrupt_request_t statusFlag)
mbed_official 146:f64d43ff0c18 718 {
mbed_official 324:406fd2029f23 719 HW_SPI_SR_SET(baseAddr, (0x1U << statusFlag));
mbed_official 146:f64d43ff0c18 720 }
mbed_official 146:f64d43ff0c18 721
mbed_official 146:f64d43ff0c18 722
mbed_official 146:f64d43ff0c18 723 /*!
mbed_official 146:f64d43ff0c18 724 * @brief Gets the DSPI FIFO counter or pointer.
mbed_official 146:f64d43ff0c18 725 *
mbed_official 146:f64d43ff0c18 726 * This function returns the number of entries or the next pointer in the Tx or Rx FIFO.
mbed_official 324:406fd2029f23 727 * The parameters to pass in are the baseAddr and either the Tx or Rx FIFO counter or a
mbed_official 324:406fd2029f23 728 * pointer. The latter is an enumeration type defined as the bitmask of
mbed_official 324:406fd2029f23 729 * those particular bit fields found in the device header file. Example usage:
mbed_official 324:406fd2029f23 730 @code
mbed_official 324:406fd2029f23 731 DSPI_HAL_GetFifoCountOrPtr(baseAddr, kDspiRxFifoCounter);
mbed_official 324:406fd2029f23 732 @endcode
mbed_official 146:f64d43ff0c18 733 *
mbed_official 324:406fd2029f23 734 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 735 * @param desiredParameter Desired parameter to obtain, of type dspi_fifo_counter_pointer_t
mbed_official 146:f64d43ff0c18 736 */
mbed_official 324:406fd2029f23 737 static inline uint32_t DSPI_HAL_GetFifoCountOrPtr(uint32_t baseAddr,
mbed_official 146:f64d43ff0c18 738 dspi_fifo_counter_pointer_t desiredParameter)
mbed_official 146:f64d43ff0c18 739 {
mbed_official 324:406fd2029f23 740 return ((HW_SPI_SR_RD(baseAddr) >> desiredParameter) & 0xFU);
mbed_official 146:f64d43ff0c18 741 }
mbed_official 146:f64d43ff0c18 742
mbed_official 146:f64d43ff0c18 743
mbed_official 146:f64d43ff0c18 744 /*@}*/
mbed_official 146:f64d43ff0c18 745
mbed_official 146:f64d43ff0c18 746 /*!
mbed_official 146:f64d43ff0c18 747 * @name Data transfer
mbed_official 146:f64d43ff0c18 748 * @{
mbed_official 146:f64d43ff0c18 749 */
mbed_official 146:f64d43ff0c18 750
mbed_official 146:f64d43ff0c18 751 /*!
mbed_official 146:f64d43ff0c18 752 * @brief Reads data from the data buffer.
mbed_official 146:f64d43ff0c18 753 *
mbed_official 324:406fd2029f23 754 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 755 */
mbed_official 324:406fd2029f23 756 static inline uint32_t DSPI_HAL_ReadData(uint32_t baseAddr)
mbed_official 146:f64d43ff0c18 757 {
mbed_official 324:406fd2029f23 758 return HW_SPI_POPR_RD(baseAddr);
mbed_official 146:f64d43ff0c18 759 }
mbed_official 146:f64d43ff0c18 760
mbed_official 146:f64d43ff0c18 761 /*!
mbed_official 146:f64d43ff0c18 762 * @brief Writes data into the data buffer, slave mode.
mbed_official 146:f64d43ff0c18 763 *
mbed_official 146:f64d43ff0c18 764 * In slave mode, up to 32-bit words may be written.
mbed_official 146:f64d43ff0c18 765 *
mbed_official 324:406fd2029f23 766 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 767 * @param data The data to send
mbed_official 146:f64d43ff0c18 768 */
mbed_official 324:406fd2029f23 769 static inline void DSPI_HAL_WriteDataSlavemode(uint32_t baseAddr, uint32_t data)
mbed_official 146:f64d43ff0c18 770 {
mbed_official 324:406fd2029f23 771 HW_SPI_PUSHR_SLAVE_WR(baseAddr, data);
mbed_official 146:f64d43ff0c18 772 }
mbed_official 146:f64d43ff0c18 773
mbed_official 146:f64d43ff0c18 774 /*!
mbed_official 146:f64d43ff0c18 775 * @brief Writes data into the data buffer, master mode.
mbed_official 146:f64d43ff0c18 776 *
mbed_official 146:f64d43ff0c18 777 * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
mbed_official 146:f64d43ff0c18 778 * provides characteristics of the data such as: optional continuous chip select
mbed_official 146:f64d43ff0c18 779 * operation between transfers, the desired Clock and Transfer Attributes register to use for the
mbed_official 146:f64d43ff0c18 780 * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
mbed_official 146:f64d43ff0c18 781 * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
mbed_official 146:f64d43ff0c18 782 * sending the first frame of a data packet). This is an example:
mbed_official 324:406fd2029f23 783 @code
mbed_official 146:f64d43ff0c18 784 dspi_command_config_t commandConfig;
mbed_official 146:f64d43ff0c18 785 commandConfig.isChipSelectContinuous = true;
mbed_official 146:f64d43ff0c18 786 commandConfig.whichCtar = kDspiCtar0;
mbed_official 146:f64d43ff0c18 787 commandConfig.whichPcs = kDspiPcs1;
mbed_official 146:f64d43ff0c18 788 commandConfig.clearTransferCount = false;
mbed_official 146:f64d43ff0c18 789 commandConfig.isEndOfQueue = false;
mbed_official 324:406fd2029f23 790 DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord);
mbed_official 324:406fd2029f23 791 @endcode
mbed_official 146:f64d43ff0c18 792 *
mbed_official 324:406fd2029f23 793 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 794 * @param command Pointer to command structure
mbed_official 146:f64d43ff0c18 795 * @param data The data word to be sent
mbed_official 146:f64d43ff0c18 796 */
mbed_official 324:406fd2029f23 797 void DSPI_HAL_WriteDataMastermode(uint32_t baseAddr,
mbed_official 324:406fd2029f23 798 dspi_command_config_t * command,
mbed_official 324:406fd2029f23 799 uint16_t data);
mbed_official 324:406fd2029f23 800
mbed_official 324:406fd2029f23 801 /*!
mbed_official 324:406fd2029f23 802 * @brief Writes data into the data buffer, master mode and waits till complete to return.
mbed_official 324:406fd2029f23 803 *
mbed_official 324:406fd2029f23 804 * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
mbed_official 324:406fd2029f23 805 * provides characteristics of the data such as: optional continuous chip select
mbed_official 324:406fd2029f23 806 * operation between transfers, the desired Clock and Transfer Attributes register to use for the
mbed_official 324:406fd2029f23 807 * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
mbed_official 324:406fd2029f23 808 * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
mbed_official 324:406fd2029f23 809 * sending the first frame of a data packet). This is an example:
mbed_official 324:406fd2029f23 810 @code
mbed_official 324:406fd2029f23 811 dspi_command_config_t commandConfig;
mbed_official 324:406fd2029f23 812 commandConfig.isChipSelectContinuous = true;
mbed_official 324:406fd2029f23 813 commandConfig.whichCtar = kDspiCtar0;
mbed_official 324:406fd2029f23 814 commandConfig.whichPcs = kDspiPcs1;
mbed_official 324:406fd2029f23 815 commandConfig.clearTransferCount = false;
mbed_official 324:406fd2029f23 816 commandConfig.isEndOfQueue = false;
mbed_official 324:406fd2029f23 817 DSPI_HAL_WriteDataMastermode(baseAddr, &commandConfig, dataWord);
mbed_official 324:406fd2029f23 818 @endcode
mbed_official 324:406fd2029f23 819 *
mbed_official 324:406fd2029f23 820 * Note that this function does not return until after the transmit is complete. Also note that
mbed_official 324:406fd2029f23 821 * the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0).
mbed_official 324:406fd2029f23 822 * Since the SPI is a synchronous protocol, receive data is available when transmit completes.
mbed_official 324:406fd2029f23 823 *
mbed_official 324:406fd2029f23 824 * @param baseAddr Module base address
mbed_official 324:406fd2029f23 825 * @param command Pointer to command structure
mbed_official 324:406fd2029f23 826 * @param data The data word to be sent
mbed_official 324:406fd2029f23 827 */
mbed_official 324:406fd2029f23 828 void DSPI_HAL_WriteDataMastermodeBlocking(uint32_t baseAddr,
mbed_official 324:406fd2029f23 829 dspi_command_config_t * command,
mbed_official 324:406fd2029f23 830 uint16_t data);
mbed_official 146:f64d43ff0c18 831
mbed_official 146:f64d43ff0c18 832 /*!
mbed_official 146:f64d43ff0c18 833 * @brief Gets the transfer count.
mbed_official 146:f64d43ff0c18 834 *
mbed_official 146:f64d43ff0c18 835 * This function returns the current value of the DSPI Transfer Count Register.
mbed_official 146:f64d43ff0c18 836 *
mbed_official 324:406fd2029f23 837 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 838 * @return The current transfer count
mbed_official 146:f64d43ff0c18 839 */
mbed_official 324:406fd2029f23 840 static inline uint32_t DSPI_HAL_GetTransferCount(uint32_t baseAddr)
mbed_official 146:f64d43ff0c18 841 {
mbed_official 324:406fd2029f23 842 return BR_SPI_TCR_SPI_TCNT(baseAddr);
mbed_official 146:f64d43ff0c18 843 }
mbed_official 146:f64d43ff0c18 844
mbed_official 146:f64d43ff0c18 845 /*!
mbed_official 146:f64d43ff0c18 846 * @brief Pre-sets the transfer count.
mbed_official 146:f64d43ff0c18 847 *
mbed_official 146:f64d43ff0c18 848 * This function allows the caller to pre-set the DSI Transfer Count Register to a desired value up
mbed_official 146:f64d43ff0c18 849 * to 65535; Incrementing past this resets the counter back to 0.
mbed_official 146:f64d43ff0c18 850 *
mbed_official 324:406fd2029f23 851 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 852 * @param presetValue The desired pre-set value for the transfer counter
mbed_official 146:f64d43ff0c18 853 */
mbed_official 324:406fd2029f23 854 static inline void DSPI_HAL_PresetTransferCount(uint32_t baseAddr, uint16_t presetValue)
mbed_official 146:f64d43ff0c18 855 {
mbed_official 324:406fd2029f23 856 BW_SPI_TCR_SPI_TCNT(baseAddr, presetValue);
mbed_official 146:f64d43ff0c18 857 }
mbed_official 146:f64d43ff0c18 858
mbed_official 146:f64d43ff0c18 859 /*@}*/
mbed_official 146:f64d43ff0c18 860
mbed_official 146:f64d43ff0c18 861 /*!
mbed_official 146:f64d43ff0c18 862 * @name Debug
mbed_official 146:f64d43ff0c18 863 * @{
mbed_official 146:f64d43ff0c18 864 */
mbed_official 146:f64d43ff0c18 865
mbed_official 146:f64d43ff0c18 866 /*!
mbed_official 324:406fd2029f23 867 * @brief Reads FIFO registers for debug purposes.
mbed_official 146:f64d43ff0c18 868 *
mbed_official 324:406fd2029f23 869 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 870 * @param whichFifo Selects Tx or Rx FIFO, of type dspi_fifo_t.
mbed_official 146:f64d43ff0c18 871 * @param whichFifoEntry Selects which FIFO entry to read: 0, 1, 2, or 3.
mbed_official 324:406fd2029f23 872 * @return The desired FIFO register contents
mbed_official 146:f64d43ff0c18 873 */
mbed_official 324:406fd2029f23 874 uint32_t DSPI_HAL_GetFifoData(uint32_t baseAddr, dspi_fifo_t whichFifo, uint32_t whichFifoEntry);
mbed_official 146:f64d43ff0c18 875
mbed_official 146:f64d43ff0c18 876 /*!
mbed_official 146:f64d43ff0c18 877 * @brief Configures the DSPI to halt during debug mode.
mbed_official 146:f64d43ff0c18 878 *
mbed_official 324:406fd2029f23 879 * @param baseAddr Module base address
mbed_official 146:f64d43ff0c18 880 * @param enable Enables (true) debug mode to halt transfers, else disable to not halt transfer
mbed_official 146:f64d43ff0c18 881 * in debug mode.
mbed_official 146:f64d43ff0c18 882 */
mbed_official 324:406fd2029f23 883 static inline void DSPI_HAL_SetHaltInDebugmodeCmd(uint32_t baseAddr, bool enable)
mbed_official 146:f64d43ff0c18 884 {
mbed_official 324:406fd2029f23 885 BW_SPI_MCR_FRZ(baseAddr, (enable == true));
mbed_official 146:f64d43ff0c18 886 }
mbed_official 146:f64d43ff0c18 887
mbed_official 146:f64d43ff0c18 888 /* @}*/
mbed_official 146:f64d43ff0c18 889
mbed_official 146:f64d43ff0c18 890 #if defined(__cplusplus)
mbed_official 146:f64d43ff0c18 891 }
mbed_official 146:f64d43ff0c18 892 #endif
mbed_official 146:f64d43ff0c18 893
mbed_official 146:f64d43ff0c18 894 /*! @}*/
mbed_official 146:f64d43ff0c18 895
mbed_official 146:f64d43ff0c18 896 #endif /* __FSL_DSPI_HAL_H__*/
mbed_official 146:f64d43ff0c18 897 /*******************************************************************************
mbed_official 146:f64d43ff0c18 898 * EOF
mbed_official 146:f64d43ff0c18 899 ******************************************************************************/
mbed_official 146:f64d43ff0c18 900