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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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If you are looking for a stable and tested release, please import one of the official mbed library releases:

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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_features.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Parent:
149:1fb5f62b92bd 
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Version: rev. 1.0, 2014-05-14
mbed_official 324:406fd2029f23 4 ** Build: b140515
mbed_official 324:406fd2029f23 5 **
mbed_official 324:406fd2029f23 6 ** Abstract:
mbed_official 324:406fd2029f23 7 ** Chip specific module features.
mbed_official 324:406fd2029f23 8 **
mbed_official 324:406fd2029f23 9 ** Copyright: 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 10 ** All rights reserved.
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 13 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 16 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 19 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 20 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 21 **
mbed_official 324:406fd2029f23 22 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 23 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 24 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 25 **
mbed_official 324:406fd2029f23 26 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 27 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 28 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 29 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 30 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 31 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 32 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 33 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 34 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 35 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 36 **
mbed_official 324:406fd2029f23 37 ** http: www.freescale.com
mbed_official 324:406fd2029f23 38 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 39 **
mbed_official 324:406fd2029f23 40 ** Revisions:
mbed_official 324:406fd2029f23 41 ** - rev. 1.0 (2014-05-14)
mbed_official 324:406fd2029f23 42 ** Customer release.
mbed_official 324:406fd2029f23 43 **
mbed_official 324:406fd2029f23 44 ** ###################################################################
mbed_official 324:406fd2029f23 45 */
mbed_official 324:406fd2029f23 46
mbed_official 146:f64d43ff0c18 47 #if !defined(__FSL_DSPI_FEATURES_H__)
mbed_official 146:f64d43ff0c18 48 #define __FSL_DSPI_FEATURES_H__
mbed_official 146:f64d43ff0c18 49
mbed_official 324:406fd2029f23 50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \
mbed_official 324:406fd2029f23 51 defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
mbed_official 324:406fd2029f23 52 defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10)
mbed_official 324:406fd2029f23 53 /* @brief Receive/transmit FIFO size in number of items. */
mbed_official 324:406fd2029f23 54 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
mbed_official 324:406fd2029f23 55 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 56 ((x) == 0 ? (4) : (-1))
mbed_official 324:406fd2029f23 57 /* @brief Maximum transfer data width in bits. */
mbed_official 324:406fd2029f23 58 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
mbed_official 324:406fd2029f23 59 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
mbed_official 324:406fd2029f23 60 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official 324:406fd2029f23 61 /* @brief Number of chip select pins. */
mbed_official 324:406fd2029f23 62 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (4)
mbed_official 324:406fd2029f23 63 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
mbed_official 324:406fd2029f23 64 ((x) == 0 ? (4) : (-1))
mbed_official 324:406fd2029f23 65 /* @brief Has chip select strobe capability on the PCS5 pin. */
mbed_official 324:406fd2029f23 66 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official 324:406fd2029f23 67 /* @brief Has 16-bit data transfer support. */
mbed_official 324:406fd2029f23 68 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
mbed_official 324:406fd2029f23 69 #elif defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || \
mbed_official 324:406fd2029f23 70 defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
mbed_official 324:406fd2029f23 71 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
mbed_official 324:406fd2029f23 72 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
mbed_official 324:406fd2029f23 73 defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \
mbed_official 324:406fd2029f23 74 defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \
mbed_official 324:406fd2029f23 75 defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \
mbed_official 324:406fd2029f23 76 defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10)
mbed_official 324:406fd2029f23 77 /* @brief Receive/transmit FIFO size in number of items. */
mbed_official 324:406fd2029f23 78 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
mbed_official 324:406fd2029f23 79 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 80 ((x) == 0 ? (4) : (-1))
mbed_official 324:406fd2029f23 81 /* @brief Maximum transfer data width in bits. */
mbed_official 324:406fd2029f23 82 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
mbed_official 324:406fd2029f23 83 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
mbed_official 324:406fd2029f23 84 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official 324:406fd2029f23 85 /* @brief Number of chip select pins. */
mbed_official 324:406fd2029f23 86 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5)
mbed_official 324:406fd2029f23 87 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
mbed_official 324:406fd2029f23 88 ((x) == 0 ? (5) : (-1))
mbed_official 324:406fd2029f23 89 /* @brief Has chip select strobe capability on the PCS5 pin. */
mbed_official 324:406fd2029f23 90 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official 324:406fd2029f23 91 /* @brief Has 16-bit data transfer support. */
mbed_official 324:406fd2029f23 92 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
mbed_official 324:406fd2029f23 93 #elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLL12) || \
mbed_official 324:406fd2029f23 94 defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLL12) || \
mbed_official 324:406fd2029f23 95 defined(CPU_MKV31F512VLL12)
mbed_official 324:406fd2029f23 96 /* @brief Receive/transmit FIFO size in number of items. */
mbed_official 324:406fd2029f23 97 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
mbed_official 324:406fd2029f23 98 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 99 ((x) == 0 ? (4) : \
mbed_official 324:406fd2029f23 100 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 101 /* @brief Maximum transfer data width in bits. */
mbed_official 324:406fd2029f23 102 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
mbed_official 324:406fd2029f23 103 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
mbed_official 324:406fd2029f23 104 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official 324:406fd2029f23 105 /* @brief Number of chip select pins. */
mbed_official 324:406fd2029f23 106 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
mbed_official 324:406fd2029f23 107 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
mbed_official 324:406fd2029f23 108 ((x) == 0 ? (6) : \
mbed_official 324:406fd2029f23 109 ((x) == 1 ? (4) : (-1)))
mbed_official 324:406fd2029f23 110 /* @brief Has chip select strobe capability on the PCS5 pin. */
mbed_official 324:406fd2029f23 111 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official 324:406fd2029f23 112 /* @brief Has 16-bit data transfer support. */
mbed_official 324:406fd2029f23 113 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
mbed_official 324:406fd2029f23 114 #elif defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VMP12) || \
mbed_official 324:406fd2029f23 115 defined(CPU_MK22FN512VLH12) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F512VLH12)
mbed_official 324:406fd2029f23 116 /* @brief Receive/transmit FIFO size in number of items. */
mbed_official 324:406fd2029f23 117 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
mbed_official 324:406fd2029f23 118 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 119 ((x) == 0 ? (4) : \
mbed_official 324:406fd2029f23 120 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 121 /* @brief Maximum transfer data width in bits. */
mbed_official 324:406fd2029f23 122 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
mbed_official 324:406fd2029f23 123 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
mbed_official 324:406fd2029f23 124 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official 324:406fd2029f23 125 /* @brief Number of chip select pins. */
mbed_official 324:406fd2029f23 126 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5)
mbed_official 324:406fd2029f23 127 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
mbed_official 146:f64d43ff0c18 128 ((x) == 0 ? (5) : \
mbed_official 324:406fd2029f23 129 ((x) == 1 ? (2) : (-1)))
mbed_official 324:406fd2029f23 130 /* @brief Has chip select strobe capability on the PCS5 pin. */
mbed_official 324:406fd2029f23 131 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official 324:406fd2029f23 132 /* @brief Has 16-bit data transfer support. */
mbed_official 324:406fd2029f23 133 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
mbed_official 324:406fd2029f23 134 #elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \
mbed_official 324:406fd2029f23 135 defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLQ12) || \
mbed_official 324:406fd2029f23 136 defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \
mbed_official 324:406fd2029f23 137 defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \
mbed_official 324:406fd2029f23 138 defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
mbed_official 324:406fd2029f23 139 /* @brief Receive/transmit FIFO size in number of items. */
mbed_official 324:406fd2029f23 140 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
mbed_official 324:406fd2029f23 141 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
mbed_official 146:f64d43ff0c18 142 ((x) == 0 ? (4) : \
mbed_official 146:f64d43ff0c18 143 ((x) == 1 ? (1) : \
mbed_official 146:f64d43ff0c18 144 ((x) == 2 ? (1) : (-1))))
mbed_official 324:406fd2029f23 145 /* @brief Maximum transfer data width in bits. */
mbed_official 324:406fd2029f23 146 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
mbed_official 324:406fd2029f23 147 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
mbed_official 324:406fd2029f23 148 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official 324:406fd2029f23 149 /* @brief Number of chip select pins. */
mbed_official 324:406fd2029f23 150 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
mbed_official 324:406fd2029f23 151 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
mbed_official 324:406fd2029f23 152 ((x) == 0 ? (6) : \
mbed_official 146:f64d43ff0c18 153 ((x) == 1 ? (4) : \
mbed_official 324:406fd2029f23 154 ((x) == 2 ? (2) : (-1))))
mbed_official 324:406fd2029f23 155 /* @brief Has chip select strobe capability on the PCS5 pin. */
mbed_official 324:406fd2029f23 156 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official 324:406fd2029f23 157 /* @brief Has 16-bit data transfer support. */
mbed_official 324:406fd2029f23 158 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
mbed_official 324:406fd2029f23 159 #elif defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12)
mbed_official 324:406fd2029f23 160 /* @brief Receive/transmit FIFO size in number of items. */
mbed_official 324:406fd2029f23 161 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
mbed_official 324:406fd2029f23 162 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 163 ((x) == 0 ? (4) : \
mbed_official 324:406fd2029f23 164 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 165 ((x) == 2 ? (1) : (-1))))
mbed_official 324:406fd2029f23 166 /* @brief Maximum transfer data width in bits. */
mbed_official 324:406fd2029f23 167 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
mbed_official 324:406fd2029f23 168 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
mbed_official 324:406fd2029f23 169 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official 324:406fd2029f23 170 /* @brief Number of chip select pins. */
mbed_official 324:406fd2029f23 171 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
mbed_official 324:406fd2029f23 172 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
mbed_official 146:f64d43ff0c18 173 ((x) == 0 ? (6) : \
mbed_official 146:f64d43ff0c18 174 ((x) == 1 ? (4) : \
mbed_official 146:f64d43ff0c18 175 ((x) == 2 ? (1) : (-1))))
mbed_official 324:406fd2029f23 176 /* @brief Has chip select strobe capability on the PCS5 pin. */
mbed_official 324:406fd2029f23 177 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official 324:406fd2029f23 178 /* @brief Has 16-bit data transfer support. */
mbed_official 324:406fd2029f23 179 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
mbed_official 324:406fd2029f23 180 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
mbed_official 324:406fd2029f23 181 defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
mbed_official 324:406fd2029f23 182 /* @brief Receive/transmit FIFO size in number of items. */
mbed_official 324:406fd2029f23 183 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
mbed_official 324:406fd2029f23 184 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
mbed_official 146:f64d43ff0c18 185 ((x) == 0 ? (4) : \
mbed_official 324:406fd2029f23 186 ((x) == 1 ? (4) : \
mbed_official 324:406fd2029f23 187 ((x) == 2 ? (4) : (-1))))
mbed_official 324:406fd2029f23 188 /* @brief Maximum transfer data width in bits. */
mbed_official 324:406fd2029f23 189 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
mbed_official 324:406fd2029f23 190 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
mbed_official 324:406fd2029f23 191 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official 324:406fd2029f23 192 /* @brief Number of chip select pins. */
mbed_official 324:406fd2029f23 193 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
mbed_official 324:406fd2029f23 194 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
mbed_official 324:406fd2029f23 195 ((x) == 0 ? (6) : \
mbed_official 324:406fd2029f23 196 ((x) == 1 ? (4) : \
mbed_official 324:406fd2029f23 197 ((x) == 2 ? (2) : (-1))))
mbed_official 324:406fd2029f23 198 /* @brief Has chip select strobe capability on the PCS5 pin. */
mbed_official 324:406fd2029f23 199 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official 324:406fd2029f23 200 /* @brief Has 16-bit data transfer support. */
mbed_official 324:406fd2029f23 201 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
mbed_official 324:406fd2029f23 202 #elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || \
mbed_official 324:406fd2029f23 203 defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \
mbed_official 324:406fd2029f23 204 defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15)
mbed_official 324:406fd2029f23 205 /* @brief Receive/transmit FIFO size in number of items. */
mbed_official 324:406fd2029f23 206 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
mbed_official 324:406fd2029f23 207 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 208 ((x) == 0 ? (4) : (-1))
mbed_official 324:406fd2029f23 209 /* @brief Maximum transfer data width in bits. */
mbed_official 324:406fd2029f23 210 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
mbed_official 324:406fd2029f23 211 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
mbed_official 324:406fd2029f23 212 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official 324:406fd2029f23 213 /* @brief Number of chip select pins. */
mbed_official 324:406fd2029f23 214 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5)
mbed_official 324:406fd2029f23 215 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
mbed_official 324:406fd2029f23 216 ((x) == 0 ? (5) : (-1))
mbed_official 324:406fd2029f23 217 /* @brief Has chip select strobe capability on the PCS5 pin. */
mbed_official 324:406fd2029f23 218 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official 324:406fd2029f23 219 /* @brief Has 16-bit data transfer support. */
mbed_official 324:406fd2029f23 220 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
mbed_official 324:406fd2029f23 221 #elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV44F128VLL15) || \
mbed_official 324:406fd2029f23 222 defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15)
mbed_official 324:406fd2029f23 223 /* @brief Receive/transmit FIFO size in number of items. */
mbed_official 324:406fd2029f23 224 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
mbed_official 324:406fd2029f23 225 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 226 ((x) == 0 ? (4) : (-1))
mbed_official 324:406fd2029f23 227 /* @brief Maximum transfer data width in bits. */
mbed_official 324:406fd2029f23 228 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
mbed_official 324:406fd2029f23 229 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
mbed_official 324:406fd2029f23 230 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official 324:406fd2029f23 231 /* @brief Number of chip select pins. */
mbed_official 324:406fd2029f23 232 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
mbed_official 324:406fd2029f23 233 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
mbed_official 324:406fd2029f23 234 ((x) == 0 ? (6) : (-1))
mbed_official 324:406fd2029f23 235 /* @brief Has chip select strobe capability on the PCS5 pin. */
mbed_official 324:406fd2029f23 236 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official 324:406fd2029f23 237 /* @brief Has 16-bit data transfer support. */
mbed_official 324:406fd2029f23 238 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
mbed_official 146:f64d43ff0c18 239 #else
mbed_official 146:f64d43ff0c18 240 #error "No valid CPU defined!"
mbed_official 146:f64d43ff0c18 241 #endif
mbed_official 146:f64d43ff0c18 242
mbed_official 324:406fd2029f23 243 #endif /* __FSL_DSPI_FEATURES_H__ */
mbed_official 324:406fd2029f23 244
mbed_official 146:f64d43ff0c18 245 /*******************************************************************************
mbed_official 146:f64d43ff0c18 246 * EOF
mbed_official 146:f64d43ff0c18 247 ******************************************************************************/