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mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_features.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:
mbed_official
Date:
Thu Apr 03 11:45:06 2014 +0100
Revision:
149:1fb5f62b92bd
Parent:
targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_KSDK_CODE/hal/dspi/fsl_dspi_features.h@146:f64d43ff0c18
Child:
324:406fd2029f23
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 146:f64d43ff0c18 6 * are permitted provided that the following conditions are met:
mbed_official 146:f64d43ff0c18 7 *
mbed_official 146:f64d43ff0c18 8 * o Redistributions of source code must retain the above copyright notice, this list
mbed_official 146:f64d43ff0c18 9 * of conditions and the following disclaimer.
mbed_official 146:f64d43ff0c18 10 *
mbed_official 146:f64d43ff0c18 11 * o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 146:f64d43ff0c18 12 * list of conditions and the following disclaimer in the documentation and/or
mbed_official 146:f64d43ff0c18 13 * other materials provided with the distribution.
mbed_official 146:f64d43ff0c18 14 *
mbed_official 146:f64d43ff0c18 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 146:f64d43ff0c18 16 * contributors may be used to endorse or promote products derived from this
mbed_official 146:f64d43ff0c18 17 * software without specific prior written permission.
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 146:f64d43ff0c18 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 146:f64d43ff0c18 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 146:f64d43ff0c18 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 146:f64d43ff0c18 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 146:f64d43ff0c18 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 146:f64d43ff0c18 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 146:f64d43ff0c18 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 146:f64d43ff0c18 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 146:f64d43ff0c18 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 29 */
mbed_official 146:f64d43ff0c18 30 #if !defined(__FSL_DSPI_FEATURES_H__)
mbed_official 146:f64d43ff0c18 31 #define __FSL_DSPI_FEATURES_H__
mbed_official 146:f64d43ff0c18 32
mbed_official 146:f64d43ff0c18 33 #if defined(CPU_MK10DN512VLK10) || defined(CPU_MK10DN512VMB10) || defined(CPU_MK10DX128VMP5) || defined(CPU_MK10DN128VMP5) || \
mbed_official 146:f64d43ff0c18 34 defined(CPU_MK10DX64VMP5) || defined(CPU_MK10DN64VMP5) || defined(CPU_MK10DX32VMP5) || defined(CPU_MK10DN32VMP5) || \
mbed_official 146:f64d43ff0c18 35 defined(CPU_MK10DX128VLH5) || defined(CPU_MK10DN128VLH5) || defined(CPU_MK10DX64VLH5) || defined(CPU_MK10DN64VLH5) || \
mbed_official 146:f64d43ff0c18 36 defined(CPU_MK10DX32VLH5) || defined(CPU_MK10DN32VLH5) || defined(CPU_MK10DX128VFT5) || defined(CPU_MK10DN128VFT5) || \
mbed_official 146:f64d43ff0c18 37 defined(CPU_MK10DX64VFT5) || defined(CPU_MK10DN64VFT5) || defined(CPU_MK10DX32VFT5) || defined(CPU_MK10DN32VFT5) || \
mbed_official 146:f64d43ff0c18 38 defined(CPU_MK10DX128VLF5) || defined(CPU_MK10DN128VLF5) || defined(CPU_MK10DX64VLF5) || defined(CPU_MK10DN64VLF5) || \
mbed_official 146:f64d43ff0c18 39 defined(CPU_MK10DX32VLF5) || defined(CPU_MK10DN32VLF5) || defined(CPU_MK10DX64VLH7) || defined(CPU_MK10DX128VLH7) || \
mbed_official 146:f64d43ff0c18 40 defined(CPU_MK10DX256VLH7) || defined(CPU_MK10DX64VLK7) || defined(CPU_MK10DX128VLK7) || defined(CPU_MK10DX256VLK7) || \
mbed_official 146:f64d43ff0c18 41 defined(CPU_MK10DX64VMB7) || defined(CPU_MK10DX128VMB7) || defined(CPU_MK10DX256VMB7) || defined(CPU_MK10DN512ZVLK10) || \
mbed_official 146:f64d43ff0c18 42 defined(CPU_MK10DN512ZVMB10) || defined(CPU_MK20DN512VLK10) || defined(CPU_MK20DN512VMB10) || defined(CPU_MK20DX128VMP5) || \
mbed_official 146:f64d43ff0c18 43 defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || \
mbed_official 146:f64d43ff0c18 44 defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \
mbed_official 146:f64d43ff0c18 45 defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFT5) || \
mbed_official 146:f64d43ff0c18 46 defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || \
mbed_official 146:f64d43ff0c18 47 defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \
mbed_official 146:f64d43ff0c18 48 defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK20DX64VLH7) || \
mbed_official 146:f64d43ff0c18 49 defined(CPU_MK20DX128VLH7) || defined(CPU_MK20DX256VLH7) || defined(CPU_MK20DX64VLK7) || defined(CPU_MK20DX128VLK7) || \
mbed_official 146:f64d43ff0c18 50 defined(CPU_MK20DX256VLK7) || defined(CPU_MK20DX64VMB7) || defined(CPU_MK20DX128VMB7) || defined(CPU_MK20DX256VMB7) || \
mbed_official 146:f64d43ff0c18 51 defined(CPU_MK20DN512ZVLK10) || defined(CPU_MK20DX256ZVLK10) || defined(CPU_MK20DN512ZVMB10) || defined(CPU_MK20DX256ZVMB10) || \
mbed_official 146:f64d43ff0c18 52 defined(CPU_MK22FX512VLH12) || defined(CPU_MK22FN1M0VLH12) || defined(CPU_MK22FX512VLK12) || defined(CPU_MK22FN1M0VLK12) || \
mbed_official 146:f64d43ff0c18 53 defined(CPU_MK30DN512VLK10) || defined(CPU_MK30DN512VMB10) || defined(CPU_MK30DX64VLH7) || defined(CPU_MK30DX128VLH7) || \
mbed_official 146:f64d43ff0c18 54 defined(CPU_MK30DX256VLH7) || defined(CPU_MK30DX64VLK7) || defined(CPU_MK30DX128VLK7) || defined(CPU_MK30DX256VLK7) || \
mbed_official 146:f64d43ff0c18 55 defined(CPU_MK30DX64VMB7) || defined(CPU_MK30DX128VMB7) || defined(CPU_MK30DX256VMB7) || defined(CPU_MK30DN512ZVLK10) || \
mbed_official 146:f64d43ff0c18 56 defined(CPU_MK30DN512ZVMB10) || defined(CPU_MK40DN512VLK10) || defined(CPU_MK40DN512VMB10) || defined(CPU_MK40DX64VLH7) || \
mbed_official 146:f64d43ff0c18 57 defined(CPU_MK40DX128VLH7) || defined(CPU_MK40DX256VLH7) || defined(CPU_MK40DX64VLK7) || defined(CPU_MK40DX128VLK7) || \
mbed_official 146:f64d43ff0c18 58 defined(CPU_MK40DX256VLK7) || defined(CPU_MK40DX64VMB7) || defined(CPU_MK40DX128VMB7) || defined(CPU_MK40DX256VMB7) || \
mbed_official 146:f64d43ff0c18 59 defined(CPU_MK40DN512ZVLK10) || defined(CPU_MK40DN512ZVMB10) || defined(CPU_MK50DX128CLH7) || defined(CPU_MK50DX256CLK10) || \
mbed_official 146:f64d43ff0c18 60 defined(CPU_MK50DX128CLK7) || defined(CPU_MK50DX256CLK7) || defined(CPU_MK50DX256CMB10) || defined(CPU_MK50DX128CMB7) || \
mbed_official 146:f64d43ff0c18 61 defined(CPU_MK50DX256CMB7) || defined(CPU_MK50DX256ZCLK10) || defined(CPU_MK50DX256ZCMB10) || defined(CPU_MK51DX128CLH7) || \
mbed_official 146:f64d43ff0c18 62 defined(CPU_MK51DX256CLK10) || defined(CPU_MK51DX128CLK7) || defined(CPU_MK51DX256CLK7) || defined(CPU_MK51DX256CMB10) || \
mbed_official 146:f64d43ff0c18 63 defined(CPU_MK51DX128CMB7) || defined(CPU_MK51DX256CMB7) || defined(CPU_MK51DX256ZCLK10) || defined(CPU_MK51DX256ZCMB10)
mbed_official 146:f64d43ff0c18 64 /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
mbed_official 146:f64d43ff0c18 65 #define FSL_FEATURE_SPI_IS_DSPI (1)
mbed_official 146:f64d43ff0c18 66 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 67 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
mbed_official 146:f64d43ff0c18 68 /* @brief Receive/transmit FIFO size in number of items.*/
mbed_official 146:f64d43ff0c18 69 #define FSL_FEATURE_SPI_FIFO_SIZE (4)
mbed_official 146:f64d43ff0c18 70 /* @brief Maximum transfer data width in bits.*/
mbed_official 146:f64d43ff0c18 71 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
mbed_official 146:f64d43ff0c18 72 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
mbed_official 146:f64d43ff0c18 73 #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official 146:f64d43ff0c18 74 /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 75 #define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \
mbed_official 146:f64d43ff0c18 76 ((x) == 0 ? (5) : \
mbed_official 146:f64d43ff0c18 77 ((x) == 1 ? (3) : (-1)))
mbed_official 146:f64d43ff0c18 78 /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 79 #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official 146:f64d43ff0c18 80 /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 81 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
mbed_official 146:f64d43ff0c18 82 /* @brief Has 16-bit data transfer support.*/
mbed_official 146:f64d43ff0c18 83 #define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
mbed_official 146:f64d43ff0c18 84 #elif defined(CPU_MK10DN512VLL10) || defined(CPU_MK10DX128VLQ10) || defined(CPU_MK10DX256VLQ10) || defined(CPU_MK10DN512VLQ10) || \
mbed_official 146:f64d43ff0c18 85 defined(CPU_MK10DN512VMC10) || defined(CPU_MK10DX128VMD10) || defined(CPU_MK10DX256VMD10) || defined(CPU_MK10DN512VMD10) || \
mbed_official 146:f64d43ff0c18 86 defined(CPU_MK10DX128VLL7) || defined(CPU_MK10DX256VLL7) || defined(CPU_MK10DX128VML7) || defined(CPU_MK10DX256VML7) || \
mbed_official 146:f64d43ff0c18 87 defined(CPU_MK10FN1M0VLQ12) || defined(CPU_MK10FX512VLQ12) || defined(CPU_MK10FN1M0VMD12) || defined(CPU_MK10FX512VMD12) || \
mbed_official 146:f64d43ff0c18 88 defined(CPU_MK10DN512ZVLL10) || defined(CPU_MK10DN512ZVLQ10) || defined(CPU_MK10DX256ZVLQ10) || defined(CPU_MK10DX128ZVLQ10) || \
mbed_official 146:f64d43ff0c18 89 defined(CPU_MK10DN512ZVMC10) || defined(CPU_MK10DN512ZVMD10) || defined(CPU_MK10DX256ZVMD10) || defined(CPU_MK10DX128ZVMD10) || \
mbed_official 146:f64d43ff0c18 90 defined(CPU_MK20DN512VLL10) || defined(CPU_MK20DX128VLQ10) || defined(CPU_MK20DX256VLQ10) || defined(CPU_MK20DN512VLQ10) || \
mbed_official 146:f64d43ff0c18 91 defined(CPU_MK20DX256VMC10) || defined(CPU_MK20DN512VMC10) || defined(CPU_MK20DX128VMD10) || defined(CPU_MK20DX256VMD10) || \
mbed_official 146:f64d43ff0c18 92 defined(CPU_MK20DN512VMD10) || defined(CPU_MK20DX128VLL7) || defined(CPU_MK20DX256VLL7) || defined(CPU_MK20DX128VML7) || \
mbed_official 146:f64d43ff0c18 93 defined(CPU_MK20DX256VML7) || defined(CPU_MK20FN1M0VLQ12) || defined(CPU_MK20FX512VLQ12) || defined(CPU_MK20FN1M0VMD12) || \
mbed_official 146:f64d43ff0c18 94 defined(CPU_MK20FX512VMD12) || defined(CPU_MK20DN512ZVLL10) || defined(CPU_MK20DX256ZVLL10) || defined(CPU_MK20DN512ZVLQ10) || \
mbed_official 146:f64d43ff0c18 95 defined(CPU_MK20DX256ZVLQ10) || defined(CPU_MK20DX128ZVLQ10) || defined(CPU_MK20DN512ZVMC10) || defined(CPU_MK20DX256ZVMC10) || \
mbed_official 146:f64d43ff0c18 96 defined(CPU_MK20DN512ZVMD10) || defined(CPU_MK20DX256ZVMD10) || defined(CPU_MK20DX128ZVMD10) || defined(CPU_MK21FX512VLQ12) || \
mbed_official 146:f64d43ff0c18 97 defined(CPU_MK21FN1M0VLQ12) || defined(CPU_MK21FX512VLQ12WS) || defined(CPU_MK21FN1M0VLQ12WS) || defined(CPU_MK21FX512VMC12) || \
mbed_official 146:f64d43ff0c18 98 defined(CPU_MK21FN1M0VMC12) || defined(CPU_MK21FX512VMC12WS) || defined(CPU_MK21FN1M0VMC12WS) || defined(CPU_MK21FX512VMD12) || \
mbed_official 146:f64d43ff0c18 99 defined(CPU_MK21FN1M0VMD12) || defined(CPU_MK21FX512VMD12WS) || defined(CPU_MK21FN1M0VMD12WS) || defined(CPU_MK22FX512VLL12) || \
mbed_official 146:f64d43ff0c18 100 defined(CPU_MK22FN1M0VLL12) || defined(CPU_MK22FX512VLQ12) || defined(CPU_MK22FN1M0VLQ12) || defined(CPU_MK22FX512VMC12) || \
mbed_official 146:f64d43ff0c18 101 defined(CPU_MK22FN1M0VMC12) || defined(CPU_MK22FX512VMD12) || defined(CPU_MK22FN1M0VMD12) || defined(CPU_MK30DN512VLL10) || \
mbed_official 146:f64d43ff0c18 102 defined(CPU_MK30DX128VLQ10) || defined(CPU_MK30DX256VLQ10) || defined(CPU_MK30DN512VLQ10) || defined(CPU_MK30DN512VMC10) || \
mbed_official 146:f64d43ff0c18 103 defined(CPU_MK30DX128VMD10) || defined(CPU_MK30DX256VMD10) || defined(CPU_MK30DN512VMD10) || defined(CPU_MK30DX128VLL7) || \
mbed_official 146:f64d43ff0c18 104 defined(CPU_MK30DX256VLL7) || defined(CPU_MK30DX128VML7) || defined(CPU_MK30DX256VML7) || defined(CPU_MK30DN512ZVLL10) || \
mbed_official 146:f64d43ff0c18 105 defined(CPU_MK30DN512ZVLQ10) || defined(CPU_MK30DX256ZVLQ10) || defined(CPU_MK30DX128ZVLQ10) || defined(CPU_MK30DN512ZVMC10) || \
mbed_official 146:f64d43ff0c18 106 defined(CPU_MK30DN512ZVMD10) || defined(CPU_MK30DX256ZVMD10) || defined(CPU_MK30DX128ZVMD10) || defined(CPU_MK40DN512VLL10) || \
mbed_official 146:f64d43ff0c18 107 defined(CPU_MK40DX128VLQ10) || defined(CPU_MK40DX256VLQ10) || defined(CPU_MK40DN512VLQ10) || defined(CPU_MK40DN512VMC10) || \
mbed_official 146:f64d43ff0c18 108 defined(CPU_MK40DX128VMD10) || defined(CPU_MK40DX256VMD10) || defined(CPU_MK40DN512VMD10) || defined(CPU_MK40DX128VLL7) || \
mbed_official 146:f64d43ff0c18 109 defined(CPU_MK40DX256VLL7) || defined(CPU_MK40DX128VML7) || defined(CPU_MK40DX256VML7) || defined(CPU_MK40DN512ZVLL10) || \
mbed_official 146:f64d43ff0c18 110 defined(CPU_MK40DN512ZVLQ10) || defined(CPU_MK40DX256ZVLQ10) || defined(CPU_MK40DX128ZVLQ10) || defined(CPU_MK40DN512ZVMC10) || \
mbed_official 146:f64d43ff0c18 111 defined(CPU_MK40DN512ZVMD10) || defined(CPU_MK40DX256ZVMD10) || defined(CPU_MK40DX128ZVMD10) || defined(CPU_MK50DX256CLL10) || \
mbed_official 146:f64d43ff0c18 112 defined(CPU_MK50DN512CLL10) || defined(CPU_MK50DN512CLQ10) || defined(CPU_MK50DX256CMC10) || defined(CPU_MK50DN512CMC10) || \
mbed_official 146:f64d43ff0c18 113 defined(CPU_MK50DN512CMD10) || defined(CPU_MK50DX256CMD10) || defined(CPU_MK50DX256CLL7) || defined(CPU_MK50DX256CML7) || \
mbed_official 146:f64d43ff0c18 114 defined(CPU_MK50DN512ZCLL10) || defined(CPU_MK50DX256ZCLL10) || defined(CPU_MK50DN512ZCLQ10) || defined(CPU_MK50DN512ZCMC10) || \
mbed_official 146:f64d43ff0c18 115 defined(CPU_MK50DX256ZCMC10) || defined(CPU_MK50DN512ZCMD10) || defined(CPU_MK51DX256CLL10) || defined(CPU_MK51DN512CLL10) || \
mbed_official 146:f64d43ff0c18 116 defined(CPU_MK51DN256CLQ10) || defined(CPU_MK51DN512CLQ10) || defined(CPU_MK51DX256CMC10) || defined(CPU_MK51DN512CMC10) || \
mbed_official 146:f64d43ff0c18 117 defined(CPU_MK51DN256CMD10) || defined(CPU_MK51DN512CMD10) || defined(CPU_MK51DX256CLL7) || defined(CPU_MK51DX256CML7) || \
mbed_official 146:f64d43ff0c18 118 defined(CPU_MK51DN512ZCLL10) || defined(CPU_MK51DX256ZCLL10) || defined(CPU_MK51DN512ZCLQ10) || defined(CPU_MK51DN256ZCLQ10) || \
mbed_official 146:f64d43ff0c18 119 defined(CPU_MK51DN512ZCMC10) || defined(CPU_MK51DX256ZCMC10) || defined(CPU_MK51DN512ZCMD10) || defined(CPU_MK51DN256ZCMD10) || \
mbed_official 146:f64d43ff0c18 120 defined(CPU_MK52DN512CLQ10) || defined(CPU_MK52DN512CMD10) || defined(CPU_MK52DN512ZCLQ10) || defined(CPU_MK52DN512ZCMD10) || \
mbed_official 146:f64d43ff0c18 121 defined(CPU_MK53DN512CLQ10) || defined(CPU_MK53DX256CLQ10) || defined(CPU_MK53DN512CMD10) || defined(CPU_MK53DX256CMD10) || \
mbed_official 146:f64d43ff0c18 122 defined(CPU_MK53DN512ZCLQ10) || defined(CPU_MK53DX256ZCLQ10) || defined(CPU_MK53DN512ZCMD10) || defined(CPU_MK53DX256ZCMD10) || \
mbed_official 146:f64d43ff0c18 123 defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DX256VLL10) || defined(CPU_MK60DN512VLL10) || defined(CPU_MK60DN256VLQ10) || \
mbed_official 146:f64d43ff0c18 124 defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DN512VLQ10) || defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DX256VMC10) || \
mbed_official 146:f64d43ff0c18 125 defined(CPU_MK60DN512VMC10) || defined(CPU_MK60DN256VMD10) || defined(CPU_MK60DX256VMD10) || defined(CPU_MK60DN512VMD10) || \
mbed_official 146:f64d43ff0c18 126 defined(CPU_MK60FN1M0VLQ12) || defined(CPU_MK60FX512VLQ12) || defined(CPU_MK60FN1M0VLQ15) || defined(CPU_MK60FX512VLQ15) || \
mbed_official 146:f64d43ff0c18 127 defined(CPU_MK60FN1M0VMD12) || defined(CPU_MK60FX512VMD12) || defined(CPU_MK60FN1M0VMD15) || defined(CPU_MK60FX512VMD15) || \
mbed_official 146:f64d43ff0c18 128 defined(CPU_MK60DN512ZVLL10) || defined(CPU_MK60DX256ZVLL10) || defined(CPU_MK60DN256ZVLL10) || defined(CPU_MK60DN512ZVLQ10) || \
mbed_official 146:f64d43ff0c18 129 defined(CPU_MK60DX256ZVLQ10) || defined(CPU_MK60DN256ZVLQ10) || defined(CPU_MK60DN512ZVMC10) || defined(CPU_MK60DX256ZVMC10) || \
mbed_official 146:f64d43ff0c18 130 defined(CPU_MK60DN256ZVMC10) || defined(CPU_MK60DN512ZVMD10) || defined(CPU_MK60DX256ZVMD10) || defined(CPU_MK60DN256ZVMD10) || \
mbed_official 146:f64d43ff0c18 131 defined(CPU_MK61FN1M0VMD12) || defined(CPU_MK61FX512VMD12) || defined(CPU_MK61FN1M0VMD15) || defined(CPU_MK61FX512VMD15) || \
mbed_official 146:f64d43ff0c18 132 defined(CPU_MK61FN1M0VMD12WS) || defined(CPU_MK61FX512VMD12WS) || defined(CPU_MK61FN1M0VMD15WS) || defined(CPU_MK61FX512VMD15WS) || \
mbed_official 146:f64d43ff0c18 133 defined(CPU_MK61FN1M0VMF12) || defined(CPU_MK61FX512VMF12) || defined(CPU_MK61FN1M0VMF15) || defined(CPU_MK61FX512VMF15) || \
mbed_official 146:f64d43ff0c18 134 defined(CPU_MK61FN1M0VMJ12) || defined(CPU_MK61FX512VMJ12) || defined(CPU_MK61FN1M0VMJ15) || defined(CPU_MK61FX512VMJ15) || \
mbed_official 146:f64d43ff0c18 135 defined(CPU_MK61FN1M0VMJ12WS) || defined(CPU_MK61FX512VMJ12WS) || defined(CPU_MK61FN1M0VMJ15WS) || defined(CPU_MK61FX512VMJ15WS) || \
mbed_official 146:f64d43ff0c18 136 defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK63FN1M0VMD12WS) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) || \
mbed_official 146:f64d43ff0c18 137 defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
mbed_official 146:f64d43ff0c18 138 defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) || \
mbed_official 146:f64d43ff0c18 139 defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || defined(CPU_MK70FN1M0VMJ15WS) || defined(CPU_MK70FX512VMJ15WS)
mbed_official 146:f64d43ff0c18 140 /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
mbed_official 146:f64d43ff0c18 141 #define FSL_FEATURE_SPI_IS_DSPI (1)
mbed_official 146:f64d43ff0c18 142 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 143 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
mbed_official 146:f64d43ff0c18 144 /* @brief Receive/transmit FIFO size in number of items.*/
mbed_official 146:f64d43ff0c18 145 #if defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12)
mbed_official 146:f64d43ff0c18 146 #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
mbed_official 146:f64d43ff0c18 147 ((x) == 0 ? (4) : \
mbed_official 146:f64d43ff0c18 148 ((x) == 1 ? (1) : \
mbed_official 146:f64d43ff0c18 149 ((x) == 2 ? (1) : (-1))))
mbed_official 146:f64d43ff0c18 150 #else
mbed_official 146:f64d43ff0c18 151 #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
mbed_official 146:f64d43ff0c18 152 ((x) == 0 ? (4) : \
mbed_official 146:f64d43ff0c18 153 ((x) == 1 ? (4) : \
mbed_official 146:f64d43ff0c18 154 ((x) == 2 ? (4) : (-1))))
mbed_official 146:f64d43ff0c18 155 #endif
mbed_official 146:f64d43ff0c18 156 /* @brief Maximum transfer data width in bits.*/
mbed_official 146:f64d43ff0c18 157 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
mbed_official 146:f64d43ff0c18 158 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
mbed_official 146:f64d43ff0c18 159 #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official 146:f64d43ff0c18 160 /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 161 #define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \
mbed_official 146:f64d43ff0c18 162 ((x) == 0 ? (6) : \
mbed_official 146:f64d43ff0c18 163 ((x) == 1 ? (4) : \
mbed_official 146:f64d43ff0c18 164 ((x) == 2 ? (1) : (-1))))
mbed_official 146:f64d43ff0c18 165 /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 166 #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official 146:f64d43ff0c18 167 /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 168 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
mbed_official 146:f64d43ff0c18 169 /* @brief Has 16-bit data transfer support.*/
mbed_official 146:f64d43ff0c18 170 #define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
mbed_official 146:f64d43ff0c18 171 #elif defined(CPU_MK10DX128VFM5) || defined(CPU_MK10DN128VFM5) || defined(CPU_MK10DX64VFM5) || defined(CPU_MK10DN64VFM5) || \
mbed_official 146:f64d43ff0c18 172 defined(CPU_MK10DX32VFM5) || defined(CPU_MK10DN32VFM5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \
mbed_official 146:f64d43ff0c18 173 defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5)
mbed_official 146:f64d43ff0c18 174 /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
mbed_official 146:f64d43ff0c18 175 #define FSL_FEATURE_SPI_IS_DSPI (1)
mbed_official 146:f64d43ff0c18 176 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 177 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
mbed_official 146:f64d43ff0c18 178 /* @brief Receive/transmit FIFO size in number of items.*/
mbed_official 146:f64d43ff0c18 179 #define FSL_FEATURE_SPI_FIFO_SIZE (4)
mbed_official 146:f64d43ff0c18 180 /* @brief Maximum transfer data width in bits.*/
mbed_official 146:f64d43ff0c18 181 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
mbed_official 146:f64d43ff0c18 182 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
mbed_official 146:f64d43ff0c18 183 #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official 146:f64d43ff0c18 184 /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 185 #define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (4)
mbed_official 146:f64d43ff0c18 186 /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 187 #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official 146:f64d43ff0c18 188 /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 189 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
mbed_official 146:f64d43ff0c18 190 /* @brief Has 16-bit data transfer support.*/
mbed_official 146:f64d43ff0c18 191 #define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
mbed_official 146:f64d43ff0c18 192 #elif defined(CPU_MK11DX128VLK5) || defined(CPU_MK11DX256VLK5) || defined(CPU_MK11DN512VLK5) || defined(CPU_MK11DX128VLK5WS) || \
mbed_official 146:f64d43ff0c18 193 defined(CPU_MK11DX256VLK5WS) || defined(CPU_MK11DN512VLK5WS) || defined(CPU_MK11DX128VMC5) || defined(CPU_MK11DX256VMC5) || \
mbed_official 146:f64d43ff0c18 194 defined(CPU_MK11DN512VMC5) || defined(CPU_MK11DX128VMC5WS) || defined(CPU_MK11DX256VMC5WS) || defined(CPU_MK11DN512VMC5WS) || \
mbed_official 146:f64d43ff0c18 195 defined(CPU_MK12DX128VLH5) || defined(CPU_MK12DX256VLH5) || defined(CPU_MK12DN512VLH5) || defined(CPU_MK12DX128VLK5) || \
mbed_official 146:f64d43ff0c18 196 defined(CPU_MK12DX256VLK5) || defined(CPU_MK12DN512VLK5) || defined(CPU_MK12DX128VMC5) || defined(CPU_MK12DX256VMC5) || \
mbed_official 146:f64d43ff0c18 197 defined(CPU_MK12DN512VMC5) || defined(CPU_MK12DX128VLF5) || defined(CPU_MK12DX256VLF5) || defined(CPU_MK21DX128VLK5) || \
mbed_official 146:f64d43ff0c18 198 defined(CPU_MK21DX256VLK5) || defined(CPU_MK21DN512VLK5) || defined(CPU_MK21DX128VLK5WS) || defined(CPU_MK21DX256VLK5WS) || \
mbed_official 146:f64d43ff0c18 199 defined(CPU_MK21DN512VLK5WS) || defined(CPU_MK21DX128VMC5) || defined(CPU_MK21DX256VMC5) || defined(CPU_MK21DN512VMC5) || \
mbed_official 146:f64d43ff0c18 200 defined(CPU_MK21DX128VMC5WS) || defined(CPU_MK21DX256VMC5WS) || defined(CPU_MK21DN512VMC5WS) || defined(CPU_MK22DX128VLH5) || \
mbed_official 146:f64d43ff0c18 201 defined(CPU_MK22DX256VLH5) || defined(CPU_MK22DN512VLH5) || defined(CPU_MK22DX128VLK5) || defined(CPU_MK22DX256VLK5) || \
mbed_official 146:f64d43ff0c18 202 defined(CPU_MK22DN512VLK5) || defined(CPU_MK22DX128VMC5) || defined(CPU_MK22DX256VMC5) || defined(CPU_MK22DN512VMC5) || \
mbed_official 146:f64d43ff0c18 203 defined(CPU_MK22DX128VLF5) || defined(CPU_MK22DX256VLF5)
mbed_official 146:f64d43ff0c18 204 /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
mbed_official 146:f64d43ff0c18 205 #define FSL_FEATURE_SPI_IS_DSPI (1)
mbed_official 146:f64d43ff0c18 206 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 207 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
mbed_official 146:f64d43ff0c18 208 /* @brief Receive/transmit FIFO size in number of items.*/
mbed_official 146:f64d43ff0c18 209 #define FSL_FEATURE_SPI_FIFO_SIZE (4)
mbed_official 146:f64d43ff0c18 210 /* @brief Maximum transfer data width in bits.*/
mbed_official 146:f64d43ff0c18 211 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
mbed_official 146:f64d43ff0c18 212 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
mbed_official 146:f64d43ff0c18 213 #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (5)
mbed_official 146:f64d43ff0c18 214 /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 215 #define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \
mbed_official 146:f64d43ff0c18 216 ((x) == 0 ? (5) : \
mbed_official 146:f64d43ff0c18 217 ((x) == 1 ? (3) : (-1)))
mbed_official 146:f64d43ff0c18 218 /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 219 #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0)
mbed_official 146:f64d43ff0c18 220 /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 221 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
mbed_official 146:f64d43ff0c18 222 /* @brief Has 16-bit data transfer support.*/
mbed_official 146:f64d43ff0c18 223 #define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
mbed_official 146:f64d43ff0c18 224 #elif defined(CPU_MK22FN512VDC12)
mbed_official 146:f64d43ff0c18 225 /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
mbed_official 146:f64d43ff0c18 226 #define FSL_FEATURE_SPI_IS_DSPI (1)
mbed_official 146:f64d43ff0c18 227 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 228 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
mbed_official 146:f64d43ff0c18 229 /* @brief Receive/transmit FIFO size in number of items.*/
mbed_official 146:f64d43ff0c18 230 #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
mbed_official 146:f64d43ff0c18 231 ((x) == 0 ? (4) : \
mbed_official 146:f64d43ff0c18 232 ((x) == 1 ? (1) : (-1)))
mbed_official 146:f64d43ff0c18 233 /* @brief Maximum transfer data width in bits.*/
mbed_official 146:f64d43ff0c18 234 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
mbed_official 146:f64d43ff0c18 235 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
mbed_official 146:f64d43ff0c18 236 #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official 146:f64d43ff0c18 237 /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 238 #define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0)
mbed_official 146:f64d43ff0c18 239 /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 240 #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official 146:f64d43ff0c18 241 /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 242 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
mbed_official 146:f64d43ff0c18 243 /* @brief Has 16-bit data transfer support.*/
mbed_official 146:f64d43ff0c18 244 #define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
mbed_official 146:f64d43ff0c18 245 #elif defined(CPU_MK22FN512VDC12)
mbed_official 146:f64d43ff0c18 246 /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
mbed_official 146:f64d43ff0c18 247 #define FSL_FEATURE_SPI_IS_DSPI (1)
mbed_official 146:f64d43ff0c18 248 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 249 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
mbed_official 146:f64d43ff0c18 250 /* @brief Receive/transmit FIFO size in number of items.*/
mbed_official 146:f64d43ff0c18 251 #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
mbed_official 146:f64d43ff0c18 252 ((x) == 0 ? (4) : \
mbed_official 146:f64d43ff0c18 253 ((x) == 1 ? (1) : (-1)))
mbed_official 146:f64d43ff0c18 254 /* @brief Maximum transfer data width in bits.*/
mbed_official 146:f64d43ff0c18 255 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
mbed_official 146:f64d43ff0c18 256 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
mbed_official 146:f64d43ff0c18 257 #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official 146:f64d43ff0c18 258 /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 259 #define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \
mbed_official 146:f64d43ff0c18 260 ((x) == 0 ? (5) : \
mbed_official 146:f64d43ff0c18 261 ((x) == 1 ? (3) : (-1)))
mbed_official 146:f64d43ff0c18 262 /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 263 #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official 146:f64d43ff0c18 264 /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 265 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0)
mbed_official 146:f64d43ff0c18 266 /* @brief Has 16-bit data transfer support.*/
mbed_official 146:f64d43ff0c18 267 #define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1)
mbed_official 146:f64d43ff0c18 268 #elif defined(CPU_MKE02Z64VLC2) || defined(CPU_MKE02Z32VLC2) || defined(CPU_MKE02Z16VLC2) || defined(CPU_MKE02Z64VLD2) || \
mbed_official 146:f64d43ff0c18 269 defined(CPU_MKE02Z32VLD2) || defined(CPU_MKE02Z16VLD2) || defined(CPU_MKE02Z64VLH2) || defined(CPU_MKE02Z64VQH2) || \
mbed_official 146:f64d43ff0c18 270 defined(CPU_MKE02Z32VLH2) || defined(CPU_MKE02Z32VQH2) || defined(CPU_MKE04Z8VFK4) || defined(CPU_MKE04Z8VTG4) || \
mbed_official 146:f64d43ff0c18 271 defined(CPU_MKE04Z8VWJ4) || defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \
mbed_official 146:f64d43ff0c18 272 defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || defined(CPU_MKL02Z16VFM4) || \
mbed_official 146:f64d43ff0c18 273 defined(CPU_MKL02Z32VFM4)
mbed_official 146:f64d43ff0c18 274 /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
mbed_official 146:f64d43ff0c18 275 #define FSL_FEATURE_SPI_IS_DSPI (0)
mbed_official 146:f64d43ff0c18 276 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 277 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (0)
mbed_official 146:f64d43ff0c18 278 /* @brief Receive/transmit FIFO size in number of items.*/
mbed_official 146:f64d43ff0c18 279 #define FSL_FEATURE_SPI_FIFO_SIZE (1)
mbed_official 146:f64d43ff0c18 280 /* @brief Maximum transfer data width in bits.*/
mbed_official 146:f64d43ff0c18 281 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (8)
mbed_official 146:f64d43ff0c18 282 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
mbed_official 146:f64d43ff0c18 283 #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (1)
mbed_official 146:f64d43ff0c18 284 /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 285 #define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0)
mbed_official 146:f64d43ff0c18 286 /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 287 #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0)
mbed_official 146:f64d43ff0c18 288 /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 289 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
mbed_official 146:f64d43ff0c18 290 /* @brief Has 16-bit data transfer support.*/
mbed_official 146:f64d43ff0c18 291 #define FSL_FEATURE_SPI_16BIT_TRANSFERS (0)
mbed_official 146:f64d43ff0c18 292 #elif defined(CPU_MKL04Z8VFK4) || defined(CPU_MKL04Z16VFK4) || defined(CPU_MKL04Z32VFK4) || defined(CPU_MKL04Z8VLC4) || \
mbed_official 146:f64d43ff0c18 293 defined(CPU_MKL04Z16VLC4) || defined(CPU_MKL04Z32VLC4) || defined(CPU_MKL04Z8VFM4) || defined(CPU_MKL04Z16VFM4) || \
mbed_official 146:f64d43ff0c18 294 defined(CPU_MKL04Z32VFM4) || defined(CPU_MKL04Z16VLF4) || defined(CPU_MKL04Z32VLF4) || defined(CPU_MKL05Z8VFK4) || \
mbed_official 146:f64d43ff0c18 295 defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || \
mbed_official 146:f64d43ff0c18 296 defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
mbed_official 146:f64d43ff0c18 297 defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL14Z32VFM4) || defined(CPU_MKL14Z64VFM4) || \
mbed_official 146:f64d43ff0c18 298 defined(CPU_MKL14Z32VFT4) || defined(CPU_MKL14Z64VFT4) || defined(CPU_MKL14Z32VLH4) || defined(CPU_MKL14Z64VLH4) || \
mbed_official 146:f64d43ff0c18 299 defined(CPU_MKL14Z32VLK4) || defined(CPU_MKL14Z64VLK4) || defined(CPU_MKL15Z32VFM4) || defined(CPU_MKL15Z64VFM4) || \
mbed_official 146:f64d43ff0c18 300 defined(CPU_MKL15Z128VFM4) || defined(CPU_MKL15Z32VFT4) || defined(CPU_MKL15Z64VFT4) || defined(CPU_MKL15Z128VFT4) || \
mbed_official 146:f64d43ff0c18 301 defined(CPU_MKL15Z32VLH4) || defined(CPU_MKL15Z64VLH4) || defined(CPU_MKL15Z128VLH4) || defined(CPU_MKL15Z32VLK4) || \
mbed_official 146:f64d43ff0c18 302 defined(CPU_MKL15Z64VLK4) || defined(CPU_MKL15Z128VLK4) || defined(CPU_MKL24Z32VFM4) || defined(CPU_MKL24Z64VFM4) || \
mbed_official 146:f64d43ff0c18 303 defined(CPU_MKL24Z32VFT4) || defined(CPU_MKL24Z64VFT4) || defined(CPU_MKL24Z32VLH4) || defined(CPU_MKL24Z64VLH4) || \
mbed_official 146:f64d43ff0c18 304 defined(CPU_MKL24Z32VLK4) || defined(CPU_MKL24Z64VLK4) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || \
mbed_official 146:f64d43ff0c18 305 defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
mbed_official 146:f64d43ff0c18 306 defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || \
mbed_official 146:f64d43ff0c18 307 defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)
mbed_official 146:f64d43ff0c18 308 /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
mbed_official 146:f64d43ff0c18 309 #define FSL_FEATURE_SPI_IS_DSPI (0)
mbed_official 146:f64d43ff0c18 310 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 311 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
mbed_official 146:f64d43ff0c18 312 /* @brief Receive/transmit FIFO size in number of items.*/
mbed_official 146:f64d43ff0c18 313 #define FSL_FEATURE_SPI_FIFO_SIZE (1)
mbed_official 146:f64d43ff0c18 314 /* @brief Maximum transfer data width in bits.*/
mbed_official 146:f64d43ff0c18 315 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (8)
mbed_official 146:f64d43ff0c18 316 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
mbed_official 146:f64d43ff0c18 317 #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (1)
mbed_official 146:f64d43ff0c18 318 /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 319 #define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0)
mbed_official 146:f64d43ff0c18 320 /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 321 #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0)
mbed_official 146:f64d43ff0c18 322 /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 323 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
mbed_official 146:f64d43ff0c18 324 /* @brief Has 16-bit data transfer support.*/
mbed_official 146:f64d43ff0c18 325 #define FSL_FEATURE_SPI_16BIT_TRANSFERS (0)
mbed_official 146:f64d43ff0c18 326 #elif defined(CPU_MKL16Z32VFM4) || defined(CPU_MKL16Z64VFM4) || defined(CPU_MKL16Z128VFM4) || defined(CPU_MKL16Z32VFT4) || \
mbed_official 146:f64d43ff0c18 327 defined(CPU_MKL16Z64VFT4) || defined(CPU_MKL16Z128VFT4) || defined(CPU_MKL16Z32VLH4) || defined(CPU_MKL16Z64VLH4) || \
mbed_official 146:f64d43ff0c18 328 defined(CPU_MKL16Z128VLH4) || defined(CPU_MKL16Z256VLH4) || defined(CPU_MKL16Z256VLK4) || defined(CPU_MKL26Z32VFM4) || \
mbed_official 146:f64d43ff0c18 329 defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || \
mbed_official 146:f64d43ff0c18 330 defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || defined(CPU_MKL26Z128VLH4) || \
mbed_official 146:f64d43ff0c18 331 defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || \
mbed_official 146:f64d43ff0c18 332 defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL34Z64VLH4) || defined(CPU_MKL34Z64VLL4) || \
mbed_official 146:f64d43ff0c18 333 defined(CPU_MKL36Z64VLH4) || defined(CPU_MKL36Z128VLH4) || defined(CPU_MKL36Z256VLH4) || defined(CPU_MKL36Z64VLL4) || \
mbed_official 146:f64d43ff0c18 334 defined(CPU_MKL36Z128VLL4) || defined(CPU_MKL36Z256VLL4) || defined(CPU_MKL36Z128VMC4) || defined(CPU_MKL36Z256VMC4) || \
mbed_official 146:f64d43ff0c18 335 defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || \
mbed_official 146:f64d43ff0c18 336 defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
mbed_official 146:f64d43ff0c18 337 /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/
mbed_official 146:f64d43ff0c18 338 #define FSL_FEATURE_SPI_IS_DSPI (0)
mbed_official 146:f64d43ff0c18 339 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 340 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
mbed_official 146:f64d43ff0c18 341 /* @brief Receive/transmit FIFO size in number of items.*/
mbed_official 146:f64d43ff0c18 342 #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
mbed_official 146:f64d43ff0c18 343 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 344 ((x) == 1 ? (8) : (-1)))
mbed_official 146:f64d43ff0c18 345 /* @brief Maximum transfer data width in bits.*/
mbed_official 146:f64d43ff0c18 346 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
mbed_official 146:f64d43ff0c18 347 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/
mbed_official 146:f64d43ff0c18 348 #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (1)
mbed_official 146:f64d43ff0c18 349 /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 350 #define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0)
mbed_official 146:f64d43ff0c18 351 /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/
mbed_official 146:f64d43ff0c18 352 #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0)
mbed_official 146:f64d43ff0c18 353 /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/
mbed_official 146:f64d43ff0c18 354 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
mbed_official 146:f64d43ff0c18 355 /* @brief Has 16-bit data transfer support.*/
mbed_official 146:f64d43ff0c18 356 #define FSL_FEATURE_SPI_16BIT_TRANSFERS (1)
mbed_official 146:f64d43ff0c18 357 #else
mbed_official 146:f64d43ff0c18 358 #error "No valid CPU defined!"
mbed_official 146:f64d43ff0c18 359 #endif
mbed_official 146:f64d43ff0c18 360
mbed_official 146:f64d43ff0c18 361 #endif /* __FSL_DSPI_FEATURES_H__*/
mbed_official 146:f64d43ff0c18 362 /*******************************************************************************
mbed_official 146:f64d43ff0c18 363 * EOF
mbed_official 146:f64d43ff0c18 364 ******************************************************************************/
mbed_official 146:f64d43ff0c18 365