Diff: targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c

Revision:

148:21d94c44109e

Parent:

144:ef7eb2e8f9f7

--- a/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c	Fri Sep 16 16:24:25 2016 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c	Fri Sep 30 18:07:01 2016 +0100
@@ -59,7 +59,7 @@
 void gpio_irq7(void) {handle_interrupt_in(7);}
 
 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
-    // PINT only supprt PIO0_*, PIO1_* and from PIO2_0 to PIO0_7 interrupt
+    // PINT only supprt PIO0_*, PIO1_* and from PIO2_0 to PIO2_7 interrupt
     if (pin >= P2_8) return -1;
     
     irq_handler = handler;
@@ -79,7 +79,18 @@
     /* Enable AHB clock to the PIN, GPIO and IOCON domain. */
     LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 19) | (1 << 16) | (1 << 7));
     
-    LPC_SYSCON->PINTSEL[obj->ch] = ((((pin >> PORT_SHIFT) & 0x3) * 24) + ((pin >> PIN_SHIFT) & 0x1F));
+    /* Gets offset value for each port */
+    uint32_t offset;
+    switch ((pin >> PORT_SHIFT) & 0x3) {
+        case 0: offset = 0; // PIO0[23:0]
+                break;
+        case 1: offset = 24; // PIO1[31:0]
+                break;
+        case 2: offset = 56; // PIO2[7:0]
+                break;
+    }
+    /* Set the INTPIN number : offset + pin_number */
+    LPC_SYSCON->PINTSEL[obj->ch] = (offset + ((pin >> PIN_SHIFT) & 0x1F));
     
     // Interrupt Wake-Up Enable
     LPC_SYSCON->STARTERP0 |= (1 << obj->ch);
@@ -88,14 +99,22 @@
     
     void (*channels_irq)(void) = NULL;
     switch (obj->ch) {
-        case 0: channels_irq = &gpio_irq0; break;
-        case 1: channels_irq = &gpio_irq1; break;
-        case 2: channels_irq = &gpio_irq2; break;
-        case 3: channels_irq = &gpio_irq3; break;
-        case 4: channels_irq = &gpio_irq4; break;
-        case 5: channels_irq = &gpio_irq5; break;
-        case 6: channels_irq = &gpio_irq6; break;
-        case 7: channels_irq = &gpio_irq7; break;
+        case 0: channels_irq = &gpio_irq0;
+                break;
+        case 1: channels_irq = &gpio_irq1;
+                break;
+        case 2: channels_irq = &gpio_irq2;
+                break;
+        case 3: channels_irq = &gpio_irq3;
+                break;
+        case 4: channels_irq = &gpio_irq4;
+                break;
+        case 5: channels_irq = &gpio_irq5;
+                break;
+        case 6: channels_irq = &gpio_irq6;
+                break;
+        case 7: channels_irq = &gpio_irq7;
+                break;
     }
     NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
     NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));