Hugo Zijlmans / Mbed 2 deprecated BLDC

Dependencies:   mbed

LPC1768.h@2:f034e862af1f, 2010-12-02 (annotated)

Committer:
hugozijlmans
Date:
Thu Dec 02 20:55:45 2010 +0000
Revision:
2:f034e862af1f
Parent:
1:2c52307d223f 
Added UART0 support over USB mBed1768

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hugozijlmans 1:2c52307d223f 1 #ifndef __LPC1768_h
hugozijlmans 1:2c52307d223f 2 #define __LPC1768_h
hugozijlmans 1:2c52307d223f 3
hugozijlmans 1:2c52307d223f 4 // Define the register names that haven't been defined
hugozijlmans 1:2c52307d223f 5
hugozijlmans 1:2c52307d223f 6 // MCPWM
hugozijlmans 1:2c52307d223f 7 #define MCLIM0 LPC_MCPWM->MCPER0
hugozijlmans 1:2c52307d223f 8 #define MCLIM1 LPC_MCPWM->MCPER1
hugozijlmans 1:2c52307d223f 9 #define MCLIM2 LPC_MCPWM->MCPER2
hugozijlmans 1:2c52307d223f 10
hugozijlmans 1:2c52307d223f 11 // Perhiperal clock select
hugozijlmans 1:2c52307d223f 12 #define PCLKSEL0 LPC_SC->PCLKSEL0
hugozijlmans 2:f034e862af1f 13 #define PCLK_UART1_1 1 << 9
hugozijlmans 2:f034e862af1f 14 #define PCLK_UART1_0 1 << 8
hugozijlmans 2:f034e862af1f 15 #define PCLK_UART0_1 1 << 7
hugozijlmans 2:f034e862af1f 16 #define PCLK_UART0_0 1 << 6
hugozijlmans 2:f034e862af1f 17 #define PCLK_TIMER1_1 1 << 5
hugozijlmans 2:f034e862af1f 18 #define PCLK_TIMER1_0 1 << 4
hugozijlmans 1:2c52307d223f 19 #define PCLK_TIMER0_1 1 << 3
hugozijlmans 1:2c52307d223f 20 #define PCLK_TIMER0_0 1 << 2
hugozijlmans 2:f034e862af1f 21 #define PCLK_WDT_1 1 << 1
hugozijlmans 2:f034e862af1f 22 #define PCLK_WDT_0 1 << 0
hugozijlmans 1:2c52307d223f 23 #define PCLKSEL1 LPC_SC->PCLKSEL1
hugozijlmans 1:2c52307d223f 24 #define PCLK_RIT_1 1 << 27
hugozijlmans 1:2c52307d223f 25 #define PCLK_RIT_0 1 << 26
hugozijlmans 1:2c52307d223f 26
hugozijlmans 1:2c52307d223f 27 // Perhiperal power control
hugozijlmans 1:2c52307d223f 28 #define PCONP LPC_SC->PCONP
hugozijlmans 1:2c52307d223f 29 #define PCTIM0 1 << 1
hugozijlmans 1:2c52307d223f 30 #define PCTIM1 1 << 2
hugozijlmans 2:f034e862af1f 31 #define PCUART0 1 << 3
hugozijlmans 2:f034e862af1f 32 #define PCUART1 1 << 4
hugozijlmans 1:2c52307d223f 33 #define PCRIT 1 << 16
hugozijlmans 1:2c52307d223f 34
hugozijlmans 1:2c52307d223f 35 // CLKOUT
hugozijlmans 1:2c52307d223f 36 #define CLKSRCSEL LPC_SC->CLKSRCSEL
hugozijlmans 1:2c52307d223f 37 #define CCLKCFG LPC_SC->CCLKCFG
hugozijlmans 1:2c52307d223f 38
hugozijlmans 2:f034e862af1f 39 // Pin output/input function selection
hugozijlmans 2:f034e862af1f 40 #define PINSEL0 LPC_PINCON->PINSEL0
hugozijlmans 2:f034e862af1f 41
hugozijlmans 1:2c52307d223f 42 // FI0
hugozijlmans 1:2c52307d223f 43 #define FIOSET LPC_GPIO1->FIOSET
hugozijlmans 1:2c52307d223f 44 #define FIOCLR LPC_GPIO1->FIOCLR
hugozijlmans 1:2c52307d223f 45 #define FIOPIN LPC_GPIO1->FIOPIN
hugozijlmans 1:2c52307d223f 46 #define FIODIR LPC_GPIO1->FIODIR
hugozijlmans 1:2c52307d223f 47
hugozijlmans 1:2c52307d223f 48 // PLL0
hugozijlmans 1:2c52307d223f 49 #define PLL0FEED LPC_SC->PLL0FEED
hugozijlmans 1:2c52307d223f 50 #define PLL0STAT LPC_SC->PLL0STAT
hugozijlmans 1:2c52307d223f 51 #define PLL0CFG LPC_SC->PLL0CFG
hugozijlmans 1:2c52307d223f 52 #define PLL0CON LPC_SC->PLL0CON
hugozijlmans 1:2c52307d223f 53
hugozijlmans 1:2c52307d223f 54 // Timer0
hugozijlmans 1:2c52307d223f 55 #define T0MR0 LPC_TIM0->MR0
hugozijlmans 1:2c52307d223f 56 #define T0PR LPC_TIM0->PR
hugozijlmans 1:2c52307d223f 57 #define T0TCR LPC_TIM0->TCR
hugozijlmans 1:2c52307d223f 58 #define T0CTCR LPC_TIM0->CTCR
hugozijlmans 1:2c52307d223f 59 #define T0MCR LPC_TIM0->MCR
hugozijlmans 1:2c52307d223f 60 #define T0IR LPC_TIM0->IR
hugozijlmans 1:2c52307d223f 61 #define T0IR_MR0 1 << 0
hugozijlmans 1:2c52307d223f 62 #define T0IR_MR1 1 << 1
hugozijlmans 1:2c52307d223f 63 #define T0IR_MR2 1 << 2
hugozijlmans 1:2c52307d223f 64 #define T0IR_MR3 1 << 3
hugozijlmans 1:2c52307d223f 65 #define T0IR_CR0 1 << 4
hugozijlmans 1:2c52307d223f 66 #define T0IR_CR1 1 << 5
hugozijlmans 1:2c52307d223f 67
hugozijlmans 2:f034e862af1f 68 // UART0
hugozijlmans 2:f034e862af1f 69 #define U0LCR LPC_UART0->LCR
hugozijlmans 2:f034e862af1f 70 #define U0DLL LPC_UART0->DLL
hugozijlmans 2:f034e862af1f 71 #define U0DLM LPC_UART0->DLM
hugozijlmans 2:f034e862af1f 72 #define U0FDR LPC_UART0->FDR
hugozijlmans 2:f034e862af1f 73 #define U0FCR LPC_UART0->FCR
hugozijlmans 2:f034e862af1f 74 #define U0THR LPC_UART0->THR
hugozijlmans 2:f034e862af1f 75 #define U0RBR LPC_UART0->RBR
hugozijlmans 2:f034e862af1f 76 #define U0IER LPC_UART0->IER
hugozijlmans 2:f034e862af1f 77 #define U0IIR LPC_UART0->IIR
hugozijlmans 2:f034e862af1f 78
hugozijlmans 1:2c52307d223f 79 // RIT
hugozijlmans 1:2c52307d223f 80 #define RICOMPVAL LPC_RIT->RICOMPVAL
hugozijlmans 1:2c52307d223f 81 #define RICTRL LPC_RIT->RICTRL
hugozijlmans 1:2c52307d223f 82 #define RITINT 1 << 0
hugozijlmans 1:2c52307d223f 83 #define RITENCLR 1 << 1
hugozijlmans 1:2c52307d223f 84 #define RITENBR 1 << 2
hugozijlmans 1:2c52307d223f 85 #define RITEN 1 << 3
hugozijlmans 1:2c52307d223f 86
hugozijlmans 1:2c52307d223f 87 extern void PLL0_init(void);
hugozijlmans 1:2c52307d223f 88 extern void PLL0_disconnect(void);
hugozijlmans 1:2c52307d223f 89 extern void PLL0_connect(void);
hugozijlmans 1:2c52307d223f 90 extern void PLL0_disable(void);
hugozijlmans 1:2c52307d223f 91 extern void PLL0_enable(void);
hugozijlmans 1:2c52307d223f 92 extern void LED_init(void);
hugozijlmans 1:2c52307d223f 93
hugozijlmans 1:2c52307d223f 94 #endif