Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_NUCLEO_F103RB/stm32f103xb.h@96:487b796308b0, 2015-03-17 (annotated)

Committer:
Kojto
Date:
Tue Mar 17 14:27:45 2015 +0000
Revision:
96:487b796308b0
Release 96 of the mbed library



Changes:

- IAR support for ble boards, lpc, ethernet stack

- RTC - attach function to redirect time functions

- Nucleo F103RB - cube driver

- k20xx - fixes for teensy and k20 platforms in sleep/deepsleep and usb

- STM32L0, Nucleo/Disco L053 - refactoring

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 96:487b796308b0 1 /**
Kojto 96:487b796308b0 2 ******************************************************************************
Kojto 96:487b796308b0 3 * @file stm32f103xb.h
Kojto 96:487b796308b0 4 * @author MCD Application Team
Kojto 96:487b796308b0 5 * @version V4.0.0
Kojto 96:487b796308b0 6 * @date 16-December-2014
Kojto 96:487b796308b0 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
Kojto 96:487b796308b0 8 * This file contains all the peripheral register's definitions, bits
Kojto 96:487b796308b0 9 * definitions and memory mapping for STM32F1xx devices.
Kojto 96:487b796308b0 10 *
Kojto 96:487b796308b0 11 * This file contains:
Kojto 96:487b796308b0 12 * - Data structures and the address mapping for all peripherals
Kojto 96:487b796308b0 13 * - Peripheral's registers declarations and bits definition
Kojto 96:487b796308b0 14 * - Macros to access peripheral’s registers hardware
Kojto 96:487b796308b0 15 *
Kojto 96:487b796308b0 16 ******************************************************************************
Kojto 96:487b796308b0 17 * @attention
Kojto 96:487b796308b0 18 *
Kojto 96:487b796308b0 19 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto 96:487b796308b0 20 *
Kojto 96:487b796308b0 21 * Redistribution and use in source and binary forms, with or without modification,
Kojto 96:487b796308b0 22 * are permitted provided that the following conditions are met:
Kojto 96:487b796308b0 23 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 96:487b796308b0 24 * this list of conditions and the following disclaimer.
Kojto 96:487b796308b0 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 96:487b796308b0 26 * this list of conditions and the following disclaimer in the documentation
Kojto 96:487b796308b0 27 * and/or other materials provided with the distribution.
Kojto 96:487b796308b0 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 96:487b796308b0 29 * may be used to endorse or promote products derived from this software
Kojto 96:487b796308b0 30 * without specific prior written permission.
Kojto 96:487b796308b0 31 *
Kojto 96:487b796308b0 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 96:487b796308b0 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 96:487b796308b0 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 96:487b796308b0 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 96:487b796308b0 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 96:487b796308b0 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 96:487b796308b0 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 96:487b796308b0 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 96:487b796308b0 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 96:487b796308b0 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 96:487b796308b0 42 *
Kojto 96:487b796308b0 43 ******************************************************************************
Kojto 96:487b796308b0 44 */
Kojto 96:487b796308b0 45
Kojto 96:487b796308b0 46
Kojto 96:487b796308b0 47 /** @addtogroup CMSIS
Kojto 96:487b796308b0 48 * @{
Kojto 96:487b796308b0 49 */
Kojto 96:487b796308b0 50
Kojto 96:487b796308b0 51 /** @addtogroup stm32f103xb
Kojto 96:487b796308b0 52 * @{
Kojto 96:487b796308b0 53 */
Kojto 96:487b796308b0 54
Kojto 96:487b796308b0 55 #ifndef __STM32F103xB_H
Kojto 96:487b796308b0 56 #define __STM32F103xB_H
Kojto 96:487b796308b0 57
Kojto 96:487b796308b0 58 #ifdef __cplusplus
Kojto 96:487b796308b0 59 extern "C" {
Kojto 96:487b796308b0 60 #endif
Kojto 96:487b796308b0 61
Kojto 96:487b796308b0 62 /** @addtogroup Configuration_section_for_CMSIS
Kojto 96:487b796308b0 63 * @{
Kojto 96:487b796308b0 64 */
Kojto 96:487b796308b0 65 /**
Kojto 96:487b796308b0 66 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
Kojto 96:487b796308b0 67 */
Kojto 96:487b796308b0 68 #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
Kojto 96:487b796308b0 69 #define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
Kojto 96:487b796308b0 70 #define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
Kojto 96:487b796308b0 71 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 96:487b796308b0 72
Kojto 96:487b796308b0 73 /**
Kojto 96:487b796308b0 74 * @}
Kojto 96:487b796308b0 75 */
Kojto 96:487b796308b0 76
Kojto 96:487b796308b0 77 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 96:487b796308b0 78 * @{
Kojto 96:487b796308b0 79 */
Kojto 96:487b796308b0 80
Kojto 96:487b796308b0 81 /**
Kojto 96:487b796308b0 82 * @brief STM32F10x Interrupt Number Definition, according to the selected device
Kojto 96:487b796308b0 83 * in @ref Library_configuration_section
Kojto 96:487b796308b0 84 */
Kojto 96:487b796308b0 85
Kojto 96:487b796308b0 86 /*!< Interrupt Number Definition */
Kojto 96:487b796308b0 87 typedef enum
Kojto 96:487b796308b0 88 {
Kojto 96:487b796308b0 89 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
Kojto 96:487b796308b0 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 96:487b796308b0 91 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
Kojto 96:487b796308b0 92 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
Kojto 96:487b796308b0 93 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
Kojto 96:487b796308b0 94 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
Kojto 96:487b796308b0 95 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
Kojto 96:487b796308b0 96 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
Kojto 96:487b796308b0 97 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
Kojto 96:487b796308b0 98
Kojto 96:487b796308b0 99 /****** STM32 specific Interrupt Numbers *********************************************************/
Kojto 96:487b796308b0 100 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 96:487b796308b0 101 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
Kojto 96:487b796308b0 102 TAMPER_IRQn = 2, /*!< Tamper Interrupt */
Kojto 96:487b796308b0 103 RTC_IRQn = 3, /*!< RTC global Interrupt */
Kojto 96:487b796308b0 104 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
Kojto 96:487b796308b0 105 RCC_IRQn = 5, /*!< RCC global Interrupt */
Kojto 96:487b796308b0 106 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
Kojto 96:487b796308b0 107 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
Kojto 96:487b796308b0 108 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
Kojto 96:487b796308b0 109 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
Kojto 96:487b796308b0 110 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
Kojto 96:487b796308b0 111 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
Kojto 96:487b796308b0 112 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
Kojto 96:487b796308b0 113 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
Kojto 96:487b796308b0 114 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
Kojto 96:487b796308b0 115 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
Kojto 96:487b796308b0 116 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
Kojto 96:487b796308b0 117 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
Kojto 96:487b796308b0 118 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
Kojto 96:487b796308b0 119 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
Kojto 96:487b796308b0 120 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
Kojto 96:487b796308b0 121 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
Kojto 96:487b796308b0 122 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
Kojto 96:487b796308b0 123 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
Kojto 96:487b796308b0 124 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
Kojto 96:487b796308b0 125 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
Kojto 96:487b796308b0 126 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
Kojto 96:487b796308b0 127 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
Kojto 96:487b796308b0 128 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
Kojto 96:487b796308b0 129 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
Kojto 96:487b796308b0 130 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
Kojto 96:487b796308b0 131 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
Kojto 96:487b796308b0 132 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
Kojto 96:487b796308b0 133 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
Kojto 96:487b796308b0 134 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
Kojto 96:487b796308b0 135 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
Kojto 96:487b796308b0 136 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
Kojto 96:487b796308b0 137 USART1_IRQn = 37, /*!< USART1 global Interrupt */
Kojto 96:487b796308b0 138 USART2_IRQn = 38, /*!< USART2 global Interrupt */
Kojto 96:487b796308b0 139 USART3_IRQn = 39, /*!< USART3 global Interrupt */
Kojto 96:487b796308b0 140 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
Kojto 96:487b796308b0 141 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
Kojto 96:487b796308b0 142 USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
Kojto 96:487b796308b0 143 } IRQn_Type;
Kojto 96:487b796308b0 144
Kojto 96:487b796308b0 145
Kojto 96:487b796308b0 146 /**
Kojto 96:487b796308b0 147 * @}
Kojto 96:487b796308b0 148 */
Kojto 96:487b796308b0 149
Kojto 96:487b796308b0 150 #include "core_cm3.h"
Kojto 96:487b796308b0 151 #include "system_stm32f1xx.h"
Kojto 96:487b796308b0 152 #include <stdint.h>
Kojto 96:487b796308b0 153
Kojto 96:487b796308b0 154 /** @addtogroup Peripheral_registers_structures
Kojto 96:487b796308b0 155 * @{
Kojto 96:487b796308b0 156 */
Kojto 96:487b796308b0 157
Kojto 96:487b796308b0 158 /**
Kojto 96:487b796308b0 159 * @brief Analog to Digital Converter
Kojto 96:487b796308b0 160 */
Kojto 96:487b796308b0 161
Kojto 96:487b796308b0 162 typedef struct
Kojto 96:487b796308b0 163 {
Kojto 96:487b796308b0 164 __IO uint32_t SR;
Kojto 96:487b796308b0 165 __IO uint32_t CR1;
Kojto 96:487b796308b0 166 __IO uint32_t CR2;
Kojto 96:487b796308b0 167 __IO uint32_t SMPR1;
Kojto 96:487b796308b0 168 __IO uint32_t SMPR2;
Kojto 96:487b796308b0 169 __IO uint32_t JOFR1;
Kojto 96:487b796308b0 170 __IO uint32_t JOFR2;
Kojto 96:487b796308b0 171 __IO uint32_t JOFR3;
Kojto 96:487b796308b0 172 __IO uint32_t JOFR4;
Kojto 96:487b796308b0 173 __IO uint32_t HTR;
Kojto 96:487b796308b0 174 __IO uint32_t LTR;
Kojto 96:487b796308b0 175 __IO uint32_t SQR1;
Kojto 96:487b796308b0 176 __IO uint32_t SQR2;
Kojto 96:487b796308b0 177 __IO uint32_t SQR3;
Kojto 96:487b796308b0 178 __IO uint32_t JSQR;
Kojto 96:487b796308b0 179 __IO uint32_t JDR1;
Kojto 96:487b796308b0 180 __IO uint32_t JDR2;
Kojto 96:487b796308b0 181 __IO uint32_t JDR3;
Kojto 96:487b796308b0 182 __IO uint32_t JDR4;
Kojto 96:487b796308b0 183 __IO uint32_t DR;
Kojto 96:487b796308b0 184 } ADC_TypeDef;
Kojto 96:487b796308b0 185
Kojto 96:487b796308b0 186 /**
Kojto 96:487b796308b0 187 * @brief Backup Registers
Kojto 96:487b796308b0 188 */
Kojto 96:487b796308b0 189
Kojto 96:487b796308b0 190 typedef struct
Kojto 96:487b796308b0 191 {
Kojto 96:487b796308b0 192 uint32_t RESERVED0;
Kojto 96:487b796308b0 193 __IO uint32_t DR1;
Kojto 96:487b796308b0 194 __IO uint32_t DR2;
Kojto 96:487b796308b0 195 __IO uint32_t DR3;
Kojto 96:487b796308b0 196 __IO uint32_t DR4;
Kojto 96:487b796308b0 197 __IO uint32_t DR5;
Kojto 96:487b796308b0 198 __IO uint32_t DR6;
Kojto 96:487b796308b0 199 __IO uint32_t DR7;
Kojto 96:487b796308b0 200 __IO uint32_t DR8;
Kojto 96:487b796308b0 201 __IO uint32_t DR9;
Kojto 96:487b796308b0 202 __IO uint32_t DR10;
Kojto 96:487b796308b0 203 __IO uint32_t RTCCR;
Kojto 96:487b796308b0 204 __IO uint32_t CR;
Kojto 96:487b796308b0 205 __IO uint32_t CSR;
Kojto 96:487b796308b0 206 } BKP_TypeDef;
Kojto 96:487b796308b0 207
Kojto 96:487b796308b0 208 /**
Kojto 96:487b796308b0 209 * @brief Controller Area Network TxMailBox
Kojto 96:487b796308b0 210 */
Kojto 96:487b796308b0 211
Kojto 96:487b796308b0 212 typedef struct
Kojto 96:487b796308b0 213 {
Kojto 96:487b796308b0 214 __IO uint32_t TIR;
Kojto 96:487b796308b0 215 __IO uint32_t TDTR;
Kojto 96:487b796308b0 216 __IO uint32_t TDLR;
Kojto 96:487b796308b0 217 __IO uint32_t TDHR;
Kojto 96:487b796308b0 218 } CAN_TxMailBox_TypeDef;
Kojto 96:487b796308b0 219
Kojto 96:487b796308b0 220 /**
Kojto 96:487b796308b0 221 * @brief Controller Area Network FIFOMailBox
Kojto 96:487b796308b0 222 */
Kojto 96:487b796308b0 223
Kojto 96:487b796308b0 224 typedef struct
Kojto 96:487b796308b0 225 {
Kojto 96:487b796308b0 226 __IO uint32_t RIR;
Kojto 96:487b796308b0 227 __IO uint32_t RDTR;
Kojto 96:487b796308b0 228 __IO uint32_t RDLR;
Kojto 96:487b796308b0 229 __IO uint32_t RDHR;
Kojto 96:487b796308b0 230 } CAN_FIFOMailBox_TypeDef;
Kojto 96:487b796308b0 231
Kojto 96:487b796308b0 232 /**
Kojto 96:487b796308b0 233 * @brief Controller Area Network FilterRegister
Kojto 96:487b796308b0 234 */
Kojto 96:487b796308b0 235
Kojto 96:487b796308b0 236 typedef struct
Kojto 96:487b796308b0 237 {
Kojto 96:487b796308b0 238 __IO uint32_t FR1;
Kojto 96:487b796308b0 239 __IO uint32_t FR2;
Kojto 96:487b796308b0 240 } CAN_FilterRegister_TypeDef;
Kojto 96:487b796308b0 241
Kojto 96:487b796308b0 242 /**
Kojto 96:487b796308b0 243 * @brief Controller Area Network
Kojto 96:487b796308b0 244 */
Kojto 96:487b796308b0 245
Kojto 96:487b796308b0 246 typedef struct
Kojto 96:487b796308b0 247 {
Kojto 96:487b796308b0 248 __IO uint32_t MCR;
Kojto 96:487b796308b0 249 __IO uint32_t MSR;
Kojto 96:487b796308b0 250 __IO uint32_t TSR;
Kojto 96:487b796308b0 251 __IO uint32_t RF0R;
Kojto 96:487b796308b0 252 __IO uint32_t RF1R;
Kojto 96:487b796308b0 253 __IO uint32_t IER;
Kojto 96:487b796308b0 254 __IO uint32_t ESR;
Kojto 96:487b796308b0 255 __IO uint32_t BTR;
Kojto 96:487b796308b0 256 uint32_t RESERVED0[88];
Kojto 96:487b796308b0 257 CAN_TxMailBox_TypeDef sTxMailBox[3];
Kojto 96:487b796308b0 258 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
Kojto 96:487b796308b0 259 uint32_t RESERVED1[12];
Kojto 96:487b796308b0 260 __IO uint32_t FMR;
Kojto 96:487b796308b0 261 __IO uint32_t FM1R;
Kojto 96:487b796308b0 262 uint32_t RESERVED2;
Kojto 96:487b796308b0 263 __IO uint32_t FS1R;
Kojto 96:487b796308b0 264 uint32_t RESERVED3;
Kojto 96:487b796308b0 265 __IO uint32_t FFA1R;
Kojto 96:487b796308b0 266 uint32_t RESERVED4;
Kojto 96:487b796308b0 267 __IO uint32_t FA1R;
Kojto 96:487b796308b0 268 uint32_t RESERVED5[8];
Kojto 96:487b796308b0 269 CAN_FilterRegister_TypeDef sFilterRegister[14];
Kojto 96:487b796308b0 270 } CAN_TypeDef;
Kojto 96:487b796308b0 271
Kojto 96:487b796308b0 272 /**
Kojto 96:487b796308b0 273 * @brief CRC calculation unit
Kojto 96:487b796308b0 274 */
Kojto 96:487b796308b0 275
Kojto 96:487b796308b0 276 typedef struct
Kojto 96:487b796308b0 277 {
Kojto 96:487b796308b0 278 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 96:487b796308b0 279 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 96:487b796308b0 280 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 96:487b796308b0 281 } CRC_TypeDef;
Kojto 96:487b796308b0 282
Kojto 96:487b796308b0 283
Kojto 96:487b796308b0 284 /**
Kojto 96:487b796308b0 285 * @brief Debug MCU
Kojto 96:487b796308b0 286 */
Kojto 96:487b796308b0 287
Kojto 96:487b796308b0 288 typedef struct
Kojto 96:487b796308b0 289 {
Kojto 96:487b796308b0 290 __IO uint32_t IDCODE;
Kojto 96:487b796308b0 291 __IO uint32_t CR;
Kojto 96:487b796308b0 292 }DBGMCU_TypeDef;
Kojto 96:487b796308b0 293
Kojto 96:487b796308b0 294 /**
Kojto 96:487b796308b0 295 * @brief DMA Controller
Kojto 96:487b796308b0 296 */
Kojto 96:487b796308b0 297
Kojto 96:487b796308b0 298 typedef struct
Kojto 96:487b796308b0 299 {
Kojto 96:487b796308b0 300 __IO uint32_t CCR;
Kojto 96:487b796308b0 301 __IO uint32_t CNDTR;
Kojto 96:487b796308b0 302 __IO uint32_t CPAR;
Kojto 96:487b796308b0 303 __IO uint32_t CMAR;
Kojto 96:487b796308b0 304 } DMA_Channel_TypeDef;
Kojto 96:487b796308b0 305
Kojto 96:487b796308b0 306 typedef struct
Kojto 96:487b796308b0 307 {
Kojto 96:487b796308b0 308 __IO uint32_t ISR;
Kojto 96:487b796308b0 309 __IO uint32_t IFCR;
Kojto 96:487b796308b0 310 } DMA_TypeDef;
Kojto 96:487b796308b0 311
Kojto 96:487b796308b0 312
Kojto 96:487b796308b0 313
Kojto 96:487b796308b0 314 /**
Kojto 96:487b796308b0 315 * @brief External Interrupt/Event Controller
Kojto 96:487b796308b0 316 */
Kojto 96:487b796308b0 317
Kojto 96:487b796308b0 318 typedef struct
Kojto 96:487b796308b0 319 {
Kojto 96:487b796308b0 320 __IO uint32_t IMR;
Kojto 96:487b796308b0 321 __IO uint32_t EMR;
Kojto 96:487b796308b0 322 __IO uint32_t RTSR;
Kojto 96:487b796308b0 323 __IO uint32_t FTSR;
Kojto 96:487b796308b0 324 __IO uint32_t SWIER;
Kojto 96:487b796308b0 325 __IO uint32_t PR;
Kojto 96:487b796308b0 326 } EXTI_TypeDef;
Kojto 96:487b796308b0 327
Kojto 96:487b796308b0 328 /**
Kojto 96:487b796308b0 329 * @brief FLASH Registers
Kojto 96:487b796308b0 330 */
Kojto 96:487b796308b0 331
Kojto 96:487b796308b0 332 typedef struct
Kojto 96:487b796308b0 333 {
Kojto 96:487b796308b0 334 __IO uint32_t ACR;
Kojto 96:487b796308b0 335 __IO uint32_t KEYR;
Kojto 96:487b796308b0 336 __IO uint32_t OPTKEYR;
Kojto 96:487b796308b0 337 __IO uint32_t SR;
Kojto 96:487b796308b0 338 __IO uint32_t CR;
Kojto 96:487b796308b0 339 __IO uint32_t AR;
Kojto 96:487b796308b0 340 __IO uint32_t RESERVED;
Kojto 96:487b796308b0 341 __IO uint32_t OBR;
Kojto 96:487b796308b0 342 __IO uint32_t WRPR;
Kojto 96:487b796308b0 343 } FLASH_TypeDef;
Kojto 96:487b796308b0 344
Kojto 96:487b796308b0 345 /**
Kojto 96:487b796308b0 346 * @brief Option Bytes Registers
Kojto 96:487b796308b0 347 */
Kojto 96:487b796308b0 348
Kojto 96:487b796308b0 349 typedef struct
Kojto 96:487b796308b0 350 {
Kojto 96:487b796308b0 351 __IO uint16_t RDP;
Kojto 96:487b796308b0 352 __IO uint16_t USER;
Kojto 96:487b796308b0 353 __IO uint16_t Data0;
Kojto 96:487b796308b0 354 __IO uint16_t Data1;
Kojto 96:487b796308b0 355 __IO uint16_t WRP0;
Kojto 96:487b796308b0 356 __IO uint16_t WRP1;
Kojto 96:487b796308b0 357 __IO uint16_t WRP2;
Kojto 96:487b796308b0 358 __IO uint16_t WRP3;
Kojto 96:487b796308b0 359 } OB_TypeDef;
Kojto 96:487b796308b0 360
Kojto 96:487b796308b0 361 /**
Kojto 96:487b796308b0 362 * @brief General Purpose I/O
Kojto 96:487b796308b0 363 */
Kojto 96:487b796308b0 364
Kojto 96:487b796308b0 365 typedef struct
Kojto 96:487b796308b0 366 {
Kojto 96:487b796308b0 367 __IO uint32_t CRL;
Kojto 96:487b796308b0 368 __IO uint32_t CRH;
Kojto 96:487b796308b0 369 __IO uint32_t IDR;
Kojto 96:487b796308b0 370 __IO uint32_t ODR;
Kojto 96:487b796308b0 371 __IO uint32_t BSRR;
Kojto 96:487b796308b0 372 __IO uint32_t BRR;
Kojto 96:487b796308b0 373 __IO uint32_t LCKR;
Kojto 96:487b796308b0 374 } GPIO_TypeDef;
Kojto 96:487b796308b0 375
Kojto 96:487b796308b0 376 /**
Kojto 96:487b796308b0 377 * @brief Alternate Function I/O
Kojto 96:487b796308b0 378 */
Kojto 96:487b796308b0 379
Kojto 96:487b796308b0 380 typedef struct
Kojto 96:487b796308b0 381 {
Kojto 96:487b796308b0 382 __IO uint32_t EVCR;
Kojto 96:487b796308b0 383 __IO uint32_t MAPR;
Kojto 96:487b796308b0 384 __IO uint32_t EXTICR[4];
Kojto 96:487b796308b0 385 uint32_t RESERVED0;
Kojto 96:487b796308b0 386 __IO uint32_t MAPR2;
Kojto 96:487b796308b0 387 } AFIO_TypeDef;
Kojto 96:487b796308b0 388 /**
Kojto 96:487b796308b0 389 * @brief Inter Integrated Circuit Interface
Kojto 96:487b796308b0 390 */
Kojto 96:487b796308b0 391
Kojto 96:487b796308b0 392 typedef struct
Kojto 96:487b796308b0 393 {
Kojto 96:487b796308b0 394 __IO uint32_t CR1;
Kojto 96:487b796308b0 395 __IO uint32_t CR2;
Kojto 96:487b796308b0 396 __IO uint32_t OAR1;
Kojto 96:487b796308b0 397 __IO uint32_t OAR2;
Kojto 96:487b796308b0 398 __IO uint32_t DR;
Kojto 96:487b796308b0 399 __IO uint32_t SR1;
Kojto 96:487b796308b0 400 __IO uint32_t SR2;
Kojto 96:487b796308b0 401 __IO uint32_t CCR;
Kojto 96:487b796308b0 402 __IO uint32_t TRISE;
Kojto 96:487b796308b0 403 } I2C_TypeDef;
Kojto 96:487b796308b0 404
Kojto 96:487b796308b0 405 /**
Kojto 96:487b796308b0 406 * @brief Independent WATCHDOG
Kojto 96:487b796308b0 407 */
Kojto 96:487b796308b0 408
Kojto 96:487b796308b0 409 typedef struct
Kojto 96:487b796308b0 410 {
Kojto 96:487b796308b0 411 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
Kojto 96:487b796308b0 412 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
Kojto 96:487b796308b0 413 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
Kojto 96:487b796308b0 414 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
Kojto 96:487b796308b0 415 } IWDG_TypeDef;
Kojto 96:487b796308b0 416
Kojto 96:487b796308b0 417 /**
Kojto 96:487b796308b0 418 * @brief Power Control
Kojto 96:487b796308b0 419 */
Kojto 96:487b796308b0 420
Kojto 96:487b796308b0 421 typedef struct
Kojto 96:487b796308b0 422 {
Kojto 96:487b796308b0 423 __IO uint32_t CR;
Kojto 96:487b796308b0 424 __IO uint32_t CSR;
Kojto 96:487b796308b0 425 } PWR_TypeDef;
Kojto 96:487b796308b0 426
Kojto 96:487b796308b0 427 /**
Kojto 96:487b796308b0 428 * @brief Reset and Clock Control
Kojto 96:487b796308b0 429 */
Kojto 96:487b796308b0 430
Kojto 96:487b796308b0 431 typedef struct
Kojto 96:487b796308b0 432 {
Kojto 96:487b796308b0 433 __IO uint32_t CR;
Kojto 96:487b796308b0 434 __IO uint32_t CFGR;
Kojto 96:487b796308b0 435 __IO uint32_t CIR;
Kojto 96:487b796308b0 436 __IO uint32_t APB2RSTR;
Kojto 96:487b796308b0 437 __IO uint32_t APB1RSTR;
Kojto 96:487b796308b0 438 __IO uint32_t AHBENR;
Kojto 96:487b796308b0 439 __IO uint32_t APB2ENR;
Kojto 96:487b796308b0 440 __IO uint32_t APB1ENR;
Kojto 96:487b796308b0 441 __IO uint32_t BDCR;
Kojto 96:487b796308b0 442 __IO uint32_t CSR;
Kojto 96:487b796308b0 443
Kojto 96:487b796308b0 444
Kojto 96:487b796308b0 445 } RCC_TypeDef;
Kojto 96:487b796308b0 446
Kojto 96:487b796308b0 447 /**
Kojto 96:487b796308b0 448 * @brief Real-Time Clock
Kojto 96:487b796308b0 449 */
Kojto 96:487b796308b0 450
Kojto 96:487b796308b0 451 typedef struct
Kojto 96:487b796308b0 452 {
Kojto 96:487b796308b0 453 __IO uint32_t CRH;
Kojto 96:487b796308b0 454 __IO uint32_t CRL;
Kojto 96:487b796308b0 455 __IO uint32_t PRLH;
Kojto 96:487b796308b0 456 __IO uint32_t PRLL;
Kojto 96:487b796308b0 457 __IO uint32_t DIVH;
Kojto 96:487b796308b0 458 __IO uint32_t DIVL;
Kojto 96:487b796308b0 459 __IO uint32_t CNTH;
Kojto 96:487b796308b0 460 __IO uint32_t CNTL;
Kojto 96:487b796308b0 461 __IO uint32_t ALRH;
Kojto 96:487b796308b0 462 __IO uint32_t ALRL;
Kojto 96:487b796308b0 463 } RTC_TypeDef;
Kojto 96:487b796308b0 464
Kojto 96:487b796308b0 465 /**
Kojto 96:487b796308b0 466 * @brief SD host Interface
Kojto 96:487b796308b0 467 */
Kojto 96:487b796308b0 468
Kojto 96:487b796308b0 469 typedef struct
Kojto 96:487b796308b0 470 {
Kojto 96:487b796308b0 471 __IO uint32_t POWER;
Kojto 96:487b796308b0 472 __IO uint32_t CLKCR;
Kojto 96:487b796308b0 473 __IO uint32_t ARG;
Kojto 96:487b796308b0 474 __IO uint32_t CMD;
Kojto 96:487b796308b0 475 __I uint32_t RESPCMD;
Kojto 96:487b796308b0 476 __I uint32_t RESP1;
Kojto 96:487b796308b0 477 __I uint32_t RESP2;
Kojto 96:487b796308b0 478 __I uint32_t RESP3;
Kojto 96:487b796308b0 479 __I uint32_t RESP4;
Kojto 96:487b796308b0 480 __IO uint32_t DTIMER;
Kojto 96:487b796308b0 481 __IO uint32_t DLEN;
Kojto 96:487b796308b0 482 __IO uint32_t DCTRL;
Kojto 96:487b796308b0 483 __I uint32_t DCOUNT;
Kojto 96:487b796308b0 484 __I uint32_t STA;
Kojto 96:487b796308b0 485 __IO uint32_t ICR;
Kojto 96:487b796308b0 486 __IO uint32_t MASK;
Kojto 96:487b796308b0 487 uint32_t RESERVED0[2];
Kojto 96:487b796308b0 488 __I uint32_t FIFOCNT;
Kojto 96:487b796308b0 489 uint32_t RESERVED1[13];
Kojto 96:487b796308b0 490 __IO uint32_t FIFO;
Kojto 96:487b796308b0 491 } SDIO_TypeDef;
Kojto 96:487b796308b0 492
Kojto 96:487b796308b0 493 /**
Kojto 96:487b796308b0 494 * @brief Serial Peripheral Interface
Kojto 96:487b796308b0 495 */
Kojto 96:487b796308b0 496
Kojto 96:487b796308b0 497 typedef struct
Kojto 96:487b796308b0 498 {
Kojto 96:487b796308b0 499 __IO uint32_t CR1;
Kojto 96:487b796308b0 500 __IO uint32_t CR2;
Kojto 96:487b796308b0 501 __IO uint32_t SR;
Kojto 96:487b796308b0 502 __IO uint32_t DR;
Kojto 96:487b796308b0 503 __IO uint32_t CRCPR;
Kojto 96:487b796308b0 504 __IO uint32_t RXCRCR;
Kojto 96:487b796308b0 505 __IO uint32_t TXCRCR;
Kojto 96:487b796308b0 506 __IO uint32_t I2SCFGR;
Kojto 96:487b796308b0 507 } SPI_TypeDef;
Kojto 96:487b796308b0 508
Kojto 96:487b796308b0 509 /**
Kojto 96:487b796308b0 510 * @brief TIM Timers
Kojto 96:487b796308b0 511 */
Kojto 96:487b796308b0 512 typedef struct
Kojto 96:487b796308b0 513 {
Kojto 96:487b796308b0 514 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 96:487b796308b0 515 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 96:487b796308b0 516 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
Kojto 96:487b796308b0 517 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 96:487b796308b0 518 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 96:487b796308b0 519 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 96:487b796308b0 520 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 96:487b796308b0 521 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 96:487b796308b0 522 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 96:487b796308b0 523 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 96:487b796308b0 524 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
Kojto 96:487b796308b0 525 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 96:487b796308b0 526 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 96:487b796308b0 527 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 96:487b796308b0 528 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 96:487b796308b0 529 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 96:487b796308b0 530 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 96:487b796308b0 531 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 96:487b796308b0 532 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 96:487b796308b0 533 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
Kojto 96:487b796308b0 534 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 96:487b796308b0 535 }TIM_TypeDef;
Kojto 96:487b796308b0 536
Kojto 96:487b796308b0 537
Kojto 96:487b796308b0 538 /**
Kojto 96:487b796308b0 539 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 96:487b796308b0 540 */
Kojto 96:487b796308b0 541
Kojto 96:487b796308b0 542 typedef struct
Kojto 96:487b796308b0 543 {
Kojto 96:487b796308b0 544 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
Kojto 96:487b796308b0 545 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
Kojto 96:487b796308b0 546 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
Kojto 96:487b796308b0 547 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
Kojto 96:487b796308b0 548 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
Kojto 96:487b796308b0 549 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
Kojto 96:487b796308b0 550 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
Kojto 96:487b796308b0 551 } USART_TypeDef;
Kojto 96:487b796308b0 552
Kojto 96:487b796308b0 553 /**
Kojto 96:487b796308b0 554 * @brief Universal Serial Bus Full Speed Device
Kojto 96:487b796308b0 555 */
Kojto 96:487b796308b0 556
Kojto 96:487b796308b0 557 typedef struct
Kojto 96:487b796308b0 558 {
Kojto 96:487b796308b0 559 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
Kojto 96:487b796308b0 560 __IO uint16_t RESERVED0; /*!< Reserved */
Kojto 96:487b796308b0 561 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
Kojto 96:487b796308b0 562 __IO uint16_t RESERVED1; /*!< Reserved */
Kojto 96:487b796308b0 563 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
Kojto 96:487b796308b0 564 __IO uint16_t RESERVED2; /*!< Reserved */
Kojto 96:487b796308b0 565 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
Kojto 96:487b796308b0 566 __IO uint16_t RESERVED3; /*!< Reserved */
Kojto 96:487b796308b0 567 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
Kojto 96:487b796308b0 568 __IO uint16_t RESERVED4; /*!< Reserved */
Kojto 96:487b796308b0 569 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
Kojto 96:487b796308b0 570 __IO uint16_t RESERVED5; /*!< Reserved */
Kojto 96:487b796308b0 571 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
Kojto 96:487b796308b0 572 __IO uint16_t RESERVED6; /*!< Reserved */
Kojto 96:487b796308b0 573 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
Kojto 96:487b796308b0 574 __IO uint16_t RESERVED7[17]; /*!< Reserved */
Kojto 96:487b796308b0 575 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
Kojto 96:487b796308b0 576 __IO uint16_t RESERVED8; /*!< Reserved */
Kojto 96:487b796308b0 577 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
Kojto 96:487b796308b0 578 __IO uint16_t RESERVED9; /*!< Reserved */
Kojto 96:487b796308b0 579 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
Kojto 96:487b796308b0 580 __IO uint16_t RESERVEDA; /*!< Reserved */
Kojto 96:487b796308b0 581 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
Kojto 96:487b796308b0 582 __IO uint16_t RESERVEDB; /*!< Reserved */
Kojto 96:487b796308b0 583 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
Kojto 96:487b796308b0 584 __IO uint16_t RESERVEDC; /*!< Reserved */
Kojto 96:487b796308b0 585 } USB_TypeDef;
Kojto 96:487b796308b0 586
Kojto 96:487b796308b0 587
Kojto 96:487b796308b0 588 /**
Kojto 96:487b796308b0 589 * @brief Window WATCHDOG
Kojto 96:487b796308b0 590 */
Kojto 96:487b796308b0 591
Kojto 96:487b796308b0 592 typedef struct
Kojto 96:487b796308b0 593 {
Kojto 96:487b796308b0 594 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 96:487b796308b0 595 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 96:487b796308b0 596 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 96:487b796308b0 597 } WWDG_TypeDef;
Kojto 96:487b796308b0 598
Kojto 96:487b796308b0 599 /**
Kojto 96:487b796308b0 600 * @}
Kojto 96:487b796308b0 601 */
Kojto 96:487b796308b0 602
Kojto 96:487b796308b0 603 /** @addtogroup Peripheral_memory_map
Kojto 96:487b796308b0 604 * @{
Kojto 96:487b796308b0 605 */
Kojto 96:487b796308b0 606
Kojto 96:487b796308b0 607
Kojto 96:487b796308b0 608 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
Kojto 96:487b796308b0 609 #define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
Kojto 96:487b796308b0 610 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
Kojto 96:487b796308b0 611 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
Kojto 96:487b796308b0 612
Kojto 96:487b796308b0 613 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
Kojto 96:487b796308b0 614 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
Kojto 96:487b796308b0 615
Kojto 96:487b796308b0 616
Kojto 96:487b796308b0 617 /*!< Peripheral memory map */
Kojto 96:487b796308b0 618 #define APB1PERIPH_BASE PERIPH_BASE
Kojto 96:487b796308b0 619 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
Kojto 96:487b796308b0 620 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
Kojto 96:487b796308b0 621
Kojto 96:487b796308b0 622 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
Kojto 96:487b796308b0 623 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
Kojto 96:487b796308b0 624 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
Kojto 96:487b796308b0 625 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
Kojto 96:487b796308b0 626 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
Kojto 96:487b796308b0 627 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
Kojto 96:487b796308b0 628 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
Kojto 96:487b796308b0 629 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
Kojto 96:487b796308b0 630 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
Kojto 96:487b796308b0 631 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
Kojto 96:487b796308b0 632 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
Kojto 96:487b796308b0 633 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
Kojto 96:487b796308b0 634 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
Kojto 96:487b796308b0 635 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
Kojto 96:487b796308b0 636 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
Kojto 96:487b796308b0 637 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
Kojto 96:487b796308b0 638 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
Kojto 96:487b796308b0 639 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
Kojto 96:487b796308b0 640 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
Kojto 96:487b796308b0 641 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
Kojto 96:487b796308b0 642 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
Kojto 96:487b796308b0 643 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
Kojto 96:487b796308b0 644 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
Kojto 96:487b796308b0 645 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
Kojto 96:487b796308b0 646 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
Kojto 96:487b796308b0 647 #define USART1_BASE (APB2PERIPH_BASE + 0x3800)
Kojto 96:487b796308b0 648
Kojto 96:487b796308b0 649 #define SDIO_BASE (PERIPH_BASE + 0x18000)
Kojto 96:487b796308b0 650
Kojto 96:487b796308b0 651 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
Kojto 96:487b796308b0 652 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
Kojto 96:487b796308b0 653 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
Kojto 96:487b796308b0 654 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
Kojto 96:487b796308b0 655 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
Kojto 96:487b796308b0 656 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
Kojto 96:487b796308b0 657 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
Kojto 96:487b796308b0 658 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
Kojto 96:487b796308b0 659 #define RCC_BASE (AHBPERIPH_BASE + 0x1000)
Kojto 96:487b796308b0 660 #define CRC_BASE (AHBPERIPH_BASE + 0x3000)
Kojto 96:487b796308b0 661
Kojto 96:487b796308b0 662 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
Kojto 96:487b796308b0 663 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
Kojto 96:487b796308b0 664
Kojto 96:487b796308b0 665
Kojto 96:487b796308b0 666
Kojto 96:487b796308b0 667 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
Kojto 96:487b796308b0 668
Kojto 96:487b796308b0 669 /* USB device FS */
Kojto 96:487b796308b0 670 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
Kojto 96:487b796308b0 671 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
Kojto 96:487b796308b0 672
Kojto 96:487b796308b0 673
Kojto 96:487b796308b0 674 /**
Kojto 96:487b796308b0 675 * @}
Kojto 96:487b796308b0 676 */
Kojto 96:487b796308b0 677
Kojto 96:487b796308b0 678 /** @addtogroup Peripheral_declaration
Kojto 96:487b796308b0 679 * @{
Kojto 96:487b796308b0 680 */
Kojto 96:487b796308b0 681
Kojto 96:487b796308b0 682 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 96:487b796308b0 683 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 96:487b796308b0 684 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Kojto 96:487b796308b0 685 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 96:487b796308b0 686 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 96:487b796308b0 687 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 96:487b796308b0 688 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 96:487b796308b0 689 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 96:487b796308b0 690 #define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto 96:487b796308b0 691 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 96:487b796308b0 692 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 96:487b796308b0 693 #define USB ((USB_TypeDef *) USB_BASE)
Kojto 96:487b796308b0 694 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
Kojto 96:487b796308b0 695 #define BKP ((BKP_TypeDef *) BKP_BASE)
Kojto 96:487b796308b0 696 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 96:487b796308b0 697 #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
Kojto 96:487b796308b0 698 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 96:487b796308b0 699 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 96:487b796308b0 700 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 96:487b796308b0 701 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 96:487b796308b0 702 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 96:487b796308b0 703 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto 96:487b796308b0 704 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 96:487b796308b0 705 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
Kojto 96:487b796308b0 706 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 96:487b796308b0 707 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 96:487b796308b0 708 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 96:487b796308b0 709 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
Kojto 96:487b796308b0 710 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 96:487b796308b0 711 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Kojto 96:487b796308b0 712 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Kojto 96:487b796308b0 713 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Kojto 96:487b796308b0 714 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Kojto 96:487b796308b0 715 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Kojto 96:487b796308b0 716 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
Kojto 96:487b796308b0 717 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
Kojto 96:487b796308b0 718 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 96:487b796308b0 719 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 96:487b796308b0 720 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 96:487b796308b0 721 #define OB ((OB_TypeDef *) OB_BASE)
Kojto 96:487b796308b0 722 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 96:487b796308b0 723
Kojto 96:487b796308b0 724
Kojto 96:487b796308b0 725 /**
Kojto 96:487b796308b0 726 * @}
Kojto 96:487b796308b0 727 */
Kojto 96:487b796308b0 728
Kojto 96:487b796308b0 729 /** @addtogroup Exported_constants
Kojto 96:487b796308b0 730 * @{
Kojto 96:487b796308b0 731 */
Kojto 96:487b796308b0 732
Kojto 96:487b796308b0 733 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 96:487b796308b0 734 * @{
Kojto 96:487b796308b0 735 */
Kojto 96:487b796308b0 736
Kojto 96:487b796308b0 737 /******************************************************************************/
Kojto 96:487b796308b0 738 /* Peripheral Registers_Bits_Definition */
Kojto 96:487b796308b0 739 /******************************************************************************/
Kojto 96:487b796308b0 740
Kojto 96:487b796308b0 741 /******************************************************************************/
Kojto 96:487b796308b0 742 /* */
Kojto 96:487b796308b0 743 /* CRC calculation unit (CRC) */
Kojto 96:487b796308b0 744 /* */
Kojto 96:487b796308b0 745 /******************************************************************************/
Kojto 96:487b796308b0 746
Kojto 96:487b796308b0 747 /******************* Bit definition for CRC_DR register *********************/
Kojto 96:487b796308b0 748 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
Kojto 96:487b796308b0 749
Kojto 96:487b796308b0 750 /******************* Bit definition for CRC_IDR register ********************/
Kojto 96:487b796308b0 751 #define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
Kojto 96:487b796308b0 752
Kojto 96:487b796308b0 753 /******************** Bit definition for CRC_CR register ********************/
Kojto 96:487b796308b0 754 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
Kojto 96:487b796308b0 755
Kojto 96:487b796308b0 756 /******************************************************************************/
Kojto 96:487b796308b0 757 /* */
Kojto 96:487b796308b0 758 /* Power Control */
Kojto 96:487b796308b0 759 /* */
Kojto 96:487b796308b0 760 /******************************************************************************/
Kojto 96:487b796308b0 761
Kojto 96:487b796308b0 762 /******************** Bit definition for PWR_CR register ********************/
Kojto 96:487b796308b0 763 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
Kojto 96:487b796308b0 764 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
Kojto 96:487b796308b0 765 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
Kojto 96:487b796308b0 766 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
Kojto 96:487b796308b0 767 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
Kojto 96:487b796308b0 768
Kojto 96:487b796308b0 769 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 96:487b796308b0 770 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 96:487b796308b0 771 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 96:487b796308b0 772 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Kojto 96:487b796308b0 773
Kojto 96:487b796308b0 774 /*!< PVD level configuration */
Kojto 96:487b796308b0 775 #define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
Kojto 96:487b796308b0 776 #define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
Kojto 96:487b796308b0 777 #define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
Kojto 96:487b796308b0 778 #define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
Kojto 96:487b796308b0 779 #define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
Kojto 96:487b796308b0 780 #define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
Kojto 96:487b796308b0 781 #define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
Kojto 96:487b796308b0 782 #define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
Kojto 96:487b796308b0 783
Kojto 96:487b796308b0 784 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
Kojto 96:487b796308b0 785
Kojto 96:487b796308b0 786
Kojto 96:487b796308b0 787 /******************* Bit definition for PWR_CSR register ********************/
Kojto 96:487b796308b0 788 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
Kojto 96:487b796308b0 789 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
Kojto 96:487b796308b0 790 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
Kojto 96:487b796308b0 791 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
Kojto 96:487b796308b0 792
Kojto 96:487b796308b0 793 /******************************************************************************/
Kojto 96:487b796308b0 794 /* */
Kojto 96:487b796308b0 795 /* Backup registers */
Kojto 96:487b796308b0 796 /* */
Kojto 96:487b796308b0 797 /******************************************************************************/
Kojto 96:487b796308b0 798
Kojto 96:487b796308b0 799 /******************* Bit definition for BKP_DR1 register ********************/
Kojto 96:487b796308b0 800 #define BKP_DR1_D ((uint32_t)0x0000FFFF) /*!< Backup data */
Kojto 96:487b796308b0 801
Kojto 96:487b796308b0 802 /******************* Bit definition for BKP_DR2 register ********************/
Kojto 96:487b796308b0 803 #define BKP_DR2_D ((uint32_t)0x0000FFFF) /*!< Backup data */
Kojto 96:487b796308b0 804
Kojto 96:487b796308b0 805 /******************* Bit definition for BKP_DR3 register ********************/
Kojto 96:487b796308b0 806 #define BKP_DR3_D ((uint32_t)0x0000FFFF) /*!< Backup data */
Kojto 96:487b796308b0 807
Kojto 96:487b796308b0 808 /******************* Bit definition for BKP_DR4 register ********************/
Kojto 96:487b796308b0 809 #define BKP_DR4_D ((uint32_t)0x0000FFFF) /*!< Backup data */
Kojto 96:487b796308b0 810
Kojto 96:487b796308b0 811 /******************* Bit definition for BKP_DR5 register ********************/
Kojto 96:487b796308b0 812 #define BKP_DR5_D ((uint32_t)0x0000FFFF) /*!< Backup data */
Kojto 96:487b796308b0 813
Kojto 96:487b796308b0 814 /******************* Bit definition for BKP_DR6 register ********************/
Kojto 96:487b796308b0 815 #define BKP_DR6_D ((uint32_t)0x0000FFFF) /*!< Backup data */
Kojto 96:487b796308b0 816
Kojto 96:487b796308b0 817 /******************* Bit definition for BKP_DR7 register ********************/
Kojto 96:487b796308b0 818 #define BKP_DR7_D ((uint32_t)0x0000FFFF) /*!< Backup data */
Kojto 96:487b796308b0 819
Kojto 96:487b796308b0 820 /******************* Bit definition for BKP_DR8 register ********************/
Kojto 96:487b796308b0 821 #define BKP_DR8_D ((uint32_t)0x0000FFFF) /*!< Backup data */
Kojto 96:487b796308b0 822
Kojto 96:487b796308b0 823 /******************* Bit definition for BKP_DR9 register ********************/
Kojto 96:487b796308b0 824 #define BKP_DR9_D ((uint32_t)0x0000FFFF) /*!< Backup data */
Kojto 96:487b796308b0 825
Kojto 96:487b796308b0 826 /******************* Bit definition for BKP_DR10 register *******************/
Kojto 96:487b796308b0 827 #define BKP_DR10_D ((uint32_t)0x0000FFFF) /*!< Backup data */
Kojto 96:487b796308b0 828
Kojto 96:487b796308b0 829 #define RTC_BKP_NUMBER 10
Kojto 96:487b796308b0 830
Kojto 96:487b796308b0 831 /****************** Bit definition for BKP_RTCCR register *******************/
Kojto 96:487b796308b0 832 #define BKP_RTCCR_CAL ((uint32_t)0x0000007F) /*!< Calibration value */
Kojto 96:487b796308b0 833 #define BKP_RTCCR_CCO ((uint32_t)0x00000080) /*!< Calibration Clock Output */
Kojto 96:487b796308b0 834 #define BKP_RTCCR_ASOE ((uint32_t)0x00000100) /*!< Alarm or Second Output Enable */
Kojto 96:487b796308b0 835 #define BKP_RTCCR_ASOS ((uint32_t)0x00000200) /*!< Alarm or Second Output Selection */
Kojto 96:487b796308b0 836
Kojto 96:487b796308b0 837 /******************** Bit definition for BKP_CR register ********************/
Kojto 96:487b796308b0 838 #define BKP_CR_TPE ((uint32_t)0x00000001) /*!< TAMPER pin enable */
Kojto 96:487b796308b0 839 #define BKP_CR_TPAL ((uint32_t)0x00000002) /*!< TAMPER pin active level */
Kojto 96:487b796308b0 840
Kojto 96:487b796308b0 841 /******************* Bit definition for BKP_CSR register ********************/
Kojto 96:487b796308b0 842 #define BKP_CSR_CTE ((uint32_t)0x00000001) /*!< Clear Tamper event */
Kojto 96:487b796308b0 843 #define BKP_CSR_CTI ((uint32_t)0x00000002) /*!< Clear Tamper Interrupt */
Kojto 96:487b796308b0 844 #define BKP_CSR_TPIE ((uint32_t)0x00000004) /*!< TAMPER Pin interrupt enable */
Kojto 96:487b796308b0 845 #define BKP_CSR_TEF ((uint32_t)0x00000100) /*!< Tamper Event Flag */
Kojto 96:487b796308b0 846 #define BKP_CSR_TIF ((uint32_t)0x00000200) /*!< Tamper Interrupt Flag */
Kojto 96:487b796308b0 847
Kojto 96:487b796308b0 848 /******************************************************************************/
Kojto 96:487b796308b0 849 /* */
Kojto 96:487b796308b0 850 /* Reset and Clock Control */
Kojto 96:487b796308b0 851 /* */
Kojto 96:487b796308b0 852 /******************************************************************************/
Kojto 96:487b796308b0 853
Kojto 96:487b796308b0 854 /******************** Bit definition for RCC_CR register ********************/
Kojto 96:487b796308b0 855 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
Kojto 96:487b796308b0 856 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
Kojto 96:487b796308b0 857 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
Kojto 96:487b796308b0 858 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
Kojto 96:487b796308b0 859 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
Kojto 96:487b796308b0 860 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
Kojto 96:487b796308b0 861 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
Kojto 96:487b796308b0 862 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
Kojto 96:487b796308b0 863 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
Kojto 96:487b796308b0 864 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
Kojto 96:487b796308b0 865
Kojto 96:487b796308b0 866
Kojto 96:487b796308b0 867 /******************* Bit definition for RCC_CFGR register *******************/
Kojto 96:487b796308b0 868 /*!< SW configuration */
Kojto 96:487b796308b0 869 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
Kojto 96:487b796308b0 870 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 871 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 872
Kojto 96:487b796308b0 873 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
Kojto 96:487b796308b0 874 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
Kojto 96:487b796308b0 875 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
Kojto 96:487b796308b0 876
Kojto 96:487b796308b0 877 /*!< SWS configuration */
Kojto 96:487b796308b0 878 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 96:487b796308b0 879 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 96:487b796308b0 880 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 96:487b796308b0 881
Kojto 96:487b796308b0 882 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
Kojto 96:487b796308b0 883 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
Kojto 96:487b796308b0 884 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
Kojto 96:487b796308b0 885
Kojto 96:487b796308b0 886 /*!< HPRE configuration */
Kojto 96:487b796308b0 887 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 96:487b796308b0 888 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 96:487b796308b0 889 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 96:487b796308b0 890 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Kojto 96:487b796308b0 891 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
Kojto 96:487b796308b0 892
Kojto 96:487b796308b0 893 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
Kojto 96:487b796308b0 894 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
Kojto 96:487b796308b0 895 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
Kojto 96:487b796308b0 896 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
Kojto 96:487b796308b0 897 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
Kojto 96:487b796308b0 898 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
Kojto 96:487b796308b0 899 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
Kojto 96:487b796308b0 900 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
Kojto 96:487b796308b0 901 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
Kojto 96:487b796308b0 902
Kojto 96:487b796308b0 903 /*!< PPRE1 configuration */
Kojto 96:487b796308b0 904 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
Kojto 96:487b796308b0 905 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 96:487b796308b0 906 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 96:487b796308b0 907 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 96:487b796308b0 908
Kojto 96:487b796308b0 909 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 96:487b796308b0 910 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
Kojto 96:487b796308b0 911 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
Kojto 96:487b796308b0 912 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
Kojto 96:487b796308b0 913 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
Kojto 96:487b796308b0 914
Kojto 96:487b796308b0 915 /*!< PPRE2 configuration */
Kojto 96:487b796308b0 916 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 96:487b796308b0 917 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
Kojto 96:487b796308b0 918 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
Kojto 96:487b796308b0 919 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
Kojto 96:487b796308b0 920
Kojto 96:487b796308b0 921 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 96:487b796308b0 922 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
Kojto 96:487b796308b0 923 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
Kojto 96:487b796308b0 924 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
Kojto 96:487b796308b0 925 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
Kojto 96:487b796308b0 926
Kojto 96:487b796308b0 927 /*!< ADCPPRE configuration */
Kojto 96:487b796308b0 928 #define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
Kojto 96:487b796308b0 929 #define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
Kojto 96:487b796308b0 930 #define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
Kojto 96:487b796308b0 931
Kojto 96:487b796308b0 932 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
Kojto 96:487b796308b0 933 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
Kojto 96:487b796308b0 934 #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
Kojto 96:487b796308b0 935 #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
Kojto 96:487b796308b0 936
Kojto 96:487b796308b0 937 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
Kojto 96:487b796308b0 938
Kojto 96:487b796308b0 939 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
Kojto 96:487b796308b0 940
Kojto 96:487b796308b0 941 /*!< PLLMUL configuration */
Kojto 96:487b796308b0 942 #define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
Kojto 96:487b796308b0 943 #define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 96:487b796308b0 944 #define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 96:487b796308b0 945 #define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
Kojto 96:487b796308b0 946 #define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
Kojto 96:487b796308b0 947
Kojto 96:487b796308b0 948 #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
Kojto 96:487b796308b0 949 #define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
Kojto 96:487b796308b0 950
Kojto 96:487b796308b0 951 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
Kojto 96:487b796308b0 952 #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
Kojto 96:487b796308b0 953 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
Kojto 96:487b796308b0 954 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
Kojto 96:487b796308b0 955 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
Kojto 96:487b796308b0 956 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
Kojto 96:487b796308b0 957 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
Kojto 96:487b796308b0 958 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
Kojto 96:487b796308b0 959 #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
Kojto 96:487b796308b0 960 #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
Kojto 96:487b796308b0 961 #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
Kojto 96:487b796308b0 962 #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
Kojto 96:487b796308b0 963 #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
Kojto 96:487b796308b0 964 #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
Kojto 96:487b796308b0 965 #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
Kojto 96:487b796308b0 966 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */
Kojto 96:487b796308b0 967
Kojto 96:487b796308b0 968 /*!< MCO configuration */
Kojto 96:487b796308b0 969 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
Kojto 96:487b796308b0 970 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 96:487b796308b0 971 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 96:487b796308b0 972 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Kojto 96:487b796308b0 973
Kojto 96:487b796308b0 974 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
Kojto 96:487b796308b0 975 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
Kojto 96:487b796308b0 976 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
Kojto 96:487b796308b0 977 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
Kojto 96:487b796308b0 978 #define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
Kojto 96:487b796308b0 979
Kojto 96:487b796308b0 980 /*!<****************** Bit definition for RCC_CIR register ********************/
Kojto 96:487b796308b0 981 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
Kojto 96:487b796308b0 982 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
Kojto 96:487b796308b0 983 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
Kojto 96:487b796308b0 984 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
Kojto 96:487b796308b0 985 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
Kojto 96:487b796308b0 986 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
Kojto 96:487b796308b0 987 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
Kojto 96:487b796308b0 988 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
Kojto 96:487b796308b0 989 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
Kojto 96:487b796308b0 990 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
Kojto 96:487b796308b0 991 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
Kojto 96:487b796308b0 992 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
Kojto 96:487b796308b0 993 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
Kojto 96:487b796308b0 994 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
Kojto 96:487b796308b0 995 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
Kojto 96:487b796308b0 996 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
Kojto 96:487b796308b0 997 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
Kojto 96:487b796308b0 998
Kojto 96:487b796308b0 999
Kojto 96:487b796308b0 1000 /***************** Bit definition for RCC_APB2RSTR register *****************/
Kojto 96:487b796308b0 1001 #define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
Kojto 96:487b796308b0 1002 #define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
Kojto 96:487b796308b0 1003 #define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
Kojto 96:487b796308b0 1004 #define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
Kojto 96:487b796308b0 1005 #define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
Kojto 96:487b796308b0 1006 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */
Kojto 96:487b796308b0 1007
Kojto 96:487b796308b0 1008 #define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */
Kojto 96:487b796308b0 1009
Kojto 96:487b796308b0 1010 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
Kojto 96:487b796308b0 1011 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
Kojto 96:487b796308b0 1012 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
Kojto 96:487b796308b0 1013
Kojto 96:487b796308b0 1014
Kojto 96:487b796308b0 1015 #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */
Kojto 96:487b796308b0 1016
Kojto 96:487b796308b0 1017
Kojto 96:487b796308b0 1018
Kojto 96:487b796308b0 1019
Kojto 96:487b796308b0 1020 /***************** Bit definition for RCC_APB1RSTR register *****************/
Kojto 96:487b796308b0 1021 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
Kojto 96:487b796308b0 1022 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
Kojto 96:487b796308b0 1023 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
Kojto 96:487b796308b0 1024 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
Kojto 96:487b796308b0 1025 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
Kojto 96:487b796308b0 1026
Kojto 96:487b796308b0 1027 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
Kojto 96:487b796308b0 1028
Kojto 96:487b796308b0 1029 #define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
Kojto 96:487b796308b0 1030 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
Kojto 96:487b796308b0 1031
Kojto 96:487b796308b0 1032 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
Kojto 96:487b796308b0 1033 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
Kojto 96:487b796308b0 1034 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
Kojto 96:487b796308b0 1035 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
Kojto 96:487b796308b0 1036
Kojto 96:487b796308b0 1037 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
Kojto 96:487b796308b0 1038
Kojto 96:487b796308b0 1039
Kojto 96:487b796308b0 1040
Kojto 96:487b796308b0 1041
Kojto 96:487b796308b0 1042
Kojto 96:487b796308b0 1043
Kojto 96:487b796308b0 1044 /****************** Bit definition for RCC_AHBENR register ******************/
Kojto 96:487b796308b0 1045 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
Kojto 96:487b796308b0 1046 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
Kojto 96:487b796308b0 1047 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
Kojto 96:487b796308b0 1048 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
Kojto 96:487b796308b0 1049
Kojto 96:487b796308b0 1050
Kojto 96:487b796308b0 1051
Kojto 96:487b796308b0 1052
Kojto 96:487b796308b0 1053 /****************** Bit definition for RCC_APB2ENR register *****************/
Kojto 96:487b796308b0 1054 #define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
Kojto 96:487b796308b0 1055 #define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
Kojto 96:487b796308b0 1056 #define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
Kojto 96:487b796308b0 1057 #define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
Kojto 96:487b796308b0 1058 #define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
Kojto 96:487b796308b0 1059 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */
Kojto 96:487b796308b0 1060
Kojto 96:487b796308b0 1061 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */
Kojto 96:487b796308b0 1062
Kojto 96:487b796308b0 1063 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
Kojto 96:487b796308b0 1064 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */
Kojto 96:487b796308b0 1065 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
Kojto 96:487b796308b0 1066
Kojto 96:487b796308b0 1067
Kojto 96:487b796308b0 1068 #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */
Kojto 96:487b796308b0 1069
Kojto 96:487b796308b0 1070
Kojto 96:487b796308b0 1071
Kojto 96:487b796308b0 1072
Kojto 96:487b796308b0 1073 /***************** Bit definition for RCC_APB1ENR register ******************/
Kojto 96:487b796308b0 1074 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
Kojto 96:487b796308b0 1075 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
Kojto 96:487b796308b0 1076 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
Kojto 96:487b796308b0 1077 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
Kojto 96:487b796308b0 1078 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
Kojto 96:487b796308b0 1079
Kojto 96:487b796308b0 1080 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
Kojto 96:487b796308b0 1081
Kojto 96:487b796308b0 1082 #define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
Kojto 96:487b796308b0 1083 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
Kojto 96:487b796308b0 1084
Kojto 96:487b796308b0 1085 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
Kojto 96:487b796308b0 1086 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
Kojto 96:487b796308b0 1087 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
Kojto 96:487b796308b0 1088 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
Kojto 96:487b796308b0 1089
Kojto 96:487b796308b0 1090 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
Kojto 96:487b796308b0 1091
Kojto 96:487b796308b0 1092
Kojto 96:487b796308b0 1093
Kojto 96:487b796308b0 1094
Kojto 96:487b796308b0 1095
Kojto 96:487b796308b0 1096
Kojto 96:487b796308b0 1097 /******************* Bit definition for RCC_BDCR register *******************/
Kojto 96:487b796308b0 1098 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
Kojto 96:487b796308b0 1099 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
Kojto 96:487b796308b0 1100 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
Kojto 96:487b796308b0 1101
Kojto 96:487b796308b0 1102 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
Kojto 96:487b796308b0 1103 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 96:487b796308b0 1104 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 96:487b796308b0 1105
Kojto 96:487b796308b0 1106 /*!< RTC congiguration */
Kojto 96:487b796308b0 1107 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
Kojto 96:487b796308b0 1108 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
Kojto 96:487b796308b0 1109 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
Kojto 96:487b796308b0 1110 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
Kojto 96:487b796308b0 1111
Kojto 96:487b796308b0 1112 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
Kojto 96:487b796308b0 1113 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
Kojto 96:487b796308b0 1114
Kojto 96:487b796308b0 1115 /******************* Bit definition for RCC_CSR register ********************/
Kojto 96:487b796308b0 1116 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
Kojto 96:487b796308b0 1117 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
Kojto 96:487b796308b0 1118 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
Kojto 96:487b796308b0 1119 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
Kojto 96:487b796308b0 1120 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
Kojto 96:487b796308b0 1121 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
Kojto 96:487b796308b0 1122 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
Kojto 96:487b796308b0 1123 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
Kojto 96:487b796308b0 1124 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
Kojto 96:487b796308b0 1125
Kojto 96:487b796308b0 1126
Kojto 96:487b796308b0 1127
Kojto 96:487b796308b0 1128 /******************************************************************************/
Kojto 96:487b796308b0 1129 /* */
Kojto 96:487b796308b0 1130 /* General Purpose and Alternate Function I/O */
Kojto 96:487b796308b0 1131 /* */
Kojto 96:487b796308b0 1132 /******************************************************************************/
Kojto 96:487b796308b0 1133
Kojto 96:487b796308b0 1134 /******************* Bit definition for GPIO_CRL register *******************/
Kojto 96:487b796308b0 1135 #define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
Kojto 96:487b796308b0 1136
Kojto 96:487b796308b0 1137 #define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
Kojto 96:487b796308b0 1138 #define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 1139 #define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 1140
Kojto 96:487b796308b0 1141 #define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
Kojto 96:487b796308b0 1142 #define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 96:487b796308b0 1143 #define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 96:487b796308b0 1144
Kojto 96:487b796308b0 1145 #define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
Kojto 96:487b796308b0 1146 #define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 96:487b796308b0 1147 #define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 96:487b796308b0 1148
Kojto 96:487b796308b0 1149 #define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
Kojto 96:487b796308b0 1150 #define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 1151 #define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 1152
Kojto 96:487b796308b0 1153 #define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
Kojto 96:487b796308b0 1154 #define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 96:487b796308b0 1155 #define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 96:487b796308b0 1156
Kojto 96:487b796308b0 1157 #define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
Kojto 96:487b796308b0 1158 #define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
Kojto 96:487b796308b0 1159 #define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
Kojto 96:487b796308b0 1160
Kojto 96:487b796308b0 1161 #define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
Kojto 96:487b796308b0 1162 #define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 96:487b796308b0 1163 #define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 96:487b796308b0 1164
Kojto 96:487b796308b0 1165 #define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
Kojto 96:487b796308b0 1166 #define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
Kojto 96:487b796308b0 1167 #define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
Kojto 96:487b796308b0 1168
Kojto 96:487b796308b0 1169 #define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
Kojto 96:487b796308b0 1170
Kojto 96:487b796308b0 1171 #define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
Kojto 96:487b796308b0 1172 #define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 96:487b796308b0 1173 #define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 96:487b796308b0 1174
Kojto 96:487b796308b0 1175 #define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
Kojto 96:487b796308b0 1176 #define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Kojto 96:487b796308b0 1177 #define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Kojto 96:487b796308b0 1178
Kojto 96:487b796308b0 1179 #define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
Kojto 96:487b796308b0 1180 #define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 1181 #define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 1182
Kojto 96:487b796308b0 1183 #define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
Kojto 96:487b796308b0 1184 #define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
Kojto 96:487b796308b0 1185 #define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
Kojto 96:487b796308b0 1186
Kojto 96:487b796308b0 1187 #define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
Kojto 96:487b796308b0 1188 #define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 96:487b796308b0 1189 #define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 96:487b796308b0 1190
Kojto 96:487b796308b0 1191 #define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
Kojto 96:487b796308b0 1192 #define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
Kojto 96:487b796308b0 1193 #define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
Kojto 96:487b796308b0 1194
Kojto 96:487b796308b0 1195 #define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
Kojto 96:487b796308b0 1196 #define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 96:487b796308b0 1197 #define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 96:487b796308b0 1198
Kojto 96:487b796308b0 1199 #define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
Kojto 96:487b796308b0 1200 #define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
Kojto 96:487b796308b0 1201 #define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
Kojto 96:487b796308b0 1202
Kojto 96:487b796308b0 1203 /******************* Bit definition for GPIO_CRH register *******************/
Kojto 96:487b796308b0 1204 #define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
Kojto 96:487b796308b0 1205
Kojto 96:487b796308b0 1206 #define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
Kojto 96:487b796308b0 1207 #define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 1208 #define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 1209
Kojto 96:487b796308b0 1210 #define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
Kojto 96:487b796308b0 1211 #define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 96:487b796308b0 1212 #define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 96:487b796308b0 1213
Kojto 96:487b796308b0 1214 #define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
Kojto 96:487b796308b0 1215 #define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 96:487b796308b0 1216 #define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 96:487b796308b0 1217
Kojto 96:487b796308b0 1218 #define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
Kojto 96:487b796308b0 1219 #define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 1220 #define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 1221
Kojto 96:487b796308b0 1222 #define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
Kojto 96:487b796308b0 1223 #define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 96:487b796308b0 1224 #define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 96:487b796308b0 1225
Kojto 96:487b796308b0 1226 #define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
Kojto 96:487b796308b0 1227 #define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
Kojto 96:487b796308b0 1228 #define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
Kojto 96:487b796308b0 1229
Kojto 96:487b796308b0 1230 #define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
Kojto 96:487b796308b0 1231 #define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 96:487b796308b0 1232 #define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 96:487b796308b0 1233
Kojto 96:487b796308b0 1234 #define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
Kojto 96:487b796308b0 1235 #define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
Kojto 96:487b796308b0 1236 #define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
Kojto 96:487b796308b0 1237
Kojto 96:487b796308b0 1238 #define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
Kojto 96:487b796308b0 1239
Kojto 96:487b796308b0 1240 #define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
Kojto 96:487b796308b0 1241 #define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 96:487b796308b0 1242 #define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 96:487b796308b0 1243
Kojto 96:487b796308b0 1244 #define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
Kojto 96:487b796308b0 1245 #define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Kojto 96:487b796308b0 1246 #define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Kojto 96:487b796308b0 1247
Kojto 96:487b796308b0 1248 #define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
Kojto 96:487b796308b0 1249 #define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 1250 #define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 1251
Kojto 96:487b796308b0 1252 #define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
Kojto 96:487b796308b0 1253 #define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
Kojto 96:487b796308b0 1254 #define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
Kojto 96:487b796308b0 1255
Kojto 96:487b796308b0 1256 #define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
Kojto 96:487b796308b0 1257 #define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 96:487b796308b0 1258 #define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 96:487b796308b0 1259
Kojto 96:487b796308b0 1260 #define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
Kojto 96:487b796308b0 1261 #define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
Kojto 96:487b796308b0 1262 #define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
Kojto 96:487b796308b0 1263
Kojto 96:487b796308b0 1264 #define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
Kojto 96:487b796308b0 1265 #define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 96:487b796308b0 1266 #define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 96:487b796308b0 1267
Kojto 96:487b796308b0 1268 #define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
Kojto 96:487b796308b0 1269 #define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
Kojto 96:487b796308b0 1270 #define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
Kojto 96:487b796308b0 1271
Kojto 96:487b796308b0 1272 /*!<****************** Bit definition for GPIO_IDR register *******************/
Kojto 96:487b796308b0 1273 #define GPIO_IDR_IDR0 ((uint32_t)0x0001) /*!< Port input data, bit 0 */
Kojto 96:487b796308b0 1274 #define GPIO_IDR_IDR1 ((uint32_t)0x0002) /*!< Port input data, bit 1 */
Kojto 96:487b796308b0 1275 #define GPIO_IDR_IDR2 ((uint32_t)0x0004) /*!< Port input data, bit 2 */
Kojto 96:487b796308b0 1276 #define GPIO_IDR_IDR3 ((uint32_t)0x0008) /*!< Port input data, bit 3 */
Kojto 96:487b796308b0 1277 #define GPIO_IDR_IDR4 ((uint32_t)0x0010) /*!< Port input data, bit 4 */
Kojto 96:487b796308b0 1278 #define GPIO_IDR_IDR5 ((uint32_t)0x0020) /*!< Port input data, bit 5 */
Kojto 96:487b796308b0 1279 #define GPIO_IDR_IDR6 ((uint32_t)0x0040) /*!< Port input data, bit 6 */
Kojto 96:487b796308b0 1280 #define GPIO_IDR_IDR7 ((uint32_t)0x0080) /*!< Port input data, bit 7 */
Kojto 96:487b796308b0 1281 #define GPIO_IDR_IDR8 ((uint32_t)0x0100) /*!< Port input data, bit 8 */
Kojto 96:487b796308b0 1282 #define GPIO_IDR_IDR9 ((uint32_t)0x0200) /*!< Port input data, bit 9 */
Kojto 96:487b796308b0 1283 #define GPIO_IDR_IDR10 ((uint32_t)0x0400) /*!< Port input data, bit 10 */
Kojto 96:487b796308b0 1284 #define GPIO_IDR_IDR11 ((uint32_t)0x0800) /*!< Port input data, bit 11 */
Kojto 96:487b796308b0 1285 #define GPIO_IDR_IDR12 ((uint32_t)0x1000) /*!< Port input data, bit 12 */
Kojto 96:487b796308b0 1286 #define GPIO_IDR_IDR13 ((uint32_t)0x2000) /*!< Port input data, bit 13 */
Kojto 96:487b796308b0 1287 #define GPIO_IDR_IDR14 ((uint32_t)0x4000) /*!< Port input data, bit 14 */
Kojto 96:487b796308b0 1288 #define GPIO_IDR_IDR15 ((uint32_t)0x8000) /*!< Port input data, bit 15 */
Kojto 96:487b796308b0 1289
Kojto 96:487b796308b0 1290 /******************* Bit definition for GPIO_ODR register *******************/
Kojto 96:487b796308b0 1291 #define GPIO_ODR_ODR0 ((uint32_t)0x0001) /*!< Port output data, bit 0 */
Kojto 96:487b796308b0 1292 #define GPIO_ODR_ODR1 ((uint32_t)0x0002) /*!< Port output data, bit 1 */
Kojto 96:487b796308b0 1293 #define GPIO_ODR_ODR2 ((uint32_t)0x0004) /*!< Port output data, bit 2 */
Kojto 96:487b796308b0 1294 #define GPIO_ODR_ODR3 ((uint32_t)0x0008) /*!< Port output data, bit 3 */
Kojto 96:487b796308b0 1295 #define GPIO_ODR_ODR4 ((uint32_t)0x0010) /*!< Port output data, bit 4 */
Kojto 96:487b796308b0 1296 #define GPIO_ODR_ODR5 ((uint32_t)0x0020) /*!< Port output data, bit 5 */
Kojto 96:487b796308b0 1297 #define GPIO_ODR_ODR6 ((uint32_t)0x0040) /*!< Port output data, bit 6 */
Kojto 96:487b796308b0 1298 #define GPIO_ODR_ODR7 ((uint32_t)0x0080) /*!< Port output data, bit 7 */
Kojto 96:487b796308b0 1299 #define GPIO_ODR_ODR8 ((uint32_t)0x0100) /*!< Port output data, bit 8 */
Kojto 96:487b796308b0 1300 #define GPIO_ODR_ODR9 ((uint32_t)0x0200) /*!< Port output data, bit 9 */
Kojto 96:487b796308b0 1301 #define GPIO_ODR_ODR10 ((uint32_t)0x0400) /*!< Port output data, bit 10 */
Kojto 96:487b796308b0 1302 #define GPIO_ODR_ODR11 ((uint32_t)0x0800) /*!< Port output data, bit 11 */
Kojto 96:487b796308b0 1303 #define GPIO_ODR_ODR12 ((uint32_t)0x1000) /*!< Port output data, bit 12 */
Kojto 96:487b796308b0 1304 #define GPIO_ODR_ODR13 ((uint32_t)0x2000) /*!< Port output data, bit 13 */
Kojto 96:487b796308b0 1305 #define GPIO_ODR_ODR14 ((uint32_t)0x4000) /*!< Port output data, bit 14 */
Kojto 96:487b796308b0 1306 #define GPIO_ODR_ODR15 ((uint32_t)0x8000) /*!< Port output data, bit 15 */
Kojto 96:487b796308b0 1307
Kojto 96:487b796308b0 1308 /****************** Bit definition for GPIO_BSRR register *******************/
Kojto 96:487b796308b0 1309 #define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
Kojto 96:487b796308b0 1310 #define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
Kojto 96:487b796308b0 1311 #define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
Kojto 96:487b796308b0 1312 #define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
Kojto 96:487b796308b0 1313 #define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
Kojto 96:487b796308b0 1314 #define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
Kojto 96:487b796308b0 1315 #define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
Kojto 96:487b796308b0 1316 #define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
Kojto 96:487b796308b0 1317 #define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
Kojto 96:487b796308b0 1318 #define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
Kojto 96:487b796308b0 1319 #define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
Kojto 96:487b796308b0 1320 #define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
Kojto 96:487b796308b0 1321 #define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
Kojto 96:487b796308b0 1322 #define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
Kojto 96:487b796308b0 1323 #define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
Kojto 96:487b796308b0 1324 #define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
Kojto 96:487b796308b0 1325
Kojto 96:487b796308b0 1326 #define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
Kojto 96:487b796308b0 1327 #define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
Kojto 96:487b796308b0 1328 #define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
Kojto 96:487b796308b0 1329 #define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
Kojto 96:487b796308b0 1330 #define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
Kojto 96:487b796308b0 1331 #define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
Kojto 96:487b796308b0 1332 #define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
Kojto 96:487b796308b0 1333 #define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
Kojto 96:487b796308b0 1334 #define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
Kojto 96:487b796308b0 1335 #define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
Kojto 96:487b796308b0 1336 #define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
Kojto 96:487b796308b0 1337 #define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
Kojto 96:487b796308b0 1338 #define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
Kojto 96:487b796308b0 1339 #define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
Kojto 96:487b796308b0 1340 #define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
Kojto 96:487b796308b0 1341 #define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
Kojto 96:487b796308b0 1342
Kojto 96:487b796308b0 1343 /******************* Bit definition for GPIO_BRR register *******************/
Kojto 96:487b796308b0 1344 #define GPIO_BRR_BR0 ((uint32_t)0x0001) /*!< Port x Reset bit 0 */
Kojto 96:487b796308b0 1345 #define GPIO_BRR_BR1 ((uint32_t)0x0002) /*!< Port x Reset bit 1 */
Kojto 96:487b796308b0 1346 #define GPIO_BRR_BR2 ((uint32_t)0x0004) /*!< Port x Reset bit 2 */
Kojto 96:487b796308b0 1347 #define GPIO_BRR_BR3 ((uint32_t)0x0008) /*!< Port x Reset bit 3 */
Kojto 96:487b796308b0 1348 #define GPIO_BRR_BR4 ((uint32_t)0x0010) /*!< Port x Reset bit 4 */
Kojto 96:487b796308b0 1349 #define GPIO_BRR_BR5 ((uint32_t)0x0020) /*!< Port x Reset bit 5 */
Kojto 96:487b796308b0 1350 #define GPIO_BRR_BR6 ((uint32_t)0x0040) /*!< Port x Reset bit 6 */
Kojto 96:487b796308b0 1351 #define GPIO_BRR_BR7 ((uint32_t)0x0080) /*!< Port x Reset bit 7 */
Kojto 96:487b796308b0 1352 #define GPIO_BRR_BR8 ((uint32_t)0x0100) /*!< Port x Reset bit 8 */
Kojto 96:487b796308b0 1353 #define GPIO_BRR_BR9 ((uint32_t)0x0200) /*!< Port x Reset bit 9 */
Kojto 96:487b796308b0 1354 #define GPIO_BRR_BR10 ((uint32_t)0x0400) /*!< Port x Reset bit 10 */
Kojto 96:487b796308b0 1355 #define GPIO_BRR_BR11 ((uint32_t)0x0800) /*!< Port x Reset bit 11 */
Kojto 96:487b796308b0 1356 #define GPIO_BRR_BR12 ((uint32_t)0x1000) /*!< Port x Reset bit 12 */
Kojto 96:487b796308b0 1357 #define GPIO_BRR_BR13 ((uint32_t)0x2000) /*!< Port x Reset bit 13 */
Kojto 96:487b796308b0 1358 #define GPIO_BRR_BR14 ((uint32_t)0x4000) /*!< Port x Reset bit 14 */
Kojto 96:487b796308b0 1359 #define GPIO_BRR_BR15 ((uint32_t)0x8000) /*!< Port x Reset bit 15 */
Kojto 96:487b796308b0 1360
Kojto 96:487b796308b0 1361 /****************** Bit definition for GPIO_LCKR register *******************/
Kojto 96:487b796308b0 1362 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
Kojto 96:487b796308b0 1363 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
Kojto 96:487b796308b0 1364 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
Kojto 96:487b796308b0 1365 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
Kojto 96:487b796308b0 1366 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
Kojto 96:487b796308b0 1367 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
Kojto 96:487b796308b0 1368 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
Kojto 96:487b796308b0 1369 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
Kojto 96:487b796308b0 1370 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
Kojto 96:487b796308b0 1371 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
Kojto 96:487b796308b0 1372 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
Kojto 96:487b796308b0 1373 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
Kojto 96:487b796308b0 1374 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
Kojto 96:487b796308b0 1375 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
Kojto 96:487b796308b0 1376 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
Kojto 96:487b796308b0 1377 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
Kojto 96:487b796308b0 1378 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
Kojto 96:487b796308b0 1379
Kojto 96:487b796308b0 1380 /*----------------------------------------------------------------------------*/
Kojto 96:487b796308b0 1381
Kojto 96:487b796308b0 1382 /****************** Bit definition for AFIO_EVCR register *******************/
Kojto 96:487b796308b0 1383 #define AFIO_EVCR_PIN ((uint32_t)0x0000000F) /*!< PIN[3:0] bits (Pin selection) */
Kojto 96:487b796308b0 1384 #define AFIO_EVCR_PIN_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 1385 #define AFIO_EVCR_PIN_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 1386 #define AFIO_EVCR_PIN_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 1387 #define AFIO_EVCR_PIN_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 96:487b796308b0 1388
Kojto 96:487b796308b0 1389 /*!< PIN configuration */
Kojto 96:487b796308b0 1390 #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
Kojto 96:487b796308b0 1391 #define AFIO_EVCR_PIN_PX1 ((uint32_t)0x00000001) /*!< Pin 1 selected */
Kojto 96:487b796308b0 1392 #define AFIO_EVCR_PIN_PX2 ((uint32_t)0x00000002) /*!< Pin 2 selected */
Kojto 96:487b796308b0 1393 #define AFIO_EVCR_PIN_PX3 ((uint32_t)0x00000003) /*!< Pin 3 selected */
Kojto 96:487b796308b0 1394 #define AFIO_EVCR_PIN_PX4 ((uint32_t)0x00000004) /*!< Pin 4 selected */
Kojto 96:487b796308b0 1395 #define AFIO_EVCR_PIN_PX5 ((uint32_t)0x00000005) /*!< Pin 5 selected */
Kojto 96:487b796308b0 1396 #define AFIO_EVCR_PIN_PX6 ((uint32_t)0x00000006) /*!< Pin 6 selected */
Kojto 96:487b796308b0 1397 #define AFIO_EVCR_PIN_PX7 ((uint32_t)0x00000007) /*!< Pin 7 selected */
Kojto 96:487b796308b0 1398 #define AFIO_EVCR_PIN_PX8 ((uint32_t)0x00000008) /*!< Pin 8 selected */
Kojto 96:487b796308b0 1399 #define AFIO_EVCR_PIN_PX9 ((uint32_t)0x00000009) /*!< Pin 9 selected */
Kojto 96:487b796308b0 1400 #define AFIO_EVCR_PIN_PX10 ((uint32_t)0x0000000A) /*!< Pin 10 selected */
Kojto 96:487b796308b0 1401 #define AFIO_EVCR_PIN_PX11 ((uint32_t)0x0000000B) /*!< Pin 11 selected */
Kojto 96:487b796308b0 1402 #define AFIO_EVCR_PIN_PX12 ((uint32_t)0x0000000C) /*!< Pin 12 selected */
Kojto 96:487b796308b0 1403 #define AFIO_EVCR_PIN_PX13 ((uint32_t)0x0000000D) /*!< Pin 13 selected */
Kojto 96:487b796308b0 1404 #define AFIO_EVCR_PIN_PX14 ((uint32_t)0x0000000E) /*!< Pin 14 selected */
Kojto 96:487b796308b0 1405 #define AFIO_EVCR_PIN_PX15 ((uint32_t)0x0000000F) /*!< Pin 15 selected */
Kojto 96:487b796308b0 1406
Kojto 96:487b796308b0 1407 #define AFIO_EVCR_PORT ((uint32_t)0x00000070) /*!< PORT[2:0] bits (Port selection) */
Kojto 96:487b796308b0 1408 #define AFIO_EVCR_PORT_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 96:487b796308b0 1409 #define AFIO_EVCR_PORT_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 96:487b796308b0 1410 #define AFIO_EVCR_PORT_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Kojto 96:487b796308b0 1411
Kojto 96:487b796308b0 1412 /*!< PORT configuration */
Kojto 96:487b796308b0 1413 #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
Kojto 96:487b796308b0 1414 #define AFIO_EVCR_PORT_PB ((uint32_t)0x00000010) /*!< Port B selected */
Kojto 96:487b796308b0 1415 #define AFIO_EVCR_PORT_PC ((uint32_t)0x00000020) /*!< Port C selected */
Kojto 96:487b796308b0 1416 #define AFIO_EVCR_PORT_PD ((uint32_t)0x00000030) /*!< Port D selected */
Kojto 96:487b796308b0 1417 #define AFIO_EVCR_PORT_PE ((uint32_t)0x00000040) /*!< Port E selected */
Kojto 96:487b796308b0 1418
Kojto 96:487b796308b0 1419 #define AFIO_EVCR_EVOE ((uint32_t)0x00000080) /*!< Event Output Enable */
Kojto 96:487b796308b0 1420
Kojto 96:487b796308b0 1421 /****************** Bit definition for AFIO_MAPR register *******************/
Kojto 96:487b796308b0 1422 #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
Kojto 96:487b796308b0 1423 #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
Kojto 96:487b796308b0 1424 #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
Kojto 96:487b796308b0 1425 #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
Kojto 96:487b796308b0 1426
Kojto 96:487b796308b0 1427 #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
Kojto 96:487b796308b0 1428 #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 96:487b796308b0 1429 #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 96:487b796308b0 1430
Kojto 96:487b796308b0 1431 /* USART3_REMAP configuration */
Kojto 96:487b796308b0 1432 #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
Kojto 96:487b796308b0 1433 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
Kojto 96:487b796308b0 1434 #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
Kojto 96:487b796308b0 1435
Kojto 96:487b796308b0 1436 #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
Kojto 96:487b796308b0 1437 #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Kojto 96:487b796308b0 1438 #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Kojto 96:487b796308b0 1439
Kojto 96:487b796308b0 1440 /*!< TIM1_REMAP configuration */
Kojto 96:487b796308b0 1441 #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
Kojto 96:487b796308b0 1442 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
Kojto 96:487b796308b0 1443 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
Kojto 96:487b796308b0 1444
Kojto 96:487b796308b0 1445 #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
Kojto 96:487b796308b0 1446 #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 96:487b796308b0 1447 #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 96:487b796308b0 1448
Kojto 96:487b796308b0 1449 /*!< TIM2_REMAP configuration */
Kojto 96:487b796308b0 1450 #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
Kojto 96:487b796308b0 1451 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
Kojto 96:487b796308b0 1452 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
Kojto 96:487b796308b0 1453 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
Kojto 96:487b796308b0 1454
Kojto 96:487b796308b0 1455 #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
Kojto 96:487b796308b0 1456 #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 1457 #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 1458
Kojto 96:487b796308b0 1459 /*!< TIM3_REMAP configuration */
Kojto 96:487b796308b0 1460 #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
Kojto 96:487b796308b0 1461 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
Kojto 96:487b796308b0 1462 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
Kojto 96:487b796308b0 1463
Kojto 96:487b796308b0 1464 #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */
Kojto 96:487b796308b0 1465
Kojto 96:487b796308b0 1466 #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
Kojto 96:487b796308b0 1467 #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */
Kojto 96:487b796308b0 1468 #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */
Kojto 96:487b796308b0 1469
Kojto 96:487b796308b0 1470 /*!< CAN_REMAP configuration */
Kojto 96:487b796308b0 1471 #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
Kojto 96:487b796308b0 1472 #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
Kojto 96:487b796308b0 1473 #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
Kojto 96:487b796308b0 1474
Kojto 96:487b796308b0 1475 #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
Kojto 96:487b796308b0 1476
Kojto 96:487b796308b0 1477 /*!< SWJ_CFG configuration */
Kojto 96:487b796308b0 1478 #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
Kojto 96:487b796308b0 1479 #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 96:487b796308b0 1480 #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 96:487b796308b0 1481 #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Kojto 96:487b796308b0 1482
Kojto 96:487b796308b0 1483 #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
Kojto 96:487b796308b0 1484 #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
Kojto 96:487b796308b0 1485 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
Kojto 96:487b796308b0 1486 #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
Kojto 96:487b796308b0 1487
Kojto 96:487b796308b0 1488
Kojto 96:487b796308b0 1489 /***************** Bit definition for AFIO_EXTICR1 register *****************/
Kojto 96:487b796308b0 1490 #define AFIO_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
Kojto 96:487b796308b0 1491 #define AFIO_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
Kojto 96:487b796308b0 1492 #define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
Kojto 96:487b796308b0 1493 #define AFIO_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
Kojto 96:487b796308b0 1494
Kojto 96:487b796308b0 1495 /*!< EXTI0 configuration */
Kojto 96:487b796308b0 1496 #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
Kojto 96:487b796308b0 1497 #define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
Kojto 96:487b796308b0 1498 #define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
Kojto 96:487b796308b0 1499 #define AFIO_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
Kojto 96:487b796308b0 1500 #define AFIO_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
Kojto 96:487b796308b0 1501 #define AFIO_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
Kojto 96:487b796308b0 1502 #define AFIO_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!< PG[0] pin */
Kojto 96:487b796308b0 1503
Kojto 96:487b796308b0 1504 /*!< EXTI1 configuration */
Kojto 96:487b796308b0 1505 #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
Kojto 96:487b796308b0 1506 #define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
Kojto 96:487b796308b0 1507 #define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
Kojto 96:487b796308b0 1508 #define AFIO_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
Kojto 96:487b796308b0 1509 #define AFIO_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
Kojto 96:487b796308b0 1510 #define AFIO_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
Kojto 96:487b796308b0 1511 #define AFIO_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!< PG[1] pin */
Kojto 96:487b796308b0 1512
Kojto 96:487b796308b0 1513 /*!< EXTI2 configuration */
Kojto 96:487b796308b0 1514 #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
Kojto 96:487b796308b0 1515 #define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
Kojto 96:487b796308b0 1516 #define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
Kojto 96:487b796308b0 1517 #define AFIO_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
Kojto 96:487b796308b0 1518 #define AFIO_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
Kojto 96:487b796308b0 1519 #define AFIO_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
Kojto 96:487b796308b0 1520 #define AFIO_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!< PG[2] pin */
Kojto 96:487b796308b0 1521
Kojto 96:487b796308b0 1522 /*!< EXTI3 configuration */
Kojto 96:487b796308b0 1523 #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
Kojto 96:487b796308b0 1524 #define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
Kojto 96:487b796308b0 1525 #define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
Kojto 96:487b796308b0 1526 #define AFIO_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
Kojto 96:487b796308b0 1527 #define AFIO_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
Kojto 96:487b796308b0 1528 #define AFIO_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
Kojto 96:487b796308b0 1529 #define AFIO_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!< PG[3] pin */
Kojto 96:487b796308b0 1530
Kojto 96:487b796308b0 1531 /***************** Bit definition for AFIO_EXTICR2 register *****************/
Kojto 96:487b796308b0 1532 #define AFIO_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
Kojto 96:487b796308b0 1533 #define AFIO_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
Kojto 96:487b796308b0 1534 #define AFIO_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
Kojto 96:487b796308b0 1535 #define AFIO_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
Kojto 96:487b796308b0 1536
Kojto 96:487b796308b0 1537 /*!< EXTI4 configuration */
Kojto 96:487b796308b0 1538 #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
Kojto 96:487b796308b0 1539 #define AFIO_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
Kojto 96:487b796308b0 1540 #define AFIO_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
Kojto 96:487b796308b0 1541 #define AFIO_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
Kojto 96:487b796308b0 1542 #define AFIO_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
Kojto 96:487b796308b0 1543 #define AFIO_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
Kojto 96:487b796308b0 1544 #define AFIO_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!< PG[4] pin */
Kojto 96:487b796308b0 1545
Kojto 96:487b796308b0 1546 /* EXTI5 configuration */
Kojto 96:487b796308b0 1547 #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
Kojto 96:487b796308b0 1548 #define AFIO_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
Kojto 96:487b796308b0 1549 #define AFIO_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
Kojto 96:487b796308b0 1550 #define AFIO_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
Kojto 96:487b796308b0 1551 #define AFIO_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
Kojto 96:487b796308b0 1552 #define AFIO_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
Kojto 96:487b796308b0 1553 #define AFIO_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!< PG[5] pin */
Kojto 96:487b796308b0 1554
Kojto 96:487b796308b0 1555 /*!< EXTI6 configuration */
Kojto 96:487b796308b0 1556 #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
Kojto 96:487b796308b0 1557 #define AFIO_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
Kojto 96:487b796308b0 1558 #define AFIO_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
Kojto 96:487b796308b0 1559 #define AFIO_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
Kojto 96:487b796308b0 1560 #define AFIO_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
Kojto 96:487b796308b0 1561 #define AFIO_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
Kojto 96:487b796308b0 1562 #define AFIO_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!< PG[6] pin */
Kojto 96:487b796308b0 1563
Kojto 96:487b796308b0 1564 /*!< EXTI7 configuration */
Kojto 96:487b796308b0 1565 #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
Kojto 96:487b796308b0 1566 #define AFIO_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
Kojto 96:487b796308b0 1567 #define AFIO_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
Kojto 96:487b796308b0 1568 #define AFIO_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
Kojto 96:487b796308b0 1569 #define AFIO_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
Kojto 96:487b796308b0 1570 #define AFIO_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
Kojto 96:487b796308b0 1571 #define AFIO_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!< PG[7] pin */
Kojto 96:487b796308b0 1572
Kojto 96:487b796308b0 1573 /***************** Bit definition for AFIO_EXTICR3 register *****************/
Kojto 96:487b796308b0 1574 #define AFIO_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
Kojto 96:487b796308b0 1575 #define AFIO_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
Kojto 96:487b796308b0 1576 #define AFIO_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
Kojto 96:487b796308b0 1577 #define AFIO_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
Kojto 96:487b796308b0 1578
Kojto 96:487b796308b0 1579 /*!< EXTI8 configuration */
Kojto 96:487b796308b0 1580 #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
Kojto 96:487b796308b0 1581 #define AFIO_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
Kojto 96:487b796308b0 1582 #define AFIO_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
Kojto 96:487b796308b0 1583 #define AFIO_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
Kojto 96:487b796308b0 1584 #define AFIO_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
Kojto 96:487b796308b0 1585 #define AFIO_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
Kojto 96:487b796308b0 1586 #define AFIO_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!< PG[8] pin */
Kojto 96:487b796308b0 1587
Kojto 96:487b796308b0 1588 /*!< EXTI9 configuration */
Kojto 96:487b796308b0 1589 #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
Kojto 96:487b796308b0 1590 #define AFIO_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
Kojto 96:487b796308b0 1591 #define AFIO_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
Kojto 96:487b796308b0 1592 #define AFIO_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
Kojto 96:487b796308b0 1593 #define AFIO_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
Kojto 96:487b796308b0 1594 #define AFIO_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
Kojto 96:487b796308b0 1595 #define AFIO_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!< PG[9] pin */
Kojto 96:487b796308b0 1596
Kojto 96:487b796308b0 1597 /*!< EXTI10 configuration */
Kojto 96:487b796308b0 1598 #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
Kojto 96:487b796308b0 1599 #define AFIO_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
Kojto 96:487b796308b0 1600 #define AFIO_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
Kojto 96:487b796308b0 1601 #define AFIO_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
Kojto 96:487b796308b0 1602 #define AFIO_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
Kojto 96:487b796308b0 1603 #define AFIO_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
Kojto 96:487b796308b0 1604 #define AFIO_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!< PG[10] pin */
Kojto 96:487b796308b0 1605
Kojto 96:487b796308b0 1606 /*!< EXTI11 configuration */
Kojto 96:487b796308b0 1607 #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
Kojto 96:487b796308b0 1608 #define AFIO_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
Kojto 96:487b796308b0 1609 #define AFIO_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
Kojto 96:487b796308b0 1610 #define AFIO_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
Kojto 96:487b796308b0 1611 #define AFIO_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
Kojto 96:487b796308b0 1612 #define AFIO_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
Kojto 96:487b796308b0 1613 #define AFIO_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!< PG[11] pin */
Kojto 96:487b796308b0 1614
Kojto 96:487b796308b0 1615 /***************** Bit definition for AFIO_EXTICR4 register *****************/
Kojto 96:487b796308b0 1616 #define AFIO_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
Kojto 96:487b796308b0 1617 #define AFIO_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
Kojto 96:487b796308b0 1618 #define AFIO_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
Kojto 96:487b796308b0 1619 #define AFIO_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
Kojto 96:487b796308b0 1620
Kojto 96:487b796308b0 1621 /* EXTI12 configuration */
Kojto 96:487b796308b0 1622 #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
Kojto 96:487b796308b0 1623 #define AFIO_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
Kojto 96:487b796308b0 1624 #define AFIO_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
Kojto 96:487b796308b0 1625 #define AFIO_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
Kojto 96:487b796308b0 1626 #define AFIO_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
Kojto 96:487b796308b0 1627 #define AFIO_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
Kojto 96:487b796308b0 1628 #define AFIO_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!< PG[12] pin */
Kojto 96:487b796308b0 1629
Kojto 96:487b796308b0 1630 /* EXTI13 configuration */
Kojto 96:487b796308b0 1631 #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
Kojto 96:487b796308b0 1632 #define AFIO_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
Kojto 96:487b796308b0 1633 #define AFIO_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
Kojto 96:487b796308b0 1634 #define AFIO_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
Kojto 96:487b796308b0 1635 #define AFIO_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
Kojto 96:487b796308b0 1636 #define AFIO_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
Kojto 96:487b796308b0 1637 #define AFIO_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!< PG[13] pin */
Kojto 96:487b796308b0 1638
Kojto 96:487b796308b0 1639 /*!< EXTI14 configuration */
Kojto 96:487b796308b0 1640 #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
Kojto 96:487b796308b0 1641 #define AFIO_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
Kojto 96:487b796308b0 1642 #define AFIO_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
Kojto 96:487b796308b0 1643 #define AFIO_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
Kojto 96:487b796308b0 1644 #define AFIO_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
Kojto 96:487b796308b0 1645 #define AFIO_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
Kojto 96:487b796308b0 1646 #define AFIO_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!< PG[14] pin */
Kojto 96:487b796308b0 1647
Kojto 96:487b796308b0 1648 /*!< EXTI15 configuration */
Kojto 96:487b796308b0 1649 #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
Kojto 96:487b796308b0 1650 #define AFIO_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
Kojto 96:487b796308b0 1651 #define AFIO_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
Kojto 96:487b796308b0 1652 #define AFIO_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
Kojto 96:487b796308b0 1653 #define AFIO_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
Kojto 96:487b796308b0 1654 #define AFIO_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
Kojto 96:487b796308b0 1655 #define AFIO_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!< PG[15] pin */
Kojto 96:487b796308b0 1656
Kojto 96:487b796308b0 1657 /****************** Bit definition for AFIO_MAPR2 register ******************/
Kojto 96:487b796308b0 1658
Kojto 96:487b796308b0 1659
Kojto 96:487b796308b0 1660
Kojto 96:487b796308b0 1661 /******************************************************************************/
Kojto 96:487b796308b0 1662 /* */
Kojto 96:487b796308b0 1663 /* SystemTick */
Kojto 96:487b796308b0 1664 /* */
Kojto 96:487b796308b0 1665 /******************************************************************************/
Kojto 96:487b796308b0 1666
Kojto 96:487b796308b0 1667 /***************** Bit definition for SysTick_CTRL register *****************/
Kojto 96:487b796308b0 1668 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
Kojto 96:487b796308b0 1669 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
Kojto 96:487b796308b0 1670 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
Kojto 96:487b796308b0 1671 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
Kojto 96:487b796308b0 1672
Kojto 96:487b796308b0 1673 /***************** Bit definition for SysTick_LOAD register *****************/
Kojto 96:487b796308b0 1674 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
Kojto 96:487b796308b0 1675
Kojto 96:487b796308b0 1676 /***************** Bit definition for SysTick_VAL register ******************/
Kojto 96:487b796308b0 1677 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
Kojto 96:487b796308b0 1678
Kojto 96:487b796308b0 1679 /***************** Bit definition for SysTick_CALIB register ****************/
Kojto 96:487b796308b0 1680 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
Kojto 96:487b796308b0 1681 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
Kojto 96:487b796308b0 1682 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
Kojto 96:487b796308b0 1683
Kojto 96:487b796308b0 1684 /******************************************************************************/
Kojto 96:487b796308b0 1685 /* */
Kojto 96:487b796308b0 1686 /* Nested Vectored Interrupt Controller */
Kojto 96:487b796308b0 1687 /* */
Kojto 96:487b796308b0 1688 /******************************************************************************/
Kojto 96:487b796308b0 1689
Kojto 96:487b796308b0 1690 /****************** Bit definition for NVIC_ISER register *******************/
Kojto 96:487b796308b0 1691 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
Kojto 96:487b796308b0 1692 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
Kojto 96:487b796308b0 1693 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
Kojto 96:487b796308b0 1694 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
Kojto 96:487b796308b0 1695 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
Kojto 96:487b796308b0 1696 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
Kojto 96:487b796308b0 1697 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
Kojto 96:487b796308b0 1698 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
Kojto 96:487b796308b0 1699 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
Kojto 96:487b796308b0 1700 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
Kojto 96:487b796308b0 1701 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
Kojto 96:487b796308b0 1702 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
Kojto 96:487b796308b0 1703 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
Kojto 96:487b796308b0 1704 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
Kojto 96:487b796308b0 1705 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
Kojto 96:487b796308b0 1706 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
Kojto 96:487b796308b0 1707 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
Kojto 96:487b796308b0 1708 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
Kojto 96:487b796308b0 1709 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
Kojto 96:487b796308b0 1710 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
Kojto 96:487b796308b0 1711 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
Kojto 96:487b796308b0 1712 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
Kojto 96:487b796308b0 1713 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
Kojto 96:487b796308b0 1714 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
Kojto 96:487b796308b0 1715 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
Kojto 96:487b796308b0 1716 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
Kojto 96:487b796308b0 1717 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
Kojto 96:487b796308b0 1718 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
Kojto 96:487b796308b0 1719 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
Kojto 96:487b796308b0 1720 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
Kojto 96:487b796308b0 1721 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
Kojto 96:487b796308b0 1722 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
Kojto 96:487b796308b0 1723 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
Kojto 96:487b796308b0 1724
Kojto 96:487b796308b0 1725 /****************** Bit definition for NVIC_ICER register *******************/
Kojto 96:487b796308b0 1726 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
Kojto 96:487b796308b0 1727 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
Kojto 96:487b796308b0 1728 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
Kojto 96:487b796308b0 1729 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
Kojto 96:487b796308b0 1730 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
Kojto 96:487b796308b0 1731 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
Kojto 96:487b796308b0 1732 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
Kojto 96:487b796308b0 1733 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
Kojto 96:487b796308b0 1734 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
Kojto 96:487b796308b0 1735 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
Kojto 96:487b796308b0 1736 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
Kojto 96:487b796308b0 1737 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
Kojto 96:487b796308b0 1738 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
Kojto 96:487b796308b0 1739 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
Kojto 96:487b796308b0 1740 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
Kojto 96:487b796308b0 1741 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
Kojto 96:487b796308b0 1742 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
Kojto 96:487b796308b0 1743 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
Kojto 96:487b796308b0 1744 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
Kojto 96:487b796308b0 1745 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
Kojto 96:487b796308b0 1746 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
Kojto 96:487b796308b0 1747 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
Kojto 96:487b796308b0 1748 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
Kojto 96:487b796308b0 1749 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
Kojto 96:487b796308b0 1750 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
Kojto 96:487b796308b0 1751 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
Kojto 96:487b796308b0 1752 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
Kojto 96:487b796308b0 1753 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
Kojto 96:487b796308b0 1754 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
Kojto 96:487b796308b0 1755 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
Kojto 96:487b796308b0 1756 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
Kojto 96:487b796308b0 1757 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
Kojto 96:487b796308b0 1758 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
Kojto 96:487b796308b0 1759
Kojto 96:487b796308b0 1760 /****************** Bit definition for NVIC_ISPR register *******************/
Kojto 96:487b796308b0 1761 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
Kojto 96:487b796308b0 1762 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
Kojto 96:487b796308b0 1763 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
Kojto 96:487b796308b0 1764 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
Kojto 96:487b796308b0 1765 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
Kojto 96:487b796308b0 1766 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
Kojto 96:487b796308b0 1767 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
Kojto 96:487b796308b0 1768 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
Kojto 96:487b796308b0 1769 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
Kojto 96:487b796308b0 1770 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
Kojto 96:487b796308b0 1771 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
Kojto 96:487b796308b0 1772 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
Kojto 96:487b796308b0 1773 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
Kojto 96:487b796308b0 1774 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
Kojto 96:487b796308b0 1775 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
Kojto 96:487b796308b0 1776 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
Kojto 96:487b796308b0 1777 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
Kojto 96:487b796308b0 1778 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
Kojto 96:487b796308b0 1779 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
Kojto 96:487b796308b0 1780 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
Kojto 96:487b796308b0 1781 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
Kojto 96:487b796308b0 1782 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
Kojto 96:487b796308b0 1783 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
Kojto 96:487b796308b0 1784 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
Kojto 96:487b796308b0 1785 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
Kojto 96:487b796308b0 1786 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
Kojto 96:487b796308b0 1787 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
Kojto 96:487b796308b0 1788 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
Kojto 96:487b796308b0 1789 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
Kojto 96:487b796308b0 1790 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
Kojto 96:487b796308b0 1791 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
Kojto 96:487b796308b0 1792 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
Kojto 96:487b796308b0 1793 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
Kojto 96:487b796308b0 1794
Kojto 96:487b796308b0 1795 /****************** Bit definition for NVIC_ICPR register *******************/
Kojto 96:487b796308b0 1796 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
Kojto 96:487b796308b0 1797 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
Kojto 96:487b796308b0 1798 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
Kojto 96:487b796308b0 1799 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
Kojto 96:487b796308b0 1800 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
Kojto 96:487b796308b0 1801 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
Kojto 96:487b796308b0 1802 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
Kojto 96:487b796308b0 1803 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
Kojto 96:487b796308b0 1804 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
Kojto 96:487b796308b0 1805 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
Kojto 96:487b796308b0 1806 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
Kojto 96:487b796308b0 1807 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
Kojto 96:487b796308b0 1808 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
Kojto 96:487b796308b0 1809 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
Kojto 96:487b796308b0 1810 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
Kojto 96:487b796308b0 1811 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
Kojto 96:487b796308b0 1812 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
Kojto 96:487b796308b0 1813 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
Kojto 96:487b796308b0 1814 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
Kojto 96:487b796308b0 1815 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
Kojto 96:487b796308b0 1816 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
Kojto 96:487b796308b0 1817 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
Kojto 96:487b796308b0 1818 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
Kojto 96:487b796308b0 1819 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
Kojto 96:487b796308b0 1820 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
Kojto 96:487b796308b0 1821 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
Kojto 96:487b796308b0 1822 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
Kojto 96:487b796308b0 1823 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
Kojto 96:487b796308b0 1824 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
Kojto 96:487b796308b0 1825 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
Kojto 96:487b796308b0 1826 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
Kojto 96:487b796308b0 1827 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
Kojto 96:487b796308b0 1828 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
Kojto 96:487b796308b0 1829
Kojto 96:487b796308b0 1830 /****************** Bit definition for NVIC_IABR register *******************/
Kojto 96:487b796308b0 1831 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
Kojto 96:487b796308b0 1832 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
Kojto 96:487b796308b0 1833 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
Kojto 96:487b796308b0 1834 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
Kojto 96:487b796308b0 1835 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
Kojto 96:487b796308b0 1836 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
Kojto 96:487b796308b0 1837 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
Kojto 96:487b796308b0 1838 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
Kojto 96:487b796308b0 1839 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
Kojto 96:487b796308b0 1840 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
Kojto 96:487b796308b0 1841 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
Kojto 96:487b796308b0 1842 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
Kojto 96:487b796308b0 1843 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
Kojto 96:487b796308b0 1844 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
Kojto 96:487b796308b0 1845 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
Kojto 96:487b796308b0 1846 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
Kojto 96:487b796308b0 1847 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
Kojto 96:487b796308b0 1848 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
Kojto 96:487b796308b0 1849 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
Kojto 96:487b796308b0 1850 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
Kojto 96:487b796308b0 1851 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
Kojto 96:487b796308b0 1852 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
Kojto 96:487b796308b0 1853 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
Kojto 96:487b796308b0 1854 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
Kojto 96:487b796308b0 1855 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
Kojto 96:487b796308b0 1856 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
Kojto 96:487b796308b0 1857 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
Kojto 96:487b796308b0 1858 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
Kojto 96:487b796308b0 1859 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
Kojto 96:487b796308b0 1860 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
Kojto 96:487b796308b0 1861 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
Kojto 96:487b796308b0 1862 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
Kojto 96:487b796308b0 1863 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
Kojto 96:487b796308b0 1864
Kojto 96:487b796308b0 1865 /****************** Bit definition for NVIC_PRI0 register *******************/
Kojto 96:487b796308b0 1866 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
Kojto 96:487b796308b0 1867 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
Kojto 96:487b796308b0 1868 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
Kojto 96:487b796308b0 1869 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
Kojto 96:487b796308b0 1870
Kojto 96:487b796308b0 1871 /****************** Bit definition for NVIC_PRI1 register *******************/
Kojto 96:487b796308b0 1872 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
Kojto 96:487b796308b0 1873 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
Kojto 96:487b796308b0 1874 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
Kojto 96:487b796308b0 1875 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
Kojto 96:487b796308b0 1876
Kojto 96:487b796308b0 1877 /****************** Bit definition for NVIC_PRI2 register *******************/
Kojto 96:487b796308b0 1878 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
Kojto 96:487b796308b0 1879 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
Kojto 96:487b796308b0 1880 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
Kojto 96:487b796308b0 1881 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
Kojto 96:487b796308b0 1882
Kojto 96:487b796308b0 1883 /****************** Bit definition for NVIC_PRI3 register *******************/
Kojto 96:487b796308b0 1884 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
Kojto 96:487b796308b0 1885 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
Kojto 96:487b796308b0 1886 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
Kojto 96:487b796308b0 1887 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
Kojto 96:487b796308b0 1888
Kojto 96:487b796308b0 1889 /****************** Bit definition for NVIC_PRI4 register *******************/
Kojto 96:487b796308b0 1890 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
Kojto 96:487b796308b0 1891 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
Kojto 96:487b796308b0 1892 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
Kojto 96:487b796308b0 1893 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
Kojto 96:487b796308b0 1894
Kojto 96:487b796308b0 1895 /****************** Bit definition for NVIC_PRI5 register *******************/
Kojto 96:487b796308b0 1896 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
Kojto 96:487b796308b0 1897 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
Kojto 96:487b796308b0 1898 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
Kojto 96:487b796308b0 1899 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
Kojto 96:487b796308b0 1900
Kojto 96:487b796308b0 1901 /****************** Bit definition for NVIC_PRI6 register *******************/
Kojto 96:487b796308b0 1902 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
Kojto 96:487b796308b0 1903 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
Kojto 96:487b796308b0 1904 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
Kojto 96:487b796308b0 1905 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
Kojto 96:487b796308b0 1906
Kojto 96:487b796308b0 1907 /****************** Bit definition for NVIC_PRI7 register *******************/
Kojto 96:487b796308b0 1908 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
Kojto 96:487b796308b0 1909 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
Kojto 96:487b796308b0 1910 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
Kojto 96:487b796308b0 1911 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
Kojto 96:487b796308b0 1912
Kojto 96:487b796308b0 1913 /****************** Bit definition for SCB_CPUID register *******************/
Kojto 96:487b796308b0 1914 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
Kojto 96:487b796308b0 1915 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
Kojto 96:487b796308b0 1916 #define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
Kojto 96:487b796308b0 1917 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
Kojto 96:487b796308b0 1918 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
Kojto 96:487b796308b0 1919
Kojto 96:487b796308b0 1920 /******************* Bit definition for SCB_ICSR register *******************/
Kojto 96:487b796308b0 1921 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
Kojto 96:487b796308b0 1922 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
Kojto 96:487b796308b0 1923 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
Kojto 96:487b796308b0 1924 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
Kojto 96:487b796308b0 1925 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
Kojto 96:487b796308b0 1926 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
Kojto 96:487b796308b0 1927 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
Kojto 96:487b796308b0 1928 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
Kojto 96:487b796308b0 1929 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
Kojto 96:487b796308b0 1930 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
Kojto 96:487b796308b0 1931
Kojto 96:487b796308b0 1932 /******************* Bit definition for SCB_VTOR register *******************/
Kojto 96:487b796308b0 1933 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
Kojto 96:487b796308b0 1934 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
Kojto 96:487b796308b0 1935
Kojto 96:487b796308b0 1936 /*!<***************** Bit definition for SCB_AIRCR register *******************/
Kojto 96:487b796308b0 1937 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
Kojto 96:487b796308b0 1938 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
Kojto 96:487b796308b0 1939 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
Kojto 96:487b796308b0 1940
Kojto 96:487b796308b0 1941 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
Kojto 96:487b796308b0 1942 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 96:487b796308b0 1943 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 96:487b796308b0 1944 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 96:487b796308b0 1945
Kojto 96:487b796308b0 1946 /* prority group configuration */
Kojto 96:487b796308b0 1947 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
Kojto 96:487b796308b0 1948 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
Kojto 96:487b796308b0 1949 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
Kojto 96:487b796308b0 1950 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
Kojto 96:487b796308b0 1951 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
Kojto 96:487b796308b0 1952 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
Kojto 96:487b796308b0 1953 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
Kojto 96:487b796308b0 1954 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
Kojto 96:487b796308b0 1955
Kojto 96:487b796308b0 1956 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
Kojto 96:487b796308b0 1957 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
Kojto 96:487b796308b0 1958
Kojto 96:487b796308b0 1959 /******************* Bit definition for SCB_SCR register ********************/
Kojto 96:487b796308b0 1960 #define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
Kojto 96:487b796308b0 1961 #define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
Kojto 96:487b796308b0 1962 #define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
Kojto 96:487b796308b0 1963
Kojto 96:487b796308b0 1964 /******************** Bit definition for SCB_CCR register *******************/
Kojto 96:487b796308b0 1965 #define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
Kojto 96:487b796308b0 1966 #define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
Kojto 96:487b796308b0 1967 #define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
Kojto 96:487b796308b0 1968 #define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
Kojto 96:487b796308b0 1969 #define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
Kojto 96:487b796308b0 1970 #define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
Kojto 96:487b796308b0 1971
Kojto 96:487b796308b0 1972 /******************* Bit definition for SCB_SHPR register ********************/
Kojto 96:487b796308b0 1973 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
Kojto 96:487b796308b0 1974 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
Kojto 96:487b796308b0 1975 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
Kojto 96:487b796308b0 1976 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
Kojto 96:487b796308b0 1977
Kojto 96:487b796308b0 1978 /****************** Bit definition for SCB_SHCSR register *******************/
Kojto 96:487b796308b0 1979 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
Kojto 96:487b796308b0 1980 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
Kojto 96:487b796308b0 1981 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
Kojto 96:487b796308b0 1982 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
Kojto 96:487b796308b0 1983 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
Kojto 96:487b796308b0 1984 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
Kojto 96:487b796308b0 1985 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
Kojto 96:487b796308b0 1986 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
Kojto 96:487b796308b0 1987 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
Kojto 96:487b796308b0 1988 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
Kojto 96:487b796308b0 1989 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
Kojto 96:487b796308b0 1990 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
Kojto 96:487b796308b0 1991 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
Kojto 96:487b796308b0 1992 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
Kojto 96:487b796308b0 1993
Kojto 96:487b796308b0 1994 /******************* Bit definition for SCB_CFSR register *******************/
Kojto 96:487b796308b0 1995 /*!< MFSR */
Kojto 96:487b796308b0 1996 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
Kojto 96:487b796308b0 1997 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
Kojto 96:487b796308b0 1998 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
Kojto 96:487b796308b0 1999 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
Kojto 96:487b796308b0 2000 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
Kojto 96:487b796308b0 2001 /*!< BFSR */
Kojto 96:487b796308b0 2002 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
Kojto 96:487b796308b0 2003 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
Kojto 96:487b796308b0 2004 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
Kojto 96:487b796308b0 2005 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
Kojto 96:487b796308b0 2006 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
Kojto 96:487b796308b0 2007 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
Kojto 96:487b796308b0 2008 /*!< UFSR */
Kojto 96:487b796308b0 2009 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
Kojto 96:487b796308b0 2010 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
Kojto 96:487b796308b0 2011 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
Kojto 96:487b796308b0 2012 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
Kojto 96:487b796308b0 2013 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
Kojto 96:487b796308b0 2014 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
Kojto 96:487b796308b0 2015
Kojto 96:487b796308b0 2016 /******************* Bit definition for SCB_HFSR register *******************/
Kojto 96:487b796308b0 2017 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
Kojto 96:487b796308b0 2018 #define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
Kojto 96:487b796308b0 2019 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
Kojto 96:487b796308b0 2020
Kojto 96:487b796308b0 2021 /******************* Bit definition for SCB_DFSR register *******************/
Kojto 96:487b796308b0 2022 #define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
Kojto 96:487b796308b0 2023 #define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
Kojto 96:487b796308b0 2024 #define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
Kojto 96:487b796308b0 2025 #define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
Kojto 96:487b796308b0 2026 #define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
Kojto 96:487b796308b0 2027
Kojto 96:487b796308b0 2028 /******************* Bit definition for SCB_MMFAR register ******************/
Kojto 96:487b796308b0 2029 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
Kojto 96:487b796308b0 2030
Kojto 96:487b796308b0 2031 /******************* Bit definition for SCB_BFAR register *******************/
Kojto 96:487b796308b0 2032 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
Kojto 96:487b796308b0 2033
Kojto 96:487b796308b0 2034 /******************* Bit definition for SCB_afsr register *******************/
Kojto 96:487b796308b0 2035 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
Kojto 96:487b796308b0 2036
Kojto 96:487b796308b0 2037 /******************************************************************************/
Kojto 96:487b796308b0 2038 /* */
Kojto 96:487b796308b0 2039 /* External Interrupt/Event Controller */
Kojto 96:487b796308b0 2040 /* */
Kojto 96:487b796308b0 2041 /******************************************************************************/
Kojto 96:487b796308b0 2042
Kojto 96:487b796308b0 2043 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 96:487b796308b0 2044 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
Kojto 96:487b796308b0 2045 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
Kojto 96:487b796308b0 2046 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
Kojto 96:487b796308b0 2047 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
Kojto 96:487b796308b0 2048 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
Kojto 96:487b796308b0 2049 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
Kojto 96:487b796308b0 2050 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
Kojto 96:487b796308b0 2051 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
Kojto 96:487b796308b0 2052 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
Kojto 96:487b796308b0 2053 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
Kojto 96:487b796308b0 2054 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
Kojto 96:487b796308b0 2055 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
Kojto 96:487b796308b0 2056 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
Kojto 96:487b796308b0 2057 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
Kojto 96:487b796308b0 2058 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
Kojto 96:487b796308b0 2059 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
Kojto 96:487b796308b0 2060 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
Kojto 96:487b796308b0 2061 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
Kojto 96:487b796308b0 2062 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
Kojto 96:487b796308b0 2063 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
Kojto 96:487b796308b0 2064
Kojto 96:487b796308b0 2065 /******************* Bit definition for EXTI_EMR register *******************/
Kojto 96:487b796308b0 2066 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
Kojto 96:487b796308b0 2067 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
Kojto 96:487b796308b0 2068 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
Kojto 96:487b796308b0 2069 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
Kojto 96:487b796308b0 2070 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
Kojto 96:487b796308b0 2071 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
Kojto 96:487b796308b0 2072 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
Kojto 96:487b796308b0 2073 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
Kojto 96:487b796308b0 2074 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
Kojto 96:487b796308b0 2075 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
Kojto 96:487b796308b0 2076 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
Kojto 96:487b796308b0 2077 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
Kojto 96:487b796308b0 2078 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
Kojto 96:487b796308b0 2079 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
Kojto 96:487b796308b0 2080 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
Kojto 96:487b796308b0 2081 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
Kojto 96:487b796308b0 2082 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
Kojto 96:487b796308b0 2083 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
Kojto 96:487b796308b0 2084 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
Kojto 96:487b796308b0 2085 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
Kojto 96:487b796308b0 2086
Kojto 96:487b796308b0 2087 /****************** Bit definition for EXTI_RTSR register *******************/
Kojto 96:487b796308b0 2088 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
Kojto 96:487b796308b0 2089 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
Kojto 96:487b796308b0 2090 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
Kojto 96:487b796308b0 2091 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
Kojto 96:487b796308b0 2092 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
Kojto 96:487b796308b0 2093 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
Kojto 96:487b796308b0 2094 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
Kojto 96:487b796308b0 2095 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
Kojto 96:487b796308b0 2096 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
Kojto 96:487b796308b0 2097 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
Kojto 96:487b796308b0 2098 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
Kojto 96:487b796308b0 2099 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
Kojto 96:487b796308b0 2100 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
Kojto 96:487b796308b0 2101 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
Kojto 96:487b796308b0 2102 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
Kojto 96:487b796308b0 2103 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
Kojto 96:487b796308b0 2104 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
Kojto 96:487b796308b0 2105 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
Kojto 96:487b796308b0 2106 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
Kojto 96:487b796308b0 2107 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
Kojto 96:487b796308b0 2108
Kojto 96:487b796308b0 2109 /****************** Bit definition for EXTI_FTSR register *******************/
Kojto 96:487b796308b0 2110 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
Kojto 96:487b796308b0 2111 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
Kojto 96:487b796308b0 2112 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
Kojto 96:487b796308b0 2113 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
Kojto 96:487b796308b0 2114 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
Kojto 96:487b796308b0 2115 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
Kojto 96:487b796308b0 2116 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
Kojto 96:487b796308b0 2117 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
Kojto 96:487b796308b0 2118 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
Kojto 96:487b796308b0 2119 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
Kojto 96:487b796308b0 2120 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
Kojto 96:487b796308b0 2121 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
Kojto 96:487b796308b0 2122 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
Kojto 96:487b796308b0 2123 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
Kojto 96:487b796308b0 2124 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
Kojto 96:487b796308b0 2125 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
Kojto 96:487b796308b0 2126 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
Kojto 96:487b796308b0 2127 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
Kojto 96:487b796308b0 2128 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
Kojto 96:487b796308b0 2129 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
Kojto 96:487b796308b0 2130
Kojto 96:487b796308b0 2131 /****************** Bit definition for EXTI_SWIER register ******************/
Kojto 96:487b796308b0 2132 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
Kojto 96:487b796308b0 2133 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
Kojto 96:487b796308b0 2134 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
Kojto 96:487b796308b0 2135 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
Kojto 96:487b796308b0 2136 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
Kojto 96:487b796308b0 2137 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
Kojto 96:487b796308b0 2138 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
Kojto 96:487b796308b0 2139 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
Kojto 96:487b796308b0 2140 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
Kojto 96:487b796308b0 2141 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
Kojto 96:487b796308b0 2142 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
Kojto 96:487b796308b0 2143 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
Kojto 96:487b796308b0 2144 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
Kojto 96:487b796308b0 2145 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
Kojto 96:487b796308b0 2146 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
Kojto 96:487b796308b0 2147 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
Kojto 96:487b796308b0 2148 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
Kojto 96:487b796308b0 2149 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
Kojto 96:487b796308b0 2150 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
Kojto 96:487b796308b0 2151 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
Kojto 96:487b796308b0 2152
Kojto 96:487b796308b0 2153 /******************* Bit definition for EXTI_PR register ********************/
Kojto 96:487b796308b0 2154 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
Kojto 96:487b796308b0 2155 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
Kojto 96:487b796308b0 2156 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
Kojto 96:487b796308b0 2157 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
Kojto 96:487b796308b0 2158 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
Kojto 96:487b796308b0 2159 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
Kojto 96:487b796308b0 2160 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
Kojto 96:487b796308b0 2161 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
Kojto 96:487b796308b0 2162 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
Kojto 96:487b796308b0 2163 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
Kojto 96:487b796308b0 2164 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
Kojto 96:487b796308b0 2165 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
Kojto 96:487b796308b0 2166 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
Kojto 96:487b796308b0 2167 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
Kojto 96:487b796308b0 2168 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
Kojto 96:487b796308b0 2169 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
Kojto 96:487b796308b0 2170 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
Kojto 96:487b796308b0 2171 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
Kojto 96:487b796308b0 2172 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
Kojto 96:487b796308b0 2173 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
Kojto 96:487b796308b0 2174
Kojto 96:487b796308b0 2175 /******************************************************************************/
Kojto 96:487b796308b0 2176 /* */
Kojto 96:487b796308b0 2177 /* DMA Controller */
Kojto 96:487b796308b0 2178 /* */
Kojto 96:487b796308b0 2179 /******************************************************************************/
Kojto 96:487b796308b0 2180
Kojto 96:487b796308b0 2181 /******************* Bit definition for DMA_ISR register ********************/
Kojto 96:487b796308b0 2182 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
Kojto 96:487b796308b0 2183 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
Kojto 96:487b796308b0 2184 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
Kojto 96:487b796308b0 2185 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
Kojto 96:487b796308b0 2186 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
Kojto 96:487b796308b0 2187 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
Kojto 96:487b796308b0 2188 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
Kojto 96:487b796308b0 2189 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
Kojto 96:487b796308b0 2190 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
Kojto 96:487b796308b0 2191 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
Kojto 96:487b796308b0 2192 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
Kojto 96:487b796308b0 2193 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
Kojto 96:487b796308b0 2194 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
Kojto 96:487b796308b0 2195 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
Kojto 96:487b796308b0 2196 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
Kojto 96:487b796308b0 2197 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
Kojto 96:487b796308b0 2198 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
Kojto 96:487b796308b0 2199 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
Kojto 96:487b796308b0 2200 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
Kojto 96:487b796308b0 2201 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
Kojto 96:487b796308b0 2202 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
Kojto 96:487b796308b0 2203 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
Kojto 96:487b796308b0 2204 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
Kojto 96:487b796308b0 2205 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
Kojto 96:487b796308b0 2206 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
Kojto 96:487b796308b0 2207 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
Kojto 96:487b796308b0 2208 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
Kojto 96:487b796308b0 2209 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
Kojto 96:487b796308b0 2210
Kojto 96:487b796308b0 2211 /******************* Bit definition for DMA_IFCR register *******************/
Kojto 96:487b796308b0 2212 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
Kojto 96:487b796308b0 2213 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
Kojto 96:487b796308b0 2214 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
Kojto 96:487b796308b0 2215 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
Kojto 96:487b796308b0 2216 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
Kojto 96:487b796308b0 2217 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
Kojto 96:487b796308b0 2218 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
Kojto 96:487b796308b0 2219 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
Kojto 96:487b796308b0 2220 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
Kojto 96:487b796308b0 2221 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
Kojto 96:487b796308b0 2222 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
Kojto 96:487b796308b0 2223 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
Kojto 96:487b796308b0 2224 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
Kojto 96:487b796308b0 2225 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
Kojto 96:487b796308b0 2226 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
Kojto 96:487b796308b0 2227 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
Kojto 96:487b796308b0 2228 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
Kojto 96:487b796308b0 2229 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
Kojto 96:487b796308b0 2230 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
Kojto 96:487b796308b0 2231 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
Kojto 96:487b796308b0 2232 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
Kojto 96:487b796308b0 2233 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
Kojto 96:487b796308b0 2234 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
Kojto 96:487b796308b0 2235 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
Kojto 96:487b796308b0 2236 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
Kojto 96:487b796308b0 2237 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
Kojto 96:487b796308b0 2238 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
Kojto 96:487b796308b0 2239 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
Kojto 96:487b796308b0 2240
Kojto 96:487b796308b0 2241 /******************* Bit definition for DMA_CCR register *******************/
Kojto 96:487b796308b0 2242 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
Kojto 96:487b796308b0 2243 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
Kojto 96:487b796308b0 2244 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
Kojto 96:487b796308b0 2245 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
Kojto 96:487b796308b0 2246 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
Kojto 96:487b796308b0 2247 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
Kojto 96:487b796308b0 2248 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
Kojto 96:487b796308b0 2249 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
Kojto 96:487b796308b0 2250
Kojto 96:487b796308b0 2251 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
Kojto 96:487b796308b0 2252 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 96:487b796308b0 2253 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 96:487b796308b0 2254
Kojto 96:487b796308b0 2255 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
Kojto 96:487b796308b0 2256 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 2257 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 2258
Kojto 96:487b796308b0 2259 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level) */
Kojto 96:487b796308b0 2260 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 2261 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 2262
Kojto 96:487b796308b0 2263 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
Kojto 96:487b796308b0 2264
Kojto 96:487b796308b0 2265 /****************** Bit definition for DMA_CNDTR register ******************/
Kojto 96:487b796308b0 2266 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
Kojto 96:487b796308b0 2267
Kojto 96:487b796308b0 2268 /****************** Bit definition for DMA_CPAR register *******************/
Kojto 96:487b796308b0 2269 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
Kojto 96:487b796308b0 2270
Kojto 96:487b796308b0 2271 /****************** Bit definition for DMA_CMAR register *******************/
Kojto 96:487b796308b0 2272 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 96:487b796308b0 2273
Kojto 96:487b796308b0 2274 /******************************************************************************/
Kojto 96:487b796308b0 2275 /* */
Kojto 96:487b796308b0 2276 /* Analog to Digital Converter */
Kojto 96:487b796308b0 2277 /* */
Kojto 96:487b796308b0 2278 /******************************************************************************/
Kojto 96:487b796308b0 2279
Kojto 96:487b796308b0 2280 /******************** Bit definition for ADC_SR register ********************/
Kojto 96:487b796308b0 2281 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
Kojto 96:487b796308b0 2282 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
Kojto 96:487b796308b0 2283 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
Kojto 96:487b796308b0 2284 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
Kojto 96:487b796308b0 2285 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
Kojto 96:487b796308b0 2286
Kojto 96:487b796308b0 2287 /******************* Bit definition for ADC_CR1 register ********************/
Kojto 96:487b796308b0 2288 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 96:487b796308b0 2289 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 2290 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 2291 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 2292 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 96:487b796308b0 2293 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
Kojto 96:487b796308b0 2294
Kojto 96:487b796308b0 2295 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
Kojto 96:487b796308b0 2296 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
Kojto 96:487b796308b0 2297 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
Kojto 96:487b796308b0 2298 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
Kojto 96:487b796308b0 2299 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
Kojto 96:487b796308b0 2300 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
Kojto 96:487b796308b0 2301 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
Kojto 96:487b796308b0 2302 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
Kojto 96:487b796308b0 2303
Kojto 96:487b796308b0 2304 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
Kojto 96:487b796308b0 2305 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
Kojto 96:487b796308b0 2306 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
Kojto 96:487b796308b0 2307 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
Kojto 96:487b796308b0 2308
Kojto 96:487b796308b0 2309 #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */
Kojto 96:487b796308b0 2310 #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 96:487b796308b0 2311 #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 96:487b796308b0 2312 #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 96:487b796308b0 2313 #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 96:487b796308b0 2314
Kojto 96:487b796308b0 2315 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
Kojto 96:487b796308b0 2316 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
Kojto 96:487b796308b0 2317
Kojto 96:487b796308b0 2318
Kojto 96:487b796308b0 2319 /******************* Bit definition for ADC_CR2 register ********************/
Kojto 96:487b796308b0 2320 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
Kojto 96:487b796308b0 2321 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
Kojto 96:487b796308b0 2322 #define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */
Kojto 96:487b796308b0 2323 #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */
Kojto 96:487b796308b0 2324 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
Kojto 96:487b796308b0 2325 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
Kojto 96:487b796308b0 2326
Kojto 96:487b796308b0 2327 #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */
Kojto 96:487b796308b0 2328 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 2329 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 2330 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
Kojto 96:487b796308b0 2331
Kojto 96:487b796308b0 2332 #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */
Kojto 96:487b796308b0 2333
Kojto 96:487b796308b0 2334 #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
Kojto 96:487b796308b0 2335 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */
Kojto 96:487b796308b0 2336 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */
Kojto 96:487b796308b0 2337 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */
Kojto 96:487b796308b0 2338
Kojto 96:487b796308b0 2339 #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */
Kojto 96:487b796308b0 2340 #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */
Kojto 96:487b796308b0 2341 #define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */
Kojto 96:487b796308b0 2342 #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
Kojto 96:487b796308b0 2343
Kojto 96:487b796308b0 2344 /****************** Bit definition for ADC_SMPR1 register *******************/
Kojto 96:487b796308b0 2345 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
Kojto 96:487b796308b0 2346 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 2347 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 2348 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 2349
Kojto 96:487b796308b0 2350 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
Kojto 96:487b796308b0 2351 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 96:487b796308b0 2352 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 96:487b796308b0 2353 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
Kojto 96:487b796308b0 2354
Kojto 96:487b796308b0 2355 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
Kojto 96:487b796308b0 2356 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Kojto 96:487b796308b0 2357 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Kojto 96:487b796308b0 2358 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
Kojto 96:487b796308b0 2359
Kojto 96:487b796308b0 2360 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
Kojto 96:487b796308b0 2361 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 96:487b796308b0 2362 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 96:487b796308b0 2363 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
Kojto 96:487b796308b0 2364
Kojto 96:487b796308b0 2365 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
Kojto 96:487b796308b0 2366 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 2367 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 2368 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
Kojto 96:487b796308b0 2369
Kojto 96:487b796308b0 2370 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
Kojto 96:487b796308b0 2371 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
Kojto 96:487b796308b0 2372 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
Kojto 96:487b796308b0 2373 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
Kojto 96:487b796308b0 2374
Kojto 96:487b796308b0 2375 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
Kojto 96:487b796308b0 2376 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 96:487b796308b0 2377 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 96:487b796308b0 2378 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
Kojto 96:487b796308b0 2379
Kojto 96:487b796308b0 2380 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
Kojto 96:487b796308b0 2381 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Kojto 96:487b796308b0 2382 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 96:487b796308b0 2383 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
Kojto 96:487b796308b0 2384
Kojto 96:487b796308b0 2385 /****************** Bit definition for ADC_SMPR2 register *******************/
Kojto 96:487b796308b0 2386 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
Kojto 96:487b796308b0 2387 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 2388 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 2389 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 2390
Kojto 96:487b796308b0 2391 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
Kojto 96:487b796308b0 2392 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 96:487b796308b0 2393 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 96:487b796308b0 2394 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
Kojto 96:487b796308b0 2395
Kojto 96:487b796308b0 2396 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
Kojto 96:487b796308b0 2397 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Kojto 96:487b796308b0 2398 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Kojto 96:487b796308b0 2399 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
Kojto 96:487b796308b0 2400
Kojto 96:487b796308b0 2401 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
Kojto 96:487b796308b0 2402 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 96:487b796308b0 2403 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 96:487b796308b0 2404 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
Kojto 96:487b796308b0 2405
Kojto 96:487b796308b0 2406 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
Kojto 96:487b796308b0 2407 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 2408 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 2409 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
Kojto 96:487b796308b0 2410
Kojto 96:487b796308b0 2411 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
Kojto 96:487b796308b0 2412 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
Kojto 96:487b796308b0 2413 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
Kojto 96:487b796308b0 2414 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
Kojto 96:487b796308b0 2415
Kojto 96:487b796308b0 2416 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
Kojto 96:487b796308b0 2417 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 96:487b796308b0 2418 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 96:487b796308b0 2419 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
Kojto 96:487b796308b0 2420
Kojto 96:487b796308b0 2421 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
Kojto 96:487b796308b0 2422 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Kojto 96:487b796308b0 2423 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 96:487b796308b0 2424 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
Kojto 96:487b796308b0 2425
Kojto 96:487b796308b0 2426 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
Kojto 96:487b796308b0 2427 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 96:487b796308b0 2428 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 96:487b796308b0 2429 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Kojto 96:487b796308b0 2430
Kojto 96:487b796308b0 2431 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
Kojto 96:487b796308b0 2432 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
Kojto 96:487b796308b0 2433 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
Kojto 96:487b796308b0 2434 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
Kojto 96:487b796308b0 2435
Kojto 96:487b796308b0 2436 /****************** Bit definition for ADC_JOFR1 register *******************/
Kojto 96:487b796308b0 2437 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
Kojto 96:487b796308b0 2438
Kojto 96:487b796308b0 2439 /****************** Bit definition for ADC_JOFR2 register *******************/
Kojto 96:487b796308b0 2440 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
Kojto 96:487b796308b0 2441
Kojto 96:487b796308b0 2442 /****************** Bit definition for ADC_JOFR3 register *******************/
Kojto 96:487b796308b0 2443 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
Kojto 96:487b796308b0 2444
Kojto 96:487b796308b0 2445 /****************** Bit definition for ADC_JOFR4 register *******************/
Kojto 96:487b796308b0 2446 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
Kojto 96:487b796308b0 2447
Kojto 96:487b796308b0 2448 /******************* Bit definition for ADC_HTR register ********************/
Kojto 96:487b796308b0 2449 #define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
Kojto 96:487b796308b0 2450
Kojto 96:487b796308b0 2451 /******************* Bit definition for ADC_LTR register ********************/
Kojto 96:487b796308b0 2452 #define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
Kojto 96:487b796308b0 2453
Kojto 96:487b796308b0 2454 /******************* Bit definition for ADC_SQR1 register *******************/
Kojto 96:487b796308b0 2455 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
Kojto 96:487b796308b0 2456 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 2457 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 2458 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 2459 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 96:487b796308b0 2460 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
Kojto 96:487b796308b0 2461
Kojto 96:487b796308b0 2462 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
Kojto 96:487b796308b0 2463 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 96:487b796308b0 2464 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 96:487b796308b0 2465 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Kojto 96:487b796308b0 2466 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
Kojto 96:487b796308b0 2467 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
Kojto 96:487b796308b0 2468
Kojto 96:487b796308b0 2469 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
Kojto 96:487b796308b0 2470 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 2471 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 2472 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 2473 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 2474 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 2475
Kojto 96:487b796308b0 2476 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
Kojto 96:487b796308b0 2477 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
Kojto 96:487b796308b0 2478 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
Kojto 96:487b796308b0 2479 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
Kojto 96:487b796308b0 2480 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
Kojto 96:487b796308b0 2481 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
Kojto 96:487b796308b0 2482
Kojto 96:487b796308b0 2483 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
Kojto 96:487b796308b0 2484 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
Kojto 96:487b796308b0 2485 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
Kojto 96:487b796308b0 2486 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
Kojto 96:487b796308b0 2487 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
Kojto 96:487b796308b0 2488
Kojto 96:487b796308b0 2489 /******************* Bit definition for ADC_SQR2 register *******************/
Kojto 96:487b796308b0 2490 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
Kojto 96:487b796308b0 2491 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 2492 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 2493 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 2494 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 96:487b796308b0 2495 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
Kojto 96:487b796308b0 2496
Kojto 96:487b796308b0 2497 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
Kojto 96:487b796308b0 2498 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 96:487b796308b0 2499 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 96:487b796308b0 2500 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Kojto 96:487b796308b0 2501 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
Kojto 96:487b796308b0 2502 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
Kojto 96:487b796308b0 2503
Kojto 96:487b796308b0 2504 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
Kojto 96:487b796308b0 2505 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 2506 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 2507 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 2508 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 2509 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 2510
Kojto 96:487b796308b0 2511 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
Kojto 96:487b796308b0 2512 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
Kojto 96:487b796308b0 2513 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
Kojto 96:487b796308b0 2514 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
Kojto 96:487b796308b0 2515 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
Kojto 96:487b796308b0 2516 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
Kojto 96:487b796308b0 2517
Kojto 96:487b796308b0 2518 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
Kojto 96:487b796308b0 2519 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
Kojto 96:487b796308b0 2520 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
Kojto 96:487b796308b0 2521 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
Kojto 96:487b796308b0 2522 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
Kojto 96:487b796308b0 2523 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
Kojto 96:487b796308b0 2524
Kojto 96:487b796308b0 2525 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
Kojto 96:487b796308b0 2526 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
Kojto 96:487b796308b0 2527 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
Kojto 96:487b796308b0 2528 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
Kojto 96:487b796308b0 2529 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
Kojto 96:487b796308b0 2530 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
Kojto 96:487b796308b0 2531
Kojto 96:487b796308b0 2532 /******************* Bit definition for ADC_SQR3 register *******************/
Kojto 96:487b796308b0 2533 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
Kojto 96:487b796308b0 2534 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 2535 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 2536 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 2537 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 96:487b796308b0 2538 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
Kojto 96:487b796308b0 2539
Kojto 96:487b796308b0 2540 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
Kojto 96:487b796308b0 2541 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 96:487b796308b0 2542 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 96:487b796308b0 2543 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Kojto 96:487b796308b0 2544 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
Kojto 96:487b796308b0 2545 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
Kojto 96:487b796308b0 2546
Kojto 96:487b796308b0 2547 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
Kojto 96:487b796308b0 2548 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 2549 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 2550 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 2551 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 2552 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 2553
Kojto 96:487b796308b0 2554 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
Kojto 96:487b796308b0 2555 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
Kojto 96:487b796308b0 2556 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
Kojto 96:487b796308b0 2557 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
Kojto 96:487b796308b0 2558 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
Kojto 96:487b796308b0 2559 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
Kojto 96:487b796308b0 2560
Kojto 96:487b796308b0 2561 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
Kojto 96:487b796308b0 2562 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
Kojto 96:487b796308b0 2563 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
Kojto 96:487b796308b0 2564 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
Kojto 96:487b796308b0 2565 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
Kojto 96:487b796308b0 2566 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
Kojto 96:487b796308b0 2567
Kojto 96:487b796308b0 2568 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
Kojto 96:487b796308b0 2569 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
Kojto 96:487b796308b0 2570 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
Kojto 96:487b796308b0 2571 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
Kojto 96:487b796308b0 2572 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
Kojto 96:487b796308b0 2573 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
Kojto 96:487b796308b0 2574
Kojto 96:487b796308b0 2575 /******************* Bit definition for ADC_JSQR register *******************/
Kojto 96:487b796308b0 2576 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
Kojto 96:487b796308b0 2577 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 2578 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 2579 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 2580 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 96:487b796308b0 2581 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
Kojto 96:487b796308b0 2582
Kojto 96:487b796308b0 2583 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
Kojto 96:487b796308b0 2584 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 96:487b796308b0 2585 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 96:487b796308b0 2586 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Kojto 96:487b796308b0 2587 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
Kojto 96:487b796308b0 2588 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
Kojto 96:487b796308b0 2589
Kojto 96:487b796308b0 2590 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
Kojto 96:487b796308b0 2591 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 2592 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 2593 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 2594 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 2595 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 2596
Kojto 96:487b796308b0 2597 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
Kojto 96:487b796308b0 2598 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
Kojto 96:487b796308b0 2599 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
Kojto 96:487b796308b0 2600 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
Kojto 96:487b796308b0 2601 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
Kojto 96:487b796308b0 2602 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
Kojto 96:487b796308b0 2603
Kojto 96:487b796308b0 2604 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
Kojto 96:487b796308b0 2605 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
Kojto 96:487b796308b0 2606 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
Kojto 96:487b796308b0 2607
Kojto 96:487b796308b0 2608 /******************* Bit definition for ADC_JDR1 register *******************/
Kojto 96:487b796308b0 2609 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
Kojto 96:487b796308b0 2610
Kojto 96:487b796308b0 2611 /******************* Bit definition for ADC_JDR2 register *******************/
Kojto 96:487b796308b0 2612 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
Kojto 96:487b796308b0 2613
Kojto 96:487b796308b0 2614 /******************* Bit definition for ADC_JDR3 register *******************/
Kojto 96:487b796308b0 2615 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
Kojto 96:487b796308b0 2616
Kojto 96:487b796308b0 2617 /******************* Bit definition for ADC_JDR4 register *******************/
Kojto 96:487b796308b0 2618 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
Kojto 96:487b796308b0 2619
Kojto 96:487b796308b0 2620 /******************** Bit definition for ADC_DR register ********************/
Kojto 96:487b796308b0 2621 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
Kojto 96:487b796308b0 2622 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */
Kojto 96:487b796308b0 2623
Kojto 96:487b796308b0 2624
Kojto 96:487b796308b0 2625 /*****************************************************************************/
Kojto 96:487b796308b0 2626 /* */
Kojto 96:487b796308b0 2627 /* Timers (TIM) */
Kojto 96:487b796308b0 2628 /* */
Kojto 96:487b796308b0 2629 /*****************************************************************************/
Kojto 96:487b796308b0 2630 /******************* Bit definition for TIM_CR1 register *******************/
Kojto 96:487b796308b0 2631 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
Kojto 96:487b796308b0 2632 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
Kojto 96:487b796308b0 2633 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
Kojto 96:487b796308b0 2634 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
Kojto 96:487b796308b0 2635 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
Kojto 96:487b796308b0 2636
Kojto 96:487b796308b0 2637 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 96:487b796308b0 2638 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 96:487b796308b0 2639 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 96:487b796308b0 2640
Kojto 96:487b796308b0 2641 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
Kojto 96:487b796308b0 2642
Kojto 96:487b796308b0 2643 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
Kojto 96:487b796308b0 2644 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 96:487b796308b0 2645 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 96:487b796308b0 2646
Kojto 96:487b796308b0 2647 /******************* Bit definition for TIM_CR2 register *******************/
Kojto 96:487b796308b0 2648 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
Kojto 96:487b796308b0 2649 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
Kojto 96:487b796308b0 2650 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
Kojto 96:487b796308b0 2651
Kojto 96:487b796308b0 2652 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 96:487b796308b0 2653 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 96:487b796308b0 2654 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 96:487b796308b0 2655 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 96:487b796308b0 2656
Kojto 96:487b796308b0 2657 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
Kojto 96:487b796308b0 2658 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
Kojto 96:487b796308b0 2659 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
Kojto 96:487b796308b0 2660 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
Kojto 96:487b796308b0 2661 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
Kojto 96:487b796308b0 2662 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
Kojto 96:487b796308b0 2663 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
Kojto 96:487b796308b0 2664 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
Kojto 96:487b796308b0 2665
Kojto 96:487b796308b0 2666 /******************* Bit definition for TIM_SMCR register ******************/
Kojto 96:487b796308b0 2667 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 96:487b796308b0 2668 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 96:487b796308b0 2669 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 96:487b796308b0 2670 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 96:487b796308b0 2671
Kojto 96:487b796308b0 2672 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
Kojto 96:487b796308b0 2673
Kojto 96:487b796308b0 2674 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
Kojto 96:487b796308b0 2675 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 96:487b796308b0 2676 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 96:487b796308b0 2677 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 96:487b796308b0 2678
Kojto 96:487b796308b0 2679 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
Kojto 96:487b796308b0 2680
Kojto 96:487b796308b0 2681 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
Kojto 96:487b796308b0 2682 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 96:487b796308b0 2683 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 96:487b796308b0 2684 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 96:487b796308b0 2685 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 96:487b796308b0 2686
Kojto 96:487b796308b0 2687 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 96:487b796308b0 2688 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 96:487b796308b0 2689 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 96:487b796308b0 2690
Kojto 96:487b796308b0 2691 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
Kojto 96:487b796308b0 2692 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
Kojto 96:487b796308b0 2693
Kojto 96:487b796308b0 2694 /******************* Bit definition for TIM_DIER register ******************/
Kojto 96:487b796308b0 2695 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
Kojto 96:487b796308b0 2696 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
Kojto 96:487b796308b0 2697 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
Kojto 96:487b796308b0 2698 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
Kojto 96:487b796308b0 2699 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
Kojto 96:487b796308b0 2700 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
Kojto 96:487b796308b0 2701 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
Kojto 96:487b796308b0 2702 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
Kojto 96:487b796308b0 2703 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
Kojto 96:487b796308b0 2704 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
Kojto 96:487b796308b0 2705 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
Kojto 96:487b796308b0 2706 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
Kojto 96:487b796308b0 2707 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
Kojto 96:487b796308b0 2708 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
Kojto 96:487b796308b0 2709 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
Kojto 96:487b796308b0 2710
Kojto 96:487b796308b0 2711 /******************** Bit definition for TIM_SR register *******************/
Kojto 96:487b796308b0 2712 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
Kojto 96:487b796308b0 2713 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
Kojto 96:487b796308b0 2714 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
Kojto 96:487b796308b0 2715 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
Kojto 96:487b796308b0 2716 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
Kojto 96:487b796308b0 2717 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
Kojto 96:487b796308b0 2718 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
Kojto 96:487b796308b0 2719 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
Kojto 96:487b796308b0 2720 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
Kojto 96:487b796308b0 2721 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
Kojto 96:487b796308b0 2722 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
Kojto 96:487b796308b0 2723 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
Kojto 96:487b796308b0 2724
Kojto 96:487b796308b0 2725 /******************* Bit definition for TIM_EGR register *******************/
Kojto 96:487b796308b0 2726 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
Kojto 96:487b796308b0 2727 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
Kojto 96:487b796308b0 2728 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
Kojto 96:487b796308b0 2729 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
Kojto 96:487b796308b0 2730 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
Kojto 96:487b796308b0 2731 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
Kojto 96:487b796308b0 2732 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
Kojto 96:487b796308b0 2733 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
Kojto 96:487b796308b0 2734
Kojto 96:487b796308b0 2735 /****************** Bit definition for TIM_CCMR1 register ******************/
Kojto 96:487b796308b0 2736 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 96:487b796308b0 2737 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 96:487b796308b0 2738 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 96:487b796308b0 2739
Kojto 96:487b796308b0 2740 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
Kojto 96:487b796308b0 2741 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
Kojto 96:487b796308b0 2742
Kojto 96:487b796308b0 2743 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 96:487b796308b0 2744 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 96:487b796308b0 2745 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 96:487b796308b0 2746 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 96:487b796308b0 2747
Kojto 96:487b796308b0 2748 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
Kojto 96:487b796308b0 2749
Kojto 96:487b796308b0 2750 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 96:487b796308b0 2751 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 96:487b796308b0 2752 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 96:487b796308b0 2753
Kojto 96:487b796308b0 2754 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
Kojto 96:487b796308b0 2755 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
Kojto 96:487b796308b0 2756
Kojto 96:487b796308b0 2757 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 96:487b796308b0 2758 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 96:487b796308b0 2759 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 96:487b796308b0 2760 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 96:487b796308b0 2761
Kojto 96:487b796308b0 2762 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
Kojto 96:487b796308b0 2763
Kojto 96:487b796308b0 2764 /*---------------------------------------------------------------------------*/
Kojto 96:487b796308b0 2765
Kojto 96:487b796308b0 2766 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 96:487b796308b0 2767 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 96:487b796308b0 2768 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 96:487b796308b0 2769
Kojto 96:487b796308b0 2770 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 96:487b796308b0 2771 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 96:487b796308b0 2772 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 96:487b796308b0 2773 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 96:487b796308b0 2774 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 96:487b796308b0 2775
Kojto 96:487b796308b0 2776 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 96:487b796308b0 2777 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 96:487b796308b0 2778 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 96:487b796308b0 2779
Kojto 96:487b796308b0 2780 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 96:487b796308b0 2781 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 96:487b796308b0 2782 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 96:487b796308b0 2783 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 96:487b796308b0 2784 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
Kojto 96:487b796308b0 2785
Kojto 96:487b796308b0 2786 /****************** Bit definition for TIM_CCMR2 register ******************/
Kojto 96:487b796308b0 2787 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 96:487b796308b0 2788 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 96:487b796308b0 2789 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 96:487b796308b0 2790
Kojto 96:487b796308b0 2791 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
Kojto 96:487b796308b0 2792 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
Kojto 96:487b796308b0 2793
Kojto 96:487b796308b0 2794 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 96:487b796308b0 2795 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 96:487b796308b0 2796 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 96:487b796308b0 2797 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 96:487b796308b0 2798
Kojto 96:487b796308b0 2799 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
Kojto 96:487b796308b0 2800
Kojto 96:487b796308b0 2801 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 96:487b796308b0 2802 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 96:487b796308b0 2803 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 96:487b796308b0 2804
Kojto 96:487b796308b0 2805 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
Kojto 96:487b796308b0 2806 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
Kojto 96:487b796308b0 2807
Kojto 96:487b796308b0 2808 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 96:487b796308b0 2809 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 96:487b796308b0 2810 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 96:487b796308b0 2811 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 96:487b796308b0 2812
Kojto 96:487b796308b0 2813 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
Kojto 96:487b796308b0 2814
Kojto 96:487b796308b0 2815 /*---------------------------------------------------------------------------*/
Kojto 96:487b796308b0 2816
Kojto 96:487b796308b0 2817 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 96:487b796308b0 2818 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 96:487b796308b0 2819 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 96:487b796308b0 2820
Kojto 96:487b796308b0 2821 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 96:487b796308b0 2822 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 96:487b796308b0 2823 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 96:487b796308b0 2824 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 96:487b796308b0 2825 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 96:487b796308b0 2826
Kojto 96:487b796308b0 2827 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 96:487b796308b0 2828 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 96:487b796308b0 2829 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 96:487b796308b0 2830
Kojto 96:487b796308b0 2831 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 96:487b796308b0 2832 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 96:487b796308b0 2833 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 96:487b796308b0 2834 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 96:487b796308b0 2835 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
Kojto 96:487b796308b0 2836
Kojto 96:487b796308b0 2837 /******************* Bit definition for TIM_CCER register ******************/
Kojto 96:487b796308b0 2838 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
Kojto 96:487b796308b0 2839 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
Kojto 96:487b796308b0 2840 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
Kojto 96:487b796308b0 2841 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 96:487b796308b0 2842 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
Kojto 96:487b796308b0 2843 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
Kojto 96:487b796308b0 2844 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
Kojto 96:487b796308b0 2845 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 96:487b796308b0 2846 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
Kojto 96:487b796308b0 2847 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
Kojto 96:487b796308b0 2848 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
Kojto 96:487b796308b0 2849 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 96:487b796308b0 2850 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
Kojto 96:487b796308b0 2851 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
Kojto 96:487b796308b0 2852 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 96:487b796308b0 2853
Kojto 96:487b796308b0 2854 /******************* Bit definition for TIM_CNT register *******************/
Kojto 96:487b796308b0 2855 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
Kojto 96:487b796308b0 2856
Kojto 96:487b796308b0 2857 /******************* Bit definition for TIM_PSC register *******************/
Kojto 96:487b796308b0 2858 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
Kojto 96:487b796308b0 2859
Kojto 96:487b796308b0 2860 /******************* Bit definition for TIM_ARR register *******************/
Kojto 96:487b796308b0 2861 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
Kojto 96:487b796308b0 2862
Kojto 96:487b796308b0 2863 /******************* Bit definition for TIM_RCR register *******************/
Kojto 96:487b796308b0 2864 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
Kojto 96:487b796308b0 2865
Kojto 96:487b796308b0 2866 /******************* Bit definition for TIM_CCR1 register ******************/
Kojto 96:487b796308b0 2867 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
Kojto 96:487b796308b0 2868
Kojto 96:487b796308b0 2869 /******************* Bit definition for TIM_CCR2 register ******************/
Kojto 96:487b796308b0 2870 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
Kojto 96:487b796308b0 2871
Kojto 96:487b796308b0 2872 /******************* Bit definition for TIM_CCR3 register ******************/
Kojto 96:487b796308b0 2873 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
Kojto 96:487b796308b0 2874
Kojto 96:487b796308b0 2875 /******************* Bit definition for TIM_CCR4 register ******************/
Kojto 96:487b796308b0 2876 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
Kojto 96:487b796308b0 2877
Kojto 96:487b796308b0 2878 /******************* Bit definition for TIM_BDTR register ******************/
Kojto 96:487b796308b0 2879 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 96:487b796308b0 2880 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 96:487b796308b0 2881 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 96:487b796308b0 2882 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 96:487b796308b0 2883 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 96:487b796308b0 2884 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 96:487b796308b0 2885 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 96:487b796308b0 2886 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 96:487b796308b0 2887 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 96:487b796308b0 2888
Kojto 96:487b796308b0 2889 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 96:487b796308b0 2890 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 96:487b796308b0 2891 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 96:487b796308b0 2892
Kojto 96:487b796308b0 2893 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
Kojto 96:487b796308b0 2894 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
Kojto 96:487b796308b0 2895 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
Kojto 96:487b796308b0 2896 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
Kojto 96:487b796308b0 2897 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
Kojto 96:487b796308b0 2898 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
Kojto 96:487b796308b0 2899
Kojto 96:487b796308b0 2900 /******************* Bit definition for TIM_DCR register *******************/
Kojto 96:487b796308b0 2901 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 96:487b796308b0 2902 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 96:487b796308b0 2903 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 96:487b796308b0 2904 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 96:487b796308b0 2905 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 96:487b796308b0 2906 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 96:487b796308b0 2907
Kojto 96:487b796308b0 2908 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 96:487b796308b0 2909 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 96:487b796308b0 2910 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 96:487b796308b0 2911 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 96:487b796308b0 2912 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 96:487b796308b0 2913 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 96:487b796308b0 2914
Kojto 96:487b796308b0 2915 /******************* Bit definition for TIM_DMAR register ******************/
Kojto 96:487b796308b0 2916 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
Kojto 96:487b796308b0 2917
Kojto 96:487b796308b0 2918 /******************* Bit definition for TIM_OR register ********************/
Kojto 96:487b796308b0 2919
Kojto 96:487b796308b0 2920 /******************************************************************************/
Kojto 96:487b796308b0 2921 /* */
Kojto 96:487b796308b0 2922 /* Real-Time Clock */
Kojto 96:487b796308b0 2923 /* */
Kojto 96:487b796308b0 2924 /******************************************************************************/
Kojto 96:487b796308b0 2925
Kojto 96:487b796308b0 2926 /******************* Bit definition for RTC_CRH register ********************/
Kojto 96:487b796308b0 2927 #define RTC_CRH_SECIE ((uint32_t)0x00000001) /*!< Second Interrupt Enable */
Kojto 96:487b796308b0 2928 #define RTC_CRH_ALRIE ((uint32_t)0x00000002) /*!< Alarm Interrupt Enable */
Kojto 96:487b796308b0 2929 #define RTC_CRH_OWIE ((uint32_t)0x00000004) /*!< OverfloW Interrupt Enable */
Kojto 96:487b796308b0 2930
Kojto 96:487b796308b0 2931 /******************* Bit definition for RTC_CRL register ********************/
Kojto 96:487b796308b0 2932 #define RTC_CRL_SECF ((uint32_t)0x00000001) /*!< Second Flag */
Kojto 96:487b796308b0 2933 #define RTC_CRL_ALRF ((uint32_t)0x00000002) /*!< Alarm Flag */
Kojto 96:487b796308b0 2934 #define RTC_CRL_OWF ((uint32_t)0x00000004) /*!< OverfloW Flag */
Kojto 96:487b796308b0 2935 #define RTC_CRL_RSF ((uint32_t)0x00000008) /*!< Registers Synchronized Flag */
Kojto 96:487b796308b0 2936 #define RTC_CRL_CNF ((uint32_t)0x00000010) /*!< Configuration Flag */
Kojto 96:487b796308b0 2937 #define RTC_CRL_RTOFF ((uint32_t)0x00000020) /*!< RTC operation OFF */
Kojto 96:487b796308b0 2938
Kojto 96:487b796308b0 2939 /******************* Bit definition for RTC_PRLH register *******************/
Kojto 96:487b796308b0 2940 #define RTC_PRLH_PRL ((uint32_t)0x0000000F) /*!< RTC Prescaler Reload Value High */
Kojto 96:487b796308b0 2941
Kojto 96:487b796308b0 2942 /******************* Bit definition for RTC_PRLL register *******************/
Kojto 96:487b796308b0 2943 #define RTC_PRLL_PRL ((uint32_t)0x0000FFFF) /*!< RTC Prescaler Reload Value Low */
Kojto 96:487b796308b0 2944
Kojto 96:487b796308b0 2945 /******************* Bit definition for RTC_DIVH register *******************/
Kojto 96:487b796308b0 2946 #define RTC_DIVH_RTC_DIV ((uint32_t)0x0000000F) /*!< RTC Clock Divider High */
Kojto 96:487b796308b0 2947
Kojto 96:487b796308b0 2948 /******************* Bit definition for RTC_DIVL register *******************/
Kojto 96:487b796308b0 2949 #define RTC_DIVL_RTC_DIV ((uint32_t)0x0000FFFF) /*!< RTC Clock Divider Low */
Kojto 96:487b796308b0 2950
Kojto 96:487b796308b0 2951 /******************* Bit definition for RTC_CNTH register *******************/
Kojto 96:487b796308b0 2952 #define RTC_CNTH_RTC_CNT ((uint32_t)0x0000FFFF) /*!< RTC Counter High */
Kojto 96:487b796308b0 2953
Kojto 96:487b796308b0 2954 /******************* Bit definition for RTC_CNTL register *******************/
Kojto 96:487b796308b0 2955 #define RTC_CNTL_RTC_CNT ((uint32_t)0x0000FFFF) /*!< RTC Counter Low */
Kojto 96:487b796308b0 2956
Kojto 96:487b796308b0 2957 /******************* Bit definition for RTC_ALRH register *******************/
Kojto 96:487b796308b0 2958 #define RTC_ALRH_RTC_ALR ((uint32_t)0x0000FFFF) /*!< RTC Alarm High */
Kojto 96:487b796308b0 2959
Kojto 96:487b796308b0 2960 /******************* Bit definition for RTC_ALRL register *******************/
Kojto 96:487b796308b0 2961 #define RTC_ALRL_RTC_ALR ((uint32_t)0x0000FFFF) /*!< RTC Alarm Low */
Kojto 96:487b796308b0 2962
Kojto 96:487b796308b0 2963 /******************************************************************************/
Kojto 96:487b796308b0 2964 /* */
Kojto 96:487b796308b0 2965 /* Independent WATCHDOG (IWDG) */
Kojto 96:487b796308b0 2966 /* */
Kojto 96:487b796308b0 2967 /******************************************************************************/
Kojto 96:487b796308b0 2968
Kojto 96:487b796308b0 2969 /******************* Bit definition for IWDG_KR register ********************/
Kojto 96:487b796308b0 2970 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
Kojto 96:487b796308b0 2971
Kojto 96:487b796308b0 2972 /******************* Bit definition for IWDG_PR register ********************/
Kojto 96:487b796308b0 2973 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
Kojto 96:487b796308b0 2974 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 2975 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 2976 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 2977
Kojto 96:487b796308b0 2978 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 96:487b796308b0 2979 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
Kojto 96:487b796308b0 2980
Kojto 96:487b796308b0 2981 /******************* Bit definition for IWDG_SR register ********************/
Kojto 96:487b796308b0 2982 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
Kojto 96:487b796308b0 2983 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
Kojto 96:487b796308b0 2984
Kojto 96:487b796308b0 2985 /******************************************************************************/
Kojto 96:487b796308b0 2986 /* */
Kojto 96:487b796308b0 2987 /* Window WATCHDOG */
Kojto 96:487b796308b0 2988 /* */
Kojto 96:487b796308b0 2989 /******************************************************************************/
Kojto 96:487b796308b0 2990
Kojto 96:487b796308b0 2991 /******************* Bit definition for WWDG_CR register ********************/
Kojto 96:487b796308b0 2992 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 96:487b796308b0 2993 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 2994 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 2995 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 2996 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 96:487b796308b0 2997 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
Kojto 96:487b796308b0 2998 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
Kojto 96:487b796308b0 2999 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
Kojto 96:487b796308b0 3000
Kojto 96:487b796308b0 3001 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
Kojto 96:487b796308b0 3002
Kojto 96:487b796308b0 3003 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 96:487b796308b0 3004 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
Kojto 96:487b796308b0 3005 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 3006 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 3007 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 3008 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 96:487b796308b0 3009 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
Kojto 96:487b796308b0 3010 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
Kojto 96:487b796308b0 3011 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
Kojto 96:487b796308b0 3012
Kojto 96:487b796308b0 3013 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
Kojto 96:487b796308b0 3014 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
Kojto 96:487b796308b0 3015 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
Kojto 96:487b796308b0 3016
Kojto 96:487b796308b0 3017 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
Kojto 96:487b796308b0 3018
Kojto 96:487b796308b0 3019 /******************* Bit definition for WWDG_SR register ********************/
Kojto 96:487b796308b0 3020 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
Kojto 96:487b796308b0 3021
Kojto 96:487b796308b0 3022
Kojto 96:487b796308b0 3023 /******************************************************************************/
Kojto 96:487b796308b0 3024 /* */
Kojto 96:487b796308b0 3025 /* SD host Interface */
Kojto 96:487b796308b0 3026 /* */
Kojto 96:487b796308b0 3027 /******************************************************************************/
Kojto 96:487b796308b0 3028
Kojto 96:487b796308b0 3029 /****************** Bit definition for SDIO_POWER register ******************/
Kojto 96:487b796308b0 3030 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */
Kojto 96:487b796308b0 3031 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!< Bit 0 */
Kojto 96:487b796308b0 3032 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!< Bit 1 */
Kojto 96:487b796308b0 3033
Kojto 96:487b796308b0 3034 /****************** Bit definition for SDIO_CLKCR register ******************/
Kojto 96:487b796308b0 3035 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!< Clock divide factor */
Kojto 96:487b796308b0 3036 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!< Clock enable bit */
Kojto 96:487b796308b0 3037 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!< Power saving configuration bit */
Kojto 96:487b796308b0 3038 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!< Clock divider bypass enable bit */
Kojto 96:487b796308b0 3039
Kojto 96:487b796308b0 3040 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
Kojto 96:487b796308b0 3041 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!< Bit 0 */
Kojto 96:487b796308b0 3042 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!< Bit 1 */
Kojto 96:487b796308b0 3043
Kojto 96:487b796308b0 3044 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!< SDIO_CK dephasing selection bit */
Kojto 96:487b796308b0 3045 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!< HW Flow Control enable */
Kojto 96:487b796308b0 3046
Kojto 96:487b796308b0 3047 /******************* Bit definition for SDIO_ARG register *******************/
Kojto 96:487b796308b0 3048 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */
Kojto 96:487b796308b0 3049
Kojto 96:487b796308b0 3050 /******************* Bit definition for SDIO_CMD register *******************/
Kojto 96:487b796308b0 3051 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!< Command Index */
Kojto 96:487b796308b0 3052
Kojto 96:487b796308b0 3053 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */
Kojto 96:487b796308b0 3054 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
Kojto 96:487b796308b0 3055 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
Kojto 96:487b796308b0 3056
Kojto 96:487b796308b0 3057 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!< CPSM Waits for Interrupt Request */
Kojto 96:487b796308b0 3058 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
Kojto 96:487b796308b0 3059 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */
Kojto 96:487b796308b0 3060 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!< SD I/O suspend command */
Kojto 96:487b796308b0 3061 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!< Enable CMD completion */
Kojto 96:487b796308b0 3062 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!< Not Interrupt Enable */
Kojto 96:487b796308b0 3063 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!< CE-ATA command */
Kojto 96:487b796308b0 3064
Kojto 96:487b796308b0 3065 /***************** Bit definition for SDIO_RESPCMD register *****************/
Kojto 96:487b796308b0 3066 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!< Response command index */
Kojto 96:487b796308b0 3067
Kojto 96:487b796308b0 3068 /****************** Bit definition for SDIO_RESP0 register ******************/
Kojto 96:487b796308b0 3069 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
Kojto 96:487b796308b0 3070
Kojto 96:487b796308b0 3071 /****************** Bit definition for SDIO_RESP1 register ******************/
Kojto 96:487b796308b0 3072 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
Kojto 96:487b796308b0 3073
Kojto 96:487b796308b0 3074 /****************** Bit definition for SDIO_RESP2 register ******************/
Kojto 96:487b796308b0 3075 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
Kojto 96:487b796308b0 3076
Kojto 96:487b796308b0 3077 /****************** Bit definition for SDIO_RESP3 register ******************/
Kojto 96:487b796308b0 3078 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
Kojto 96:487b796308b0 3079
Kojto 96:487b796308b0 3080 /****************** Bit definition for SDIO_RESP4 register ******************/
Kojto 96:487b796308b0 3081 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
Kojto 96:487b796308b0 3082
Kojto 96:487b796308b0 3083 /****************** Bit definition for SDIO_DTIMER register *****************/
Kojto 96:487b796308b0 3084 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */
Kojto 96:487b796308b0 3085
Kojto 96:487b796308b0 3086 /****************** Bit definition for SDIO_DLEN register *******************/
Kojto 96:487b796308b0 3087 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */
Kojto 96:487b796308b0 3088
Kojto 96:487b796308b0 3089 /****************** Bit definition for SDIO_DCTRL register ******************/
Kojto 96:487b796308b0 3090 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!< Data transfer enabled bit */
Kojto 96:487b796308b0 3091 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!< Data transfer direction selection */
Kojto 96:487b796308b0 3092 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!< Data transfer mode selection */
Kojto 96:487b796308b0 3093 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!< DMA enabled bit */
Kojto 96:487b796308b0 3094
Kojto 96:487b796308b0 3095 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */
Kojto 96:487b796308b0 3096 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!< Bit 0 */
Kojto 96:487b796308b0 3097 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!< Bit 1 */
Kojto 96:487b796308b0 3098 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!< Bit 2 */
Kojto 96:487b796308b0 3099 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!< Bit 3 */
Kojto 96:487b796308b0 3100
Kojto 96:487b796308b0 3101 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!< Read wait start */
Kojto 96:487b796308b0 3102 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!< Read wait stop */
Kojto 96:487b796308b0 3103 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!< Read wait mode */
Kojto 96:487b796308b0 3104 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!< SD I/O enable functions */
Kojto 96:487b796308b0 3105
Kojto 96:487b796308b0 3106 /****************** Bit definition for SDIO_DCOUNT register *****************/
Kojto 96:487b796308b0 3107 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */
Kojto 96:487b796308b0 3108
Kojto 96:487b796308b0 3109 /****************** Bit definition for SDIO_STA register ********************/
Kojto 96:487b796308b0 3110 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */
Kojto 96:487b796308b0 3111 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */
Kojto 96:487b796308b0 3112 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */
Kojto 96:487b796308b0 3113 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */
Kojto 96:487b796308b0 3114 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */
Kojto 96:487b796308b0 3115 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */
Kojto 96:487b796308b0 3116 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */
Kojto 96:487b796308b0 3117 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */
Kojto 96:487b796308b0 3118 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */
Kojto 96:487b796308b0 3119 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */
Kojto 96:487b796308b0 3120 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */
Kojto 96:487b796308b0 3121 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */
Kojto 96:487b796308b0 3122 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */
Kojto 96:487b796308b0 3123 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */
Kojto 96:487b796308b0 3124 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
Kojto 96:487b796308b0 3125 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
Kojto 96:487b796308b0 3126 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */
Kojto 96:487b796308b0 3127 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */
Kojto 96:487b796308b0 3128 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */
Kojto 96:487b796308b0 3129 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */
Kojto 96:487b796308b0 3130 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */
Kojto 96:487b796308b0 3131 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */
Kojto 96:487b796308b0 3132 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */
Kojto 96:487b796308b0 3133 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */
Kojto 96:487b796308b0 3134
Kojto 96:487b796308b0 3135 /******************* Bit definition for SDIO_ICR register *******************/
Kojto 96:487b796308b0 3136 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */
Kojto 96:487b796308b0 3137 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */
Kojto 96:487b796308b0 3138 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */
Kojto 96:487b796308b0 3139 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */
Kojto 96:487b796308b0 3140 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */
Kojto 96:487b796308b0 3141 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */
Kojto 96:487b796308b0 3142 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */
Kojto 96:487b796308b0 3143 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */
Kojto 96:487b796308b0 3144 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */
Kojto 96:487b796308b0 3145 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */
Kojto 96:487b796308b0 3146 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */
Kojto 96:487b796308b0 3147 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */
Kojto 96:487b796308b0 3148 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */
Kojto 96:487b796308b0 3149
Kojto 96:487b796308b0 3150 /****************** Bit definition for SDIO_MASK register *******************/
Kojto 96:487b796308b0 3151 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */
Kojto 96:487b796308b0 3152 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */
Kojto 96:487b796308b0 3153 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */
Kojto 96:487b796308b0 3154 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */
Kojto 96:487b796308b0 3155 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */
Kojto 96:487b796308b0 3156 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */
Kojto 96:487b796308b0 3157 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */
Kojto 96:487b796308b0 3158 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */
Kojto 96:487b796308b0 3159 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */
Kojto 96:487b796308b0 3160 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */
Kojto 96:487b796308b0 3161 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */
Kojto 96:487b796308b0 3162 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */
Kojto 96:487b796308b0 3163 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */
Kojto 96:487b796308b0 3164 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */
Kojto 96:487b796308b0 3165 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */
Kojto 96:487b796308b0 3166 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */
Kojto 96:487b796308b0 3167 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */
Kojto 96:487b796308b0 3168 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */
Kojto 96:487b796308b0 3169 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */
Kojto 96:487b796308b0 3170 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */
Kojto 96:487b796308b0 3171 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */
Kojto 96:487b796308b0 3172 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */
Kojto 96:487b796308b0 3173 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */
Kojto 96:487b796308b0 3174 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */
Kojto 96:487b796308b0 3175
Kojto 96:487b796308b0 3176 /***************** Bit definition for SDIO_FIFOCNT register *****************/
Kojto 96:487b796308b0 3177 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */
Kojto 96:487b796308b0 3178
Kojto 96:487b796308b0 3179 /****************** Bit definition for SDIO_FIFO register *******************/
Kojto 96:487b796308b0 3180 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */
Kojto 96:487b796308b0 3181
Kojto 96:487b796308b0 3182 /******************************************************************************/
Kojto 96:487b796308b0 3183 /* */
Kojto 96:487b796308b0 3184 /* USB Device FS */
Kojto 96:487b796308b0 3185 /* */
Kojto 96:487b796308b0 3186 /******************************************************************************/
Kojto 96:487b796308b0 3187
Kojto 96:487b796308b0 3188 /*!< Endpoint-specific registers */
Kojto 96:487b796308b0 3189 #define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
Kojto 96:487b796308b0 3190 #define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
Kojto 96:487b796308b0 3191 #define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
Kojto 96:487b796308b0 3192 #define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
Kojto 96:487b796308b0 3193 #define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
Kojto 96:487b796308b0 3194 #define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
Kojto 96:487b796308b0 3195 #define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
Kojto 96:487b796308b0 3196 #define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
Kojto 96:487b796308b0 3197
Kojto 96:487b796308b0 3198 /* bit positions */
Kojto 96:487b796308b0 3199 #define USB_EP_CTR_RX ((uint32_t)0x00008000) /*!< EndPoint Correct TRansfer RX */
Kojto 96:487b796308b0 3200 #define USB_EP_DTOG_RX ((uint32_t)0x00004000) /*!< EndPoint Data TOGGLE RX */
Kojto 96:487b796308b0 3201 #define USB_EPRX_STAT ((uint32_t)0x00003000) /*!< EndPoint RX STATus bit field */
Kojto 96:487b796308b0 3202 #define USB_EP_SETUP ((uint32_t)0x00000800) /*!< EndPoint SETUP */
Kojto 96:487b796308b0 3203 #define USB_EP_T_FIELD ((uint32_t)0x00000600) /*!< EndPoint TYPE */
Kojto 96:487b796308b0 3204 #define USB_EP_KIND ((uint32_t)0x00000100) /*!< EndPoint KIND */
Kojto 96:487b796308b0 3205 #define USB_EP_CTR_TX ((uint32_t)0x00000080) /*!< EndPoint Correct TRansfer TX */
Kojto 96:487b796308b0 3206 #define USB_EP_DTOG_TX ((uint32_t)0x00000040) /*!< EndPoint Data TOGGLE TX */
Kojto 96:487b796308b0 3207 #define USB_EPTX_STAT ((uint32_t)0x00000030) /*!< EndPoint TX STATus bit field */
Kojto 96:487b796308b0 3208 #define USB_EPADDR_FIELD ((uint32_t)0x0000000F) /*!< EndPoint ADDRess FIELD */
Kojto 96:487b796308b0 3209
Kojto 96:487b796308b0 3210 /* EndPoint REGister MASK (no toggle fields) */
Kojto 96:487b796308b0 3211 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
Kojto 96:487b796308b0 3212 /*!< EP_TYPE[1:0] EndPoint TYPE */
Kojto 96:487b796308b0 3213 #define USB_EP_TYPE_MASK ((uint32_t)0x00000600) /*!< EndPoint TYPE Mask */
Kojto 96:487b796308b0 3214 #define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
Kojto 96:487b796308b0 3215 #define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
Kojto 96:487b796308b0 3216 #define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
Kojto 96:487b796308b0 3217 #define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
Kojto 96:487b796308b0 3218 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
Kojto 96:487b796308b0 3219
Kojto 96:487b796308b0 3220 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
Kojto 96:487b796308b0 3221 /*!< STAT_TX[1:0] STATus for TX transfer */
Kojto 96:487b796308b0 3222 #define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
Kojto 96:487b796308b0 3223 #define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
Kojto 96:487b796308b0 3224 #define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
Kojto 96:487b796308b0 3225 #define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
Kojto 96:487b796308b0 3226 #define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
Kojto 96:487b796308b0 3227 #define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
Kojto 96:487b796308b0 3228 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
Kojto 96:487b796308b0 3229 /*!< STAT_RX[1:0] STATus for RX transfer */
Kojto 96:487b796308b0 3230 #define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
Kojto 96:487b796308b0 3231 #define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
Kojto 96:487b796308b0 3232 #define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
Kojto 96:487b796308b0 3233 #define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
Kojto 96:487b796308b0 3234 #define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
Kojto 96:487b796308b0 3235 #define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
Kojto 96:487b796308b0 3236 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
Kojto 96:487b796308b0 3237
Kojto 96:487b796308b0 3238 /******************* Bit definition for USB_EP0R register *******************/
Kojto 96:487b796308b0 3239 #define USB_EP0R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
Kojto 96:487b796308b0 3240
Kojto 96:487b796308b0 3241 #define USB_EP0R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 96:487b796308b0 3242 #define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 96:487b796308b0 3243 #define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 96:487b796308b0 3244
Kojto 96:487b796308b0 3245 #define USB_EP0R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
Kojto 96:487b796308b0 3246 #define USB_EP0R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
Kojto 96:487b796308b0 3247 #define USB_EP0R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
Kojto 96:487b796308b0 3248
Kojto 96:487b796308b0 3249 #define USB_EP0R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
Kojto 96:487b796308b0 3250 #define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 96:487b796308b0 3251 #define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 96:487b796308b0 3252
Kojto 96:487b796308b0 3253 #define USB_EP0R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
Kojto 96:487b796308b0 3254
Kojto 96:487b796308b0 3255 #define USB_EP0R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 96:487b796308b0 3256 #define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 3257 #define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 3258
Kojto 96:487b796308b0 3259 #define USB_EP0R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
Kojto 96:487b796308b0 3260 #define USB_EP0R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
Kojto 96:487b796308b0 3261
Kojto 96:487b796308b0 3262 /******************* Bit definition for USB_EP1R register *******************/
Kojto 96:487b796308b0 3263 #define USB_EP1R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
Kojto 96:487b796308b0 3264
Kojto 96:487b796308b0 3265 #define USB_EP1R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 96:487b796308b0 3266 #define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 96:487b796308b0 3267 #define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 96:487b796308b0 3268
Kojto 96:487b796308b0 3269 #define USB_EP1R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
Kojto 96:487b796308b0 3270 #define USB_EP1R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
Kojto 96:487b796308b0 3271 #define USB_EP1R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
Kojto 96:487b796308b0 3272
Kojto 96:487b796308b0 3273 #define USB_EP1R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
Kojto 96:487b796308b0 3274 #define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 96:487b796308b0 3275 #define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 96:487b796308b0 3276
Kojto 96:487b796308b0 3277 #define USB_EP1R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
Kojto 96:487b796308b0 3278
Kojto 96:487b796308b0 3279 #define USB_EP1R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 96:487b796308b0 3280 #define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 3281 #define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 3282
Kojto 96:487b796308b0 3283 #define USB_EP1R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
Kojto 96:487b796308b0 3284 #define USB_EP1R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
Kojto 96:487b796308b0 3285
Kojto 96:487b796308b0 3286 /******************* Bit definition for USB_EP2R register *******************/
Kojto 96:487b796308b0 3287 #define USB_EP2R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
Kojto 96:487b796308b0 3288
Kojto 96:487b796308b0 3289 #define USB_EP2R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 96:487b796308b0 3290 #define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 96:487b796308b0 3291 #define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 96:487b796308b0 3292
Kojto 96:487b796308b0 3293 #define USB_EP2R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
Kojto 96:487b796308b0 3294 #define USB_EP2R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
Kojto 96:487b796308b0 3295 #define USB_EP2R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
Kojto 96:487b796308b0 3296
Kojto 96:487b796308b0 3297 #define USB_EP2R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
Kojto 96:487b796308b0 3298 #define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 96:487b796308b0 3299 #define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 96:487b796308b0 3300
Kojto 96:487b796308b0 3301 #define USB_EP2R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
Kojto 96:487b796308b0 3302
Kojto 96:487b796308b0 3303 #define USB_EP2R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 96:487b796308b0 3304 #define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 3305 #define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 3306
Kojto 96:487b796308b0 3307 #define USB_EP2R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
Kojto 96:487b796308b0 3308 #define USB_EP2R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
Kojto 96:487b796308b0 3309
Kojto 96:487b796308b0 3310 /******************* Bit definition for USB_EP3R register *******************/
Kojto 96:487b796308b0 3311 #define USB_EP3R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
Kojto 96:487b796308b0 3312
Kojto 96:487b796308b0 3313 #define USB_EP3R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 96:487b796308b0 3314 #define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 96:487b796308b0 3315 #define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 96:487b796308b0 3316
Kojto 96:487b796308b0 3317 #define USB_EP3R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
Kojto 96:487b796308b0 3318 #define USB_EP3R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
Kojto 96:487b796308b0 3319 #define USB_EP3R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
Kojto 96:487b796308b0 3320
Kojto 96:487b796308b0 3321 #define USB_EP3R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
Kojto 96:487b796308b0 3322 #define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 96:487b796308b0 3323 #define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 96:487b796308b0 3324
Kojto 96:487b796308b0 3325 #define USB_EP3R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
Kojto 96:487b796308b0 3326
Kojto 96:487b796308b0 3327 #define USB_EP3R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 96:487b796308b0 3328 #define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 3329 #define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 3330
Kojto 96:487b796308b0 3331 #define USB_EP3R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
Kojto 96:487b796308b0 3332 #define USB_EP3R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
Kojto 96:487b796308b0 3333
Kojto 96:487b796308b0 3334 /******************* Bit definition for USB_EP4R register *******************/
Kojto 96:487b796308b0 3335 #define USB_EP4R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
Kojto 96:487b796308b0 3336
Kojto 96:487b796308b0 3337 #define USB_EP4R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 96:487b796308b0 3338 #define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 96:487b796308b0 3339 #define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 96:487b796308b0 3340
Kojto 96:487b796308b0 3341 #define USB_EP4R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
Kojto 96:487b796308b0 3342 #define USB_EP4R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
Kojto 96:487b796308b0 3343 #define USB_EP4R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
Kojto 96:487b796308b0 3344
Kojto 96:487b796308b0 3345 #define USB_EP4R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
Kojto 96:487b796308b0 3346 #define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 96:487b796308b0 3347 #define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 96:487b796308b0 3348
Kojto 96:487b796308b0 3349 #define USB_EP4R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
Kojto 96:487b796308b0 3350
Kojto 96:487b796308b0 3351 #define USB_EP4R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 96:487b796308b0 3352 #define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 3353 #define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 3354
Kojto 96:487b796308b0 3355 #define USB_EP4R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
Kojto 96:487b796308b0 3356 #define USB_EP4R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
Kojto 96:487b796308b0 3357
Kojto 96:487b796308b0 3358 /******************* Bit definition for USB_EP5R register *******************/
Kojto 96:487b796308b0 3359 #define USB_EP5R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
Kojto 96:487b796308b0 3360
Kojto 96:487b796308b0 3361 #define USB_EP5R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 96:487b796308b0 3362 #define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 96:487b796308b0 3363 #define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 96:487b796308b0 3364
Kojto 96:487b796308b0 3365 #define USB_EP5R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
Kojto 96:487b796308b0 3366 #define USB_EP5R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
Kojto 96:487b796308b0 3367 #define USB_EP5R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
Kojto 96:487b796308b0 3368
Kojto 96:487b796308b0 3369 #define USB_EP5R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
Kojto 96:487b796308b0 3370 #define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 96:487b796308b0 3371 #define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 96:487b796308b0 3372
Kojto 96:487b796308b0 3373 #define USB_EP5R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
Kojto 96:487b796308b0 3374
Kojto 96:487b796308b0 3375 #define USB_EP5R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 96:487b796308b0 3376 #define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 3377 #define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 3378
Kojto 96:487b796308b0 3379 #define USB_EP5R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
Kojto 96:487b796308b0 3380 #define USB_EP5R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
Kojto 96:487b796308b0 3381
Kojto 96:487b796308b0 3382 /******************* Bit definition for USB_EP6R register *******************/
Kojto 96:487b796308b0 3383 #define USB_EP6R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
Kojto 96:487b796308b0 3384
Kojto 96:487b796308b0 3385 #define USB_EP6R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 96:487b796308b0 3386 #define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 96:487b796308b0 3387 #define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 96:487b796308b0 3388
Kojto 96:487b796308b0 3389 #define USB_EP6R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
Kojto 96:487b796308b0 3390 #define USB_EP6R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
Kojto 96:487b796308b0 3391 #define USB_EP6R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
Kojto 96:487b796308b0 3392
Kojto 96:487b796308b0 3393 #define USB_EP6R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
Kojto 96:487b796308b0 3394 #define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 96:487b796308b0 3395 #define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 96:487b796308b0 3396
Kojto 96:487b796308b0 3397 #define USB_EP6R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
Kojto 96:487b796308b0 3398
Kojto 96:487b796308b0 3399 #define USB_EP6R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 96:487b796308b0 3400 #define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 3401 #define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 3402
Kojto 96:487b796308b0 3403 #define USB_EP6R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
Kojto 96:487b796308b0 3404 #define USB_EP6R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
Kojto 96:487b796308b0 3405
Kojto 96:487b796308b0 3406 /******************* Bit definition for USB_EP7R register *******************/
Kojto 96:487b796308b0 3407 #define USB_EP7R_EA ((uint32_t)0x0000000F) /*!< Endpoint Address */
Kojto 96:487b796308b0 3408
Kojto 96:487b796308b0 3409 #define USB_EP7R_STAT_TX ((uint32_t)0x00000030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 96:487b796308b0 3410 #define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 96:487b796308b0 3411 #define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 96:487b796308b0 3412
Kojto 96:487b796308b0 3413 #define USB_EP7R_DTOG_TX ((uint32_t)0x00000040) /*!< Data Toggle, for transmission transfers */
Kojto 96:487b796308b0 3414 #define USB_EP7R_CTR_TX ((uint32_t)0x00000080) /*!< Correct Transfer for transmission */
Kojto 96:487b796308b0 3415 #define USB_EP7R_EP_KIND ((uint32_t)0x00000100) /*!< Endpoint Kind */
Kojto 96:487b796308b0 3416
Kojto 96:487b796308b0 3417 #define USB_EP7R_EP_TYPE ((uint32_t)0x00000600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
Kojto 96:487b796308b0 3418 #define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 96:487b796308b0 3419 #define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 96:487b796308b0 3420
Kojto 96:487b796308b0 3421 #define USB_EP7R_SETUP ((uint32_t)0x00000800) /*!< Setup transaction completed */
Kojto 96:487b796308b0 3422
Kojto 96:487b796308b0 3423 #define USB_EP7R_STAT_RX ((uint32_t)0x00003000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 96:487b796308b0 3424 #define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 3425 #define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 3426
Kojto 96:487b796308b0 3427 #define USB_EP7R_DTOG_RX ((uint32_t)0x00004000) /*!< Data Toggle, for reception transfers */
Kojto 96:487b796308b0 3428 #define USB_EP7R_CTR_RX ((uint32_t)0x00008000) /*!< Correct Transfer for reception */
Kojto 96:487b796308b0 3429
Kojto 96:487b796308b0 3430 /*!< Common registers */
Kojto 96:487b796308b0 3431 /******************* Bit definition for USB_CNTR register *******************/
Kojto 96:487b796308b0 3432 #define USB_CNTR_FRES ((uint32_t)0x00000001) /*!< Force USB Reset */
Kojto 96:487b796308b0 3433 #define USB_CNTR_PDWN ((uint32_t)0x00000002) /*!< Power down */
Kojto 96:487b796308b0 3434 #define USB_CNTR_LP_MODE ((uint32_t)0x00000004) /*!< Low-power mode */
Kojto 96:487b796308b0 3435 #define USB_CNTR_FSUSP ((uint32_t)0x00000008) /*!< Force suspend */
Kojto 96:487b796308b0 3436 #define USB_CNTR_RESUME ((uint32_t)0x00000010) /*!< Resume request */
Kojto 96:487b796308b0 3437 #define USB_CNTR_ESOFM ((uint32_t)0x00000100) /*!< Expected Start Of Frame Interrupt Mask */
Kojto 96:487b796308b0 3438 #define USB_CNTR_SOFM ((uint32_t)0x00000200) /*!< Start Of Frame Interrupt Mask */
Kojto 96:487b796308b0 3439 #define USB_CNTR_RESETM ((uint32_t)0x00000400) /*!< RESET Interrupt Mask */
Kojto 96:487b796308b0 3440 #define USB_CNTR_SUSPM ((uint32_t)0x00000800) /*!< Suspend mode Interrupt Mask */
Kojto 96:487b796308b0 3441 #define USB_CNTR_WKUPM ((uint32_t)0x00001000) /*!< Wakeup Interrupt Mask */
Kojto 96:487b796308b0 3442 #define USB_CNTR_ERRM ((uint32_t)0x00002000) /*!< Error Interrupt Mask */
Kojto 96:487b796308b0 3443 #define USB_CNTR_PMAOVRM ((uint32_t)0x00004000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */
Kojto 96:487b796308b0 3444 #define USB_CNTR_CTRM ((uint32_t)0x00008000) /*!< Correct Transfer Interrupt Mask */
Kojto 96:487b796308b0 3445
Kojto 96:487b796308b0 3446 /******************* Bit definition for USB_ISTR register *******************/
Kojto 96:487b796308b0 3447 #define USB_ISTR_EP_ID ((uint32_t)0x0000000F) /*!< Endpoint Identifier */
Kojto 96:487b796308b0 3448 #define USB_ISTR_DIR ((uint32_t)0x00000010) /*!< Direction of transaction */
Kojto 96:487b796308b0 3449 #define USB_ISTR_ESOF ((uint32_t)0x00000100) /*!< Expected Start Of Frame */
Kojto 96:487b796308b0 3450 #define USB_ISTR_SOF ((uint32_t)0x00000200) /*!< Start Of Frame */
Kojto 96:487b796308b0 3451 #define USB_ISTR_RESET ((uint32_t)0x00000400) /*!< USB RESET request */
Kojto 96:487b796308b0 3452 #define USB_ISTR_SUSP ((uint32_t)0x00000800) /*!< Suspend mode request */
Kojto 96:487b796308b0 3453 #define USB_ISTR_WKUP ((uint32_t)0x00001000) /*!< Wake up */
Kojto 96:487b796308b0 3454 #define USB_ISTR_ERR ((uint32_t)0x00002000) /*!< Error */
Kojto 96:487b796308b0 3455 #define USB_ISTR_PMAOVR ((uint32_t)0x00004000) /*!< Packet Memory Area Over / Underrun */
Kojto 96:487b796308b0 3456 #define USB_ISTR_CTR ((uint32_t)0x00008000) /*!< Correct Transfer */
Kojto 96:487b796308b0 3457
Kojto 96:487b796308b0 3458 /******************* Bit definition for USB_FNR register ********************/
Kojto 96:487b796308b0 3459 #define USB_FNR_FN ((uint32_t)0x000007FF) /*!< Frame Number */
Kojto 96:487b796308b0 3460 #define USB_FNR_LSOF ((uint32_t)0x00001800) /*!< Lost SOF */
Kojto 96:487b796308b0 3461 #define USB_FNR_LCK ((uint32_t)0x00002000) /*!< Locked */
Kojto 96:487b796308b0 3462 #define USB_FNR_RXDM ((uint32_t)0x00004000) /*!< Receive Data - Line Status */
Kojto 96:487b796308b0 3463 #define USB_FNR_RXDP ((uint32_t)0x00008000) /*!< Receive Data + Line Status */
Kojto 96:487b796308b0 3464
Kojto 96:487b796308b0 3465 /****************** Bit definition for USB_DADDR register *******************/
Kojto 96:487b796308b0 3466 #define USB_DADDR_ADD ((uint32_t)0x0000007F) /*!< ADD[6:0] bits (Device Address) */
Kojto 96:487b796308b0 3467 #define USB_DADDR_ADD0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 3468 #define USB_DADDR_ADD1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 3469 #define USB_DADDR_ADD2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 3470 #define USB_DADDR_ADD3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 96:487b796308b0 3471 #define USB_DADDR_ADD4 ((uint32_t)0x00000010) /*!< Bit 4 */
Kojto 96:487b796308b0 3472 #define USB_DADDR_ADD5 ((uint32_t)0x00000020) /*!< Bit 5 */
Kojto 96:487b796308b0 3473 #define USB_DADDR_ADD6 ((uint32_t)0x00000040) /*!< Bit 6 */
Kojto 96:487b796308b0 3474
Kojto 96:487b796308b0 3475 #define USB_DADDR_EF ((uint32_t)0x00000080) /*!< Enable Function */
Kojto 96:487b796308b0 3476
Kojto 96:487b796308b0 3477 /****************** Bit definition for USB_BTABLE register ******************/
Kojto 96:487b796308b0 3478 #define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) /*!< Buffer Table */
Kojto 96:487b796308b0 3479
Kojto 96:487b796308b0 3480 /*!< Buffer descriptor table */
Kojto 96:487b796308b0 3481 /***************** Bit definition for USB_ADDR0_TX register *****************/
Kojto 96:487b796308b0 3482 #define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 0 */
Kojto 96:487b796308b0 3483
Kojto 96:487b796308b0 3484 /***************** Bit definition for USB_ADDR1_TX register *****************/
Kojto 96:487b796308b0 3485 #define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 1 */
Kojto 96:487b796308b0 3486
Kojto 96:487b796308b0 3487 /***************** Bit definition for USB_ADDR2_TX register *****************/
Kojto 96:487b796308b0 3488 #define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 2 */
Kojto 96:487b796308b0 3489
Kojto 96:487b796308b0 3490 /***************** Bit definition for USB_ADDR3_TX register *****************/
Kojto 96:487b796308b0 3491 #define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 3 */
Kojto 96:487b796308b0 3492
Kojto 96:487b796308b0 3493 /***************** Bit definition for USB_ADDR4_TX register *****************/
Kojto 96:487b796308b0 3494 #define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 4 */
Kojto 96:487b796308b0 3495
Kojto 96:487b796308b0 3496 /***************** Bit definition for USB_ADDR5_TX register *****************/
Kojto 96:487b796308b0 3497 #define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 5 */
Kojto 96:487b796308b0 3498
Kojto 96:487b796308b0 3499 /***************** Bit definition for USB_ADDR6_TX register *****************/
Kojto 96:487b796308b0 3500 #define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 6 */
Kojto 96:487b796308b0 3501
Kojto 96:487b796308b0 3502 /***************** Bit definition for USB_ADDR7_TX register *****************/
Kojto 96:487b796308b0 3503 #define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 7 */
Kojto 96:487b796308b0 3504
Kojto 96:487b796308b0 3505 /*----------------------------------------------------------------------------*/
Kojto 96:487b796308b0 3506
Kojto 96:487b796308b0 3507 /***************** Bit definition for USB_COUNT0_TX register ****************/
Kojto 96:487b796308b0 3508 #define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 */
Kojto 96:487b796308b0 3509
Kojto 96:487b796308b0 3510 /***************** Bit definition for USB_COUNT1_TX register ****************/
Kojto 96:487b796308b0 3511 #define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 */
Kojto 96:487b796308b0 3512
Kojto 96:487b796308b0 3513 /***************** Bit definition for USB_COUNT2_TX register ****************/
Kojto 96:487b796308b0 3514 #define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 */
Kojto 96:487b796308b0 3515
Kojto 96:487b796308b0 3516 /***************** Bit definition for USB_COUNT3_TX register ****************/
Kojto 96:487b796308b0 3517 #define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 */
Kojto 96:487b796308b0 3518
Kojto 96:487b796308b0 3519 /***************** Bit definition for USB_COUNT4_TX register ****************/
Kojto 96:487b796308b0 3520 #define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 */
Kojto 96:487b796308b0 3521
Kojto 96:487b796308b0 3522 /***************** Bit definition for USB_COUNT5_TX register ****************/
Kojto 96:487b796308b0 3523 #define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 */
Kojto 96:487b796308b0 3524
Kojto 96:487b796308b0 3525 /***************** Bit definition for USB_COUNT6_TX register ****************/
Kojto 96:487b796308b0 3526 #define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 */
Kojto 96:487b796308b0 3527
Kojto 96:487b796308b0 3528 /***************** Bit definition for USB_COUNT7_TX register ****************/
Kojto 96:487b796308b0 3529 #define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 */
Kojto 96:487b796308b0 3530
Kojto 96:487b796308b0 3531 /*----------------------------------------------------------------------------*/
Kojto 96:487b796308b0 3532
Kojto 96:487b796308b0 3533 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
Kojto 96:487b796308b0 3534 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
Kojto 96:487b796308b0 3535
Kojto 96:487b796308b0 3536 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
Kojto 96:487b796308b0 3537 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
Kojto 96:487b796308b0 3538
Kojto 96:487b796308b0 3539 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
Kojto 96:487b796308b0 3540 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
Kojto 96:487b796308b0 3541
Kojto 96:487b796308b0 3542 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
Kojto 96:487b796308b0 3543 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
Kojto 96:487b796308b0 3544
Kojto 96:487b796308b0 3545 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
Kojto 96:487b796308b0 3546 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
Kojto 96:487b796308b0 3547
Kojto 96:487b796308b0 3548 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
Kojto 96:487b796308b0 3549 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
Kojto 96:487b796308b0 3550
Kojto 96:487b796308b0 3551 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
Kojto 96:487b796308b0 3552 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
Kojto 96:487b796308b0 3553
Kojto 96:487b796308b0 3554 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
Kojto 96:487b796308b0 3555 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
Kojto 96:487b796308b0 3556
Kojto 96:487b796308b0 3557 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
Kojto 96:487b796308b0 3558 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
Kojto 96:487b796308b0 3559
Kojto 96:487b796308b0 3560 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
Kojto 96:487b796308b0 3561 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
Kojto 96:487b796308b0 3562
Kojto 96:487b796308b0 3563 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
Kojto 96:487b796308b0 3564 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
Kojto 96:487b796308b0 3565
Kojto 96:487b796308b0 3566 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
Kojto 96:487b796308b0 3567 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
Kojto 96:487b796308b0 3568
Kojto 96:487b796308b0 3569 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
Kojto 96:487b796308b0 3570 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
Kojto 96:487b796308b0 3571
Kojto 96:487b796308b0 3572 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
Kojto 96:487b796308b0 3573 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
Kojto 96:487b796308b0 3574
Kojto 96:487b796308b0 3575 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
Kojto 96:487b796308b0 3576 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
Kojto 96:487b796308b0 3577
Kojto 96:487b796308b0 3578 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
Kojto 96:487b796308b0 3579 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
Kojto 96:487b796308b0 3580
Kojto 96:487b796308b0 3581 /*----------------------------------------------------------------------------*/
Kojto 96:487b796308b0 3582
Kojto 96:487b796308b0 3583 /***************** Bit definition for USB_ADDR0_RX register *****************/
Kojto 96:487b796308b0 3584 #define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 0 */
Kojto 96:487b796308b0 3585
Kojto 96:487b796308b0 3586 /***************** Bit definition for USB_ADDR1_RX register *****************/
Kojto 96:487b796308b0 3587 #define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 1 */
Kojto 96:487b796308b0 3588
Kojto 96:487b796308b0 3589 /***************** Bit definition for USB_ADDR2_RX register *****************/
Kojto 96:487b796308b0 3590 #define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 2 */
Kojto 96:487b796308b0 3591
Kojto 96:487b796308b0 3592 /***************** Bit definition for USB_ADDR3_RX register *****************/
Kojto 96:487b796308b0 3593 #define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 3 */
Kojto 96:487b796308b0 3594
Kojto 96:487b796308b0 3595 /***************** Bit definition for USB_ADDR4_RX register *****************/
Kojto 96:487b796308b0 3596 #define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 4 */
Kojto 96:487b796308b0 3597
Kojto 96:487b796308b0 3598 /***************** Bit definition for USB_ADDR5_RX register *****************/
Kojto 96:487b796308b0 3599 #define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 5 */
Kojto 96:487b796308b0 3600
Kojto 96:487b796308b0 3601 /***************** Bit definition for USB_ADDR6_RX register *****************/
Kojto 96:487b796308b0 3602 #define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 6 */
Kojto 96:487b796308b0 3603
Kojto 96:487b796308b0 3604 /***************** Bit definition for USB_ADDR7_RX register *****************/
Kojto 96:487b796308b0 3605 #define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 7 */
Kojto 96:487b796308b0 3606
Kojto 96:487b796308b0 3607 /*----------------------------------------------------------------------------*/
Kojto 96:487b796308b0 3608
Kojto 96:487b796308b0 3609 /***************** Bit definition for USB_COUNT0_RX register ****************/
Kojto 96:487b796308b0 3610 #define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
Kojto 96:487b796308b0 3611
Kojto 96:487b796308b0 3612 #define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 96:487b796308b0 3613 #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3614 #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3615 #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3616 #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3617 #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3618
Kojto 96:487b796308b0 3619 #define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
Kojto 96:487b796308b0 3620
Kojto 96:487b796308b0 3621 /***************** Bit definition for USB_COUNT1_RX register ****************/
Kojto 96:487b796308b0 3622 #define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
Kojto 96:487b796308b0 3623
Kojto 96:487b796308b0 3624 #define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 96:487b796308b0 3625 #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3626 #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3627 #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3628 #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3629 #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3630
Kojto 96:487b796308b0 3631 #define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
Kojto 96:487b796308b0 3632
Kojto 96:487b796308b0 3633 /***************** Bit definition for USB_COUNT2_RX register ****************/
Kojto 96:487b796308b0 3634 #define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
Kojto 96:487b796308b0 3635
Kojto 96:487b796308b0 3636 #define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 96:487b796308b0 3637 #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3638 #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3639 #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3640 #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3641 #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3642
Kojto 96:487b796308b0 3643 #define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
Kojto 96:487b796308b0 3644
Kojto 96:487b796308b0 3645 /***************** Bit definition for USB_COUNT3_RX register ****************/
Kojto 96:487b796308b0 3646 #define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
Kojto 96:487b796308b0 3647
Kojto 96:487b796308b0 3648 #define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 96:487b796308b0 3649 #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3650 #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3651 #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3652 #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3653 #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3654
Kojto 96:487b796308b0 3655 #define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
Kojto 96:487b796308b0 3656
Kojto 96:487b796308b0 3657 /***************** Bit definition for USB_COUNT4_RX register ****************/
Kojto 96:487b796308b0 3658 #define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
Kojto 96:487b796308b0 3659
Kojto 96:487b796308b0 3660 #define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 96:487b796308b0 3661 #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3662 #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3663 #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3664 #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3665 #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3666
Kojto 96:487b796308b0 3667 #define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
Kojto 96:487b796308b0 3668
Kojto 96:487b796308b0 3669 /***************** Bit definition for USB_COUNT5_RX register ****************/
Kojto 96:487b796308b0 3670 #define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
Kojto 96:487b796308b0 3671
Kojto 96:487b796308b0 3672 #define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 96:487b796308b0 3673 #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3674 #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3675 #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3676 #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3677 #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3678
Kojto 96:487b796308b0 3679 #define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
Kojto 96:487b796308b0 3680
Kojto 96:487b796308b0 3681 /***************** Bit definition for USB_COUNT6_RX register ****************/
Kojto 96:487b796308b0 3682 #define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
Kojto 96:487b796308b0 3683
Kojto 96:487b796308b0 3684 #define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 96:487b796308b0 3685 #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3686 #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3687 #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3688 #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3689 #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3690
Kojto 96:487b796308b0 3691 #define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
Kojto 96:487b796308b0 3692
Kojto 96:487b796308b0 3693 /***************** Bit definition for USB_COUNT7_RX register ****************/
Kojto 96:487b796308b0 3694 #define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
Kojto 96:487b796308b0 3695
Kojto 96:487b796308b0 3696 #define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 96:487b796308b0 3697 #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3698 #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3699 #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3700 #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3701 #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3702
Kojto 96:487b796308b0 3703 #define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
Kojto 96:487b796308b0 3704
Kojto 96:487b796308b0 3705 /*----------------------------------------------------------------------------*/
Kojto 96:487b796308b0 3706
Kojto 96:487b796308b0 3707 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
Kojto 96:487b796308b0 3708 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
Kojto 96:487b796308b0 3709
Kojto 96:487b796308b0 3710 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 96:487b796308b0 3711 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3712 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3713 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3714 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3715 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3716
Kojto 96:487b796308b0 3717 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
Kojto 96:487b796308b0 3718
Kojto 96:487b796308b0 3719 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
Kojto 96:487b796308b0 3720 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
Kojto 96:487b796308b0 3721
Kojto 96:487b796308b0 3722 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 96:487b796308b0 3723 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
Kojto 96:487b796308b0 3724 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 96:487b796308b0 3725 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
Kojto 96:487b796308b0 3726 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
Kojto 96:487b796308b0 3727 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
Kojto 96:487b796308b0 3728
Kojto 96:487b796308b0 3729 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
Kojto 96:487b796308b0 3730
Kojto 96:487b796308b0 3731 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
Kojto 96:487b796308b0 3732 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
Kojto 96:487b796308b0 3733
Kojto 96:487b796308b0 3734 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 96:487b796308b0 3735 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3736 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3737 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3738 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3739 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3740
Kojto 96:487b796308b0 3741 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
Kojto 96:487b796308b0 3742
Kojto 96:487b796308b0 3743 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
Kojto 96:487b796308b0 3744 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
Kojto 96:487b796308b0 3745
Kojto 96:487b796308b0 3746 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 96:487b796308b0 3747 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 96:487b796308b0 3748 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 96:487b796308b0 3749 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
Kojto 96:487b796308b0 3750 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
Kojto 96:487b796308b0 3751 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
Kojto 96:487b796308b0 3752
Kojto 96:487b796308b0 3753 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
Kojto 96:487b796308b0 3754
Kojto 96:487b796308b0 3755 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
Kojto 96:487b796308b0 3756 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
Kojto 96:487b796308b0 3757
Kojto 96:487b796308b0 3758 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 96:487b796308b0 3759 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3760 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3761 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3762 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3763 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3764
Kojto 96:487b796308b0 3765 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
Kojto 96:487b796308b0 3766
Kojto 96:487b796308b0 3767 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
Kojto 96:487b796308b0 3768 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
Kojto 96:487b796308b0 3769
Kojto 96:487b796308b0 3770 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 96:487b796308b0 3771 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 96:487b796308b0 3772 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 96:487b796308b0 3773 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
Kojto 96:487b796308b0 3774 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
Kojto 96:487b796308b0 3775 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
Kojto 96:487b796308b0 3776
Kojto 96:487b796308b0 3777 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
Kojto 96:487b796308b0 3778
Kojto 96:487b796308b0 3779 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
Kojto 96:487b796308b0 3780 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
Kojto 96:487b796308b0 3781
Kojto 96:487b796308b0 3782 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 96:487b796308b0 3783 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3784 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3785 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3786 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3787 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3788
Kojto 96:487b796308b0 3789 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
Kojto 96:487b796308b0 3790
Kojto 96:487b796308b0 3791 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
Kojto 96:487b796308b0 3792 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
Kojto 96:487b796308b0 3793
Kojto 96:487b796308b0 3794 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 96:487b796308b0 3795 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 96:487b796308b0 3796 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 96:487b796308b0 3797 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
Kojto 96:487b796308b0 3798 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
Kojto 96:487b796308b0 3799 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
Kojto 96:487b796308b0 3800
Kojto 96:487b796308b0 3801 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
Kojto 96:487b796308b0 3802
Kojto 96:487b796308b0 3803 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
Kojto 96:487b796308b0 3804 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
Kojto 96:487b796308b0 3805
Kojto 96:487b796308b0 3806 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 96:487b796308b0 3807 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3808 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3809 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3810 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3811 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3812
Kojto 96:487b796308b0 3813 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
Kojto 96:487b796308b0 3814
Kojto 96:487b796308b0 3815 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
Kojto 96:487b796308b0 3816 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
Kojto 96:487b796308b0 3817
Kojto 96:487b796308b0 3818 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 96:487b796308b0 3819 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 96:487b796308b0 3820 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 96:487b796308b0 3821 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
Kojto 96:487b796308b0 3822 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
Kojto 96:487b796308b0 3823 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
Kojto 96:487b796308b0 3824
Kojto 96:487b796308b0 3825 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
Kojto 96:487b796308b0 3826
Kojto 96:487b796308b0 3827 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
Kojto 96:487b796308b0 3828 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
Kojto 96:487b796308b0 3829
Kojto 96:487b796308b0 3830 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 96:487b796308b0 3831 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3832 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3833 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3834 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3835 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3836
Kojto 96:487b796308b0 3837 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
Kojto 96:487b796308b0 3838
Kojto 96:487b796308b0 3839 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
Kojto 96:487b796308b0 3840 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
Kojto 96:487b796308b0 3841
Kojto 96:487b796308b0 3842 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 96:487b796308b0 3843 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 96:487b796308b0 3844 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 96:487b796308b0 3845 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
Kojto 96:487b796308b0 3846 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
Kojto 96:487b796308b0 3847 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
Kojto 96:487b796308b0 3848
Kojto 96:487b796308b0 3849 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
Kojto 96:487b796308b0 3850
Kojto 96:487b796308b0 3851 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
Kojto 96:487b796308b0 3852 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
Kojto 96:487b796308b0 3853
Kojto 96:487b796308b0 3854 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 96:487b796308b0 3855 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3856 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3857 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3858 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3859 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3860
Kojto 96:487b796308b0 3861 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
Kojto 96:487b796308b0 3862
Kojto 96:487b796308b0 3863 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
Kojto 96:487b796308b0 3864 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
Kojto 96:487b796308b0 3865
Kojto 96:487b796308b0 3866 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 96:487b796308b0 3867 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 96:487b796308b0 3868 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 96:487b796308b0 3869 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
Kojto 96:487b796308b0 3870 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
Kojto 96:487b796308b0 3871 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
Kojto 96:487b796308b0 3872
Kojto 96:487b796308b0 3873 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
Kojto 96:487b796308b0 3874
Kojto 96:487b796308b0 3875 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
Kojto 96:487b796308b0 3876 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
Kojto 96:487b796308b0 3877
Kojto 96:487b796308b0 3878 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 96:487b796308b0 3879 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 96:487b796308b0 3880 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 96:487b796308b0 3881 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 96:487b796308b0 3882 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
Kojto 96:487b796308b0 3883 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
Kojto 96:487b796308b0 3884
Kojto 96:487b796308b0 3885 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
Kojto 96:487b796308b0 3886
Kojto 96:487b796308b0 3887 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
Kojto 96:487b796308b0 3888 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
Kojto 96:487b796308b0 3889
Kojto 96:487b796308b0 3890 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 96:487b796308b0 3891 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 96:487b796308b0 3892 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 96:487b796308b0 3893 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
Kojto 96:487b796308b0 3894 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
Kojto 96:487b796308b0 3895 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
Kojto 96:487b796308b0 3896
Kojto 96:487b796308b0 3897 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
Kojto 96:487b796308b0 3898
Kojto 96:487b796308b0 3899 /******************************************************************************/
Kojto 96:487b796308b0 3900 /* */
Kojto 96:487b796308b0 3901 /* Controller Area Network */
Kojto 96:487b796308b0 3902 /* */
Kojto 96:487b796308b0 3903 /******************************************************************************/
Kojto 96:487b796308b0 3904
Kojto 96:487b796308b0 3905 /*!< CAN control and status registers */
Kojto 96:487b796308b0 3906 /******************* Bit definition for CAN_MCR register ********************/
Kojto 96:487b796308b0 3907 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!< Initialization Request */
Kojto 96:487b796308b0 3908 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!< Sleep Mode Request */
Kojto 96:487b796308b0 3909 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!< Transmit FIFO Priority */
Kojto 96:487b796308b0 3910 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!< Receive FIFO Locked Mode */
Kojto 96:487b796308b0 3911 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!< No Automatic Retransmission */
Kojto 96:487b796308b0 3912 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!< Automatic Wakeup Mode */
Kojto 96:487b796308b0 3913 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!< Automatic Bus-Off Management */
Kojto 96:487b796308b0 3914 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!< Time Triggered Communication Mode */
Kojto 96:487b796308b0 3915 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!< CAN software master reset */
Kojto 96:487b796308b0 3916 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!< CAN Debug freeze */
Kojto 96:487b796308b0 3917
Kojto 96:487b796308b0 3918 /******************* Bit definition for CAN_MSR register ********************/
Kojto 96:487b796308b0 3919 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!< Initialization Acknowledge */
Kojto 96:487b796308b0 3920 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!< Sleep Acknowledge */
Kojto 96:487b796308b0 3921 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!< Error Interrupt */
Kojto 96:487b796308b0 3922 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!< Wakeup Interrupt */
Kojto 96:487b796308b0 3923 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!< Sleep Acknowledge Interrupt */
Kojto 96:487b796308b0 3924 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!< Transmit Mode */
Kojto 96:487b796308b0 3925 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!< Receive Mode */
Kojto 96:487b796308b0 3926 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!< Last Sample Point */
Kojto 96:487b796308b0 3927 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!< CAN Rx Signal */
Kojto 96:487b796308b0 3928
Kojto 96:487b796308b0 3929 /******************* Bit definition for CAN_TSR register ********************/
Kojto 96:487b796308b0 3930 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */
Kojto 96:487b796308b0 3931 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */
Kojto 96:487b796308b0 3932 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */
Kojto 96:487b796308b0 3933 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */
Kojto 96:487b796308b0 3934 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */
Kojto 96:487b796308b0 3935 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */
Kojto 96:487b796308b0 3936 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */
Kojto 96:487b796308b0 3937 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */
Kojto 96:487b796308b0 3938 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */
Kojto 96:487b796308b0 3939 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */
Kojto 96:487b796308b0 3940 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */
Kojto 96:487b796308b0 3941 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */
Kojto 96:487b796308b0 3942 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */
Kojto 96:487b796308b0 3943 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */
Kojto 96:487b796308b0 3944 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */
Kojto 96:487b796308b0 3945 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */
Kojto 96:487b796308b0 3946
Kojto 96:487b796308b0 3947 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */
Kojto 96:487b796308b0 3948 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */
Kojto 96:487b796308b0 3949 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */
Kojto 96:487b796308b0 3950 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */
Kojto 96:487b796308b0 3951
Kojto 96:487b796308b0 3952 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */
Kojto 96:487b796308b0 3953 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */
Kojto 96:487b796308b0 3954 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */
Kojto 96:487b796308b0 3955 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */
Kojto 96:487b796308b0 3956
Kojto 96:487b796308b0 3957 /******************* Bit definition for CAN_RF0R register *******************/
Kojto 96:487b796308b0 3958 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!< FIFO 0 Message Pending */
Kojto 96:487b796308b0 3959 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!< FIFO 0 Full */
Kojto 96:487b796308b0 3960 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!< FIFO 0 Overrun */
Kojto 96:487b796308b0 3961 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!< Release FIFO 0 Output Mailbox */
Kojto 96:487b796308b0 3962
Kojto 96:487b796308b0 3963 /******************* Bit definition for CAN_RF1R register *******************/
Kojto 96:487b796308b0 3964 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!< FIFO 1 Message Pending */
Kojto 96:487b796308b0 3965 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!< FIFO 1 Full */
Kojto 96:487b796308b0 3966 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!< FIFO 1 Overrun */
Kojto 96:487b796308b0 3967 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!< Release FIFO 1 Output Mailbox */
Kojto 96:487b796308b0 3968
Kojto 96:487b796308b0 3969 /******************** Bit definition for CAN_IER register *******************/
Kojto 96:487b796308b0 3970 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */
Kojto 96:487b796308b0 3971 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */
Kojto 96:487b796308b0 3972 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */
Kojto 96:487b796308b0 3973 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */
Kojto 96:487b796308b0 3974 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */
Kojto 96:487b796308b0 3975 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */
Kojto 96:487b796308b0 3976 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */
Kojto 96:487b796308b0 3977 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */
Kojto 96:487b796308b0 3978 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */
Kojto 96:487b796308b0 3979 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */
Kojto 96:487b796308b0 3980 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */
Kojto 96:487b796308b0 3981 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */
Kojto 96:487b796308b0 3982 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */
Kojto 96:487b796308b0 3983 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */
Kojto 96:487b796308b0 3984
Kojto 96:487b796308b0 3985 /******************** Bit definition for CAN_ESR register *******************/
Kojto 96:487b796308b0 3986 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */
Kojto 96:487b796308b0 3987 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */
Kojto 96:487b796308b0 3988 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */
Kojto 96:487b796308b0 3989
Kojto 96:487b796308b0 3990 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */
Kojto 96:487b796308b0 3991 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 96:487b796308b0 3992 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 96:487b796308b0 3993 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Kojto 96:487b796308b0 3994
Kojto 96:487b796308b0 3995 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */
Kojto 96:487b796308b0 3996 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */
Kojto 96:487b796308b0 3997
Kojto 96:487b796308b0 3998 /******************* Bit definition for CAN_BTR register ********************/
Kojto 96:487b796308b0 3999 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
Kojto 96:487b796308b0 4000 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
Kojto 96:487b796308b0 4001 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
Kojto 96:487b796308b0 4002 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
Kojto 96:487b796308b0 4003 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
Kojto 96:487b796308b0 4004 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
Kojto 96:487b796308b0 4005 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
Kojto 96:487b796308b0 4006 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
Kojto 96:487b796308b0 4007 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
Kojto 96:487b796308b0 4008 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
Kojto 96:487b796308b0 4009 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
Kojto 96:487b796308b0 4010 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
Kojto 96:487b796308b0 4011 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
Kojto 96:487b796308b0 4012 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
Kojto 96:487b796308b0 4013 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
Kojto 96:487b796308b0 4014
Kojto 96:487b796308b0 4015 /*!< Mailbox registers */
Kojto 96:487b796308b0 4016 /****************** Bit definition for CAN_TI0R register ********************/
Kojto 96:487b796308b0 4017 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
Kojto 96:487b796308b0 4018 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
Kojto 96:487b796308b0 4019 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
Kojto 96:487b796308b0 4020 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
Kojto 96:487b796308b0 4021 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
Kojto 96:487b796308b0 4022
Kojto 96:487b796308b0 4023 /****************** Bit definition for CAN_TDT0R register *******************/
Kojto 96:487b796308b0 4024 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
Kojto 96:487b796308b0 4025 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
Kojto 96:487b796308b0 4026 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
Kojto 96:487b796308b0 4027
Kojto 96:487b796308b0 4028 /****************** Bit definition for CAN_TDL0R register *******************/
Kojto 96:487b796308b0 4029 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
Kojto 96:487b796308b0 4030 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
Kojto 96:487b796308b0 4031 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
Kojto 96:487b796308b0 4032 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
Kojto 96:487b796308b0 4033
Kojto 96:487b796308b0 4034 /****************** Bit definition for CAN_TDH0R register *******************/
Kojto 96:487b796308b0 4035 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
Kojto 96:487b796308b0 4036 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
Kojto 96:487b796308b0 4037 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
Kojto 96:487b796308b0 4038 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
Kojto 96:487b796308b0 4039
Kojto 96:487b796308b0 4040 /******************* Bit definition for CAN_TI1R register *******************/
Kojto 96:487b796308b0 4041 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
Kojto 96:487b796308b0 4042 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
Kojto 96:487b796308b0 4043 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
Kojto 96:487b796308b0 4044 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
Kojto 96:487b796308b0 4045 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
Kojto 96:487b796308b0 4046
Kojto 96:487b796308b0 4047 /******************* Bit definition for CAN_TDT1R register ******************/
Kojto 96:487b796308b0 4048 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
Kojto 96:487b796308b0 4049 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
Kojto 96:487b796308b0 4050 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
Kojto 96:487b796308b0 4051
Kojto 96:487b796308b0 4052 /******************* Bit definition for CAN_TDL1R register ******************/
Kojto 96:487b796308b0 4053 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
Kojto 96:487b796308b0 4054 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
Kojto 96:487b796308b0 4055 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
Kojto 96:487b796308b0 4056 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
Kojto 96:487b796308b0 4057
Kojto 96:487b796308b0 4058 /******************* Bit definition for CAN_TDH1R register ******************/
Kojto 96:487b796308b0 4059 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
Kojto 96:487b796308b0 4060 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
Kojto 96:487b796308b0 4061 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
Kojto 96:487b796308b0 4062 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
Kojto 96:487b796308b0 4063
Kojto 96:487b796308b0 4064 /******************* Bit definition for CAN_TI2R register *******************/
Kojto 96:487b796308b0 4065 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
Kojto 96:487b796308b0 4066 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
Kojto 96:487b796308b0 4067 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
Kojto 96:487b796308b0 4068 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
Kojto 96:487b796308b0 4069 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
Kojto 96:487b796308b0 4070
Kojto 96:487b796308b0 4071 /******************* Bit definition for CAN_TDT2R register ******************/
Kojto 96:487b796308b0 4072 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
Kojto 96:487b796308b0 4073 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
Kojto 96:487b796308b0 4074 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
Kojto 96:487b796308b0 4075
Kojto 96:487b796308b0 4076 /******************* Bit definition for CAN_TDL2R register ******************/
Kojto 96:487b796308b0 4077 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
Kojto 96:487b796308b0 4078 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
Kojto 96:487b796308b0 4079 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
Kojto 96:487b796308b0 4080 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
Kojto 96:487b796308b0 4081
Kojto 96:487b796308b0 4082 /******************* Bit definition for CAN_TDH2R register ******************/
Kojto 96:487b796308b0 4083 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
Kojto 96:487b796308b0 4084 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
Kojto 96:487b796308b0 4085 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
Kojto 96:487b796308b0 4086 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
Kojto 96:487b796308b0 4087
Kojto 96:487b796308b0 4088 /******************* Bit definition for CAN_RI0R register *******************/
Kojto 96:487b796308b0 4089 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
Kojto 96:487b796308b0 4090 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
Kojto 96:487b796308b0 4091 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
Kojto 96:487b796308b0 4092 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
Kojto 96:487b796308b0 4093
Kojto 96:487b796308b0 4094 /******************* Bit definition for CAN_RDT0R register ******************/
Kojto 96:487b796308b0 4095 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
Kojto 96:487b796308b0 4096 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
Kojto 96:487b796308b0 4097 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
Kojto 96:487b796308b0 4098
Kojto 96:487b796308b0 4099 /******************* Bit definition for CAN_RDL0R register ******************/
Kojto 96:487b796308b0 4100 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
Kojto 96:487b796308b0 4101 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
Kojto 96:487b796308b0 4102 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
Kojto 96:487b796308b0 4103 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
Kojto 96:487b796308b0 4104
Kojto 96:487b796308b0 4105 /******************* Bit definition for CAN_RDH0R register ******************/
Kojto 96:487b796308b0 4106 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
Kojto 96:487b796308b0 4107 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
Kojto 96:487b796308b0 4108 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
Kojto 96:487b796308b0 4109 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
Kojto 96:487b796308b0 4110
Kojto 96:487b796308b0 4111 /******************* Bit definition for CAN_RI1R register *******************/
Kojto 96:487b796308b0 4112 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
Kojto 96:487b796308b0 4113 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
Kojto 96:487b796308b0 4114 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
Kojto 96:487b796308b0 4115 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
Kojto 96:487b796308b0 4116
Kojto 96:487b796308b0 4117 /******************* Bit definition for CAN_RDT1R register ******************/
Kojto 96:487b796308b0 4118 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
Kojto 96:487b796308b0 4119 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
Kojto 96:487b796308b0 4120 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
Kojto 96:487b796308b0 4121
Kojto 96:487b796308b0 4122 /******************* Bit definition for CAN_RDL1R register ******************/
Kojto 96:487b796308b0 4123 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
Kojto 96:487b796308b0 4124 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
Kojto 96:487b796308b0 4125 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
Kojto 96:487b796308b0 4126 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
Kojto 96:487b796308b0 4127
Kojto 96:487b796308b0 4128 /******************* Bit definition for CAN_RDH1R register ******************/
Kojto 96:487b796308b0 4129 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
Kojto 96:487b796308b0 4130 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
Kojto 96:487b796308b0 4131 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
Kojto 96:487b796308b0 4132 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
Kojto 96:487b796308b0 4133
Kojto 96:487b796308b0 4134 /*!< CAN filter registers */
Kojto 96:487b796308b0 4135 /******************* Bit definition for CAN_FMR register ********************/
Kojto 96:487b796308b0 4136 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!< Filter Init Mode */
Kojto 96:487b796308b0 4137 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!< CAN2 start bank */
Kojto 96:487b796308b0 4138
Kojto 96:487b796308b0 4139 /******************* Bit definition for CAN_FM1R register *******************/
Kojto 96:487b796308b0 4140 #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!< Filter Mode */
Kojto 96:487b796308b0 4141 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!< Filter Init Mode for filter 0 */
Kojto 96:487b796308b0 4142 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!< Filter Init Mode for filter 1 */
Kojto 96:487b796308b0 4143 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!< Filter Init Mode for filter 2 */
Kojto 96:487b796308b0 4144 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!< Filter Init Mode for filter 3 */
Kojto 96:487b796308b0 4145 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!< Filter Init Mode for filter 4 */
Kojto 96:487b796308b0 4146 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!< Filter Init Mode for filter 5 */
Kojto 96:487b796308b0 4147 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!< Filter Init Mode for filter 6 */
Kojto 96:487b796308b0 4148 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!< Filter Init Mode for filter 7 */
Kojto 96:487b796308b0 4149 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!< Filter Init Mode for filter 8 */
Kojto 96:487b796308b0 4150 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!< Filter Init Mode for filter 9 */
Kojto 96:487b796308b0 4151 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!< Filter Init Mode for filter 10 */
Kojto 96:487b796308b0 4152 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!< Filter Init Mode for filter 11 */
Kojto 96:487b796308b0 4153 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!< Filter Init Mode for filter 12 */
Kojto 96:487b796308b0 4154 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!< Filter Init Mode for filter 13 */
Kojto 96:487b796308b0 4155
Kojto 96:487b796308b0 4156 /******************* Bit definition for CAN_FS1R register *******************/
Kojto 96:487b796308b0 4157 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!< Filter Scale Configuration */
Kojto 96:487b796308b0 4158 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!< Filter Scale Configuration for filter 0 */
Kojto 96:487b796308b0 4159 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!< Filter Scale Configuration for filter 1 */
Kojto 96:487b796308b0 4160 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!< Filter Scale Configuration for filter 2 */
Kojto 96:487b796308b0 4161 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!< Filter Scale Configuration for filter 3 */
Kojto 96:487b796308b0 4162 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!< Filter Scale Configuration for filter 4 */
Kojto 96:487b796308b0 4163 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!< Filter Scale Configuration for filter 5 */
Kojto 96:487b796308b0 4164 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!< Filter Scale Configuration for filter 6 */
Kojto 96:487b796308b0 4165 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!< Filter Scale Configuration for filter 7 */
Kojto 96:487b796308b0 4166 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!< Filter Scale Configuration for filter 8 */
Kojto 96:487b796308b0 4167 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!< Filter Scale Configuration for filter 9 */
Kojto 96:487b796308b0 4168 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!< Filter Scale Configuration for filter 10 */
Kojto 96:487b796308b0 4169 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!< Filter Scale Configuration for filter 11 */
Kojto 96:487b796308b0 4170 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!< Filter Scale Configuration for filter 12 */
Kojto 96:487b796308b0 4171 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!< Filter Scale Configuration for filter 13 */
Kojto 96:487b796308b0 4172
Kojto 96:487b796308b0 4173 /****************** Bit definition for CAN_FFA1R register *******************/
Kojto 96:487b796308b0 4174 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!< Filter FIFO Assignment */
Kojto 96:487b796308b0 4175 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!< Filter FIFO Assignment for filter 0 */
Kojto 96:487b796308b0 4176 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!< Filter FIFO Assignment for filter 1 */
Kojto 96:487b796308b0 4177 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!< Filter FIFO Assignment for filter 2 */
Kojto 96:487b796308b0 4178 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!< Filter FIFO Assignment for filter 3 */
Kojto 96:487b796308b0 4179 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!< Filter FIFO Assignment for filter 4 */
Kojto 96:487b796308b0 4180 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!< Filter FIFO Assignment for filter 5 */
Kojto 96:487b796308b0 4181 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!< Filter FIFO Assignment for filter 6 */
Kojto 96:487b796308b0 4182 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!< Filter FIFO Assignment for filter 7 */
Kojto 96:487b796308b0 4183 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!< Filter FIFO Assignment for filter 8 */
Kojto 96:487b796308b0 4184 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!< Filter FIFO Assignment for filter 9 */
Kojto 96:487b796308b0 4185 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!< Filter FIFO Assignment for filter 10 */
Kojto 96:487b796308b0 4186 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!< Filter FIFO Assignment for filter 11 */
Kojto 96:487b796308b0 4187 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!< Filter FIFO Assignment for filter 12 */
Kojto 96:487b796308b0 4188 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!< Filter FIFO Assignment for filter 13 */
Kojto 96:487b796308b0 4189
Kojto 96:487b796308b0 4190 /******************* Bit definition for CAN_FA1R register *******************/
Kojto 96:487b796308b0 4191 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!< Filter Active */
Kojto 96:487b796308b0 4192 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!< Filter 0 Active */
Kojto 96:487b796308b0 4193 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!< Filter 1 Active */
Kojto 96:487b796308b0 4194 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!< Filter 2 Active */
Kojto 96:487b796308b0 4195 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!< Filter 3 Active */
Kojto 96:487b796308b0 4196 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!< Filter 4 Active */
Kojto 96:487b796308b0 4197 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!< Filter 5 Active */
Kojto 96:487b796308b0 4198 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!< Filter 6 Active */
Kojto 96:487b796308b0 4199 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!< Filter 7 Active */
Kojto 96:487b796308b0 4200 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!< Filter 8 Active */
Kojto 96:487b796308b0 4201 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!< Filter 9 Active */
Kojto 96:487b796308b0 4202 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!< Filter 10 Active */
Kojto 96:487b796308b0 4203 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!< Filter 11 Active */
Kojto 96:487b796308b0 4204 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!< Filter 12 Active */
Kojto 96:487b796308b0 4205 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!< Filter 13 Active */
Kojto 96:487b796308b0 4206
Kojto 96:487b796308b0 4207 /******************* Bit definition for CAN_F0R1 register *******************/
Kojto 96:487b796308b0 4208 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4209 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4210 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4211 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4212 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4213 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4214 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4215 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4216 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4217 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4218 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4219 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4220 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4221 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4222 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4223 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4224 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4225 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4226 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4227 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4228 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4229 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4230 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4231 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4232 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4233 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4234 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4235 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4236 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4237 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4238 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4239 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4240
Kojto 96:487b796308b0 4241 /******************* Bit definition for CAN_F1R1 register *******************/
Kojto 96:487b796308b0 4242 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4243 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4244 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4245 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4246 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4247 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4248 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4249 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4250 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4251 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4252 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4253 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4254 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4255 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4256 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4257 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4258 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4259 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4260 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4261 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4262 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4263 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4264 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4265 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4266 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4267 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4268 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4269 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4270 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4271 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4272 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4273 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4274
Kojto 96:487b796308b0 4275 /******************* Bit definition for CAN_F2R1 register *******************/
Kojto 96:487b796308b0 4276 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4277 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4278 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4279 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4280 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4281 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4282 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4283 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4284 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4285 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4286 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4287 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4288 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4289 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4290 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4291 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4292 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4293 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4294 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4295 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4296 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4297 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4298 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4299 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4300 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4301 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4302 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4303 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4304 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4305 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4306 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4307 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4308
Kojto 96:487b796308b0 4309 /******************* Bit definition for CAN_F3R1 register *******************/
Kojto 96:487b796308b0 4310 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4311 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4312 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4313 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4314 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4315 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4316 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4317 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4318 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4319 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4320 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4321 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4322 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4323 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4324 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4325 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4326 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4327 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4328 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4329 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4330 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4331 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4332 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4333 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4334 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4335 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4336 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4337 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4338 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4339 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4340 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4341 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4342
Kojto 96:487b796308b0 4343 /******************* Bit definition for CAN_F4R1 register *******************/
Kojto 96:487b796308b0 4344 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4345 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4346 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4347 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4348 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4349 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4350 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4351 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4352 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4353 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4354 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4355 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4356 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4357 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4358 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4359 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4360 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4361 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4362 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4363 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4364 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4365 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4366 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4367 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4368 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4369 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4370 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4371 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4372 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4373 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4374 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4375 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4376
Kojto 96:487b796308b0 4377 /******************* Bit definition for CAN_F5R1 register *******************/
Kojto 96:487b796308b0 4378 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4379 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4380 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4381 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4382 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4383 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4384 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4385 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4386 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4387 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4388 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4389 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4390 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4391 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4392 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4393 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4394 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4395 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4396 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4397 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4398 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4399 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4400 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4401 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4402 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4403 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4404 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4405 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4406 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4407 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4408 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4409 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4410
Kojto 96:487b796308b0 4411 /******************* Bit definition for CAN_F6R1 register *******************/
Kojto 96:487b796308b0 4412 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4413 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4414 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4415 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4416 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4417 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4418 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4419 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4420 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4421 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4422 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4423 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4424 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4425 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4426 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4427 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4428 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4429 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4430 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4431 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4432 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4433 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4434 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4435 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4436 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4437 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4438 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4439 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4440 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4441 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4442 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4443 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4444
Kojto 96:487b796308b0 4445 /******************* Bit definition for CAN_F7R1 register *******************/
Kojto 96:487b796308b0 4446 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4447 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4448 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4449 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4450 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4451 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4452 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4453 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4454 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4455 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4456 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4457 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4458 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4459 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4460 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4461 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4462 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4463 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4464 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4465 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4466 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4467 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4468 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4469 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4470 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4471 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4472 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4473 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4474 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4475 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4476 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4477 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4478
Kojto 96:487b796308b0 4479 /******************* Bit definition for CAN_F8R1 register *******************/
Kojto 96:487b796308b0 4480 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4481 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4482 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4483 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4484 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4485 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4486 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4487 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4488 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4489 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4490 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4491 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4492 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4493 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4494 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4495 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4496 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4497 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4498 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4499 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4500 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4501 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4502 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4503 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4504 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4505 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4506 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4507 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4508 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4509 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4510 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4511 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4512
Kojto 96:487b796308b0 4513 /******************* Bit definition for CAN_F9R1 register *******************/
Kojto 96:487b796308b0 4514 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4515 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4516 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4517 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4518 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4519 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4520 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4521 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4522 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4523 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4524 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4525 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4526 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4527 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4528 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4529 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4530 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4531 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4532 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4533 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4534 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4535 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4536 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4537 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4538 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4539 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4540 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4541 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4542 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4543 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4544 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4545 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4546
Kojto 96:487b796308b0 4547 /******************* Bit definition for CAN_F10R1 register ******************/
Kojto 96:487b796308b0 4548 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4549 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4550 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4551 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4552 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4553 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4554 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4555 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4556 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4557 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4558 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4559 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4560 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4561 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4562 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4563 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4564 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4565 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4566 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4567 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4568 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4569 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4570 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4571 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4572 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4573 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4574 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4575 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4576 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4577 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4578 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4579 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4580
Kojto 96:487b796308b0 4581 /******************* Bit definition for CAN_F11R1 register ******************/
Kojto 96:487b796308b0 4582 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4583 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4584 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4585 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4586 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4587 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4588 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4589 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4590 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4591 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4592 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4593 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4594 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4595 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4596 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4597 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4598 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4599 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4600 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4601 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4602 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4603 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4604 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4605 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4606 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4607 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4608 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4609 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4610 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4611 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4612 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4613 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4614
Kojto 96:487b796308b0 4615 /******************* Bit definition for CAN_F12R1 register ******************/
Kojto 96:487b796308b0 4616 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4617 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4618 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4619 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4620 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4621 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4622 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4623 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4624 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4625 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4626 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4627 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4628 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4629 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4630 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4631 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4632 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4633 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4634 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4635 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4636 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4637 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4638 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4639 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4640 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4641 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4642 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4643 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4644 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4645 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4646 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4647 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4648
Kojto 96:487b796308b0 4649 /******************* Bit definition for CAN_F13R1 register ******************/
Kojto 96:487b796308b0 4650 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4651 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4652 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4653 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4654 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4655 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4656 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4657 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4658 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4659 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4660 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4661 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4662 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4663 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4664 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4665 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4666 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4667 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4668 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4669 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4670 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4671 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4672 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4673 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4674 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4675 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4676 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4677 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4678 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4679 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4680 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4681 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4682
Kojto 96:487b796308b0 4683 /******************* Bit definition for CAN_F0R2 register *******************/
Kojto 96:487b796308b0 4684 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4685 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4686 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4687 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4688 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4689 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4690 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4691 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4692 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4693 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4694 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4695 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4696 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4697 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4698 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4699 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4700 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4701 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4702 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4703 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4704 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4705 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4706 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4707 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4708 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4709 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4710 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4711 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4712 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4713 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4714 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4715 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4716
Kojto 96:487b796308b0 4717 /******************* Bit definition for CAN_F1R2 register *******************/
Kojto 96:487b796308b0 4718 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4719 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4720 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4721 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4722 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4723 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4724 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4725 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4726 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4727 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4728 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4729 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4730 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4731 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4732 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4733 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4734 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4735 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4736 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4737 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4738 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4739 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4740 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4741 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4742 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4743 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4744 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4745 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4746 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4747 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4748 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4749 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4750
Kojto 96:487b796308b0 4751 /******************* Bit definition for CAN_F2R2 register *******************/
Kojto 96:487b796308b0 4752 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4753 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4754 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4755 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4756 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4757 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4758 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4759 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4760 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4761 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4762 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4763 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4764 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4765 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4766 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4767 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4768 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4769 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4770 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4771 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4772 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4773 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4774 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4775 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4776 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4777 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4778 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4779 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4780 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4781 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4782 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4783 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4784
Kojto 96:487b796308b0 4785 /******************* Bit definition for CAN_F3R2 register *******************/
Kojto 96:487b796308b0 4786 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4787 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4788 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4789 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4790 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4791 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4792 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4793 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4794 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4795 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4796 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4797 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4798 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4799 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4800 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4801 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4802 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4803 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4804 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4805 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4806 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4807 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4808 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4809 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4810 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4811 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4812 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4813 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4814 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4815 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4816 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4817 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4818
Kojto 96:487b796308b0 4819 /******************* Bit definition for CAN_F4R2 register *******************/
Kojto 96:487b796308b0 4820 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4821 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4822 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4823 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4824 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4825 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4826 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4827 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4828 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4829 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4830 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4831 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4832 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4833 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4834 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4835 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4836 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4837 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4838 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4839 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4840 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4841 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4842 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4843 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4844 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4845 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4846 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4847 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4848 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4849 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4850 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4851 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4852
Kojto 96:487b796308b0 4853 /******************* Bit definition for CAN_F5R2 register *******************/
Kojto 96:487b796308b0 4854 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4855 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4856 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4857 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4858 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4859 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4860 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4861 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4862 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4863 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4864 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4865 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4866 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4867 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4868 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4869 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4870 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4871 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4872 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4873 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4874 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4875 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4876 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4877 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4878 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4879 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4880 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4881 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4882 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4883 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4884 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4885 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4886
Kojto 96:487b796308b0 4887 /******************* Bit definition for CAN_F6R2 register *******************/
Kojto 96:487b796308b0 4888 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4889 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4890 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4891 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4892 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4893 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4894 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4895 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4896 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4897 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4898 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4899 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4900 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4901 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4902 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4903 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4904 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4905 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4906 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4907 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4908 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4909 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4910 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4911 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4912 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4913 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4914 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4915 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4916 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4917 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4918 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4919 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4920
Kojto 96:487b796308b0 4921 /******************* Bit definition for CAN_F7R2 register *******************/
Kojto 96:487b796308b0 4922 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4923 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4924 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4925 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4926 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4927 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4928 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4929 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4930 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4931 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4932 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4933 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4934 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4935 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4936 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4937 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4938 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4939 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4940 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4941 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4942 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4943 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4944 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4945 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4946 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4947 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4948 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4949 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4950 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4951 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4952 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4953 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4954
Kojto 96:487b796308b0 4955 /******************* Bit definition for CAN_F8R2 register *******************/
Kojto 96:487b796308b0 4956 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4957 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4958 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4959 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4960 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4961 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4962 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4963 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4964 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4965 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 4966 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 4967 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 4968 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 4969 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 4970 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 4971 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 4972 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 4973 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 4974 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 4975 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 4976 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 4977 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 4978 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 4979 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 4980 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 4981 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 4982 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 4983 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 4984 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 4985 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 4986 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 4987 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 4988
Kojto 96:487b796308b0 4989 /******************* Bit definition for CAN_F9R2 register *******************/
Kojto 96:487b796308b0 4990 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 4991 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 4992 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 4993 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 4994 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 4995 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 4996 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 4997 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 4998 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 4999 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 5000 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 5001 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 5002 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 5003 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 5004 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 5005 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 5006 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 5007 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 5008 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 5009 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 5010 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 5011 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 5012 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 5013 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 5014 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 5015 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 5016 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 5017 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 5018 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 5019 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 5020 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 5021 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 5022
Kojto 96:487b796308b0 5023 /******************* Bit definition for CAN_F10R2 register ******************/
Kojto 96:487b796308b0 5024 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 5025 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 5026 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 5027 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 5028 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 5029 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 5030 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 5031 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 5032 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 5033 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 5034 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 5035 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 5036 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 5037 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 5038 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 5039 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 5040 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 5041 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 5042 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 5043 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 5044 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 5045 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 5046 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 5047 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 5048 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 5049 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 5050 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 5051 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 5052 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 5053 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 5054 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 5055 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 5056
Kojto 96:487b796308b0 5057 /******************* Bit definition for CAN_F11R2 register ******************/
Kojto 96:487b796308b0 5058 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 5059 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 5060 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 5061 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 5062 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 5063 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 5064 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 5065 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 5066 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 5067 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 5068 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 5069 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 5070 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 5071 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 5072 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 5073 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 5074 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 5075 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 5076 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 5077 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 5078 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 5079 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 5080 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 5081 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 5082 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 5083 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 5084 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 5085 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 5086 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 5087 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 5088 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 5089 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 5090
Kojto 96:487b796308b0 5091 /******************* Bit definition for CAN_F12R2 register ******************/
Kojto 96:487b796308b0 5092 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 5093 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 5094 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 5095 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 5096 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 5097 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 5098 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 5099 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 5100 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 5101 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 5102 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 5103 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 5104 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 5105 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 5106 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 5107 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 5108 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 5109 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 5110 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 5111 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 5112 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 5113 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 5114 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 5115 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 5116 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 5117 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 5118 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 5119 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 5120 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 5121 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 5122 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 5123 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 5124
Kojto 96:487b796308b0 5125 /******************* Bit definition for CAN_F13R2 register ******************/
Kojto 96:487b796308b0 5126 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
Kojto 96:487b796308b0 5127 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
Kojto 96:487b796308b0 5128 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
Kojto 96:487b796308b0 5129 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
Kojto 96:487b796308b0 5130 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
Kojto 96:487b796308b0 5131 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
Kojto 96:487b796308b0 5132 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
Kojto 96:487b796308b0 5133 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
Kojto 96:487b796308b0 5134 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
Kojto 96:487b796308b0 5135 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
Kojto 96:487b796308b0 5136 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
Kojto 96:487b796308b0 5137 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
Kojto 96:487b796308b0 5138 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
Kojto 96:487b796308b0 5139 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
Kojto 96:487b796308b0 5140 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
Kojto 96:487b796308b0 5141 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
Kojto 96:487b796308b0 5142 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
Kojto 96:487b796308b0 5143 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
Kojto 96:487b796308b0 5144 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
Kojto 96:487b796308b0 5145 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
Kojto 96:487b796308b0 5146 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
Kojto 96:487b796308b0 5147 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
Kojto 96:487b796308b0 5148 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
Kojto 96:487b796308b0 5149 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
Kojto 96:487b796308b0 5150 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
Kojto 96:487b796308b0 5151 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
Kojto 96:487b796308b0 5152 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
Kojto 96:487b796308b0 5153 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
Kojto 96:487b796308b0 5154 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
Kojto 96:487b796308b0 5155 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
Kojto 96:487b796308b0 5156 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
Kojto 96:487b796308b0 5157 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
Kojto 96:487b796308b0 5158
Kojto 96:487b796308b0 5159 /******************************************************************************/
Kojto 96:487b796308b0 5160 /* */
Kojto 96:487b796308b0 5161 /* Serial Peripheral Interface */
Kojto 96:487b796308b0 5162 /* */
Kojto 96:487b796308b0 5163 /******************************************************************************/
Kojto 96:487b796308b0 5164
Kojto 96:487b796308b0 5165 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 96:487b796308b0 5166 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
Kojto 96:487b796308b0 5167 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
Kojto 96:487b796308b0 5168 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
Kojto 96:487b796308b0 5169
Kojto 96:487b796308b0 5170 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
Kojto 96:487b796308b0 5171 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 96:487b796308b0 5172 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 96:487b796308b0 5173 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
Kojto 96:487b796308b0 5174
Kojto 96:487b796308b0 5175 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
Kojto 96:487b796308b0 5176 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
Kojto 96:487b796308b0 5177 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
Kojto 96:487b796308b0 5178 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
Kojto 96:487b796308b0 5179 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
Kojto 96:487b796308b0 5180 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
Kojto 96:487b796308b0 5181 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
Kojto 96:487b796308b0 5182 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
Kojto 96:487b796308b0 5183 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
Kojto 96:487b796308b0 5184 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
Kojto 96:487b796308b0 5185
Kojto 96:487b796308b0 5186 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 96:487b796308b0 5187 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
Kojto 96:487b796308b0 5188 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
Kojto 96:487b796308b0 5189 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
Kojto 96:487b796308b0 5190 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
Kojto 96:487b796308b0 5191 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
Kojto 96:487b796308b0 5192 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
Kojto 96:487b796308b0 5193
Kojto 96:487b796308b0 5194 /******************** Bit definition for SPI_SR register ********************/
Kojto 96:487b796308b0 5195 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
Kojto 96:487b796308b0 5196 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
Kojto 96:487b796308b0 5197 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
Kojto 96:487b796308b0 5198 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
Kojto 96:487b796308b0 5199 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
Kojto 96:487b796308b0 5200 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
Kojto 96:487b796308b0 5201 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
Kojto 96:487b796308b0 5202 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
Kojto 96:487b796308b0 5203
Kojto 96:487b796308b0 5204 /******************** Bit definition for SPI_DR register ********************/
Kojto 96:487b796308b0 5205 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
Kojto 96:487b796308b0 5206
Kojto 96:487b796308b0 5207 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 96:487b796308b0 5208 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
Kojto 96:487b796308b0 5209
Kojto 96:487b796308b0 5210 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 96:487b796308b0 5211 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
Kojto 96:487b796308b0 5212
Kojto 96:487b796308b0 5213 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 96:487b796308b0 5214 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
Kojto 96:487b796308b0 5215
Kojto 96:487b796308b0 5216 /****************** Bit definition for SPI_I2SCFGR register *****************/
Kojto 96:487b796308b0 5217 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!< I2S mode selection */
Kojto 96:487b796308b0 5218
Kojto 96:487b796308b0 5219
Kojto 96:487b796308b0 5220 /******************************************************************************/
Kojto 96:487b796308b0 5221 /* */
Kojto 96:487b796308b0 5222 /* Inter-integrated Circuit Interface */
Kojto 96:487b796308b0 5223 /* */
Kojto 96:487b796308b0 5224 /******************************************************************************/
Kojto 96:487b796308b0 5225
Kojto 96:487b796308b0 5226 /******************* Bit definition for I2C_CR1 register ********************/
Kojto 96:487b796308b0 5227 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */
Kojto 96:487b796308b0 5228 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!< SMBus Mode */
Kojto 96:487b796308b0 5229 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!< SMBus Type */
Kojto 96:487b796308b0 5230 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!< ARP Enable */
Kojto 96:487b796308b0 5231 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!< PEC Enable */
Kojto 96:487b796308b0 5232 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!< General Call Enable */
Kojto 96:487b796308b0 5233 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!< Clock Stretching Disable (Slave mode) */
Kojto 96:487b796308b0 5234 #define I2C_CR1_START ((uint32_t)0x00000100) /*!< Start Generation */
Kojto 96:487b796308b0 5235 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!< Stop Generation */
Kojto 96:487b796308b0 5236 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!< Acknowledge Enable */
Kojto 96:487b796308b0 5237 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!< Acknowledge/PEC Position (for data reception) */
Kojto 96:487b796308b0 5238 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!< Packet Error Checking */
Kojto 96:487b796308b0 5239 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!< SMBus Alert */
Kojto 96:487b796308b0 5240 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!< Software Reset */
Kojto 96:487b796308b0 5241
Kojto 96:487b796308b0 5242 /******************* Bit definition for I2C_CR2 register ********************/
Kojto 96:487b796308b0 5243 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
Kojto 96:487b796308b0 5244 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 5245 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 5246 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 5247 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 96:487b796308b0 5248 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!< Bit 4 */
Kojto 96:487b796308b0 5249 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!< Bit 5 */
Kojto 96:487b796308b0 5250
Kojto 96:487b796308b0 5251 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!< Error Interrupt Enable */
Kojto 96:487b796308b0 5252 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!< Event Interrupt Enable */
Kojto 96:487b796308b0 5253 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!< Buffer Interrupt Enable */
Kojto 96:487b796308b0 5254 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!< DMA Requests Enable */
Kojto 96:487b796308b0 5255 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!< DMA Last Transfer */
Kojto 96:487b796308b0 5256
Kojto 96:487b796308b0 5257 /******************* Bit definition for I2C_OAR1 register *******************/
Kojto 96:487b796308b0 5258 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
Kojto 96:487b796308b0 5259 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
Kojto 96:487b796308b0 5260
Kojto 96:487b796308b0 5261 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 5262 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 5263 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 5264 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 96:487b796308b0 5265 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!< Bit 4 */
Kojto 96:487b796308b0 5266 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!< Bit 5 */
Kojto 96:487b796308b0 5267 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!< Bit 6 */
Kojto 96:487b796308b0 5268 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!< Bit 7 */
Kojto 96:487b796308b0 5269 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!< Bit 8 */
Kojto 96:487b796308b0 5270 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!< Bit 9 */
Kojto 96:487b796308b0 5271
Kojto 96:487b796308b0 5272 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!< Addressing Mode (Slave mode) */
Kojto 96:487b796308b0 5273
Kojto 96:487b796308b0 5274 /******************* Bit definition for I2C_OAR2 register *******************/
Kojto 96:487b796308b0 5275 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!< Dual addressing mode enable */
Kojto 96:487b796308b0 5276 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!< Interface address */
Kojto 96:487b796308b0 5277
Kojto 96:487b796308b0 5278 /******************* Bit definition for I2C_SR1 register ********************/
Kojto 96:487b796308b0 5279 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!< Start Bit (Master mode) */
Kojto 96:487b796308b0 5280 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!< Address sent (master mode)/matched (slave mode) */
Kojto 96:487b796308b0 5281 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!< Byte Transfer Finished */
Kojto 96:487b796308b0 5282 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!< 10-bit header sent (Master mode) */
Kojto 96:487b796308b0 5283 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!< Stop detection (Slave mode) */
Kojto 96:487b796308b0 5284 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!< Data Register not Empty (receivers) */
Kojto 96:487b796308b0 5285 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!< Data Register Empty (transmitters) */
Kojto 96:487b796308b0 5286 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!< Bus Error */
Kojto 96:487b796308b0 5287 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!< Arbitration Lost (master mode) */
Kojto 96:487b796308b0 5288 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!< Acknowledge Failure */
Kojto 96:487b796308b0 5289 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!< Overrun/Underrun */
Kojto 96:487b796308b0 5290 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!< PEC Error in reception */
Kojto 96:487b796308b0 5291 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!< Timeout or Tlow Error */
Kojto 96:487b796308b0 5292 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!< SMBus Alert */
Kojto 96:487b796308b0 5293
Kojto 96:487b796308b0 5294 /******************* Bit definition for I2C_SR2 register ********************/
Kojto 96:487b796308b0 5295 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!< Master/Slave */
Kojto 96:487b796308b0 5296 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!< Bus Busy */
Kojto 96:487b796308b0 5297 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!< Transmitter/Receiver */
Kojto 96:487b796308b0 5298 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!< General Call Address (Slave mode) */
Kojto 96:487b796308b0 5299 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!< SMBus Device Default Address (Slave mode) */
Kojto 96:487b796308b0 5300 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!< SMBus Host Header (Slave mode) */
Kojto 96:487b796308b0 5301 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!< Dual Flag (Slave mode) */
Kojto 96:487b796308b0 5302 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!< Packet Error Checking Register */
Kojto 96:487b796308b0 5303
Kojto 96:487b796308b0 5304 /******************* Bit definition for I2C_CCR register ********************/
Kojto 96:487b796308b0 5305 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
Kojto 96:487b796308b0 5306 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!< Fast Mode Duty Cycle */
Kojto 96:487b796308b0 5307 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!< I2C Master Mode Selection */
Kojto 96:487b796308b0 5308
Kojto 96:487b796308b0 5309 /****************** Bit definition for I2C_TRISE register *******************/
Kojto 96:487b796308b0 5310 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
Kojto 96:487b796308b0 5311
Kojto 96:487b796308b0 5312 /******************************************************************************/
Kojto 96:487b796308b0 5313 /* */
Kojto 96:487b796308b0 5314 /* Universal Synchronous Asynchronous Receiver Transmitter */
Kojto 96:487b796308b0 5315 /* */
Kojto 96:487b796308b0 5316 /******************************************************************************/
Kojto 96:487b796308b0 5317
Kojto 96:487b796308b0 5318 /******************* Bit definition for USART_SR register *******************/
Kojto 96:487b796308b0 5319 #define USART_SR_PE ((uint32_t)0x00000001) /*!< Parity Error */
Kojto 96:487b796308b0 5320 #define USART_SR_FE ((uint32_t)0x00000002) /*!< Framing Error */
Kojto 96:487b796308b0 5321 #define USART_SR_NE ((uint32_t)0x00000004) /*!< Noise Error Flag */
Kojto 96:487b796308b0 5322 #define USART_SR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
Kojto 96:487b796308b0 5323 #define USART_SR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
Kojto 96:487b796308b0 5324 #define USART_SR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
Kojto 96:487b796308b0 5325 #define USART_SR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
Kojto 96:487b796308b0 5326 #define USART_SR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
Kojto 96:487b796308b0 5327 #define USART_SR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
Kojto 96:487b796308b0 5328 #define USART_SR_CTS ((uint32_t)0x00000200) /*!< CTS Flag */
Kojto 96:487b796308b0 5329
Kojto 96:487b796308b0 5330 /******************* Bit definition for USART_DR register *******************/
Kojto 96:487b796308b0 5331 #define USART_DR_DR ((uint32_t)0x000001FF) /*!< Data value */
Kojto 96:487b796308b0 5332
Kojto 96:487b796308b0 5333 /****************** Bit definition for USART_BRR register *******************/
Kojto 96:487b796308b0 5334 #define USART_BRR_DIV_Fraction ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
Kojto 96:487b796308b0 5335 #define USART_BRR_DIV_Mantissa ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
Kojto 96:487b796308b0 5336
Kojto 96:487b796308b0 5337 /****************** Bit definition for USART_CR1 register *******************/
Kojto 96:487b796308b0 5338 #define USART_CR1_SBK ((uint32_t)0x00000001) /*!< Send Break */
Kojto 96:487b796308b0 5339 #define USART_CR1_RWU ((uint32_t)0x00000002) /*!< Receiver wakeup */
Kojto 96:487b796308b0 5340 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
Kojto 96:487b796308b0 5341 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
Kojto 96:487b796308b0 5342 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
Kojto 96:487b796308b0 5343 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
Kojto 96:487b796308b0 5344 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
Kojto 96:487b796308b0 5345 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< PE Interrupt Enable */
Kojto 96:487b796308b0 5346 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
Kojto 96:487b796308b0 5347 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
Kojto 96:487b796308b0 5348 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
Kojto 96:487b796308b0 5349 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Wakeup method */
Kojto 96:487b796308b0 5350 #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
Kojto 96:487b796308b0 5351 #define USART_CR1_UE ((uint32_t)0x00002000) /*!< USART Enable */
Kojto 96:487b796308b0 5352
Kojto 96:487b796308b0 5353 /****************** Bit definition for USART_CR2 register *******************/
Kojto 96:487b796308b0 5354 #define USART_CR2_ADD ((uint32_t)0x0000000F) /*!< Address of the USART node */
Kojto 96:487b796308b0 5355 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
Kojto 96:487b796308b0 5356 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
Kojto 96:487b796308b0 5357 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
Kojto 96:487b796308b0 5358 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
Kojto 96:487b796308b0 5359 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
Kojto 96:487b796308b0 5360 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
Kojto 96:487b796308b0 5361
Kojto 96:487b796308b0 5362 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
Kojto 96:487b796308b0 5363 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 96:487b796308b0 5364 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 96:487b796308b0 5365
Kojto 96:487b796308b0 5366 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
Kojto 96:487b796308b0 5367
Kojto 96:487b796308b0 5368 /****************** Bit definition for USART_CR3 register *******************/
Kojto 96:487b796308b0 5369 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
Kojto 96:487b796308b0 5370 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
Kojto 96:487b796308b0 5371 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
Kojto 96:487b796308b0 5372 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
Kojto 96:487b796308b0 5373 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< Smartcard NACK enable */
Kojto 96:487b796308b0 5374 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< Smartcard mode enable */
Kojto 96:487b796308b0 5375 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
Kojto 96:487b796308b0 5376 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
Kojto 96:487b796308b0 5377 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
Kojto 96:487b796308b0 5378 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
Kojto 96:487b796308b0 5379 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
Kojto 96:487b796308b0 5380
Kojto 96:487b796308b0 5381 /****************** Bit definition for USART_GTPR register ******************/
Kojto 96:487b796308b0 5382 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
Kojto 96:487b796308b0 5383 #define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 5384 #define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 5385 #define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 5386 #define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 96:487b796308b0 5387 #define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
Kojto 96:487b796308b0 5388 #define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
Kojto 96:487b796308b0 5389 #define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
Kojto 96:487b796308b0 5390 #define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
Kojto 96:487b796308b0 5391
Kojto 96:487b796308b0 5392 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< Guard time value */
Kojto 96:487b796308b0 5393
Kojto 96:487b796308b0 5394 /******************************************************************************/
Kojto 96:487b796308b0 5395 /* */
Kojto 96:487b796308b0 5396 /* Debug MCU */
Kojto 96:487b796308b0 5397 /* */
Kojto 96:487b796308b0 5398 /******************************************************************************/
Kojto 96:487b796308b0 5399
Kojto 96:487b796308b0 5400 /**************** Bit definition for DBGMCU_IDCODE register *****************/
Kojto 96:487b796308b0 5401 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
Kojto 96:487b796308b0 5402
Kojto 96:487b796308b0 5403 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
Kojto 96:487b796308b0 5404 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 96:487b796308b0 5405 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 96:487b796308b0 5406 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 96:487b796308b0 5407 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 96:487b796308b0 5408 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Kojto 96:487b796308b0 5409 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
Kojto 96:487b796308b0 5410 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
Kojto 96:487b796308b0 5411 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
Kojto 96:487b796308b0 5412 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
Kojto 96:487b796308b0 5413 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
Kojto 96:487b796308b0 5414 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
Kojto 96:487b796308b0 5415 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
Kojto 96:487b796308b0 5416 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
Kojto 96:487b796308b0 5417 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
Kojto 96:487b796308b0 5418 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
Kojto 96:487b796308b0 5419 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
Kojto 96:487b796308b0 5420
Kojto 96:487b796308b0 5421 /****************** Bit definition for DBGMCU_CR register *******************/
Kojto 96:487b796308b0 5422 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
Kojto 96:487b796308b0 5423 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
Kojto 96:487b796308b0 5424 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
Kojto 96:487b796308b0 5425 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
Kojto 96:487b796308b0 5426
Kojto 96:487b796308b0 5427 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
Kojto 96:487b796308b0 5428 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Kojto 96:487b796308b0 5429 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Kojto 96:487b796308b0 5430
Kojto 96:487b796308b0 5431 #define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */
Kojto 96:487b796308b0 5432 #define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */
Kojto 96:487b796308b0 5433 #define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */
Kojto 96:487b796308b0 5434 #define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */
Kojto 96:487b796308b0 5435 #define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */
Kojto 96:487b796308b0 5436 #define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */
Kojto 96:487b796308b0 5437 #define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */
Kojto 96:487b796308b0 5438 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */
Kojto 96:487b796308b0 5439 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */
Kojto 96:487b796308b0 5440
Kojto 96:487b796308b0 5441 /******************************************************************************/
Kojto 96:487b796308b0 5442 /* */
Kojto 96:487b796308b0 5443 /* FLASH and Option Bytes Registers */
Kojto 96:487b796308b0 5444 /* */
Kojto 96:487b796308b0 5445 /******************************************************************************/
Kojto 96:487b796308b0 5446 /******************* Bit definition for FLASH_ACR register ******************/
Kojto 96:487b796308b0 5447 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */
Kojto 96:487b796308b0 5448 #define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 96:487b796308b0 5449 #define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 96:487b796308b0 5450 #define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 96:487b796308b0 5451
Kojto 96:487b796308b0 5452 #define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
Kojto 96:487b796308b0 5453 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
Kojto 96:487b796308b0 5454 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
Kojto 96:487b796308b0 5455
Kojto 96:487b796308b0 5456 /****************** Bit definition for FLASH_KEYR register ******************/
Kojto 96:487b796308b0 5457 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
Kojto 96:487b796308b0 5458
Kojto 96:487b796308b0 5459 #define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
Kojto 96:487b796308b0 5460 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
Kojto 96:487b796308b0 5461 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
Kojto 96:487b796308b0 5462
Kojto 96:487b796308b0 5463 /***************** Bit definition for FLASH_OPTKEYR register ****************/
Kojto 96:487b796308b0 5464 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
Kojto 96:487b796308b0 5465
Kojto 96:487b796308b0 5466 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
Kojto 96:487b796308b0 5467 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
Kojto 96:487b796308b0 5468
Kojto 96:487b796308b0 5469 /****************** Bit definition for FLASH_SR register ********************/
Kojto 96:487b796308b0 5470 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
Kojto 96:487b796308b0 5471 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
Kojto 96:487b796308b0 5472 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
Kojto 96:487b796308b0 5473 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
Kojto 96:487b796308b0 5474
Kojto 96:487b796308b0 5475 /******************* Bit definition for FLASH_CR register *******************/
Kojto 96:487b796308b0 5476 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
Kojto 96:487b796308b0 5477 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
Kojto 96:487b796308b0 5478 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
Kojto 96:487b796308b0 5479 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
Kojto 96:487b796308b0 5480 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
Kojto 96:487b796308b0 5481 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
Kojto 96:487b796308b0 5482 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
Kojto 96:487b796308b0 5483 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
Kojto 96:487b796308b0 5484 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
Kojto 96:487b796308b0 5485 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
Kojto 96:487b796308b0 5486
Kojto 96:487b796308b0 5487 /******************* Bit definition for FLASH_AR register *******************/
Kojto 96:487b796308b0 5488 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
Kojto 96:487b796308b0 5489
Kojto 96:487b796308b0 5490 /****************** Bit definition for FLASH_OBR register *******************/
Kojto 96:487b796308b0 5491 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
Kojto 96:487b796308b0 5492 #define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /*!< Read protection */
Kojto 96:487b796308b0 5493
Kojto 96:487b796308b0 5494 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000004) /*!< IWDG SW */
Kojto 96:487b796308b0 5495 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000008) /*!< nRST_STOP */
Kojto 96:487b796308b0 5496 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000010) /*!< nRST_STDBY */
Kojto 96:487b796308b0 5497 #define FLASH_OBR_USER ((uint32_t)0x0000001C) /*!< User Option Bytes */
Kojto 96:487b796308b0 5498
Kojto 96:487b796308b0 5499 /****************** Bit definition for FLASH_WRPR register ******************/
Kojto 96:487b796308b0 5500 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
Kojto 96:487b796308b0 5501
Kojto 96:487b796308b0 5502 /*----------------------------------------------------------------------------*/
Kojto 96:487b796308b0 5503
Kojto 96:487b796308b0 5504 /****************** Bit definition for FLASH_RDP register *******************/
Kojto 96:487b796308b0 5505 #define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
Kojto 96:487b796308b0 5506 #define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
Kojto 96:487b796308b0 5507
Kojto 96:487b796308b0 5508 /****************** Bit definition for FLASH_USER register ******************/
Kojto 96:487b796308b0 5509 #define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
Kojto 96:487b796308b0 5510 #define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
Kojto 96:487b796308b0 5511
Kojto 96:487b796308b0 5512 /****************** Bit definition for FLASH_Data0 register *****************/
Kojto 96:487b796308b0 5513 #define FLASH_DATA0_DATA0 ((uint32_t)0x000000FF) /*!< User data storage option byte */
Kojto 96:487b796308b0 5514 #define FLASH_DATA0_nDATA0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */
Kojto 96:487b796308b0 5515
Kojto 96:487b796308b0 5516 /****************** Bit definition for FLASH_Data1 register *****************/
Kojto 96:487b796308b0 5517 #define FLASH_DATA1_DATA1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */
Kojto 96:487b796308b0 5518 #define FLASH_DATA1_nDATA1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */
Kojto 96:487b796308b0 5519
Kojto 96:487b796308b0 5520 /****************** Bit definition for FLASH_WRP0 register ******************/
Kojto 96:487b796308b0 5521 #define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
Kojto 96:487b796308b0 5522 #define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
Kojto 96:487b796308b0 5523
Kojto 96:487b796308b0 5524 /****************** Bit definition for FLASH_WRP1 register ******************/
Kojto 96:487b796308b0 5525 #define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
Kojto 96:487b796308b0 5526 #define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
Kojto 96:487b796308b0 5527
Kojto 96:487b796308b0 5528 /****************** Bit definition for FLASH_WRP2 register ******************/
Kojto 96:487b796308b0 5529 #define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
Kojto 96:487b796308b0 5530 #define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
Kojto 96:487b796308b0 5531
Kojto 96:487b796308b0 5532 /****************** Bit definition for FLASH_WRP3 register ******************/
Kojto 96:487b796308b0 5533 #define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
Kojto 96:487b796308b0 5534 #define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
Kojto 96:487b796308b0 5535
Kojto 96:487b796308b0 5536
Kojto 96:487b796308b0 5537
Kojto 96:487b796308b0 5538 /**
Kojto 96:487b796308b0 5539 * @}
Kojto 96:487b796308b0 5540 */
Kojto 96:487b796308b0 5541
Kojto 96:487b796308b0 5542 /**
Kojto 96:487b796308b0 5543 * @}
Kojto 96:487b796308b0 5544 */
Kojto 96:487b796308b0 5545
Kojto 96:487b796308b0 5546 /** @addtogroup Exported_macro
Kojto 96:487b796308b0 5547 * @{
Kojto 96:487b796308b0 5548 */
Kojto 96:487b796308b0 5549
Kojto 96:487b796308b0 5550 /****************************** ADC Instances *********************************/
Kojto 96:487b796308b0 5551 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
Kojto 96:487b796308b0 5552 ((INSTANCE) == ADC2))
Kojto 96:487b796308b0 5553
Kojto 96:487b796308b0 5554 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto 96:487b796308b0 5555
Kojto 96:487b796308b0 5556 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto 96:487b796308b0 5557
Kojto 96:487b796308b0 5558
Kojto 96:487b796308b0 5559 /****************************** CAN Instances *********************************/
Kojto 96:487b796308b0 5560 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
Kojto 96:487b796308b0 5561
Kojto 96:487b796308b0 5562 /****************************** CRC Instances *********************************/
Kojto 96:487b796308b0 5563 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 96:487b796308b0 5564
Kojto 96:487b796308b0 5565 /****************************** DAC Instances *********************************/
Kojto 96:487b796308b0 5566
Kojto 96:487b796308b0 5567 /****************************** DMA Instances *********************************/
Kojto 96:487b796308b0 5568 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Kojto 96:487b796308b0 5569 ((INSTANCE) == DMA1_Channel2) || \
Kojto 96:487b796308b0 5570 ((INSTANCE) == DMA1_Channel3) || \
Kojto 96:487b796308b0 5571 ((INSTANCE) == DMA1_Channel4) || \
Kojto 96:487b796308b0 5572 ((INSTANCE) == DMA1_Channel5) || \
Kojto 96:487b796308b0 5573 ((INSTANCE) == DMA1_Channel6) || \
Kojto 96:487b796308b0 5574 ((INSTANCE) == DMA1_Channel7))
Kojto 96:487b796308b0 5575
Kojto 96:487b796308b0 5576 /******************************* GPIO Instances *******************************/
Kojto 96:487b796308b0 5577 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 96:487b796308b0 5578 ((INSTANCE) == GPIOB) || \
Kojto 96:487b796308b0 5579 ((INSTANCE) == GPIOC) || \
Kojto 96:487b796308b0 5580 ((INSTANCE) == GPIOD) || \
Kojto 96:487b796308b0 5581 ((INSTANCE) == GPIOE))
Kojto 96:487b796308b0 5582
Kojto 96:487b796308b0 5583 /**************************** GPIO Alternate Function Instances ***************/
Kojto 96:487b796308b0 5584 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
Kojto 96:487b796308b0 5585
Kojto 96:487b796308b0 5586 /**************************** GPIO Lock Instances *****************************/
Kojto 96:487b796308b0 5587 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
Kojto 96:487b796308b0 5588
Kojto 96:487b796308b0 5589 /******************************** I2C Instances *******************************/
Kojto 96:487b796308b0 5590 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 96:487b796308b0 5591 ((INSTANCE) == I2C2))
Kojto 96:487b796308b0 5592
Kojto 96:487b796308b0 5593 /****************************** IWDG Instances ********************************/
Kojto 96:487b796308b0 5594 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 96:487b796308b0 5595
Kojto 96:487b796308b0 5596 /******************************** SPI Instances *******************************/
Kojto 96:487b796308b0 5597 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 96:487b796308b0 5598 ((INSTANCE) == SPI2))
Kojto 96:487b796308b0 5599
Kojto 96:487b796308b0 5600 /****************************** START TIM Instances ***************************/
Kojto 96:487b796308b0 5601 /****************************** TIM Instances *********************************/
Kojto 96:487b796308b0 5602 #define IS_TIM_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5603 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5604 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5605 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5606 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5607
Kojto 96:487b796308b0 5608 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5609 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5610 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5611 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5612 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5613
Kojto 96:487b796308b0 5614 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5615 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5616 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5617 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5618 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5619
Kojto 96:487b796308b0 5620 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5621 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5622 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5623 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5624 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5625
Kojto 96:487b796308b0 5626 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5627 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5628 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5629 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5630 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5631
Kojto 96:487b796308b0 5632 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5633 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5634 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5635 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5636 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5637
Kojto 96:487b796308b0 5638 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5639 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5640 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5641 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5642 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5643
Kojto 96:487b796308b0 5644 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5645 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5646 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5647 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5648 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5649
Kojto 96:487b796308b0 5650 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5651 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5652 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5653 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5654 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5655
Kojto 96:487b796308b0 5656 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5657 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5658 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5659 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5660 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5661
Kojto 96:487b796308b0 5662 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5663 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5664 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5665 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5666 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5667
Kojto 96:487b796308b0 5668 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5669 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5670 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5671 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5672 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5673
Kojto 96:487b796308b0 5674 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5675 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5676 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5677 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5678 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5679
Kojto 96:487b796308b0 5680 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5681 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5682 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5683 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5684 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5685
Kojto 96:487b796308b0 5686 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5687 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5688 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5689 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5690 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5691
Kojto 96:487b796308b0 5692 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5693 ((INSTANCE) == TIM1)
Kojto 96:487b796308b0 5694
Kojto 96:487b796308b0 5695 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 96:487b796308b0 5696 ((((INSTANCE) == TIM1) && \
Kojto 96:487b796308b0 5697 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 96:487b796308b0 5698 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 96:487b796308b0 5699 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 96:487b796308b0 5700 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 96:487b796308b0 5701 || \
Kojto 96:487b796308b0 5702 (((INSTANCE) == TIM2) && \
Kojto 96:487b796308b0 5703 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 96:487b796308b0 5704 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 96:487b796308b0 5705 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 96:487b796308b0 5706 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 96:487b796308b0 5707 || \
Kojto 96:487b796308b0 5708 (((INSTANCE) == TIM3) && \
Kojto 96:487b796308b0 5709 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 96:487b796308b0 5710 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 96:487b796308b0 5711 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 96:487b796308b0 5712 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 96:487b796308b0 5713 || \
Kojto 96:487b796308b0 5714 (((INSTANCE) == TIM4) && \
Kojto 96:487b796308b0 5715 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 96:487b796308b0 5716 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 96:487b796308b0 5717 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 96:487b796308b0 5718 ((CHANNEL) == TIM_CHANNEL_4))))
Kojto 96:487b796308b0 5719
Kojto 96:487b796308b0 5720 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 96:487b796308b0 5721 (((INSTANCE) == TIM1) && \
Kojto 96:487b796308b0 5722 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 96:487b796308b0 5723 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 96:487b796308b0 5724 ((CHANNEL) == TIM_CHANNEL_3)))
Kojto 96:487b796308b0 5725
Kojto 96:487b796308b0 5726 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5727 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5728 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5729 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5730 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5731
Kojto 96:487b796308b0 5732 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5733 ((INSTANCE) == TIM1)
Kojto 96:487b796308b0 5734
Kojto 96:487b796308b0 5735 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5736 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5737 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5738 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5739 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5740
Kojto 96:487b796308b0 5741 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5742 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5743 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5744 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5745 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5746
Kojto 96:487b796308b0 5747 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5748 (((INSTANCE) == TIM1) || \
Kojto 96:487b796308b0 5749 ((INSTANCE) == TIM2) || \
Kojto 96:487b796308b0 5750 ((INSTANCE) == TIM3) || \
Kojto 96:487b796308b0 5751 ((INSTANCE) == TIM4))
Kojto 96:487b796308b0 5752
Kojto 96:487b796308b0 5753 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
Kojto 96:487b796308b0 5754 ((INSTANCE) == TIM1)
Kojto 96:487b796308b0 5755
Kojto 96:487b796308b0 5756 /****************************** END TIM Instances *****************************/
Kojto 96:487b796308b0 5757
Kojto 96:487b796308b0 5758
Kojto 96:487b796308b0 5759 /******************** USART Instances : Synchronous mode **********************/
Kojto 96:487b796308b0 5760 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 96:487b796308b0 5761 ((INSTANCE) == USART2) || \
Kojto 96:487b796308b0 5762 ((INSTANCE) == USART3))
Kojto 96:487b796308b0 5763
Kojto 96:487b796308b0 5764 /******************** UART Instances : Asynchronous mode **********************/
Kojto 96:487b796308b0 5765 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 96:487b796308b0 5766 ((INSTANCE) == USART2) || \
Kojto 96:487b796308b0 5767 ((INSTANCE) == USART3))
Kojto 96:487b796308b0 5768
Kojto 96:487b796308b0 5769 /******************** UART Instances : Half-Duplex mode **********************/
Kojto 96:487b796308b0 5770 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 96:487b796308b0 5771 ((INSTANCE) == USART2) || \
Kojto 96:487b796308b0 5772 ((INSTANCE) == USART3))
Kojto 96:487b796308b0 5773
Kojto 96:487b796308b0 5774 /******************** UART Instances : LIN mode **********************/
Kojto 96:487b796308b0 5775 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 96:487b796308b0 5776 ((INSTANCE) == USART2) || \
Kojto 96:487b796308b0 5777 ((INSTANCE) == USART3))
Kojto 96:487b796308b0 5778
Kojto 96:487b796308b0 5779 /****************** UART Instances : Hardware Flow control ********************/
Kojto 96:487b796308b0 5780 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 96:487b796308b0 5781 ((INSTANCE) == USART2) || \
Kojto 96:487b796308b0 5782 ((INSTANCE) == USART3))
Kojto 96:487b796308b0 5783
Kojto 96:487b796308b0 5784 /********************* UART Instances : Smard card mode ***********************/
Kojto 96:487b796308b0 5785 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 96:487b796308b0 5786 ((INSTANCE) == USART2) || \
Kojto 96:487b796308b0 5787 ((INSTANCE) == USART3))
Kojto 96:487b796308b0 5788
Kojto 96:487b796308b0 5789 /*********************** UART Instances : IRDA mode ***************************/
Kojto 96:487b796308b0 5790 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 96:487b796308b0 5791 ((INSTANCE) == USART2) || \
Kojto 96:487b796308b0 5792 ((INSTANCE) == USART3))
Kojto 96:487b796308b0 5793
Kojto 96:487b796308b0 5794 /***************** UART Instances : Multi-Processor mode **********************/
Kojto 96:487b796308b0 5795 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 96:487b796308b0 5796 ((INSTANCE) == USART2) || \
Kojto 96:487b796308b0 5797 ((INSTANCE) == USART3))
Kojto 96:487b796308b0 5798
Kojto 96:487b796308b0 5799 /***************** UART Instances : DMA mode available **********************/
Kojto 96:487b796308b0 5800 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 96:487b796308b0 5801 ((INSTANCE) == USART2) || \
Kojto 96:487b796308b0 5802 ((INSTANCE) == USART3))
Kojto 96:487b796308b0 5803
Kojto 96:487b796308b0 5804 /****************************** RTC Instances *********************************/
Kojto 96:487b796308b0 5805 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 96:487b796308b0 5806
Kojto 96:487b796308b0 5807 /**************************** WWDG Instances *****************************/
Kojto 96:487b796308b0 5808 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 96:487b796308b0 5809
Kojto 96:487b796308b0 5810 /****************************** USB Instances ********************************/
Kojto 96:487b796308b0 5811 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
Kojto 96:487b796308b0 5812
Kojto 96:487b796308b0 5813
Kojto 96:487b796308b0 5814
Kojto 96:487b796308b0 5815
Kojto 96:487b796308b0 5816 /**
Kojto 96:487b796308b0 5817 * @}
Kojto 96:487b796308b0 5818 */
Kojto 96:487b796308b0 5819 /******************************************************************************/
Kojto 96:487b796308b0 5820 /* For a painless codes migration between the STM32F1xx device product */
Kojto 96:487b796308b0 5821 /* lines, the aliases defined below are put in place to overcome the */
Kojto 96:487b796308b0 5822 /* differences in the interrupt handlers and IRQn definitions. */
Kojto 96:487b796308b0 5823 /* No need to update developed interrupt code when moving across */
Kojto 96:487b796308b0 5824 /* product lines within the same STM32F1 Family */
Kojto 96:487b796308b0 5825 /******************************************************************************/
Kojto 96:487b796308b0 5826
Kojto 96:487b796308b0 5827 /* Aliases for __IRQn */
Kojto 96:487b796308b0 5828 #define ADC1_IRQn ADC1_2_IRQn
Kojto 96:487b796308b0 5829
Kojto 96:487b796308b0 5830
Kojto 96:487b796308b0 5831
Kojto 96:487b796308b0 5832 #define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
Kojto 96:487b796308b0 5833 #define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
Kojto 96:487b796308b0 5834
Kojto 96:487b796308b0 5835 #define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
Kojto 96:487b796308b0 5836 #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
Kojto 96:487b796308b0 5837
Kojto 96:487b796308b0 5838
Kojto 96:487b796308b0 5839
Kojto 96:487b796308b0 5840 #define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
Kojto 96:487b796308b0 5841 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
Kojto 96:487b796308b0 5842 #define TIM9_IRQn TIM1_BRK_IRQn
Kojto 96:487b796308b0 5843
Kojto 96:487b796308b0 5844 #define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
Kojto 96:487b796308b0 5845 #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
Kojto 96:487b796308b0 5846 #define TIM10_IRQn TIM1_UP_IRQn
Kojto 96:487b796308b0 5847
Kojto 96:487b796308b0 5848 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
Kojto 96:487b796308b0 5849 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
Kojto 96:487b796308b0 5850 #define TIM11_IRQn TIM1_TRG_COM_IRQn
Kojto 96:487b796308b0 5851
Kojto 96:487b796308b0 5852 #define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
Kojto 96:487b796308b0 5853 #define CEC_IRQn USBWakeUp_IRQn
Kojto 96:487b796308b0 5854
Kojto 96:487b796308b0 5855
Kojto 96:487b796308b0 5856
Kojto 96:487b796308b0 5857
Kojto 96:487b796308b0 5858 /* Aliases for __IRQHandler */
Kojto 96:487b796308b0 5859 #define ADC1_IRQHandler ADC1_2_IRQHandler
Kojto 96:487b796308b0 5860
Kojto 96:487b796308b0 5861
Kojto 96:487b796308b0 5862
Kojto 96:487b796308b0 5863 #define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
Kojto 96:487b796308b0 5864 #define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
Kojto 96:487b796308b0 5865
Kojto 96:487b796308b0 5866 #define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
Kojto 96:487b796308b0 5867 #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
Kojto 96:487b796308b0 5868
Kojto 96:487b796308b0 5869
Kojto 96:487b796308b0 5870
Kojto 96:487b796308b0 5871 #define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
Kojto 96:487b796308b0 5872 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
Kojto 96:487b796308b0 5873 #define TIM9_IRQHandler TIM1_BRK_IRQHandler
Kojto 96:487b796308b0 5874
Kojto 96:487b796308b0 5875 #define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
Kojto 96:487b796308b0 5876 #define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
Kojto 96:487b796308b0 5877 #define TIM10_IRQHandler TIM1_UP_IRQHandler
Kojto 96:487b796308b0 5878
Kojto 96:487b796308b0 5879 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
Kojto 96:487b796308b0 5880 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
Kojto 96:487b796308b0 5881 #define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
Kojto 96:487b796308b0 5882
Kojto 96:487b796308b0 5883 #define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
Kojto 96:487b796308b0 5884 #define CEC_IRQHandler USBWakeUp_IRQHandler
Kojto 96:487b796308b0 5885
Kojto 96:487b796308b0 5886
Kojto 96:487b796308b0 5887
Kojto 96:487b796308b0 5888
Kojto 96:487b796308b0 5889 /**
Kojto 96:487b796308b0 5890 * @}
Kojto 96:487b796308b0 5891 */
Kojto 96:487b796308b0 5892
Kojto 96:487b796308b0 5893 /**
Kojto 96:487b796308b0 5894 * @}
Kojto 96:487b796308b0 5895 */
Kojto 96:487b796308b0 5896
Kojto 96:487b796308b0 5897
Kojto 96:487b796308b0 5898 #ifdef __cplusplus
Kojto 96:487b796308b0 5899 }
Kojto 96:487b796308b0 5900 #endif /* __cplusplus */
Kojto 96:487b796308b0 5901
Kojto 96:487b796308b0 5902 #endif /* __STM32F103xB_H */
Kojto 96:487b796308b0 5903
Kojto 96:487b796308b0 5904
Kojto 96:487b796308b0 5905
Kojto 96:487b796308b0 5906 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/