mbed-F401 - mbed library with additional peripherals for ST F…

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Peter Drescher / mbed-F401

mbed library with additional peripherals for ST F401 board

Fork of mbed-src by mbed official

This mbed LIB has additional peripherals for ST F401 board

UART2 : PA_3 rx, PA_2 tx
UART3 : PC_7 rx, PC_6 tx
I2C2 : PB_3 SDA, PB_10 SCL
I2C3 : PB_4 SDA, PA_8 SCL

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.c@106:ced8cbb51063, 2014-02-26 (annotated)

Committer:: mbed_official
Date:: Wed Feb 26 09:45:12 2014 +0000
Revision:: 106:ced8cbb51063
Parent:: 87:085cde657901

Synchronized with git revision 4222735eff5868389433f0e9271976b39c8115cd



Full URL: https://github.com/mbedmicro/mbed/commit/4222735eff5868389433f0e9271976b39c8115cd/



[NUCLEO_xxx] Update STM32CubeF4 driver V1.0.0 + update license

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	87:085cde657901	1	/**
mbed_official	87:085cde657901	2	******************************************************************************
mbed_official	87:085cde657901	3	* @file stm32f4xx_hal_rcc.c
mbed_official	87:085cde657901	4	* @author MCD Application Team
mbed_official	106:ced8cbb51063	5	* @version V1.0.0
mbed_official	106:ced8cbb51063	6	* @date 18-February-2014
mbed_official	87:085cde657901	7	* @brief RCC HAL module driver.
mbed_official	87:085cde657901	8	* This file provides firmware functions to manage the following
mbed_official	87:085cde657901	9	* functionalities of the Reset and Clock Control (RCC) peripheral:
mbed_official	87:085cde657901	10	* + Initialization and de-initialization functions
mbed_official	87:085cde657901	11	* + Peripheral Control functions
mbed_official	87:085cde657901	12	*
mbed_official	87:085cde657901	13	@verbatim
mbed_official	87:085cde657901	14	==============================================================================
mbed_official	87:085cde657901	15	##### RCC specific features #####
mbed_official	87:085cde657901	16	==============================================================================
mbed_official	87:085cde657901	17	[..]
mbed_official	87:085cde657901	18	After reset the device is running from Internal High Speed oscillator
mbed_official	87:085cde657901	19	(HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
mbed_official	87:085cde657901	20	and I-Cache are disabled, and all peripherals are off except internal
mbed_official	87:085cde657901	21	SRAM, Flash and JTAG.
mbed_official	87:085cde657901	22	(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
mbed_official	87:085cde657901	23	all peripherals mapped on these busses are running at HSI speed.
mbed_official	87:085cde657901	24	(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
mbed_official	87:085cde657901	25	(+) All GPIOs are in input floating state, except the JTAG pins which
mbed_official	87:085cde657901	26	are assigned to be used for debug purpose.
mbed_official	87:085cde657901	27
mbed_official	87:085cde657901	28	[..]
mbed_official	87:085cde657901	29	Once the device started from reset, the user application has to:
mbed_official	87:085cde657901	30	(+) Configure the clock source to be used to drive the System clock
mbed_official	87:085cde657901	31	(if the application needs higher frequency/performance)
mbed_official	87:085cde657901	32	(+) Configure the System clock frequency and Flash settings
mbed_official	87:085cde657901	33	(+) Configure the AHB and APB busses prescalers
mbed_official	87:085cde657901	34	(+) Enable the clock for the peripheral(s) to be used
mbed_official	87:085cde657901	35	(+) Configure the clock source(s) for peripherals which clocks are not
mbed_official	87:085cde657901	36	derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
mbed_official	87:085cde657901	37
mbed_official	87:085cde657901	38	@endverbatim
mbed_official	87:085cde657901	39	******************************************************************************
mbed_official	87:085cde657901	40	* @attention
mbed_official	87:085cde657901	41	*
mbed_official	87:085cde657901	42	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	87:085cde657901	43	*
mbed_official	87:085cde657901	44	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	87:085cde657901	45	* are permitted provided that the following conditions are met:
mbed_official	87:085cde657901	46	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	87:085cde657901	47	* this list of conditions and the following disclaimer.
mbed_official	87:085cde657901	48	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	87:085cde657901	49	* this list of conditions and the following disclaimer in the documentation
mbed_official	87:085cde657901	50	* and/or other materials provided with the distribution.
mbed_official	87:085cde657901	51	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	87:085cde657901	52	* may be used to endorse or promote products derived from this software
mbed_official	87:085cde657901	53	* without specific prior written permission.
mbed_official	87:085cde657901	54	*
mbed_official	87:085cde657901	55	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	87:085cde657901	56	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	87:085cde657901	57	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	87:085cde657901	58	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	87:085cde657901	59	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	87:085cde657901	60	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	87:085cde657901	61	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	87:085cde657901	62	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	87:085cde657901	63	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	87:085cde657901	64	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	87:085cde657901	65	*
mbed_official	87:085cde657901	66	******************************************************************************
mbed_official	87:085cde657901	67	*/
mbed_official	87:085cde657901	68
mbed_official	87:085cde657901	69	/* Includes ------------------------------------------------------------------*/
mbed_official	87:085cde657901	70	#include "stm32f4xx_hal.h"
mbed_official	87:085cde657901	71
mbed_official	87:085cde657901	72	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	87:085cde657901	73	* @{
mbed_official	87:085cde657901	74	*/
mbed_official	87:085cde657901	75
mbed_official	87:085cde657901	76	/** @defgroup RCC
mbed_official	87:085cde657901	77	* @brief RCC HAL module driver
mbed_official	87:085cde657901	78	* @{
mbed_official	87:085cde657901	79	*/
mbed_official	87:085cde657901	80
mbed_official	87:085cde657901	81	#ifdef HAL_RCC_MODULE_ENABLED
mbed_official	87:085cde657901	82
mbed_official	87:085cde657901	83	/* Private typedef -----------------------------------------------------------*/
mbed_official	87:085cde657901	84	/* Private define ------------------------------------------------------------*/
mbed_official	87:085cde657901	85	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
mbed_official	87:085cde657901	86	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	87:085cde657901	87	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	87:085cde657901	88	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	87:085cde657901	89	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
mbed_official	87:085cde657901	90
mbed_official	87:085cde657901	91	/* Private macro -------------------------------------------------------------*/
mbed_official	87:085cde657901	92	#define __MCO1_CLK_ENABLE() __GPIOA_CLK_ENABLE()
mbed_official	87:085cde657901	93	#define MCO1_GPIO_PORT GPIOA
mbed_official	87:085cde657901	94	#define MCO1_PIN GPIO_PIN_8
mbed_official	87:085cde657901	95
mbed_official	87:085cde657901	96	#define __MCO2_CLK_ENABLE() __GPIOC_CLK_ENABLE()
mbed_official	87:085cde657901	97	#define MCO2_GPIO_PORT GPIOC
mbed_official	87:085cde657901	98	#define MCO2_PIN GPIO_PIN_9
mbed_official	87:085cde657901	99
mbed_official	87:085cde657901	100	/* Private variables ---------------------------------------------------------*/
mbed_official	87:085cde657901	101	const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official	87:085cde657901	102
mbed_official	87:085cde657901	103	/* Private function prototypes -----------------------------------------------*/
mbed_official	87:085cde657901	104	/* Private functions ---------------------------------------------------------*/
mbed_official	87:085cde657901	105
mbed_official	87:085cde657901	106	/** @defgroup RCC_Private_Functions
mbed_official	87:085cde657901	107	* @{
mbed_official	87:085cde657901	108	*/
mbed_official	87:085cde657901	109
mbed_official	87:085cde657901	110	/** @defgroup RCC_Group1 Initialization and de-initialization functions
mbed_official	87:085cde657901	111	* @brief Initialization and Configuration functions
mbed_official	87:085cde657901	112	*
mbed_official	87:085cde657901	113	@verbatim
mbed_official	87:085cde657901	114	===============================================================================
mbed_official	87:085cde657901	115	##### Initialization and de-initialization functions #####
mbed_official	87:085cde657901	116	===============================================================================
mbed_official	87:085cde657901	117	[..]
mbed_official	87:085cde657901	118	This section provide functions allowing to configure the internal/external oscillators
mbed_official	87:085cde657901	119	(HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
mbed_official	87:085cde657901	120	and APB2).
mbed_official	87:085cde657901	121
mbed_official	87:085cde657901	122	[..] Internal/external clock and PLL configuration
mbed_official	87:085cde657901	123	(#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
mbed_official	87:085cde657901	124	the PLL as System clock source.
mbed_official	87:085cde657901	125
mbed_official	87:085cde657901	126	(#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
mbed_official	87:085cde657901	127	clock source.
mbed_official	87:085cde657901	128
mbed_official	87:085cde657901	129	(#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
mbed_official	87:085cde657901	130	through the PLL as System clock source. Can be used also as RTC clock source.
mbed_official	87:085cde657901	131
mbed_official	87:085cde657901	132	(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
mbed_official	87:085cde657901	133
mbed_official	87:085cde657901	134	(#) PLL (clocked by HSI or HSE), featuring two different output clocks:
mbed_official	87:085cde657901	135	(++) The first output is used to generate the high speed system clock (up to 168 MHz)
mbed_official	87:085cde657901	136	(++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
mbed_official	87:085cde657901	137	the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
mbed_official	87:085cde657901	138
mbed_official	87:085cde657901	139	(#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
mbed_official	87:085cde657901	140	and if a HSE clock failure occurs(HSE used directly or through PLL as System
mbed_official	87:085cde657901	141	clock source), the System clockis automatically switched to HSI and an interrupt
mbed_official	87:085cde657901	142	is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
mbed_official	87:085cde657901	143	(Non-Maskable Interrupt) exception vector.
mbed_official	87:085cde657901	144
mbed_official	87:085cde657901	145	(#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
mbed_official	87:085cde657901	146	clock (through a configurable prescaler) on PA8 pin.
mbed_official	87:085cde657901	147
mbed_official	87:085cde657901	148	(#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
mbed_official	87:085cde657901	149	clock (through a configurable prescaler) on PC9 pin.
mbed_official	87:085cde657901	150
mbed_official	87:085cde657901	151	[..] System, AHB and APB busses clocks configuration
mbed_official	87:085cde657901	152	(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
mbed_official	87:085cde657901	153	HSE and PLL.
mbed_official	87:085cde657901	154	The AHB clock (HCLK) is derived from System clock through configurable
mbed_official	87:085cde657901	155	prescaler and used to clock the CPU, memory and peripherals mapped
mbed_official	87:085cde657901	156	on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
mbed_official	87:085cde657901	157	from AHB clock through configurable prescalers and used to clock
mbed_official	87:085cde657901	158	the peripherals mapped on these busses. You can use
mbed_official	87:085cde657901	159	"HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
mbed_official	87:085cde657901	160
mbed_official	87:085cde657901	161	-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
mbed_official	87:085cde657901	162	(+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
mbed_official	87:085cde657901	163	from an external clock mapped on the I2S_CKIN pin.
mbed_official	87:085cde657901	164	You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
mbed_official	87:085cde657901	165	(+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
mbed_official	87:085cde657901	166	from an external clock mapped on the I2S_CKIN pin.
mbed_official	87:085cde657901	167	You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
mbed_official	87:085cde657901	168	(+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
mbed_official	87:085cde657901	169	divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
mbed_official	87:085cde657901	170	macros to configure this clock.
mbed_official	87:085cde657901	171	(+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
mbed_official	87:085cde657901	172	to work correctly, while the SDIO require a frequency equal or lower than
mbed_official	87:085cde657901	173	to 48. This clock is derived of the main PLL through PLLQ divider.
mbed_official	87:085cde657901	174	(+@) IWDG clock which is always the LSI clock.
mbed_official	87:085cde657901	175
mbed_official	87:085cde657901	176	(#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
mbed_official	87:085cde657901	177	frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
mbed_official	87:085cde657901	178	Depending on the device voltage range, the maximum frequency should
mbed_official	87:085cde657901	179	be adapted accordingly:
mbed_official	87:085cde657901	180	+-------------------------------------------------------------------------------------+
mbed_official	87:085cde657901	181	\| Latency \| HCLK clock frequency (MHz) \|
mbed_official	87:085cde657901	182	\| \|---------------------------------------------------------------------\|
mbed_official	87:085cde657901	183	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
mbed_official	87:085cde657901	184	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
mbed_official	87:085cde657901	185	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	186	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 22 \|0 < HCLK <= 20 \|
mbed_official	87:085cde657901	187	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	188	\|1WS(2CPU cycle)\|30 < HCLK <= 60 \|24 < HCLK <= 48 \|22 < HCLK <= 44 \|20 < HCLK <= 40 \|
mbed_official	87:085cde657901	189	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	190	\|2WS(3CPU cycle)\|60 < HCLK <= 90 \|48 < HCLK <= 72 \|44 < HCLK <= 66 \|40 < HCLK <= 60 \|
mbed_official	87:085cde657901	191	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	192	\|3WS(4CPU cycle)\|90 < HCLK <= 120\|72 < HCLK <= 96 \|66 < HCLK <= 88 \|60 < HCLK <= 80 \|
mbed_official	87:085cde657901	193	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	194	\|4WS(5CPU cycle)\|120< HCLK <= 150\|96 < HCLK <= 120\|88 < HCLK <= 110 \|80 < HCLK <= 100 \|
mbed_official	87:085cde657901	195	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	196	\|5WS(6CPU cycle)\|150< HCLK <= 168\|120< HCLK <= 144\|110 < HCLK <= 132\|100 < HCLK <= 120\|
mbed_official	87:085cde657901	197	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	198	\|6WS(7CPU cycle)\| NA \|144< HCLK <= 168\|132 < HCLK <= 154\|120 < HCLK <= 140\|
mbed_official	87:085cde657901	199	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	200	\|7WS(8CPU cycle)\| NA \| NA \|154 < HCLK <= 168\|140 < HCLK <= 160\|
mbed_official	87:085cde657901	201	+-------------------------------------------------------------------------------------+
mbed_official	87:085cde657901	202	(#) For the STM32F42xxx and STM32F43xxx devices, the maximum frequency
mbed_official	87:085cde657901	203	of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
mbed_official	87:085cde657901	204	Depending on the device voltage range, the maximum frequency should
mbed_official	87:085cde657901	205	be adapted accordingly:
mbed_official	87:085cde657901	206	+-------------------------------------------------------------------------------------+
mbed_official	87:085cde657901	207	\| Latency \| HCLK clock frequency (MHz) \|
mbed_official	87:085cde657901	208	\| \|---------------------------------------------------------------------\|
mbed_official	87:085cde657901	209	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
mbed_official	87:085cde657901	210	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
mbed_official	87:085cde657901	211	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	212	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 22 \|0 < HCLK <= 20 \|
mbed_official	87:085cde657901	213	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	214	\|1WS(2CPU cycle)\|30 < HCLK <= 60 \|24 < HCLK <= 48 \|22 < HCLK <= 44 \|20 < HCLK <= 40 \|
mbed_official	87:085cde657901	215	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	216	\|2WS(3CPU cycle)\|60 < HCLK <= 90 \|48 < HCLK <= 72 \|44 < HCLK <= 66 \|40 < HCLK <= 60 \|
mbed_official	87:085cde657901	217	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	218	\|3WS(4CPU cycle)\|90 < HCLK <= 120\|72 < HCLK <= 96 \|66 < HCLK <= 88 \|60 < HCLK <= 80 \|
mbed_official	87:085cde657901	219	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	220	\|4WS(5CPU cycle)\|120< HCLK <= 150\|96 < HCLK <= 120\|88 < HCLK <= 110 \|80 < HCLK <= 100 \|
mbed_official	87:085cde657901	221	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	222	\|5WS(6CPU cycle)\|150< HCLK <= 180\|120< HCLK <= 144\|110 < HCLK <= 132\|100 < HCLK <= 120\|
mbed_official	87:085cde657901	223	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	224	\|6WS(7CPU cycle)\| NA \|144< HCLK <= 168\|132 < HCLK <= 154\|120 < HCLK <= 140\|
mbed_official	87:085cde657901	225	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	226	\|7WS(8CPU cycle)\| NA \|168< HCLK <= 180\|154 < HCLK <= 176\|140 < HCLK <= 160\|
mbed_official	87:085cde657901	227	\|-------------------------------------------------------------------------------------\|
mbed_official	87:085cde657901	228	\|8WS(9CPU cycle)\| NA \| NA \|176 < HCLK <= 180\|160 < HCLK <= 180\|
mbed_official	87:085cde657901	229	+-------------------------------------------------------------------------------------+
mbed_official	87:085cde657901	230	(#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
mbed_official	87:085cde657901	231	PCLK2 84 MHz and PCLK1 42 MHz.
mbed_official	87:085cde657901	232	Depending on the device voltage range, the maximum frequency should
mbed_official	87:085cde657901	233	be adapted accordingly:
mbed_official	87:085cde657901	234	+-------------------------------------------------------------------------------------+
mbed_official	87:085cde657901	235	\| Latency \| HCLK clock frequency (MHz) \|
mbed_official	87:085cde657901	236	\| \|---------------------------------------------------------------------\|
mbed_official	87:085cde657901	237	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
mbed_official	87:085cde657901	238	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
mbed_official	87:085cde657901	239	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	240	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 22 \|0 < HCLK <= 20 \|
mbed_official	87:085cde657901	241	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	242	\|1WS(2CPU cycle)\|30 < HCLK <= 60 \|24 < HCLK <= 48 \|22 < HCLK <= 44 \|20 < HCLK <= 40 \|
mbed_official	87:085cde657901	243	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	244	\|2WS(3CPU cycle)\|60 < HCLK <= 84 \|48 < HCLK <= 72 \|44 < HCLK <= 66 \|40 < HCLK <= 60 \|
mbed_official	87:085cde657901	245	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	246	\|3WS(4CPU cycle)\| NA \|72 < HCLK <= 84 \|66 < HCLK <= 84 \|60 < HCLK <= 80 \|
mbed_official	87:085cde657901	247	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
mbed_official	87:085cde657901	248	\|4WS(5CPU cycle)\| NA \| NA \| NA \|80 < HCLK <= 84 \|
mbed_official	87:085cde657901	249	+-------------------------------------------------------------------------------------+
mbed_official	87:085cde657901	250	@endverbatim
mbed_official	87:085cde657901	251	* @{
mbed_official	87:085cde657901	252	*/
mbed_official	87:085cde657901	253
mbed_official	87:085cde657901	254	/**
mbed_official	87:085cde657901	255	* @brief Resets the RCC clock configuration to the default reset state.
mbed_official	87:085cde657901	256	* @note The default reset state of the clock configuration is given below:
mbed_official	87:085cde657901	257	* - HSI ON and used as system clock source
mbed_official	87:085cde657901	258	* - HSE, PLL and PLLI2S OFF
mbed_official	87:085cde657901	259	* - AHB, APB1 and APB2 prescaler set to 1.
mbed_official	87:085cde657901	260	* - CSS, MCO1 and MCO2 OFF
mbed_official	87:085cde657901	261	* - All interrupts disabled
mbed_official	87:085cde657901	262	* @note This function doesn't modify the configuration of the
mbed_official	87:085cde657901	263	* - Peripheral clocks
mbed_official	87:085cde657901	264	* - LSI, LSE and RTC clocks
mbed_official	87:085cde657901	265	* @param None
mbed_official	87:085cde657901	266	* @retval None
mbed_official	87:085cde657901	267	*/
mbed_official	87:085cde657901	268	void HAL_RCC_DeInit(void)
mbed_official	87:085cde657901	269	{
mbed_official	87:085cde657901	270	/* Set HSION bit */
mbed_official	87:085cde657901	271	SET_BIT(RCC->CR, RCC_CR_HSION \| RCC_CR_HSITRIM_4);
mbed_official	87:085cde657901	272
mbed_official	87:085cde657901	273	/* Reset CFGR register */
mbed_official	87:085cde657901	274	CLEAR_REG(RCC->CFGR);
mbed_official	87:085cde657901	275
mbed_official	87:085cde657901	276	/* Reset HSEON, CSSON, PLLON, PLLI2S */
mbed_official	87:085cde657901	277	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_CSSON \| RCC_CR_PLLON\| RCC_CR_PLLI2SON);
mbed_official	87:085cde657901	278
mbed_official	87:085cde657901	279	/* Reset PLLCFGR register */
mbed_official	87:085cde657901	280	CLEAR_REG(RCC->PLLCFGR);
mbed_official	87:085cde657901	281	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLN_6 \| RCC_PLLCFGR_PLLN_7 \| RCC_PLLCFGR_PLLQ_2);
mbed_official	87:085cde657901	282
mbed_official	87:085cde657901	283	/* Reset PLLI2SCFGR register */
mbed_official	87:085cde657901	284	CLEAR_REG(RCC->PLLI2SCFGR);
mbed_official	87:085cde657901	285	SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 \| RCC_PLLI2SCFGR_PLLI2SN_7 \| RCC_PLLI2SCFGR_PLLI2SR_1);
mbed_official	87:085cde657901	286
mbed_official	87:085cde657901	287	/* Reset HSEBYP bit */
mbed_official	87:085cde657901	288	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
mbed_official	87:085cde657901	289
mbed_official	87:085cde657901	290	/* Disable all interrupts */
mbed_official	87:085cde657901	291	CLEAR_REG(RCC->CIR);
mbed_official	87:085cde657901	292	}
mbed_official	87:085cde657901	293
mbed_official	87:085cde657901	294	/**
mbed_official	87:085cde657901	295	* @brief Initializes the RCC Oscillators according to the specified parameters in the
mbed_official	87:085cde657901	296	* RCC_OscInitTypeDef.
mbed_official	87:085cde657901	297	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official	87:085cde657901	298	* contains the configuration information for the RCC Oscillators.
mbed_official	87:085cde657901	299	* @note The PLL is not disabled when used as system clock.
mbed_official	87:085cde657901	300	* @retval HAL status
mbed_official	87:085cde657901	301	*/
mbed_official	87:085cde657901	302	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official	87:085cde657901	303	{
mbed_official	87:085cde657901	304
mbed_official	87:085cde657901	305	uint32_t timeout = 0;
mbed_official	87:085cde657901	306
mbed_official	87:085cde657901	307	/* Check the parameters */
mbed_official	87:085cde657901	308	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
mbed_official	87:085cde657901	309	/------------------------------- HSE Configuration ------------------------/
mbed_official	87:085cde657901	310	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
mbed_official	87:085cde657901	311	{
mbed_official	87:085cde657901	312	/* Check the parameters */
mbed_official	87:085cde657901	313	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
mbed_official	87:085cde657901	314	/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
mbed_official	87:085cde657901	315	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
mbed_official	87:085cde657901	316	{
mbed_official	87:085cde657901	317	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
mbed_official	87:085cde657901	318	{
mbed_official	87:085cde657901	319	return HAL_ERROR;
mbed_official	87:085cde657901	320	}
mbed_official	87:085cde657901	321	}
mbed_official	87:085cde657901	322	else
mbed_official	87:085cde657901	323	{
mbed_official	87:085cde657901	324	/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
mbed_official	87:085cde657901	325	__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
mbed_official	87:085cde657901	326
mbed_official	87:085cde657901	327	/* Get timeout */
mbed_official	87:085cde657901	328	timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE;
mbed_official	87:085cde657901	329
mbed_official	87:085cde657901	330	/* Wait till HSE is disabled */
mbed_official	87:085cde657901	331	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
mbed_official	87:085cde657901	332	{
mbed_official	87:085cde657901	333	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	334	{
mbed_official	87:085cde657901	335	return HAL_TIMEOUT;
mbed_official	87:085cde657901	336	}
mbed_official	87:085cde657901	337	}
mbed_official	87:085cde657901	338
mbed_official	87:085cde657901	339	/* Set the new HSE configuration ---------------------------------------*/
mbed_official	87:085cde657901	340	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
mbed_official	87:085cde657901	341
mbed_official	87:085cde657901	342	/* Check the HSE State */
mbed_official	87:085cde657901	343	if((RCC_OscInitStruct->HSEState) == RCC_HSE_ON)
mbed_official	87:085cde657901	344	{
mbed_official	87:085cde657901	345	/* Get timeout */
mbed_official	87:085cde657901	346	timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE;
mbed_official	87:085cde657901	347
mbed_official	87:085cde657901	348	/* Wait till HSE is ready */
mbed_official	87:085cde657901	349	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official	87:085cde657901	350	{
mbed_official	87:085cde657901	351	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	352	{
mbed_official	87:085cde657901	353	return HAL_TIMEOUT;
mbed_official	87:085cde657901	354	}
mbed_official	87:085cde657901	355	}
mbed_official	87:085cde657901	356	}
mbed_official	87:085cde657901	357	else
mbed_official	87:085cde657901	358	{
mbed_official	87:085cde657901	359	/* Get timeout */
mbed_official	87:085cde657901	360	timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE;
mbed_official	87:085cde657901	361
mbed_official	87:085cde657901	362	/* Wait till HSE is bypassed or disabled */
mbed_official	87:085cde657901	363	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
mbed_official	87:085cde657901	364	{
mbed_official	87:085cde657901	365	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	366	{
mbed_official	87:085cde657901	367	return HAL_TIMEOUT;
mbed_official	87:085cde657901	368	}
mbed_official	87:085cde657901	369	}
mbed_official	87:085cde657901	370	}
mbed_official	87:085cde657901	371	}
mbed_official	87:085cde657901	372	}
mbed_official	87:085cde657901	373	/----------------------------- HSI Configuration --------------------------/
mbed_official	87:085cde657901	374	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
mbed_official	87:085cde657901	375	{
mbed_official	87:085cde657901	376	/* Check the parameters */
mbed_official	87:085cde657901	377	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
mbed_official	87:085cde657901	378	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
mbed_official	87:085cde657901	379
mbed_official	87:085cde657901	380	/* When the HSI is used as system clock it will not disabled */
mbed_official	87:085cde657901	381	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
mbed_official	87:085cde657901	382	{
mbed_official	87:085cde657901	383	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
mbed_official	87:085cde657901	384	{
mbed_official	87:085cde657901	385	return HAL_ERROR;
mbed_official	87:085cde657901	386	}
mbed_official	87:085cde657901	387	}
mbed_official	87:085cde657901	388	else
mbed_official	87:085cde657901	389	{
mbed_official	87:085cde657901	390	/* Check the HSI State */
mbed_official	87:085cde657901	391	if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
mbed_official	87:085cde657901	392	{
mbed_official	87:085cde657901	393	/* Enable the Internal High Speed oscillator (HSI). */
mbed_official	87:085cde657901	394	__HAL_RCC_HSI_ENABLE();
mbed_official	87:085cde657901	395
mbed_official	87:085cde657901	396	/* Get timeout */
mbed_official	87:085cde657901	397	timeout = HAL_GetTick() + HSI_TIMEOUT_VALUE;
mbed_official	87:085cde657901	398
mbed_official	87:085cde657901	399	/* Wait till HSI is ready */
mbed_official	87:085cde657901	400	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official	87:085cde657901	401	{
mbed_official	87:085cde657901	402	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	403	{
mbed_official	87:085cde657901	404	return HAL_TIMEOUT;
mbed_official	87:085cde657901	405	}
mbed_official	87:085cde657901	406	}
mbed_official	87:085cde657901	407
mbed_official	87:085cde657901	408	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
mbed_official	87:085cde657901	409	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
mbed_official	87:085cde657901	410	}
mbed_official	87:085cde657901	411	else
mbed_official	87:085cde657901	412	{
mbed_official	87:085cde657901	413	/* Disable the Internal High Speed oscillator (HSI). */
mbed_official	87:085cde657901	414	__HAL_RCC_HSI_DISABLE();
mbed_official	87:085cde657901	415
mbed_official	87:085cde657901	416	/* Get timeout */
mbed_official	87:085cde657901	417	timeout = HAL_GetTick() + HSI_TIMEOUT_VALUE;
mbed_official	87:085cde657901	418
mbed_official	87:085cde657901	419	/* Wait till HSI is ready */
mbed_official	87:085cde657901	420	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
mbed_official	87:085cde657901	421	{
mbed_official	87:085cde657901	422	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	423	{
mbed_official	87:085cde657901	424	return HAL_TIMEOUT;
mbed_official	87:085cde657901	425	}
mbed_official	87:085cde657901	426	}
mbed_official	87:085cde657901	427	}
mbed_official	87:085cde657901	428	}
mbed_official	87:085cde657901	429	}
mbed_official	87:085cde657901	430	/------------------------------ LSI Configuration -------------------------/
mbed_official	87:085cde657901	431	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
mbed_official	87:085cde657901	432	{
mbed_official	87:085cde657901	433	/* Check the parameters */
mbed_official	87:085cde657901	434	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
mbed_official	87:085cde657901	435
mbed_official	87:085cde657901	436	/* Check the LSI State */
mbed_official	87:085cde657901	437	if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
mbed_official	87:085cde657901	438	{
mbed_official	87:085cde657901	439	/* Enable the Internal Low Speed oscillator (LSI). */
mbed_official	87:085cde657901	440	__HAL_RCC_LSI_ENABLE();
mbed_official	87:085cde657901	441
mbed_official	87:085cde657901	442	/* Get timeout */
mbed_official	87:085cde657901	443	timeout = HAL_GetTick() + LSI_TIMEOUT_VALUE;
mbed_official	87:085cde657901	444
mbed_official	87:085cde657901	445	/* Wait till LSI is ready */
mbed_official	87:085cde657901	446	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
mbed_official	87:085cde657901	447	{
mbed_official	87:085cde657901	448	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	449	{
mbed_official	87:085cde657901	450	return HAL_TIMEOUT;
mbed_official	87:085cde657901	451	}
mbed_official	87:085cde657901	452	}
mbed_official	87:085cde657901	453	}
mbed_official	87:085cde657901	454	else
mbed_official	87:085cde657901	455	{
mbed_official	87:085cde657901	456	/* Disable the Internal Low Speed oscillator (LSI). */
mbed_official	87:085cde657901	457	__HAL_RCC_LSI_DISABLE();
mbed_official	87:085cde657901	458
mbed_official	87:085cde657901	459	/* Get timeout */
mbed_official	87:085cde657901	460	timeout = HAL_GetTick() + LSI_TIMEOUT_VALUE;
mbed_official	87:085cde657901	461
mbed_official	87:085cde657901	462	/* Wait till LSI is ready */
mbed_official	87:085cde657901	463	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
mbed_official	87:085cde657901	464	{
mbed_official	87:085cde657901	465	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	466	{
mbed_official	87:085cde657901	467	return HAL_TIMEOUT;
mbed_official	87:085cde657901	468	}
mbed_official	87:085cde657901	469	}
mbed_official	87:085cde657901	470	}
mbed_official	87:085cde657901	471	}
mbed_official	87:085cde657901	472	/------------------------------ LSE Configuration -------------------------/
mbed_official	87:085cde657901	473	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
mbed_official	87:085cde657901	474	{
mbed_official	87:085cde657901	475	/* Check the parameters */
mbed_official	87:085cde657901	476	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
mbed_official	87:085cde657901	477
mbed_official	106:ced8cbb51063	478	/* Enable Power Clock*/
mbed_official	106:ced8cbb51063	479	__PWR_CLK_ENABLE();
mbed_official	106:ced8cbb51063	480
mbed_official	106:ced8cbb51063	481	/* Enable write access to Backup domain */
mbed_official	106:ced8cbb51063	482	PWR->CR \|= PWR_CR_DBP;
mbed_official	106:ced8cbb51063	483
mbed_official	106:ced8cbb51063	484	/* Wait for Backup domain Write protection disable */
mbed_official	106:ced8cbb51063	485	timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE;
mbed_official	106:ced8cbb51063	486
mbed_official	106:ced8cbb51063	487	while((PWR->CR & PWR_CR_DBP) == RESET)
mbed_official	87:085cde657901	488	{
mbed_official	106:ced8cbb51063	489	if(HAL_GetTick() >= timeout)
mbed_official	106:ced8cbb51063	490	{
mbed_official	106:ced8cbb51063	491	return HAL_TIMEOUT;
mbed_official	106:ced8cbb51063	492	}
mbed_official	87:085cde657901	493	}
mbed_official	106:ced8cbb51063	494
mbed_official	87:085cde657901	495	/* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
mbed_official	87:085cde657901	496	__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
mbed_official	87:085cde657901	497
mbed_official	87:085cde657901	498	/* Get timeout */
mbed_official	87:085cde657901	499	timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
mbed_official	87:085cde657901	500
mbed_official	87:085cde657901	501	/* Wait till LSE is ready */
mbed_official	87:085cde657901	502	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
mbed_official	87:085cde657901	503	{
mbed_official	87:085cde657901	504	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	505	{
mbed_official	87:085cde657901	506	return HAL_TIMEOUT;
mbed_official	87:085cde657901	507	}
mbed_official	87:085cde657901	508	}
mbed_official	87:085cde657901	509
mbed_official	87:085cde657901	510	/* Set the new LSE configuration -----------------------------------------*/
mbed_official	87:085cde657901	511	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
mbed_official	87:085cde657901	512	/* Check the LSE State */
mbed_official	87:085cde657901	513	if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
mbed_official	87:085cde657901	514	{
mbed_official	87:085cde657901	515	/* Get timeout */
mbed_official	87:085cde657901	516	timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
mbed_official	87:085cde657901	517
mbed_official	87:085cde657901	518	/* Wait till LSE is ready */
mbed_official	87:085cde657901	519	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official	87:085cde657901	520	{
mbed_official	87:085cde657901	521	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	522	{
mbed_official	87:085cde657901	523	return HAL_TIMEOUT;
mbed_official	87:085cde657901	524	}
mbed_official	87:085cde657901	525	}
mbed_official	87:085cde657901	526	}
mbed_official	87:085cde657901	527	else
mbed_official	87:085cde657901	528	{
mbed_official	87:085cde657901	529	/* Get timeout */
mbed_official	87:085cde657901	530	timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
mbed_official	87:085cde657901	531
mbed_official	87:085cde657901	532	/* Wait till LSE is ready */
mbed_official	87:085cde657901	533	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
mbed_official	87:085cde657901	534	{
mbed_official	87:085cde657901	535	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	536	{
mbed_official	87:085cde657901	537	return HAL_TIMEOUT;
mbed_official	87:085cde657901	538	}
mbed_official	87:085cde657901	539	}
mbed_official	87:085cde657901	540	}
mbed_official	87:085cde657901	541	}
mbed_official	87:085cde657901	542	/-------------------------------- PLL Configuration -----------------------/
mbed_official	87:085cde657901	543	/* Check the parameters */
mbed_official	87:085cde657901	544	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
mbed_official	87:085cde657901	545	if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
mbed_official	87:085cde657901	546	{
mbed_official	87:085cde657901	547	/* Check if the PLL is used as system clock or not */
mbed_official	87:085cde657901	548	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
mbed_official	87:085cde657901	549	{
mbed_official	87:085cde657901	550	if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
mbed_official	87:085cde657901	551	{
mbed_official	87:085cde657901	552	/* Check the parameters */
mbed_official	87:085cde657901	553	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
mbed_official	87:085cde657901	554	assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
mbed_official	87:085cde657901	555	assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
mbed_official	87:085cde657901	556	assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
mbed_official	87:085cde657901	557	assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
mbed_official	87:085cde657901	558
mbed_official	87:085cde657901	559	/* Disable the main PLL. */
mbed_official	87:085cde657901	560	__HAL_RCC_PLL_DISABLE();
mbed_official	87:085cde657901	561
mbed_official	87:085cde657901	562	/* Get timeout */
mbed_official	87:085cde657901	563	timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE;
mbed_official	87:085cde657901	564
mbed_official	87:085cde657901	565	/* Wait till PLL is ready */
mbed_official	87:085cde657901	566	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
mbed_official	87:085cde657901	567	{
mbed_official	87:085cde657901	568	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	569	{
mbed_official	87:085cde657901	570	return HAL_TIMEOUT;
mbed_official	87:085cde657901	571	}
mbed_official	87:085cde657901	572	}
mbed_official	87:085cde657901	573
mbed_official	87:085cde657901	574	/* Configure the main PLL clock source, multiplication and division factors. */
mbed_official	87:085cde657901	575	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
mbed_official	87:085cde657901	576	RCC_OscInitStruct->PLL.PLLM,
mbed_official	87:085cde657901	577	RCC_OscInitStruct->PLL.PLLN,
mbed_official	87:085cde657901	578	RCC_OscInitStruct->PLL.PLLP,
mbed_official	87:085cde657901	579	RCC_OscInitStruct->PLL.PLLQ);
mbed_official	87:085cde657901	580	/* Enable the main PLL. */
mbed_official	87:085cde657901	581	__HAL_RCC_PLL_ENABLE();
mbed_official	87:085cde657901	582
mbed_official	87:085cde657901	583	/* Get timeout */
mbed_official	87:085cde657901	584	timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE;
mbed_official	87:085cde657901	585
mbed_official	87:085cde657901	586	/* Wait till PLL is ready */
mbed_official	87:085cde657901	587	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official	87:085cde657901	588	{
mbed_official	87:085cde657901	589	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	590	{
mbed_official	87:085cde657901	591	return HAL_TIMEOUT;
mbed_official	87:085cde657901	592	}
mbed_official	87:085cde657901	593	}
mbed_official	87:085cde657901	594	}
mbed_official	87:085cde657901	595	else
mbed_official	87:085cde657901	596	{
mbed_official	87:085cde657901	597	/* Disable the main PLL. */
mbed_official	87:085cde657901	598	__HAL_RCC_PLL_DISABLE();
mbed_official	87:085cde657901	599	/* Get timeout */
mbed_official	87:085cde657901	600	timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE;
mbed_official	87:085cde657901	601
mbed_official	87:085cde657901	602	/* Wait till PLL is ready */
mbed_official	87:085cde657901	603	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
mbed_official	87:085cde657901	604	{
mbed_official	87:085cde657901	605	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	606	{
mbed_official	87:085cde657901	607	return HAL_TIMEOUT;
mbed_official	87:085cde657901	608	}
mbed_official	87:085cde657901	609	}
mbed_official	87:085cde657901	610	}
mbed_official	87:085cde657901	611	}
mbed_official	87:085cde657901	612	else
mbed_official	87:085cde657901	613	{
mbed_official	87:085cde657901	614	return HAL_ERROR;
mbed_official	87:085cde657901	615	}
mbed_official	87:085cde657901	616	}
mbed_official	87:085cde657901	617	return HAL_OK;
mbed_official	87:085cde657901	618	}
mbed_official	87:085cde657901	619
mbed_official	87:085cde657901	620	/**
mbed_official	87:085cde657901	621	* @brief Initializes the CPU, AHB and APB busses clocks according to the specified
mbed_official	87:085cde657901	622	* parameters in the RCC_ClkInitStruct.
mbed_official	87:085cde657901	623	* @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official	87:085cde657901	624	* contains the configuration information for the RCC peripheral.
mbed_official	87:085cde657901	625	* @param FLatency: FLASH Latency, this parameter depend on device selected
mbed_official	87:085cde657901	626	*
mbed_official	87:085cde657901	627	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
mbed_official	87:085cde657901	628	* and updated by HAL_RCC_GetHCLKFreq() function called within this function
mbed_official	87:085cde657901	629	*
mbed_official	87:085cde657901	630	* @note The HSI is used (enabled by hardware) as system clock source after
mbed_official	87:085cde657901	631	* startup from Reset, wake-up from STOP and STANDBY mode, or in case
mbed_official	87:085cde657901	632	* of failure of the HSE used directly or indirectly as system clock
mbed_official	87:085cde657901	633	* (if the Clock Security System CSS is enabled).
mbed_official	87:085cde657901	634	*
mbed_official	87:085cde657901	635	* @note A switch from one clock source to another occurs only if the target
mbed_official	87:085cde657901	636	* clock source is ready (clock stable after startup delay or PLL locked).
mbed_official	87:085cde657901	637	* If a clock source which is not yet ready is selected, the switch will
mbed_official	87:085cde657901	638	* occur when the clock source will be ready.
mbed_official	87:085cde657901	639	*
mbed_official	87:085cde657901	640	* @note Depending on the device voltage range, the software has to set correctly
mbed_official	87:085cde657901	641	* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
mbed_official	87:085cde657901	642	* (for more details refer to section above "Initialization/de-initialization functions")
mbed_official	87:085cde657901	643	* @retval None
mbed_official	87:085cde657901	644	*/
mbed_official	87:085cde657901	645	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
mbed_official	87:085cde657901	646	{
mbed_official	87:085cde657901	647
mbed_official	87:085cde657901	648	uint32_t timeout = 0;
mbed_official	87:085cde657901	649
mbed_official	87:085cde657901	650	/* Check the parameters */
mbed_official	87:085cde657901	651	assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
mbed_official	87:085cde657901	652	assert_param(IS_FLASH_LATENCY(FLatency));
mbed_official	87:085cde657901	653
mbed_official	87:085cde657901	654	/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
mbed_official	87:085cde657901	655	must be correctly programmed according to the frequency of the CPU clock
mbed_official	87:085cde657901	656	(HCLK) and the supply voltage of the device. */
mbed_official	87:085cde657901	657
mbed_official	87:085cde657901	658	/* Increasing the CPU frequency */
mbed_official	87:085cde657901	659	if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
mbed_official	87:085cde657901	660	{
mbed_official	87:085cde657901	661	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
mbed_official	87:085cde657901	662	__HAL_FLASH_SET_LATENCY(FLatency);
mbed_official	87:085cde657901	663
mbed_official	87:085cde657901	664	/* Check that the new number of wait states is taken into account to access the Flash
mbed_official	87:085cde657901	665	memory by reading the FLASH_ACR register */
mbed_official	87:085cde657901	666	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
mbed_official	87:085cde657901	667	{
mbed_official	87:085cde657901	668	return HAL_ERROR;
mbed_official	87:085cde657901	669	}
mbed_official	87:085cde657901	670
mbed_official	87:085cde657901	671	/------------------------- SYSCLK Configuration ---------------------------/
mbed_official	87:085cde657901	672	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
mbed_official	87:085cde657901	673	{
mbed_official	87:085cde657901	674	assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
mbed_official	87:085cde657901	675
mbed_official	87:085cde657901	676	/* HSE is selected as System Clock Source */
mbed_official	87:085cde657901	677	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official	87:085cde657901	678	{
mbed_official	87:085cde657901	679	/* Check the HSE ready flag */
mbed_official	87:085cde657901	680	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official	87:085cde657901	681	{
mbed_official	87:085cde657901	682	return HAL_ERROR;
mbed_official	87:085cde657901	683	}
mbed_official	87:085cde657901	684	}
mbed_official	87:085cde657901	685	/* PLL is selected as System Clock Source */
mbed_official	87:085cde657901	686	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official	87:085cde657901	687	{
mbed_official	87:085cde657901	688	/* Check the PLL ready flag */
mbed_official	87:085cde657901	689	if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official	87:085cde657901	690	{
mbed_official	87:085cde657901	691	return HAL_ERROR;
mbed_official	87:085cde657901	692	}
mbed_official	87:085cde657901	693	}
mbed_official	87:085cde657901	694	/* HSI is selected as System Clock Source */
mbed_official	87:085cde657901	695	else
mbed_official	87:085cde657901	696	{
mbed_official	87:085cde657901	697	/* Check the HSI ready flag */
mbed_official	87:085cde657901	698	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official	87:085cde657901	699	{
mbed_official	87:085cde657901	700	return HAL_ERROR;
mbed_official	87:085cde657901	701	}
mbed_official	87:085cde657901	702	}
mbed_official	87:085cde657901	703	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
mbed_official	87:085cde657901	704
mbed_official	87:085cde657901	705	/* Get timeout */
mbed_official	87:085cde657901	706	timeout = HAL_GetTick() + CLOCKSWITCH_TIMEOUT_VALUE;
mbed_official	87:085cde657901	707
mbed_official	87:085cde657901	708	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official	87:085cde657901	709	{
mbed_official	87:085cde657901	710	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
mbed_official	87:085cde657901	711	{
mbed_official	87:085cde657901	712	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	713	{
mbed_official	87:085cde657901	714	return HAL_TIMEOUT;
mbed_official	87:085cde657901	715	}
mbed_official	87:085cde657901	716	}
mbed_official	87:085cde657901	717	}
mbed_official	87:085cde657901	718	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official	87:085cde657901	719	{
mbed_official	87:085cde657901	720	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
mbed_official	87:085cde657901	721	{
mbed_official	87:085cde657901	722	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	723	{
mbed_official	87:085cde657901	724	return HAL_TIMEOUT;
mbed_official	87:085cde657901	725	}
mbed_official	87:085cde657901	726	}
mbed_official	87:085cde657901	727	}
mbed_official	87:085cde657901	728	else
mbed_official	87:085cde657901	729	{
mbed_official	87:085cde657901	730	while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
mbed_official	87:085cde657901	731	{
mbed_official	87:085cde657901	732	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	733	{
mbed_official	87:085cde657901	734	return HAL_TIMEOUT;
mbed_official	87:085cde657901	735	}
mbed_official	87:085cde657901	736	}
mbed_official	87:085cde657901	737	}
mbed_official	87:085cde657901	738	}
mbed_official	87:085cde657901	739	}
mbed_official	87:085cde657901	740	/* Decreasing the CPU frequency */
mbed_official	87:085cde657901	741	else
mbed_official	87:085cde657901	742	{
mbed_official	87:085cde657901	743	/------------------------- SYSCLK Configuration ---------------------------/
mbed_official	87:085cde657901	744	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
mbed_official	87:085cde657901	745	{
mbed_official	87:085cde657901	746	assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
mbed_official	87:085cde657901	747
mbed_official	87:085cde657901	748	/* HSE is selected as System Clock Source */
mbed_official	87:085cde657901	749	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official	87:085cde657901	750	{
mbed_official	87:085cde657901	751	/* Check the HSE ready flag */
mbed_official	87:085cde657901	752	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official	87:085cde657901	753	{
mbed_official	87:085cde657901	754	return HAL_ERROR;
mbed_official	87:085cde657901	755	}
mbed_official	87:085cde657901	756	}
mbed_official	87:085cde657901	757	/* PLL is selected as System Clock Source */
mbed_official	87:085cde657901	758	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official	87:085cde657901	759	{
mbed_official	87:085cde657901	760	/* Check the PLL ready flag */
mbed_official	87:085cde657901	761	if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official	87:085cde657901	762	{
mbed_official	87:085cde657901	763	return HAL_ERROR;
mbed_official	87:085cde657901	764	}
mbed_official	87:085cde657901	765	}
mbed_official	87:085cde657901	766	/* HSI is selected as System Clock Source */
mbed_official	87:085cde657901	767	else
mbed_official	87:085cde657901	768	{
mbed_official	87:085cde657901	769	/* Check the HSI ready flag */
mbed_official	87:085cde657901	770	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official	87:085cde657901	771	{
mbed_official	87:085cde657901	772	return HAL_ERROR;
mbed_official	87:085cde657901	773	}
mbed_official	87:085cde657901	774	}
mbed_official	87:085cde657901	775	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
mbed_official	87:085cde657901	776
mbed_official	87:085cde657901	777	/* Get timeout */
mbed_official	87:085cde657901	778	timeout = HAL_GetTick() + CLOCKSWITCH_TIMEOUT_VALUE;
mbed_official	87:085cde657901	779
mbed_official	87:085cde657901	780	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official	87:085cde657901	781	{
mbed_official	87:085cde657901	782	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
mbed_official	87:085cde657901	783	{
mbed_official	87:085cde657901	784	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	785	{
mbed_official	87:085cde657901	786	return HAL_TIMEOUT;
mbed_official	87:085cde657901	787	}
mbed_official	87:085cde657901	788	}
mbed_official	87:085cde657901	789	}
mbed_official	87:085cde657901	790	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official	87:085cde657901	791	{
mbed_official	87:085cde657901	792	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
mbed_official	87:085cde657901	793	{
mbed_official	87:085cde657901	794	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	795	{
mbed_official	87:085cde657901	796	return HAL_TIMEOUT;
mbed_official	87:085cde657901	797	}
mbed_official	87:085cde657901	798	}
mbed_official	87:085cde657901	799	}
mbed_official	87:085cde657901	800	else
mbed_official	87:085cde657901	801	{
mbed_official	87:085cde657901	802	while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
mbed_official	87:085cde657901	803	{
mbed_official	87:085cde657901	804	if(HAL_GetTick() >= timeout)
mbed_official	87:085cde657901	805	{
mbed_official	87:085cde657901	806	return HAL_TIMEOUT;
mbed_official	87:085cde657901	807	}
mbed_official	87:085cde657901	808	}
mbed_official	87:085cde657901	809	}
mbed_official	87:085cde657901	810	}
mbed_official	87:085cde657901	811
mbed_official	87:085cde657901	812	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
mbed_official	87:085cde657901	813	__HAL_FLASH_SET_LATENCY(FLatency);
mbed_official	87:085cde657901	814
mbed_official	87:085cde657901	815	/* Check that the new number of wait states is taken into account to access the Flash
mbed_official	87:085cde657901	816	memory by reading the FLASH_ACR register */
mbed_official	87:085cde657901	817	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
mbed_official	87:085cde657901	818	{
mbed_official	87:085cde657901	819	return HAL_ERROR;
mbed_official	87:085cde657901	820	}
mbed_official	87:085cde657901	821	}
mbed_official	87:085cde657901	822
mbed_official	87:085cde657901	823	/-------------------------- HCLK Configuration ----------------------------/
mbed_official	87:085cde657901	824	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
mbed_official	87:085cde657901	825	{
mbed_official	87:085cde657901	826	assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
mbed_official	87:085cde657901	827	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
mbed_official	87:085cde657901	828	}
mbed_official	87:085cde657901	829
mbed_official	87:085cde657901	830	/-------------------------- PCLK1 Configuration ---------------------------/
mbed_official	87:085cde657901	831	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
mbed_official	87:085cde657901	832	{
mbed_official	87:085cde657901	833	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
mbed_official	87:085cde657901	834	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
mbed_official	87:085cde657901	835	}
mbed_official	87:085cde657901	836
mbed_official	87:085cde657901	837	/-------------------------- PCLK2 Configuration ---------------------------/
mbed_official	87:085cde657901	838	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
mbed_official	87:085cde657901	839	{
mbed_official	87:085cde657901	840	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
mbed_official	87:085cde657901	841	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
mbed_official	87:085cde657901	842	}
mbed_official	87:085cde657901	843
mbed_official	87:085cde657901	844	/* Setup SysTick Timer for 1 msec interrupts.
mbed_official	87:085cde657901	845	------------------------------------------
mbed_official	87:085cde657901	846	The SysTick_Config() function is a CMSIS function which configure:
mbed_official	87:085cde657901	847	- The SysTick Reload register with value passed as function parameter.
mbed_official	87:085cde657901	848	- Configure the SysTick IRQ priority to the lowest value (0x0F).
mbed_official	87:085cde657901	849	- Reset the SysTick Counter register.
mbed_official	87:085cde657901	850	- Configure the SysTick Counter clock source to be Core Clock Source (HCLK).
mbed_official	87:085cde657901	851	- Enable the SysTick Interrupt.
mbed_official	87:085cde657901	852	- Start the SysTick Counter.*/
mbed_official	87:085cde657901	853	SysTick_Config(HAL_RCC_GetHCLKFreq() / 1000);
mbed_official	87:085cde657901	854
mbed_official	87:085cde657901	855	return HAL_OK;
mbed_official	87:085cde657901	856	}
mbed_official	87:085cde657901	857
mbed_official	87:085cde657901	858	/**
mbed_official	87:085cde657901	859	* @}
mbed_official	87:085cde657901	860	*/
mbed_official	87:085cde657901	861
mbed_official	87:085cde657901	862	/** @defgroup RCC_Group2 Peripheral Control functions
mbed_official	87:085cde657901	863	* @brief RCC clocks control functions
mbed_official	87:085cde657901	864	*
mbed_official	87:085cde657901	865	@verbatim
mbed_official	87:085cde657901	866	===============================================================================
mbed_official	87:085cde657901	867	##### Peripheral Control functions #####
mbed_official	87:085cde657901	868	===============================================================================
mbed_official	87:085cde657901	869	[..]
mbed_official	87:085cde657901	870	This subsection provides a set of functions allowing to control the RCC Clocks
mbed_official	87:085cde657901	871	frequencies.
mbed_official	87:085cde657901	872
mbed_official	87:085cde657901	873	@endverbatim
mbed_official	87:085cde657901	874	* @{
mbed_official	87:085cde657901	875	*/
mbed_official	87:085cde657901	876
mbed_official	87:085cde657901	877	/**
mbed_official	87:085cde657901	878	* @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
mbed_official	87:085cde657901	879	* @note PA8/PC9 should be configured in alternate function mode.
mbed_official	87:085cde657901	880	* @param RCC_MCOx: specifies the output direction for the clock source.
mbed_official	87:085cde657901	881	* This parameter can be one of the following values:
mbed_official	87:085cde657901	882	* @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
mbed_official	87:085cde657901	883	* @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
mbed_official	87:085cde657901	884	* @param RCC_MCOSource: specifies the clock source to output.
mbed_official	87:085cde657901	885	* This parameter can be one of the following values:
mbed_official	87:085cde657901	886	* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
mbed_official	87:085cde657901	887	* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
mbed_official	87:085cde657901	888	* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
mbed_official	87:085cde657901	889	* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
mbed_official	87:085cde657901	890	* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
mbed_official	87:085cde657901	891	* @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
mbed_official	87:085cde657901	892	* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
mbed_official	87:085cde657901	893	* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
mbed_official	87:085cde657901	894	* @param RCC_MCODiv: specifies the MCOx prescaler.
mbed_official	87:085cde657901	895	* This parameter can be one of the following values:
mbed_official	87:085cde657901	896	* @arg RCC_MCODIV_1: no division applied to MCOx clock
mbed_official	87:085cde657901	897	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
mbed_official	87:085cde657901	898	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
mbed_official	87:085cde657901	899	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
mbed_official	87:085cde657901	900	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
mbed_official	87:085cde657901	901	* @retval None
mbed_official	87:085cde657901	902	*/
mbed_official	87:085cde657901	903	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
mbed_official	87:085cde657901	904	{
mbed_official	87:085cde657901	905	GPIO_InitTypeDef GPIO_InitStruct;
mbed_official	87:085cde657901	906	/* Check the parameters */
mbed_official	87:085cde657901	907	assert_param(IS_RCC_MCO(RCC_MCOx));
mbed_official	87:085cde657901	908	assert_param(IS_RCC_MCODIV(RCC_MCODiv));
mbed_official	87:085cde657901	909	/* RCC_MCO1 */
mbed_official	87:085cde657901	910	if(RCC_MCOx == RCC_MCO1)
mbed_official	87:085cde657901	911	{
mbed_official	87:085cde657901	912	assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
mbed_official	87:085cde657901	913
mbed_official	87:085cde657901	914	/* MCO1 Clock Enable */
mbed_official	87:085cde657901	915	__MCO1_CLK_ENABLE();
mbed_official	87:085cde657901	916
mbed_official	87:085cde657901	917	/* Configue the MCO1 pin in alternate function mode */
mbed_official	87:085cde657901	918	GPIO_InitStruct.Pin = MCO1_PIN;
mbed_official	87:085cde657901	919	GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
mbed_official	87:085cde657901	920	GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
mbed_official	87:085cde657901	921	GPIO_InitStruct.Pull = GPIO_NOPULL;
mbed_official	87:085cde657901	922	GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
mbed_official	87:085cde657901	923	HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
mbed_official	87:085cde657901	924
mbed_official	87:085cde657901	925	/* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
mbed_official	87:085cde657901	926	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 \| RCC_CFGR_MCO1PRE), (RCC_MCOSource \| RCC_MCODiv));
mbed_official	87:085cde657901	927	}
mbed_official	87:085cde657901	928	else
mbed_official	87:085cde657901	929	{
mbed_official	87:085cde657901	930	assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
mbed_official	87:085cde657901	931
mbed_official	87:085cde657901	932	/* MCO2 Clock Enable */
mbed_official	87:085cde657901	933	__MCO2_CLK_ENABLE();
mbed_official	87:085cde657901	934
mbed_official	87:085cde657901	935	/* Configue the MCO2 pin in alternate function mode */
mbed_official	87:085cde657901	936	GPIO_InitStruct.Pin = MCO2_PIN;
mbed_official	87:085cde657901	937	GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
mbed_official	87:085cde657901	938	GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
mbed_official	87:085cde657901	939	GPIO_InitStruct.Pull = GPIO_NOPULL;
mbed_official	87:085cde657901	940	GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
mbed_official	87:085cde657901	941	HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
mbed_official	87:085cde657901	942
mbed_official	87:085cde657901	943	/* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
mbed_official	87:085cde657901	944	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 \| RCC_CFGR_MCO2PRE), (RCC_MCOSource \| (RCC_MCODiv << 3)));
mbed_official	87:085cde657901	945	}
mbed_official	87:085cde657901	946	}
mbed_official	87:085cde657901	947
mbed_official	87:085cde657901	948	/**
mbed_official	87:085cde657901	949	* @brief Enables the Clock Security System.
mbed_official	87:085cde657901	950	* @note If a failure is detected on the HSE oscillator clock, this oscillator
mbed_official	87:085cde657901	951	* is automatically disabled and an interrupt is generated to inform the
mbed_official	87:085cde657901	952	* software about the failure (Clock Security System Interrupt, CSSI),
mbed_official	87:085cde657901	953	* allowing the MCU to perform rescue operations. The CSSI is linked to
mbed_official	87:085cde657901	954	* the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
mbed_official	87:085cde657901	955	* @param None
mbed_official	87:085cde657901	956	* @retval None
mbed_official	87:085cde657901	957	*/
mbed_official	87:085cde657901	958	void HAL_RCC_EnableCSS(void)
mbed_official	87:085cde657901	959	{
mbed_official	87:085cde657901	960	(__IO uint32_t ) CR_CSSON_BB = (uint32_t)ENABLE;
mbed_official	87:085cde657901	961	}
mbed_official	87:085cde657901	962
mbed_official	87:085cde657901	963	/**
mbed_official	87:085cde657901	964	* @brief Disables the Clock Security System.
mbed_official	87:085cde657901	965	* @param None
mbed_official	87:085cde657901	966	* @retval None
mbed_official	87:085cde657901	967	*/
mbed_official	87:085cde657901	968	void HAL_RCC_DisableCSS(void)
mbed_official	87:085cde657901	969	{
mbed_official	87:085cde657901	970	(__IO uint32_t ) CR_CSSON_BB = (uint32_t)DISABLE;
mbed_official	87:085cde657901	971	}
mbed_official	87:085cde657901	972
mbed_official	87:085cde657901	973	/**
mbed_official	87:085cde657901	974	* @brief Returns the SYSCLK frequency
mbed_official	87:085cde657901	975	*
mbed_official	87:085cde657901	976	* @note The system frequency computed by this function is not the real
mbed_official	87:085cde657901	977	* frequency in the chip. It is calculated based on the predefined
mbed_official	87:085cde657901	978	* constant and the selected clock source:
mbed_official	87:085cde657901	979	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
mbed_official	87:085cde657901	980	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
mbed_official	87:085cde657901	981	* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
mbed_official	87:085cde657901	982	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official	87:085cde657901	983	* @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official	87:085cde657901	984	* 16 MHz) but the real value may vary depending on the variations
mbed_official	87:085cde657901	985	* in voltage and temperature.
mbed_official	87:085cde657901	986	* @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official	87:085cde657901	987	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official	87:085cde657901	988	* frequency of the crystal used. Otherwise, this function may
mbed_official	87:085cde657901	989	* have wrong result.
mbed_official	87:085cde657901	990	*
mbed_official	87:085cde657901	991	* @note The result of this function could be not correct when using fractional
mbed_official	87:085cde657901	992	* value for HSE crystal.
mbed_official	87:085cde657901	993	*
mbed_official	87:085cde657901	994	* @note This function can be used by the user application to compute the
mbed_official	87:085cde657901	995	* baudrate for the communication peripherals or configure other parameters.
mbed_official	87:085cde657901	996	*
mbed_official	87:085cde657901	997	* @note Each time SYSCLK changes, this function must be called to update the
mbed_official	87:085cde657901	998	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official	87:085cde657901	999	*
mbed_official	87:085cde657901	1000	*
mbed_official	87:085cde657901	1001	* @param None
mbed_official	87:085cde657901	1002	* @retval SYSCLK frequency
mbed_official	87:085cde657901	1003	*/
mbed_official	87:085cde657901	1004	uint32_t HAL_RCC_GetSysClockFreq(void)
mbed_official	87:085cde657901	1005	{
mbed_official	87:085cde657901	1006	uint32_t pllm = 0, pllvco = 0, pllp = 0;
mbed_official	87:085cde657901	1007	uint32_t sysclockfreq = 0;
mbed_official	87:085cde657901	1008
mbed_official	87:085cde657901	1009	/* Get SYSCLK source -------------------------------------------------------*/
mbed_official	87:085cde657901	1010	switch (RCC->CFGR & RCC_CFGR_SWS)
mbed_official	87:085cde657901	1011	{
mbed_official	87:085cde657901	1012	case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
mbed_official	87:085cde657901	1013	{
mbed_official	87:085cde657901	1014	sysclockfreq = HSI_VALUE;
mbed_official	87:085cde657901	1015	break;
mbed_official	87:085cde657901	1016	}
mbed_official	87:085cde657901	1017	case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
mbed_official	87:085cde657901	1018	{
mbed_official	87:085cde657901	1019	sysclockfreq = HSE_VALUE;
mbed_official	87:085cde657901	1020	break;
mbed_official	87:085cde657901	1021	}
mbed_official	87:085cde657901	1022	case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
mbed_official	87:085cde657901	1023	{
mbed_official	87:085cde657901	1024	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
mbed_official	87:085cde657901	1025	SYSCLK = PLL_VCO / PLLP */
mbed_official	87:085cde657901	1026	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official	87:085cde657901	1027	if (__RCC_PLLSRC() != 0)
mbed_official	87:085cde657901	1028	{
mbed_official	87:085cde657901	1029	/* HSE used as PLL clock source */
mbed_official	87:085cde657901	1030	pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
mbed_official	87:085cde657901	1031	}
mbed_official	87:085cde657901	1032	else
mbed_official	87:085cde657901	1033	{
mbed_official	87:085cde657901	1034	/* HSI used as PLL clock source */
mbed_official	87:085cde657901	1035	pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
mbed_official	87:085cde657901	1036	}
mbed_official	87:085cde657901	1037	pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
mbed_official	87:085cde657901	1038
mbed_official	87:085cde657901	1039	sysclockfreq = pllvco/pllp;
mbed_official	87:085cde657901	1040	break;
mbed_official	87:085cde657901	1041	}
mbed_official	87:085cde657901	1042	default:
mbed_official	87:085cde657901	1043	{
mbed_official	87:085cde657901	1044	sysclockfreq = HSI_VALUE;
mbed_official	87:085cde657901	1045	break;
mbed_official	87:085cde657901	1046	}
mbed_official	87:085cde657901	1047	}
mbed_official	87:085cde657901	1048	return sysclockfreq;
mbed_official	87:085cde657901	1049	}
mbed_official	87:085cde657901	1050
mbed_official	87:085cde657901	1051	/**
mbed_official	87:085cde657901	1052	* @brief Returns the HCLK frequency
mbed_official	87:085cde657901	1053	* @note Each time HCLK changes, this function must be called to update the
mbed_official	87:085cde657901	1054	* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official	87:085cde657901	1055	*
mbed_official	87:085cde657901	1056	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
mbed_official	87:085cde657901	1057	* and updated within this function
mbed_official	87:085cde657901	1058	* @param None
mbed_official	87:085cde657901	1059	* @retval HCLK frequency
mbed_official	87:085cde657901	1060	*/
mbed_official	87:085cde657901	1061	uint32_t HAL_RCC_GetHCLKFreq(void)
mbed_official	87:085cde657901	1062	{
mbed_official	87:085cde657901	1063	SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
mbed_official	87:085cde657901	1064	return SystemCoreClock;
mbed_official	87:085cde657901	1065	}
mbed_official	87:085cde657901	1066
mbed_official	87:085cde657901	1067	/**
mbed_official	87:085cde657901	1068	* @brief Returns the PCLK1 frequency
mbed_official	87:085cde657901	1069	* @note Each time PCLK1 changes, this function must be called to update the
mbed_official	87:085cde657901	1070	* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
mbed_official	87:085cde657901	1071	* @param None
mbed_official	87:085cde657901	1072	* @retval PCLK1 frequency
mbed_official	87:085cde657901	1073	*/
mbed_official	87:085cde657901	1074	uint32_t HAL_RCC_GetPCLK1Freq(void)
mbed_official	87:085cde657901	1075	{
mbed_official	87:085cde657901	1076	/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
mbed_official	87:085cde657901	1077	return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
mbed_official	87:085cde657901	1078	}
mbed_official	87:085cde657901	1079
mbed_official	87:085cde657901	1080	/**
mbed_official	87:085cde657901	1081	* @brief Returns the PCLK2 frequency
mbed_official	87:085cde657901	1082	* @note Each time PCLK2 changes, this function must be called to update the
mbed_official	87:085cde657901	1083	* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
mbed_official	87:085cde657901	1084	* @param None
mbed_official	87:085cde657901	1085	* @retval PCLK2 frequency
mbed_official	87:085cde657901	1086	*/
mbed_official	87:085cde657901	1087	uint32_t HAL_RCC_GetPCLK2Freq(void)
mbed_official	87:085cde657901	1088	{
mbed_official	87:085cde657901	1089	/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
mbed_official	87:085cde657901	1090	return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
mbed_official	87:085cde657901	1091	}
mbed_official	87:085cde657901	1092
mbed_official	87:085cde657901	1093	/**
mbed_official	87:085cde657901	1094	* @brief Configures the RCC_OscInitStruct according to the internal
mbed_official	87:085cde657901	1095	* RCC configuration registers.
mbed_official	87:085cde657901	1096	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official	87:085cde657901	1097	* will be configured.
mbed_official	87:085cde657901	1098	* @retval None
mbed_official	87:085cde657901	1099	*/
mbed_official	87:085cde657901	1100	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official	87:085cde657901	1101	{
mbed_official	87:085cde657901	1102	/* Set all possible values for the Oscillator type parameter ---------------*/
mbed_official	87:085cde657901	1103	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI;
mbed_official	87:085cde657901	1104
mbed_official	87:085cde657901	1105	/* Get the HSE configuration -----------------------------------------------*/
mbed_official	87:085cde657901	1106	if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
mbed_official	87:085cde657901	1107	{
mbed_official	87:085cde657901	1108	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
mbed_official	87:085cde657901	1109	}
mbed_official	87:085cde657901	1110	else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
mbed_official	87:085cde657901	1111	{
mbed_official	87:085cde657901	1112	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
mbed_official	87:085cde657901	1113	}
mbed_official	87:085cde657901	1114	else
mbed_official	87:085cde657901	1115	{
mbed_official	87:085cde657901	1116	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
mbed_official	87:085cde657901	1117	}
mbed_official	87:085cde657901	1118
mbed_official	87:085cde657901	1119	/* Get the HSI configuration -----------------------------------------------*/
mbed_official	87:085cde657901	1120	if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
mbed_official	87:085cde657901	1121	{
mbed_official	87:085cde657901	1122	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
mbed_official	87:085cde657901	1123	}
mbed_official	87:085cde657901	1124	else
mbed_official	87:085cde657901	1125	{
mbed_official	87:085cde657901	1126	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
mbed_official	87:085cde657901	1127	}
mbed_official	87:085cde657901	1128
mbed_official	87:085cde657901	1129	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
mbed_official	87:085cde657901	1130
mbed_official	87:085cde657901	1131	/* Get the LSE configuration -----------------------------------------------*/
mbed_official	87:085cde657901	1132	if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
mbed_official	87:085cde657901	1133	{
mbed_official	87:085cde657901	1134	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
mbed_official	87:085cde657901	1135	}
mbed_official	87:085cde657901	1136	else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
mbed_official	87:085cde657901	1137	{
mbed_official	87:085cde657901	1138	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
mbed_official	87:085cde657901	1139	}
mbed_official	87:085cde657901	1140	else
mbed_official	87:085cde657901	1141	{
mbed_official	87:085cde657901	1142	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
mbed_official	87:085cde657901	1143	}
mbed_official	87:085cde657901	1144
mbed_official	87:085cde657901	1145	/* Get the LSI configuration -----------------------------------------------*/
mbed_official	87:085cde657901	1146	if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
mbed_official	87:085cde657901	1147	{
mbed_official	87:085cde657901	1148	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
mbed_official	87:085cde657901	1149	}
mbed_official	87:085cde657901	1150	else
mbed_official	87:085cde657901	1151	{
mbed_official	87:085cde657901	1152	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
mbed_official	87:085cde657901	1153	}
mbed_official	87:085cde657901	1154
mbed_official	87:085cde657901	1155	/* Get the PLL configuration -----------------------------------------------*/
mbed_official	87:085cde657901	1156	if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
mbed_official	87:085cde657901	1157	{
mbed_official	87:085cde657901	1158	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
mbed_official	87:085cde657901	1159	}
mbed_official	87:085cde657901	1160	else
mbed_official	87:085cde657901	1161	{
mbed_official	87:085cde657901	1162	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
mbed_official	87:085cde657901	1163	}
mbed_official	87:085cde657901	1164	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
mbed_official	87:085cde657901	1165	RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
mbed_official	87:085cde657901	1166	RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
mbed_official	87:085cde657901	1167	RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
mbed_official	87:085cde657901	1168	RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
mbed_official	87:085cde657901	1169	}
mbed_official	87:085cde657901	1170
mbed_official	87:085cde657901	1171	/**
mbed_official	87:085cde657901	1172	* @brief Configures the RCC_ClkInitStruct according to the internal
mbed_official	87:085cde657901	1173	* RCC configuration registers.
mbed_official	87:085cde657901	1174	* @param RCC_OscInitStruct: pointer to an RCC_ClkInitTypeDef structure that
mbed_official	87:085cde657901	1175	* will be configured.
mbed_official	87:085cde657901	1176	* @param pFLatency: Pointer on the Flash Latency.
mbed_official	87:085cde657901	1177	* @retval None
mbed_official	87:085cde657901	1178	*/
mbed_official	87:085cde657901	1179	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency)
mbed_official	87:085cde657901	1180	{
mbed_official	87:085cde657901	1181	/* Set all possible values for the Clock type parameter --------------------*/
mbed_official	87:085cde657901	1182	RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2;
mbed_official	87:085cde657901	1183
mbed_official	87:085cde657901	1184	/* Get the SYSCLK configuration --------------------------------------------*/
mbed_official	87:085cde657901	1185	RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
mbed_official	87:085cde657901	1186
mbed_official	87:085cde657901	1187	/* Get the HCLK configuration ----------------------------------------------*/
mbed_official	87:085cde657901	1188	RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
mbed_official	87:085cde657901	1189
mbed_official	87:085cde657901	1190	/* Get the APB1 configuration ----------------------------------------------*/
mbed_official	87:085cde657901	1191	RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
mbed_official	87:085cde657901	1192
mbed_official	87:085cde657901	1193	/* Get the APB2 configuration ----------------------------------------------*/
mbed_official	87:085cde657901	1194	RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
mbed_official	87:085cde657901	1195
mbed_official	87:085cde657901	1196	/* Get the Flash Wait State (Latency) configuration ------------------------*/
mbed_official	87:085cde657901	1197	*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
mbed_official	87:085cde657901	1198	}
mbed_official	87:085cde657901	1199
mbed_official	87:085cde657901	1200	/**
mbed_official	87:085cde657901	1201	* @brief This function handles the RCC CSS interrupt request.
mbed_official	87:085cde657901	1202	* @note This API should be called under the NMI_Handler().
mbed_official	87:085cde657901	1203	* @param None
mbed_official	87:085cde657901	1204	* @retval None
mbed_official	87:085cde657901	1205	*/
mbed_official	87:085cde657901	1206	void HAL_RCC_NMI_IRQHandler(void)
mbed_official	87:085cde657901	1207	{
mbed_official	87:085cde657901	1208	/* Check RCC CSSF flag */
mbed_official	87:085cde657901	1209	if(__HAL_RCC_GET_IT(RCC_IT_CSS))
mbed_official	87:085cde657901	1210	{
mbed_official	87:085cde657901	1211	/* RCC Clock Security System interrupt user callback */
mbed_official	87:085cde657901	1212	HAL_RCC_CCSCallback();
mbed_official	87:085cde657901	1213
mbed_official	87:085cde657901	1214	/* Clear RCC CSS pending bit */
mbed_official	87:085cde657901	1215	__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
mbed_official	87:085cde657901	1216	}
mbed_official	87:085cde657901	1217	}
mbed_official	87:085cde657901	1218
mbed_official	87:085cde657901	1219	/**
mbed_official	87:085cde657901	1220	* @brief RCC Clock Security System interrupt callback
mbed_official	87:085cde657901	1221	* @param none
mbed_official	87:085cde657901	1222	* @retval none
mbed_official	87:085cde657901	1223	*/
mbed_official	87:085cde657901	1224	__weak void HAL_RCC_CCSCallback(void)
mbed_official	87:085cde657901	1225	{
mbed_official	87:085cde657901	1226	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1227	the HAL_RCC_CCSCallback could be implemented in the user file
mbed_official	87:085cde657901	1228	*/
mbed_official	87:085cde657901	1229	}
mbed_official	87:085cde657901	1230
mbed_official	87:085cde657901	1231	/**
mbed_official	87:085cde657901	1232	* @}
mbed_official	87:085cde657901	1233	*/
mbed_official	87:085cde657901	1234
mbed_official	87:085cde657901	1235	/**
mbed_official	87:085cde657901	1236	* @}
mbed_official	87:085cde657901	1237	*/
mbed_official	87:085cde657901	1238
mbed_official	87:085cde657901	1239	#endif /* HAL_RCC_MODULE_ENABLED */
mbed_official	87:085cde657901	1240	/**
mbed_official	87:085cde657901	1241	* @}
mbed_official	87:085cde657901	1242	*/
mbed_official	87:085cde657901	1243
mbed_official	87:085cde657901	1244	/**
mbed_official	87:085cde657901	1245	* @}
mbed_official	87:085cde657901	1246	*/
mbed_official	87:085cde657901	1247
mbed_official	87:085cde657901	1248	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Mar 2014
Imports:	301
Forks:	0
Commits:	115
Dependents:	0
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Followers:	15
Issues:	1

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.c@106:ced8cbb51063, 2014-02-26 (annotated)

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