Peter Drescher
mbed library with additional peripherals for ST F401 board
Fork of
mbed-src
by 
mbed official
This mbed LIB has additional peripherals for ST F401 board
- UART2 : PA_3 rx, PA_2 tx
- UART3 : PC_7 rx, PC_6 tx
- I2C2 : PB_3 SDA, PB_10 SCL
- I2C3 : PB_4 SDA, PA_8 SCL
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h@106:ced8cbb51063, 2014-02-26 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Feb 26 09:45:12 2014 +0000
- Revision:
- 106:ced8cbb51063
- Parent:
- 87:085cde657901
Synchronized with git revision 4222735eff5868389433f0e9271976b39c8115cd
Full URL: https://github.com/mbedmicro/mbed/commit/4222735eff5868389433f0e9271976b39c8115cd/
[NUCLEO_xxx] Update STM32CubeF4 driver V1.0.0 + update license
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 87:085cde657901 | 1 | /** |
| mbed_official | 87:085cde657901 | 2 | ****************************************************************************** |
| mbed_official | 87:085cde657901 | 3 | * @file stm32f4xx_hal_dma2d.h |
| mbed_official | 87:085cde657901 | 4 | * @author MCD Application Team |
| mbed_official | 106:ced8cbb51063 | 5 | * @version V1.0.0 |
| mbed_official | 106:ced8cbb51063 | 6 | * @date 18-February-2014 |
| mbed_official | 87:085cde657901 | 7 | * @brief Header file of DMA2D HAL module. |
| mbed_official | 87:085cde657901 | 8 | ****************************************************************************** |
| mbed_official | 87:085cde657901 | 9 | * @attention |
| mbed_official | 87:085cde657901 | 10 | * |
| mbed_official | 87:085cde657901 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 87:085cde657901 | 12 | * |
| mbed_official | 87:085cde657901 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 87:085cde657901 | 14 | * are permitted provided that the following conditions are met: |
| mbed_official | 87:085cde657901 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 87:085cde657901 | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 87:085cde657901 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 87:085cde657901 | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 87:085cde657901 | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 87:085cde657901 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 87:085cde657901 | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 87:085cde657901 | 22 | * without specific prior written permission. |
| mbed_official | 87:085cde657901 | 23 | * |
| mbed_official | 87:085cde657901 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 87:085cde657901 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 87:085cde657901 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 87:085cde657901 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 87:085cde657901 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 87:085cde657901 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 87:085cde657901 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 87:085cde657901 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 87:085cde657901 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 87:085cde657901 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 87:085cde657901 | 34 | * |
| mbed_official | 87:085cde657901 | 35 | ****************************************************************************** |
| mbed_official | 87:085cde657901 | 36 | */ |
| mbed_official | 87:085cde657901 | 37 | |
| mbed_official | 87:085cde657901 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 87:085cde657901 | 39 | #ifndef __STM32F4xx_HAL_DMA2D_H |
| mbed_official | 87:085cde657901 | 40 | #define __STM32F4xx_HAL_DMA2D_H |
| mbed_official | 87:085cde657901 | 41 | |
| mbed_official | 87:085cde657901 | 42 | #ifdef __cplusplus |
| mbed_official | 87:085cde657901 | 43 | extern "C" { |
| mbed_official | 87:085cde657901 | 44 | #endif |
| mbed_official | 87:085cde657901 | 45 | |
| mbed_official | 106:ced8cbb51063 | 46 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 87:085cde657901 | 47 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 87:085cde657901 | 48 | #include "stm32f4xx_hal_def.h" |
| mbed_official | 87:085cde657901 | 49 | |
| mbed_official | 87:085cde657901 | 50 | /** @addtogroup STM32F4xx_HAL_Driver |
| mbed_official | 87:085cde657901 | 51 | * @{ |
| mbed_official | 87:085cde657901 | 52 | */ |
| mbed_official | 87:085cde657901 | 53 | |
| mbed_official | 87:085cde657901 | 54 | /** @addtogroup DMA2D |
| mbed_official | 87:085cde657901 | 55 | * @{ |
| mbed_official | 87:085cde657901 | 56 | */ |
| mbed_official | 87:085cde657901 | 57 | |
| mbed_official | 87:085cde657901 | 58 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 87:085cde657901 | 59 | |
| mbed_official | 87:085cde657901 | 60 | #define MAX_DMA2D_LAYER 2 |
| mbed_official | 87:085cde657901 | 61 | |
| mbed_official | 87:085cde657901 | 62 | /** |
| mbed_official | 87:085cde657901 | 63 | * @brief DMA2D color Structure definition |
| mbed_official | 87:085cde657901 | 64 | */ |
| mbed_official | 87:085cde657901 | 65 | typedef struct |
| mbed_official | 87:085cde657901 | 66 | { |
| mbed_official | 87:085cde657901 | 67 | uint32_t Blue; /*!< Configures the blue value. |
| mbed_official | 87:085cde657901 | 68 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
| mbed_official | 87:085cde657901 | 69 | |
| mbed_official | 87:085cde657901 | 70 | uint32_t Green; /*!< Configures the green value. |
| mbed_official | 87:085cde657901 | 71 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
| mbed_official | 87:085cde657901 | 72 | |
| mbed_official | 87:085cde657901 | 73 | uint32_t Red; /*!< Configures the red value. |
| mbed_official | 87:085cde657901 | 74 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
| mbed_official | 87:085cde657901 | 75 | } DMA2D_ColorTypeDef; |
| mbed_official | 87:085cde657901 | 76 | |
| mbed_official | 87:085cde657901 | 77 | /** |
| mbed_official | 87:085cde657901 | 78 | * @brief DMA2D CLUT Structure definition |
| mbed_official | 87:085cde657901 | 79 | */ |
| mbed_official | 87:085cde657901 | 80 | typedef struct |
| mbed_official | 87:085cde657901 | 81 | { |
| mbed_official | 87:085cde657901 | 82 | uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address. */ |
| mbed_official | 87:085cde657901 | 83 | |
| mbed_official | 87:085cde657901 | 84 | uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode. |
| mbed_official | 87:085cde657901 | 85 | This parameter can be one value of @ref DMA2D_CLUT_CM */ |
| mbed_official | 87:085cde657901 | 86 | |
| mbed_official | 87:085cde657901 | 87 | uint32_t Size; /*!< configures the DMA2D CLUT size. |
| mbed_official | 87:085cde657901 | 88 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
| mbed_official | 87:085cde657901 | 89 | } DMA2D_CLUTCfgTypeDef; |
| mbed_official | 87:085cde657901 | 90 | |
| mbed_official | 87:085cde657901 | 91 | /** |
| mbed_official | 87:085cde657901 | 92 | * @brief DMA2D Init structure definition |
| mbed_official | 87:085cde657901 | 93 | */ |
| mbed_official | 87:085cde657901 | 94 | typedef struct |
| mbed_official | 87:085cde657901 | 95 | { |
| mbed_official | 87:085cde657901 | 96 | uint32_t Mode; /*!< configures the DMA2D transfer mode. |
| mbed_official | 87:085cde657901 | 97 | This parameter can be one value of @ref DMA2D_Mode */ |
| mbed_official | 87:085cde657901 | 98 | |
| mbed_official | 87:085cde657901 | 99 | uint32_t ColorMode; /*!< configures the color format of the output image. |
| mbed_official | 87:085cde657901 | 100 | This parameter can be one value of @ref DMA2D_Color_Mode */ |
| mbed_official | 87:085cde657901 | 101 | |
| mbed_official | 87:085cde657901 | 102 | uint32_t OutputOffset; /*!< Specifies the Offset value. |
| mbed_official | 87:085cde657901 | 103 | This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ |
| mbed_official | 87:085cde657901 | 104 | |
| mbed_official | 87:085cde657901 | 105 | } DMA2D_InitTypeDef; |
| mbed_official | 87:085cde657901 | 106 | |
| mbed_official | 87:085cde657901 | 107 | /** |
| mbed_official | 87:085cde657901 | 108 | * @brief DMA2D Layer structure definition |
| mbed_official | 87:085cde657901 | 109 | */ |
| mbed_official | 87:085cde657901 | 110 | typedef struct |
| mbed_official | 87:085cde657901 | 111 | { |
| mbed_official | 87:085cde657901 | 112 | |
| mbed_official | 87:085cde657901 | 113 | |
| mbed_official | 87:085cde657901 | 114 | uint32_t InputOffset; /*!< configures the DMA2D foreground offset. |
| mbed_official | 87:085cde657901 | 115 | This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ |
| mbed_official | 87:085cde657901 | 116 | |
| mbed_official | 87:085cde657901 | 117 | uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode . |
| mbed_official | 87:085cde657901 | 118 | This parameter can be one value of @ref DMA2D_Input_Color_Mode */ |
| mbed_official | 87:085cde657901 | 119 | |
| mbed_official | 87:085cde657901 | 120 | uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode. |
| mbed_official | 87:085cde657901 | 121 | This parameter can be one value of @ref DMA2D_ALPHA_MODE */ |
| mbed_official | 87:085cde657901 | 122 | |
| mbed_official | 87:085cde657901 | 123 | uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value |
| mbed_official | 87:085cde657901 | 124 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ |
| mbed_official | 87:085cde657901 | 125 | |
| mbed_official | 87:085cde657901 | 126 | } DMA2D_LayerCfgTypeDef; |
| mbed_official | 87:085cde657901 | 127 | |
| mbed_official | 87:085cde657901 | 128 | /** |
| mbed_official | 87:085cde657901 | 129 | * @brief HAL DMA2D State structures definition |
| mbed_official | 87:085cde657901 | 130 | */ |
| mbed_official | 87:085cde657901 | 131 | typedef enum |
| mbed_official | 87:085cde657901 | 132 | { |
| mbed_official | 87:085cde657901 | 133 | HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */ |
| mbed_official | 87:085cde657901 | 134 | HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ |
| mbed_official | 87:085cde657901 | 135 | HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ |
| mbed_official | 87:085cde657901 | 136 | HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
| mbed_official | 87:085cde657901 | 137 | HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */ |
| mbed_official | 87:085cde657901 | 138 | HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */ |
| mbed_official | 87:085cde657901 | 139 | |
| mbed_official | 87:085cde657901 | 140 | }HAL_DMA2D_StateTypeDef; |
| mbed_official | 87:085cde657901 | 141 | |
| mbed_official | 87:085cde657901 | 142 | /** |
| mbed_official | 87:085cde657901 | 143 | * @brief DMA2D handle Structure definition |
| mbed_official | 87:085cde657901 | 144 | */ |
| mbed_official | 87:085cde657901 | 145 | typedef struct __DMA2D_HandleTypeDef |
| mbed_official | 87:085cde657901 | 146 | { |
| mbed_official | 87:085cde657901 | 147 | DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */ |
| mbed_official | 87:085cde657901 | 148 | |
| mbed_official | 87:085cde657901 | 149 | DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */ |
| mbed_official | 87:085cde657901 | 150 | |
| mbed_official | 87:085cde657901 | 151 | void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */ |
| mbed_official | 87:085cde657901 | 152 | |
| mbed_official | 87:085cde657901 | 153 | void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */ |
| mbed_official | 87:085cde657901 | 154 | |
| mbed_official | 87:085cde657901 | 155 | DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ |
| mbed_official | 87:085cde657901 | 156 | |
| mbed_official | 87:085cde657901 | 157 | HAL_LockTypeDef Lock; /*!< DMA2D Lock */ |
| mbed_official | 87:085cde657901 | 158 | |
| mbed_official | 87:085cde657901 | 159 | __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */ |
| mbed_official | 87:085cde657901 | 160 | |
| mbed_official | 87:085cde657901 | 161 | __IO uint32_t ErrorCode; /*!< DMA2D Error code */ |
| mbed_official | 87:085cde657901 | 162 | |
| mbed_official | 87:085cde657901 | 163 | } DMA2D_HandleTypeDef; |
| mbed_official | 87:085cde657901 | 164 | |
| mbed_official | 87:085cde657901 | 165 | |
| mbed_official | 87:085cde657901 | 166 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 87:085cde657901 | 167 | |
| mbed_official | 87:085cde657901 | 168 | /** @defgroup DMA2D_Exported_Constants |
| mbed_official | 87:085cde657901 | 169 | * @{ |
| mbed_official | 87:085cde657901 | 170 | */ |
| mbed_official | 87:085cde657901 | 171 | |
| mbed_official | 87:085cde657901 | 172 | /** @defgroup DMA2D_Layer |
| mbed_official | 87:085cde657901 | 173 | * @{ |
| mbed_official | 87:085cde657901 | 174 | */ |
| mbed_official | 87:085cde657901 | 175 | #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER) |
| mbed_official | 87:085cde657901 | 176 | /** |
| mbed_official | 87:085cde657901 | 177 | * @} |
| mbed_official | 87:085cde657901 | 178 | */ |
| mbed_official | 87:085cde657901 | 179 | |
| mbed_official | 87:085cde657901 | 180 | /** @defgroup DMA2D_Error_Code |
| mbed_official | 87:085cde657901 | 181 | * @{ |
| mbed_official | 87:085cde657901 | 182 | */ |
| mbed_official | 87:085cde657901 | 183 | #define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
| mbed_official | 87:085cde657901 | 184 | #define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ |
| mbed_official | 87:085cde657901 | 185 | #define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */ |
| mbed_official | 87:085cde657901 | 186 | #define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ |
| mbed_official | 87:085cde657901 | 187 | /** |
| mbed_official | 87:085cde657901 | 188 | * @} |
| mbed_official | 87:085cde657901 | 189 | */ |
| mbed_official | 87:085cde657901 | 190 | |
| mbed_official | 87:085cde657901 | 191 | /** @defgroup DMA2D_Mode |
| mbed_official | 87:085cde657901 | 192 | * @{ |
| mbed_official | 87:085cde657901 | 193 | */ |
| mbed_official | 87:085cde657901 | 194 | #define DMA2D_M2M ((uint32_t)0x00000000) /*!< DMA2D memory to memory transfer mode */ |
| mbed_official | 87:085cde657901 | 195 | #define DMA2D_M2M_PFC ((uint32_t)0x00010000) /*!< DMA2D memory to memory with pixel format conversion transfer mode */ |
| mbed_official | 87:085cde657901 | 196 | #define DMA2D_M2M_BLEND ((uint32_t)0x00020000) /*!< DMA2D memory to memory with blending transfer mode */ |
| mbed_official | 87:085cde657901 | 197 | #define DMA2D_R2M ((uint32_t)0x00030000) /*!< DMA2D register to memory transfer mode */ |
| mbed_official | 87:085cde657901 | 198 | |
| mbed_official | 87:085cde657901 | 199 | #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ |
| mbed_official | 87:085cde657901 | 200 | ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) |
| mbed_official | 87:085cde657901 | 201 | /** |
| mbed_official | 87:085cde657901 | 202 | * @} |
| mbed_official | 87:085cde657901 | 203 | */ |
| mbed_official | 87:085cde657901 | 204 | |
| mbed_official | 87:085cde657901 | 205 | /** @defgroup DMA2D_Color_Mode |
| mbed_official | 87:085cde657901 | 206 | * @{ |
| mbed_official | 87:085cde657901 | 207 | */ |
| mbed_official | 87:085cde657901 | 208 | #define DMA2D_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D color mode */ |
| mbed_official | 87:085cde657901 | 209 | #define DMA2D_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D color mode */ |
| mbed_official | 87:085cde657901 | 210 | #define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */ |
| mbed_official | 87:085cde657901 | 211 | #define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */ |
| mbed_official | 87:085cde657901 | 212 | #define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */ |
| mbed_official | 87:085cde657901 | 213 | |
| mbed_official | 87:085cde657901 | 214 | #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \ |
| mbed_official | 87:085cde657901 | 215 | ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \ |
| mbed_official | 87:085cde657901 | 216 | ((MODE_ARGB) == DMA2D_ARGB4444)) |
| mbed_official | 87:085cde657901 | 217 | /** |
| mbed_official | 87:085cde657901 | 218 | * @} |
| mbed_official | 87:085cde657901 | 219 | */ |
| mbed_official | 87:085cde657901 | 220 | |
| mbed_official | 87:085cde657901 | 221 | /** @defgroup DMA2D_COLOR_VALUE |
| mbed_official | 87:085cde657901 | 222 | * @{ |
| mbed_official | 87:085cde657901 | 223 | */ |
| mbed_official | 87:085cde657901 | 224 | |
| mbed_official | 87:085cde657901 | 225 | #define COLOR_VALUE ((uint32_t)0x000000FF) /*!< color value mask */ |
| mbed_official | 87:085cde657901 | 226 | |
| mbed_official | 87:085cde657901 | 227 | #define IS_DMA2D_ALPHA_VALUE(ALPHA_VALUE) ((ALPHA_VALUE) <= COLOR_VALUE) |
| mbed_official | 87:085cde657901 | 228 | #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE) |
| mbed_official | 87:085cde657901 | 229 | /** |
| mbed_official | 87:085cde657901 | 230 | * @} |
| mbed_official | 87:085cde657901 | 231 | */ |
| mbed_official | 87:085cde657901 | 232 | |
| mbed_official | 87:085cde657901 | 233 | /** @defgroup DMA2D_SIZE |
| mbed_official | 87:085cde657901 | 234 | * @{ |
| mbed_official | 87:085cde657901 | 235 | */ |
| mbed_official | 87:085cde657901 | 236 | #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16) /*!< DMA2D pixel per line */ |
| mbed_official | 87:085cde657901 | 237 | #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of line */ |
| mbed_official | 87:085cde657901 | 238 | |
| mbed_official | 87:085cde657901 | 239 | #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) |
| mbed_official | 87:085cde657901 | 240 | #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) |
| mbed_official | 87:085cde657901 | 241 | /** |
| mbed_official | 87:085cde657901 | 242 | * @} |
| mbed_official | 87:085cde657901 | 243 | */ |
| mbed_official | 87:085cde657901 | 244 | |
| mbed_official | 87:085cde657901 | 245 | /** @defgroup DMA2D_OFFSET |
| mbed_official | 87:085cde657901 | 246 | * @{ |
| mbed_official | 87:085cde657901 | 247 | */ |
| mbed_official | 87:085cde657901 | 248 | #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */ |
| mbed_official | 87:085cde657901 | 249 | |
| mbed_official | 87:085cde657901 | 250 | #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) |
| mbed_official | 87:085cde657901 | 251 | /** |
| mbed_official | 87:085cde657901 | 252 | * @} |
| mbed_official | 87:085cde657901 | 253 | */ |
| mbed_official | 87:085cde657901 | 254 | |
| mbed_official | 87:085cde657901 | 255 | /** @defgroup DMA2D_Input_Color_Mode |
| mbed_official | 87:085cde657901 | 256 | * @{ |
| mbed_official | 87:085cde657901 | 257 | */ |
| mbed_official | 87:085cde657901 | 258 | #define CM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 color mode */ |
| mbed_official | 87:085cde657901 | 259 | #define CM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 color mode */ |
| mbed_official | 87:085cde657901 | 260 | #define CM_RGB565 ((uint32_t)0x00000002) /*!< RGB565 color mode */ |
| mbed_official | 87:085cde657901 | 261 | #define CM_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 color mode */ |
| mbed_official | 87:085cde657901 | 262 | #define CM_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 color mode */ |
| mbed_official | 87:085cde657901 | 263 | #define CM_L8 ((uint32_t)0x00000005) /*!< L8 color mode */ |
| mbed_official | 87:085cde657901 | 264 | #define CM_AL44 ((uint32_t)0x00000006) /*!< AL44 color mode */ |
| mbed_official | 87:085cde657901 | 265 | #define CM_AL88 ((uint32_t)0x00000007) /*!< AL88 color mode */ |
| mbed_official | 87:085cde657901 | 266 | #define CM_L4 ((uint32_t)0x00000008) /*!< L4 color mode */ |
| mbed_official | 87:085cde657901 | 267 | #define CM_A8 ((uint32_t)0x00000009) /*!< A8 color mode */ |
| mbed_official | 87:085cde657901 | 268 | #define CM_A4 ((uint32_t)0x0000000A) /*!< A4 color mode */ |
| mbed_official | 87:085cde657901 | 269 | |
| mbed_official | 87:085cde657901 | 270 | #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888) || \ |
| mbed_official | 87:085cde657901 | 271 | ((INPUT_CM) == CM_RGB565) || ((INPUT_CM) == CM_ARGB1555) || \ |
| mbed_official | 87:085cde657901 | 272 | ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8) || \ |
| mbed_official | 87:085cde657901 | 273 | ((INPUT_CM) == CM_AL44) || ((INPUT_CM) == CM_AL88) || \ |
| mbed_official | 87:085cde657901 | 274 | ((INPUT_CM) == CM_L4) || ((INPUT_CM) == CM_A8) || \ |
| mbed_official | 87:085cde657901 | 275 | ((INPUT_CM) == CM_A4)) |
| mbed_official | 87:085cde657901 | 276 | /** |
| mbed_official | 87:085cde657901 | 277 | * @} |
| mbed_official | 87:085cde657901 | 278 | */ |
| mbed_official | 87:085cde657901 | 279 | |
| mbed_official | 87:085cde657901 | 280 | /** @defgroup DMA2D_ALPHA_MODE |
| mbed_official | 87:085cde657901 | 281 | * @{ |
| mbed_official | 87:085cde657901 | 282 | */ |
| mbed_official | 87:085cde657901 | 283 | #define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000) /*!< No modification of the alpha channel value */ |
| mbed_official | 87:085cde657901 | 284 | #define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001) /*!< Replace original alpha channel value by programmed alpha value */ |
| mbed_official | 87:085cde657901 | 285 | #define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002) /*!< Replace original alpha channel value by programmed alpha value |
| mbed_official | 87:085cde657901 | 286 | with original alpha channel value */ |
| mbed_official | 87:085cde657901 | 287 | |
| mbed_official | 87:085cde657901 | 288 | #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ |
| mbed_official | 87:085cde657901 | 289 | ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ |
| mbed_official | 87:085cde657901 | 290 | ((AlphaMode) == DMA2D_COMBINE_ALPHA)) |
| mbed_official | 87:085cde657901 | 291 | /** |
| mbed_official | 87:085cde657901 | 292 | * @} |
| mbed_official | 87:085cde657901 | 293 | */ |
| mbed_official | 87:085cde657901 | 294 | |
| mbed_official | 87:085cde657901 | 295 | /** @defgroup DMA2D_CLUT_CM |
| mbed_official | 87:085cde657901 | 296 | * @{ |
| mbed_official | 87:085cde657901 | 297 | */ |
| mbed_official | 87:085cde657901 | 298 | #define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D C-LUT color mode */ |
| mbed_official | 87:085cde657901 | 299 | #define DMA2D_CCM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D C-LUT color mode */ |
| mbed_official | 87:085cde657901 | 300 | |
| mbed_official | 87:085cde657901 | 301 | #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) |
| mbed_official | 87:085cde657901 | 302 | /** |
| mbed_official | 87:085cde657901 | 303 | * @} |
| mbed_official | 87:085cde657901 | 304 | */ |
| mbed_official | 87:085cde657901 | 305 | |
| mbed_official | 87:085cde657901 | 306 | /** @defgroup DMA2D_CLUT_SIZE |
| mbed_official | 87:085cde657901 | 307 | * @{ |
| mbed_official | 87:085cde657901 | 308 | */ |
| mbed_official | 87:085cde657901 | 309 | #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */ |
| mbed_official | 87:085cde657901 | 310 | |
| mbed_official | 87:085cde657901 | 311 | #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) |
| mbed_official | 87:085cde657901 | 312 | /** |
| mbed_official | 87:085cde657901 | 313 | * @} |
| mbed_official | 87:085cde657901 | 314 | */ |
| mbed_official | 87:085cde657901 | 315 | |
| mbed_official | 87:085cde657901 | 316 | /** @defgroup DMA2D_DeadTime |
| mbed_official | 87:085cde657901 | 317 | * @{ |
| mbed_official | 87:085cde657901 | 318 | */ |
| mbed_official | 87:085cde657901 | 319 | #define LINE_WATERMARK DMA2D_LWR_LW |
| mbed_official | 87:085cde657901 | 320 | |
| mbed_official | 87:085cde657901 | 321 | #define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK) |
| mbed_official | 87:085cde657901 | 322 | /** |
| mbed_official | 87:085cde657901 | 323 | * @} |
| mbed_official | 87:085cde657901 | 324 | */ |
| mbed_official | 87:085cde657901 | 325 | |
| mbed_official | 87:085cde657901 | 326 | /** @defgroup DMA2D_Interrupts |
| mbed_official | 87:085cde657901 | 327 | * @{ |
| mbed_official | 87:085cde657901 | 328 | */ |
| mbed_official | 87:085cde657901 | 329 | #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ |
| mbed_official | 87:085cde657901 | 330 | #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< C-LUT Transfer Complete Interrupt */ |
| mbed_official | 87:085cde657901 | 331 | #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< C-LUT Access Error Interrupt */ |
| mbed_official | 87:085cde657901 | 332 | #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ |
| mbed_official | 87:085cde657901 | 333 | #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ |
| mbed_official | 87:085cde657901 | 334 | #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ |
| mbed_official | 87:085cde657901 | 335 | |
| mbed_official | 87:085cde657901 | 336 | #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ |
| mbed_official | 87:085cde657901 | 337 | ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ |
| mbed_official | 87:085cde657901 | 338 | ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) |
| mbed_official | 87:085cde657901 | 339 | /** |
| mbed_official | 87:085cde657901 | 340 | * @} |
| mbed_official | 87:085cde657901 | 341 | */ |
| mbed_official | 87:085cde657901 | 342 | |
| mbed_official | 87:085cde657901 | 343 | /** @defgroup DMA2D_Flag |
| mbed_official | 87:085cde657901 | 344 | * @{ |
| mbed_official | 87:085cde657901 | 345 | */ |
| mbed_official | 87:085cde657901 | 346 | #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ |
| mbed_official | 87:085cde657901 | 347 | #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< C-LUT Transfer Complete Interrupt Flag */ |
| mbed_official | 87:085cde657901 | 348 | #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< C-LUT Access Error Interrupt Flag */ |
| mbed_official | 87:085cde657901 | 349 | #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ |
| mbed_official | 87:085cde657901 | 350 | #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ |
| mbed_official | 87:085cde657901 | 351 | #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ |
| mbed_official | 87:085cde657901 | 352 | |
| mbed_official | 87:085cde657901 | 353 | #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ |
| mbed_official | 87:085cde657901 | 354 | ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ |
| mbed_official | 87:085cde657901 | 355 | ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) |
| mbed_official | 87:085cde657901 | 356 | /** |
| mbed_official | 87:085cde657901 | 357 | * @} |
| mbed_official | 87:085cde657901 | 358 | */ |
| mbed_official | 87:085cde657901 | 359 | |
| mbed_official | 87:085cde657901 | 360 | /** |
| mbed_official | 87:085cde657901 | 361 | * @} |
| mbed_official | 87:085cde657901 | 362 | */ |
| mbed_official | 87:085cde657901 | 363 | /* Exported macro ------------------------------------------------------------*/ |
| mbed_official | 87:085cde657901 | 364 | /** |
| mbed_official | 87:085cde657901 | 365 | * @brief Enable the DMA2D. |
| mbed_official | 87:085cde657901 | 366 | * @param __HANDLE__: DMA2D handle |
| mbed_official | 87:085cde657901 | 367 | * @retval None. |
| mbed_official | 87:085cde657901 | 368 | */ |
| mbed_official | 87:085cde657901 | 369 | #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) |
| mbed_official | 87:085cde657901 | 370 | |
| mbed_official | 87:085cde657901 | 371 | /** |
| mbed_official | 87:085cde657901 | 372 | * @brief Disable the DMA2D. |
| mbed_official | 87:085cde657901 | 373 | * @param __HANDLE__: DMA2D handle |
| mbed_official | 87:085cde657901 | 374 | * @retval None. |
| mbed_official | 87:085cde657901 | 375 | */ |
| mbed_official | 87:085cde657901 | 376 | #define __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START) |
| mbed_official | 87:085cde657901 | 377 | |
| mbed_official | 87:085cde657901 | 378 | /* Interrupt & Flag management */ |
| mbed_official | 87:085cde657901 | 379 | /** |
| mbed_official | 87:085cde657901 | 380 | * @brief Get the DMA2D pending flags. |
| mbed_official | 87:085cde657901 | 381 | * @param __HANDLE__: DMA2D handle |
| mbed_official | 87:085cde657901 | 382 | * @param __FLAG__: Get the specified flag. |
| mbed_official | 87:085cde657901 | 383 | * This parameter can be any combination of the following values: |
| mbed_official | 87:085cde657901 | 384 | * @arg DMA2D_FLAG_CE: Configuration error flag |
| mbed_official | 87:085cde657901 | 385 | * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag |
| mbed_official | 87:085cde657901 | 386 | * @arg DMA2D_FLAG_CAE: C-LUT access error flag |
| mbed_official | 87:085cde657901 | 387 | * @arg DMA2D_FLAG_TW: Transfer Watermark flag |
| mbed_official | 87:085cde657901 | 388 | * @arg DMA2D_FLAG_TC: Transfer complete flag |
| mbed_official | 87:085cde657901 | 389 | * @arg DMA2D_FLAG_TE: Transfer error flag |
| mbed_official | 87:085cde657901 | 390 | * @retval The state of FLAG. |
| mbed_official | 87:085cde657901 | 391 | */ |
| mbed_official | 87:085cde657901 | 392 | #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) |
| mbed_official | 87:085cde657901 | 393 | |
| mbed_official | 87:085cde657901 | 394 | /** |
| mbed_official | 87:085cde657901 | 395 | * @brief Clears the DMA2D pending flags. |
| mbed_official | 87:085cde657901 | 396 | * @param __HANDLE__: DMA2D handle |
| mbed_official | 87:085cde657901 | 397 | * @param __FLAG__: specifies the flag to clear. |
| mbed_official | 87:085cde657901 | 398 | * This parameter can be any combination of the following values: |
| mbed_official | 87:085cde657901 | 399 | * @arg DMA2D_FLAG_CE: Configuration error flag |
| mbed_official | 87:085cde657901 | 400 | * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag |
| mbed_official | 87:085cde657901 | 401 | * @arg DMA2D_FLAG_CAE: C-LUT access error flag |
| mbed_official | 87:085cde657901 | 402 | * @arg DMA2D_FLAG_TW: Transfer Watermark flag |
| mbed_official | 87:085cde657901 | 403 | * @arg DMA2D_FLAG_TC: Transfer complete flag |
| mbed_official | 87:085cde657901 | 404 | * @arg DMA2D_FLAG_TE: Transfer error flag |
| mbed_official | 87:085cde657901 | 405 | * @retval None |
| mbed_official | 87:085cde657901 | 406 | */ |
| mbed_official | 87:085cde657901 | 407 | #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR |= (__FLAG__)) |
| mbed_official | 87:085cde657901 | 408 | |
| mbed_official | 87:085cde657901 | 409 | /** |
| mbed_official | 87:085cde657901 | 410 | * @brief Enables the specified DMA2D interrupts. |
| mbed_official | 87:085cde657901 | 411 | * @param __HANDLE__: DMA2D handle |
| mbed_official | 87:085cde657901 | 412 | * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. |
| mbed_official | 87:085cde657901 | 413 | * This parameter can be any combination of the following values: |
| mbed_official | 87:085cde657901 | 414 | * @arg DMA2D_IT_CE: Configuration error interrupt mask |
| mbed_official | 87:085cde657901 | 415 | * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask |
| mbed_official | 87:085cde657901 | 416 | * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask |
| mbed_official | 87:085cde657901 | 417 | * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
| mbed_official | 87:085cde657901 | 418 | * @arg DMA2D_IT_TC: Transfer complete interrupt mask |
| mbed_official | 87:085cde657901 | 419 | * @arg DMA2D_IT_TE: Transfer error interrupt mask |
| mbed_official | 87:085cde657901 | 420 | * @retval None |
| mbed_official | 87:085cde657901 | 421 | */ |
| mbed_official | 87:085cde657901 | 422 | #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) |
| mbed_official | 87:085cde657901 | 423 | |
| mbed_official | 87:085cde657901 | 424 | /** |
| mbed_official | 87:085cde657901 | 425 | * @brief Disables the specified DMA2D interrupts. |
| mbed_official | 87:085cde657901 | 426 | * @param __HANDLE__: DMA2D handle |
| mbed_official | 87:085cde657901 | 427 | * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. |
| mbed_official | 87:085cde657901 | 428 | * This parameter can be any combination of the following values: |
| mbed_official | 87:085cde657901 | 429 | * @arg DMA2D_IT_CE: Configuration error interrupt mask |
| mbed_official | 87:085cde657901 | 430 | * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask |
| mbed_official | 87:085cde657901 | 431 | * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask |
| mbed_official | 87:085cde657901 | 432 | * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
| mbed_official | 87:085cde657901 | 433 | * @arg DMA2D_IT_TC: Transfer complete interrupt mask |
| mbed_official | 87:085cde657901 | 434 | * @arg DMA2D_IT_TE: Transfer error interrupt mask |
| mbed_official | 87:085cde657901 | 435 | * @retval None |
| mbed_official | 87:085cde657901 | 436 | */ |
| mbed_official | 87:085cde657901 | 437 | #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) |
| mbed_official | 87:085cde657901 | 438 | |
| mbed_official | 87:085cde657901 | 439 | /** |
| mbed_official | 87:085cde657901 | 440 | * @brief Checks whether the specified DMA2D interrupt has occurred or not. |
| mbed_official | 87:085cde657901 | 441 | * @param __HANDLE__: DMA2D handle |
| mbed_official | 87:085cde657901 | 442 | * @param __INTERRUPT__: specifies the DMA2D interrupt source to check. |
| mbed_official | 87:085cde657901 | 443 | * This parameter can be one of the following values: |
| mbed_official | 87:085cde657901 | 444 | * @arg DMA2D_IT_CE: Configuration error interrupt mask |
| mbed_official | 87:085cde657901 | 445 | * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask |
| mbed_official | 87:085cde657901 | 446 | * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask |
| mbed_official | 87:085cde657901 | 447 | * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask |
| mbed_official | 87:085cde657901 | 448 | * @arg DMA2D_IT_TC: Transfer complete interrupt mask |
| mbed_official | 87:085cde657901 | 449 | * @arg DMA2D_IT_TE: Transfer error interrupt mask |
| mbed_official | 87:085cde657901 | 450 | * @retval The state of INTERRUPT. |
| mbed_official | 87:085cde657901 | 451 | */ |
| mbed_official | 106:ced8cbb51063 | 452 | #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) |
| mbed_official | 87:085cde657901 | 453 | |
| mbed_official | 87:085cde657901 | 454 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 87:085cde657901 | 455 | |
| mbed_official | 87:085cde657901 | 456 | /* Initialization and de-initialization functions *******************************/ |
| mbed_official | 87:085cde657901 | 457 | HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); |
| mbed_official | 87:085cde657901 | 458 | HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); |
| mbed_official | 106:ced8cbb51063 | 459 | void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); |
| mbed_official | 106:ced8cbb51063 | 460 | void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); |
| mbed_official | 87:085cde657901 | 461 | |
| mbed_official | 87:085cde657901 | 462 | /* IO operation functions *******************************************************/ |
| mbed_official | 87:085cde657901 | 463 | HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh); |
| mbed_official | 87:085cde657901 | 464 | HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh); |
| mbed_official | 87:085cde657901 | 465 | HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh); |
| mbed_official | 87:085cde657901 | 466 | HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh); |
| mbed_official | 87:085cde657901 | 467 | HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); |
| mbed_official | 87:085cde657901 | 468 | HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); |
| mbed_official | 87:085cde657901 | 469 | HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); |
| mbed_official | 87:085cde657901 | 470 | HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); |
| mbed_official | 87:085cde657901 | 471 | void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); |
| mbed_official | 87:085cde657901 | 472 | |
| mbed_official | 87:085cde657901 | 473 | /* Peripheral Control functions *************************************************/ |
| mbed_official | 87:085cde657901 | 474 | HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
| mbed_official | 87:085cde657901 | 475 | HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); |
| mbed_official | 87:085cde657901 | 476 | HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
| mbed_official | 87:085cde657901 | 477 | HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); |
| mbed_official | 87:085cde657901 | 478 | HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); |
| mbed_official | 87:085cde657901 | 479 | |
| mbed_official | 87:085cde657901 | 480 | /* Peripheral State functions ***************************************************/ |
| mbed_official | 87:085cde657901 | 481 | HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); |
| mbed_official | 87:085cde657901 | 482 | uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); |
| mbed_official | 87:085cde657901 | 483 | |
| mbed_official | 106:ced8cbb51063 | 484 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 87:085cde657901 | 485 | |
| mbed_official | 87:085cde657901 | 486 | /** |
| mbed_official | 87:085cde657901 | 487 | * @} |
| mbed_official | 87:085cde657901 | 488 | */ |
| mbed_official | 87:085cde657901 | 489 | |
| mbed_official | 87:085cde657901 | 490 | /** |
| mbed_official | 87:085cde657901 | 491 | * @} |
| mbed_official | 87:085cde657901 | 492 | */ |
| mbed_official | 87:085cde657901 | 493 | |
| mbed_official | 87:085cde657901 | 494 | #ifdef __cplusplus |
| mbed_official | 87:085cde657901 | 495 | } |
| mbed_official | 87:085cde657901 | 496 | #endif |
| mbed_official | 87:085cde657901 | 497 | |
| mbed_official | 87:085cde657901 | 498 | #endif /* __STM32F4xx_HAL_DMA2D_H */ |
| mbed_official | 87:085cde657901 | 499 | |
| mbed_official | 87:085cde657901 | 500 | |
| mbed_official | 87:085cde657901 | 501 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |