Peter Drescher / mbed-F401

mbed library with additional peripherals for ST F401 board

Fork of mbed-src by mbed official

This mbed LIB has additional peripherals for ST F401 board

  • UART2 : PA_3 rx, PA_2 tx
  • UART3 : PC_7 rx, PC_6 tx
  • I2C2 : PB_3 SDA, PB_10 SCL
  • I2C3 : PB_4 SDA, PA_8 SCL

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F030R8/stm32f0xx_dma.c@106:ced8cbb51063, 2014-02-26 (annotated)

Committer:
mbed_official
Date:
Wed Feb 26 09:45:12 2014 +0000
Revision:
106:ced8cbb51063
Parent:
76:aeb1df146756 
Synchronized with git revision 4222735eff5868389433f0e9271976b39c8115cd



Full URL: https://github.com/mbedmicro/mbed/commit/4222735eff5868389433f0e9271976b39c8115cd/



[NUCLEO_xxx] Update STM32CubeF4 driver V1.0.0 + update license

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 76:aeb1df146756 1 /**
mbed_official 76:aeb1df146756 2 ******************************************************************************
mbed_official 76:aeb1df146756 3 * @file stm32f0xx_dma.c
mbed_official 76:aeb1df146756 4 * @author MCD Application Team
mbed_official 76:aeb1df146756 5 * @version V1.3.0
mbed_official 76:aeb1df146756 6 * @date 16-January-2014
mbed_official 76:aeb1df146756 7 * @brief This file provides firmware functions to manage the following
mbed_official 76:aeb1df146756 8 * functionalities of the Direct Memory Access controller (DMA):
mbed_official 76:aeb1df146756 9 * + Initialization and Configuration
mbed_official 76:aeb1df146756 10 * + Data Counter
mbed_official 76:aeb1df146756 11 * + Interrupts and flags management
mbed_official 76:aeb1df146756 12 *
mbed_official 76:aeb1df146756 13 * @verbatim
mbed_official 76:aeb1df146756 14 ==============================================================================
mbed_official 76:aeb1df146756 15 ##### How to use this driver #####
mbed_official 76:aeb1df146756 16 ==============================================================================
mbed_official 76:aeb1df146756 17 [..]
mbed_official 76:aeb1df146756 18 (#) Enable The DMA controller clock using
mbed_official 76:aeb1df146756 19 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1.
mbed_official 76:aeb1df146756 20 (#) Enable and configure the peripheral to be connected to the DMA channel
mbed_official 76:aeb1df146756 21 (except for internal SRAM / FLASH memories: no initialization is necessary).
mbed_official 76:aeb1df146756 22 (#) For a given Channel, program the Source and Destination addresses,
mbed_official 76:aeb1df146756 23 the transfer Direction, the Buffer Size, the Peripheral and Memory
mbed_official 76:aeb1df146756 24 Incrementation mode and Data Size, the Circular or Normal mode,
mbed_official 76:aeb1df146756 25 the channel transfer Priority and the Memory-to-Memory transfer
mbed_official 76:aeb1df146756 26 mode (if needed) using the DMA_Init() function.
mbed_official 76:aeb1df146756 27 (#) Enable the NVIC and the corresponding interrupt(s) using the function
mbed_official 76:aeb1df146756 28 DMA_ITConfig() if you need to use DMA interrupts.
mbed_official 76:aeb1df146756 29 (#) Enable the DMA channel using the DMA_Cmd() function.
mbed_official 76:aeb1df146756 30 (#) Activate the needed channel Request using PPP_DMACmd() function for
mbed_official 76:aeb1df146756 31 any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
mbed_official 76:aeb1df146756 32 The function allowing this operation is provided in each PPP peripheral
mbed_official 76:aeb1df146756 33 driver (ie. SPI_DMACmd for SPI peripheral).
mbed_official 76:aeb1df146756 34 (#) Optionally, you can configure the number of data to be transferred
mbed_official 76:aeb1df146756 35 when the channel is disabled (ie. after each Transfer Complete event
mbed_official 76:aeb1df146756 36 or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
mbed_official 76:aeb1df146756 37 And you can get the number of remaining data to be transferred using
mbed_official 76:aeb1df146756 38 the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
mbed_official 76:aeb1df146756 39 enabled and running).
mbed_official 76:aeb1df146756 40 (#) To control DMA events you can use one of the following two methods:
mbed_official 76:aeb1df146756 41 (##) Check on DMA channel flags using the function DMA_GetFlagStatus().
mbed_official 76:aeb1df146756 42 (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
mbed_official 76:aeb1df146756 43 phase and DMA_GetITStatus() function into interrupt routines in
mbed_official 76:aeb1df146756 44 communication phase.
mbed_official 76:aeb1df146756 45 After checking on a flag you should clear it using DMA_ClearFlag()
mbed_official 76:aeb1df146756 46 function. And after checking on an interrupt event you should
mbed_official 76:aeb1df146756 47 clear it using DMA_ClearITPendingBit() function.
mbed_official 76:aeb1df146756 48 @endverbatim
mbed_official 76:aeb1df146756 49 *
mbed_official 76:aeb1df146756 50 ******************************************************************************
mbed_official 76:aeb1df146756 51 * @attention
mbed_official 76:aeb1df146756 52 *
mbed_official 106:ced8cbb51063 53 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 76:aeb1df146756 54 *
mbed_official 106:ced8cbb51063 55 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 106:ced8cbb51063 56 * are permitted provided that the following conditions are met:
mbed_official 106:ced8cbb51063 57 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 106:ced8cbb51063 58 * this list of conditions and the following disclaimer.
mbed_official 106:ced8cbb51063 59 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 106:ced8cbb51063 60 * this list of conditions and the following disclaimer in the documentation
mbed_official 106:ced8cbb51063 61 * and/or other materials provided with the distribution.
mbed_official 106:ced8cbb51063 62 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 106:ced8cbb51063 63 * may be used to endorse or promote products derived from this software
mbed_official 106:ced8cbb51063 64 * without specific prior written permission.
mbed_official 76:aeb1df146756 65 *
mbed_official 106:ced8cbb51063 66 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 106:ced8cbb51063 67 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 106:ced8cbb51063 68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 106:ced8cbb51063 69 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 106:ced8cbb51063 70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 106:ced8cbb51063 71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 106:ced8cbb51063 72 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 106:ced8cbb51063 73 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 106:ced8cbb51063 74 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 106:ced8cbb51063 75 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 76:aeb1df146756 76 *
mbed_official 76:aeb1df146756 77 ******************************************************************************
mbed_official 76:aeb1df146756 78 */
mbed_official 76:aeb1df146756 79
mbed_official 76:aeb1df146756 80 /* Includes ------------------------------------------------------------------*/
mbed_official 76:aeb1df146756 81 #include "stm32f0xx_dma.h"
mbed_official 76:aeb1df146756 82
mbed_official 76:aeb1df146756 83 /** @addtogroup STM32F0xx_StdPeriph_Driver
mbed_official 76:aeb1df146756 84 * @{
mbed_official 76:aeb1df146756 85 */
mbed_official 76:aeb1df146756 86
mbed_official 76:aeb1df146756 87 /** @defgroup DMA
mbed_official 76:aeb1df146756 88 * @brief DMA driver modules
mbed_official 76:aeb1df146756 89 * @{
mbed_official 76:aeb1df146756 90 */
mbed_official 76:aeb1df146756 91
mbed_official 76:aeb1df146756 92 /* Private typedef -----------------------------------------------------------*/
mbed_official 76:aeb1df146756 93 /* Private define ------------------------------------------------------------*/
mbed_official 76:aeb1df146756 94 #define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
mbed_official 76:aeb1df146756 95
mbed_official 76:aeb1df146756 96 /* DMA1 Channelx interrupt pending bit masks */
mbed_official 76:aeb1df146756 97 #define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
mbed_official 76:aeb1df146756 98 #define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
mbed_official 76:aeb1df146756 99 #define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
mbed_official 76:aeb1df146756 100 #define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
mbed_official 76:aeb1df146756 101 #define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
mbed_official 76:aeb1df146756 102 #define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) /*!< Only applicable for STM32F072 devices */
mbed_official 76:aeb1df146756 103 #define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) /*!< Only applicable for STM32F072 devices */
mbed_official 76:aeb1df146756 104
mbed_official 76:aeb1df146756 105 /* Private macro -------------------------------------------------------------*/
mbed_official 76:aeb1df146756 106 /* Private variables ---------------------------------------------------------*/
mbed_official 76:aeb1df146756 107 /* Private function prototypes -----------------------------------------------*/
mbed_official 76:aeb1df146756 108 /* Private functions ---------------------------------------------------------*/
mbed_official 76:aeb1df146756 109
mbed_official 76:aeb1df146756 110 /** @defgroup DMA_Private_Functions
mbed_official 76:aeb1df146756 111 * @{
mbed_official 76:aeb1df146756 112 */
mbed_official 76:aeb1df146756 113
mbed_official 76:aeb1df146756 114 /** @defgroup DMA_Group1 Initialization and Configuration functions
mbed_official 76:aeb1df146756 115 * @brief Initialization and Configuration functions
mbed_official 76:aeb1df146756 116 *
mbed_official 76:aeb1df146756 117 @verbatim
mbed_official 76:aeb1df146756 118 ===============================================================================
mbed_official 76:aeb1df146756 119 ##### Initialization and Configuration functions #####
mbed_official 76:aeb1df146756 120 ===============================================================================
mbed_official 76:aeb1df146756 121 [..] This subsection provides functions allowing to initialize the DMA channel
mbed_official 76:aeb1df146756 122 source and destination addresses, incrementation and data sizes, transfer
mbed_official 76:aeb1df146756 123 direction, buffer size, circular/normal mode selection, memory-to-memory
mbed_official 76:aeb1df146756 124 mode selection and channel priority value.
mbed_official 76:aeb1df146756 125 [..] The DMA_Init() function follows the DMA configuration procedures as described
mbed_official 76:aeb1df146756 126 in reference manual (RM0091).
mbed_official 76:aeb1df146756 127 @endverbatim
mbed_official 76:aeb1df146756 128 * @{
mbed_official 76:aeb1df146756 129 */
mbed_official 76:aeb1df146756 130
mbed_official 76:aeb1df146756 131 /**
mbed_official 76:aeb1df146756 132 * @brief Deinitializes the DMAy Channelx registers to their default reset
mbed_official 76:aeb1df146756 133 * values.
mbed_official 76:aeb1df146756 134 * @param DMAy_Channelx: where y can be 1 to select the DMA and
mbed_official 76:aeb1df146756 135 * x can be 1 to 7 for DMA1 to select the DMA Channel.
mbed_official 76:aeb1df146756 136 * @note Channel 6 and 7 are available only for STM32F072 devices.
mbed_official 76:aeb1df146756 137 * @retval None
mbed_official 76:aeb1df146756 138 */
mbed_official 76:aeb1df146756 139 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
mbed_official 76:aeb1df146756 140 {
mbed_official 76:aeb1df146756 141 /* Check the parameters */
mbed_official 76:aeb1df146756 142 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
mbed_official 76:aeb1df146756 143
mbed_official 76:aeb1df146756 144 /* Disable the selected DMAy Channelx */
mbed_official 76:aeb1df146756 145 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
mbed_official 76:aeb1df146756 146
mbed_official 76:aeb1df146756 147 /* Reset DMAy Channelx control register */
mbed_official 76:aeb1df146756 148 DMAy_Channelx->CCR = 0;
mbed_official 76:aeb1df146756 149
mbed_official 76:aeb1df146756 150 /* Reset DMAy Channelx remaining bytes register */
mbed_official 76:aeb1df146756 151 DMAy_Channelx->CNDTR = 0;
mbed_official 76:aeb1df146756 152
mbed_official 76:aeb1df146756 153 /* Reset DMAy Channelx peripheral address register */
mbed_official 76:aeb1df146756 154 DMAy_Channelx->CPAR = 0;
mbed_official 76:aeb1df146756 155
mbed_official 76:aeb1df146756 156 /* Reset DMAy Channelx memory address register */
mbed_official 76:aeb1df146756 157 DMAy_Channelx->CMAR = 0;
mbed_official 76:aeb1df146756 158
mbed_official 76:aeb1df146756 159 if (DMAy_Channelx == DMA1_Channel1)
mbed_official 76:aeb1df146756 160 {
mbed_official 76:aeb1df146756 161 /* Reset interrupt pending bits for DMA1 Channel1 */
mbed_official 76:aeb1df146756 162 DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
mbed_official 76:aeb1df146756 163 }
mbed_official 76:aeb1df146756 164 else if (DMAy_Channelx == DMA1_Channel2)
mbed_official 76:aeb1df146756 165 {
mbed_official 76:aeb1df146756 166 /* Reset interrupt pending bits for DMA1 Channel2 */
mbed_official 76:aeb1df146756 167 DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
mbed_official 76:aeb1df146756 168 }
mbed_official 76:aeb1df146756 169 else if (DMAy_Channelx == DMA1_Channel3)
mbed_official 76:aeb1df146756 170 {
mbed_official 76:aeb1df146756 171 /* Reset interrupt pending bits for DMA1 Channel3 */
mbed_official 76:aeb1df146756 172 DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
mbed_official 76:aeb1df146756 173 }
mbed_official 76:aeb1df146756 174 else if (DMAy_Channelx == DMA1_Channel4)
mbed_official 76:aeb1df146756 175 {
mbed_official 76:aeb1df146756 176 /* Reset interrupt pending bits for DMA1 Channel4 */
mbed_official 76:aeb1df146756 177 DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
mbed_official 76:aeb1df146756 178 }
mbed_official 76:aeb1df146756 179 else if (DMAy_Channelx == DMA1_Channel5)
mbed_official 76:aeb1df146756 180 {
mbed_official 76:aeb1df146756 181 /* Reset interrupt pending bits for DMA1 Channel5 */
mbed_official 76:aeb1df146756 182 DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
mbed_official 76:aeb1df146756 183 }
mbed_official 76:aeb1df146756 184 else if (DMAy_Channelx == DMA1_Channel6)
mbed_official 76:aeb1df146756 185 {
mbed_official 76:aeb1df146756 186 /* Reset interrupt pending bits for DMA1 Channel6 */
mbed_official 76:aeb1df146756 187 DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
mbed_official 76:aeb1df146756 188 }
mbed_official 76:aeb1df146756 189 else
mbed_official 76:aeb1df146756 190 {
mbed_official 76:aeb1df146756 191 if (DMAy_Channelx == DMA1_Channel7)
mbed_official 76:aeb1df146756 192 {
mbed_official 76:aeb1df146756 193 /* Reset interrupt pending bits for DMA1 Channel7 */
mbed_official 76:aeb1df146756 194 DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
mbed_official 76:aeb1df146756 195 }
mbed_official 76:aeb1df146756 196 }
mbed_official 76:aeb1df146756 197 }
mbed_official 76:aeb1df146756 198
mbed_official 76:aeb1df146756 199 /**
mbed_official 76:aeb1df146756 200 * @brief Initializes the DMAy Channelx according to the specified parameters
mbed_official 76:aeb1df146756 201 * in the DMA_InitStruct.
mbed_official 76:aeb1df146756 202 * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
mbed_official 76:aeb1df146756 203 * for DMA1 to select the DMA Channel.
mbed_official 76:aeb1df146756 204 * @note Channel 6 and 7 are available only for STM32F072 devices.
mbed_official 76:aeb1df146756 205 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
mbed_official 76:aeb1df146756 206 * the configuration information for the specified DMA Channel.
mbed_official 76:aeb1df146756 207 * @retval None
mbed_official 76:aeb1df146756 208 */
mbed_official 76:aeb1df146756 209 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
mbed_official 76:aeb1df146756 210 {
mbed_official 76:aeb1df146756 211 uint32_t tmpreg = 0;
mbed_official 76:aeb1df146756 212
mbed_official 76:aeb1df146756 213 /* Check the parameters */
mbed_official 76:aeb1df146756 214 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
mbed_official 76:aeb1df146756 215 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
mbed_official 76:aeb1df146756 216 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
mbed_official 76:aeb1df146756 217 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
mbed_official 76:aeb1df146756 218 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
mbed_official 76:aeb1df146756 219 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
mbed_official 76:aeb1df146756 220 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
mbed_official 76:aeb1df146756 221 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
mbed_official 76:aeb1df146756 222 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
mbed_official 76:aeb1df146756 223 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
mbed_official 76:aeb1df146756 224
mbed_official 76:aeb1df146756 225 /*--------------------------- DMAy Channelx CCR Configuration ----------------*/
mbed_official 76:aeb1df146756 226 /* Get the DMAy_Channelx CCR value */
mbed_official 76:aeb1df146756 227 tmpreg = DMAy_Channelx->CCR;
mbed_official 76:aeb1df146756 228
mbed_official 76:aeb1df146756 229 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
mbed_official 76:aeb1df146756 230 tmpreg &= CCR_CLEAR_MASK;
mbed_official 76:aeb1df146756 231
mbed_official 76:aeb1df146756 232 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
mbed_official 76:aeb1df146756 233 /* Set DIR bit according to DMA_DIR value */
mbed_official 76:aeb1df146756 234 /* Set CIRC bit according to DMA_Mode value */
mbed_official 76:aeb1df146756 235 /* Set PINC bit according to DMA_PeripheralInc value */
mbed_official 76:aeb1df146756 236 /* Set MINC bit according to DMA_MemoryInc value */
mbed_official 76:aeb1df146756 237 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
mbed_official 76:aeb1df146756 238 /* Set MSIZE bits according to DMA_MemoryDataSize value */
mbed_official 76:aeb1df146756 239 /* Set PL bits according to DMA_Priority value */
mbed_official 76:aeb1df146756 240 /* Set the MEM2MEM bit according to DMA_M2M value */
mbed_official 76:aeb1df146756 241 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
mbed_official 76:aeb1df146756 242 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
mbed_official 76:aeb1df146756 243 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
mbed_official 76:aeb1df146756 244 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
mbed_official 76:aeb1df146756 245
mbed_official 76:aeb1df146756 246 /* Write to DMAy Channelx CCR */
mbed_official 76:aeb1df146756 247 DMAy_Channelx->CCR = tmpreg;
mbed_official 76:aeb1df146756 248
mbed_official 76:aeb1df146756 249 /*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
mbed_official 76:aeb1df146756 250 /* Write to DMAy Channelx CNDTR */
mbed_official 76:aeb1df146756 251 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
mbed_official 76:aeb1df146756 252
mbed_official 76:aeb1df146756 253 /*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
mbed_official 76:aeb1df146756 254 /* Write to DMAy Channelx CPAR */
mbed_official 76:aeb1df146756 255 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
mbed_official 76:aeb1df146756 256
mbed_official 76:aeb1df146756 257 /*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
mbed_official 76:aeb1df146756 258 /* Write to DMAy Channelx CMAR */
mbed_official 76:aeb1df146756 259 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
mbed_official 76:aeb1df146756 260 }
mbed_official 76:aeb1df146756 261
mbed_official 76:aeb1df146756 262 /**
mbed_official 76:aeb1df146756 263 * @brief Fills each DMA_InitStruct member with its default value.
mbed_official 76:aeb1df146756 264 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
mbed_official 76:aeb1df146756 265 * be initialized.
mbed_official 76:aeb1df146756 266 * @retval None
mbed_official 76:aeb1df146756 267 */
mbed_official 76:aeb1df146756 268 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
mbed_official 76:aeb1df146756 269 {
mbed_official 76:aeb1df146756 270 /*-------------- Reset DMA init structure parameters values ------------------*/
mbed_official 76:aeb1df146756 271 /* Initialize the DMA_PeripheralBaseAddr member */
mbed_official 76:aeb1df146756 272 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
mbed_official 76:aeb1df146756 273 /* Initialize the DMA_MemoryBaseAddr member */
mbed_official 76:aeb1df146756 274 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
mbed_official 76:aeb1df146756 275 /* Initialize the DMA_DIR member */
mbed_official 76:aeb1df146756 276 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
mbed_official 76:aeb1df146756 277 /* Initialize the DMA_BufferSize member */
mbed_official 76:aeb1df146756 278 DMA_InitStruct->DMA_BufferSize = 0;
mbed_official 76:aeb1df146756 279 /* Initialize the DMA_PeripheralInc member */
mbed_official 76:aeb1df146756 280 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
mbed_official 76:aeb1df146756 281 /* Initialize the DMA_MemoryInc member */
mbed_official 76:aeb1df146756 282 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
mbed_official 76:aeb1df146756 283 /* Initialize the DMA_PeripheralDataSize member */
mbed_official 76:aeb1df146756 284 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
mbed_official 76:aeb1df146756 285 /* Initialize the DMA_MemoryDataSize member */
mbed_official 76:aeb1df146756 286 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
mbed_official 76:aeb1df146756 287 /* Initialize the DMA_Mode member */
mbed_official 76:aeb1df146756 288 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
mbed_official 76:aeb1df146756 289 /* Initialize the DMA_Priority member */
mbed_official 76:aeb1df146756 290 DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
mbed_official 76:aeb1df146756 291 /* Initialize the DMA_M2M member */
mbed_official 76:aeb1df146756 292 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
mbed_official 76:aeb1df146756 293 }
mbed_official 76:aeb1df146756 294
mbed_official 76:aeb1df146756 295 /**
mbed_official 76:aeb1df146756 296 * @brief Enables or disables the specified DMAy Channelx.
mbed_official 76:aeb1df146756 297 * @param DMAy_Channelx: where y can be 1 to select the DMA and
mbed_official 76:aeb1df146756 298 * x can be 1 to 7 for DMA1 to select the DMA Channel.
mbed_official 76:aeb1df146756 299 * @note Channel 6 and 7 are available only for STM32F072 devices.
mbed_official 76:aeb1df146756 300 * @param NewState: new state of the DMAy Channelx.
mbed_official 76:aeb1df146756 301 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 302 * @retval None
mbed_official 76:aeb1df146756 303 */
mbed_official 76:aeb1df146756 304 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
mbed_official 76:aeb1df146756 305 {
mbed_official 76:aeb1df146756 306 /* Check the parameters */
mbed_official 76:aeb1df146756 307 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
mbed_official 76:aeb1df146756 308 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 309
mbed_official 76:aeb1df146756 310 if (NewState != DISABLE)
mbed_official 76:aeb1df146756 311 {
mbed_official 76:aeb1df146756 312 /* Enable the selected DMAy Channelx */
mbed_official 76:aeb1df146756 313 DMAy_Channelx->CCR |= DMA_CCR_EN;
mbed_official 76:aeb1df146756 314 }
mbed_official 76:aeb1df146756 315 else
mbed_official 76:aeb1df146756 316 {
mbed_official 76:aeb1df146756 317 /* Disable the selected DMAy Channelx */
mbed_official 76:aeb1df146756 318 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
mbed_official 76:aeb1df146756 319 }
mbed_official 76:aeb1df146756 320 }
mbed_official 76:aeb1df146756 321
mbed_official 76:aeb1df146756 322 /**
mbed_official 76:aeb1df146756 323 * @}
mbed_official 76:aeb1df146756 324 */
mbed_official 76:aeb1df146756 325
mbed_official 76:aeb1df146756 326 /** @defgroup DMA_Group2 Data Counter functions
mbed_official 76:aeb1df146756 327 * @brief Data Counter functions
mbed_official 76:aeb1df146756 328 *
mbed_official 76:aeb1df146756 329 @verbatim
mbed_official 76:aeb1df146756 330 ===============================================================================
mbed_official 76:aeb1df146756 331 ##### Data Counter functions #####
mbed_official 76:aeb1df146756 332 ===============================================================================
mbed_official 76:aeb1df146756 333 [..] This subsection provides function allowing to configure and read the buffer
mbed_official 76:aeb1df146756 334 size (number of data to be transferred).The DMA data counter can be written
mbed_official 76:aeb1df146756 335 only when the DMA channel is disabled (ie. after transfer complete event).
mbed_official 76:aeb1df146756 336 [..] The following function can be used to write the Channel data counter value:
mbed_official 76:aeb1df146756 337 (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t
mbed_official 76:aeb1df146756 338 DataNumber).
mbed_official 76:aeb1df146756 339 -@- It is advised to use this function rather than DMA_Init() in situations
mbed_official 76:aeb1df146756 340 where only the Data buffer needs to be reloaded.
mbed_official 76:aeb1df146756 341 [..] The DMA data counter can be read to indicate the number of remaining transfers
mbed_official 76:aeb1df146756 342 for the relative DMA channel. This counter is decremented at the end of each
mbed_official 76:aeb1df146756 343 data transfer and when the transfer is complete:
mbed_official 76:aeb1df146756 344 (+) If Normal mode is selected: the counter is set to 0.
mbed_official 76:aeb1df146756 345 (+) If Circular mode is selected: the counter is reloaded with the initial
mbed_official 76:aeb1df146756 346 value(configured before enabling the DMA channel).
mbed_official 76:aeb1df146756 347 [..] The following function can be used to read the Channel data counter value:
mbed_official 76:aeb1df146756 348 (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
mbed_official 76:aeb1df146756 349
mbed_official 76:aeb1df146756 350 @endverbatim
mbed_official 76:aeb1df146756 351 * @{
mbed_official 76:aeb1df146756 352 */
mbed_official 76:aeb1df146756 353
mbed_official 76:aeb1df146756 354 /**
mbed_official 76:aeb1df146756 355 * @brief Sets the number of data units in the current DMAy Channelx transfer.
mbed_official 76:aeb1df146756 356 * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be
mbed_official 76:aeb1df146756 357 * 1 to 7 for DMA1 to select the DMA Channel.
mbed_official 76:aeb1df146756 358 * @note Channel 6 and 7 are available only for STM32F072 devices.
mbed_official 76:aeb1df146756 359 * @param DataNumber: The number of data units in the current DMAy Channelx
mbed_official 76:aeb1df146756 360 * transfer.
mbed_official 76:aeb1df146756 361 * @note This function can only be used when the DMAy_Channelx is disabled.
mbed_official 76:aeb1df146756 362 * @retval None.
mbed_official 76:aeb1df146756 363 */
mbed_official 76:aeb1df146756 364 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
mbed_official 76:aeb1df146756 365 {
mbed_official 76:aeb1df146756 366 /* Check the parameters */
mbed_official 76:aeb1df146756 367 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
mbed_official 76:aeb1df146756 368
mbed_official 76:aeb1df146756 369 /*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
mbed_official 76:aeb1df146756 370 /* Write to DMAy Channelx CNDTR */
mbed_official 76:aeb1df146756 371 DMAy_Channelx->CNDTR = DataNumber;
mbed_official 76:aeb1df146756 372 }
mbed_official 76:aeb1df146756 373
mbed_official 76:aeb1df146756 374 /**
mbed_official 76:aeb1df146756 375 * @brief Returns the number of remaining data units in the current
mbed_official 76:aeb1df146756 376 * DMAy Channelx transfer.
mbed_official 76:aeb1df146756 377 * @param DMAy_Channelx: where y can be 1 to select the DMA and
mbed_official 76:aeb1df146756 378 * x can be 1 to 7 for DMA1 to select the DMA Channel.
mbed_official 76:aeb1df146756 379 * @note Channel 6 and 7 are available only for STM32F072 devices.
mbed_official 76:aeb1df146756 380 * @retval The number of remaining data units in the current DMAy Channelx
mbed_official 76:aeb1df146756 381 * transfer.
mbed_official 76:aeb1df146756 382 */
mbed_official 76:aeb1df146756 383 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
mbed_official 76:aeb1df146756 384 {
mbed_official 76:aeb1df146756 385 /* Check the parameters */
mbed_official 76:aeb1df146756 386 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
mbed_official 76:aeb1df146756 387 /* Return the number of remaining data units for DMAy Channelx */
mbed_official 76:aeb1df146756 388 return ((uint16_t)(DMAy_Channelx->CNDTR));
mbed_official 76:aeb1df146756 389 }
mbed_official 76:aeb1df146756 390
mbed_official 76:aeb1df146756 391 /**
mbed_official 76:aeb1df146756 392 * @}
mbed_official 76:aeb1df146756 393 */
mbed_official 76:aeb1df146756 394
mbed_official 76:aeb1df146756 395 /** @defgroup DMA_Group3 Interrupts and flags management functions
mbed_official 76:aeb1df146756 396 * @brief Interrupts and flags management functions
mbed_official 76:aeb1df146756 397 *
mbed_official 76:aeb1df146756 398 @verbatim
mbed_official 76:aeb1df146756 399 ===============================================================================
mbed_official 76:aeb1df146756 400 ##### Interrupts and flags management functions #####
mbed_official 76:aeb1df146756 401 ===============================================================================
mbed_official 76:aeb1df146756 402 [..] This subsection provides functions allowing to configure the DMA Interrupts
mbed_official 76:aeb1df146756 403 sources and check or clear the flags or pending bits status.
mbed_official 76:aeb1df146756 404 The user should identify which mode will be used in his application to manage
mbed_official 76:aeb1df146756 405 the DMA controller events: Polling mode or Interrupt mode.
mbed_official 76:aeb1df146756 406 *** Polling Mode ***
mbed_official 76:aeb1df146756 407 ====================
mbed_official 76:aeb1df146756 408 [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller
mbed_official 76:aeb1df146756 409 number x : DMA channel number ).
mbed_official 76:aeb1df146756 410 (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
mbed_official 76:aeb1df146756 411 (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
mbed_official 76:aeb1df146756 412 (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
mbed_official 76:aeb1df146756 413 (#) DMAy_FLAG_GLx : to indicate that at least one of the events described
mbed_official 76:aeb1df146756 414 above occurred.
mbed_official 76:aeb1df146756 415 -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
mbed_official 76:aeb1df146756 416 same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
mbed_official 76:aeb1df146756 417 [..]In this Mode it is advised to use the following functions:
mbed_official 76:aeb1df146756 418 (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
mbed_official 76:aeb1df146756 419 (+) void DMA_ClearFlag(uint32_t DMA_FLAG);
mbed_official 76:aeb1df146756 420
mbed_official 76:aeb1df146756 421 *** Interrupt Mode ***
mbed_official 76:aeb1df146756 422 ======================
mbed_official 76:aeb1df146756 423 [..] Each DMA channel can be managed through 4 Interrupts:
mbed_official 76:aeb1df146756 424 (+) Interrupt Source
mbed_official 76:aeb1df146756 425 (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete
mbed_official 76:aeb1df146756 426 event.
mbed_official 76:aeb1df146756 427 (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete
mbed_official 76:aeb1df146756 428 event.
mbed_official 76:aeb1df146756 429 (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.
mbed_official 76:aeb1df146756 430 (##) DMA_IT_GL : to indicate that at least one of the interrupts described
mbed_official 76:aeb1df146756 431 above occurred.
mbed_official 76:aeb1df146756 432 -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of
mbed_official 76:aeb1df146756 433 the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
mbed_official 76:aeb1df146756 434 [..]In this Mode it is advised to use the following functions:
mbed_official 76:aeb1df146756 435 (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT,
mbed_official 76:aeb1df146756 436 FunctionalState NewState);
mbed_official 76:aeb1df146756 437 (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
mbed_official 76:aeb1df146756 438 (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
mbed_official 76:aeb1df146756 439
mbed_official 76:aeb1df146756 440 @endverbatim
mbed_official 76:aeb1df146756 441 * @{
mbed_official 76:aeb1df146756 442 */
mbed_official 76:aeb1df146756 443
mbed_official 76:aeb1df146756 444 /**
mbed_official 76:aeb1df146756 445 * @brief Enables or disables the specified DMAy Channelx interrupts.
mbed_official 76:aeb1df146756 446 * @param DMAy_Channelx: where y can be 1 to select the DMA and
mbed_official 76:aeb1df146756 447 * x can be 1 to 7 for DMA1 to select the DMA Channel.
mbed_official 76:aeb1df146756 448 * @note Channel 6 and 7 are available only for STM32F072 devices.
mbed_official 76:aeb1df146756 449 * @param DMA_IT: specifies the DMA interrupts sources to be enabled
mbed_official 76:aeb1df146756 450 * or disabled.
mbed_official 76:aeb1df146756 451 * This parameter can be any combination of the following values:
mbed_official 76:aeb1df146756 452 * @arg DMA_IT_TC: Transfer complete interrupt mask
mbed_official 76:aeb1df146756 453 * @arg DMA_IT_HT: Half transfer interrupt mask
mbed_official 76:aeb1df146756 454 * @arg DMA_IT_TE: Transfer error interrupt mask
mbed_official 76:aeb1df146756 455 * @param NewState: new state of the specified DMA interrupts.
mbed_official 76:aeb1df146756 456 * This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 457 * @retval None
mbed_official 76:aeb1df146756 458 */
mbed_official 76:aeb1df146756 459 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
mbed_official 76:aeb1df146756 460 {
mbed_official 76:aeb1df146756 461 /* Check the parameters */
mbed_official 76:aeb1df146756 462 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
mbed_official 76:aeb1df146756 463 assert_param(IS_DMA_CONFIG_IT(DMA_IT));
mbed_official 76:aeb1df146756 464 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 465
mbed_official 76:aeb1df146756 466 if (NewState != DISABLE)
mbed_official 76:aeb1df146756 467 {
mbed_official 76:aeb1df146756 468 /* Enable the selected DMA interrupts */
mbed_official 76:aeb1df146756 469 DMAy_Channelx->CCR |= DMA_IT;
mbed_official 76:aeb1df146756 470 }
mbed_official 76:aeb1df146756 471 else
mbed_official 76:aeb1df146756 472 {
mbed_official 76:aeb1df146756 473 /* Disable the selected DMA interrupts */
mbed_official 76:aeb1df146756 474 DMAy_Channelx->CCR &= ~DMA_IT;
mbed_official 76:aeb1df146756 475 }
mbed_official 76:aeb1df146756 476 }
mbed_official 76:aeb1df146756 477
mbed_official 76:aeb1df146756 478 /**
mbed_official 76:aeb1df146756 479 * @brief Checks whether the specified DMAy Channelx flag is set or not.
mbed_official 76:aeb1df146756 480 * @param DMA_FLAG: specifies the flag to check.
mbed_official 76:aeb1df146756 481 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 482 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
mbed_official 76:aeb1df146756 483 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
mbed_official 76:aeb1df146756 484 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
mbed_official 76:aeb1df146756 485 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
mbed_official 76:aeb1df146756 486 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
mbed_official 76:aeb1df146756 487 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
mbed_official 76:aeb1df146756 488 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
mbed_official 76:aeb1df146756 489 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
mbed_official 76:aeb1df146756 490 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
mbed_official 76:aeb1df146756 491 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
mbed_official 76:aeb1df146756 492 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
mbed_official 76:aeb1df146756 493 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
mbed_official 76:aeb1df146756 494 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
mbed_official 76:aeb1df146756 495 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
mbed_official 76:aeb1df146756 496 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
mbed_official 76:aeb1df146756 497 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
mbed_official 76:aeb1df146756 498 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
mbed_official 76:aeb1df146756 499 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
mbed_official 76:aeb1df146756 500 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
mbed_official 76:aeb1df146756 501 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
mbed_official 76:aeb1df146756 502 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 503 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 504 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 505 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 506 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 507 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 508 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 509 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 510 * @note The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
mbed_official 76:aeb1df146756 511 * relative to the same channel is set (Transfer Complete, Half-transfer
mbed_official 76:aeb1df146756 512 * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
mbed_official 76:aeb1df146756 513 * DMAy_FLAG_TEx).
mbed_official 76:aeb1df146756 514 *
mbed_official 76:aeb1df146756 515 * @retval The new state of DMA_FLAG (SET or RESET).
mbed_official 76:aeb1df146756 516 */
mbed_official 76:aeb1df146756 517 FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
mbed_official 76:aeb1df146756 518 {
mbed_official 76:aeb1df146756 519 FlagStatus bitstatus = RESET;
mbed_official 76:aeb1df146756 520
mbed_official 76:aeb1df146756 521 /* Check the parameters */
mbed_official 76:aeb1df146756 522 assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
mbed_official 76:aeb1df146756 523
mbed_official 76:aeb1df146756 524 /* Check the status of the specified DMA flag */
mbed_official 76:aeb1df146756 525 if ((DMA1->ISR & DMA_FLAG) != (uint32_t)RESET)
mbed_official 76:aeb1df146756 526 {
mbed_official 76:aeb1df146756 527 /* DMA_FLAG is set */
mbed_official 76:aeb1df146756 528 bitstatus = SET;
mbed_official 76:aeb1df146756 529 }
mbed_official 76:aeb1df146756 530 else
mbed_official 76:aeb1df146756 531 {
mbed_official 76:aeb1df146756 532 /* DMA_FLAG is reset */
mbed_official 76:aeb1df146756 533 bitstatus = RESET;
mbed_official 76:aeb1df146756 534 }
mbed_official 76:aeb1df146756 535
mbed_official 76:aeb1df146756 536 /* Return the DMA_FLAG status */
mbed_official 76:aeb1df146756 537 return bitstatus;
mbed_official 76:aeb1df146756 538 }
mbed_official 76:aeb1df146756 539
mbed_official 76:aeb1df146756 540 /**
mbed_official 76:aeb1df146756 541 * @brief Clears the DMAy Channelx's pending flags.
mbed_official 76:aeb1df146756 542 * @param DMA_FLAG: specifies the flag to clear.
mbed_official 76:aeb1df146756 543 * This parameter can be any combination (for the same DMA) of the following values:
mbed_official 76:aeb1df146756 544 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
mbed_official 76:aeb1df146756 545 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
mbed_official 76:aeb1df146756 546 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
mbed_official 76:aeb1df146756 547 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
mbed_official 76:aeb1df146756 548 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
mbed_official 76:aeb1df146756 549 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
mbed_official 76:aeb1df146756 550 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
mbed_official 76:aeb1df146756 551 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
mbed_official 76:aeb1df146756 552 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
mbed_official 76:aeb1df146756 553 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
mbed_official 76:aeb1df146756 554 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
mbed_official 76:aeb1df146756 555 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
mbed_official 76:aeb1df146756 556 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
mbed_official 76:aeb1df146756 557 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
mbed_official 76:aeb1df146756 558 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
mbed_official 76:aeb1df146756 559 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
mbed_official 76:aeb1df146756 560 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
mbed_official 76:aeb1df146756 561 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
mbed_official 76:aeb1df146756 562 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
mbed_official 76:aeb1df146756 563 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
mbed_official 76:aeb1df146756 564 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 565 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 566 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 567 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 568 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 569 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 570 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 571 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 572 *
mbed_official 76:aeb1df146756 573 * @note Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
mbed_official 76:aeb1df146756 574 * relative to the same channel (Transfer Complete, Half-transfer Complete and
mbed_official 76:aeb1df146756 575 * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
mbed_official 76:aeb1df146756 576 *
mbed_official 76:aeb1df146756 577 * @retval None
mbed_official 76:aeb1df146756 578 */
mbed_official 76:aeb1df146756 579 void DMA_ClearFlag(uint32_t DMA_FLAG)
mbed_official 76:aeb1df146756 580 {
mbed_official 76:aeb1df146756 581 /* Check the parameters */
mbed_official 76:aeb1df146756 582 assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
mbed_official 76:aeb1df146756 583
mbed_official 76:aeb1df146756 584 /* Clear the selected DMA flags */
mbed_official 76:aeb1df146756 585 DMA1->IFCR = DMA_FLAG;
mbed_official 76:aeb1df146756 586 }
mbed_official 76:aeb1df146756 587
mbed_official 76:aeb1df146756 588 /**
mbed_official 76:aeb1df146756 589 * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
mbed_official 76:aeb1df146756 590 * @param DMA_IT: specifies the DMA interrupt source to check.
mbed_official 76:aeb1df146756 591 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 592 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
mbed_official 76:aeb1df146756 593 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
mbed_official 76:aeb1df146756 594 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
mbed_official 76:aeb1df146756 595 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
mbed_official 76:aeb1df146756 596 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
mbed_official 76:aeb1df146756 597 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
mbed_official 76:aeb1df146756 598 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
mbed_official 76:aeb1df146756 599 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
mbed_official 76:aeb1df146756 600 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
mbed_official 76:aeb1df146756 601 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
mbed_official 76:aeb1df146756 602 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
mbed_official 76:aeb1df146756 603 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
mbed_official 76:aeb1df146756 604 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
mbed_official 76:aeb1df146756 605 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
mbed_official 76:aeb1df146756 606 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
mbed_official 76:aeb1df146756 607 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
mbed_official 76:aeb1df146756 608 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
mbed_official 76:aeb1df146756 609 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
mbed_official 76:aeb1df146756 610 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
mbed_official 76:aeb1df146756 611 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
mbed_official 76:aeb1df146756 612 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 613 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 614 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 615 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 616 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 617 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 618 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 619 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 620 *
mbed_official 76:aeb1df146756 621 * @note The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
mbed_official 76:aeb1df146756 622 * interrupts relative to the same channel is set (Transfer Complete,
mbed_official 76:aeb1df146756 623 * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
mbed_official 76:aeb1df146756 624 * DMAy_IT_HTx or DMAy_IT_TEx).
mbed_official 76:aeb1df146756 625 *
mbed_official 76:aeb1df146756 626 * @retval The new state of DMA_IT (SET or RESET).
mbed_official 76:aeb1df146756 627 */
mbed_official 76:aeb1df146756 628 ITStatus DMA_GetITStatus(uint32_t DMA_IT)
mbed_official 76:aeb1df146756 629 {
mbed_official 76:aeb1df146756 630 ITStatus bitstatus = RESET;
mbed_official 76:aeb1df146756 631
mbed_official 76:aeb1df146756 632 /* Check the parameters */
mbed_official 76:aeb1df146756 633 assert_param(IS_DMA_GET_IT(DMA_IT));
mbed_official 76:aeb1df146756 634
mbed_official 76:aeb1df146756 635 /* Check the status of the specified DMA interrupt */
mbed_official 76:aeb1df146756 636 if ((DMA1->ISR & DMA_IT) != (uint32_t)RESET)
mbed_official 76:aeb1df146756 637 {
mbed_official 76:aeb1df146756 638 /* DMA_IT is set */
mbed_official 76:aeb1df146756 639 bitstatus = SET;
mbed_official 76:aeb1df146756 640 }
mbed_official 76:aeb1df146756 641 else
mbed_official 76:aeb1df146756 642 {
mbed_official 76:aeb1df146756 643 /* DMA_IT is reset */
mbed_official 76:aeb1df146756 644 bitstatus = RESET;
mbed_official 76:aeb1df146756 645 }
mbed_official 76:aeb1df146756 646 /* Return the DMA_IT status */
mbed_official 76:aeb1df146756 647 return bitstatus;
mbed_official 76:aeb1df146756 648 }
mbed_official 76:aeb1df146756 649
mbed_official 76:aeb1df146756 650 /**
mbed_official 76:aeb1df146756 651 * @brief Clears the DMAy Channelx's interrupt pending bits.
mbed_official 76:aeb1df146756 652 * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
mbed_official 76:aeb1df146756 653 * This parameter can be any combination (for the same DMA) of the following values:
mbed_official 76:aeb1df146756 654 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
mbed_official 76:aeb1df146756 655 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
mbed_official 76:aeb1df146756 656 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
mbed_official 76:aeb1df146756 657 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
mbed_official 76:aeb1df146756 658 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
mbed_official 76:aeb1df146756 659 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
mbed_official 76:aeb1df146756 660 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
mbed_official 76:aeb1df146756 661 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
mbed_official 76:aeb1df146756 662 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
mbed_official 76:aeb1df146756 663 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
mbed_official 76:aeb1df146756 664 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
mbed_official 76:aeb1df146756 665 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
mbed_official 76:aeb1df146756 666 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
mbed_official 76:aeb1df146756 667 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
mbed_official 76:aeb1df146756 668 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
mbed_official 76:aeb1df146756 669 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
mbed_official 76:aeb1df146756 670 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
mbed_official 76:aeb1df146756 671 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
mbed_official 76:aeb1df146756 672 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
mbed_official 76:aeb1df146756 673 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
mbed_official 76:aeb1df146756 674 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 675 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 676 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 677 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 678 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 679 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 680 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 681 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt, applicable only for STM32F072 devices.
mbed_official 76:aeb1df146756 682 *
mbed_official 76:aeb1df146756 683 * @note Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
mbed_official 76:aeb1df146756 684 * interrupts relative to the same channel (Transfer Complete, Half-transfer
mbed_official 76:aeb1df146756 685 * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
mbed_official 76:aeb1df146756 686 * DMAy_IT_TEx).
mbed_official 76:aeb1df146756 687 *
mbed_official 76:aeb1df146756 688 * @retval None
mbed_official 76:aeb1df146756 689 */
mbed_official 76:aeb1df146756 690 void DMA_ClearITPendingBit(uint32_t DMA_IT)
mbed_official 76:aeb1df146756 691 {
mbed_official 76:aeb1df146756 692 /* Check the parameters */
mbed_official 76:aeb1df146756 693 assert_param(IS_DMA_CLEAR_IT(DMA_IT));
mbed_official 76:aeb1df146756 694
mbed_official 76:aeb1df146756 695 /* Clear the selected DMA interrupt pending bits */
mbed_official 76:aeb1df146756 696 DMA1->IFCR = DMA_IT;
mbed_official 76:aeb1df146756 697 }
mbed_official 76:aeb1df146756 698
mbed_official 76:aeb1df146756 699 /**
mbed_official 76:aeb1df146756 700 * @}
mbed_official 76:aeb1df146756 701 */
mbed_official 76:aeb1df146756 702
mbed_official 76:aeb1df146756 703 /**
mbed_official 76:aeb1df146756 704 * @}
mbed_official 76:aeb1df146756 705 */
mbed_official 76:aeb1df146756 706
mbed_official 76:aeb1df146756 707 /**
mbed_official 76:aeb1df146756 708 * @}
mbed_official 76:aeb1df146756 709 */
mbed_official 76:aeb1df146756 710
mbed_official 76:aeb1df146756 711 /**
mbed_official 76:aeb1df146756 712 * @}
mbed_official 76:aeb1df146756 713 */
mbed_official 76:aeb1df146756 714
mbed_official 76:aeb1df146756 715 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/