mbed-F401 - mbed library with additional peripherals for ST F…

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Peter Drescher / mbed-F401

mbed library with additional peripherals for ST F401 board

Fork of mbed-src by mbed official

This mbed LIB has additional peripherals for ST F401 board

UART2 : PA_3 rx, PA_2 tx
UART3 : PC_7 rx, PC_6 tx
I2C2 : PB_3 SDA, PB_10 SCL
I2C3 : PB_4 SDA, PA_8 SCL

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_tim.c@70:c1fbde68b492, 2014-01-07 (annotated)

Committer:: mbed_official
Date:: Tue Jan 07 11:00:05 2014 +0000
Revision:: 70:c1fbde68b492
Parent:: 52:a51c77007319
Child:: 84:f54042cbc282

Synchronized with git revision 3f438a307904431f2782db3c8fa49946b9fc1d85



Full URL: https://github.com/mbedmicro/mbed/commit/3f438a307904431f2782db3c8fa49946b9fc1d85/



[NUCLEO_F103RB] license text changed + sleep hal updated

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	52:a51c77007319	1	/**
mbed_official	52:a51c77007319	2	******************************************************************************
mbed_official	52:a51c77007319	3	* @file stm32f10x_tim.c
mbed_official	52:a51c77007319	4	* @author MCD Application Team
mbed_official	52:a51c77007319	5	* @version V3.5.0
mbed_official	52:a51c77007319	6	* @date 11-March-2011
mbed_official	52:a51c77007319	7	* @brief This file provides all the TIM firmware functions.
mbed_official	70:c1fbde68b492	8	*******************************************************************************
mbed_official	70:c1fbde68b492	9	* Copyright (c) 2014, STMicroelectronics
mbed_official	70:c1fbde68b492	10	* All rights reserved.
mbed_official	70:c1fbde68b492	11	*
mbed_official	70:c1fbde68b492	12	* Redistribution and use in source and binary forms, with or without
mbed_official	70:c1fbde68b492	13	* modification, are permitted provided that the following conditions are met:
mbed_official	70:c1fbde68b492	14	*
mbed_official	70:c1fbde68b492	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	70:c1fbde68b492	16	* this list of conditions and the following disclaimer.
mbed_official	70:c1fbde68b492	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	70:c1fbde68b492	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	70:c1fbde68b492	19	* and/or other materials provided with the distribution.
mbed_official	70:c1fbde68b492	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	70:c1fbde68b492	21	* may be used to endorse or promote products derived from this software
mbed_official	70:c1fbde68b492	22	* without specific prior written permission.
mbed_official	70:c1fbde68b492	23	*
mbed_official	70:c1fbde68b492	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	70:c1fbde68b492	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	70:c1fbde68b492	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	70:c1fbde68b492	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	70:c1fbde68b492	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	70:c1fbde68b492	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	70:c1fbde68b492	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	70:c1fbde68b492	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	70:c1fbde68b492	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	70:c1fbde68b492	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	70:c1fbde68b492	34	*******************************************************************************
mbed_official	70:c1fbde68b492	35	*/
mbed_official	52:a51c77007319	36
mbed_official	52:a51c77007319	37	/* Includes ------------------------------------------------------------------*/
mbed_official	52:a51c77007319	38	#include "stm32f10x_tim.h"
mbed_official	52:a51c77007319	39	#include "stm32f10x_rcc.h"
mbed_official	52:a51c77007319	40
mbed_official	52:a51c77007319	41	/** @addtogroup STM32F10x_StdPeriph_Driver
mbed_official	52:a51c77007319	42	* @{
mbed_official	52:a51c77007319	43	*/
mbed_official	52:a51c77007319	44
mbed_official	52:a51c77007319	45	/** @defgroup TIM
mbed_official	52:a51c77007319	46	* @brief TIM driver modules
mbed_official	52:a51c77007319	47	* @{
mbed_official	52:a51c77007319	48	*/
mbed_official	52:a51c77007319	49
mbed_official	52:a51c77007319	50	/** @defgroup TIM_Private_TypesDefinitions
mbed_official	52:a51c77007319	51	* @{
mbed_official	52:a51c77007319	52	*/
mbed_official	52:a51c77007319	53
mbed_official	52:a51c77007319	54	/**
mbed_official	52:a51c77007319	55	* @}
mbed_official	52:a51c77007319	56	*/
mbed_official	52:a51c77007319	57
mbed_official	52:a51c77007319	58	/** @defgroup TIM_Private_Defines
mbed_official	52:a51c77007319	59	* @{
mbed_official	52:a51c77007319	60	*/
mbed_official	52:a51c77007319	61
mbed_official	52:a51c77007319	62	/* ---------------------- TIM registers bit mask ------------------------ */
mbed_official	52:a51c77007319	63	#define SMCR_ETR_Mask ((uint16_t)0x00FF)
mbed_official	52:a51c77007319	64	#define CCMR_Offset ((uint16_t)0x0018)
mbed_official	52:a51c77007319	65	#define CCER_CCE_Set ((uint16_t)0x0001)
mbed_official	52:a51c77007319	66	#define CCER_CCNE_Set ((uint16_t)0x0004)
mbed_official	52:a51c77007319	67
mbed_official	52:a51c77007319	68	/**
mbed_official	52:a51c77007319	69	* @}
mbed_official	52:a51c77007319	70	*/
mbed_official	52:a51c77007319	71
mbed_official	52:a51c77007319	72	/** @defgroup TIM_Private_Macros
mbed_official	52:a51c77007319	73	* @{
mbed_official	52:a51c77007319	74	*/
mbed_official	52:a51c77007319	75
mbed_official	52:a51c77007319	76	/**
mbed_official	52:a51c77007319	77	* @}
mbed_official	52:a51c77007319	78	*/
mbed_official	52:a51c77007319	79
mbed_official	52:a51c77007319	80	/** @defgroup TIM_Private_Variables
mbed_official	52:a51c77007319	81	* @{
mbed_official	52:a51c77007319	82	*/
mbed_official	52:a51c77007319	83
mbed_official	52:a51c77007319	84	/**
mbed_official	52:a51c77007319	85	* @}
mbed_official	52:a51c77007319	86	*/
mbed_official	52:a51c77007319	87
mbed_official	52:a51c77007319	88	/** @defgroup TIM_Private_FunctionPrototypes
mbed_official	52:a51c77007319	89	* @{
mbed_official	52:a51c77007319	90	*/
mbed_official	52:a51c77007319	91
mbed_official	52:a51c77007319	92	static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	93	uint16_t TIM_ICFilter);
mbed_official	52:a51c77007319	94	static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	95	uint16_t TIM_ICFilter);
mbed_official	52:a51c77007319	96	static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	97	uint16_t TIM_ICFilter);
mbed_official	52:a51c77007319	98	static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	99	uint16_t TIM_ICFilter);
mbed_official	52:a51c77007319	100	/**
mbed_official	52:a51c77007319	101	* @}
mbed_official	52:a51c77007319	102	*/
mbed_official	52:a51c77007319	103
mbed_official	52:a51c77007319	104	/** @defgroup TIM_Private_Macros
mbed_official	52:a51c77007319	105	* @{
mbed_official	52:a51c77007319	106	*/
mbed_official	52:a51c77007319	107
mbed_official	52:a51c77007319	108	/**
mbed_official	52:a51c77007319	109	* @}
mbed_official	52:a51c77007319	110	*/
mbed_official	52:a51c77007319	111
mbed_official	52:a51c77007319	112	/** @defgroup TIM_Private_Variables
mbed_official	52:a51c77007319	113	* @{
mbed_official	52:a51c77007319	114	*/
mbed_official	52:a51c77007319	115
mbed_official	52:a51c77007319	116	/**
mbed_official	52:a51c77007319	117	* @}
mbed_official	52:a51c77007319	118	*/
mbed_official	52:a51c77007319	119
mbed_official	52:a51c77007319	120	/** @defgroup TIM_Private_FunctionPrototypes
mbed_official	52:a51c77007319	121	* @{
mbed_official	52:a51c77007319	122	*/
mbed_official	52:a51c77007319	123
mbed_official	52:a51c77007319	124	/**
mbed_official	52:a51c77007319	125	* @}
mbed_official	52:a51c77007319	126	*/
mbed_official	52:a51c77007319	127
mbed_official	52:a51c77007319	128	/** @defgroup TIM_Private_Functions
mbed_official	52:a51c77007319	129	* @{
mbed_official	52:a51c77007319	130	*/
mbed_official	52:a51c77007319	131
mbed_official	52:a51c77007319	132	/**
mbed_official	52:a51c77007319	133	* @brief Deinitializes the TIMx peripheral registers to their default reset values.
mbed_official	52:a51c77007319	134	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	135	* @retval None
mbed_official	52:a51c77007319	136	*/
mbed_official	52:a51c77007319	137	void TIM_DeInit(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	138	{
mbed_official	52:a51c77007319	139	/* Check the parameters */
mbed_official	52:a51c77007319	140	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	141
mbed_official	52:a51c77007319	142	if (TIMx == TIM1)
mbed_official	52:a51c77007319	143	{
mbed_official	52:a51c77007319	144	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
mbed_official	52:a51c77007319	145	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
mbed_official	52:a51c77007319	146	}
mbed_official	52:a51c77007319	147	else if (TIMx == TIM2)
mbed_official	52:a51c77007319	148	{
mbed_official	52:a51c77007319	149	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
mbed_official	52:a51c77007319	150	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
mbed_official	52:a51c77007319	151	}
mbed_official	52:a51c77007319	152	else if (TIMx == TIM3)
mbed_official	52:a51c77007319	153	{
mbed_official	52:a51c77007319	154	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
mbed_official	52:a51c77007319	155	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
mbed_official	52:a51c77007319	156	}
mbed_official	52:a51c77007319	157	else if (TIMx == TIM4)
mbed_official	52:a51c77007319	158	{
mbed_official	52:a51c77007319	159	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
mbed_official	52:a51c77007319	160	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
mbed_official	52:a51c77007319	161	}
mbed_official	52:a51c77007319	162	else if (TIMx == TIM5)
mbed_official	52:a51c77007319	163	{
mbed_official	52:a51c77007319	164	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
mbed_official	52:a51c77007319	165	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
mbed_official	52:a51c77007319	166	}
mbed_official	52:a51c77007319	167	else if (TIMx == TIM6)
mbed_official	52:a51c77007319	168	{
mbed_official	52:a51c77007319	169	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
mbed_official	52:a51c77007319	170	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
mbed_official	52:a51c77007319	171	}
mbed_official	52:a51c77007319	172	else if (TIMx == TIM7)
mbed_official	52:a51c77007319	173	{
mbed_official	52:a51c77007319	174	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
mbed_official	52:a51c77007319	175	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
mbed_official	52:a51c77007319	176	}
mbed_official	52:a51c77007319	177	else if (TIMx == TIM8)
mbed_official	52:a51c77007319	178	{
mbed_official	52:a51c77007319	179	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
mbed_official	52:a51c77007319	180	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
mbed_official	52:a51c77007319	181	}
mbed_official	52:a51c77007319	182	else if (TIMx == TIM9)
mbed_official	52:a51c77007319	183	{
mbed_official	52:a51c77007319	184	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
mbed_official	52:a51c77007319	185	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
mbed_official	52:a51c77007319	186	}
mbed_official	52:a51c77007319	187	else if (TIMx == TIM10)
mbed_official	52:a51c77007319	188	{
mbed_official	52:a51c77007319	189	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
mbed_official	52:a51c77007319	190	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
mbed_official	52:a51c77007319	191	}
mbed_official	52:a51c77007319	192	else if (TIMx == TIM11)
mbed_official	52:a51c77007319	193	{
mbed_official	52:a51c77007319	194	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
mbed_official	52:a51c77007319	195	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
mbed_official	52:a51c77007319	196	}
mbed_official	52:a51c77007319	197	else if (TIMx == TIM12)
mbed_official	52:a51c77007319	198	{
mbed_official	52:a51c77007319	199	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
mbed_official	52:a51c77007319	200	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
mbed_official	52:a51c77007319	201	}
mbed_official	52:a51c77007319	202	else if (TIMx == TIM13)
mbed_official	52:a51c77007319	203	{
mbed_official	52:a51c77007319	204	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
mbed_official	52:a51c77007319	205	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
mbed_official	52:a51c77007319	206	}
mbed_official	52:a51c77007319	207	else if (TIMx == TIM14)
mbed_official	52:a51c77007319	208	{
mbed_official	52:a51c77007319	209	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
mbed_official	52:a51c77007319	210	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
mbed_official	52:a51c77007319	211	}
mbed_official	52:a51c77007319	212	else if (TIMx == TIM15)
mbed_official	52:a51c77007319	213	{
mbed_official	52:a51c77007319	214	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
mbed_official	52:a51c77007319	215	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
mbed_official	52:a51c77007319	216	}
mbed_official	52:a51c77007319	217	else if (TIMx == TIM16)
mbed_official	52:a51c77007319	218	{
mbed_official	52:a51c77007319	219	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
mbed_official	52:a51c77007319	220	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
mbed_official	52:a51c77007319	221	}
mbed_official	52:a51c77007319	222	else
mbed_official	52:a51c77007319	223	{
mbed_official	52:a51c77007319	224	if (TIMx == TIM17)
mbed_official	52:a51c77007319	225	{
mbed_official	52:a51c77007319	226	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
mbed_official	52:a51c77007319	227	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
mbed_official	52:a51c77007319	228	}
mbed_official	52:a51c77007319	229	}
mbed_official	52:a51c77007319	230	}
mbed_official	52:a51c77007319	231
mbed_official	52:a51c77007319	232	/**
mbed_official	52:a51c77007319	233	* @brief Initializes the TIMx Time Base Unit peripheral according to
mbed_official	52:a51c77007319	234	* the specified parameters in the TIM_TimeBaseInitStruct.
mbed_official	52:a51c77007319	235	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	236	* @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
mbed_official	52:a51c77007319	237	* structure that contains the configuration information for the
mbed_official	52:a51c77007319	238	* specified TIM peripheral.
mbed_official	52:a51c77007319	239	* @retval None
mbed_official	52:a51c77007319	240	*/
mbed_official	52:a51c77007319	241	void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
mbed_official	52:a51c77007319	242	{
mbed_official	52:a51c77007319	243	uint16_t tmpcr1 = 0;
mbed_official	52:a51c77007319	244
mbed_official	52:a51c77007319	245	/* Check the parameters */
mbed_official	52:a51c77007319	246	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	247	assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
mbed_official	52:a51c77007319	248	assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
mbed_official	52:a51c77007319	249
mbed_official	52:a51c77007319	250	tmpcr1 = TIMx->CR1;
mbed_official	52:a51c77007319	251
mbed_official	52:a51c77007319	252	if((TIMx == TIM1) \|\| (TIMx == TIM8)\|\| (TIMx == TIM2) \|\| (TIMx == TIM3)\|\|
mbed_official	52:a51c77007319	253	(TIMx == TIM4) \|\| (TIMx == TIM5))
mbed_official	52:a51c77007319	254	{
mbed_official	52:a51c77007319	255	/* Select the Counter Mode */
mbed_official	52:a51c77007319	256	tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR \| TIM_CR1_CMS)));
mbed_official	52:a51c77007319	257	tmpcr1 \|= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
mbed_official	52:a51c77007319	258	}
mbed_official	52:a51c77007319	259
mbed_official	52:a51c77007319	260	if((TIMx != TIM6) && (TIMx != TIM7))
mbed_official	52:a51c77007319	261	{
mbed_official	52:a51c77007319	262	/* Set the clock division */
mbed_official	52:a51c77007319	263	tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
mbed_official	52:a51c77007319	264	tmpcr1 \|= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
mbed_official	52:a51c77007319	265	}
mbed_official	52:a51c77007319	266
mbed_official	52:a51c77007319	267	TIMx->CR1 = tmpcr1;
mbed_official	52:a51c77007319	268
mbed_official	52:a51c77007319	269	/* Set the Autoreload value */
mbed_official	52:a51c77007319	270	TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
mbed_official	52:a51c77007319	271
mbed_official	52:a51c77007319	272	/* Set the Prescaler value */
mbed_official	52:a51c77007319	273	TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
mbed_official	52:a51c77007319	274
mbed_official	52:a51c77007319	275	if ((TIMx == TIM1) \|\| (TIMx == TIM8)\|\| (TIMx == TIM15)\|\| (TIMx == TIM16) \|\| (TIMx == TIM17))
mbed_official	52:a51c77007319	276	{
mbed_official	52:a51c77007319	277	/* Set the Repetition Counter value */
mbed_official	52:a51c77007319	278	TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
mbed_official	52:a51c77007319	279	}
mbed_official	52:a51c77007319	280
mbed_official	52:a51c77007319	281	/* Generate an update event to reload the Prescaler and the Repetition counter
mbed_official	52:a51c77007319	282	values immediately */
mbed_official	52:a51c77007319	283	TIMx->EGR = TIM_PSCReloadMode_Immediate;
mbed_official	52:a51c77007319	284	}
mbed_official	52:a51c77007319	285
mbed_official	52:a51c77007319	286	/**
mbed_official	52:a51c77007319	287	* @brief Initializes the TIMx Channel1 according to the specified
mbed_official	52:a51c77007319	288	* parameters in the TIM_OCInitStruct.
mbed_official	52:a51c77007319	289	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	290	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
mbed_official	52:a51c77007319	291	* that contains the configuration information for the specified TIM peripheral.
mbed_official	52:a51c77007319	292	* @retval None
mbed_official	52:a51c77007319	293	*/
mbed_official	52:a51c77007319	294	void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
mbed_official	52:a51c77007319	295	{
mbed_official	52:a51c77007319	296	uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
mbed_official	52:a51c77007319	297
mbed_official	52:a51c77007319	298	/* Check the parameters */
mbed_official	52:a51c77007319	299	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	300	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
mbed_official	52:a51c77007319	301	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
mbed_official	52:a51c77007319	302	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
mbed_official	52:a51c77007319	303	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	52:a51c77007319	304	TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
mbed_official	52:a51c77007319	305	/* Get the TIMx CCER register value */
mbed_official	52:a51c77007319	306	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	307	/* Get the TIMx CR2 register value */
mbed_official	52:a51c77007319	308	tmpcr2 = TIMx->CR2;
mbed_official	52:a51c77007319	309
mbed_official	52:a51c77007319	310	/* Get the TIMx CCMR1 register value */
mbed_official	52:a51c77007319	311	tmpccmrx = TIMx->CCMR1;
mbed_official	52:a51c77007319	312
mbed_official	52:a51c77007319	313	/* Reset the Output Compare Mode Bits */
mbed_official	52:a51c77007319	314	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
mbed_official	52:a51c77007319	315	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
mbed_official	52:a51c77007319	316
mbed_official	52:a51c77007319	317	/* Select the Output Compare Mode */
mbed_official	52:a51c77007319	318	tmpccmrx \|= TIM_OCInitStruct->TIM_OCMode;
mbed_official	52:a51c77007319	319
mbed_official	52:a51c77007319	320	/* Reset the Output Polarity level */
mbed_official	52:a51c77007319	321	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
mbed_official	52:a51c77007319	322	/* Set the Output Compare Polarity */
mbed_official	52:a51c77007319	323	tmpccer \|= TIM_OCInitStruct->TIM_OCPolarity;
mbed_official	52:a51c77007319	324
mbed_official	52:a51c77007319	325	/* Set the Output State */
mbed_official	52:a51c77007319	326	tmpccer \|= TIM_OCInitStruct->TIM_OutputState;
mbed_official	52:a51c77007319	327
mbed_official	52:a51c77007319	328	if((TIMx == TIM1) \|\| (TIMx == TIM8)\|\| (TIMx == TIM15)\|\|
mbed_official	52:a51c77007319	329	(TIMx == TIM16)\|\| (TIMx == TIM17))
mbed_official	52:a51c77007319	330	{
mbed_official	52:a51c77007319	331	assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
mbed_official	52:a51c77007319	332	assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
mbed_official	52:a51c77007319	333	assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
mbed_official	52:a51c77007319	334	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
mbed_official	52:a51c77007319	335
mbed_official	52:a51c77007319	336	/* Reset the Output N Polarity level */
mbed_official	52:a51c77007319	337	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
mbed_official	52:a51c77007319	338	/* Set the Output N Polarity */
mbed_official	52:a51c77007319	339	tmpccer \|= TIM_OCInitStruct->TIM_OCNPolarity;
mbed_official	52:a51c77007319	340
mbed_official	52:a51c77007319	341	/* Reset the Output N State */
mbed_official	52:a51c77007319	342	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
mbed_official	52:a51c77007319	343	/* Set the Output N State */
mbed_official	52:a51c77007319	344	tmpccer \|= TIM_OCInitStruct->TIM_OutputNState;
mbed_official	52:a51c77007319	345
mbed_official	52:a51c77007319	346	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	52:a51c77007319	347	tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
mbed_official	52:a51c77007319	348	tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
mbed_official	52:a51c77007319	349
mbed_official	52:a51c77007319	350	/* Set the Output Idle state */
mbed_official	52:a51c77007319	351	tmpcr2 \|= TIM_OCInitStruct->TIM_OCIdleState;
mbed_official	52:a51c77007319	352	/* Set the Output N Idle state */
mbed_official	52:a51c77007319	353	tmpcr2 \|= TIM_OCInitStruct->TIM_OCNIdleState;
mbed_official	52:a51c77007319	354	}
mbed_official	52:a51c77007319	355	/* Write to TIMx CR2 */
mbed_official	52:a51c77007319	356	TIMx->CR2 = tmpcr2;
mbed_official	52:a51c77007319	357
mbed_official	52:a51c77007319	358	/* Write to TIMx CCMR1 */
mbed_official	52:a51c77007319	359	TIMx->CCMR1 = tmpccmrx;
mbed_official	52:a51c77007319	360
mbed_official	52:a51c77007319	361	/* Set the Capture Compare Register value */
mbed_official	52:a51c77007319	362	TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
mbed_official	52:a51c77007319	363
mbed_official	52:a51c77007319	364	/* Write to TIMx CCER */
mbed_official	52:a51c77007319	365	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	366	}
mbed_official	52:a51c77007319	367
mbed_official	52:a51c77007319	368	/**
mbed_official	52:a51c77007319	369	* @brief Initializes the TIMx Channel2 according to the specified
mbed_official	52:a51c77007319	370	* parameters in the TIM_OCInitStruct.
mbed_official	52:a51c77007319	371	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
mbed_official	52:a51c77007319	372	* the TIM peripheral.
mbed_official	52:a51c77007319	373	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
mbed_official	52:a51c77007319	374	* that contains the configuration information for the specified TIM peripheral.
mbed_official	52:a51c77007319	375	* @retval None
mbed_official	52:a51c77007319	376	*/
mbed_official	52:a51c77007319	377	void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
mbed_official	52:a51c77007319	378	{
mbed_official	52:a51c77007319	379	uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
mbed_official	52:a51c77007319	380
mbed_official	52:a51c77007319	381	/* Check the parameters */
mbed_official	52:a51c77007319	382	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	383	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
mbed_official	52:a51c77007319	384	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
mbed_official	52:a51c77007319	385	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
mbed_official	52:a51c77007319	386	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	52:a51c77007319	387	TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
mbed_official	52:a51c77007319	388
mbed_official	52:a51c77007319	389	/* Get the TIMx CCER register value */
mbed_official	52:a51c77007319	390	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	391	/* Get the TIMx CR2 register value */
mbed_official	52:a51c77007319	392	tmpcr2 = TIMx->CR2;
mbed_official	52:a51c77007319	393
mbed_official	52:a51c77007319	394	/* Get the TIMx CCMR1 register value */
mbed_official	52:a51c77007319	395	tmpccmrx = TIMx->CCMR1;
mbed_official	52:a51c77007319	396
mbed_official	52:a51c77007319	397	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	52:a51c77007319	398	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
mbed_official	52:a51c77007319	399	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
mbed_official	52:a51c77007319	400
mbed_official	52:a51c77007319	401	/* Select the Output Compare Mode */
mbed_official	52:a51c77007319	402	tmpccmrx \|= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
mbed_official	52:a51c77007319	403
mbed_official	52:a51c77007319	404	/* Reset the Output Polarity level */
mbed_official	52:a51c77007319	405	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
mbed_official	52:a51c77007319	406	/* Set the Output Compare Polarity */
mbed_official	52:a51c77007319	407	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
mbed_official	52:a51c77007319	408
mbed_official	52:a51c77007319	409	/* Set the Output State */
mbed_official	52:a51c77007319	410	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
mbed_official	52:a51c77007319	411
mbed_official	52:a51c77007319	412	if((TIMx == TIM1) \|\| (TIMx == TIM8))
mbed_official	52:a51c77007319	413	{
mbed_official	52:a51c77007319	414	assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
mbed_official	52:a51c77007319	415	assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
mbed_official	52:a51c77007319	416	assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
mbed_official	52:a51c77007319	417	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
mbed_official	52:a51c77007319	418
mbed_official	52:a51c77007319	419	/* Reset the Output N Polarity level */
mbed_official	52:a51c77007319	420	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
mbed_official	52:a51c77007319	421	/* Set the Output N Polarity */
mbed_official	52:a51c77007319	422	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
mbed_official	52:a51c77007319	423
mbed_official	52:a51c77007319	424	/* Reset the Output N State */
mbed_official	52:a51c77007319	425	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
mbed_official	52:a51c77007319	426	/* Set the Output N State */
mbed_official	52:a51c77007319	427	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
mbed_official	52:a51c77007319	428
mbed_official	52:a51c77007319	429	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	52:a51c77007319	430	tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
mbed_official	52:a51c77007319	431	tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
mbed_official	52:a51c77007319	432
mbed_official	52:a51c77007319	433	/* Set the Output Idle state */
mbed_official	52:a51c77007319	434	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
mbed_official	52:a51c77007319	435	/* Set the Output N Idle state */
mbed_official	52:a51c77007319	436	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
mbed_official	52:a51c77007319	437	}
mbed_official	52:a51c77007319	438	/* Write to TIMx CR2 */
mbed_official	52:a51c77007319	439	TIMx->CR2 = tmpcr2;
mbed_official	52:a51c77007319	440
mbed_official	52:a51c77007319	441	/* Write to TIMx CCMR1 */
mbed_official	52:a51c77007319	442	TIMx->CCMR1 = tmpccmrx;
mbed_official	52:a51c77007319	443
mbed_official	52:a51c77007319	444	/* Set the Capture Compare Register value */
mbed_official	52:a51c77007319	445	TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
mbed_official	52:a51c77007319	446
mbed_official	52:a51c77007319	447	/* Write to TIMx CCER */
mbed_official	52:a51c77007319	448	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	449	}
mbed_official	52:a51c77007319	450
mbed_official	52:a51c77007319	451	/**
mbed_official	52:a51c77007319	452	* @brief Initializes the TIMx Channel3 according to the specified
mbed_official	52:a51c77007319	453	* parameters in the TIM_OCInitStruct.
mbed_official	52:a51c77007319	454	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	455	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
mbed_official	52:a51c77007319	456	* that contains the configuration information for the specified TIM peripheral.
mbed_official	52:a51c77007319	457	* @retval None
mbed_official	52:a51c77007319	458	*/
mbed_official	52:a51c77007319	459	void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
mbed_official	52:a51c77007319	460	{
mbed_official	52:a51c77007319	461	uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
mbed_official	52:a51c77007319	462
mbed_official	52:a51c77007319	463	/* Check the parameters */
mbed_official	52:a51c77007319	464	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	465	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
mbed_official	52:a51c77007319	466	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
mbed_official	52:a51c77007319	467	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
mbed_official	52:a51c77007319	468	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	52:a51c77007319	469	TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
mbed_official	52:a51c77007319	470
mbed_official	52:a51c77007319	471	/* Get the TIMx CCER register value */
mbed_official	52:a51c77007319	472	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	473	/* Get the TIMx CR2 register value */
mbed_official	52:a51c77007319	474	tmpcr2 = TIMx->CR2;
mbed_official	52:a51c77007319	475
mbed_official	52:a51c77007319	476	/* Get the TIMx CCMR2 register value */
mbed_official	52:a51c77007319	477	tmpccmrx = TIMx->CCMR2;
mbed_official	52:a51c77007319	478
mbed_official	52:a51c77007319	479	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	52:a51c77007319	480	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
mbed_official	52:a51c77007319	481	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
mbed_official	52:a51c77007319	482	/* Select the Output Compare Mode */
mbed_official	52:a51c77007319	483	tmpccmrx \|= TIM_OCInitStruct->TIM_OCMode;
mbed_official	52:a51c77007319	484
mbed_official	52:a51c77007319	485	/* Reset the Output Polarity level */
mbed_official	52:a51c77007319	486	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
mbed_official	52:a51c77007319	487	/* Set the Output Compare Polarity */
mbed_official	52:a51c77007319	488	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
mbed_official	52:a51c77007319	489
mbed_official	52:a51c77007319	490	/* Set the Output State */
mbed_official	52:a51c77007319	491	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
mbed_official	52:a51c77007319	492
mbed_official	52:a51c77007319	493	if((TIMx == TIM1) \|\| (TIMx == TIM8))
mbed_official	52:a51c77007319	494	{
mbed_official	52:a51c77007319	495	assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
mbed_official	52:a51c77007319	496	assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
mbed_official	52:a51c77007319	497	assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
mbed_official	52:a51c77007319	498	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
mbed_official	52:a51c77007319	499
mbed_official	52:a51c77007319	500	/* Reset the Output N Polarity level */
mbed_official	52:a51c77007319	501	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
mbed_official	52:a51c77007319	502	/* Set the Output N Polarity */
mbed_official	52:a51c77007319	503	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
mbed_official	52:a51c77007319	504	/* Reset the Output N State */
mbed_official	52:a51c77007319	505	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
mbed_official	52:a51c77007319	506
mbed_official	52:a51c77007319	507	/* Set the Output N State */
mbed_official	52:a51c77007319	508	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
mbed_official	52:a51c77007319	509	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	52:a51c77007319	510	tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
mbed_official	52:a51c77007319	511	tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
mbed_official	52:a51c77007319	512	/* Set the Output Idle state */
mbed_official	52:a51c77007319	513	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
mbed_official	52:a51c77007319	514	/* Set the Output N Idle state */
mbed_official	52:a51c77007319	515	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
mbed_official	52:a51c77007319	516	}
mbed_official	52:a51c77007319	517	/* Write to TIMx CR2 */
mbed_official	52:a51c77007319	518	TIMx->CR2 = tmpcr2;
mbed_official	52:a51c77007319	519
mbed_official	52:a51c77007319	520	/* Write to TIMx CCMR2 */
mbed_official	52:a51c77007319	521	TIMx->CCMR2 = tmpccmrx;
mbed_official	52:a51c77007319	522
mbed_official	52:a51c77007319	523	/* Set the Capture Compare Register value */
mbed_official	52:a51c77007319	524	TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
mbed_official	52:a51c77007319	525
mbed_official	52:a51c77007319	526	/* Write to TIMx CCER */
mbed_official	52:a51c77007319	527	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	528	}
mbed_official	52:a51c77007319	529
mbed_official	52:a51c77007319	530	/**
mbed_official	52:a51c77007319	531	* @brief Initializes the TIMx Channel4 according to the specified
mbed_official	52:a51c77007319	532	* parameters in the TIM_OCInitStruct.
mbed_official	52:a51c77007319	533	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	534	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
mbed_official	52:a51c77007319	535	* that contains the configuration information for the specified TIM peripheral.
mbed_official	52:a51c77007319	536	* @retval None
mbed_official	52:a51c77007319	537	*/
mbed_official	52:a51c77007319	538	void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
mbed_official	52:a51c77007319	539	{
mbed_official	52:a51c77007319	540	uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
mbed_official	52:a51c77007319	541
mbed_official	52:a51c77007319	542	/* Check the parameters */
mbed_official	52:a51c77007319	543	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	544	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
mbed_official	52:a51c77007319	545	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
mbed_official	52:a51c77007319	546	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
mbed_official	52:a51c77007319	547	/* Disable the Channel 2: Reset the CC4E Bit */
mbed_official	52:a51c77007319	548	TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
mbed_official	52:a51c77007319	549
mbed_official	52:a51c77007319	550	/* Get the TIMx CCER register value */
mbed_official	52:a51c77007319	551	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	552	/* Get the TIMx CR2 register value */
mbed_official	52:a51c77007319	553	tmpcr2 = TIMx->CR2;
mbed_official	52:a51c77007319	554
mbed_official	52:a51c77007319	555	/* Get the TIMx CCMR2 register value */
mbed_official	52:a51c77007319	556	tmpccmrx = TIMx->CCMR2;
mbed_official	52:a51c77007319	557
mbed_official	52:a51c77007319	558	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	52:a51c77007319	559	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
mbed_official	52:a51c77007319	560	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
mbed_official	52:a51c77007319	561
mbed_official	52:a51c77007319	562	/* Select the Output Compare Mode */
mbed_official	52:a51c77007319	563	tmpccmrx \|= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
mbed_official	52:a51c77007319	564
mbed_official	52:a51c77007319	565	/* Reset the Output Polarity level */
mbed_official	52:a51c77007319	566	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
mbed_official	52:a51c77007319	567	/* Set the Output Compare Polarity */
mbed_official	52:a51c77007319	568	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
mbed_official	52:a51c77007319	569
mbed_official	52:a51c77007319	570	/* Set the Output State */
mbed_official	52:a51c77007319	571	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
mbed_official	52:a51c77007319	572
mbed_official	52:a51c77007319	573	if((TIMx == TIM1) \|\| (TIMx == TIM8))
mbed_official	52:a51c77007319	574	{
mbed_official	52:a51c77007319	575	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
mbed_official	52:a51c77007319	576	/* Reset the Output Compare IDLE State */
mbed_official	52:a51c77007319	577	tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
mbed_official	52:a51c77007319	578	/* Set the Output Idle state */
mbed_official	52:a51c77007319	579	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
mbed_official	52:a51c77007319	580	}
mbed_official	52:a51c77007319	581	/* Write to TIMx CR2 */
mbed_official	52:a51c77007319	582	TIMx->CR2 = tmpcr2;
mbed_official	52:a51c77007319	583
mbed_official	52:a51c77007319	584	/* Write to TIMx CCMR2 */
mbed_official	52:a51c77007319	585	TIMx->CCMR2 = tmpccmrx;
mbed_official	52:a51c77007319	586
mbed_official	52:a51c77007319	587	/* Set the Capture Compare Register value */
mbed_official	52:a51c77007319	588	TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
mbed_official	52:a51c77007319	589
mbed_official	52:a51c77007319	590	/* Write to TIMx CCER */
mbed_official	52:a51c77007319	591	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	592	}
mbed_official	52:a51c77007319	593
mbed_official	52:a51c77007319	594	/**
mbed_official	52:a51c77007319	595	* @brief Initializes the TIM peripheral according to the specified
mbed_official	52:a51c77007319	596	* parameters in the TIM_ICInitStruct.
mbed_official	52:a51c77007319	597	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	598	* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
mbed_official	52:a51c77007319	599	* that contains the configuration information for the specified TIM peripheral.
mbed_official	52:a51c77007319	600	* @retval None
mbed_official	52:a51c77007319	601	*/
mbed_official	52:a51c77007319	602	void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
mbed_official	52:a51c77007319	603	{
mbed_official	52:a51c77007319	604	/* Check the parameters */
mbed_official	52:a51c77007319	605	assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
mbed_official	52:a51c77007319	606	assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
mbed_official	52:a51c77007319	607	assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
mbed_official	52:a51c77007319	608	assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
mbed_official	52:a51c77007319	609
mbed_official	52:a51c77007319	610	if((TIMx == TIM1) \|\| (TIMx == TIM8) \|\| (TIMx == TIM2) \|\| (TIMx == TIM3) \|\|
mbed_official	52:a51c77007319	611	(TIMx == TIM4) \|\|(TIMx == TIM5))
mbed_official	52:a51c77007319	612	{
mbed_official	52:a51c77007319	613	assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
mbed_official	52:a51c77007319	614	}
mbed_official	52:a51c77007319	615	else
mbed_official	52:a51c77007319	616	{
mbed_official	52:a51c77007319	617	assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
mbed_official	52:a51c77007319	618	}
mbed_official	52:a51c77007319	619	if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
mbed_official	52:a51c77007319	620	{
mbed_official	52:a51c77007319	621	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	622	/* TI1 Configuration */
mbed_official	52:a51c77007319	623	TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
mbed_official	52:a51c77007319	624	TIM_ICInitStruct->TIM_ICSelection,
mbed_official	52:a51c77007319	625	TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	626	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	627	TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	628	}
mbed_official	52:a51c77007319	629	else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
mbed_official	52:a51c77007319	630	{
mbed_official	52:a51c77007319	631	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	632	/* TI2 Configuration */
mbed_official	52:a51c77007319	633	TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
mbed_official	52:a51c77007319	634	TIM_ICInitStruct->TIM_ICSelection,
mbed_official	52:a51c77007319	635	TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	636	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	637	TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	638	}
mbed_official	52:a51c77007319	639	else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
mbed_official	52:a51c77007319	640	{
mbed_official	52:a51c77007319	641	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	642	/* TI3 Configuration */
mbed_official	52:a51c77007319	643	TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
mbed_official	52:a51c77007319	644	TIM_ICInitStruct->TIM_ICSelection,
mbed_official	52:a51c77007319	645	TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	646	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	647	TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	648	}
mbed_official	52:a51c77007319	649	else
mbed_official	52:a51c77007319	650	{
mbed_official	52:a51c77007319	651	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	652	/* TI4 Configuration */
mbed_official	52:a51c77007319	653	TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
mbed_official	52:a51c77007319	654	TIM_ICInitStruct->TIM_ICSelection,
mbed_official	52:a51c77007319	655	TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	656	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	657	TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	658	}
mbed_official	52:a51c77007319	659	}
mbed_official	52:a51c77007319	660
mbed_official	52:a51c77007319	661	/**
mbed_official	52:a51c77007319	662	* @brief Configures the TIM peripheral according to the specified
mbed_official	52:a51c77007319	663	* parameters in the TIM_ICInitStruct to measure an external PWM signal.
mbed_official	52:a51c77007319	664	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	665	* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
mbed_official	52:a51c77007319	666	* that contains the configuration information for the specified TIM peripheral.
mbed_official	52:a51c77007319	667	* @retval None
mbed_official	52:a51c77007319	668	*/
mbed_official	52:a51c77007319	669	void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
mbed_official	52:a51c77007319	670	{
mbed_official	52:a51c77007319	671	uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
mbed_official	52:a51c77007319	672	uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
mbed_official	52:a51c77007319	673	/* Check the parameters */
mbed_official	52:a51c77007319	674	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	675	/* Select the Opposite Input Polarity */
mbed_official	52:a51c77007319	676	if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
mbed_official	52:a51c77007319	677	{
mbed_official	52:a51c77007319	678	icoppositepolarity = TIM_ICPolarity_Falling;
mbed_official	52:a51c77007319	679	}
mbed_official	52:a51c77007319	680	else
mbed_official	52:a51c77007319	681	{
mbed_official	52:a51c77007319	682	icoppositepolarity = TIM_ICPolarity_Rising;
mbed_official	52:a51c77007319	683	}
mbed_official	52:a51c77007319	684	/* Select the Opposite Input */
mbed_official	52:a51c77007319	685	if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
mbed_official	52:a51c77007319	686	{
mbed_official	52:a51c77007319	687	icoppositeselection = TIM_ICSelection_IndirectTI;
mbed_official	52:a51c77007319	688	}
mbed_official	52:a51c77007319	689	else
mbed_official	52:a51c77007319	690	{
mbed_official	52:a51c77007319	691	icoppositeselection = TIM_ICSelection_DirectTI;
mbed_official	52:a51c77007319	692	}
mbed_official	52:a51c77007319	693	if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
mbed_official	52:a51c77007319	694	{
mbed_official	52:a51c77007319	695	/* TI1 Configuration */
mbed_official	52:a51c77007319	696	TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
mbed_official	52:a51c77007319	697	TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	698	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	699	TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	700	/* TI2 Configuration */
mbed_official	52:a51c77007319	701	TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	702	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	703	TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	704	}
mbed_official	52:a51c77007319	705	else
mbed_official	52:a51c77007319	706	{
mbed_official	52:a51c77007319	707	/* TI2 Configuration */
mbed_official	52:a51c77007319	708	TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
mbed_official	52:a51c77007319	709	TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	710	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	711	TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	712	/* TI1 Configuration */
mbed_official	52:a51c77007319	713	TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	714	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	715	TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	716	}
mbed_official	52:a51c77007319	717	}
mbed_official	52:a51c77007319	718
mbed_official	52:a51c77007319	719	/**
mbed_official	52:a51c77007319	720	* @brief Configures the: Break feature, dead time, Lock level, the OSSI,
mbed_official	52:a51c77007319	721	* the OSSR State and the AOE(automatic output enable).
mbed_official	52:a51c77007319	722	* @param TIMx: where x can be 1 or 8 to select the TIM
mbed_official	52:a51c77007319	723	* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
mbed_official	52:a51c77007319	724	* contains the BDTR Register configuration information for the TIM peripheral.
mbed_official	52:a51c77007319	725	* @retval None
mbed_official	52:a51c77007319	726	*/
mbed_official	52:a51c77007319	727	void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
mbed_official	52:a51c77007319	728	{
mbed_official	52:a51c77007319	729	/* Check the parameters */
mbed_official	52:a51c77007319	730	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
mbed_official	52:a51c77007319	731	assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
mbed_official	52:a51c77007319	732	assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
mbed_official	52:a51c77007319	733	assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
mbed_official	52:a51c77007319	734	assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
mbed_official	52:a51c77007319	735	assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
mbed_official	52:a51c77007319	736	assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
mbed_official	52:a51c77007319	737	/* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
mbed_official	52:a51c77007319	738	the OSSI State, the dead time value and the Automatic Output Enable Bit */
mbed_official	52:a51c77007319	739	TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState \| TIM_BDTRInitStruct->TIM_OSSIState \|
mbed_official	52:a51c77007319	740	TIM_BDTRInitStruct->TIM_LOCKLevel \| TIM_BDTRInitStruct->TIM_DeadTime \|
mbed_official	52:a51c77007319	741	TIM_BDTRInitStruct->TIM_Break \| TIM_BDTRInitStruct->TIM_BreakPolarity \|
mbed_official	52:a51c77007319	742	TIM_BDTRInitStruct->TIM_AutomaticOutput;
mbed_official	52:a51c77007319	743	}
mbed_official	52:a51c77007319	744
mbed_official	52:a51c77007319	745	/**
mbed_official	52:a51c77007319	746	* @brief Fills each TIM_TimeBaseInitStruct member with its default value.
mbed_official	52:a51c77007319	747	* @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
mbed_official	52:a51c77007319	748	* structure which will be initialized.
mbed_official	52:a51c77007319	749	* @retval None
mbed_official	52:a51c77007319	750	*/
mbed_official	52:a51c77007319	751	void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
mbed_official	52:a51c77007319	752	{
mbed_official	52:a51c77007319	753	/* Set the default configuration */
mbed_official	52:a51c77007319	754	TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
mbed_official	52:a51c77007319	755	TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
mbed_official	52:a51c77007319	756	TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
mbed_official	52:a51c77007319	757	TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
mbed_official	52:a51c77007319	758	TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
mbed_official	52:a51c77007319	759	}
mbed_official	52:a51c77007319	760
mbed_official	52:a51c77007319	761	/**
mbed_official	52:a51c77007319	762	* @brief Fills each TIM_OCInitStruct member with its default value.
mbed_official	52:a51c77007319	763	* @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
mbed_official	52:a51c77007319	764	* be initialized.
mbed_official	52:a51c77007319	765	* @retval None
mbed_official	52:a51c77007319	766	*/
mbed_official	52:a51c77007319	767	void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
mbed_official	52:a51c77007319	768	{
mbed_official	52:a51c77007319	769	/* Set the default configuration */
mbed_official	52:a51c77007319	770	TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
mbed_official	52:a51c77007319	771	TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
mbed_official	52:a51c77007319	772	TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
mbed_official	52:a51c77007319	773	TIM_OCInitStruct->TIM_Pulse = 0x0000;
mbed_official	52:a51c77007319	774	TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
mbed_official	52:a51c77007319	775	TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
mbed_official	52:a51c77007319	776	TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
mbed_official	52:a51c77007319	777	TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
mbed_official	52:a51c77007319	778	}
mbed_official	52:a51c77007319	779
mbed_official	52:a51c77007319	780	/**
mbed_official	52:a51c77007319	781	* @brief Fills each TIM_ICInitStruct member with its default value.
mbed_official	52:a51c77007319	782	* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
mbed_official	52:a51c77007319	783	* be initialized.
mbed_official	52:a51c77007319	784	* @retval None
mbed_official	52:a51c77007319	785	*/
mbed_official	52:a51c77007319	786	void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
mbed_official	52:a51c77007319	787	{
mbed_official	52:a51c77007319	788	/* Set the default configuration */
mbed_official	52:a51c77007319	789	TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
mbed_official	52:a51c77007319	790	TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
mbed_official	52:a51c77007319	791	TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
mbed_official	52:a51c77007319	792	TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
mbed_official	52:a51c77007319	793	TIM_ICInitStruct->TIM_ICFilter = 0x00;
mbed_official	52:a51c77007319	794	}
mbed_official	52:a51c77007319	795
mbed_official	52:a51c77007319	796	/**
mbed_official	52:a51c77007319	797	* @brief Fills each TIM_BDTRInitStruct member with its default value.
mbed_official	52:a51c77007319	798	* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
mbed_official	52:a51c77007319	799	* will be initialized.
mbed_official	52:a51c77007319	800	* @retval None
mbed_official	52:a51c77007319	801	*/
mbed_official	52:a51c77007319	802	void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
mbed_official	52:a51c77007319	803	{
mbed_official	52:a51c77007319	804	/* Set the default configuration */
mbed_official	52:a51c77007319	805	TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
mbed_official	52:a51c77007319	806	TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
mbed_official	52:a51c77007319	807	TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
mbed_official	52:a51c77007319	808	TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
mbed_official	52:a51c77007319	809	TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
mbed_official	52:a51c77007319	810	TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
mbed_official	52:a51c77007319	811	TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
mbed_official	52:a51c77007319	812	}
mbed_official	52:a51c77007319	813
mbed_official	52:a51c77007319	814	/**
mbed_official	52:a51c77007319	815	* @brief Enables or disables the specified TIM peripheral.
mbed_official	52:a51c77007319	816	* @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
mbed_official	52:a51c77007319	817	* @param NewState: new state of the TIMx peripheral.
mbed_official	52:a51c77007319	818	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	819	* @retval None
mbed_official	52:a51c77007319	820	*/
mbed_official	52:a51c77007319	821	void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	822	{
mbed_official	52:a51c77007319	823	/* Check the parameters */
mbed_official	52:a51c77007319	824	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	825	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	826
mbed_official	52:a51c77007319	827	if (NewState != DISABLE)
mbed_official	52:a51c77007319	828	{
mbed_official	52:a51c77007319	829	/* Enable the TIM Counter */
mbed_official	52:a51c77007319	830	TIMx->CR1 \|= TIM_CR1_CEN;
mbed_official	52:a51c77007319	831	}
mbed_official	52:a51c77007319	832	else
mbed_official	52:a51c77007319	833	{
mbed_official	52:a51c77007319	834	/* Disable the TIM Counter */
mbed_official	52:a51c77007319	835	TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
mbed_official	52:a51c77007319	836	}
mbed_official	52:a51c77007319	837	}
mbed_official	52:a51c77007319	838
mbed_official	52:a51c77007319	839	/**
mbed_official	52:a51c77007319	840	* @brief Enables or disables the TIM peripheral Main Outputs.
mbed_official	52:a51c77007319	841	* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
mbed_official	52:a51c77007319	842	* @param NewState: new state of the TIM peripheral Main Outputs.
mbed_official	52:a51c77007319	843	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	844	* @retval None
mbed_official	52:a51c77007319	845	*/
mbed_official	52:a51c77007319	846	void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	847	{
mbed_official	52:a51c77007319	848	/* Check the parameters */
mbed_official	52:a51c77007319	849	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
mbed_official	52:a51c77007319	850	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	851	if (NewState != DISABLE)
mbed_official	52:a51c77007319	852	{
mbed_official	52:a51c77007319	853	/* Enable the TIM Main Output */
mbed_official	52:a51c77007319	854	TIMx->BDTR \|= TIM_BDTR_MOE;
mbed_official	52:a51c77007319	855	}
mbed_official	52:a51c77007319	856	else
mbed_official	52:a51c77007319	857	{
mbed_official	52:a51c77007319	858	/* Disable the TIM Main Output */
mbed_official	52:a51c77007319	859	TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
mbed_official	52:a51c77007319	860	}
mbed_official	52:a51c77007319	861	}
mbed_official	52:a51c77007319	862
mbed_official	52:a51c77007319	863	/**
mbed_official	52:a51c77007319	864	* @brief Enables or disables the specified TIM interrupts.
mbed_official	52:a51c77007319	865	* @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
mbed_official	52:a51c77007319	866	* @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
mbed_official	52:a51c77007319	867	* This parameter can be any combination of the following values:
mbed_official	52:a51c77007319	868	* @arg TIM_IT_Update: TIM update Interrupt source
mbed_official	52:a51c77007319	869	* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
mbed_official	52:a51c77007319	870	* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
mbed_official	52:a51c77007319	871	* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
mbed_official	52:a51c77007319	872	* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
mbed_official	52:a51c77007319	873	* @arg TIM_IT_COM: TIM Commutation Interrupt source
mbed_official	52:a51c77007319	874	* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
mbed_official	52:a51c77007319	875	* @arg TIM_IT_Break: TIM Break Interrupt source
mbed_official	52:a51c77007319	876	* @note
mbed_official	52:a51c77007319	877	* - TIM6 and TIM7 can only generate an update interrupt.
mbed_official	52:a51c77007319	878	* - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
mbed_official	52:a51c77007319	879	* TIM_IT_CC2 or TIM_IT_Trigger.
mbed_official	52:a51c77007319	880	* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
mbed_official	52:a51c77007319	881	* - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
mbed_official	52:a51c77007319	882	* - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
mbed_official	52:a51c77007319	883	* @param NewState: new state of the TIM interrupts.
mbed_official	52:a51c77007319	884	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	885	* @retval None
mbed_official	52:a51c77007319	886	*/
mbed_official	52:a51c77007319	887	void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
mbed_official	52:a51c77007319	888	{
mbed_official	52:a51c77007319	889	/* Check the parameters */
mbed_official	52:a51c77007319	890	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	891	assert_param(IS_TIM_IT(TIM_IT));
mbed_official	52:a51c77007319	892	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	893
mbed_official	52:a51c77007319	894	if (NewState != DISABLE)
mbed_official	52:a51c77007319	895	{
mbed_official	52:a51c77007319	896	/* Enable the Interrupt sources */
mbed_official	52:a51c77007319	897	TIMx->DIER \|= TIM_IT;
mbed_official	52:a51c77007319	898	}
mbed_official	52:a51c77007319	899	else
mbed_official	52:a51c77007319	900	{
mbed_official	52:a51c77007319	901	/* Disable the Interrupt sources */
mbed_official	52:a51c77007319	902	TIMx->DIER &= (uint16_t)~TIM_IT;
mbed_official	52:a51c77007319	903	}
mbed_official	52:a51c77007319	904	}
mbed_official	52:a51c77007319	905
mbed_official	52:a51c77007319	906	/**
mbed_official	52:a51c77007319	907	* @brief Configures the TIMx event to be generate by software.
mbed_official	52:a51c77007319	908	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	909	* @param TIM_EventSource: specifies the event source.
mbed_official	52:a51c77007319	910	* This parameter can be one or more of the following values:
mbed_official	52:a51c77007319	911	* @arg TIM_EventSource_Update: Timer update Event source
mbed_official	52:a51c77007319	912	* @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
mbed_official	52:a51c77007319	913	* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
mbed_official	52:a51c77007319	914	* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
mbed_official	52:a51c77007319	915	* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
mbed_official	52:a51c77007319	916	* @arg TIM_EventSource_COM: Timer COM event source
mbed_official	52:a51c77007319	917	* @arg TIM_EventSource_Trigger: Timer Trigger Event source
mbed_official	52:a51c77007319	918	* @arg TIM_EventSource_Break: Timer Break event source
mbed_official	52:a51c77007319	919	* @note
mbed_official	52:a51c77007319	920	* - TIM6 and TIM7 can only generate an update event.
mbed_official	52:a51c77007319	921	* - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
mbed_official	52:a51c77007319	922	* @retval None
mbed_official	52:a51c77007319	923	*/
mbed_official	52:a51c77007319	924	void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
mbed_official	52:a51c77007319	925	{
mbed_official	52:a51c77007319	926	/* Check the parameters */
mbed_official	52:a51c77007319	927	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	928	assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
mbed_official	52:a51c77007319	929
mbed_official	52:a51c77007319	930	/* Set the event sources */
mbed_official	52:a51c77007319	931	TIMx->EGR = TIM_EventSource;
mbed_official	52:a51c77007319	932	}
mbed_official	52:a51c77007319	933
mbed_official	52:a51c77007319	934	/**
mbed_official	52:a51c77007319	935	* @brief Configures the TIMx's DMA interface.
mbed_official	52:a51c77007319	936	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
mbed_official	52:a51c77007319	937	* the TIM peripheral.
mbed_official	52:a51c77007319	938	* @param TIM_DMABase: DMA Base address.
mbed_official	52:a51c77007319	939	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	940	* @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
mbed_official	52:a51c77007319	941	* TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
mbed_official	52:a51c77007319	942	* TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
mbed_official	52:a51c77007319	943	* TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
mbed_official	52:a51c77007319	944	* TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
mbed_official	52:a51c77007319	945	* TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
mbed_official	52:a51c77007319	946	* TIM_DMABase_DCR.
mbed_official	52:a51c77007319	947	* @param TIM_DMABurstLength: DMA Burst length.
mbed_official	52:a51c77007319	948	* This parameter can be one value between:
mbed_official	52:a51c77007319	949	* TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
mbed_official	52:a51c77007319	950	* @retval None
mbed_official	52:a51c77007319	951	*/
mbed_official	52:a51c77007319	952	void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
mbed_official	52:a51c77007319	953	{
mbed_official	52:a51c77007319	954	/* Check the parameters */
mbed_official	52:a51c77007319	955	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
mbed_official	52:a51c77007319	956	assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
mbed_official	52:a51c77007319	957	assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
mbed_official	52:a51c77007319	958	/* Set the DMA Base and the DMA Burst Length */
mbed_official	52:a51c77007319	959	TIMx->DCR = TIM_DMABase \| TIM_DMABurstLength;
mbed_official	52:a51c77007319	960	}
mbed_official	52:a51c77007319	961
mbed_official	52:a51c77007319	962	/**
mbed_official	52:a51c77007319	963	* @brief Enables or disables the TIMx's DMA Requests.
mbed_official	52:a51c77007319	964	* @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17
mbed_official	52:a51c77007319	965	* to select the TIM peripheral.
mbed_official	52:a51c77007319	966	* @param TIM_DMASource: specifies the DMA Request sources.
mbed_official	52:a51c77007319	967	* This parameter can be any combination of the following values:
mbed_official	52:a51c77007319	968	* @arg TIM_DMA_Update: TIM update Interrupt source
mbed_official	52:a51c77007319	969	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official	52:a51c77007319	970	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official	52:a51c77007319	971	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official	52:a51c77007319	972	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official	52:a51c77007319	973	* @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official	52:a51c77007319	974	* @arg TIM_DMA_Trigger: TIM Trigger DMA source
mbed_official	52:a51c77007319	975	* @param NewState: new state of the DMA Request sources.
mbed_official	52:a51c77007319	976	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	977	* @retval None
mbed_official	52:a51c77007319	978	*/
mbed_official	52:a51c77007319	979	void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
mbed_official	52:a51c77007319	980	{
mbed_official	52:a51c77007319	981	/* Check the parameters */
mbed_official	52:a51c77007319	982	assert_param(IS_TIM_LIST9_PERIPH(TIMx));
mbed_official	52:a51c77007319	983	assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
mbed_official	52:a51c77007319	984	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	985
mbed_official	52:a51c77007319	986	if (NewState != DISABLE)
mbed_official	52:a51c77007319	987	{
mbed_official	52:a51c77007319	988	/* Enable the DMA sources */
mbed_official	52:a51c77007319	989	TIMx->DIER \|= TIM_DMASource;
mbed_official	52:a51c77007319	990	}
mbed_official	52:a51c77007319	991	else
mbed_official	52:a51c77007319	992	{
mbed_official	52:a51c77007319	993	/* Disable the DMA sources */
mbed_official	52:a51c77007319	994	TIMx->DIER &= (uint16_t)~TIM_DMASource;
mbed_official	52:a51c77007319	995	}
mbed_official	52:a51c77007319	996	}
mbed_official	52:a51c77007319	997
mbed_official	52:a51c77007319	998	/**
mbed_official	52:a51c77007319	999	* @brief Configures the TIMx internal Clock
mbed_official	52:a51c77007319	1000	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15
mbed_official	52:a51c77007319	1001	* to select the TIM peripheral.
mbed_official	52:a51c77007319	1002	* @retval None
mbed_official	52:a51c77007319	1003	*/
mbed_official	52:a51c77007319	1004	void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	1005	{
mbed_official	52:a51c77007319	1006	/* Check the parameters */
mbed_official	52:a51c77007319	1007	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1008	/* Disable slave mode to clock the prescaler directly with the internal clock */
mbed_official	52:a51c77007319	1009	TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
mbed_official	52:a51c77007319	1010	}
mbed_official	52:a51c77007319	1011
mbed_official	52:a51c77007319	1012	/**
mbed_official	52:a51c77007319	1013	* @brief Configures the TIMx Internal Trigger as External Clock
mbed_official	52:a51c77007319	1014	* @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	1015	* @param TIM_ITRSource: Trigger source.
mbed_official	52:a51c77007319	1016	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1017	* @param TIM_TS_ITR0: Internal Trigger 0
mbed_official	52:a51c77007319	1018	* @param TIM_TS_ITR1: Internal Trigger 1
mbed_official	52:a51c77007319	1019	* @param TIM_TS_ITR2: Internal Trigger 2
mbed_official	52:a51c77007319	1020	* @param TIM_TS_ITR3: Internal Trigger 3
mbed_official	52:a51c77007319	1021	* @retval None
mbed_official	52:a51c77007319	1022	*/
mbed_official	52:a51c77007319	1023	void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
mbed_official	52:a51c77007319	1024	{
mbed_official	52:a51c77007319	1025	/* Check the parameters */
mbed_official	52:a51c77007319	1026	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1027	assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
mbed_official	52:a51c77007319	1028	/* Select the Internal Trigger */
mbed_official	52:a51c77007319	1029	TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
mbed_official	52:a51c77007319	1030	/* Select the External clock mode1 */
mbed_official	52:a51c77007319	1031	TIMx->SMCR \|= TIM_SlaveMode_External1;
mbed_official	52:a51c77007319	1032	}
mbed_official	52:a51c77007319	1033
mbed_official	52:a51c77007319	1034	/**
mbed_official	52:a51c77007319	1035	* @brief Configures the TIMx Trigger as External Clock
mbed_official	52:a51c77007319	1036	* @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	1037	* @param TIM_TIxExternalCLKSource: Trigger source.
mbed_official	52:a51c77007319	1038	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1039	* @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
mbed_official	52:a51c77007319	1040	* @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
mbed_official	52:a51c77007319	1041	* @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
mbed_official	52:a51c77007319	1042	* @param TIM_ICPolarity: specifies the TIx Polarity.
mbed_official	52:a51c77007319	1043	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1044	* @arg TIM_ICPolarity_Rising
mbed_official	52:a51c77007319	1045	* @arg TIM_ICPolarity_Falling
mbed_official	52:a51c77007319	1046	* @param ICFilter : specifies the filter value.
mbed_official	52:a51c77007319	1047	* This parameter must be a value between 0x0 and 0xF.
mbed_official	52:a51c77007319	1048	* @retval None
mbed_official	52:a51c77007319	1049	*/
mbed_official	52:a51c77007319	1050	void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
mbed_official	52:a51c77007319	1051	uint16_t TIM_ICPolarity, uint16_t ICFilter)
mbed_official	52:a51c77007319	1052	{
mbed_official	52:a51c77007319	1053	/* Check the parameters */
mbed_official	52:a51c77007319	1054	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1055	assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
mbed_official	52:a51c77007319	1056	assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
mbed_official	52:a51c77007319	1057	assert_param(IS_TIM_IC_FILTER(ICFilter));
mbed_official	52:a51c77007319	1058	/* Configure the Timer Input Clock Source */
mbed_official	52:a51c77007319	1059	if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
mbed_official	52:a51c77007319	1060	{
mbed_official	52:a51c77007319	1061	TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
mbed_official	52:a51c77007319	1062	}
mbed_official	52:a51c77007319	1063	else
mbed_official	52:a51c77007319	1064	{
mbed_official	52:a51c77007319	1065	TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
mbed_official	52:a51c77007319	1066	}
mbed_official	52:a51c77007319	1067	/* Select the Trigger source */
mbed_official	52:a51c77007319	1068	TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
mbed_official	52:a51c77007319	1069	/* Select the External clock mode1 */
mbed_official	52:a51c77007319	1070	TIMx->SMCR \|= TIM_SlaveMode_External1;
mbed_official	52:a51c77007319	1071	}
mbed_official	52:a51c77007319	1072
mbed_official	52:a51c77007319	1073	/**
mbed_official	52:a51c77007319	1074	* @brief Configures the External clock Mode1
mbed_official	52:a51c77007319	1075	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1076	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
mbed_official	52:a51c77007319	1077	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1078	* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
mbed_official	52:a51c77007319	1079	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
mbed_official	52:a51c77007319	1080	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
mbed_official	52:a51c77007319	1081	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
mbed_official	52:a51c77007319	1082	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
mbed_official	52:a51c77007319	1083	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1084	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
mbed_official	52:a51c77007319	1085	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
mbed_official	52:a51c77007319	1086	* @param ExtTRGFilter: External Trigger Filter.
mbed_official	52:a51c77007319	1087	* This parameter must be a value between 0x00 and 0x0F
mbed_official	52:a51c77007319	1088	* @retval None
mbed_official	52:a51c77007319	1089	*/
mbed_official	52:a51c77007319	1090	void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
mbed_official	52:a51c77007319	1091	uint16_t ExtTRGFilter)
mbed_official	52:a51c77007319	1092	{
mbed_official	52:a51c77007319	1093	uint16_t tmpsmcr = 0;
mbed_official	52:a51c77007319	1094	/* Check the parameters */
mbed_official	52:a51c77007319	1095	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1096	assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
mbed_official	52:a51c77007319	1097	assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
mbed_official	52:a51c77007319	1098	assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
mbed_official	52:a51c77007319	1099	/* Configure the ETR Clock source */
mbed_official	52:a51c77007319	1100	TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
mbed_official	52:a51c77007319	1101
mbed_official	52:a51c77007319	1102	/* Get the TIMx SMCR register value */
mbed_official	52:a51c77007319	1103	tmpsmcr = TIMx->SMCR;
mbed_official	52:a51c77007319	1104	/* Reset the SMS Bits */
mbed_official	52:a51c77007319	1105	tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
mbed_official	52:a51c77007319	1106	/* Select the External clock mode1 */
mbed_official	52:a51c77007319	1107	tmpsmcr \|= TIM_SlaveMode_External1;
mbed_official	52:a51c77007319	1108	/* Select the Trigger selection : ETRF */
mbed_official	52:a51c77007319	1109	tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
mbed_official	52:a51c77007319	1110	tmpsmcr \|= TIM_TS_ETRF;
mbed_official	52:a51c77007319	1111	/* Write to TIMx SMCR */
mbed_official	52:a51c77007319	1112	TIMx->SMCR = tmpsmcr;
mbed_official	52:a51c77007319	1113	}
mbed_official	52:a51c77007319	1114
mbed_official	52:a51c77007319	1115	/**
mbed_official	52:a51c77007319	1116	* @brief Configures the External clock Mode2
mbed_official	52:a51c77007319	1117	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1118	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
mbed_official	52:a51c77007319	1119	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1120	* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
mbed_official	52:a51c77007319	1121	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
mbed_official	52:a51c77007319	1122	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
mbed_official	52:a51c77007319	1123	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
mbed_official	52:a51c77007319	1124	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
mbed_official	52:a51c77007319	1125	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1126	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
mbed_official	52:a51c77007319	1127	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
mbed_official	52:a51c77007319	1128	* @param ExtTRGFilter: External Trigger Filter.
mbed_official	52:a51c77007319	1129	* This parameter must be a value between 0x00 and 0x0F
mbed_official	52:a51c77007319	1130	* @retval None
mbed_official	52:a51c77007319	1131	*/
mbed_official	52:a51c77007319	1132	void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
mbed_official	52:a51c77007319	1133	uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
mbed_official	52:a51c77007319	1134	{
mbed_official	52:a51c77007319	1135	/* Check the parameters */
mbed_official	52:a51c77007319	1136	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1137	assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
mbed_official	52:a51c77007319	1138	assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
mbed_official	52:a51c77007319	1139	assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
mbed_official	52:a51c77007319	1140	/* Configure the ETR Clock source */
mbed_official	52:a51c77007319	1141	TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
mbed_official	52:a51c77007319	1142	/* Enable the External clock mode2 */
mbed_official	52:a51c77007319	1143	TIMx->SMCR \|= TIM_SMCR_ECE;
mbed_official	52:a51c77007319	1144	}
mbed_official	52:a51c77007319	1145
mbed_official	52:a51c77007319	1146	/**
mbed_official	52:a51c77007319	1147	* @brief Configures the TIMx External Trigger (ETR).
mbed_official	52:a51c77007319	1148	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1149	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
mbed_official	52:a51c77007319	1150	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1151	* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
mbed_official	52:a51c77007319	1152	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
mbed_official	52:a51c77007319	1153	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
mbed_official	52:a51c77007319	1154	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
mbed_official	52:a51c77007319	1155	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
mbed_official	52:a51c77007319	1156	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1157	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
mbed_official	52:a51c77007319	1158	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
mbed_official	52:a51c77007319	1159	* @param ExtTRGFilter: External Trigger Filter.
mbed_official	52:a51c77007319	1160	* This parameter must be a value between 0x00 and 0x0F
mbed_official	52:a51c77007319	1161	* @retval None
mbed_official	52:a51c77007319	1162	*/
mbed_official	52:a51c77007319	1163	void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
mbed_official	52:a51c77007319	1164	uint16_t ExtTRGFilter)
mbed_official	52:a51c77007319	1165	{
mbed_official	52:a51c77007319	1166	uint16_t tmpsmcr = 0;
mbed_official	52:a51c77007319	1167	/* Check the parameters */
mbed_official	52:a51c77007319	1168	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1169	assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
mbed_official	52:a51c77007319	1170	assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
mbed_official	52:a51c77007319	1171	assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
mbed_official	52:a51c77007319	1172	tmpsmcr = TIMx->SMCR;
mbed_official	52:a51c77007319	1173	/* Reset the ETR Bits */
mbed_official	52:a51c77007319	1174	tmpsmcr &= SMCR_ETR_Mask;
mbed_official	52:a51c77007319	1175	/* Set the Prescaler, the Filter value and the Polarity */
mbed_official	52:a51c77007319	1176	tmpsmcr \|= (uint16_t)(TIM_ExtTRGPrescaler \| (uint16_t)(TIM_ExtTRGPolarity \| (uint16_t)(ExtTRGFilter << (uint16_t)8)));
mbed_official	52:a51c77007319	1177	/* Write to TIMx SMCR */
mbed_official	52:a51c77007319	1178	TIMx->SMCR = tmpsmcr;
mbed_official	52:a51c77007319	1179	}
mbed_official	52:a51c77007319	1180
mbed_official	52:a51c77007319	1181	/**
mbed_official	52:a51c77007319	1182	* @brief Configures the TIMx Prescaler.
mbed_official	52:a51c77007319	1183	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	1184	* @param Prescaler: specifies the Prescaler Register value
mbed_official	52:a51c77007319	1185	* @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
mbed_official	52:a51c77007319	1186	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1187	* @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
mbed_official	52:a51c77007319	1188	* @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
mbed_official	52:a51c77007319	1189	* @retval None
mbed_official	52:a51c77007319	1190	*/
mbed_official	52:a51c77007319	1191	void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
mbed_official	52:a51c77007319	1192	{
mbed_official	52:a51c77007319	1193	/* Check the parameters */
mbed_official	52:a51c77007319	1194	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	1195	assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
mbed_official	52:a51c77007319	1196	/* Set the Prescaler value */
mbed_official	52:a51c77007319	1197	TIMx->PSC = Prescaler;
mbed_official	52:a51c77007319	1198	/* Set or reset the UG Bit */
mbed_official	52:a51c77007319	1199	TIMx->EGR = TIM_PSCReloadMode;
mbed_official	52:a51c77007319	1200	}
mbed_official	52:a51c77007319	1201
mbed_official	52:a51c77007319	1202	/**
mbed_official	52:a51c77007319	1203	* @brief Specifies the TIMx Counter Mode to be used.
mbed_official	52:a51c77007319	1204	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1205	* @param TIM_CounterMode: specifies the Counter Mode to be used
mbed_official	52:a51c77007319	1206	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1207	* @arg TIM_CounterMode_Up: TIM Up Counting Mode
mbed_official	52:a51c77007319	1208	* @arg TIM_CounterMode_Down: TIM Down Counting Mode
mbed_official	52:a51c77007319	1209	* @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
mbed_official	52:a51c77007319	1210	* @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
mbed_official	52:a51c77007319	1211	* @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
mbed_official	52:a51c77007319	1212	* @retval None
mbed_official	52:a51c77007319	1213	*/
mbed_official	52:a51c77007319	1214	void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
mbed_official	52:a51c77007319	1215	{
mbed_official	52:a51c77007319	1216	uint16_t tmpcr1 = 0;
mbed_official	52:a51c77007319	1217	/* Check the parameters */
mbed_official	52:a51c77007319	1218	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1219	assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
mbed_official	52:a51c77007319	1220	tmpcr1 = TIMx->CR1;
mbed_official	52:a51c77007319	1221	/* Reset the CMS and DIR Bits */
mbed_official	52:a51c77007319	1222	tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR \| TIM_CR1_CMS)));
mbed_official	52:a51c77007319	1223	/* Set the Counter Mode */
mbed_official	52:a51c77007319	1224	tmpcr1 \|= TIM_CounterMode;
mbed_official	52:a51c77007319	1225	/* Write to TIMx CR1 register */
mbed_official	52:a51c77007319	1226	TIMx->CR1 = tmpcr1;
mbed_official	52:a51c77007319	1227	}
mbed_official	52:a51c77007319	1228
mbed_official	52:a51c77007319	1229	/**
mbed_official	52:a51c77007319	1230	* @brief Selects the Input Trigger source
mbed_official	52:a51c77007319	1231	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	1232	* @param TIM_InputTriggerSource: The Input Trigger source.
mbed_official	52:a51c77007319	1233	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1234	* @arg TIM_TS_ITR0: Internal Trigger 0
mbed_official	52:a51c77007319	1235	* @arg TIM_TS_ITR1: Internal Trigger 1
mbed_official	52:a51c77007319	1236	* @arg TIM_TS_ITR2: Internal Trigger 2
mbed_official	52:a51c77007319	1237	* @arg TIM_TS_ITR3: Internal Trigger 3
mbed_official	52:a51c77007319	1238	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
mbed_official	52:a51c77007319	1239	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
mbed_official	52:a51c77007319	1240	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
mbed_official	52:a51c77007319	1241	* @arg TIM_TS_ETRF: External Trigger input
mbed_official	52:a51c77007319	1242	* @retval None
mbed_official	52:a51c77007319	1243	*/
mbed_official	52:a51c77007319	1244	void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
mbed_official	52:a51c77007319	1245	{
mbed_official	52:a51c77007319	1246	uint16_t tmpsmcr = 0;
mbed_official	52:a51c77007319	1247	/* Check the parameters */
mbed_official	52:a51c77007319	1248	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1249	assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
mbed_official	52:a51c77007319	1250	/* Get the TIMx SMCR register value */
mbed_official	52:a51c77007319	1251	tmpsmcr = TIMx->SMCR;
mbed_official	52:a51c77007319	1252	/* Reset the TS Bits */
mbed_official	52:a51c77007319	1253	tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
mbed_official	52:a51c77007319	1254	/* Set the Input Trigger source */
mbed_official	52:a51c77007319	1255	tmpsmcr \|= TIM_InputTriggerSource;
mbed_official	52:a51c77007319	1256	/* Write to TIMx SMCR */
mbed_official	52:a51c77007319	1257	TIMx->SMCR = tmpsmcr;
mbed_official	52:a51c77007319	1258	}
mbed_official	52:a51c77007319	1259
mbed_official	52:a51c77007319	1260	/**
mbed_official	52:a51c77007319	1261	* @brief Configures the TIMx Encoder Interface.
mbed_official	52:a51c77007319	1262	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1263	* @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
mbed_official	52:a51c77007319	1264	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1265	* @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
mbed_official	52:a51c77007319	1266	* @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
mbed_official	52:a51c77007319	1267	* @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
mbed_official	52:a51c77007319	1268	* on the level of the other input.
mbed_official	52:a51c77007319	1269	* @param TIM_IC1Polarity: specifies the IC1 Polarity
mbed_official	52:a51c77007319	1270	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1271	* @arg TIM_ICPolarity_Falling: IC Falling edge.
mbed_official	52:a51c77007319	1272	* @arg TIM_ICPolarity_Rising: IC Rising edge.
mbed_official	52:a51c77007319	1273	* @param TIM_IC2Polarity: specifies the IC2 Polarity
mbed_official	52:a51c77007319	1274	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1275	* @arg TIM_ICPolarity_Falling: IC Falling edge.
mbed_official	52:a51c77007319	1276	* @arg TIM_ICPolarity_Rising: IC Rising edge.
mbed_official	52:a51c77007319	1277	* @retval None
mbed_official	52:a51c77007319	1278	*/
mbed_official	52:a51c77007319	1279	void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
mbed_official	52:a51c77007319	1280	uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
mbed_official	52:a51c77007319	1281	{
mbed_official	52:a51c77007319	1282	uint16_t tmpsmcr = 0;
mbed_official	52:a51c77007319	1283	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1284	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1285
mbed_official	52:a51c77007319	1286	/* Check the parameters */
mbed_official	52:a51c77007319	1287	assert_param(IS_TIM_LIST5_PERIPH(TIMx));
mbed_official	52:a51c77007319	1288	assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
mbed_official	52:a51c77007319	1289	assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
mbed_official	52:a51c77007319	1290	assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
mbed_official	52:a51c77007319	1291
mbed_official	52:a51c77007319	1292	/* Get the TIMx SMCR register value */
mbed_official	52:a51c77007319	1293	tmpsmcr = TIMx->SMCR;
mbed_official	52:a51c77007319	1294
mbed_official	52:a51c77007319	1295	/* Get the TIMx CCMR1 register value */
mbed_official	52:a51c77007319	1296	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1297
mbed_official	52:a51c77007319	1298	/* Get the TIMx CCER register value */
mbed_official	52:a51c77007319	1299	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1300
mbed_official	52:a51c77007319	1301	/* Set the encoder Mode */
mbed_official	52:a51c77007319	1302	tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
mbed_official	52:a51c77007319	1303	tmpsmcr \|= TIM_EncoderMode;
mbed_official	52:a51c77007319	1304
mbed_official	52:a51c77007319	1305	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
mbed_official	52:a51c77007319	1306	tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
mbed_official	52:a51c77007319	1307	tmpccmr1 \|= TIM_CCMR1_CC1S_0 \| TIM_CCMR1_CC2S_0;
mbed_official	52:a51c77007319	1308
mbed_official	52:a51c77007319	1309	/* Set the TI1 and the TI2 Polarities */
mbed_official	52:a51c77007319	1310	tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
mbed_official	52:a51c77007319	1311	tmpccer \|= (uint16_t)(TIM_IC1Polarity \| (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
mbed_official	52:a51c77007319	1312
mbed_official	52:a51c77007319	1313	/* Write to TIMx SMCR */
mbed_official	52:a51c77007319	1314	TIMx->SMCR = tmpsmcr;
mbed_official	52:a51c77007319	1315	/* Write to TIMx CCMR1 */
mbed_official	52:a51c77007319	1316	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1317	/* Write to TIMx CCER */
mbed_official	52:a51c77007319	1318	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1319	}
mbed_official	52:a51c77007319	1320
mbed_official	52:a51c77007319	1321	/**
mbed_official	52:a51c77007319	1322	* @brief Forces the TIMx output 1 waveform to active or inactive level.
mbed_official	52:a51c77007319	1323	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	1324	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
mbed_official	52:a51c77007319	1325	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1326	* @arg TIM_ForcedAction_Active: Force active level on OC1REF
mbed_official	52:a51c77007319	1327	* @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
mbed_official	52:a51c77007319	1328	* @retval None
mbed_official	52:a51c77007319	1329	*/
mbed_official	52:a51c77007319	1330	void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
mbed_official	52:a51c77007319	1331	{
mbed_official	52:a51c77007319	1332	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1333	/* Check the parameters */
mbed_official	52:a51c77007319	1334	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	1335	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
mbed_official	52:a51c77007319	1336	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1337	/* Reset the OC1M Bits */
mbed_official	52:a51c77007319	1338	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
mbed_official	52:a51c77007319	1339	/* Configure The Forced output Mode */
mbed_official	52:a51c77007319	1340	tmpccmr1 \|= TIM_ForcedAction;
mbed_official	52:a51c77007319	1341	/* Write to TIMx CCMR1 register */
mbed_official	52:a51c77007319	1342	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1343	}
mbed_official	52:a51c77007319	1344
mbed_official	52:a51c77007319	1345	/**
mbed_official	52:a51c77007319	1346	* @brief Forces the TIMx output 2 waveform to active or inactive level.
mbed_official	52:a51c77007319	1347	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	1348	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
mbed_official	52:a51c77007319	1349	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1350	* @arg TIM_ForcedAction_Active: Force active level on OC2REF
mbed_official	52:a51c77007319	1351	* @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
mbed_official	52:a51c77007319	1352	* @retval None
mbed_official	52:a51c77007319	1353	*/
mbed_official	52:a51c77007319	1354	void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
mbed_official	52:a51c77007319	1355	{
mbed_official	52:a51c77007319	1356	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1357	/* Check the parameters */
mbed_official	52:a51c77007319	1358	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1359	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
mbed_official	52:a51c77007319	1360	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1361	/* Reset the OC2M Bits */
mbed_official	52:a51c77007319	1362	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
mbed_official	52:a51c77007319	1363	/* Configure The Forced output Mode */
mbed_official	52:a51c77007319	1364	tmpccmr1 \|= (uint16_t)(TIM_ForcedAction << 8);
mbed_official	52:a51c77007319	1365	/* Write to TIMx CCMR1 register */
mbed_official	52:a51c77007319	1366	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1367	}
mbed_official	52:a51c77007319	1368
mbed_official	52:a51c77007319	1369	/**
mbed_official	52:a51c77007319	1370	* @brief Forces the TIMx output 3 waveform to active or inactive level.
mbed_official	52:a51c77007319	1371	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1372	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
mbed_official	52:a51c77007319	1373	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1374	* @arg TIM_ForcedAction_Active: Force active level on OC3REF
mbed_official	52:a51c77007319	1375	* @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
mbed_official	52:a51c77007319	1376	* @retval None
mbed_official	52:a51c77007319	1377	*/
mbed_official	52:a51c77007319	1378	void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
mbed_official	52:a51c77007319	1379	{
mbed_official	52:a51c77007319	1380	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1381	/* Check the parameters */
mbed_official	52:a51c77007319	1382	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1383	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
mbed_official	52:a51c77007319	1384	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1385	/* Reset the OC1M Bits */
mbed_official	52:a51c77007319	1386	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
mbed_official	52:a51c77007319	1387	/* Configure The Forced output Mode */
mbed_official	52:a51c77007319	1388	tmpccmr2 \|= TIM_ForcedAction;
mbed_official	52:a51c77007319	1389	/* Write to TIMx CCMR2 register */
mbed_official	52:a51c77007319	1390	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1391	}
mbed_official	52:a51c77007319	1392
mbed_official	52:a51c77007319	1393	/**
mbed_official	52:a51c77007319	1394	* @brief Forces the TIMx output 4 waveform to active or inactive level.
mbed_official	52:a51c77007319	1395	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1396	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
mbed_official	52:a51c77007319	1397	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1398	* @arg TIM_ForcedAction_Active: Force active level on OC4REF
mbed_official	52:a51c77007319	1399	* @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
mbed_official	52:a51c77007319	1400	* @retval None
mbed_official	52:a51c77007319	1401	*/
mbed_official	52:a51c77007319	1402	void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
mbed_official	52:a51c77007319	1403	{
mbed_official	52:a51c77007319	1404	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1405	/* Check the parameters */
mbed_official	52:a51c77007319	1406	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1407	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
mbed_official	52:a51c77007319	1408	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1409	/* Reset the OC2M Bits */
mbed_official	52:a51c77007319	1410	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
mbed_official	52:a51c77007319	1411	/* Configure The Forced output Mode */
mbed_official	52:a51c77007319	1412	tmpccmr2 \|= (uint16_t)(TIM_ForcedAction << 8);
mbed_official	52:a51c77007319	1413	/* Write to TIMx CCMR2 register */
mbed_official	52:a51c77007319	1414	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1415	}
mbed_official	52:a51c77007319	1416
mbed_official	52:a51c77007319	1417	/**
mbed_official	52:a51c77007319	1418	* @brief Enables or disables TIMx peripheral Preload register on ARR.
mbed_official	52:a51c77007319	1419	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	1420	* @param NewState: new state of the TIMx peripheral Preload register
mbed_official	52:a51c77007319	1421	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1422	* @retval None
mbed_official	52:a51c77007319	1423	*/
mbed_official	52:a51c77007319	1424	void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	1425	{
mbed_official	52:a51c77007319	1426	/* Check the parameters */
mbed_official	52:a51c77007319	1427	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	1428	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1429	if (NewState != DISABLE)
mbed_official	52:a51c77007319	1430	{
mbed_official	52:a51c77007319	1431	/* Set the ARR Preload Bit */
mbed_official	52:a51c77007319	1432	TIMx->CR1 \|= TIM_CR1_ARPE;
mbed_official	52:a51c77007319	1433	}
mbed_official	52:a51c77007319	1434	else
mbed_official	52:a51c77007319	1435	{
mbed_official	52:a51c77007319	1436	/* Reset the ARR Preload Bit */
mbed_official	52:a51c77007319	1437	TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
mbed_official	52:a51c77007319	1438	}
mbed_official	52:a51c77007319	1439	}
mbed_official	52:a51c77007319	1440
mbed_official	52:a51c77007319	1441	/**
mbed_official	52:a51c77007319	1442	* @brief Selects the TIM peripheral Commutation event.
mbed_official	52:a51c77007319	1443	* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
mbed_official	52:a51c77007319	1444	* @param NewState: new state of the Commutation event.
mbed_official	52:a51c77007319	1445	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1446	* @retval None
mbed_official	52:a51c77007319	1447	*/
mbed_official	52:a51c77007319	1448	void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	1449	{
mbed_official	52:a51c77007319	1450	/* Check the parameters */
mbed_official	52:a51c77007319	1451	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
mbed_official	52:a51c77007319	1452	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1453	if (NewState != DISABLE)
mbed_official	52:a51c77007319	1454	{
mbed_official	52:a51c77007319	1455	/* Set the COM Bit */
mbed_official	52:a51c77007319	1456	TIMx->CR2 \|= TIM_CR2_CCUS;
mbed_official	52:a51c77007319	1457	}
mbed_official	52:a51c77007319	1458	else
mbed_official	52:a51c77007319	1459	{
mbed_official	52:a51c77007319	1460	/* Reset the COM Bit */
mbed_official	52:a51c77007319	1461	TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
mbed_official	52:a51c77007319	1462	}
mbed_official	52:a51c77007319	1463	}
mbed_official	52:a51c77007319	1464
mbed_official	52:a51c77007319	1465	/**
mbed_official	52:a51c77007319	1466	* @brief Selects the TIMx peripheral Capture Compare DMA source.
mbed_official	52:a51c77007319	1467	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
mbed_official	52:a51c77007319	1468	* the TIM peripheral.
mbed_official	52:a51c77007319	1469	* @param NewState: new state of the Capture Compare DMA source
mbed_official	52:a51c77007319	1470	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1471	* @retval None
mbed_official	52:a51c77007319	1472	*/
mbed_official	52:a51c77007319	1473	void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	1474	{
mbed_official	52:a51c77007319	1475	/* Check the parameters */
mbed_official	52:a51c77007319	1476	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
mbed_official	52:a51c77007319	1477	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1478	if (NewState != DISABLE)
mbed_official	52:a51c77007319	1479	{
mbed_official	52:a51c77007319	1480	/* Set the CCDS Bit */
mbed_official	52:a51c77007319	1481	TIMx->CR2 \|= TIM_CR2_CCDS;
mbed_official	52:a51c77007319	1482	}
mbed_official	52:a51c77007319	1483	else
mbed_official	52:a51c77007319	1484	{
mbed_official	52:a51c77007319	1485	/* Reset the CCDS Bit */
mbed_official	52:a51c77007319	1486	TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
mbed_official	52:a51c77007319	1487	}
mbed_official	52:a51c77007319	1488	}
mbed_official	52:a51c77007319	1489
mbed_official	52:a51c77007319	1490	/**
mbed_official	52:a51c77007319	1491	* @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
mbed_official	52:a51c77007319	1492	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15
mbed_official	52:a51c77007319	1493	* to select the TIMx peripheral
mbed_official	52:a51c77007319	1494	* @param NewState: new state of the Capture Compare Preload Control bit
mbed_official	52:a51c77007319	1495	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1496	* @retval None
mbed_official	52:a51c77007319	1497	*/
mbed_official	52:a51c77007319	1498	void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	1499	{
mbed_official	52:a51c77007319	1500	/* Check the parameters */
mbed_official	52:a51c77007319	1501	assert_param(IS_TIM_LIST5_PERIPH(TIMx));
mbed_official	52:a51c77007319	1502	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1503	if (NewState != DISABLE)
mbed_official	52:a51c77007319	1504	{
mbed_official	52:a51c77007319	1505	/* Set the CCPC Bit */
mbed_official	52:a51c77007319	1506	TIMx->CR2 \|= TIM_CR2_CCPC;
mbed_official	52:a51c77007319	1507	}
mbed_official	52:a51c77007319	1508	else
mbed_official	52:a51c77007319	1509	{
mbed_official	52:a51c77007319	1510	/* Reset the CCPC Bit */
mbed_official	52:a51c77007319	1511	TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
mbed_official	52:a51c77007319	1512	}
mbed_official	52:a51c77007319	1513	}
mbed_official	52:a51c77007319	1514
mbed_official	52:a51c77007319	1515	/**
mbed_official	52:a51c77007319	1516	* @brief Enables or disables the TIMx peripheral Preload register on CCR1.
mbed_official	52:a51c77007319	1517	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	1518	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
mbed_official	52:a51c77007319	1519	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1520	* @arg TIM_OCPreload_Enable
mbed_official	52:a51c77007319	1521	* @arg TIM_OCPreload_Disable
mbed_official	52:a51c77007319	1522	* @retval None
mbed_official	52:a51c77007319	1523	*/
mbed_official	52:a51c77007319	1524	void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
mbed_official	52:a51c77007319	1525	{
mbed_official	52:a51c77007319	1526	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1527	/* Check the parameters */
mbed_official	52:a51c77007319	1528	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	1529	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
mbed_official	52:a51c77007319	1530	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1531	/* Reset the OC1PE Bit */
mbed_official	52:a51c77007319	1532	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
mbed_official	52:a51c77007319	1533	/* Enable or Disable the Output Compare Preload feature */
mbed_official	52:a51c77007319	1534	tmpccmr1 \|= TIM_OCPreload;
mbed_official	52:a51c77007319	1535	/* Write to TIMx CCMR1 register */
mbed_official	52:a51c77007319	1536	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1537	}
mbed_official	52:a51c77007319	1538
mbed_official	52:a51c77007319	1539	/**
mbed_official	52:a51c77007319	1540	* @brief Enables or disables the TIMx peripheral Preload register on CCR2.
mbed_official	52:a51c77007319	1541	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
mbed_official	52:a51c77007319	1542	* the TIM peripheral.
mbed_official	52:a51c77007319	1543	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
mbed_official	52:a51c77007319	1544	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1545	* @arg TIM_OCPreload_Enable
mbed_official	52:a51c77007319	1546	* @arg TIM_OCPreload_Disable
mbed_official	52:a51c77007319	1547	* @retval None
mbed_official	52:a51c77007319	1548	*/
mbed_official	52:a51c77007319	1549	void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
mbed_official	52:a51c77007319	1550	{
mbed_official	52:a51c77007319	1551	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1552	/* Check the parameters */
mbed_official	52:a51c77007319	1553	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1554	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
mbed_official	52:a51c77007319	1555	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1556	/* Reset the OC2PE Bit */
mbed_official	52:a51c77007319	1557	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
mbed_official	52:a51c77007319	1558	/* Enable or Disable the Output Compare Preload feature */
mbed_official	52:a51c77007319	1559	tmpccmr1 \|= (uint16_t)(TIM_OCPreload << 8);
mbed_official	52:a51c77007319	1560	/* Write to TIMx CCMR1 register */
mbed_official	52:a51c77007319	1561	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1562	}
mbed_official	52:a51c77007319	1563
mbed_official	52:a51c77007319	1564	/**
mbed_official	52:a51c77007319	1565	* @brief Enables or disables the TIMx peripheral Preload register on CCR3.
mbed_official	52:a51c77007319	1566	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1567	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
mbed_official	52:a51c77007319	1568	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1569	* @arg TIM_OCPreload_Enable
mbed_official	52:a51c77007319	1570	* @arg TIM_OCPreload_Disable
mbed_official	52:a51c77007319	1571	* @retval None
mbed_official	52:a51c77007319	1572	*/
mbed_official	52:a51c77007319	1573	void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
mbed_official	52:a51c77007319	1574	{
mbed_official	52:a51c77007319	1575	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1576	/* Check the parameters */
mbed_official	52:a51c77007319	1577	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1578	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
mbed_official	52:a51c77007319	1579	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1580	/* Reset the OC3PE Bit */
mbed_official	52:a51c77007319	1581	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
mbed_official	52:a51c77007319	1582	/* Enable or Disable the Output Compare Preload feature */
mbed_official	52:a51c77007319	1583	tmpccmr2 \|= TIM_OCPreload;
mbed_official	52:a51c77007319	1584	/* Write to TIMx CCMR2 register */
mbed_official	52:a51c77007319	1585	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1586	}
mbed_official	52:a51c77007319	1587
mbed_official	52:a51c77007319	1588	/**
mbed_official	52:a51c77007319	1589	* @brief Enables or disables the TIMx peripheral Preload register on CCR4.
mbed_official	52:a51c77007319	1590	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1591	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
mbed_official	52:a51c77007319	1592	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1593	* @arg TIM_OCPreload_Enable
mbed_official	52:a51c77007319	1594	* @arg TIM_OCPreload_Disable
mbed_official	52:a51c77007319	1595	* @retval None
mbed_official	52:a51c77007319	1596	*/
mbed_official	52:a51c77007319	1597	void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
mbed_official	52:a51c77007319	1598	{
mbed_official	52:a51c77007319	1599	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1600	/* Check the parameters */
mbed_official	52:a51c77007319	1601	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1602	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
mbed_official	52:a51c77007319	1603	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1604	/* Reset the OC4PE Bit */
mbed_official	52:a51c77007319	1605	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
mbed_official	52:a51c77007319	1606	/* Enable or Disable the Output Compare Preload feature */
mbed_official	52:a51c77007319	1607	tmpccmr2 \|= (uint16_t)(TIM_OCPreload << 8);
mbed_official	52:a51c77007319	1608	/* Write to TIMx CCMR2 register */
mbed_official	52:a51c77007319	1609	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1610	}
mbed_official	52:a51c77007319	1611
mbed_official	52:a51c77007319	1612	/**
mbed_official	52:a51c77007319	1613	* @brief Configures the TIMx Output Compare 1 Fast feature.
mbed_official	52:a51c77007319	1614	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	1615	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
mbed_official	52:a51c77007319	1616	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1617	* @arg TIM_OCFast_Enable: TIM output compare fast enable
mbed_official	52:a51c77007319	1618	* @arg TIM_OCFast_Disable: TIM output compare fast disable
mbed_official	52:a51c77007319	1619	* @retval None
mbed_official	52:a51c77007319	1620	*/
mbed_official	52:a51c77007319	1621	void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
mbed_official	52:a51c77007319	1622	{
mbed_official	52:a51c77007319	1623	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1624	/* Check the parameters */
mbed_official	52:a51c77007319	1625	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	1626	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
mbed_official	52:a51c77007319	1627	/* Get the TIMx CCMR1 register value */
mbed_official	52:a51c77007319	1628	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1629	/* Reset the OC1FE Bit */
mbed_official	52:a51c77007319	1630	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
mbed_official	52:a51c77007319	1631	/* Enable or Disable the Output Compare Fast Bit */
mbed_official	52:a51c77007319	1632	tmpccmr1 \|= TIM_OCFast;
mbed_official	52:a51c77007319	1633	/* Write to TIMx CCMR1 */
mbed_official	52:a51c77007319	1634	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1635	}
mbed_official	52:a51c77007319	1636
mbed_official	52:a51c77007319	1637	/**
mbed_official	52:a51c77007319	1638	* @brief Configures the TIMx Output Compare 2 Fast feature.
mbed_official	52:a51c77007319	1639	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
mbed_official	52:a51c77007319	1640	* the TIM peripheral.
mbed_official	52:a51c77007319	1641	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
mbed_official	52:a51c77007319	1642	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1643	* @arg TIM_OCFast_Enable: TIM output compare fast enable
mbed_official	52:a51c77007319	1644	* @arg TIM_OCFast_Disable: TIM output compare fast disable
mbed_official	52:a51c77007319	1645	* @retval None
mbed_official	52:a51c77007319	1646	*/
mbed_official	52:a51c77007319	1647	void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
mbed_official	52:a51c77007319	1648	{
mbed_official	52:a51c77007319	1649	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1650	/* Check the parameters */
mbed_official	52:a51c77007319	1651	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1652	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
mbed_official	52:a51c77007319	1653	/* Get the TIMx CCMR1 register value */
mbed_official	52:a51c77007319	1654	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1655	/* Reset the OC2FE Bit */
mbed_official	52:a51c77007319	1656	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
mbed_official	52:a51c77007319	1657	/* Enable or Disable the Output Compare Fast Bit */
mbed_official	52:a51c77007319	1658	tmpccmr1 \|= (uint16_t)(TIM_OCFast << 8);
mbed_official	52:a51c77007319	1659	/* Write to TIMx CCMR1 */
mbed_official	52:a51c77007319	1660	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1661	}
mbed_official	52:a51c77007319	1662
mbed_official	52:a51c77007319	1663	/**
mbed_official	52:a51c77007319	1664	* @brief Configures the TIMx Output Compare 3 Fast feature.
mbed_official	52:a51c77007319	1665	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1666	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
mbed_official	52:a51c77007319	1667	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1668	* @arg TIM_OCFast_Enable: TIM output compare fast enable
mbed_official	52:a51c77007319	1669	* @arg TIM_OCFast_Disable: TIM output compare fast disable
mbed_official	52:a51c77007319	1670	* @retval None
mbed_official	52:a51c77007319	1671	*/
mbed_official	52:a51c77007319	1672	void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
mbed_official	52:a51c77007319	1673	{
mbed_official	52:a51c77007319	1674	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1675	/* Check the parameters */
mbed_official	52:a51c77007319	1676	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1677	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
mbed_official	52:a51c77007319	1678	/* Get the TIMx CCMR2 register value */
mbed_official	52:a51c77007319	1679	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1680	/* Reset the OC3FE Bit */
mbed_official	52:a51c77007319	1681	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
mbed_official	52:a51c77007319	1682	/* Enable or Disable the Output Compare Fast Bit */
mbed_official	52:a51c77007319	1683	tmpccmr2 \|= TIM_OCFast;
mbed_official	52:a51c77007319	1684	/* Write to TIMx CCMR2 */
mbed_official	52:a51c77007319	1685	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1686	}
mbed_official	52:a51c77007319	1687
mbed_official	52:a51c77007319	1688	/**
mbed_official	52:a51c77007319	1689	* @brief Configures the TIMx Output Compare 4 Fast feature.
mbed_official	52:a51c77007319	1690	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1691	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
mbed_official	52:a51c77007319	1692	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1693	* @arg TIM_OCFast_Enable: TIM output compare fast enable
mbed_official	52:a51c77007319	1694	* @arg TIM_OCFast_Disable: TIM output compare fast disable
mbed_official	52:a51c77007319	1695	* @retval None
mbed_official	52:a51c77007319	1696	*/
mbed_official	52:a51c77007319	1697	void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
mbed_official	52:a51c77007319	1698	{
mbed_official	52:a51c77007319	1699	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1700	/* Check the parameters */
mbed_official	52:a51c77007319	1701	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1702	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
mbed_official	52:a51c77007319	1703	/* Get the TIMx CCMR2 register value */
mbed_official	52:a51c77007319	1704	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1705	/* Reset the OC4FE Bit */
mbed_official	52:a51c77007319	1706	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
mbed_official	52:a51c77007319	1707	/* Enable or Disable the Output Compare Fast Bit */
mbed_official	52:a51c77007319	1708	tmpccmr2 \|= (uint16_t)(TIM_OCFast << 8);
mbed_official	52:a51c77007319	1709	/* Write to TIMx CCMR2 */
mbed_official	52:a51c77007319	1710	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1711	}
mbed_official	52:a51c77007319	1712
mbed_official	52:a51c77007319	1713	/**
mbed_official	52:a51c77007319	1714	* @brief Clears or safeguards the OCREF1 signal on an external event
mbed_official	52:a51c77007319	1715	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1716	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
mbed_official	52:a51c77007319	1717	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1718	* @arg TIM_OCClear_Enable: TIM Output clear enable
mbed_official	52:a51c77007319	1719	* @arg TIM_OCClear_Disable: TIM Output clear disable
mbed_official	52:a51c77007319	1720	* @retval None
mbed_official	52:a51c77007319	1721	*/
mbed_official	52:a51c77007319	1722	void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
mbed_official	52:a51c77007319	1723	{
mbed_official	52:a51c77007319	1724	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1725	/* Check the parameters */
mbed_official	52:a51c77007319	1726	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1727	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
mbed_official	52:a51c77007319	1728
mbed_official	52:a51c77007319	1729	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1730
mbed_official	52:a51c77007319	1731	/* Reset the OC1CE Bit */
mbed_official	52:a51c77007319	1732	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
mbed_official	52:a51c77007319	1733	/* Enable or Disable the Output Compare Clear Bit */
mbed_official	52:a51c77007319	1734	tmpccmr1 \|= TIM_OCClear;
mbed_official	52:a51c77007319	1735	/* Write to TIMx CCMR1 register */
mbed_official	52:a51c77007319	1736	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1737	}
mbed_official	52:a51c77007319	1738
mbed_official	52:a51c77007319	1739	/**
mbed_official	52:a51c77007319	1740	* @brief Clears or safeguards the OCREF2 signal on an external event
mbed_official	52:a51c77007319	1741	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1742	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
mbed_official	52:a51c77007319	1743	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1744	* @arg TIM_OCClear_Enable: TIM Output clear enable
mbed_official	52:a51c77007319	1745	* @arg TIM_OCClear_Disable: TIM Output clear disable
mbed_official	52:a51c77007319	1746	* @retval None
mbed_official	52:a51c77007319	1747	*/
mbed_official	52:a51c77007319	1748	void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
mbed_official	52:a51c77007319	1749	{
mbed_official	52:a51c77007319	1750	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1751	/* Check the parameters */
mbed_official	52:a51c77007319	1752	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1753	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
mbed_official	52:a51c77007319	1754	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1755	/* Reset the OC2CE Bit */
mbed_official	52:a51c77007319	1756	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
mbed_official	52:a51c77007319	1757	/* Enable or Disable the Output Compare Clear Bit */
mbed_official	52:a51c77007319	1758	tmpccmr1 \|= (uint16_t)(TIM_OCClear << 8);
mbed_official	52:a51c77007319	1759	/* Write to TIMx CCMR1 register */
mbed_official	52:a51c77007319	1760	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1761	}
mbed_official	52:a51c77007319	1762
mbed_official	52:a51c77007319	1763	/**
mbed_official	52:a51c77007319	1764	* @brief Clears or safeguards the OCREF3 signal on an external event
mbed_official	52:a51c77007319	1765	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1766	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
mbed_official	52:a51c77007319	1767	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1768	* @arg TIM_OCClear_Enable: TIM Output clear enable
mbed_official	52:a51c77007319	1769	* @arg TIM_OCClear_Disable: TIM Output clear disable
mbed_official	52:a51c77007319	1770	* @retval None
mbed_official	52:a51c77007319	1771	*/
mbed_official	52:a51c77007319	1772	void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
mbed_official	52:a51c77007319	1773	{
mbed_official	52:a51c77007319	1774	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1775	/* Check the parameters */
mbed_official	52:a51c77007319	1776	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1777	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
mbed_official	52:a51c77007319	1778	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1779	/* Reset the OC3CE Bit */
mbed_official	52:a51c77007319	1780	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
mbed_official	52:a51c77007319	1781	/* Enable or Disable the Output Compare Clear Bit */
mbed_official	52:a51c77007319	1782	tmpccmr2 \|= TIM_OCClear;
mbed_official	52:a51c77007319	1783	/* Write to TIMx CCMR2 register */
mbed_official	52:a51c77007319	1784	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1785	}
mbed_official	52:a51c77007319	1786
mbed_official	52:a51c77007319	1787	/**
mbed_official	52:a51c77007319	1788	* @brief Clears or safeguards the OCREF4 signal on an external event
mbed_official	52:a51c77007319	1789	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1790	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
mbed_official	52:a51c77007319	1791	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1792	* @arg TIM_OCClear_Enable: TIM Output clear enable
mbed_official	52:a51c77007319	1793	* @arg TIM_OCClear_Disable: TIM Output clear disable
mbed_official	52:a51c77007319	1794	* @retval None
mbed_official	52:a51c77007319	1795	*/
mbed_official	52:a51c77007319	1796	void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
mbed_official	52:a51c77007319	1797	{
mbed_official	52:a51c77007319	1798	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1799	/* Check the parameters */
mbed_official	52:a51c77007319	1800	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1801	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
mbed_official	52:a51c77007319	1802	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1803	/* Reset the OC4CE Bit */
mbed_official	52:a51c77007319	1804	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
mbed_official	52:a51c77007319	1805	/* Enable or Disable the Output Compare Clear Bit */
mbed_official	52:a51c77007319	1806	tmpccmr2 \|= (uint16_t)(TIM_OCClear << 8);
mbed_official	52:a51c77007319	1807	/* Write to TIMx CCMR2 register */
mbed_official	52:a51c77007319	1808	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1809	}
mbed_official	52:a51c77007319	1810
mbed_official	52:a51c77007319	1811	/**
mbed_official	52:a51c77007319	1812	* @brief Configures the TIMx channel 1 polarity.
mbed_official	52:a51c77007319	1813	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	1814	* @param TIM_OCPolarity: specifies the OC1 Polarity
mbed_official	52:a51c77007319	1815	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1816	* @arg TIM_OCPolarity_High: Output Compare active high
mbed_official	52:a51c77007319	1817	* @arg TIM_OCPolarity_Low: Output Compare active low
mbed_official	52:a51c77007319	1818	* @retval None
mbed_official	52:a51c77007319	1819	*/
mbed_official	52:a51c77007319	1820	void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
mbed_official	52:a51c77007319	1821	{
mbed_official	52:a51c77007319	1822	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1823	/* Check the parameters */
mbed_official	52:a51c77007319	1824	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	1825	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
mbed_official	52:a51c77007319	1826	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1827	/* Set or Reset the CC1P Bit */
mbed_official	52:a51c77007319	1828	tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
mbed_official	52:a51c77007319	1829	tmpccer \|= TIM_OCPolarity;
mbed_official	52:a51c77007319	1830	/* Write to TIMx CCER register */
mbed_official	52:a51c77007319	1831	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1832	}
mbed_official	52:a51c77007319	1833
mbed_official	52:a51c77007319	1834	/**
mbed_official	52:a51c77007319	1835	* @brief Configures the TIMx Channel 1N polarity.
mbed_official	52:a51c77007319	1836	* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	1837	* @param TIM_OCNPolarity: specifies the OC1N Polarity
mbed_official	52:a51c77007319	1838	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1839	* @arg TIM_OCNPolarity_High: Output Compare active high
mbed_official	52:a51c77007319	1840	* @arg TIM_OCNPolarity_Low: Output Compare active low
mbed_official	52:a51c77007319	1841	* @retval None
mbed_official	52:a51c77007319	1842	*/
mbed_official	52:a51c77007319	1843	void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
mbed_official	52:a51c77007319	1844	{
mbed_official	52:a51c77007319	1845	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1846	/* Check the parameters */
mbed_official	52:a51c77007319	1847	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
mbed_official	52:a51c77007319	1848	assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
mbed_official	52:a51c77007319	1849
mbed_official	52:a51c77007319	1850	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1851	/* Set or Reset the CC1NP Bit */
mbed_official	52:a51c77007319	1852	tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
mbed_official	52:a51c77007319	1853	tmpccer \|= TIM_OCNPolarity;
mbed_official	52:a51c77007319	1854	/* Write to TIMx CCER register */
mbed_official	52:a51c77007319	1855	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1856	}
mbed_official	52:a51c77007319	1857
mbed_official	52:a51c77007319	1858	/**
mbed_official	52:a51c77007319	1859	* @brief Configures the TIMx channel 2 polarity.
mbed_official	52:a51c77007319	1860	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	1861	* @param TIM_OCPolarity: specifies the OC2 Polarity
mbed_official	52:a51c77007319	1862	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1863	* @arg TIM_OCPolarity_High: Output Compare active high
mbed_official	52:a51c77007319	1864	* @arg TIM_OCPolarity_Low: Output Compare active low
mbed_official	52:a51c77007319	1865	* @retval None
mbed_official	52:a51c77007319	1866	*/
mbed_official	52:a51c77007319	1867	void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
mbed_official	52:a51c77007319	1868	{
mbed_official	52:a51c77007319	1869	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1870	/* Check the parameters */
mbed_official	52:a51c77007319	1871	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1872	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
mbed_official	52:a51c77007319	1873	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1874	/* Set or Reset the CC2P Bit */
mbed_official	52:a51c77007319	1875	tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
mbed_official	52:a51c77007319	1876	tmpccer \|= (uint16_t)(TIM_OCPolarity << 4);
mbed_official	52:a51c77007319	1877	/* Write to TIMx CCER register */
mbed_official	52:a51c77007319	1878	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1879	}
mbed_official	52:a51c77007319	1880
mbed_official	52:a51c77007319	1881	/**
mbed_official	52:a51c77007319	1882	* @brief Configures the TIMx Channel 2N polarity.
mbed_official	52:a51c77007319	1883	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1884	* @param TIM_OCNPolarity: specifies the OC2N Polarity
mbed_official	52:a51c77007319	1885	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1886	* @arg TIM_OCNPolarity_High: Output Compare active high
mbed_official	52:a51c77007319	1887	* @arg TIM_OCNPolarity_Low: Output Compare active low
mbed_official	52:a51c77007319	1888	* @retval None
mbed_official	52:a51c77007319	1889	*/
mbed_official	52:a51c77007319	1890	void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
mbed_official	52:a51c77007319	1891	{
mbed_official	52:a51c77007319	1892	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1893	/* Check the parameters */
mbed_official	52:a51c77007319	1894	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
mbed_official	52:a51c77007319	1895	assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
mbed_official	52:a51c77007319	1896
mbed_official	52:a51c77007319	1897	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1898	/* Set or Reset the CC2NP Bit */
mbed_official	52:a51c77007319	1899	tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
mbed_official	52:a51c77007319	1900	tmpccer \|= (uint16_t)(TIM_OCNPolarity << 4);
mbed_official	52:a51c77007319	1901	/* Write to TIMx CCER register */
mbed_official	52:a51c77007319	1902	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1903	}
mbed_official	52:a51c77007319	1904
mbed_official	52:a51c77007319	1905	/**
mbed_official	52:a51c77007319	1906	* @brief Configures the TIMx channel 3 polarity.
mbed_official	52:a51c77007319	1907	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1908	* @param TIM_OCPolarity: specifies the OC3 Polarity
mbed_official	52:a51c77007319	1909	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1910	* @arg TIM_OCPolarity_High: Output Compare active high
mbed_official	52:a51c77007319	1911	* @arg TIM_OCPolarity_Low: Output Compare active low
mbed_official	52:a51c77007319	1912	* @retval None
mbed_official	52:a51c77007319	1913	*/
mbed_official	52:a51c77007319	1914	void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
mbed_official	52:a51c77007319	1915	{
mbed_official	52:a51c77007319	1916	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1917	/* Check the parameters */
mbed_official	52:a51c77007319	1918	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1919	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
mbed_official	52:a51c77007319	1920	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1921	/* Set or Reset the CC3P Bit */
mbed_official	52:a51c77007319	1922	tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
mbed_official	52:a51c77007319	1923	tmpccer \|= (uint16_t)(TIM_OCPolarity << 8);
mbed_official	52:a51c77007319	1924	/* Write to TIMx CCER register */
mbed_official	52:a51c77007319	1925	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1926	}
mbed_official	52:a51c77007319	1927
mbed_official	52:a51c77007319	1928	/**
mbed_official	52:a51c77007319	1929	* @brief Configures the TIMx Channel 3N polarity.
mbed_official	52:a51c77007319	1930	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1931	* @param TIM_OCNPolarity: specifies the OC3N Polarity
mbed_official	52:a51c77007319	1932	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1933	* @arg TIM_OCNPolarity_High: Output Compare active high
mbed_official	52:a51c77007319	1934	* @arg TIM_OCNPolarity_Low: Output Compare active low
mbed_official	52:a51c77007319	1935	* @retval None
mbed_official	52:a51c77007319	1936	*/
mbed_official	52:a51c77007319	1937	void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
mbed_official	52:a51c77007319	1938	{
mbed_official	52:a51c77007319	1939	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1940
mbed_official	52:a51c77007319	1941	/* Check the parameters */
mbed_official	52:a51c77007319	1942	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
mbed_official	52:a51c77007319	1943	assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
mbed_official	52:a51c77007319	1944
mbed_official	52:a51c77007319	1945	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1946	/* Set or Reset the CC3NP Bit */
mbed_official	52:a51c77007319	1947	tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
mbed_official	52:a51c77007319	1948	tmpccer \|= (uint16_t)(TIM_OCNPolarity << 8);
mbed_official	52:a51c77007319	1949	/* Write to TIMx CCER register */
mbed_official	52:a51c77007319	1950	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1951	}
mbed_official	52:a51c77007319	1952
mbed_official	52:a51c77007319	1953	/**
mbed_official	52:a51c77007319	1954	* @brief Configures the TIMx channel 4 polarity.
mbed_official	52:a51c77007319	1955	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1956	* @param TIM_OCPolarity: specifies the OC4 Polarity
mbed_official	52:a51c77007319	1957	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1958	* @arg TIM_OCPolarity_High: Output Compare active high
mbed_official	52:a51c77007319	1959	* @arg TIM_OCPolarity_Low: Output Compare active low
mbed_official	52:a51c77007319	1960	* @retval None
mbed_official	52:a51c77007319	1961	*/
mbed_official	52:a51c77007319	1962	void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
mbed_official	52:a51c77007319	1963	{
mbed_official	52:a51c77007319	1964	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1965	/* Check the parameters */
mbed_official	52:a51c77007319	1966	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1967	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
mbed_official	52:a51c77007319	1968	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1969	/* Set or Reset the CC4P Bit */
mbed_official	52:a51c77007319	1970	tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
mbed_official	52:a51c77007319	1971	tmpccer \|= (uint16_t)(TIM_OCPolarity << 12);
mbed_official	52:a51c77007319	1972	/* Write to TIMx CCER register */
mbed_official	52:a51c77007319	1973	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1974	}
mbed_official	52:a51c77007319	1975
mbed_official	52:a51c77007319	1976	/**
mbed_official	52:a51c77007319	1977	* @brief Enables or disables the TIM Capture Compare Channel x.
mbed_official	52:a51c77007319	1978	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	1979	* @param TIM_Channel: specifies the TIM Channel
mbed_official	52:a51c77007319	1980	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1981	* @arg TIM_Channel_1: TIM Channel 1
mbed_official	52:a51c77007319	1982	* @arg TIM_Channel_2: TIM Channel 2
mbed_official	52:a51c77007319	1983	* @arg TIM_Channel_3: TIM Channel 3
mbed_official	52:a51c77007319	1984	* @arg TIM_Channel_4: TIM Channel 4
mbed_official	52:a51c77007319	1985	* @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
mbed_official	52:a51c77007319	1986	* This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
mbed_official	52:a51c77007319	1987	* @retval None
mbed_official	52:a51c77007319	1988	*/
mbed_official	52:a51c77007319	1989	void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
mbed_official	52:a51c77007319	1990	{
mbed_official	52:a51c77007319	1991	uint16_t tmp = 0;
mbed_official	52:a51c77007319	1992
mbed_official	52:a51c77007319	1993	/* Check the parameters */
mbed_official	52:a51c77007319	1994	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	1995	assert_param(IS_TIM_CHANNEL(TIM_Channel));
mbed_official	52:a51c77007319	1996	assert_param(IS_TIM_CCX(TIM_CCx));
mbed_official	52:a51c77007319	1997
mbed_official	52:a51c77007319	1998	tmp = CCER_CCE_Set << TIM_Channel;
mbed_official	52:a51c77007319	1999
mbed_official	52:a51c77007319	2000	/* Reset the CCxE Bit */
mbed_official	52:a51c77007319	2001	TIMx->CCER &= (uint16_t)~ tmp;
mbed_official	52:a51c77007319	2002
mbed_official	52:a51c77007319	2003	/* Set or reset the CCxE Bit */
mbed_official	52:a51c77007319	2004	TIMx->CCER \|= (uint16_t)(TIM_CCx << TIM_Channel);
mbed_official	52:a51c77007319	2005	}
mbed_official	52:a51c77007319	2006
mbed_official	52:a51c77007319	2007	/**
mbed_official	52:a51c77007319	2008	* @brief Enables or disables the TIM Capture Compare Channel xN.
mbed_official	52:a51c77007319	2009	* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2010	* @param TIM_Channel: specifies the TIM Channel
mbed_official	52:a51c77007319	2011	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2012	* @arg TIM_Channel_1: TIM Channel 1
mbed_official	52:a51c77007319	2013	* @arg TIM_Channel_2: TIM Channel 2
mbed_official	52:a51c77007319	2014	* @arg TIM_Channel_3: TIM Channel 3
mbed_official	52:a51c77007319	2015	* @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
mbed_official	52:a51c77007319	2016	* This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
mbed_official	52:a51c77007319	2017	* @retval None
mbed_official	52:a51c77007319	2018	*/
mbed_official	52:a51c77007319	2019	void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
mbed_official	52:a51c77007319	2020	{
mbed_official	52:a51c77007319	2021	uint16_t tmp = 0;
mbed_official	52:a51c77007319	2022
mbed_official	52:a51c77007319	2023	/* Check the parameters */
mbed_official	52:a51c77007319	2024	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
mbed_official	52:a51c77007319	2025	assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
mbed_official	52:a51c77007319	2026	assert_param(IS_TIM_CCXN(TIM_CCxN));
mbed_official	52:a51c77007319	2027
mbed_official	52:a51c77007319	2028	tmp = CCER_CCNE_Set << TIM_Channel;
mbed_official	52:a51c77007319	2029
mbed_official	52:a51c77007319	2030	/* Reset the CCxNE Bit */
mbed_official	52:a51c77007319	2031	TIMx->CCER &= (uint16_t) ~tmp;
mbed_official	52:a51c77007319	2032
mbed_official	52:a51c77007319	2033	/* Set or reset the CCxNE Bit */
mbed_official	52:a51c77007319	2034	TIMx->CCER \|= (uint16_t)(TIM_CCxN << TIM_Channel);
mbed_official	52:a51c77007319	2035	}
mbed_official	52:a51c77007319	2036
mbed_official	52:a51c77007319	2037	/**
mbed_official	52:a51c77007319	2038	* @brief Selects the TIM Output Compare Mode.
mbed_official	52:a51c77007319	2039	* @note This function disables the selected channel before changing the Output
mbed_official	52:a51c77007319	2040	* Compare Mode.
mbed_official	52:a51c77007319	2041	* User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
mbed_official	52:a51c77007319	2042	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	2043	* @param TIM_Channel: specifies the TIM Channel
mbed_official	52:a51c77007319	2044	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2045	* @arg TIM_Channel_1: TIM Channel 1
mbed_official	52:a51c77007319	2046	* @arg TIM_Channel_2: TIM Channel 2
mbed_official	52:a51c77007319	2047	* @arg TIM_Channel_3: TIM Channel 3
mbed_official	52:a51c77007319	2048	* @arg TIM_Channel_4: TIM Channel 4
mbed_official	52:a51c77007319	2049	* @param TIM_OCMode: specifies the TIM Output Compare Mode.
mbed_official	52:a51c77007319	2050	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2051	* @arg TIM_OCMode_Timing
mbed_official	52:a51c77007319	2052	* @arg TIM_OCMode_Active
mbed_official	52:a51c77007319	2053	* @arg TIM_OCMode_Toggle
mbed_official	52:a51c77007319	2054	* @arg TIM_OCMode_PWM1
mbed_official	52:a51c77007319	2055	* @arg TIM_OCMode_PWM2
mbed_official	52:a51c77007319	2056	* @arg TIM_ForcedAction_Active
mbed_official	52:a51c77007319	2057	* @arg TIM_ForcedAction_InActive
mbed_official	52:a51c77007319	2058	* @retval None
mbed_official	52:a51c77007319	2059	*/
mbed_official	52:a51c77007319	2060	void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
mbed_official	52:a51c77007319	2061	{
mbed_official	52:a51c77007319	2062	uint32_t tmp = 0;
mbed_official	52:a51c77007319	2063	uint16_t tmp1 = 0;
mbed_official	52:a51c77007319	2064
mbed_official	52:a51c77007319	2065	/* Check the parameters */
mbed_official	52:a51c77007319	2066	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	2067	assert_param(IS_TIM_CHANNEL(TIM_Channel));
mbed_official	52:a51c77007319	2068	assert_param(IS_TIM_OCM(TIM_OCMode));
mbed_official	52:a51c77007319	2069
mbed_official	52:a51c77007319	2070	tmp = (uint32_t) TIMx;
mbed_official	52:a51c77007319	2071	tmp += CCMR_Offset;
mbed_official	52:a51c77007319	2072
mbed_official	52:a51c77007319	2073	tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
mbed_official	52:a51c77007319	2074
mbed_official	52:a51c77007319	2075	/* Disable the Channel: Reset the CCxE Bit */
mbed_official	52:a51c77007319	2076	TIMx->CCER &= (uint16_t) ~tmp1;
mbed_official	52:a51c77007319	2077
mbed_official	52:a51c77007319	2078	if((TIM_Channel == TIM_Channel_1) \|\|(TIM_Channel == TIM_Channel_3))
mbed_official	52:a51c77007319	2079	{
mbed_official	52:a51c77007319	2080	tmp += (TIM_Channel>>1);
mbed_official	52:a51c77007319	2081
mbed_official	52:a51c77007319	2082	/* Reset the OCxM bits in the CCMRx register */
mbed_official	52:a51c77007319	2083	(__IO uint32_t ) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
mbed_official	52:a51c77007319	2084
mbed_official	52:a51c77007319	2085	/* Configure the OCxM bits in the CCMRx register */
mbed_official	52:a51c77007319	2086	(__IO uint32_t ) tmp \|= TIM_OCMode;
mbed_official	52:a51c77007319	2087	}
mbed_official	52:a51c77007319	2088	else
mbed_official	52:a51c77007319	2089	{
mbed_official	52:a51c77007319	2090	tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
mbed_official	52:a51c77007319	2091
mbed_official	52:a51c77007319	2092	/* Reset the OCxM bits in the CCMRx register */
mbed_official	52:a51c77007319	2093	(__IO uint32_t ) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
mbed_official	52:a51c77007319	2094
mbed_official	52:a51c77007319	2095	/* Configure the OCxM bits in the CCMRx register */
mbed_official	52:a51c77007319	2096	(__IO uint32_t ) tmp \|= (uint16_t)(TIM_OCMode << 8);
mbed_official	52:a51c77007319	2097	}
mbed_official	52:a51c77007319	2098	}
mbed_official	52:a51c77007319	2099
mbed_official	52:a51c77007319	2100	/**
mbed_official	52:a51c77007319	2101	* @brief Enables or Disables the TIMx Update event.
mbed_official	52:a51c77007319	2102	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2103	* @param NewState: new state of the TIMx UDIS bit
mbed_official	52:a51c77007319	2104	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	2105	* @retval None
mbed_official	52:a51c77007319	2106	*/
mbed_official	52:a51c77007319	2107	void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	2108	{
mbed_official	52:a51c77007319	2109	/* Check the parameters */
mbed_official	52:a51c77007319	2110	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2111	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	2112	if (NewState != DISABLE)
mbed_official	52:a51c77007319	2113	{
mbed_official	52:a51c77007319	2114	/* Set the Update Disable Bit */
mbed_official	52:a51c77007319	2115	TIMx->CR1 \|= TIM_CR1_UDIS;
mbed_official	52:a51c77007319	2116	}
mbed_official	52:a51c77007319	2117	else
mbed_official	52:a51c77007319	2118	{
mbed_official	52:a51c77007319	2119	/* Reset the Update Disable Bit */
mbed_official	52:a51c77007319	2120	TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
mbed_official	52:a51c77007319	2121	}
mbed_official	52:a51c77007319	2122	}
mbed_official	52:a51c77007319	2123
mbed_official	52:a51c77007319	2124	/**
mbed_official	52:a51c77007319	2125	* @brief Configures the TIMx Update Request Interrupt source.
mbed_official	52:a51c77007319	2126	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2127	* @param TIM_UpdateSource: specifies the Update source.
mbed_official	52:a51c77007319	2128	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2129	* @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
mbed_official	52:a51c77007319	2130	or the setting of UG bit, or an update generation
mbed_official	52:a51c77007319	2131	through the slave mode controller.
mbed_official	52:a51c77007319	2132	* @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
mbed_official	52:a51c77007319	2133	* @retval None
mbed_official	52:a51c77007319	2134	*/
mbed_official	52:a51c77007319	2135	void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
mbed_official	52:a51c77007319	2136	{
mbed_official	52:a51c77007319	2137	/* Check the parameters */
mbed_official	52:a51c77007319	2138	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2139	assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
mbed_official	52:a51c77007319	2140	if (TIM_UpdateSource != TIM_UpdateSource_Global)
mbed_official	52:a51c77007319	2141	{
mbed_official	52:a51c77007319	2142	/* Set the URS Bit */
mbed_official	52:a51c77007319	2143	TIMx->CR1 \|= TIM_CR1_URS;
mbed_official	52:a51c77007319	2144	}
mbed_official	52:a51c77007319	2145	else
mbed_official	52:a51c77007319	2146	{
mbed_official	52:a51c77007319	2147	/* Reset the URS Bit */
mbed_official	52:a51c77007319	2148	TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
mbed_official	52:a51c77007319	2149	}
mbed_official	52:a51c77007319	2150	}
mbed_official	52:a51c77007319	2151
mbed_official	52:a51c77007319	2152	/**
mbed_official	52:a51c77007319	2153	* @brief Enables or disables the TIMx's Hall sensor interface.
mbed_official	52:a51c77007319	2154	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2155	* @param NewState: new state of the TIMx Hall sensor interface.
mbed_official	52:a51c77007319	2156	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	2157	* @retval None
mbed_official	52:a51c77007319	2158	*/
mbed_official	52:a51c77007319	2159	void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	2160	{
mbed_official	52:a51c77007319	2161	/* Check the parameters */
mbed_official	52:a51c77007319	2162	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	2163	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	2164	if (NewState != DISABLE)
mbed_official	52:a51c77007319	2165	{
mbed_official	52:a51c77007319	2166	/* Set the TI1S Bit */
mbed_official	52:a51c77007319	2167	TIMx->CR2 \|= TIM_CR2_TI1S;
mbed_official	52:a51c77007319	2168	}
mbed_official	52:a51c77007319	2169	else
mbed_official	52:a51c77007319	2170	{
mbed_official	52:a51c77007319	2171	/* Reset the TI1S Bit */
mbed_official	52:a51c77007319	2172	TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
mbed_official	52:a51c77007319	2173	}
mbed_official	52:a51c77007319	2174	}
mbed_official	52:a51c77007319	2175
mbed_official	52:a51c77007319	2176	/**
mbed_official	52:a51c77007319	2177	* @brief Selects the TIMx's One Pulse Mode.
mbed_official	52:a51c77007319	2178	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2179	* @param TIM_OPMode: specifies the OPM Mode to be used.
mbed_official	52:a51c77007319	2180	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2181	* @arg TIM_OPMode_Single
mbed_official	52:a51c77007319	2182	* @arg TIM_OPMode_Repetitive
mbed_official	52:a51c77007319	2183	* @retval None
mbed_official	52:a51c77007319	2184	*/
mbed_official	52:a51c77007319	2185	void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
mbed_official	52:a51c77007319	2186	{
mbed_official	52:a51c77007319	2187	/* Check the parameters */
mbed_official	52:a51c77007319	2188	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2189	assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
mbed_official	52:a51c77007319	2190	/* Reset the OPM Bit */
mbed_official	52:a51c77007319	2191	TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
mbed_official	52:a51c77007319	2192	/* Configure the OPM Mode */
mbed_official	52:a51c77007319	2193	TIMx->CR1 \|= TIM_OPMode;
mbed_official	52:a51c77007319	2194	}
mbed_official	52:a51c77007319	2195
mbed_official	52:a51c77007319	2196	/**
mbed_official	52:a51c77007319	2197	* @brief Selects the TIMx Trigger Output Mode.
mbed_official	52:a51c77007319	2198	* @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	2199	* @param TIM_TRGOSource: specifies the Trigger Output source.
mbed_official	52:a51c77007319	2200	* This paramter can be one of the following values:
mbed_official	52:a51c77007319	2201	*
mbed_official	52:a51c77007319	2202	* - For all TIMx
mbed_official	52:a51c77007319	2203	* @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
mbed_official	52:a51c77007319	2204	* @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
mbed_official	52:a51c77007319	2205	* @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
mbed_official	52:a51c77007319	2206	*
mbed_official	52:a51c77007319	2207	* - For all TIMx except TIM6 and TIM7
mbed_official	52:a51c77007319	2208	* @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
mbed_official	52:a51c77007319	2209	* is to be set, as soon as a capture or compare match occurs (TRGO).
mbed_official	52:a51c77007319	2210	* @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
mbed_official	52:a51c77007319	2211	* @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
mbed_official	52:a51c77007319	2212	* @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
mbed_official	52:a51c77007319	2213	* @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
mbed_official	52:a51c77007319	2214	*
mbed_official	52:a51c77007319	2215	* @retval None
mbed_official	52:a51c77007319	2216	*/
mbed_official	52:a51c77007319	2217	void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
mbed_official	52:a51c77007319	2218	{
mbed_official	52:a51c77007319	2219	/* Check the parameters */
mbed_official	52:a51c77007319	2220	assert_param(IS_TIM_LIST7_PERIPH(TIMx));
mbed_official	52:a51c77007319	2221	assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
mbed_official	52:a51c77007319	2222	/* Reset the MMS Bits */
mbed_official	52:a51c77007319	2223	TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
mbed_official	52:a51c77007319	2224	/* Select the TRGO source */
mbed_official	52:a51c77007319	2225	TIMx->CR2 \|= TIM_TRGOSource;
mbed_official	52:a51c77007319	2226	}
mbed_official	52:a51c77007319	2227
mbed_official	52:a51c77007319	2228	/**
mbed_official	52:a51c77007319	2229	* @brief Selects the TIMx Slave Mode.
mbed_official	52:a51c77007319	2230	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	2231	* @param TIM_SlaveMode: specifies the Timer Slave Mode.
mbed_official	52:a51c77007319	2232	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2233	* @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
mbed_official	52:a51c77007319	2234	* the counter and triggers an update of the registers.
mbed_official	52:a51c77007319	2235	* @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
mbed_official	52:a51c77007319	2236	* @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
mbed_official	52:a51c77007319	2237	* @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
mbed_official	52:a51c77007319	2238	* @retval None
mbed_official	52:a51c77007319	2239	*/
mbed_official	52:a51c77007319	2240	void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
mbed_official	52:a51c77007319	2241	{
mbed_official	52:a51c77007319	2242	/* Check the parameters */
mbed_official	52:a51c77007319	2243	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	2244	assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
mbed_official	52:a51c77007319	2245	/* Reset the SMS Bits */
mbed_official	52:a51c77007319	2246	TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
mbed_official	52:a51c77007319	2247	/* Select the Slave Mode */
mbed_official	52:a51c77007319	2248	TIMx->SMCR \|= TIM_SlaveMode;
mbed_official	52:a51c77007319	2249	}
mbed_official	52:a51c77007319	2250
mbed_official	52:a51c77007319	2251	/**
mbed_official	52:a51c77007319	2252	* @brief Sets or Resets the TIMx Master/Slave Mode.
mbed_official	52:a51c77007319	2253	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	2254	* @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
mbed_official	52:a51c77007319	2255	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2256	* @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
mbed_official	52:a51c77007319	2257	* and its slaves (through TRGO).
mbed_official	52:a51c77007319	2258	* @arg TIM_MasterSlaveMode_Disable: No action
mbed_official	52:a51c77007319	2259	* @retval None
mbed_official	52:a51c77007319	2260	*/
mbed_official	52:a51c77007319	2261	void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
mbed_official	52:a51c77007319	2262	{
mbed_official	52:a51c77007319	2263	/* Check the parameters */
mbed_official	52:a51c77007319	2264	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	2265	assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
mbed_official	52:a51c77007319	2266	/* Reset the MSM Bit */
mbed_official	52:a51c77007319	2267	TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
mbed_official	52:a51c77007319	2268
mbed_official	52:a51c77007319	2269	/* Set or Reset the MSM Bit */
mbed_official	52:a51c77007319	2270	TIMx->SMCR \|= TIM_MasterSlaveMode;
mbed_official	52:a51c77007319	2271	}
mbed_official	52:a51c77007319	2272
mbed_official	52:a51c77007319	2273	/**
mbed_official	52:a51c77007319	2274	* @brief Sets the TIMx Counter Register value
mbed_official	52:a51c77007319	2275	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2276	* @param Counter: specifies the Counter register new value.
mbed_official	52:a51c77007319	2277	* @retval None
mbed_official	52:a51c77007319	2278	*/
mbed_official	52:a51c77007319	2279	void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
mbed_official	52:a51c77007319	2280	{
mbed_official	52:a51c77007319	2281	/* Check the parameters */
mbed_official	52:a51c77007319	2282	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2283	/* Set the Counter Register value */
mbed_official	52:a51c77007319	2284	TIMx->CNT = Counter;
mbed_official	52:a51c77007319	2285	}
mbed_official	52:a51c77007319	2286
mbed_official	52:a51c77007319	2287	/**
mbed_official	52:a51c77007319	2288	* @brief Sets the TIMx Autoreload Register value
mbed_official	52:a51c77007319	2289	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2290	* @param Autoreload: specifies the Autoreload register new value.
mbed_official	52:a51c77007319	2291	* @retval None
mbed_official	52:a51c77007319	2292	*/
mbed_official	52:a51c77007319	2293	void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
mbed_official	52:a51c77007319	2294	{
mbed_official	52:a51c77007319	2295	/* Check the parameters */
mbed_official	52:a51c77007319	2296	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2297	/* Set the Autoreload Register value */
mbed_official	52:a51c77007319	2298	TIMx->ARR = Autoreload;
mbed_official	52:a51c77007319	2299	}
mbed_official	52:a51c77007319	2300
mbed_official	52:a51c77007319	2301	/**
mbed_official	52:a51c77007319	2302	* @brief Sets the TIMx Capture Compare1 Register value
mbed_official	52:a51c77007319	2303	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	2304	* @param Compare1: specifies the Capture Compare1 register new value.
mbed_official	52:a51c77007319	2305	* @retval None
mbed_official	52:a51c77007319	2306	*/
mbed_official	52:a51c77007319	2307	void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
mbed_official	52:a51c77007319	2308	{
mbed_official	52:a51c77007319	2309	/* Check the parameters */
mbed_official	52:a51c77007319	2310	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	2311	/* Set the Capture Compare1 Register value */
mbed_official	52:a51c77007319	2312	TIMx->CCR1 = Compare1;
mbed_official	52:a51c77007319	2313	}
mbed_official	52:a51c77007319	2314
mbed_official	52:a51c77007319	2315	/**
mbed_official	52:a51c77007319	2316	* @brief Sets the TIMx Capture Compare2 Register value
mbed_official	52:a51c77007319	2317	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	2318	* @param Compare2: specifies the Capture Compare2 register new value.
mbed_official	52:a51c77007319	2319	* @retval None
mbed_official	52:a51c77007319	2320	*/
mbed_official	52:a51c77007319	2321	void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
mbed_official	52:a51c77007319	2322	{
mbed_official	52:a51c77007319	2323	/* Check the parameters */
mbed_official	52:a51c77007319	2324	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	2325	/* Set the Capture Compare2 Register value */
mbed_official	52:a51c77007319	2326	TIMx->CCR2 = Compare2;
mbed_official	52:a51c77007319	2327	}
mbed_official	52:a51c77007319	2328
mbed_official	52:a51c77007319	2329	/**
mbed_official	52:a51c77007319	2330	* @brief Sets the TIMx Capture Compare3 Register value
mbed_official	52:a51c77007319	2331	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2332	* @param Compare3: specifies the Capture Compare3 register new value.
mbed_official	52:a51c77007319	2333	* @retval None
mbed_official	52:a51c77007319	2334	*/
mbed_official	52:a51c77007319	2335	void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
mbed_official	52:a51c77007319	2336	{
mbed_official	52:a51c77007319	2337	/* Check the parameters */
mbed_official	52:a51c77007319	2338	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	2339	/* Set the Capture Compare3 Register value */
mbed_official	52:a51c77007319	2340	TIMx->CCR3 = Compare3;
mbed_official	52:a51c77007319	2341	}
mbed_official	52:a51c77007319	2342
mbed_official	52:a51c77007319	2343	/**
mbed_official	52:a51c77007319	2344	* @brief Sets the TIMx Capture Compare4 Register value
mbed_official	52:a51c77007319	2345	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2346	* @param Compare4: specifies the Capture Compare4 register new value.
mbed_official	52:a51c77007319	2347	* @retval None
mbed_official	52:a51c77007319	2348	*/
mbed_official	52:a51c77007319	2349	void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
mbed_official	52:a51c77007319	2350	{
mbed_official	52:a51c77007319	2351	/* Check the parameters */
mbed_official	52:a51c77007319	2352	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	2353	/* Set the Capture Compare4 Register value */
mbed_official	52:a51c77007319	2354	TIMx->CCR4 = Compare4;
mbed_official	52:a51c77007319	2355	}
mbed_official	52:a51c77007319	2356
mbed_official	52:a51c77007319	2357	/**
mbed_official	52:a51c77007319	2358	* @brief Sets the TIMx Input Capture 1 prescaler.
mbed_official	52:a51c77007319	2359	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	2360	* @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
mbed_official	52:a51c77007319	2361	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2362	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	52:a51c77007319	2363	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	52:a51c77007319	2364	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	52:a51c77007319	2365	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	52:a51c77007319	2366	* @retval None
mbed_official	52:a51c77007319	2367	*/
mbed_official	52:a51c77007319	2368	void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
mbed_official	52:a51c77007319	2369	{
mbed_official	52:a51c77007319	2370	/* Check the parameters */
mbed_official	52:a51c77007319	2371	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	2372	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
mbed_official	52:a51c77007319	2373	/* Reset the IC1PSC Bits */
mbed_official	52:a51c77007319	2374	TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
mbed_official	52:a51c77007319	2375	/* Set the IC1PSC value */
mbed_official	52:a51c77007319	2376	TIMx->CCMR1 \|= TIM_ICPSC;
mbed_official	52:a51c77007319	2377	}
mbed_official	52:a51c77007319	2378
mbed_official	52:a51c77007319	2379	/**
mbed_official	52:a51c77007319	2380	* @brief Sets the TIMx Input Capture 2 prescaler.
mbed_official	52:a51c77007319	2381	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	2382	* @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
mbed_official	52:a51c77007319	2383	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2384	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	52:a51c77007319	2385	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	52:a51c77007319	2386	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	52:a51c77007319	2387	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	52:a51c77007319	2388	* @retval None
mbed_official	52:a51c77007319	2389	*/
mbed_official	52:a51c77007319	2390	void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
mbed_official	52:a51c77007319	2391	{
mbed_official	52:a51c77007319	2392	/* Check the parameters */
mbed_official	52:a51c77007319	2393	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	2394	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
mbed_official	52:a51c77007319	2395	/* Reset the IC2PSC Bits */
mbed_official	52:a51c77007319	2396	TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
mbed_official	52:a51c77007319	2397	/* Set the IC2PSC value */
mbed_official	52:a51c77007319	2398	TIMx->CCMR1 \|= (uint16_t)(TIM_ICPSC << 8);
mbed_official	52:a51c77007319	2399	}
mbed_official	52:a51c77007319	2400
mbed_official	52:a51c77007319	2401	/**
mbed_official	52:a51c77007319	2402	* @brief Sets the TIMx Input Capture 3 prescaler.
mbed_official	52:a51c77007319	2403	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2404	* @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
mbed_official	52:a51c77007319	2405	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2406	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	52:a51c77007319	2407	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	52:a51c77007319	2408	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	52:a51c77007319	2409	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	52:a51c77007319	2410	* @retval None
mbed_official	52:a51c77007319	2411	*/
mbed_official	52:a51c77007319	2412	void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
mbed_official	52:a51c77007319	2413	{
mbed_official	52:a51c77007319	2414	/* Check the parameters */
mbed_official	52:a51c77007319	2415	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	2416	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
mbed_official	52:a51c77007319	2417	/* Reset the IC3PSC Bits */
mbed_official	52:a51c77007319	2418	TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
mbed_official	52:a51c77007319	2419	/* Set the IC3PSC value */
mbed_official	52:a51c77007319	2420	TIMx->CCMR2 \|= TIM_ICPSC;
mbed_official	52:a51c77007319	2421	}
mbed_official	52:a51c77007319	2422
mbed_official	52:a51c77007319	2423	/**
mbed_official	52:a51c77007319	2424	* @brief Sets the TIMx Input Capture 4 prescaler.
mbed_official	52:a51c77007319	2425	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2426	* @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
mbed_official	52:a51c77007319	2427	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2428	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	52:a51c77007319	2429	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	52:a51c77007319	2430	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	52:a51c77007319	2431	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	52:a51c77007319	2432	* @retval None
mbed_official	52:a51c77007319	2433	*/
mbed_official	52:a51c77007319	2434	void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
mbed_official	52:a51c77007319	2435	{
mbed_official	52:a51c77007319	2436	/* Check the parameters */
mbed_official	52:a51c77007319	2437	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	2438	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
mbed_official	52:a51c77007319	2439	/* Reset the IC4PSC Bits */
mbed_official	52:a51c77007319	2440	TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
mbed_official	52:a51c77007319	2441	/* Set the IC4PSC value */
mbed_official	52:a51c77007319	2442	TIMx->CCMR2 \|= (uint16_t)(TIM_ICPSC << 8);
mbed_official	52:a51c77007319	2443	}
mbed_official	52:a51c77007319	2444
mbed_official	52:a51c77007319	2445	/**
mbed_official	52:a51c77007319	2446	* @brief Sets the TIMx Clock Division value.
mbed_official	52:a51c77007319	2447	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select
mbed_official	52:a51c77007319	2448	* the TIM peripheral.
mbed_official	52:a51c77007319	2449	* @param TIM_CKD: specifies the clock division value.
mbed_official	52:a51c77007319	2450	* This parameter can be one of the following value:
mbed_official	52:a51c77007319	2451	* @arg TIM_CKD_DIV1: TDTS = Tck_tim
mbed_official	52:a51c77007319	2452	* @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
mbed_official	52:a51c77007319	2453	* @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
mbed_official	52:a51c77007319	2454	* @retval None
mbed_official	52:a51c77007319	2455	*/
mbed_official	52:a51c77007319	2456	void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
mbed_official	52:a51c77007319	2457	{
mbed_official	52:a51c77007319	2458	/* Check the parameters */
mbed_official	52:a51c77007319	2459	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	2460	assert_param(IS_TIM_CKD_DIV(TIM_CKD));
mbed_official	52:a51c77007319	2461	/* Reset the CKD Bits */
mbed_official	52:a51c77007319	2462	TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
mbed_official	52:a51c77007319	2463	/* Set the CKD value */
mbed_official	52:a51c77007319	2464	TIMx->CR1 \|= TIM_CKD;
mbed_official	52:a51c77007319	2465	}
mbed_official	52:a51c77007319	2466
mbed_official	52:a51c77007319	2467	/**
mbed_official	52:a51c77007319	2468	* @brief Gets the TIMx Input Capture 1 value.
mbed_official	52:a51c77007319	2469	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	2470	* @retval Capture Compare 1 Register value.
mbed_official	52:a51c77007319	2471	*/
mbed_official	52:a51c77007319	2472	uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	2473	{
mbed_official	52:a51c77007319	2474	/* Check the parameters */
mbed_official	52:a51c77007319	2475	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	2476	/* Get the Capture 1 Register value */
mbed_official	52:a51c77007319	2477	return TIMx->CCR1;
mbed_official	52:a51c77007319	2478	}
mbed_official	52:a51c77007319	2479
mbed_official	52:a51c77007319	2480	/**
mbed_official	52:a51c77007319	2481	* @brief Gets the TIMx Input Capture 2 value.
mbed_official	52:a51c77007319	2482	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	2483	* @retval Capture Compare 2 Register value.
mbed_official	52:a51c77007319	2484	*/
mbed_official	52:a51c77007319	2485	uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	2486	{
mbed_official	52:a51c77007319	2487	/* Check the parameters */
mbed_official	52:a51c77007319	2488	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	2489	/* Get the Capture 2 Register value */
mbed_official	52:a51c77007319	2490	return TIMx->CCR2;
mbed_official	52:a51c77007319	2491	}
mbed_official	52:a51c77007319	2492
mbed_official	52:a51c77007319	2493	/**
mbed_official	52:a51c77007319	2494	* @brief Gets the TIMx Input Capture 3 value.
mbed_official	52:a51c77007319	2495	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2496	* @retval Capture Compare 3 Register value.
mbed_official	52:a51c77007319	2497	*/
mbed_official	52:a51c77007319	2498	uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	2499	{
mbed_official	52:a51c77007319	2500	/* Check the parameters */
mbed_official	52:a51c77007319	2501	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	2502	/* Get the Capture 3 Register value */
mbed_official	52:a51c77007319	2503	return TIMx->CCR3;
mbed_official	52:a51c77007319	2504	}
mbed_official	52:a51c77007319	2505
mbed_official	52:a51c77007319	2506	/**
mbed_official	52:a51c77007319	2507	* @brief Gets the TIMx Input Capture 4 value.
mbed_official	52:a51c77007319	2508	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2509	* @retval Capture Compare 4 Register value.
mbed_official	52:a51c77007319	2510	*/
mbed_official	52:a51c77007319	2511	uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	2512	{
mbed_official	52:a51c77007319	2513	/* Check the parameters */
mbed_official	52:a51c77007319	2514	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	2515	/* Get the Capture 4 Register value */
mbed_official	52:a51c77007319	2516	return TIMx->CCR4;
mbed_official	52:a51c77007319	2517	}
mbed_official	52:a51c77007319	2518
mbed_official	52:a51c77007319	2519	/**
mbed_official	52:a51c77007319	2520	* @brief Gets the TIMx Counter value.
mbed_official	52:a51c77007319	2521	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2522	* @retval Counter Register value.
mbed_official	52:a51c77007319	2523	*/
mbed_official	52:a51c77007319	2524	uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	2525	{
mbed_official	52:a51c77007319	2526	/* Check the parameters */
mbed_official	52:a51c77007319	2527	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2528	/* Get the Counter Register value */
mbed_official	52:a51c77007319	2529	return TIMx->CNT;
mbed_official	52:a51c77007319	2530	}
mbed_official	52:a51c77007319	2531
mbed_official	52:a51c77007319	2532	/**
mbed_official	52:a51c77007319	2533	* @brief Gets the TIMx Prescaler value.
mbed_official	52:a51c77007319	2534	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2535	* @retval Prescaler Register value.
mbed_official	52:a51c77007319	2536	*/
mbed_official	52:a51c77007319	2537	uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	2538	{
mbed_official	52:a51c77007319	2539	/* Check the parameters */
mbed_official	52:a51c77007319	2540	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2541	/* Get the Prescaler Register value */
mbed_official	52:a51c77007319	2542	return TIMx->PSC;
mbed_official	52:a51c77007319	2543	}
mbed_official	52:a51c77007319	2544
mbed_official	52:a51c77007319	2545	/**
mbed_official	52:a51c77007319	2546	* @brief Checks whether the specified TIM flag is set or not.
mbed_official	52:a51c77007319	2547	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2548	* @param TIM_FLAG: specifies the flag to check.
mbed_official	52:a51c77007319	2549	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2550	* @arg TIM_FLAG_Update: TIM update Flag
mbed_official	52:a51c77007319	2551	* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
mbed_official	52:a51c77007319	2552	* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
mbed_official	52:a51c77007319	2553	* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
mbed_official	52:a51c77007319	2554	* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
mbed_official	52:a51c77007319	2555	* @arg TIM_FLAG_COM: TIM Commutation Flag
mbed_official	52:a51c77007319	2556	* @arg TIM_FLAG_Trigger: TIM Trigger Flag
mbed_official	52:a51c77007319	2557	* @arg TIM_FLAG_Break: TIM Break Flag
mbed_official	52:a51c77007319	2558	* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
mbed_official	52:a51c77007319	2559	* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
mbed_official	52:a51c77007319	2560	* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
mbed_official	52:a51c77007319	2561	* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
mbed_official	52:a51c77007319	2562	* @note
mbed_official	52:a51c77007319	2563	* - TIM6 and TIM7 can have only one update flag.
mbed_official	52:a51c77007319	2564	* - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
mbed_official	52:a51c77007319	2565	* TIM_FLAG_CC2 or TIM_FLAG_Trigger.
mbed_official	52:a51c77007319	2566	* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
mbed_official	52:a51c77007319	2567	* - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
mbed_official	52:a51c77007319	2568	* - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
mbed_official	52:a51c77007319	2569	* @retval The new state of TIM_FLAG (SET or RESET).
mbed_official	52:a51c77007319	2570	*/
mbed_official	52:a51c77007319	2571	FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
mbed_official	52:a51c77007319	2572	{
mbed_official	52:a51c77007319	2573	ITStatus bitstatus = RESET;
mbed_official	52:a51c77007319	2574	/* Check the parameters */
mbed_official	52:a51c77007319	2575	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2576	assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
mbed_official	52:a51c77007319	2577
mbed_official	52:a51c77007319	2578	if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
mbed_official	52:a51c77007319	2579	{
mbed_official	52:a51c77007319	2580	bitstatus = SET;
mbed_official	52:a51c77007319	2581	}
mbed_official	52:a51c77007319	2582	else
mbed_official	52:a51c77007319	2583	{
mbed_official	52:a51c77007319	2584	bitstatus = RESET;
mbed_official	52:a51c77007319	2585	}
mbed_official	52:a51c77007319	2586	return bitstatus;
mbed_official	52:a51c77007319	2587	}
mbed_official	52:a51c77007319	2588
mbed_official	52:a51c77007319	2589	/**
mbed_official	52:a51c77007319	2590	* @brief Clears the TIMx's pending flags.
mbed_official	52:a51c77007319	2591	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2592	* @param TIM_FLAG: specifies the flag bit to clear.
mbed_official	52:a51c77007319	2593	* This parameter can be any combination of the following values:
mbed_official	52:a51c77007319	2594	* @arg TIM_FLAG_Update: TIM update Flag
mbed_official	52:a51c77007319	2595	* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
mbed_official	52:a51c77007319	2596	* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
mbed_official	52:a51c77007319	2597	* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
mbed_official	52:a51c77007319	2598	* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
mbed_official	52:a51c77007319	2599	* @arg TIM_FLAG_COM: TIM Commutation Flag
mbed_official	52:a51c77007319	2600	* @arg TIM_FLAG_Trigger: TIM Trigger Flag
mbed_official	52:a51c77007319	2601	* @arg TIM_FLAG_Break: TIM Break Flag
mbed_official	52:a51c77007319	2602	* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
mbed_official	52:a51c77007319	2603	* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
mbed_official	52:a51c77007319	2604	* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
mbed_official	52:a51c77007319	2605	* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
mbed_official	52:a51c77007319	2606	* @note
mbed_official	52:a51c77007319	2607	* - TIM6 and TIM7 can have only one update flag.
mbed_official	52:a51c77007319	2608	* - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
mbed_official	52:a51c77007319	2609	* TIM_FLAG_CC2 or TIM_FLAG_Trigger.
mbed_official	52:a51c77007319	2610	* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
mbed_official	52:a51c77007319	2611	* - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
mbed_official	52:a51c77007319	2612	* - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
mbed_official	52:a51c77007319	2613	* @retval None
mbed_official	52:a51c77007319	2614	*/
mbed_official	52:a51c77007319	2615	void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
mbed_official	52:a51c77007319	2616	{
mbed_official	52:a51c77007319	2617	/* Check the parameters */
mbed_official	52:a51c77007319	2618	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2619	assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
mbed_official	52:a51c77007319	2620
mbed_official	52:a51c77007319	2621	/* Clear the flags */
mbed_official	52:a51c77007319	2622	TIMx->SR = (uint16_t)~TIM_FLAG;
mbed_official	52:a51c77007319	2623	}
mbed_official	52:a51c77007319	2624
mbed_official	52:a51c77007319	2625	/**
mbed_official	52:a51c77007319	2626	* @brief Checks whether the TIM interrupt has occurred or not.
mbed_official	52:a51c77007319	2627	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2628	* @param TIM_IT: specifies the TIM interrupt source to check.
mbed_official	52:a51c77007319	2629	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2630	* @arg TIM_IT_Update: TIM update Interrupt source
mbed_official	52:a51c77007319	2631	* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
mbed_official	52:a51c77007319	2632	* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
mbed_official	52:a51c77007319	2633	* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
mbed_official	52:a51c77007319	2634	* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
mbed_official	52:a51c77007319	2635	* @arg TIM_IT_COM: TIM Commutation Interrupt source
mbed_official	52:a51c77007319	2636	* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
mbed_official	52:a51c77007319	2637	* @arg TIM_IT_Break: TIM Break Interrupt source
mbed_official	52:a51c77007319	2638	* @note
mbed_official	52:a51c77007319	2639	* - TIM6 and TIM7 can generate only an update interrupt.
mbed_official	52:a51c77007319	2640	* - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
mbed_official	52:a51c77007319	2641	* TIM_IT_CC2 or TIM_IT_Trigger.
mbed_official	52:a51c77007319	2642	* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
mbed_official	52:a51c77007319	2643	* - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
mbed_official	52:a51c77007319	2644	* - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
mbed_official	52:a51c77007319	2645	* @retval The new state of the TIM_IT(SET or RESET).
mbed_official	52:a51c77007319	2646	*/
mbed_official	52:a51c77007319	2647	ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
mbed_official	52:a51c77007319	2648	{
mbed_official	52:a51c77007319	2649	ITStatus bitstatus = RESET;
mbed_official	52:a51c77007319	2650	uint16_t itstatus = 0x0, itenable = 0x0;
mbed_official	52:a51c77007319	2651	/* Check the parameters */
mbed_official	52:a51c77007319	2652	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2653	assert_param(IS_TIM_GET_IT(TIM_IT));
mbed_official	52:a51c77007319	2654
mbed_official	52:a51c77007319	2655	itstatus = TIMx->SR & TIM_IT;
mbed_official	52:a51c77007319	2656
mbed_official	52:a51c77007319	2657	itenable = TIMx->DIER & TIM_IT;
mbed_official	52:a51c77007319	2658	if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
mbed_official	52:a51c77007319	2659	{
mbed_official	52:a51c77007319	2660	bitstatus = SET;
mbed_official	52:a51c77007319	2661	}
mbed_official	52:a51c77007319	2662	else
mbed_official	52:a51c77007319	2663	{
mbed_official	52:a51c77007319	2664	bitstatus = RESET;
mbed_official	52:a51c77007319	2665	}
mbed_official	52:a51c77007319	2666	return bitstatus;
mbed_official	52:a51c77007319	2667	}
mbed_official	52:a51c77007319	2668
mbed_official	52:a51c77007319	2669	/**
mbed_official	52:a51c77007319	2670	* @brief Clears the TIMx's interrupt pending bits.
mbed_official	52:a51c77007319	2671	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2672	* @param TIM_IT: specifies the pending bit to clear.
mbed_official	52:a51c77007319	2673	* This parameter can be any combination of the following values:
mbed_official	52:a51c77007319	2674	* @arg TIM_IT_Update: TIM1 update Interrupt source
mbed_official	52:a51c77007319	2675	* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
mbed_official	52:a51c77007319	2676	* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
mbed_official	52:a51c77007319	2677	* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
mbed_official	52:a51c77007319	2678	* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
mbed_official	52:a51c77007319	2679	* @arg TIM_IT_COM: TIM Commutation Interrupt source
mbed_official	52:a51c77007319	2680	* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
mbed_official	52:a51c77007319	2681	* @arg TIM_IT_Break: TIM Break Interrupt source
mbed_official	52:a51c77007319	2682	* @note
mbed_official	52:a51c77007319	2683	* - TIM6 and TIM7 can generate only an update interrupt.
mbed_official	52:a51c77007319	2684	* - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
mbed_official	52:a51c77007319	2685	* TIM_IT_CC2 or TIM_IT_Trigger.
mbed_official	52:a51c77007319	2686	* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
mbed_official	52:a51c77007319	2687	* - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
mbed_official	52:a51c77007319	2688	* - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
mbed_official	52:a51c77007319	2689	* @retval None
mbed_official	52:a51c77007319	2690	*/
mbed_official	52:a51c77007319	2691	void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
mbed_official	52:a51c77007319	2692	{
mbed_official	52:a51c77007319	2693	/* Check the parameters */
mbed_official	52:a51c77007319	2694	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2695	assert_param(IS_TIM_IT(TIM_IT));
mbed_official	52:a51c77007319	2696	/* Clear the IT pending Bit */
mbed_official	52:a51c77007319	2697	TIMx->SR = (uint16_t)~TIM_IT;
mbed_official	52:a51c77007319	2698	}
mbed_official	52:a51c77007319	2699
mbed_official	52:a51c77007319	2700	/**
mbed_official	52:a51c77007319	2701	* @brief Configure the TI1 as Input.
mbed_official	52:a51c77007319	2702	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	2703	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	52:a51c77007319	2704	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2705	* @arg TIM_ICPolarity_Rising
mbed_official	52:a51c77007319	2706	* @arg TIM_ICPolarity_Falling
mbed_official	52:a51c77007319	2707	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	52:a51c77007319	2708	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2709	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
mbed_official	52:a51c77007319	2710	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
mbed_official	52:a51c77007319	2711	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
mbed_official	52:a51c77007319	2712	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	52:a51c77007319	2713	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	52:a51c77007319	2714	* @retval None
mbed_official	52:a51c77007319	2715	*/
mbed_official	52:a51c77007319	2716	static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	2717	uint16_t TIM_ICFilter)
mbed_official	52:a51c77007319	2718	{
mbed_official	52:a51c77007319	2719	uint16_t tmpccmr1 = 0, tmpccer = 0;
mbed_official	52:a51c77007319	2720	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	52:a51c77007319	2721	TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
mbed_official	52:a51c77007319	2722	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	2723	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	2724	/* Select the Input and set the filter */
mbed_official	52:a51c77007319	2725	tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
mbed_official	52:a51c77007319	2726	tmpccmr1 \|= (uint16_t)(TIM_ICSelection \| (uint16_t)(TIM_ICFilter << (uint16_t)4));
mbed_official	52:a51c77007319	2727
mbed_official	52:a51c77007319	2728	if((TIMx == TIM1) \|\| (TIMx == TIM8) \|\| (TIMx == TIM2) \|\| (TIMx == TIM3) \|\|
mbed_official	52:a51c77007319	2729	(TIMx == TIM4) \|\|(TIMx == TIM5))
mbed_official	52:a51c77007319	2730	{
mbed_official	52:a51c77007319	2731	/* Select the Polarity and set the CC1E Bit */
mbed_official	52:a51c77007319	2732	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
mbed_official	52:a51c77007319	2733	tmpccer \|= (uint16_t)(TIM_ICPolarity \| (uint16_t)TIM_CCER_CC1E);
mbed_official	52:a51c77007319	2734	}
mbed_official	52:a51c77007319	2735	else
mbed_official	52:a51c77007319	2736	{
mbed_official	52:a51c77007319	2737	/* Select the Polarity and set the CC1E Bit */
mbed_official	52:a51c77007319	2738	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P \| TIM_CCER_CC1NP));
mbed_official	52:a51c77007319	2739	tmpccer \|= (uint16_t)(TIM_ICPolarity \| (uint16_t)TIM_CCER_CC1E);
mbed_official	52:a51c77007319	2740	}
mbed_official	52:a51c77007319	2741
mbed_official	52:a51c77007319	2742	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	52:a51c77007319	2743	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	2744	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	2745	}
mbed_official	52:a51c77007319	2746
mbed_official	52:a51c77007319	2747	/**
mbed_official	52:a51c77007319	2748	* @brief Configure the TI2 as Input.
mbed_official	52:a51c77007319	2749	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	2750	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	52:a51c77007319	2751	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2752	* @arg TIM_ICPolarity_Rising
mbed_official	52:a51c77007319	2753	* @arg TIM_ICPolarity_Falling
mbed_official	52:a51c77007319	2754	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	52:a51c77007319	2755	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2756	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
mbed_official	52:a51c77007319	2757	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
mbed_official	52:a51c77007319	2758	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
mbed_official	52:a51c77007319	2759	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	52:a51c77007319	2760	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	52:a51c77007319	2761	* @retval None
mbed_official	52:a51c77007319	2762	*/
mbed_official	52:a51c77007319	2763	static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	2764	uint16_t TIM_ICFilter)
mbed_official	52:a51c77007319	2765	{
mbed_official	52:a51c77007319	2766	uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
mbed_official	52:a51c77007319	2767	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	52:a51c77007319	2768	TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
mbed_official	52:a51c77007319	2769	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	2770	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	2771	tmp = (uint16_t)(TIM_ICPolarity << 4);
mbed_official	52:a51c77007319	2772	/* Select the Input and set the filter */
mbed_official	52:a51c77007319	2773	tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
mbed_official	52:a51c77007319	2774	tmpccmr1 \|= (uint16_t)(TIM_ICFilter << 12);
mbed_official	52:a51c77007319	2775	tmpccmr1 \|= (uint16_t)(TIM_ICSelection << 8);
mbed_official	52:a51c77007319	2776
mbed_official	52:a51c77007319	2777	if((TIMx == TIM1) \|\| (TIMx == TIM8) \|\| (TIMx == TIM2) \|\| (TIMx == TIM3) \|\|
mbed_official	52:a51c77007319	2778	(TIMx == TIM4) \|\|(TIMx == TIM5))
mbed_official	52:a51c77007319	2779	{
mbed_official	52:a51c77007319	2780	/* Select the Polarity and set the CC2E Bit */
mbed_official	52:a51c77007319	2781	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
mbed_official	52:a51c77007319	2782	tmpccer \|= (uint16_t)(tmp \| (uint16_t)TIM_CCER_CC2E);
mbed_official	52:a51c77007319	2783	}
mbed_official	52:a51c77007319	2784	else
mbed_official	52:a51c77007319	2785	{
mbed_official	52:a51c77007319	2786	/* Select the Polarity and set the CC2E Bit */
mbed_official	52:a51c77007319	2787	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P \| TIM_CCER_CC2NP));
mbed_official	52:a51c77007319	2788	tmpccer \|= (uint16_t)(TIM_ICPolarity \| (uint16_t)TIM_CCER_CC2E);
mbed_official	52:a51c77007319	2789	}
mbed_official	52:a51c77007319	2790
mbed_official	52:a51c77007319	2791	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	52:a51c77007319	2792	TIMx->CCMR1 = tmpccmr1 ;
mbed_official	52:a51c77007319	2793	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	2794	}
mbed_official	52:a51c77007319	2795
mbed_official	52:a51c77007319	2796	/**
mbed_official	52:a51c77007319	2797	* @brief Configure the TI3 as Input.
mbed_official	52:a51c77007319	2798	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2799	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	52:a51c77007319	2800	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2801	* @arg TIM_ICPolarity_Rising
mbed_official	52:a51c77007319	2802	* @arg TIM_ICPolarity_Falling
mbed_official	52:a51c77007319	2803	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	52:a51c77007319	2804	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2805	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
mbed_official	52:a51c77007319	2806	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
mbed_official	52:a51c77007319	2807	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
mbed_official	52:a51c77007319	2808	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	52:a51c77007319	2809	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	52:a51c77007319	2810	* @retval None
mbed_official	52:a51c77007319	2811	*/
mbed_official	52:a51c77007319	2812	static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	2813	uint16_t TIM_ICFilter)
mbed_official	52:a51c77007319	2814	{
mbed_official	52:a51c77007319	2815	uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
mbed_official	52:a51c77007319	2816	/* Disable the Channel 3: Reset the CC3E Bit */
mbed_official	52:a51c77007319	2817	TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
mbed_official	52:a51c77007319	2818	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	2819	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	2820	tmp = (uint16_t)(TIM_ICPolarity << 8);
mbed_official	52:a51c77007319	2821	/* Select the Input and set the filter */
mbed_official	52:a51c77007319	2822	tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
mbed_official	52:a51c77007319	2823	tmpccmr2 \|= (uint16_t)(TIM_ICSelection \| (uint16_t)(TIM_ICFilter << (uint16_t)4));
mbed_official	52:a51c77007319	2824
mbed_official	52:a51c77007319	2825	if((TIMx == TIM1) \|\| (TIMx == TIM8) \|\| (TIMx == TIM2) \|\| (TIMx == TIM3) \|\|
mbed_official	52:a51c77007319	2826	(TIMx == TIM4) \|\|(TIMx == TIM5))
mbed_official	52:a51c77007319	2827	{
mbed_official	52:a51c77007319	2828	/* Select the Polarity and set the CC3E Bit */
mbed_official	52:a51c77007319	2829	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
mbed_official	52:a51c77007319	2830	tmpccer \|= (uint16_t)(tmp \| (uint16_t)TIM_CCER_CC3E);
mbed_official	52:a51c77007319	2831	}
mbed_official	52:a51c77007319	2832	else
mbed_official	52:a51c77007319	2833	{
mbed_official	52:a51c77007319	2834	/* Select the Polarity and set the CC3E Bit */
mbed_official	52:a51c77007319	2835	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P \| TIM_CCER_CC3NP));
mbed_official	52:a51c77007319	2836	tmpccer \|= (uint16_t)(TIM_ICPolarity \| (uint16_t)TIM_CCER_CC3E);
mbed_official	52:a51c77007319	2837	}
mbed_official	52:a51c77007319	2838
mbed_official	52:a51c77007319	2839	/* Write to TIMx CCMR2 and CCER registers */
mbed_official	52:a51c77007319	2840	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	2841	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	2842	}
mbed_official	52:a51c77007319	2843
mbed_official	52:a51c77007319	2844	/**
mbed_official	52:a51c77007319	2845	* @brief Configure the TI4 as Input.
mbed_official	52:a51c77007319	2846	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2847	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	52:a51c77007319	2848	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2849	* @arg TIM_ICPolarity_Rising
mbed_official	52:a51c77007319	2850	* @arg TIM_ICPolarity_Falling
mbed_official	52:a51c77007319	2851	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	52:a51c77007319	2852	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2853	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
mbed_official	52:a51c77007319	2854	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
mbed_official	52:a51c77007319	2855	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
mbed_official	52:a51c77007319	2856	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	52:a51c77007319	2857	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	52:a51c77007319	2858	* @retval None
mbed_official	52:a51c77007319	2859	*/
mbed_official	52:a51c77007319	2860	static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	2861	uint16_t TIM_ICFilter)
mbed_official	52:a51c77007319	2862	{
mbed_official	52:a51c77007319	2863	uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
mbed_official	52:a51c77007319	2864
mbed_official	52:a51c77007319	2865	/* Disable the Channel 4: Reset the CC4E Bit */
mbed_official	52:a51c77007319	2866	TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
mbed_official	52:a51c77007319	2867	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	2868	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	2869	tmp = (uint16_t)(TIM_ICPolarity << 12);
mbed_official	52:a51c77007319	2870	/* Select the Input and set the filter */
mbed_official	52:a51c77007319	2871	tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
mbed_official	52:a51c77007319	2872	tmpccmr2 \|= (uint16_t)(TIM_ICSelection << 8);
mbed_official	52:a51c77007319	2873	tmpccmr2 \|= (uint16_t)(TIM_ICFilter << 12);
mbed_official	52:a51c77007319	2874
mbed_official	52:a51c77007319	2875	if((TIMx == TIM1) \|\| (TIMx == TIM8) \|\| (TIMx == TIM2) \|\| (TIMx == TIM3) \|\|
mbed_official	52:a51c77007319	2876	(TIMx == TIM4) \|\|(TIMx == TIM5))
mbed_official	52:a51c77007319	2877	{
mbed_official	52:a51c77007319	2878	/* Select the Polarity and set the CC4E Bit */
mbed_official	52:a51c77007319	2879	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
mbed_official	52:a51c77007319	2880	tmpccer \|= (uint16_t)(tmp \| (uint16_t)TIM_CCER_CC4E);
mbed_official	52:a51c77007319	2881	}
mbed_official	52:a51c77007319	2882	else
mbed_official	52:a51c77007319	2883	{
mbed_official	52:a51c77007319	2884	/* Select the Polarity and set the CC4E Bit */
mbed_official	52:a51c77007319	2885	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P \| TIM_CCER_CC4NP));
mbed_official	52:a51c77007319	2886	tmpccer \|= (uint16_t)(TIM_ICPolarity \| (uint16_t)TIM_CCER_CC4E);
mbed_official	52:a51c77007319	2887	}
mbed_official	52:a51c77007319	2888	/* Write to TIMx CCMR2 and CCER registers */
mbed_official	52:a51c77007319	2889	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	2890	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	2891	}
mbed_official	52:a51c77007319	2892
mbed_official	52:a51c77007319	2893	/**
mbed_official	52:a51c77007319	2894	* @}
mbed_official	52:a51c77007319	2895	*/
mbed_official	52:a51c77007319	2896
mbed_official	52:a51c77007319	2897	/**
mbed_official	52:a51c77007319	2898	* @}
mbed_official	52:a51c77007319	2899	*/
mbed_official	52:a51c77007319	2900
mbed_official	52:a51c77007319	2901	/**
mbed_official	52:a51c77007319	2902	* @}
mbed_official	52:a51c77007319	2903	*/
mbed_official	52:a51c77007319	2904
mbed_official	52:a51c77007319	2905	/***************** (C) COPYRIGHT 2011 STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Mar 2014
Imports:	301
Forks:	0
Commits:	115
Dependents:	0
Dependencies:	0
Followers:	15
Issues:	1

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_tim.c@70:c1fbde68b492, 2014-01-07 (annotated)

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