Peter Drescher / mbed-F401

mbed library with additional peripherals for ST F401 board

Fork of mbed-src by mbed official

This mbed LIB has additional peripherals for ST F401 board

  • UART2 : PA_3 rx, PA_2 tx
  • UART3 : PC_7 rx, PC_6 tx
  • I2C2 : PB_3 SDA, PB_10 SCL
  • I2C3 : PB_4 SDA, PA_8 SCL

targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_fsmc.c@76:aeb1df146756, 2014-01-27 (annotated)

Committer:
mbed_official
Date:
Mon Jan 27 14:30:07 2014 +0000
Revision:
76:aeb1df146756
Child:
80:66393a7b209d
Synchronized with git revision a31ec9c5f7bcb5c8a1b2eced103f6a1dfa921abd



Full URL: https://github.com/mbedmicro/mbed/commit/a31ec9c5f7bcb5c8a1b2eced103f6a1dfa921abd/



Add NUCLEO_L152RE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 76:aeb1df146756 1 /**
mbed_official 76:aeb1df146756 2 ******************************************************************************
mbed_official 76:aeb1df146756 3 * @file stm32l1xx_fsmc.c
mbed_official 76:aeb1df146756 4 * @author MCD Application Team
mbed_official 76:aeb1df146756 5 * @version V1.2.0
mbed_official 76:aeb1df146756 6 * @date 22-February-2013
mbed_official 76:aeb1df146756 7 * @brief This file provides firmware functions to manage the following
mbed_official 76:aeb1df146756 8 * functionalities of the FSMC peripheral:
mbed_official 76:aeb1df146756 9 * + Initialization
mbed_official 76:aeb1df146756 10 * + Interrupts and flags management
mbed_official 76:aeb1df146756 11 *
mbed_official 76:aeb1df146756 12 ******************************************************************************
mbed_official 76:aeb1df146756 13 * @attention
mbed_official 76:aeb1df146756 14 *
mbed_official 76:aeb1df146756 15 * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
mbed_official 76:aeb1df146756 16 *
mbed_official 76:aeb1df146756 17 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
mbed_official 76:aeb1df146756 18 * You may not use this file except in compliance with the License.
mbed_official 76:aeb1df146756 19 * You may obtain a copy of the License at:
mbed_official 76:aeb1df146756 20 *
mbed_official 76:aeb1df146756 21 * http://www.st.com/software_license_agreement_liberty_v2
mbed_official 76:aeb1df146756 22 *
mbed_official 76:aeb1df146756 23 * Unless required by applicable law or agreed to in writing, software
mbed_official 76:aeb1df146756 24 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 76:aeb1df146756 25 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 76:aeb1df146756 26 * See the License for the specific language governing permissions and
mbed_official 76:aeb1df146756 27 * limitations under the License.
mbed_official 76:aeb1df146756 28 *
mbed_official 76:aeb1df146756 29 ******************************************************************************
mbed_official 76:aeb1df146756 30 */
mbed_official 76:aeb1df146756 31
mbed_official 76:aeb1df146756 32 /* Includes ------------------------------------------------------------------*/
mbed_official 76:aeb1df146756 33 #include "stm32l1xx_fsmc.h"
mbed_official 76:aeb1df146756 34 #include "stm32l1xx_rcc.h"
mbed_official 76:aeb1df146756 35
mbed_official 76:aeb1df146756 36 /** @addtogroup STM32L1xx_StdPeriph_Driver
mbed_official 76:aeb1df146756 37 * @{
mbed_official 76:aeb1df146756 38 */
mbed_official 76:aeb1df146756 39
mbed_official 76:aeb1df146756 40 /** @defgroup FSMC
mbed_official 76:aeb1df146756 41 * @brief FSMC driver modules
mbed_official 76:aeb1df146756 42 * @{
mbed_official 76:aeb1df146756 43 */
mbed_official 76:aeb1df146756 44
mbed_official 76:aeb1df146756 45 /* Private typedef -----------------------------------------------------------*/
mbed_official 76:aeb1df146756 46 /* Private define ------------------------------------------------------------*/
mbed_official 76:aeb1df146756 47 /* Private macro -------------------------------------------------------------*/
mbed_official 76:aeb1df146756 48 /* Private variables ---------------------------------------------------------*/
mbed_official 76:aeb1df146756 49 /* Private function prototypes -----------------------------------------------*/
mbed_official 76:aeb1df146756 50 /* Private functions ---------------------------------------------------------*/
mbed_official 76:aeb1df146756 51
mbed_official 76:aeb1df146756 52 /** @defgroup FSMC_Private_Functions
mbed_official 76:aeb1df146756 53 * @{
mbed_official 76:aeb1df146756 54 */
mbed_official 76:aeb1df146756 55
mbed_official 76:aeb1df146756 56 /** @defgroup FSMC_Group1 NOR/SRAM Controller functions
mbed_official 76:aeb1df146756 57 * @brief NOR/SRAM Controller functions
mbed_official 76:aeb1df146756 58 *
mbed_official 76:aeb1df146756 59 @verbatim
mbed_official 76:aeb1df146756 60 ==============================================================================
mbed_official 76:aeb1df146756 61 ##### NOR-SRAM Controller functions #####
mbed_official 76:aeb1df146756 62 ==============================================================================
mbed_official 76:aeb1df146756 63 [..] The following sequence should be followed to configure the FSMC to
mbed_official 76:aeb1df146756 64 interface with SRAM, PSRAM, NOR or OneNAND memory connected to the
mbed_official 76:aeb1df146756 65 NOR/SRAM Bank:
mbed_official 76:aeb1df146756 66 (#) Enable the clock for the FSMC and associated GPIOs using the following
mbed_official 76:aeb1df146756 67 functions:
mbed_official 76:aeb1df146756 68 (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
mbed_official 76:aeb1df146756 69 (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
mbed_official 76:aeb1df146756 70 (#) FSMC pins configuration
mbed_official 76:aeb1df146756 71 (++) Connect the involved FSMC pins to AF12 using the following function
mbed_official 76:aeb1df146756 72 GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
mbed_official 76:aeb1df146756 73 (++) Configure these FSMC pins in alternate function mode by calling the
mbed_official 76:aeb1df146756 74 function GPIO_Init();
mbed_official 76:aeb1df146756 75 (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:
mbed_official 76:aeb1df146756 76 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; and fill the
mbed_official 76:aeb1df146756 77 FSMC_NORSRAMInitStructure variable with the allowed values of the
mbed_official 76:aeb1df146756 78 structure member.
mbed_official 76:aeb1df146756 79 (#) Initialize the NOR/SRAM Controller by calling the function
mbed_official 76:aeb1df146756 80 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
mbed_official 76:aeb1df146756 81 (#) Then enable the NOR/SRAM Bank, for example:
mbed_official 76:aeb1df146756 82 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
mbed_official 76:aeb1df146756 83 (#) At this stage you can read/write from/to the memory connected to the
mbed_official 76:aeb1df146756 84 NOR/SRAM Bank.
mbed_official 76:aeb1df146756 85
mbed_official 76:aeb1df146756 86 @endverbatim
mbed_official 76:aeb1df146756 87
mbed_official 76:aeb1df146756 88 * @{
mbed_official 76:aeb1df146756 89 */
mbed_official 76:aeb1df146756 90
mbed_official 76:aeb1df146756 91 /**
mbed_official 76:aeb1df146756 92 * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
mbed_official 76:aeb1df146756 93 * reset values.
mbed_official 76:aeb1df146756 94 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 76:aeb1df146756 95 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 96 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
mbed_official 76:aeb1df146756 97 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
mbed_official 76:aeb1df146756 98 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
mbed_official 76:aeb1df146756 99 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
mbed_official 76:aeb1df146756 100 * @retval None
mbed_official 76:aeb1df146756 101 */
mbed_official 76:aeb1df146756 102 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
mbed_official 76:aeb1df146756 103 {
mbed_official 76:aeb1df146756 104 /* Check the parameter */
mbed_official 76:aeb1df146756 105 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
mbed_official 76:aeb1df146756 106
mbed_official 76:aeb1df146756 107 /* FSMC_Bank1_NORSRAM1 */
mbed_official 76:aeb1df146756 108 if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
mbed_official 76:aeb1df146756 109 {
mbed_official 76:aeb1df146756 110 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
mbed_official 76:aeb1df146756 111 }
mbed_official 76:aeb1df146756 112 /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
mbed_official 76:aeb1df146756 113 else
mbed_official 76:aeb1df146756 114 {
mbed_official 76:aeb1df146756 115 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
mbed_official 76:aeb1df146756 116 }
mbed_official 76:aeb1df146756 117 FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
mbed_official 76:aeb1df146756 118 FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
mbed_official 76:aeb1df146756 119 }
mbed_official 76:aeb1df146756 120
mbed_official 76:aeb1df146756 121 /**
mbed_official 76:aeb1df146756 122 * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
mbed_official 76:aeb1df146756 123 * parameters in the FSMC_NORSRAMInitStruct.
mbed_official 76:aeb1df146756 124 * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
mbed_official 76:aeb1df146756 125 * structure that contains the configuration information for
mbed_official 76:aeb1df146756 126 * the FSMC NOR/SRAM specified Banks.
mbed_official 76:aeb1df146756 127 * @retval None
mbed_official 76:aeb1df146756 128 */
mbed_official 76:aeb1df146756 129 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
mbed_official 76:aeb1df146756 130 {
mbed_official 76:aeb1df146756 131 /* Check the parameters */
mbed_official 76:aeb1df146756 132 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
mbed_official 76:aeb1df146756 133 assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
mbed_official 76:aeb1df146756 134 assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
mbed_official 76:aeb1df146756 135 assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
mbed_official 76:aeb1df146756 136 assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
mbed_official 76:aeb1df146756 137 assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
mbed_official 76:aeb1df146756 138 assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
mbed_official 76:aeb1df146756 139 assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
mbed_official 76:aeb1df146756 140 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
mbed_official 76:aeb1df146756 141 assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
mbed_official 76:aeb1df146756 142 assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
mbed_official 76:aeb1df146756 143 assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
mbed_official 76:aeb1df146756 144 assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
mbed_official 76:aeb1df146756 145 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
mbed_official 76:aeb1df146756 146 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
mbed_official 76:aeb1df146756 147 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
mbed_official 76:aeb1df146756 148 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
mbed_official 76:aeb1df146756 149 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
mbed_official 76:aeb1df146756 150 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
mbed_official 76:aeb1df146756 151 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
mbed_official 76:aeb1df146756 152
mbed_official 76:aeb1df146756 153 /* Bank1 NOR/SRAM control register configuration */
mbed_official 76:aeb1df146756 154 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
mbed_official 76:aeb1df146756 155 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
mbed_official 76:aeb1df146756 156 FSMC_NORSRAMInitStruct->FSMC_MemoryType |
mbed_official 76:aeb1df146756 157 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
mbed_official 76:aeb1df146756 158 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
mbed_official 76:aeb1df146756 159 FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
mbed_official 76:aeb1df146756 160 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
mbed_official 76:aeb1df146756 161 FSMC_NORSRAMInitStruct->FSMC_WrapMode |
mbed_official 76:aeb1df146756 162 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
mbed_official 76:aeb1df146756 163 FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
mbed_official 76:aeb1df146756 164 FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
mbed_official 76:aeb1df146756 165 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
mbed_official 76:aeb1df146756 166 FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
mbed_official 76:aeb1df146756 167
mbed_official 76:aeb1df146756 168 if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
mbed_official 76:aeb1df146756 169 {
mbed_official 76:aeb1df146756 170 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)FSMC_BCR1_FACCEN;
mbed_official 76:aeb1df146756 171 }
mbed_official 76:aeb1df146756 172
mbed_official 76:aeb1df146756 173 /* Bank1 NOR/SRAM timing register configuration */
mbed_official 76:aeb1df146756 174 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
mbed_official 76:aeb1df146756 175 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
mbed_official 76:aeb1df146756 176 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
mbed_official 76:aeb1df146756 177 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
mbed_official 76:aeb1df146756 178 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
mbed_official 76:aeb1df146756 179 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
mbed_official 76:aeb1df146756 180 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
mbed_official 76:aeb1df146756 181 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
mbed_official 76:aeb1df146756 182
mbed_official 76:aeb1df146756 183
mbed_official 76:aeb1df146756 184 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
mbed_official 76:aeb1df146756 185 if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
mbed_official 76:aeb1df146756 186 {
mbed_official 76:aeb1df146756 187 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
mbed_official 76:aeb1df146756 188 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
mbed_official 76:aeb1df146756 189 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
mbed_official 76:aeb1df146756 190 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
mbed_official 76:aeb1df146756 191 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
mbed_official 76:aeb1df146756 192 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
mbed_official 76:aeb1df146756 193 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
mbed_official 76:aeb1df146756 194 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
mbed_official 76:aeb1df146756 195 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
mbed_official 76:aeb1df146756 196 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
mbed_official 76:aeb1df146756 197 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
mbed_official 76:aeb1df146756 198 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
mbed_official 76:aeb1df146756 199 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
mbed_official 76:aeb1df146756 200 }
mbed_official 76:aeb1df146756 201 else
mbed_official 76:aeb1df146756 202 {
mbed_official 76:aeb1df146756 203 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
mbed_official 76:aeb1df146756 204 }
mbed_official 76:aeb1df146756 205 }
mbed_official 76:aeb1df146756 206
mbed_official 76:aeb1df146756 207 /**
mbed_official 76:aeb1df146756 208 * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
mbed_official 76:aeb1df146756 209 * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
mbed_official 76:aeb1df146756 210 * structure which will be initialized.
mbed_official 76:aeb1df146756 211 * @retval None
mbed_official 76:aeb1df146756 212 */
mbed_official 76:aeb1df146756 213 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
mbed_official 76:aeb1df146756 214 {
mbed_official 76:aeb1df146756 215 /* Reset NOR/SRAM Init structure parameters values */
mbed_official 76:aeb1df146756 216 FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
mbed_official 76:aeb1df146756 217 FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
mbed_official 76:aeb1df146756 218 FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
mbed_official 76:aeb1df146756 219 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
mbed_official 76:aeb1df146756 220 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
mbed_official 76:aeb1df146756 221 FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
mbed_official 76:aeb1df146756 222 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
mbed_official 76:aeb1df146756 223 FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
mbed_official 76:aeb1df146756 224 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
mbed_official 76:aeb1df146756 225 FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
mbed_official 76:aeb1df146756 226 FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
mbed_official 76:aeb1df146756 227 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
mbed_official 76:aeb1df146756 228 FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
mbed_official 76:aeb1df146756 229 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
mbed_official 76:aeb1df146756 230 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
mbed_official 76:aeb1df146756 231 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
mbed_official 76:aeb1df146756 232 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
mbed_official 76:aeb1df146756 233 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
mbed_official 76:aeb1df146756 234 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
mbed_official 76:aeb1df146756 235 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
mbed_official 76:aeb1df146756 236 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
mbed_official 76:aeb1df146756 237 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
mbed_official 76:aeb1df146756 238 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
mbed_official 76:aeb1df146756 239 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
mbed_official 76:aeb1df146756 240 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
mbed_official 76:aeb1df146756 241 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
mbed_official 76:aeb1df146756 242 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
mbed_official 76:aeb1df146756 243 }
mbed_official 76:aeb1df146756 244
mbed_official 76:aeb1df146756 245 /**
mbed_official 76:aeb1df146756 246 * @brief Enables or disables the specified NOR/SRAM Memory Bank.
mbed_official 76:aeb1df146756 247 * @param FSMC_Bank: specifies the FSMC Bank to be used
mbed_official 76:aeb1df146756 248 * This parameter can be one of the following values:
mbed_official 76:aeb1df146756 249 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
mbed_official 76:aeb1df146756 250 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
mbed_official 76:aeb1df146756 251 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
mbed_official 76:aeb1df146756 252 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
mbed_official 76:aeb1df146756 253 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
mbed_official 76:aeb1df146756 254 * @retval None
mbed_official 76:aeb1df146756 255 */
mbed_official 76:aeb1df146756 256 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
mbed_official 76:aeb1df146756 257 {
mbed_official 76:aeb1df146756 258 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
mbed_official 76:aeb1df146756 259 assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official 76:aeb1df146756 260
mbed_official 76:aeb1df146756 261 if (NewState != DISABLE)
mbed_official 76:aeb1df146756 262 {
mbed_official 76:aeb1df146756 263 /* Enable the selected NOR/SRAM Bank by setting the MBKEN bit in the BCRx register */
mbed_official 76:aeb1df146756 264 FSMC_Bank1->BTCR[FSMC_Bank] |= FSMC_BCR1_MBKEN;
mbed_official 76:aeb1df146756 265 }
mbed_official 76:aeb1df146756 266 else
mbed_official 76:aeb1df146756 267 {
mbed_official 76:aeb1df146756 268 /* Disable the selected NOR/SRAM Bank by clearing the MBKEN bit in the BCRx register */
mbed_official 76:aeb1df146756 269 FSMC_Bank1->BTCR[FSMC_Bank] &= (uint32_t)(~FSMC_BCR1_MBKEN);
mbed_official 76:aeb1df146756 270 }
mbed_official 76:aeb1df146756 271 }
mbed_official 76:aeb1df146756 272
mbed_official 76:aeb1df146756 273 /**
mbed_official 76:aeb1df146756 274 * @}
mbed_official 76:aeb1df146756 275 */
mbed_official 76:aeb1df146756 276
mbed_official 76:aeb1df146756 277 /**
mbed_official 76:aeb1df146756 278 * @}
mbed_official 76:aeb1df146756 279 */
mbed_official 76:aeb1df146756 280
mbed_official 76:aeb1df146756 281 /**
mbed_official 76:aeb1df146756 282 * @}
mbed_official 76:aeb1df146756 283 */
mbed_official 76:aeb1df146756 284
mbed_official 76:aeb1df146756 285 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/