mbed - mbed library

Users » JulienKern » Code » mbed

mbed library

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_uart.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_uart.h@82:6473597d706e

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_UART_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_UART_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 UART
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Serial Communication Interface
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_UART_BDH - UART Baud Rate Registers: High
bogdanm	82:6473597d706e	33	* - HW_UART_BDL - UART Baud Rate Registers: Low
bogdanm	82:6473597d706e	34	* - HW_UART_C1 - UART Control Register 1
bogdanm	82:6473597d706e	35	* - HW_UART_C2 - UART Control Register 2
bogdanm	82:6473597d706e	36	* - HW_UART_S1 - UART Status Register 1
bogdanm	82:6473597d706e	37	* - HW_UART_S2 - UART Status Register 2
bogdanm	82:6473597d706e	38	* - HW_UART_C3 - UART Control Register 3
bogdanm	82:6473597d706e	39	* - HW_UART_D - UART Data Register
bogdanm	82:6473597d706e	40	* - HW_UART_MA1 - UART Match Address Registers 1
bogdanm	82:6473597d706e	41	* - HW_UART_MA2 - UART Match Address Registers 2
bogdanm	82:6473597d706e	42	* - HW_UART_C4 - UART Control Register 4
bogdanm	82:6473597d706e	43	* - HW_UART_C5 - UART Control Register 5
bogdanm	82:6473597d706e	44	* - HW_UART_ED - UART Extended Data Register
bogdanm	82:6473597d706e	45	* - HW_UART_MODEM - UART Modem Register
bogdanm	82:6473597d706e	46	* - HW_UART_IR - UART Infrared Register
bogdanm	82:6473597d706e	47	* - HW_UART_PFIFO - UART FIFO Parameters
bogdanm	82:6473597d706e	48	* - HW_UART_CFIFO - UART FIFO Control Register
bogdanm	82:6473597d706e	49	* - HW_UART_SFIFO - UART FIFO Status Register
bogdanm	82:6473597d706e	50	* - HW_UART_TWFIFO - UART FIFO Transmit Watermark
bogdanm	82:6473597d706e	51	* - HW_UART_TCFIFO - UART FIFO Transmit Count
bogdanm	82:6473597d706e	52	* - HW_UART_RWFIFO - UART FIFO Receive Watermark
bogdanm	82:6473597d706e	53	* - HW_UART_RCFIFO - UART FIFO Receive Count
bogdanm	82:6473597d706e	54	* - HW_UART_C7816 - UART 7816 Control Register
bogdanm	82:6473597d706e	55	* - HW_UART_IE7816 - UART 7816 Interrupt Enable Register
bogdanm	82:6473597d706e	56	* - HW_UART_IS7816 - UART 7816 Interrupt Status Register
bogdanm	82:6473597d706e	57	* - HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register
bogdanm	82:6473597d706e	58	* - HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register
bogdanm	82:6473597d706e	59	* - HW_UART_WN7816 - UART 7816 Wait N Register
bogdanm	82:6473597d706e	60	* - HW_UART_WF7816 - UART 7816 Wait FD Register
bogdanm	82:6473597d706e	61	* - HW_UART_ET7816 - UART 7816 Error Threshold Register
bogdanm	82:6473597d706e	62	* - HW_UART_TL7816 - UART 7816 Transmit Length Register
bogdanm	82:6473597d706e	63	*
bogdanm	82:6473597d706e	64	* - hw_uart_t - Struct containing all module registers.
bogdanm	82:6473597d706e	65	*/
bogdanm	82:6473597d706e	66
bogdanm	82:6473597d706e	67	//! @name Module base addresses
bogdanm	82:6473597d706e	68	//@{
bogdanm	82:6473597d706e	69	#ifndef REGS_UART_BASE
bogdanm	82:6473597d706e	70	#define HW_UART_INSTANCE_COUNT (6U) //!< Number of instances of the UART module.
bogdanm	82:6473597d706e	71	#define HW_UART0 (0U) //!< Instance number for UART0.
bogdanm	82:6473597d706e	72	#define HW_UART1 (1U) //!< Instance number for UART1.
bogdanm	82:6473597d706e	73	#define HW_UART2 (2U) //!< Instance number for UART2.
bogdanm	82:6473597d706e	74	#define HW_UART3 (3U) //!< Instance number for UART3.
bogdanm	82:6473597d706e	75	#define HW_UART4 (4U) //!< Instance number for UART4.
bogdanm	82:6473597d706e	76	#define HW_UART5 (5U) //!< Instance number for UART5.
bogdanm	82:6473597d706e	77	#define REGS_UART0_BASE (0x4006A000U) //!< Base address for UART0.
bogdanm	82:6473597d706e	78	#define REGS_UART1_BASE (0x4006B000U) //!< Base address for UART1.
bogdanm	82:6473597d706e	79	#define REGS_UART2_BASE (0x4006C000U) //!< Base address for UART2.
bogdanm	82:6473597d706e	80	#define REGS_UART3_BASE (0x4006D000U) //!< Base address for UART3.
bogdanm	82:6473597d706e	81	#define REGS_UART4_BASE (0x400EA000U) //!< Base address for UART4.
bogdanm	82:6473597d706e	82	#define REGS_UART5_BASE (0x400EB000U) //!< Base address for UART5.
bogdanm	82:6473597d706e	83
bogdanm	82:6473597d706e	84	//! @brief Table of base addresses for UART instances.
bogdanm	82:6473597d706e	85	static const uint32_t __g_regs_UART_base_addresses[] = {
bogdanm	82:6473597d706e	86	REGS_UART0_BASE,
bogdanm	82:6473597d706e	87	REGS_UART1_BASE,
bogdanm	82:6473597d706e	88	REGS_UART2_BASE,
bogdanm	82:6473597d706e	89	REGS_UART3_BASE,
bogdanm	82:6473597d706e	90	REGS_UART4_BASE,
bogdanm	82:6473597d706e	91	REGS_UART5_BASE,
bogdanm	82:6473597d706e	92	};
bogdanm	82:6473597d706e	93
bogdanm	82:6473597d706e	94	//! @brief Get the base address of UART by instance number.
bogdanm	82:6473597d706e	95	//! @param x UART instance number, from 0 through 5.
bogdanm	82:6473597d706e	96	#define REGS_UART_BASE(x) (__g_regs_UART_base_addresses[(x)])
bogdanm	82:6473597d706e	97
bogdanm	82:6473597d706e	98	//! @brief Get the instance number given a base address.
bogdanm	82:6473597d706e	99	//! @param b Base address for an instance of UART.
bogdanm	82:6473597d706e	100	#define REGS_UART_INSTANCE(b) ((b) == REGS_UART0_BASE ? HW_UART0 : (b) == REGS_UART1_BASE ? HW_UART1 : (b) == REGS_UART2_BASE ? HW_UART2 : (b) == REGS_UART3_BASE ? HW_UART3 : (b) == REGS_UART4_BASE ? HW_UART4 : (b) == REGS_UART5_BASE ? HW_UART5 : 0)
bogdanm	82:6473597d706e	101	#endif
bogdanm	82:6473597d706e	102	//@}
bogdanm	82:6473597d706e	103
bogdanm	82:6473597d706e	104	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	105	// HW_UART_BDH - UART Baud Rate Registers: High
bogdanm	82:6473597d706e	106	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	107
bogdanm	82:6473597d706e	108	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	109	/*!
bogdanm	82:6473597d706e	110	* @brief HW_UART_BDH - UART Baud Rate Registers: High (RW)
bogdanm	82:6473597d706e	111	*
bogdanm	82:6473597d706e	112	* Reset value: 0x00U
bogdanm	82:6473597d706e	113	*
bogdanm	82:6473597d706e	114	* This register, along with the BDL register, controls the prescale divisor for
bogdanm	82:6473597d706e	115	* UART baud rate generation. To update the 13-bit baud rate setting
bogdanm	82:6473597d706e	116	* (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
bogdanm	82:6473597d706e	117	* to BDL. The working value in BDH does not change until BDL is written. BDL is
bogdanm	82:6473597d706e	118	* reset to a nonzero value, but after reset, the baud rate generator remains
bogdanm	82:6473597d706e	119	* disabled until the first time the receiver or transmitter is enabled, that is,
bogdanm	82:6473597d706e	120	* when C2[RE] or C2[TE] is set.
bogdanm	82:6473597d706e	121	*/
bogdanm	82:6473597d706e	122	typedef union _hw_uart_bdh
bogdanm	82:6473597d706e	123	{
bogdanm	82:6473597d706e	124	uint8_t U;
bogdanm	82:6473597d706e	125	struct _hw_uart_bdh_bitfields
bogdanm	82:6473597d706e	126	{
bogdanm	82:6473597d706e	127	uint8_t SBR : 5; //!< [4:0] UART Baud Rate Bits
bogdanm	82:6473597d706e	128	uint8_t SBNS : 1; //!< [5] Stop Bit Number Select
bogdanm	82:6473597d706e	129	uint8_t RXEDGIE : 1; //!< [6] RxD Input Active Edge Interrupt Enable
bogdanm	82:6473597d706e	130	uint8_t LBKDIE : 1; //!< [7] LIN Break Detect Interrupt or DMA
bogdanm	82:6473597d706e	131	//! Request Enable
bogdanm	82:6473597d706e	132	} B;
bogdanm	82:6473597d706e	133	} hw_uart_bdh_t;
bogdanm	82:6473597d706e	134	#endif
bogdanm	82:6473597d706e	135
bogdanm	82:6473597d706e	136	/*!
bogdanm	82:6473597d706e	137	* @name Constants and macros for entire UART_BDH register
bogdanm	82:6473597d706e	138	*/
bogdanm	82:6473597d706e	139	//@{
bogdanm	82:6473597d706e	140	#define HW_UART_BDH_ADDR(x) (REGS_UART_BASE(x) + 0x0U)
bogdanm	82:6473597d706e	141
bogdanm	82:6473597d706e	142	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	143	#define HW_UART_BDH(x) ((__IO hw_uart_bdh_t ) HW_UART_BDH_ADDR(x))
bogdanm	82:6473597d706e	144	#define HW_UART_BDH_RD(x) (HW_UART_BDH(x).U)
bogdanm	82:6473597d706e	145	#define HW_UART_BDH_WR(x, v) (HW_UART_BDH(x).U = (v))
bogdanm	82:6473597d706e	146	#define HW_UART_BDH_SET(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) \| (v)))
bogdanm	82:6473597d706e	147	#define HW_UART_BDH_CLR(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) & ~(v)))
bogdanm	82:6473597d706e	148	#define HW_UART_BDH_TOG(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) ^ (v)))
bogdanm	82:6473597d706e	149	#endif
bogdanm	82:6473597d706e	150	//@}
bogdanm	82:6473597d706e	151
bogdanm	82:6473597d706e	152	/*
bogdanm	82:6473597d706e	153	* Constants & macros for individual UART_BDH bitfields
bogdanm	82:6473597d706e	154	*/
bogdanm	82:6473597d706e	155
bogdanm	82:6473597d706e	156	/*!
bogdanm	82:6473597d706e	157	* @name Register UART_BDH, field SBR[4:0] (RW)
bogdanm	82:6473597d706e	158	*
bogdanm	82:6473597d706e	159	* The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
bogdanm	82:6473597d706e	160	* generation for details. The baud rate generator is disabled until C2[TE] or
bogdanm	82:6473597d706e	161	* C2[RE] is set for the first time after reset.The baud rate generator is disabled
bogdanm	82:6473597d706e	162	* when SBR = 0. Writing to BDH has no effect without writing to BDL, because
bogdanm	82:6473597d706e	163	* writing to BDH puts the data in a temporary location until BDL is written.
bogdanm	82:6473597d706e	164	*/
bogdanm	82:6473597d706e	165	//@{
bogdanm	82:6473597d706e	166	#define BP_UART_BDH_SBR (0U) //!< Bit position for UART_BDH_SBR.
bogdanm	82:6473597d706e	167	#define BM_UART_BDH_SBR (0x1FU) //!< Bit mask for UART_BDH_SBR.
bogdanm	82:6473597d706e	168	#define BS_UART_BDH_SBR (5U) //!< Bit field size in bits for UART_BDH_SBR.
bogdanm	82:6473597d706e	169
bogdanm	82:6473597d706e	170	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	171	//! @brief Read current value of the UART_BDH_SBR field.
bogdanm	82:6473597d706e	172	#define BR_UART_BDH_SBR(x) (HW_UART_BDH(x).B.SBR)
bogdanm	82:6473597d706e	173	#endif
bogdanm	82:6473597d706e	174
bogdanm	82:6473597d706e	175	//! @brief Format value for bitfield UART_BDH_SBR.
bogdanm	82:6473597d706e	176	#define BF_UART_BDH_SBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_SBR), uint8_t) & BM_UART_BDH_SBR)
bogdanm	82:6473597d706e	177
bogdanm	82:6473597d706e	178	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	179	//! @brief Set the SBR field to a new value.
bogdanm	82:6473597d706e	180	#define BW_UART_BDH_SBR(x, v) (HW_UART_BDH_WR(x, (HW_UART_BDH_RD(x) & ~BM_UART_BDH_SBR) \| BF_UART_BDH_SBR(v)))
bogdanm	82:6473597d706e	181	#endif
bogdanm	82:6473597d706e	182	//@}
bogdanm	82:6473597d706e	183
bogdanm	82:6473597d706e	184	/*!
bogdanm	82:6473597d706e	185	* @name Register UART_BDH, field SBNS[5] (RW)
bogdanm	82:6473597d706e	186	*
bogdanm	82:6473597d706e	187	* SBNS selects the number of stop bits present in a data frame. This field
bogdanm	82:6473597d706e	188	* valid for all 8, 9 and 10 bit data formats available. This field is not valid when
bogdanm	82:6473597d706e	189	* C7816[ISO7816E] is enabled.
bogdanm	82:6473597d706e	190	*
bogdanm	82:6473597d706e	191	* Values:
bogdanm	82:6473597d706e	192	* - 0 - Data frame consists of a single stop bit.
bogdanm	82:6473597d706e	193	* - 1 - Data frame consists of two stop bits.
bogdanm	82:6473597d706e	194	*/
bogdanm	82:6473597d706e	195	//@{
bogdanm	82:6473597d706e	196	#define BP_UART_BDH_SBNS (5U) //!< Bit position for UART_BDH_SBNS.
bogdanm	82:6473597d706e	197	#define BM_UART_BDH_SBNS (0x20U) //!< Bit mask for UART_BDH_SBNS.
bogdanm	82:6473597d706e	198	#define BS_UART_BDH_SBNS (1U) //!< Bit field size in bits for UART_BDH_SBNS.
bogdanm	82:6473597d706e	199
bogdanm	82:6473597d706e	200	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	201	//! @brief Read current value of the UART_BDH_SBNS field.
bogdanm	82:6473597d706e	202	#define BR_UART_BDH_SBNS(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS))
bogdanm	82:6473597d706e	203	#endif
bogdanm	82:6473597d706e	204
bogdanm	82:6473597d706e	205	//! @brief Format value for bitfield UART_BDH_SBNS.
bogdanm	82:6473597d706e	206	#define BF_UART_BDH_SBNS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_SBNS), uint8_t) & BM_UART_BDH_SBNS)
bogdanm	82:6473597d706e	207
bogdanm	82:6473597d706e	208	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	209	//! @brief Set the SBNS field to a new value.
bogdanm	82:6473597d706e	210	#define BW_UART_BDH_SBNS(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS) = (v))
bogdanm	82:6473597d706e	211	#endif
bogdanm	82:6473597d706e	212	//@}
bogdanm	82:6473597d706e	213
bogdanm	82:6473597d706e	214	/*!
bogdanm	82:6473597d706e	215	* @name Register UART_BDH, field RXEDGIE[6] (RW)
bogdanm	82:6473597d706e	216	*
bogdanm	82:6473597d706e	217	* Enables the receive input active edge, RXEDGIF, to generate interrupt
bogdanm	82:6473597d706e	218	* requests.
bogdanm	82:6473597d706e	219	*
bogdanm	82:6473597d706e	220	* Values:
bogdanm	82:6473597d706e	221	* - 0 - Hardware interrupts from RXEDGIF disabled using polling.
bogdanm	82:6473597d706e	222	* - 1 - RXEDGIF interrupt request enabled.
bogdanm	82:6473597d706e	223	*/
bogdanm	82:6473597d706e	224	//@{
bogdanm	82:6473597d706e	225	#define BP_UART_BDH_RXEDGIE (6U) //!< Bit position for UART_BDH_RXEDGIE.
bogdanm	82:6473597d706e	226	#define BM_UART_BDH_RXEDGIE (0x40U) //!< Bit mask for UART_BDH_RXEDGIE.
bogdanm	82:6473597d706e	227	#define BS_UART_BDH_RXEDGIE (1U) //!< Bit field size in bits for UART_BDH_RXEDGIE.
bogdanm	82:6473597d706e	228
bogdanm	82:6473597d706e	229	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	230	//! @brief Read current value of the UART_BDH_RXEDGIE field.
bogdanm	82:6473597d706e	231	#define BR_UART_BDH_RXEDGIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE))
bogdanm	82:6473597d706e	232	#endif
bogdanm	82:6473597d706e	233
bogdanm	82:6473597d706e	234	//! @brief Format value for bitfield UART_BDH_RXEDGIE.
bogdanm	82:6473597d706e	235	#define BF_UART_BDH_RXEDGIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_RXEDGIE), uint8_t) & BM_UART_BDH_RXEDGIE)
bogdanm	82:6473597d706e	236
bogdanm	82:6473597d706e	237	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	238	//! @brief Set the RXEDGIE field to a new value.
bogdanm	82:6473597d706e	239	#define BW_UART_BDH_RXEDGIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE) = (v))
bogdanm	82:6473597d706e	240	#endif
bogdanm	82:6473597d706e	241	//@}
bogdanm	82:6473597d706e	242
bogdanm	82:6473597d706e	243	/*!
bogdanm	82:6473597d706e	244	* @name Register UART_BDH, field LBKDIE[7] (RW)
bogdanm	82:6473597d706e	245	*
bogdanm	82:6473597d706e	246	* Enables the LIN break detect flag, LBKDIF, to generate interrupt requests
bogdanm	82:6473597d706e	247	* based on the state of LBKDDMAS. or DMA transfer requests,
bogdanm	82:6473597d706e	248	*
bogdanm	82:6473597d706e	249	* Values:
bogdanm	82:6473597d706e	250	* - 0 - LBKDIF interrupt and DMA transfer requests disabled.
bogdanm	82:6473597d706e	251	* - 1 - LBKDIF interrupt or DMA transfer requests enabled.
bogdanm	82:6473597d706e	252	*/
bogdanm	82:6473597d706e	253	//@{
bogdanm	82:6473597d706e	254	#define BP_UART_BDH_LBKDIE (7U) //!< Bit position for UART_BDH_LBKDIE.
bogdanm	82:6473597d706e	255	#define BM_UART_BDH_LBKDIE (0x80U) //!< Bit mask for UART_BDH_LBKDIE.
bogdanm	82:6473597d706e	256	#define BS_UART_BDH_LBKDIE (1U) //!< Bit field size in bits for UART_BDH_LBKDIE.
bogdanm	82:6473597d706e	257
bogdanm	82:6473597d706e	258	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	259	//! @brief Read current value of the UART_BDH_LBKDIE field.
bogdanm	82:6473597d706e	260	#define BR_UART_BDH_LBKDIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE))
bogdanm	82:6473597d706e	261	#endif
bogdanm	82:6473597d706e	262
bogdanm	82:6473597d706e	263	//! @brief Format value for bitfield UART_BDH_LBKDIE.
bogdanm	82:6473597d706e	264	#define BF_UART_BDH_LBKDIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_LBKDIE), uint8_t) & BM_UART_BDH_LBKDIE)
bogdanm	82:6473597d706e	265
bogdanm	82:6473597d706e	266	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	267	//! @brief Set the LBKDIE field to a new value.
bogdanm	82:6473597d706e	268	#define BW_UART_BDH_LBKDIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE) = (v))
bogdanm	82:6473597d706e	269	#endif
bogdanm	82:6473597d706e	270	//@}
bogdanm	82:6473597d706e	271
bogdanm	82:6473597d706e	272	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	273	// HW_UART_BDL - UART Baud Rate Registers: Low
bogdanm	82:6473597d706e	274	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	275
bogdanm	82:6473597d706e	276	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	277	/*!
bogdanm	82:6473597d706e	278	* @brief HW_UART_BDL - UART Baud Rate Registers: Low (RW)
bogdanm	82:6473597d706e	279	*
bogdanm	82:6473597d706e	280	* Reset value: 0x04U
bogdanm	82:6473597d706e	281	*
bogdanm	82:6473597d706e	282	* This register, along with the BDH register, controls the prescale divisor for
bogdanm	82:6473597d706e	283	* UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
bogdanm	82:6473597d706e	284	* first write to BDH to buffer the high half of the new value and then write to
bogdanm	82:6473597d706e	285	* BDL. The working value in BDH does not change until BDL is written. BDL is
bogdanm	82:6473597d706e	286	* reset to a nonzero value, but after reset, the baud rate generator remains
bogdanm	82:6473597d706e	287	* disabled until the first time the receiver or transmitter is enabled, that is, when
bogdanm	82:6473597d706e	288	* C2[RE] or C2[TE] is set.
bogdanm	82:6473597d706e	289	*/
bogdanm	82:6473597d706e	290	typedef union _hw_uart_bdl
bogdanm	82:6473597d706e	291	{
bogdanm	82:6473597d706e	292	uint8_t U;
bogdanm	82:6473597d706e	293	struct _hw_uart_bdl_bitfields
bogdanm	82:6473597d706e	294	{
bogdanm	82:6473597d706e	295	uint8_t SBR : 8; //!< [7:0] UART Baud Rate Bits
bogdanm	82:6473597d706e	296	} B;
bogdanm	82:6473597d706e	297	} hw_uart_bdl_t;
bogdanm	82:6473597d706e	298	#endif
bogdanm	82:6473597d706e	299
bogdanm	82:6473597d706e	300	/*!
bogdanm	82:6473597d706e	301	* @name Constants and macros for entire UART_BDL register
bogdanm	82:6473597d706e	302	*/
bogdanm	82:6473597d706e	303	//@{
bogdanm	82:6473597d706e	304	#define HW_UART_BDL_ADDR(x) (REGS_UART_BASE(x) + 0x1U)
bogdanm	82:6473597d706e	305
bogdanm	82:6473597d706e	306	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	307	#define HW_UART_BDL(x) ((__IO hw_uart_bdl_t ) HW_UART_BDL_ADDR(x))
bogdanm	82:6473597d706e	308	#define HW_UART_BDL_RD(x) (HW_UART_BDL(x).U)
bogdanm	82:6473597d706e	309	#define HW_UART_BDL_WR(x, v) (HW_UART_BDL(x).U = (v))
bogdanm	82:6473597d706e	310	#define HW_UART_BDL_SET(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) \| (v)))
bogdanm	82:6473597d706e	311	#define HW_UART_BDL_CLR(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) & ~(v)))
bogdanm	82:6473597d706e	312	#define HW_UART_BDL_TOG(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) ^ (v)))
bogdanm	82:6473597d706e	313	#endif
bogdanm	82:6473597d706e	314	//@}
bogdanm	82:6473597d706e	315
bogdanm	82:6473597d706e	316	/*
bogdanm	82:6473597d706e	317	* Constants & macros for individual UART_BDL bitfields
bogdanm	82:6473597d706e	318	*/
bogdanm	82:6473597d706e	319
bogdanm	82:6473597d706e	320	/*!
bogdanm	82:6473597d706e	321	* @name Register UART_BDL, field SBR[7:0] (RW)
bogdanm	82:6473597d706e	322	*
bogdanm	82:6473597d706e	323	* The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
bogdanm	82:6473597d706e	324	* generation for details. The baud rate generator is disabled until C2[TE] or
bogdanm	82:6473597d706e	325	* C2[RE] is set for the first time after reset.The baud rate generator is disabled
bogdanm	82:6473597d706e	326	* when SBR = 0. Writing to BDH has no effect without writing to BDL, because
bogdanm	82:6473597d706e	327	* writing to BDH puts the data in a temporary location until BDL is written. When
bogdanm	82:6473597d706e	328	* the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate
bogdanm	82:6473597d706e	329	* fields must be even, the least significant bit is 0. See MODEM register for more
bogdanm	82:6473597d706e	330	* details.
bogdanm	82:6473597d706e	331	*/
bogdanm	82:6473597d706e	332	//@{
bogdanm	82:6473597d706e	333	#define BP_UART_BDL_SBR (0U) //!< Bit position for UART_BDL_SBR.
bogdanm	82:6473597d706e	334	#define BM_UART_BDL_SBR (0xFFU) //!< Bit mask for UART_BDL_SBR.
bogdanm	82:6473597d706e	335	#define BS_UART_BDL_SBR (8U) //!< Bit field size in bits for UART_BDL_SBR.
bogdanm	82:6473597d706e	336
bogdanm	82:6473597d706e	337	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	338	//! @brief Read current value of the UART_BDL_SBR field.
bogdanm	82:6473597d706e	339	#define BR_UART_BDL_SBR(x) (HW_UART_BDL(x).U)
bogdanm	82:6473597d706e	340	#endif
bogdanm	82:6473597d706e	341
bogdanm	82:6473597d706e	342	//! @brief Format value for bitfield UART_BDL_SBR.
bogdanm	82:6473597d706e	343	#define BF_UART_BDL_SBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDL_SBR), uint8_t) & BM_UART_BDL_SBR)
bogdanm	82:6473597d706e	344
bogdanm	82:6473597d706e	345	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	346	//! @brief Set the SBR field to a new value.
bogdanm	82:6473597d706e	347	#define BW_UART_BDL_SBR(x, v) (HW_UART_BDL_WR(x, v))
bogdanm	82:6473597d706e	348	#endif
bogdanm	82:6473597d706e	349	//@}
bogdanm	82:6473597d706e	350
bogdanm	82:6473597d706e	351	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	352	// HW_UART_C1 - UART Control Register 1
bogdanm	82:6473597d706e	353	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	354
bogdanm	82:6473597d706e	355	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	356	/*!
bogdanm	82:6473597d706e	357	* @brief HW_UART_C1 - UART Control Register 1 (RW)
bogdanm	82:6473597d706e	358	*
bogdanm	82:6473597d706e	359	* Reset value: 0x00U
bogdanm	82:6473597d706e	360	*
bogdanm	82:6473597d706e	361	* This read/write register controls various optional features of the UART
bogdanm	82:6473597d706e	362	* system.
bogdanm	82:6473597d706e	363	*/
bogdanm	82:6473597d706e	364	typedef union _hw_uart_c1
bogdanm	82:6473597d706e	365	{
bogdanm	82:6473597d706e	366	uint8_t U;
bogdanm	82:6473597d706e	367	struct _hw_uart_c1_bitfields
bogdanm	82:6473597d706e	368	{
bogdanm	82:6473597d706e	369	uint8_t PT : 1; //!< [0] Parity Type
bogdanm	82:6473597d706e	370	uint8_t PE : 1; //!< [1] Parity Enable
bogdanm	82:6473597d706e	371	uint8_t ILT : 1; //!< [2] Idle Line Type Select
bogdanm	82:6473597d706e	372	uint8_t WAKE : 1; //!< [3] Receiver Wakeup Method Select
bogdanm	82:6473597d706e	373	uint8_t M : 1; //!< [4] 9-bit or 8-bit Mode Select
bogdanm	82:6473597d706e	374	uint8_t RSRC : 1; //!< [5] Receiver Source Select
bogdanm	82:6473597d706e	375	uint8_t UARTSWAI : 1; //!< [6] UART Stops in Wait Mode
bogdanm	82:6473597d706e	376	uint8_t LOOPS : 1; //!< [7] Loop Mode Select
bogdanm	82:6473597d706e	377	} B;
bogdanm	82:6473597d706e	378	} hw_uart_c1_t;
bogdanm	82:6473597d706e	379	#endif
bogdanm	82:6473597d706e	380
bogdanm	82:6473597d706e	381	/*!
bogdanm	82:6473597d706e	382	* @name Constants and macros for entire UART_C1 register
bogdanm	82:6473597d706e	383	*/
bogdanm	82:6473597d706e	384	//@{
bogdanm	82:6473597d706e	385	#define HW_UART_C1_ADDR(x) (REGS_UART_BASE(x) + 0x2U)
bogdanm	82:6473597d706e	386
bogdanm	82:6473597d706e	387	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	388	#define HW_UART_C1(x) ((__IO hw_uart_c1_t ) HW_UART_C1_ADDR(x))
bogdanm	82:6473597d706e	389	#define HW_UART_C1_RD(x) (HW_UART_C1(x).U)
bogdanm	82:6473597d706e	390	#define HW_UART_C1_WR(x, v) (HW_UART_C1(x).U = (v))
bogdanm	82:6473597d706e	391	#define HW_UART_C1_SET(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) \| (v)))
bogdanm	82:6473597d706e	392	#define HW_UART_C1_CLR(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	393	#define HW_UART_C1_TOG(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	394	#endif
bogdanm	82:6473597d706e	395	//@}
bogdanm	82:6473597d706e	396
bogdanm	82:6473597d706e	397	/*
bogdanm	82:6473597d706e	398	* Constants & macros for individual UART_C1 bitfields
bogdanm	82:6473597d706e	399	*/
bogdanm	82:6473597d706e	400
bogdanm	82:6473597d706e	401	/*!
bogdanm	82:6473597d706e	402	* @name Register UART_C1, field PT[0] (RW)
bogdanm	82:6473597d706e	403	*
bogdanm	82:6473597d706e	404	* Determines whether the UART generates and checks for even parity or odd
bogdanm	82:6473597d706e	405	* parity. With even parity, an even number of 1s clears the parity bit and an odd
bogdanm	82:6473597d706e	406	* number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
bogdanm	82:6473597d706e	407	* parity bit and an even number of 1s sets the parity bit. This field must be
bogdanm	82:6473597d706e	408	* cleared when C7816[ISO_7816E] is set/enabled.
bogdanm	82:6473597d706e	409	*
bogdanm	82:6473597d706e	410	* Values:
bogdanm	82:6473597d706e	411	* - 0 - Even parity.
bogdanm	82:6473597d706e	412	* - 1 - Odd parity.
bogdanm	82:6473597d706e	413	*/
bogdanm	82:6473597d706e	414	//@{
bogdanm	82:6473597d706e	415	#define BP_UART_C1_PT (0U) //!< Bit position for UART_C1_PT.
bogdanm	82:6473597d706e	416	#define BM_UART_C1_PT (0x01U) //!< Bit mask for UART_C1_PT.
bogdanm	82:6473597d706e	417	#define BS_UART_C1_PT (1U) //!< Bit field size in bits for UART_C1_PT.
bogdanm	82:6473597d706e	418
bogdanm	82:6473597d706e	419	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	420	//! @brief Read current value of the UART_C1_PT field.
bogdanm	82:6473597d706e	421	#define BR_UART_C1_PT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT))
bogdanm	82:6473597d706e	422	#endif
bogdanm	82:6473597d706e	423
bogdanm	82:6473597d706e	424	//! @brief Format value for bitfield UART_C1_PT.
bogdanm	82:6473597d706e	425	#define BF_UART_C1_PT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_PT), uint8_t) & BM_UART_C1_PT)
bogdanm	82:6473597d706e	426
bogdanm	82:6473597d706e	427	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	428	//! @brief Set the PT field to a new value.
bogdanm	82:6473597d706e	429	#define BW_UART_C1_PT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT) = (v))
bogdanm	82:6473597d706e	430	#endif
bogdanm	82:6473597d706e	431	//@}
bogdanm	82:6473597d706e	432
bogdanm	82:6473597d706e	433	/*!
bogdanm	82:6473597d706e	434	* @name Register UART_C1, field PE[1] (RW)
bogdanm	82:6473597d706e	435	*
bogdanm	82:6473597d706e	436	* Enables the parity function. When parity is enabled, parity function inserts
bogdanm	82:6473597d706e	437	* a parity bit in the bit position immediately preceding the stop bit. This
bogdanm	82:6473597d706e	438	* field must be set when C7816[ISO_7816E] is set/enabled.
bogdanm	82:6473597d706e	439	*
bogdanm	82:6473597d706e	440	* Values:
bogdanm	82:6473597d706e	441	* - 0 - Parity function disabled.
bogdanm	82:6473597d706e	442	* - 1 - Parity function enabled.
bogdanm	82:6473597d706e	443	*/
bogdanm	82:6473597d706e	444	//@{
bogdanm	82:6473597d706e	445	#define BP_UART_C1_PE (1U) //!< Bit position for UART_C1_PE.
bogdanm	82:6473597d706e	446	#define BM_UART_C1_PE (0x02U) //!< Bit mask for UART_C1_PE.
bogdanm	82:6473597d706e	447	#define BS_UART_C1_PE (1U) //!< Bit field size in bits for UART_C1_PE.
bogdanm	82:6473597d706e	448
bogdanm	82:6473597d706e	449	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	450	//! @brief Read current value of the UART_C1_PE field.
bogdanm	82:6473597d706e	451	#define BR_UART_C1_PE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE))
bogdanm	82:6473597d706e	452	#endif
bogdanm	82:6473597d706e	453
bogdanm	82:6473597d706e	454	//! @brief Format value for bitfield UART_C1_PE.
bogdanm	82:6473597d706e	455	#define BF_UART_C1_PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_PE), uint8_t) & BM_UART_C1_PE)
bogdanm	82:6473597d706e	456
bogdanm	82:6473597d706e	457	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	458	//! @brief Set the PE field to a new value.
bogdanm	82:6473597d706e	459	#define BW_UART_C1_PE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE) = (v))
bogdanm	82:6473597d706e	460	#endif
bogdanm	82:6473597d706e	461	//@}
bogdanm	82:6473597d706e	462
bogdanm	82:6473597d706e	463	/*!
bogdanm	82:6473597d706e	464	* @name Register UART_C1, field ILT[2] (RW)
bogdanm	82:6473597d706e	465	*
bogdanm	82:6473597d706e	466	* Determines when the receiver starts counting logic 1s as idle character bits.
bogdanm	82:6473597d706e	467	* The count begins either after a valid start bit or after the stop bit. If the
bogdanm	82:6473597d706e	468	* count begins after the start bit, then a string of logic 1s preceding the
bogdanm	82:6473597d706e	469	* stop bit can cause false recognition of an idle character. Beginning the count
bogdanm	82:6473597d706e	470	* after the stop bit avoids false idle character recognition, but requires
bogdanm	82:6473597d706e	471	* properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
bogdanm	82:6473597d706e	472	* logic of 1'b0 is automatically shifted after a received stop bit, therefore
bogdanm	82:6473597d706e	473	* resetting the idle count. In case the UART is programmed for IDLE line wakeup
bogdanm	82:6473597d706e	474	* (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
bogdanm	82:6473597d706e	475	* logic 1s as idle character bits. In idle line wakeup, an idle character is
bogdanm	82:6473597d706e	476	* recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
bogdanm	82:6473597d706e	477	* and C4[M10] fields.
bogdanm	82:6473597d706e	478	*
bogdanm	82:6473597d706e	479	* Values:
bogdanm	82:6473597d706e	480	* - 0 - Idle character bit count starts after start bit.
bogdanm	82:6473597d706e	481	* - 1 - Idle character bit count starts after stop bit.
bogdanm	82:6473597d706e	482	*/
bogdanm	82:6473597d706e	483	//@{
bogdanm	82:6473597d706e	484	#define BP_UART_C1_ILT (2U) //!< Bit position for UART_C1_ILT.
bogdanm	82:6473597d706e	485	#define BM_UART_C1_ILT (0x04U) //!< Bit mask for UART_C1_ILT.
bogdanm	82:6473597d706e	486	#define BS_UART_C1_ILT (1U) //!< Bit field size in bits for UART_C1_ILT.
bogdanm	82:6473597d706e	487
bogdanm	82:6473597d706e	488	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	489	//! @brief Read current value of the UART_C1_ILT field.
bogdanm	82:6473597d706e	490	#define BR_UART_C1_ILT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT))
bogdanm	82:6473597d706e	491	#endif
bogdanm	82:6473597d706e	492
bogdanm	82:6473597d706e	493	//! @brief Format value for bitfield UART_C1_ILT.
bogdanm	82:6473597d706e	494	#define BF_UART_C1_ILT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_ILT), uint8_t) & BM_UART_C1_ILT)
bogdanm	82:6473597d706e	495
bogdanm	82:6473597d706e	496	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	497	//! @brief Set the ILT field to a new value.
bogdanm	82:6473597d706e	498	#define BW_UART_C1_ILT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT) = (v))
bogdanm	82:6473597d706e	499	#endif
bogdanm	82:6473597d706e	500	//@}
bogdanm	82:6473597d706e	501
bogdanm	82:6473597d706e	502	/*!
bogdanm	82:6473597d706e	503	* @name Register UART_C1, field WAKE[3] (RW)
bogdanm	82:6473597d706e	504	*
bogdanm	82:6473597d706e	505	* Determines which condition wakes the UART: Address mark in the most
bogdanm	82:6473597d706e	506	* significant bit position of a received data character, or An idle condition on the
bogdanm	82:6473597d706e	507	* receive pin input signal.
bogdanm	82:6473597d706e	508	*
bogdanm	82:6473597d706e	509	* Values:
bogdanm	82:6473597d706e	510	* - 0 - Idle line wakeup.
bogdanm	82:6473597d706e	511	* - 1 - Address mark wakeup.
bogdanm	82:6473597d706e	512	*/
bogdanm	82:6473597d706e	513	//@{
bogdanm	82:6473597d706e	514	#define BP_UART_C1_WAKE (3U) //!< Bit position for UART_C1_WAKE.
bogdanm	82:6473597d706e	515	#define BM_UART_C1_WAKE (0x08U) //!< Bit mask for UART_C1_WAKE.
bogdanm	82:6473597d706e	516	#define BS_UART_C1_WAKE (1U) //!< Bit field size in bits for UART_C1_WAKE.
bogdanm	82:6473597d706e	517
bogdanm	82:6473597d706e	518	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	519	//! @brief Read current value of the UART_C1_WAKE field.
bogdanm	82:6473597d706e	520	#define BR_UART_C1_WAKE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE))
bogdanm	82:6473597d706e	521	#endif
bogdanm	82:6473597d706e	522
bogdanm	82:6473597d706e	523	//! @brief Format value for bitfield UART_C1_WAKE.
bogdanm	82:6473597d706e	524	#define BF_UART_C1_WAKE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_WAKE), uint8_t) & BM_UART_C1_WAKE)
bogdanm	82:6473597d706e	525
bogdanm	82:6473597d706e	526	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	527	//! @brief Set the WAKE field to a new value.
bogdanm	82:6473597d706e	528	#define BW_UART_C1_WAKE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE) = (v))
bogdanm	82:6473597d706e	529	#endif
bogdanm	82:6473597d706e	530	//@}
bogdanm	82:6473597d706e	531
bogdanm	82:6473597d706e	532	/*!
bogdanm	82:6473597d706e	533	* @name Register UART_C1, field M[4] (RW)
bogdanm	82:6473597d706e	534	*
bogdanm	82:6473597d706e	535	* This field must be set when C7816[ISO_7816E] is set/enabled.
bogdanm	82:6473597d706e	536	*
bogdanm	82:6473597d706e	537	* Values:
bogdanm	82:6473597d706e	538	* - 0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
bogdanm	82:6473597d706e	539	* - 1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
bogdanm	82:6473597d706e	540	*/
bogdanm	82:6473597d706e	541	//@{
bogdanm	82:6473597d706e	542	#define BP_UART_C1_M (4U) //!< Bit position for UART_C1_M.
bogdanm	82:6473597d706e	543	#define BM_UART_C1_M (0x10U) //!< Bit mask for UART_C1_M.
bogdanm	82:6473597d706e	544	#define BS_UART_C1_M (1U) //!< Bit field size in bits for UART_C1_M.
bogdanm	82:6473597d706e	545
bogdanm	82:6473597d706e	546	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	547	//! @brief Read current value of the UART_C1_M field.
bogdanm	82:6473597d706e	548	#define BR_UART_C1_M(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M))
bogdanm	82:6473597d706e	549	#endif
bogdanm	82:6473597d706e	550
bogdanm	82:6473597d706e	551	//! @brief Format value for bitfield UART_C1_M.
bogdanm	82:6473597d706e	552	#define BF_UART_C1_M(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_M), uint8_t) & BM_UART_C1_M)
bogdanm	82:6473597d706e	553
bogdanm	82:6473597d706e	554	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	555	//! @brief Set the M field to a new value.
bogdanm	82:6473597d706e	556	#define BW_UART_C1_M(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M) = (v))
bogdanm	82:6473597d706e	557	#endif
bogdanm	82:6473597d706e	558	//@}
bogdanm	82:6473597d706e	559
bogdanm	82:6473597d706e	560	/*!
bogdanm	82:6473597d706e	561	* @name Register UART_C1, field RSRC[5] (RW)
bogdanm	82:6473597d706e	562	*
bogdanm	82:6473597d706e	563	* This field has no meaning or effect unless the LOOPS field is set. When LOOPS
bogdanm	82:6473597d706e	564	* is set, the RSRC field determines the source for the receiver shift register
bogdanm	82:6473597d706e	565	* input.
bogdanm	82:6473597d706e	566	*
bogdanm	82:6473597d706e	567	* Values:
bogdanm	82:6473597d706e	568	* - 0 - Selects internal loop back mode. The receiver input is internally
bogdanm	82:6473597d706e	569	* connected to transmitter output.
bogdanm	82:6473597d706e	570	* - 1 - Single wire UART mode where the receiver input is connected to the
bogdanm	82:6473597d706e	571	* transmit pin input signal.
bogdanm	82:6473597d706e	572	*/
bogdanm	82:6473597d706e	573	//@{
bogdanm	82:6473597d706e	574	#define BP_UART_C1_RSRC (5U) //!< Bit position for UART_C1_RSRC.
bogdanm	82:6473597d706e	575	#define BM_UART_C1_RSRC (0x20U) //!< Bit mask for UART_C1_RSRC.
bogdanm	82:6473597d706e	576	#define BS_UART_C1_RSRC (1U) //!< Bit field size in bits for UART_C1_RSRC.
bogdanm	82:6473597d706e	577
bogdanm	82:6473597d706e	578	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	579	//! @brief Read current value of the UART_C1_RSRC field.
bogdanm	82:6473597d706e	580	#define BR_UART_C1_RSRC(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC))
bogdanm	82:6473597d706e	581	#endif
bogdanm	82:6473597d706e	582
bogdanm	82:6473597d706e	583	//! @brief Format value for bitfield UART_C1_RSRC.
bogdanm	82:6473597d706e	584	#define BF_UART_C1_RSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_RSRC), uint8_t) & BM_UART_C1_RSRC)
bogdanm	82:6473597d706e	585
bogdanm	82:6473597d706e	586	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	587	//! @brief Set the RSRC field to a new value.
bogdanm	82:6473597d706e	588	#define BW_UART_C1_RSRC(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC) = (v))
bogdanm	82:6473597d706e	589	#endif
bogdanm	82:6473597d706e	590	//@}
bogdanm	82:6473597d706e	591
bogdanm	82:6473597d706e	592	/*!
bogdanm	82:6473597d706e	593	* @name Register UART_C1, field UARTSWAI[6] (RW)
bogdanm	82:6473597d706e	594	*
bogdanm	82:6473597d706e	595	* Values:
bogdanm	82:6473597d706e	596	* - 0 - UART clock continues to run in Wait mode.
bogdanm	82:6473597d706e	597	* - 1 - UART clock freezes while CPU is in Wait mode.
bogdanm	82:6473597d706e	598	*/
bogdanm	82:6473597d706e	599	//@{
bogdanm	82:6473597d706e	600	#define BP_UART_C1_UARTSWAI (6U) //!< Bit position for UART_C1_UARTSWAI.
bogdanm	82:6473597d706e	601	#define BM_UART_C1_UARTSWAI (0x40U) //!< Bit mask for UART_C1_UARTSWAI.
bogdanm	82:6473597d706e	602	#define BS_UART_C1_UARTSWAI (1U) //!< Bit field size in bits for UART_C1_UARTSWAI.
bogdanm	82:6473597d706e	603
bogdanm	82:6473597d706e	604	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	605	//! @brief Read current value of the UART_C1_UARTSWAI field.
bogdanm	82:6473597d706e	606	#define BR_UART_C1_UARTSWAI(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI))
bogdanm	82:6473597d706e	607	#endif
bogdanm	82:6473597d706e	608
bogdanm	82:6473597d706e	609	//! @brief Format value for bitfield UART_C1_UARTSWAI.
bogdanm	82:6473597d706e	610	#define BF_UART_C1_UARTSWAI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_UARTSWAI), uint8_t) & BM_UART_C1_UARTSWAI)
bogdanm	82:6473597d706e	611
bogdanm	82:6473597d706e	612	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	613	//! @brief Set the UARTSWAI field to a new value.
bogdanm	82:6473597d706e	614	#define BW_UART_C1_UARTSWAI(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI) = (v))
bogdanm	82:6473597d706e	615	#endif
bogdanm	82:6473597d706e	616	//@}
bogdanm	82:6473597d706e	617
bogdanm	82:6473597d706e	618	/*!
bogdanm	82:6473597d706e	619	* @name Register UART_C1, field LOOPS[7] (RW)
bogdanm	82:6473597d706e	620	*
bogdanm	82:6473597d706e	621	* When LOOPS is set, the RxD pin is disconnected from the UART and the
bogdanm	82:6473597d706e	622	* transmitter output is internally connected to the receiver input. The transmitter and
bogdanm	82:6473597d706e	623	* the receiver must be enabled to use the loop function.
bogdanm	82:6473597d706e	624	*
bogdanm	82:6473597d706e	625	* Values:
bogdanm	82:6473597d706e	626	* - 0 - Normal operation.
bogdanm	82:6473597d706e	627	* - 1 - Loop mode where transmitter output is internally connected to receiver
bogdanm	82:6473597d706e	628	* input. The receiver input is determined by RSRC.
bogdanm	82:6473597d706e	629	*/
bogdanm	82:6473597d706e	630	//@{
bogdanm	82:6473597d706e	631	#define BP_UART_C1_LOOPS (7U) //!< Bit position for UART_C1_LOOPS.
bogdanm	82:6473597d706e	632	#define BM_UART_C1_LOOPS (0x80U) //!< Bit mask for UART_C1_LOOPS.
bogdanm	82:6473597d706e	633	#define BS_UART_C1_LOOPS (1U) //!< Bit field size in bits for UART_C1_LOOPS.
bogdanm	82:6473597d706e	634
bogdanm	82:6473597d706e	635	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	636	//! @brief Read current value of the UART_C1_LOOPS field.
bogdanm	82:6473597d706e	637	#define BR_UART_C1_LOOPS(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS))
bogdanm	82:6473597d706e	638	#endif
bogdanm	82:6473597d706e	639
bogdanm	82:6473597d706e	640	//! @brief Format value for bitfield UART_C1_LOOPS.
bogdanm	82:6473597d706e	641	#define BF_UART_C1_LOOPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_LOOPS), uint8_t) & BM_UART_C1_LOOPS)
bogdanm	82:6473597d706e	642
bogdanm	82:6473597d706e	643	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	644	//! @brief Set the LOOPS field to a new value.
bogdanm	82:6473597d706e	645	#define BW_UART_C1_LOOPS(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS) = (v))
bogdanm	82:6473597d706e	646	#endif
bogdanm	82:6473597d706e	647	//@}
bogdanm	82:6473597d706e	648
bogdanm	82:6473597d706e	649	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	650	// HW_UART_C2 - UART Control Register 2
bogdanm	82:6473597d706e	651	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	652
bogdanm	82:6473597d706e	653	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	654	/*!
bogdanm	82:6473597d706e	655	* @brief HW_UART_C2 - UART Control Register 2 (RW)
bogdanm	82:6473597d706e	656	*
bogdanm	82:6473597d706e	657	* Reset value: 0x00U
bogdanm	82:6473597d706e	658	*
bogdanm	82:6473597d706e	659	* This register can be read or written at any time.
bogdanm	82:6473597d706e	660	*/
bogdanm	82:6473597d706e	661	typedef union _hw_uart_c2
bogdanm	82:6473597d706e	662	{
bogdanm	82:6473597d706e	663	uint8_t U;
bogdanm	82:6473597d706e	664	struct _hw_uart_c2_bitfields
bogdanm	82:6473597d706e	665	{
bogdanm	82:6473597d706e	666	uint8_t SBK : 1; //!< [0] Send Break
bogdanm	82:6473597d706e	667	uint8_t RWU : 1; //!< [1] Receiver Wakeup Control
bogdanm	82:6473597d706e	668	uint8_t RE : 1; //!< [2] Receiver Enable
bogdanm	82:6473597d706e	669	uint8_t TE : 1; //!< [3] Transmitter Enable
bogdanm	82:6473597d706e	670	uint8_t ILIE : 1; //!< [4] Idle Line Interrupt DMA Transfer Enable
bogdanm	82:6473597d706e	671	uint8_t RIE : 1; //!< [5] Receiver Full Interrupt or DMA Transfer
bogdanm	82:6473597d706e	672	//! Enable
bogdanm	82:6473597d706e	673	uint8_t TCIE : 1; //!< [6] Transmission Complete Interrupt or DMA
bogdanm	82:6473597d706e	674	//! Transfer Enable
bogdanm	82:6473597d706e	675	uint8_t TIE : 1; //!< [7] Transmitter Interrupt or DMA Transfer
bogdanm	82:6473597d706e	676	//! Enable.
bogdanm	82:6473597d706e	677	} B;
bogdanm	82:6473597d706e	678	} hw_uart_c2_t;
bogdanm	82:6473597d706e	679	#endif
bogdanm	82:6473597d706e	680
bogdanm	82:6473597d706e	681	/*!
bogdanm	82:6473597d706e	682	* @name Constants and macros for entire UART_C2 register
bogdanm	82:6473597d706e	683	*/
bogdanm	82:6473597d706e	684	//@{
bogdanm	82:6473597d706e	685	#define HW_UART_C2_ADDR(x) (REGS_UART_BASE(x) + 0x3U)
bogdanm	82:6473597d706e	686
bogdanm	82:6473597d706e	687	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	688	#define HW_UART_C2(x) ((__IO hw_uart_c2_t ) HW_UART_C2_ADDR(x))
bogdanm	82:6473597d706e	689	#define HW_UART_C2_RD(x) (HW_UART_C2(x).U)
bogdanm	82:6473597d706e	690	#define HW_UART_C2_WR(x, v) (HW_UART_C2(x).U = (v))
bogdanm	82:6473597d706e	691	#define HW_UART_C2_SET(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) \| (v)))
bogdanm	82:6473597d706e	692	#define HW_UART_C2_CLR(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) & ~(v)))
bogdanm	82:6473597d706e	693	#define HW_UART_C2_TOG(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) ^ (v)))
bogdanm	82:6473597d706e	694	#endif
bogdanm	82:6473597d706e	695	//@}
bogdanm	82:6473597d706e	696
bogdanm	82:6473597d706e	697	/*
bogdanm	82:6473597d706e	698	* Constants & macros for individual UART_C2 bitfields
bogdanm	82:6473597d706e	699	*/
bogdanm	82:6473597d706e	700
bogdanm	82:6473597d706e	701	/*!
bogdanm	82:6473597d706e	702	* @name Register UART_C2, field SBK[0] (RW)
bogdanm	82:6473597d706e	703	*
bogdanm	82:6473597d706e	704	* Toggling SBK sends one break character from the following: See Transmitting
bogdanm	82:6473597d706e	705	* break characters for the number of logic 0s for the different configurations.
bogdanm	82:6473597d706e	706	* Toggling implies clearing the SBK field before the break character has finished
bogdanm	82:6473597d706e	707	* transmitting. As long as SBK is set, the transmitter continues to send
bogdanm	82:6473597d706e	708	* complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits).
bogdanm	82:6473597d706e	709	* Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit.
bogdanm	82:6473597d706e	710	* 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13]
bogdanm	82:6473597d706e	711	* is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when
bogdanm	82:6473597d706e	712	* C7816[ISO_7816E] is set.
bogdanm	82:6473597d706e	713	*
bogdanm	82:6473597d706e	714	* Values:
bogdanm	82:6473597d706e	715	* - 0 - Normal transmitter operation.
bogdanm	82:6473597d706e	716	* - 1 - Queue break characters to be sent.
bogdanm	82:6473597d706e	717	*/
bogdanm	82:6473597d706e	718	//@{
bogdanm	82:6473597d706e	719	#define BP_UART_C2_SBK (0U) //!< Bit position for UART_C2_SBK.
bogdanm	82:6473597d706e	720	#define BM_UART_C2_SBK (0x01U) //!< Bit mask for UART_C2_SBK.
bogdanm	82:6473597d706e	721	#define BS_UART_C2_SBK (1U) //!< Bit field size in bits for UART_C2_SBK.
bogdanm	82:6473597d706e	722
bogdanm	82:6473597d706e	723	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	724	//! @brief Read current value of the UART_C2_SBK field.
bogdanm	82:6473597d706e	725	#define BR_UART_C2_SBK(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK))
bogdanm	82:6473597d706e	726	#endif
bogdanm	82:6473597d706e	727
bogdanm	82:6473597d706e	728	//! @brief Format value for bitfield UART_C2_SBK.
bogdanm	82:6473597d706e	729	#define BF_UART_C2_SBK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_SBK), uint8_t) & BM_UART_C2_SBK)
bogdanm	82:6473597d706e	730
bogdanm	82:6473597d706e	731	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	732	//! @brief Set the SBK field to a new value.
bogdanm	82:6473597d706e	733	#define BW_UART_C2_SBK(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK) = (v))
bogdanm	82:6473597d706e	734	#endif
bogdanm	82:6473597d706e	735	//@}
bogdanm	82:6473597d706e	736
bogdanm	82:6473597d706e	737	/*!
bogdanm	82:6473597d706e	738	* @name Register UART_C2, field RWU[1] (RW)
bogdanm	82:6473597d706e	739	*
bogdanm	82:6473597d706e	740	* This field can be set to place the UART receiver in a standby state. RWU
bogdanm	82:6473597d706e	741	* automatically clears when an RWU event occurs, that is, an IDLE event when
bogdanm	82:6473597d706e	742	* C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
bogdanm	82:6473597d706e	743	* cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
bogdanm	82:6473597d706e	744	* on idle) if the channel is currently not idle. This can be determined by
bogdanm	82:6473597d706e	745	* S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
bogdanm	82:6473597d706e	746	* idle, it is possible that the UART will discard data. This is because the data
bogdanm	82:6473597d706e	747	* must be received or a LIN break detected after an IDLE is detected before IDLE
bogdanm	82:6473597d706e	748	* is allowed to reasserted.
bogdanm	82:6473597d706e	749	*
bogdanm	82:6473597d706e	750	* Values:
bogdanm	82:6473597d706e	751	* - 0 - Normal operation.
bogdanm	82:6473597d706e	752	* - 1 - RWU enables the wakeup function and inhibits further receiver interrupt
bogdanm	82:6473597d706e	753	* requests. Normally, hardware wakes the receiver by automatically clearing
bogdanm	82:6473597d706e	754	* RWU.
bogdanm	82:6473597d706e	755	*/
bogdanm	82:6473597d706e	756	//@{
bogdanm	82:6473597d706e	757	#define BP_UART_C2_RWU (1U) //!< Bit position for UART_C2_RWU.
bogdanm	82:6473597d706e	758	#define BM_UART_C2_RWU (0x02U) //!< Bit mask for UART_C2_RWU.
bogdanm	82:6473597d706e	759	#define BS_UART_C2_RWU (1U) //!< Bit field size in bits for UART_C2_RWU.
bogdanm	82:6473597d706e	760
bogdanm	82:6473597d706e	761	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	762	//! @brief Read current value of the UART_C2_RWU field.
bogdanm	82:6473597d706e	763	#define BR_UART_C2_RWU(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU))
bogdanm	82:6473597d706e	764	#endif
bogdanm	82:6473597d706e	765
bogdanm	82:6473597d706e	766	//! @brief Format value for bitfield UART_C2_RWU.
bogdanm	82:6473597d706e	767	#define BF_UART_C2_RWU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RWU), uint8_t) & BM_UART_C2_RWU)
bogdanm	82:6473597d706e	768
bogdanm	82:6473597d706e	769	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	770	//! @brief Set the RWU field to a new value.
bogdanm	82:6473597d706e	771	#define BW_UART_C2_RWU(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU) = (v))
bogdanm	82:6473597d706e	772	#endif
bogdanm	82:6473597d706e	773	//@}
bogdanm	82:6473597d706e	774
bogdanm	82:6473597d706e	775	/*!
bogdanm	82:6473597d706e	776	* @name Register UART_C2, field RE[2] (RW)
bogdanm	82:6473597d706e	777	*
bogdanm	82:6473597d706e	778	* Enables the UART receiver.
bogdanm	82:6473597d706e	779	*
bogdanm	82:6473597d706e	780	* Values:
bogdanm	82:6473597d706e	781	* - 0 - Receiver off.
bogdanm	82:6473597d706e	782	* - 1 - Receiver on.
bogdanm	82:6473597d706e	783	*/
bogdanm	82:6473597d706e	784	//@{
bogdanm	82:6473597d706e	785	#define BP_UART_C2_RE (2U) //!< Bit position for UART_C2_RE.
bogdanm	82:6473597d706e	786	#define BM_UART_C2_RE (0x04U) //!< Bit mask for UART_C2_RE.
bogdanm	82:6473597d706e	787	#define BS_UART_C2_RE (1U) //!< Bit field size in bits for UART_C2_RE.
bogdanm	82:6473597d706e	788
bogdanm	82:6473597d706e	789	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	790	//! @brief Read current value of the UART_C2_RE field.
bogdanm	82:6473597d706e	791	#define BR_UART_C2_RE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE))
bogdanm	82:6473597d706e	792	#endif
bogdanm	82:6473597d706e	793
bogdanm	82:6473597d706e	794	//! @brief Format value for bitfield UART_C2_RE.
bogdanm	82:6473597d706e	795	#define BF_UART_C2_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RE), uint8_t) & BM_UART_C2_RE)
bogdanm	82:6473597d706e	796
bogdanm	82:6473597d706e	797	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	798	//! @brief Set the RE field to a new value.
bogdanm	82:6473597d706e	799	#define BW_UART_C2_RE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE) = (v))
bogdanm	82:6473597d706e	800	#endif
bogdanm	82:6473597d706e	801	//@}
bogdanm	82:6473597d706e	802
bogdanm	82:6473597d706e	803	/*!
bogdanm	82:6473597d706e	804	* @name Register UART_C2, field TE[3] (RW)
bogdanm	82:6473597d706e	805	*
bogdanm	82:6473597d706e	806	* Enables the UART transmitter. TE can be used to queue an idle preamble by
bogdanm	82:6473597d706e	807	* clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
bogdanm	82:6473597d706e	808	* C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
bogdanm	82:6473597d706e	809	* transmitted. This condition is detected when TL7816[TLEN] = 0 and four
bogdanm	82:6473597d706e	810	* additional characters are transmitted.
bogdanm	82:6473597d706e	811	*
bogdanm	82:6473597d706e	812	* Values:
bogdanm	82:6473597d706e	813	* - 0 - Transmitter off.
bogdanm	82:6473597d706e	814	* - 1 - Transmitter on.
bogdanm	82:6473597d706e	815	*/
bogdanm	82:6473597d706e	816	//@{
bogdanm	82:6473597d706e	817	#define BP_UART_C2_TE (3U) //!< Bit position for UART_C2_TE.
bogdanm	82:6473597d706e	818	#define BM_UART_C2_TE (0x08U) //!< Bit mask for UART_C2_TE.
bogdanm	82:6473597d706e	819	#define BS_UART_C2_TE (1U) //!< Bit field size in bits for UART_C2_TE.
bogdanm	82:6473597d706e	820
bogdanm	82:6473597d706e	821	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	822	//! @brief Read current value of the UART_C2_TE field.
bogdanm	82:6473597d706e	823	#define BR_UART_C2_TE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE))
bogdanm	82:6473597d706e	824	#endif
bogdanm	82:6473597d706e	825
bogdanm	82:6473597d706e	826	//! @brief Format value for bitfield UART_C2_TE.
bogdanm	82:6473597d706e	827	#define BF_UART_C2_TE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TE), uint8_t) & BM_UART_C2_TE)
bogdanm	82:6473597d706e	828
bogdanm	82:6473597d706e	829	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	830	//! @brief Set the TE field to a new value.
bogdanm	82:6473597d706e	831	#define BW_UART_C2_TE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE) = (v))
bogdanm	82:6473597d706e	832	#endif
bogdanm	82:6473597d706e	833	//@}
bogdanm	82:6473597d706e	834
bogdanm	82:6473597d706e	835	/*!
bogdanm	82:6473597d706e	836	* @name Register UART_C2, field ILIE[4] (RW)
bogdanm	82:6473597d706e	837	*
bogdanm	82:6473597d706e	838	* Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA
bogdanm	82:6473597d706e	839	* transfer requests based on the state of C5[ILDMAS].
bogdanm	82:6473597d706e	840	*
bogdanm	82:6473597d706e	841	* Values:
bogdanm	82:6473597d706e	842	* - 0 - IDLE interrupt requests disabled. and DMA transfer
bogdanm	82:6473597d706e	843	* - 1 - IDLE interrupt requests enabled. or DMA transfer
bogdanm	82:6473597d706e	844	*/
bogdanm	82:6473597d706e	845	//@{
bogdanm	82:6473597d706e	846	#define BP_UART_C2_ILIE (4U) //!< Bit position for UART_C2_ILIE.
bogdanm	82:6473597d706e	847	#define BM_UART_C2_ILIE (0x10U) //!< Bit mask for UART_C2_ILIE.
bogdanm	82:6473597d706e	848	#define BS_UART_C2_ILIE (1U) //!< Bit field size in bits for UART_C2_ILIE.
bogdanm	82:6473597d706e	849
bogdanm	82:6473597d706e	850	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	851	//! @brief Read current value of the UART_C2_ILIE field.
bogdanm	82:6473597d706e	852	#define BR_UART_C2_ILIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE))
bogdanm	82:6473597d706e	853	#endif
bogdanm	82:6473597d706e	854
bogdanm	82:6473597d706e	855	//! @brief Format value for bitfield UART_C2_ILIE.
bogdanm	82:6473597d706e	856	#define BF_UART_C2_ILIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_ILIE), uint8_t) & BM_UART_C2_ILIE)
bogdanm	82:6473597d706e	857
bogdanm	82:6473597d706e	858	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	859	//! @brief Set the ILIE field to a new value.
bogdanm	82:6473597d706e	860	#define BW_UART_C2_ILIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE) = (v))
bogdanm	82:6473597d706e	861	#endif
bogdanm	82:6473597d706e	862	//@}
bogdanm	82:6473597d706e	863
bogdanm	82:6473597d706e	864	/*!
bogdanm	82:6473597d706e	865	* @name Register UART_C2, field RIE[5] (RW)
bogdanm	82:6473597d706e	866	*
bogdanm	82:6473597d706e	867	* Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
bogdanm	82:6473597d706e	868	* based on the state of C5[RDMAS].
bogdanm	82:6473597d706e	869	*
bogdanm	82:6473597d706e	870	* Values:
bogdanm	82:6473597d706e	871	* - 0 - RDRF interrupt and DMA transfer requests disabled.
bogdanm	82:6473597d706e	872	* - 1 - RDRF interrupt or DMA transfer requests enabled.
bogdanm	82:6473597d706e	873	*/
bogdanm	82:6473597d706e	874	//@{
bogdanm	82:6473597d706e	875	#define BP_UART_C2_RIE (5U) //!< Bit position for UART_C2_RIE.
bogdanm	82:6473597d706e	876	#define BM_UART_C2_RIE (0x20U) //!< Bit mask for UART_C2_RIE.
bogdanm	82:6473597d706e	877	#define BS_UART_C2_RIE (1U) //!< Bit field size in bits for UART_C2_RIE.
bogdanm	82:6473597d706e	878
bogdanm	82:6473597d706e	879	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	880	//! @brief Read current value of the UART_C2_RIE field.
bogdanm	82:6473597d706e	881	#define BR_UART_C2_RIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE))
bogdanm	82:6473597d706e	882	#endif
bogdanm	82:6473597d706e	883
bogdanm	82:6473597d706e	884	//! @brief Format value for bitfield UART_C2_RIE.
bogdanm	82:6473597d706e	885	#define BF_UART_C2_RIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RIE), uint8_t) & BM_UART_C2_RIE)
bogdanm	82:6473597d706e	886
bogdanm	82:6473597d706e	887	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	888	//! @brief Set the RIE field to a new value.
bogdanm	82:6473597d706e	889	#define BW_UART_C2_RIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE) = (v))
bogdanm	82:6473597d706e	890	#endif
bogdanm	82:6473597d706e	891	//@}
bogdanm	82:6473597d706e	892
bogdanm	82:6473597d706e	893	/*!
bogdanm	82:6473597d706e	894	* @name Register UART_C2, field TCIE[6] (RW)
bogdanm	82:6473597d706e	895	*
bogdanm	82:6473597d706e	896	* Enables the transmission complete flag, S1[TC], to generate interrupt
bogdanm	82:6473597d706e	897	* requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and
bogdanm	82:6473597d706e	898	* C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be
bogdanm	82:6473597d706e	899	* written unless servicing a DMA request.
bogdanm	82:6473597d706e	900	*
bogdanm	82:6473597d706e	901	* Values:
bogdanm	82:6473597d706e	902	* - 0 - TC interrupt and DMA transfer requests disabled.
bogdanm	82:6473597d706e	903	* - 1 - TC interrupt or DMA transfer requests enabled.
bogdanm	82:6473597d706e	904	*/
bogdanm	82:6473597d706e	905	//@{
bogdanm	82:6473597d706e	906	#define BP_UART_C2_TCIE (6U) //!< Bit position for UART_C2_TCIE.
bogdanm	82:6473597d706e	907	#define BM_UART_C2_TCIE (0x40U) //!< Bit mask for UART_C2_TCIE.
bogdanm	82:6473597d706e	908	#define BS_UART_C2_TCIE (1U) //!< Bit field size in bits for UART_C2_TCIE.
bogdanm	82:6473597d706e	909
bogdanm	82:6473597d706e	910	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	911	//! @brief Read current value of the UART_C2_TCIE field.
bogdanm	82:6473597d706e	912	#define BR_UART_C2_TCIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE))
bogdanm	82:6473597d706e	913	#endif
bogdanm	82:6473597d706e	914
bogdanm	82:6473597d706e	915	//! @brief Format value for bitfield UART_C2_TCIE.
bogdanm	82:6473597d706e	916	#define BF_UART_C2_TCIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TCIE), uint8_t) & BM_UART_C2_TCIE)
bogdanm	82:6473597d706e	917
bogdanm	82:6473597d706e	918	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	919	//! @brief Set the TCIE field to a new value.
bogdanm	82:6473597d706e	920	#define BW_UART_C2_TCIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE) = (v))
bogdanm	82:6473597d706e	921	#endif
bogdanm	82:6473597d706e	922	//@}
bogdanm	82:6473597d706e	923
bogdanm	82:6473597d706e	924	/*!
bogdanm	82:6473597d706e	925	* @name Register UART_C2, field TIE[7] (RW)
bogdanm	82:6473597d706e	926	*
bogdanm	82:6473597d706e	927	* Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
bogdanm	82:6473597d706e	928	* based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
bogdanm	82:6473597d706e	929	* must be cleared, and D[D] must not be written unless servicing a DMA request.
bogdanm	82:6473597d706e	930	*
bogdanm	82:6473597d706e	931	* Values:
bogdanm	82:6473597d706e	932	* - 0 - TDRE interrupt and DMA transfer requests disabled.
bogdanm	82:6473597d706e	933	* - 1 - TDRE interrupt or DMA transfer requests enabled.
bogdanm	82:6473597d706e	934	*/
bogdanm	82:6473597d706e	935	//@{
bogdanm	82:6473597d706e	936	#define BP_UART_C2_TIE (7U) //!< Bit position for UART_C2_TIE.
bogdanm	82:6473597d706e	937	#define BM_UART_C2_TIE (0x80U) //!< Bit mask for UART_C2_TIE.
bogdanm	82:6473597d706e	938	#define BS_UART_C2_TIE (1U) //!< Bit field size in bits for UART_C2_TIE.
bogdanm	82:6473597d706e	939
bogdanm	82:6473597d706e	940	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	941	//! @brief Read current value of the UART_C2_TIE field.
bogdanm	82:6473597d706e	942	#define BR_UART_C2_TIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE))
bogdanm	82:6473597d706e	943	#endif
bogdanm	82:6473597d706e	944
bogdanm	82:6473597d706e	945	//! @brief Format value for bitfield UART_C2_TIE.
bogdanm	82:6473597d706e	946	#define BF_UART_C2_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TIE), uint8_t) & BM_UART_C2_TIE)
bogdanm	82:6473597d706e	947
bogdanm	82:6473597d706e	948	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	949	//! @brief Set the TIE field to a new value.
bogdanm	82:6473597d706e	950	#define BW_UART_C2_TIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE) = (v))
bogdanm	82:6473597d706e	951	#endif
bogdanm	82:6473597d706e	952	//@}
bogdanm	82:6473597d706e	953
bogdanm	82:6473597d706e	954	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	955	// HW_UART_S1 - UART Status Register 1
bogdanm	82:6473597d706e	956	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	957
bogdanm	82:6473597d706e	958	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	959	/*!
bogdanm	82:6473597d706e	960	* @brief HW_UART_S1 - UART Status Register 1 (RO)
bogdanm	82:6473597d706e	961	*
bogdanm	82:6473597d706e	962	* Reset value: 0xC0U
bogdanm	82:6473597d706e	963	*
bogdanm	82:6473597d706e	964	* The S1 register provides inputs to the MCU for generation of UART interrupts
bogdanm	82:6473597d706e	965	* or DMA requests. This register can also be polled by the MCU to check the
bogdanm	82:6473597d706e	966	* status of its fields. To clear a flag, the status register should be read followed
bogdanm	82:6473597d706e	967	* by a read or write to D register, depending on the interrupt flag type. Other
bogdanm	82:6473597d706e	968	* instructions can be executed between the two steps as long the handling of
bogdanm	82:6473597d706e	969	* I/O is not compromised, but the order of operations is important for flag
bogdanm	82:6473597d706e	970	* clearing. When a flag is configured to trigger a DMA request, assertion of the
bogdanm	82:6473597d706e	971	* associated DMA done signal from the DMA controller clears the flag. If the
bogdanm	82:6473597d706e	972	* condition that results in the assertion of the flag, interrupt, or DMA request is not
bogdanm	82:6473597d706e	973	* resolved prior to clearing the flag, the flag, and interrupt/DMA request,
bogdanm	82:6473597d706e	974	* reasserts. For example, if the DMA or interrupt service routine fails to write
bogdanm	82:6473597d706e	975	* sufficient data to the transmit buffer to raise it above the watermark level, the
bogdanm	82:6473597d706e	976	* flag reasserts and generates another interrupt or DMA request. Reading an
bogdanm	82:6473597d706e	977	* empty data register to clear one of the flags of the S1 register causes the FIFO
bogdanm	82:6473597d706e	978	* pointers to become misaligned. A receive FIFO flush reinitializes the
bogdanm	82:6473597d706e	979	* pointers. A better way to prevent this situation is to always leave one byte in FIFO
bogdanm	82:6473597d706e	980	* and this byte will be read eventually in clearing the flag bit.
bogdanm	82:6473597d706e	981	*/
bogdanm	82:6473597d706e	982	typedef union _hw_uart_s1
bogdanm	82:6473597d706e	983	{
bogdanm	82:6473597d706e	984	uint8_t U;
bogdanm	82:6473597d706e	985	struct _hw_uart_s1_bitfields
bogdanm	82:6473597d706e	986	{
bogdanm	82:6473597d706e	987	uint8_t PF : 1; //!< [0] Parity Error Flag
bogdanm	82:6473597d706e	988	uint8_t FE : 1; //!< [1] Framing Error Flag
bogdanm	82:6473597d706e	989	uint8_t NF : 1; //!< [2] Noise Flag
bogdanm	82:6473597d706e	990	uint8_t OR : 1; //!< [3] Receiver Overrun Flag
bogdanm	82:6473597d706e	991	uint8_t IDLE : 1; //!< [4] Idle Line Flag
bogdanm	82:6473597d706e	992	uint8_t RDRF : 1; //!< [5] Receive Data Register Full Flag
bogdanm	82:6473597d706e	993	uint8_t TC : 1; //!< [6] Transmit Complete Flag
bogdanm	82:6473597d706e	994	uint8_t TDRE : 1; //!< [7] Transmit Data Register Empty Flag
bogdanm	82:6473597d706e	995	} B;
bogdanm	82:6473597d706e	996	} hw_uart_s1_t;
bogdanm	82:6473597d706e	997	#endif
bogdanm	82:6473597d706e	998
bogdanm	82:6473597d706e	999	/*!
bogdanm	82:6473597d706e	1000	* @name Constants and macros for entire UART_S1 register
bogdanm	82:6473597d706e	1001	*/
bogdanm	82:6473597d706e	1002	//@{
bogdanm	82:6473597d706e	1003	#define HW_UART_S1_ADDR(x) (REGS_UART_BASE(x) + 0x4U)
bogdanm	82:6473597d706e	1004
bogdanm	82:6473597d706e	1005	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1006	#define HW_UART_S1(x) ((__I hw_uart_s1_t ) HW_UART_S1_ADDR(x))
bogdanm	82:6473597d706e	1007	#define HW_UART_S1_RD(x) (HW_UART_S1(x).U)
bogdanm	82:6473597d706e	1008	#endif
bogdanm	82:6473597d706e	1009	//@}
bogdanm	82:6473597d706e	1010
bogdanm	82:6473597d706e	1011	/*
bogdanm	82:6473597d706e	1012	* Constants & macros for individual UART_S1 bitfields
bogdanm	82:6473597d706e	1013	*/
bogdanm	82:6473597d706e	1014
bogdanm	82:6473597d706e	1015	/*!
bogdanm	82:6473597d706e	1016	* @name Register UART_S1, field PF[0] (RO)
bogdanm	82:6473597d706e	1017	*
bogdanm	82:6473597d706e	1018	* PF is set when PE is set and the parity of the received data does not match
bogdanm	82:6473597d706e	1019	* its parity bit. The PF is not set in the case of an overrun condition. When PF
bogdanm	82:6473597d706e	1020	* is set, it indicates only that a dataword was received with parity error since
bogdanm	82:6473597d706e	1021	* the last time it was cleared. There is no guarantee that the first dataword
bogdanm	82:6473597d706e	1022	* read from the receive buffer has a parity error or that there is only one
bogdanm	82:6473597d706e	1023	* dataword in the buffer that was received with a parity error, unless the receive
bogdanm	82:6473597d706e	1024	* buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is
bogdanm	82:6473597d706e	1025	* disabled, Within the receive buffer structure the received dataword is tagged
bogdanm	82:6473597d706e	1026	* if it is received with a parity error. This information is available by reading
bogdanm	82:6473597d706e	1027	* the ED register prior to reading the D register.
bogdanm	82:6473597d706e	1028	*
bogdanm	82:6473597d706e	1029	* Values:
bogdanm	82:6473597d706e	1030	* - 0 - No parity error detected since the last time this flag was cleared. If
bogdanm	82:6473597d706e	1031	* the receive buffer has a depth greater than 1, then there may be data in
bogdanm	82:6473597d706e	1032	* the receive buffer what was received with a parity error.
bogdanm	82:6473597d706e	1033	* - 1 - At least one dataword was received with a parity error since the last
bogdanm	82:6473597d706e	1034	* time this flag was cleared.
bogdanm	82:6473597d706e	1035	*/
bogdanm	82:6473597d706e	1036	//@{
bogdanm	82:6473597d706e	1037	#define BP_UART_S1_PF (0U) //!< Bit position for UART_S1_PF.
bogdanm	82:6473597d706e	1038	#define BM_UART_S1_PF (0x01U) //!< Bit mask for UART_S1_PF.
bogdanm	82:6473597d706e	1039	#define BS_UART_S1_PF (1U) //!< Bit field size in bits for UART_S1_PF.
bogdanm	82:6473597d706e	1040
bogdanm	82:6473597d706e	1041	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1042	//! @brief Read current value of the UART_S1_PF field.
bogdanm	82:6473597d706e	1043	#define BR_UART_S1_PF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_PF))
bogdanm	82:6473597d706e	1044	#endif
bogdanm	82:6473597d706e	1045	//@}
bogdanm	82:6473597d706e	1046
bogdanm	82:6473597d706e	1047	/*!
bogdanm	82:6473597d706e	1048	* @name Register UART_S1, field FE[1] (RO)
bogdanm	82:6473597d706e	1049	*
bogdanm	82:6473597d706e	1050	* FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set,
bogdanm	82:6473597d706e	1051	* then FE will set when a logic 0 is accepted for either of the two stop bits.
bogdanm	82:6473597d706e	1052	* FE does not set in the case of an overrun or while the LIN break detect feature
bogdanm	82:6473597d706e	1053	* is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is
bogdanm	82:6473597d706e	1054	* cleared. To clear FE, read S1 with FE set and then read D. The last data in the
bogdanm	82:6473597d706e	1055	* receive buffer represents the data that was received with the frame error
bogdanm	82:6473597d706e	1056	* enabled. Framing errors are not supported when 7816E is set/enabled. However, if
bogdanm	82:6473597d706e	1057	* this flag is set, data is still not received in 7816 mode.
bogdanm	82:6473597d706e	1058	*
bogdanm	82:6473597d706e	1059	* Values:
bogdanm	82:6473597d706e	1060	* - 0 - No framing error detected.
bogdanm	82:6473597d706e	1061	* - 1 - Framing error.
bogdanm	82:6473597d706e	1062	*/
bogdanm	82:6473597d706e	1063	//@{
bogdanm	82:6473597d706e	1064	#define BP_UART_S1_FE (1U) //!< Bit position for UART_S1_FE.
bogdanm	82:6473597d706e	1065	#define BM_UART_S1_FE (0x02U) //!< Bit mask for UART_S1_FE.
bogdanm	82:6473597d706e	1066	#define BS_UART_S1_FE (1U) //!< Bit field size in bits for UART_S1_FE.
bogdanm	82:6473597d706e	1067
bogdanm	82:6473597d706e	1068	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1069	//! @brief Read current value of the UART_S1_FE field.
bogdanm	82:6473597d706e	1070	#define BR_UART_S1_FE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_FE))
bogdanm	82:6473597d706e	1071	#endif
bogdanm	82:6473597d706e	1072	//@}
bogdanm	82:6473597d706e	1073
bogdanm	82:6473597d706e	1074	/*!
bogdanm	82:6473597d706e	1075	* @name Register UART_S1, field NF[2] (RO)
bogdanm	82:6473597d706e	1076	*
bogdanm	82:6473597d706e	1077	* NF is set when the UART detects noise on the receiver input. NF does not
bogdanm	82:6473597d706e	1078	* become set in the case of an overrun or while the LIN break detect feature is
bogdanm	82:6473597d706e	1079	* enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has
bogdanm	82:6473597d706e	1080	* been received with noise since the last time it was cleared. There is no
bogdanm	82:6473597d706e	1081	* guarantee that the first dataword read from the receive buffer has noise or that there
bogdanm	82:6473597d706e	1082	* is only one dataword in the buffer that was received with noise unless the
bogdanm	82:6473597d706e	1083	* receive buffer has a depth of one. To clear NF, read S1 and then read D.
bogdanm	82:6473597d706e	1084	*
bogdanm	82:6473597d706e	1085	* Values:
bogdanm	82:6473597d706e	1086	* - 0 - No noise detected since the last time this flag was cleared. If the
bogdanm	82:6473597d706e	1087	* receive buffer has a depth greater than 1 then there may be data in the
bogdanm	82:6473597d706e	1088	* receiver buffer that was received with noise.
bogdanm	82:6473597d706e	1089	* - 1 - At least one dataword was received with noise detected since the last
bogdanm	82:6473597d706e	1090	* time the flag was cleared.
bogdanm	82:6473597d706e	1091	*/
bogdanm	82:6473597d706e	1092	//@{
bogdanm	82:6473597d706e	1093	#define BP_UART_S1_NF (2U) //!< Bit position for UART_S1_NF.
bogdanm	82:6473597d706e	1094	#define BM_UART_S1_NF (0x04U) //!< Bit mask for UART_S1_NF.
bogdanm	82:6473597d706e	1095	#define BS_UART_S1_NF (1U) //!< Bit field size in bits for UART_S1_NF.
bogdanm	82:6473597d706e	1096
bogdanm	82:6473597d706e	1097	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1098	//! @brief Read current value of the UART_S1_NF field.
bogdanm	82:6473597d706e	1099	#define BR_UART_S1_NF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_NF))
bogdanm	82:6473597d706e	1100	#endif
bogdanm	82:6473597d706e	1101	//@}
bogdanm	82:6473597d706e	1102
bogdanm	82:6473597d706e	1103	/*!
bogdanm	82:6473597d706e	1104	* @name Register UART_S1, field OR[3] (RO)
bogdanm	82:6473597d706e	1105	*
bogdanm	82:6473597d706e	1106	* OR is set when software fails to prevent the receive data register from
bogdanm	82:6473597d706e	1107	* overflowing with data. The OR bit is set immediately after the stop bit has been
bogdanm	82:6473597d706e	1108	* completely received for the dataword that overflows the buffer and all the other
bogdanm	82:6473597d706e	1109	* error flags (FE, NF, and PF) are prevented from setting. The data in the
bogdanm	82:6473597d706e	1110	* shift register is lost, but the data already in the UART data registers is not
bogdanm	82:6473597d706e	1111	* affected. If the OR flag is set, no data is stored in the data buffer even if
bogdanm	82:6473597d706e	1112	* sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
bogdanm	82:6473597d706e	1113	* flags are blocked from asserting, that is, transition from an inactive to an
bogdanm	82:6473597d706e	1114	* active state. To clear OR, read S1 when OR is set and then read D. See
bogdanm	82:6473597d706e	1115	* functional description for more details regarding the operation of the OR bit.If
bogdanm	82:6473597d706e	1116	* LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF]
bogdanm	82:6473597d706e	1117	* is not cleared before the next data character is received. In 7816 mode, it is
bogdanm	82:6473597d706e	1118	* possible to configure a NACK to be returned by programing C7816[ONACK].
bogdanm	82:6473597d706e	1119	*
bogdanm	82:6473597d706e	1120	* Values:
bogdanm	82:6473597d706e	1121	* - 0 - No overrun has occurred since the last time the flag was cleared.
bogdanm	82:6473597d706e	1122	* - 1 - Overrun has occurred or the overrun flag has not been cleared since the
bogdanm	82:6473597d706e	1123	* last overrun occured.
bogdanm	82:6473597d706e	1124	*/
bogdanm	82:6473597d706e	1125	//@{
bogdanm	82:6473597d706e	1126	#define BP_UART_S1_OR (3U) //!< Bit position for UART_S1_OR.
bogdanm	82:6473597d706e	1127	#define BM_UART_S1_OR (0x08U) //!< Bit mask for UART_S1_OR.
bogdanm	82:6473597d706e	1128	#define BS_UART_S1_OR (1U) //!< Bit field size in bits for UART_S1_OR.
bogdanm	82:6473597d706e	1129
bogdanm	82:6473597d706e	1130	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1131	//! @brief Read current value of the UART_S1_OR field.
bogdanm	82:6473597d706e	1132	#define BR_UART_S1_OR(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_OR))
bogdanm	82:6473597d706e	1133	#endif
bogdanm	82:6473597d706e	1134	//@}
bogdanm	82:6473597d706e	1135
bogdanm	82:6473597d706e	1136	/*!
bogdanm	82:6473597d706e	1137	* @name Register UART_S1, field IDLE[4] (RO)
bogdanm	82:6473597d706e	1138	*
bogdanm	82:6473597d706e	1139	* After the IDLE flag is cleared, a frame must be received (although not
bogdanm	82:6473597d706e	1140	* necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN
bogdanm	82:6473597d706e	1141	* break character must set the S2[LBKDIF] flag before an idle condition can set the
bogdanm	82:6473597d706e	1142	* IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
bogdanm	82:6473597d706e	1143	* IDLE is set when either of the following appear on the receiver input: 10
bogdanm	82:6473597d706e	1144	* consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10]
bogdanm	82:6473597d706e	1145	* = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle
bogdanm	82:6473597d706e	1146	* detection is not supported when 7816E is set/enabled and hence this flag is
bogdanm	82:6473597d706e	1147	* ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE
bogdanm	82:6473597d706e	1148	* flag if RWUID is set, else the IDLE flag does not become set.
bogdanm	82:6473597d706e	1149	*
bogdanm	82:6473597d706e	1150	* Values:
bogdanm	82:6473597d706e	1151	* - 0 - Receiver input is either active now or has never become active since
bogdanm	82:6473597d706e	1152	* the IDLE flag was last cleared.
bogdanm	82:6473597d706e	1153	* - 1 - Receiver input has become idle or the flag has not been cleared since
bogdanm	82:6473597d706e	1154	* it last asserted.
bogdanm	82:6473597d706e	1155	*/
bogdanm	82:6473597d706e	1156	//@{
bogdanm	82:6473597d706e	1157	#define BP_UART_S1_IDLE (4U) //!< Bit position for UART_S1_IDLE.
bogdanm	82:6473597d706e	1158	#define BM_UART_S1_IDLE (0x10U) //!< Bit mask for UART_S1_IDLE.
bogdanm	82:6473597d706e	1159	#define BS_UART_S1_IDLE (1U) //!< Bit field size in bits for UART_S1_IDLE.
bogdanm	82:6473597d706e	1160
bogdanm	82:6473597d706e	1161	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1162	//! @brief Read current value of the UART_S1_IDLE field.
bogdanm	82:6473597d706e	1163	#define BR_UART_S1_IDLE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_IDLE))
bogdanm	82:6473597d706e	1164	#endif
bogdanm	82:6473597d706e	1165	//@}
bogdanm	82:6473597d706e	1166
bogdanm	82:6473597d706e	1167	/*!
bogdanm	82:6473597d706e	1168	* @name Register UART_S1, field RDRF[5] (RO)
bogdanm	82:6473597d706e	1169	*
bogdanm	82:6473597d706e	1170	* RDRF is set when the number of datawords in the receive buffer is equal to or
bogdanm	82:6473597d706e	1171	* more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
bogdanm	82:6473597d706e	1172	* process of being received is not included in the count. To clear RDRF, read S1
bogdanm	82:6473597d706e	1173	* when RDRF is set and then read D. For more efficient interrupt and DMA
bogdanm	82:6473597d706e	1174	* operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
bogdanm	82:6473597d706e	1175	* Then read S1 and the final data value, resulting in the clearing of the RDRF
bogdanm	82:6473597d706e	1176	* flag. Even if RDRF is set, data will continue to be received until an overrun
bogdanm	82:6473597d706e	1177	* condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
bogdanm	82:6473597d706e	1178	* Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive
bogdanm	82:6473597d706e	1179	* buffer but over-write each other.
bogdanm	82:6473597d706e	1180	*
bogdanm	82:6473597d706e	1181	* Values:
bogdanm	82:6473597d706e	1182	* - 0 - The number of datawords in the receive buffer is less than the number
bogdanm	82:6473597d706e	1183	* indicated by RXWATER.
bogdanm	82:6473597d706e	1184	* - 1 - The number of datawords in the receive buffer is equal to or greater
bogdanm	82:6473597d706e	1185	* than the number indicated by RXWATER at some point in time since this flag
bogdanm	82:6473597d706e	1186	* was last cleared.
bogdanm	82:6473597d706e	1187	*/
bogdanm	82:6473597d706e	1188	//@{
bogdanm	82:6473597d706e	1189	#define BP_UART_S1_RDRF (5U) //!< Bit position for UART_S1_RDRF.
bogdanm	82:6473597d706e	1190	#define BM_UART_S1_RDRF (0x20U) //!< Bit mask for UART_S1_RDRF.
bogdanm	82:6473597d706e	1191	#define BS_UART_S1_RDRF (1U) //!< Bit field size in bits for UART_S1_RDRF.
bogdanm	82:6473597d706e	1192
bogdanm	82:6473597d706e	1193	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1194	//! @brief Read current value of the UART_S1_RDRF field.
bogdanm	82:6473597d706e	1195	#define BR_UART_S1_RDRF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_RDRF))
bogdanm	82:6473597d706e	1196	#endif
bogdanm	82:6473597d706e	1197	//@}
bogdanm	82:6473597d706e	1198
bogdanm	82:6473597d706e	1199	/*!
bogdanm	82:6473597d706e	1200	* @name Register UART_S1, field TC[6] (RO)
bogdanm	82:6473597d706e	1201	*
bogdanm	82:6473597d706e	1202	* TC is set when the transmit buffer is empty and no data, preamble, or break
bogdanm	82:6473597d706e	1203	* character is being transmitted. When TC is set, the transmit data output signal
bogdanm	82:6473597d706e	1204	* becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
bogdanm	82:6473597d706e	1205	* doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
bogdanm	82:6473597d706e	1206	* set after any NACK signal has been received, but prior to any corresponding
bogdanm	82:6473597d706e	1207	* guard times expiring. Writing to D to transmit new data. Queuing a preamble by
bogdanm	82:6473597d706e	1208	* clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
bogdanm	82:6473597d706e	1209	* in C2.
bogdanm	82:6473597d706e	1210	*
bogdanm	82:6473597d706e	1211	* Values:
bogdanm	82:6473597d706e	1212	* - 0 - Transmitter active (sending data, a preamble, or a break).
bogdanm	82:6473597d706e	1213	* - 1 - Transmitter idle (transmission activity complete).
bogdanm	82:6473597d706e	1214	*/
bogdanm	82:6473597d706e	1215	//@{
bogdanm	82:6473597d706e	1216	#define BP_UART_S1_TC (6U) //!< Bit position for UART_S1_TC.
bogdanm	82:6473597d706e	1217	#define BM_UART_S1_TC (0x40U) //!< Bit mask for UART_S1_TC.
bogdanm	82:6473597d706e	1218	#define BS_UART_S1_TC (1U) //!< Bit field size in bits for UART_S1_TC.
bogdanm	82:6473597d706e	1219
bogdanm	82:6473597d706e	1220	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1221	//! @brief Read current value of the UART_S1_TC field.
bogdanm	82:6473597d706e	1222	#define BR_UART_S1_TC(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TC))
bogdanm	82:6473597d706e	1223	#endif
bogdanm	82:6473597d706e	1224	//@}
bogdanm	82:6473597d706e	1225
bogdanm	82:6473597d706e	1226	/*!
bogdanm	82:6473597d706e	1227	* @name Register UART_S1, field TDRE[7] (RO)
bogdanm	82:6473597d706e	1228	*
bogdanm	82:6473597d706e	1229	* TDRE will set when the number of datawords in the transmit buffer (D and
bogdanm	82:6473597d706e	1230	* C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
bogdanm	82:6473597d706e	1231	* character that is in the process of being transmitted is not included in the count.
bogdanm	82:6473597d706e	1232	* To clear TDRE, read S1 when TDRE is set and then write to the UART data
bogdanm	82:6473597d706e	1233	* register (D). For more efficient interrupt servicing, all data except the final value
bogdanm	82:6473597d706e	1234	* to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
bogdanm	82:6473597d706e	1235	* before writing the final data value, resulting in the clearing of the TRDE
bogdanm	82:6473597d706e	1236	* flag. This is more efficient because the TDRE reasserts until the watermark has
bogdanm	82:6473597d706e	1237	* been exceeded. So, attempting to clear the TDRE with every write will be
bogdanm	82:6473597d706e	1238	* ineffective until sufficient data has been written.
bogdanm	82:6473597d706e	1239	*
bogdanm	82:6473597d706e	1240	* Values:
bogdanm	82:6473597d706e	1241	* - 0 - The amount of data in the transmit buffer is greater than the value
bogdanm	82:6473597d706e	1242	* indicated by TWFIFO[TXWATER].
bogdanm	82:6473597d706e	1243	* - 1 - The amount of data in the transmit buffer is less than or equal to the
bogdanm	82:6473597d706e	1244	* value indicated by TWFIFO[TXWATER] at some point in time since the flag
bogdanm	82:6473597d706e	1245	* has been cleared.
bogdanm	82:6473597d706e	1246	*/
bogdanm	82:6473597d706e	1247	//@{
bogdanm	82:6473597d706e	1248	#define BP_UART_S1_TDRE (7U) //!< Bit position for UART_S1_TDRE.
bogdanm	82:6473597d706e	1249	#define BM_UART_S1_TDRE (0x80U) //!< Bit mask for UART_S1_TDRE.
bogdanm	82:6473597d706e	1250	#define BS_UART_S1_TDRE (1U) //!< Bit field size in bits for UART_S1_TDRE.
bogdanm	82:6473597d706e	1251
bogdanm	82:6473597d706e	1252	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1253	//! @brief Read current value of the UART_S1_TDRE field.
bogdanm	82:6473597d706e	1254	#define BR_UART_S1_TDRE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TDRE))
bogdanm	82:6473597d706e	1255	#endif
bogdanm	82:6473597d706e	1256	//@}
bogdanm	82:6473597d706e	1257
bogdanm	82:6473597d706e	1258	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1259	// HW_UART_S2 - UART Status Register 2
bogdanm	82:6473597d706e	1260	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1261
bogdanm	82:6473597d706e	1262	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1263	/*!
bogdanm	82:6473597d706e	1264	* @brief HW_UART_S2 - UART Status Register 2 (RW)
bogdanm	82:6473597d706e	1265	*
bogdanm	82:6473597d706e	1266	* Reset value: 0x00U
bogdanm	82:6473597d706e	1267	*
bogdanm	82:6473597d706e	1268	* The S2 register provides inputs to the MCU for generation of UART interrupts
bogdanm	82:6473597d706e	1269	* or DMA requests. Also, this register can be polled by the MCU to check the
bogdanm	82:6473597d706e	1270	* status of these bits. This register can be read or written at any time, with the
bogdanm	82:6473597d706e	1271	* exception of the MSBF and RXINV bits, which should be changed by the user only
bogdanm	82:6473597d706e	1272	* between transmit and receive packets.
bogdanm	82:6473597d706e	1273	*/
bogdanm	82:6473597d706e	1274	typedef union _hw_uart_s2
bogdanm	82:6473597d706e	1275	{
bogdanm	82:6473597d706e	1276	uint8_t U;
bogdanm	82:6473597d706e	1277	struct _hw_uart_s2_bitfields
bogdanm	82:6473597d706e	1278	{
bogdanm	82:6473597d706e	1279	uint8_t RAF : 1; //!< [0] Receiver Active Flag
bogdanm	82:6473597d706e	1280	uint8_t LBKDE : 1; //!< [1] LIN Break Detection Enable
bogdanm	82:6473597d706e	1281	uint8_t BRK13 : 1; //!< [2] Break Transmit Character Length
bogdanm	82:6473597d706e	1282	uint8_t RWUID : 1; //!< [3] Receive Wakeup Idle Detect
bogdanm	82:6473597d706e	1283	uint8_t RXINV : 1; //!< [4] Receive Data Inversion
bogdanm	82:6473597d706e	1284	uint8_t MSBF : 1; //!< [5] Most Significant Bit First
bogdanm	82:6473597d706e	1285	uint8_t RXEDGIF : 1; //!< [6] RxD Pin Active Edge Interrupt Flag
bogdanm	82:6473597d706e	1286	uint8_t LBKDIF : 1; //!< [7] LIN Break Detect Interrupt Flag
bogdanm	82:6473597d706e	1287	} B;
bogdanm	82:6473597d706e	1288	} hw_uart_s2_t;
bogdanm	82:6473597d706e	1289	#endif
bogdanm	82:6473597d706e	1290
bogdanm	82:6473597d706e	1291	/*!
bogdanm	82:6473597d706e	1292	* @name Constants and macros for entire UART_S2 register
bogdanm	82:6473597d706e	1293	*/
bogdanm	82:6473597d706e	1294	//@{
bogdanm	82:6473597d706e	1295	#define HW_UART_S2_ADDR(x) (REGS_UART_BASE(x) + 0x5U)
bogdanm	82:6473597d706e	1296
bogdanm	82:6473597d706e	1297	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1298	#define HW_UART_S2(x) ((__IO hw_uart_s2_t ) HW_UART_S2_ADDR(x))
bogdanm	82:6473597d706e	1299	#define HW_UART_S2_RD(x) (HW_UART_S2(x).U)
bogdanm	82:6473597d706e	1300	#define HW_UART_S2_WR(x, v) (HW_UART_S2(x).U = (v))
bogdanm	82:6473597d706e	1301	#define HW_UART_S2_SET(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) \| (v)))
bogdanm	82:6473597d706e	1302	#define HW_UART_S2_CLR(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1303	#define HW_UART_S2_TOG(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1304	#endif
bogdanm	82:6473597d706e	1305	//@}
bogdanm	82:6473597d706e	1306
bogdanm	82:6473597d706e	1307	/*
bogdanm	82:6473597d706e	1308	* Constants & macros for individual UART_S2 bitfields
bogdanm	82:6473597d706e	1309	*/
bogdanm	82:6473597d706e	1310
bogdanm	82:6473597d706e	1311	/*!
bogdanm	82:6473597d706e	1312	* @name Register UART_S2, field RAF[0] (RO)
bogdanm	82:6473597d706e	1313	*
bogdanm	82:6473597d706e	1314	* RAF is set when the UART receiver detects a logic 0 during the RT1 time
bogdanm	82:6473597d706e	1315	* period of the start bit search. RAF is cleared when the receiver detects an idle
bogdanm	82:6473597d706e	1316	* character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
bogdanm	82:6473597d706e	1317	* enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
bogdanm	82:6473597d706e	1318	* 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
bogdanm	82:6473597d706e	1319	* to configure the guard time to 12. However, if a NACK is required to be
bogdanm	82:6473597d706e	1320	* transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
bogdanm	82:6473597d706e	1321	* inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
bogdanm	82:6473597d706e	1322	* prior to actually being inactive.
bogdanm	82:6473597d706e	1323	*
bogdanm	82:6473597d706e	1324	* Values:
bogdanm	82:6473597d706e	1325	* - 0 - UART receiver idle/inactive waiting for a start bit.
bogdanm	82:6473597d706e	1326	* - 1 - UART receiver active, RxD input not idle.
bogdanm	82:6473597d706e	1327	*/
bogdanm	82:6473597d706e	1328	//@{
bogdanm	82:6473597d706e	1329	#define BP_UART_S2_RAF (0U) //!< Bit position for UART_S2_RAF.
bogdanm	82:6473597d706e	1330	#define BM_UART_S2_RAF (0x01U) //!< Bit mask for UART_S2_RAF.
bogdanm	82:6473597d706e	1331	#define BS_UART_S2_RAF (1U) //!< Bit field size in bits for UART_S2_RAF.
bogdanm	82:6473597d706e	1332
bogdanm	82:6473597d706e	1333	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1334	//! @brief Read current value of the UART_S2_RAF field.
bogdanm	82:6473597d706e	1335	#define BR_UART_S2_RAF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RAF))
bogdanm	82:6473597d706e	1336	#endif
bogdanm	82:6473597d706e	1337	//@}
bogdanm	82:6473597d706e	1338
bogdanm	82:6473597d706e	1339	/*!
bogdanm	82:6473597d706e	1340	* @name Register UART_S2, field LBKDE[1] (RW)
bogdanm	82:6473597d706e	1341	*
bogdanm	82:6473597d706e	1342	* Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF],
bogdanm	82:6473597d706e	1343	* S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see .
bogdanm	82:6473597d706e	1344	* Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set.
bogdanm	82:6473597d706e	1345	*
bogdanm	82:6473597d706e	1346	* Values:
bogdanm	82:6473597d706e	1347	* - 0 - Break character detection is disabled.
bogdanm	82:6473597d706e	1348	* - 1 - Break character is detected at length of 11 bit times if C1[M] = 0 or
bogdanm	82:6473597d706e	1349	* 12 bits time if C1[M] = 1.
bogdanm	82:6473597d706e	1350	*/
bogdanm	82:6473597d706e	1351	//@{
bogdanm	82:6473597d706e	1352	#define BP_UART_S2_LBKDE (1U) //!< Bit position for UART_S2_LBKDE.
bogdanm	82:6473597d706e	1353	#define BM_UART_S2_LBKDE (0x02U) //!< Bit mask for UART_S2_LBKDE.
bogdanm	82:6473597d706e	1354	#define BS_UART_S2_LBKDE (1U) //!< Bit field size in bits for UART_S2_LBKDE.
bogdanm	82:6473597d706e	1355
bogdanm	82:6473597d706e	1356	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1357	//! @brief Read current value of the UART_S2_LBKDE field.
bogdanm	82:6473597d706e	1358	#define BR_UART_S2_LBKDE(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE))
bogdanm	82:6473597d706e	1359	#endif
bogdanm	82:6473597d706e	1360
bogdanm	82:6473597d706e	1361	//! @brief Format value for bitfield UART_S2_LBKDE.
bogdanm	82:6473597d706e	1362	#define BF_UART_S2_LBKDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_LBKDE), uint8_t) & BM_UART_S2_LBKDE)
bogdanm	82:6473597d706e	1363
bogdanm	82:6473597d706e	1364	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1365	//! @brief Set the LBKDE field to a new value.
bogdanm	82:6473597d706e	1366	#define BW_UART_S2_LBKDE(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE) = (v))
bogdanm	82:6473597d706e	1367	#endif
bogdanm	82:6473597d706e	1368	//@}
bogdanm	82:6473597d706e	1369
bogdanm	82:6473597d706e	1370	/*!
bogdanm	82:6473597d706e	1371	* @name Register UART_S2, field BRK13[2] (RW)
bogdanm	82:6473597d706e	1372	*
bogdanm	82:6473597d706e	1373	* Determines whether the transmit break character is 10, 11, or 12 bits long,
bogdanm	82:6473597d706e	1374	* or 13 or 14 bits long. See for the length of the break character for the
bogdanm	82:6473597d706e	1375	* different configurations. The detection of a framing error is not affected by this
bogdanm	82:6473597d706e	1376	* field. Transmitting break characters
bogdanm	82:6473597d706e	1377	*
bogdanm	82:6473597d706e	1378	* Values:
bogdanm	82:6473597d706e	1379	* - 0 - Break character is 10, 11, or 12 bits long.
bogdanm	82:6473597d706e	1380	* - 1 - Break character is 13 or 14 bits long.
bogdanm	82:6473597d706e	1381	*/
bogdanm	82:6473597d706e	1382	//@{
bogdanm	82:6473597d706e	1383	#define BP_UART_S2_BRK13 (2U) //!< Bit position for UART_S2_BRK13.
bogdanm	82:6473597d706e	1384	#define BM_UART_S2_BRK13 (0x04U) //!< Bit mask for UART_S2_BRK13.
bogdanm	82:6473597d706e	1385	#define BS_UART_S2_BRK13 (1U) //!< Bit field size in bits for UART_S2_BRK13.
bogdanm	82:6473597d706e	1386
bogdanm	82:6473597d706e	1387	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1388	//! @brief Read current value of the UART_S2_BRK13 field.
bogdanm	82:6473597d706e	1389	#define BR_UART_S2_BRK13(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13))
bogdanm	82:6473597d706e	1390	#endif
bogdanm	82:6473597d706e	1391
bogdanm	82:6473597d706e	1392	//! @brief Format value for bitfield UART_S2_BRK13.
bogdanm	82:6473597d706e	1393	#define BF_UART_S2_BRK13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_BRK13), uint8_t) & BM_UART_S2_BRK13)
bogdanm	82:6473597d706e	1394
bogdanm	82:6473597d706e	1395	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1396	//! @brief Set the BRK13 field to a new value.
bogdanm	82:6473597d706e	1397	#define BW_UART_S2_BRK13(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13) = (v))
bogdanm	82:6473597d706e	1398	#endif
bogdanm	82:6473597d706e	1399	//@}
bogdanm	82:6473597d706e	1400
bogdanm	82:6473597d706e	1401	/*!
bogdanm	82:6473597d706e	1402	* @name Register UART_S2, field RWUID[3] (RW)
bogdanm	82:6473597d706e	1403	*
bogdanm	82:6473597d706e	1404	* When RWU is set and WAKE is cleared, this field controls whether the idle
bogdanm	82:6473597d706e	1405	* character that wakes the receiver sets S1[IDLE]. This field must be cleared when
bogdanm	82:6473597d706e	1406	* C7816[ISO7816E] is set/enabled.
bogdanm	82:6473597d706e	1407	*
bogdanm	82:6473597d706e	1408	* Values:
bogdanm	82:6473597d706e	1409	* - 0 - S1[IDLE] is not set upon detection of an idle character.
bogdanm	82:6473597d706e	1410	* - 1 - S1[IDLE] is set upon detection of an idle character.
bogdanm	82:6473597d706e	1411	*/
bogdanm	82:6473597d706e	1412	//@{
bogdanm	82:6473597d706e	1413	#define BP_UART_S2_RWUID (3U) //!< Bit position for UART_S2_RWUID.
bogdanm	82:6473597d706e	1414	#define BM_UART_S2_RWUID (0x08U) //!< Bit mask for UART_S2_RWUID.
bogdanm	82:6473597d706e	1415	#define BS_UART_S2_RWUID (1U) //!< Bit field size in bits for UART_S2_RWUID.
bogdanm	82:6473597d706e	1416
bogdanm	82:6473597d706e	1417	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1418	//! @brief Read current value of the UART_S2_RWUID field.
bogdanm	82:6473597d706e	1419	#define BR_UART_S2_RWUID(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID))
bogdanm	82:6473597d706e	1420	#endif
bogdanm	82:6473597d706e	1421
bogdanm	82:6473597d706e	1422	//! @brief Format value for bitfield UART_S2_RWUID.
bogdanm	82:6473597d706e	1423	#define BF_UART_S2_RWUID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RWUID), uint8_t) & BM_UART_S2_RWUID)
bogdanm	82:6473597d706e	1424
bogdanm	82:6473597d706e	1425	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1426	//! @brief Set the RWUID field to a new value.
bogdanm	82:6473597d706e	1427	#define BW_UART_S2_RWUID(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID) = (v))
bogdanm	82:6473597d706e	1428	#endif
bogdanm	82:6473597d706e	1429	//@}
bogdanm	82:6473597d706e	1430
bogdanm	82:6473597d706e	1431	/*!
bogdanm	82:6473597d706e	1432	* @name Register UART_S2, field RXINV[4] (RW)
bogdanm	82:6473597d706e	1433	*
bogdanm	82:6473597d706e	1434	* Setting this field reverses the polarity of the received data input. In NRZ
bogdanm	82:6473597d706e	1435	* format, a one is represented by a mark and a zero is represented by a space for
bogdanm	82:6473597d706e	1436	* normal polarity, and the opposite for inverted polarity. In IrDA format, a
bogdanm	82:6473597d706e	1437	* zero is represented by short high pulse in the middle of a bit time remaining
bogdanm	82:6473597d706e	1438	* idle low for a one for normal polarity. A zero is represented by a short low
bogdanm	82:6473597d706e	1439	* pulse in the middle of a bit time remaining idle high for a one for inverted
bogdanm	82:6473597d706e	1440	* polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are
bogdanm	82:6473597d706e	1441	* enabled and an initial character is detected in T = 0 protocol mode. Setting
bogdanm	82:6473597d706e	1442	* RXINV inverts the RxD input for data bits, start and stop bits, break, and
bogdanm	82:6473597d706e	1443	* idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit
bogdanm	82:6473597d706e	1444	* are inverted.
bogdanm	82:6473597d706e	1445	*
bogdanm	82:6473597d706e	1446	* Values:
bogdanm	82:6473597d706e	1447	* - 0 - Receive data is not inverted.
bogdanm	82:6473597d706e	1448	* - 1 - Receive data is inverted.
bogdanm	82:6473597d706e	1449	*/
bogdanm	82:6473597d706e	1450	//@{
bogdanm	82:6473597d706e	1451	#define BP_UART_S2_RXINV (4U) //!< Bit position for UART_S2_RXINV.
bogdanm	82:6473597d706e	1452	#define BM_UART_S2_RXINV (0x10U) //!< Bit mask for UART_S2_RXINV.
bogdanm	82:6473597d706e	1453	#define BS_UART_S2_RXINV (1U) //!< Bit field size in bits for UART_S2_RXINV.
bogdanm	82:6473597d706e	1454
bogdanm	82:6473597d706e	1455	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1456	//! @brief Read current value of the UART_S2_RXINV field.
bogdanm	82:6473597d706e	1457	#define BR_UART_S2_RXINV(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV))
bogdanm	82:6473597d706e	1458	#endif
bogdanm	82:6473597d706e	1459
bogdanm	82:6473597d706e	1460	//! @brief Format value for bitfield UART_S2_RXINV.
bogdanm	82:6473597d706e	1461	#define BF_UART_S2_RXINV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RXINV), uint8_t) & BM_UART_S2_RXINV)
bogdanm	82:6473597d706e	1462
bogdanm	82:6473597d706e	1463	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1464	//! @brief Set the RXINV field to a new value.
bogdanm	82:6473597d706e	1465	#define BW_UART_S2_RXINV(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV) = (v))
bogdanm	82:6473597d706e	1466	#endif
bogdanm	82:6473597d706e	1467	//@}
bogdanm	82:6473597d706e	1468
bogdanm	82:6473597d706e	1469	/*!
bogdanm	82:6473597d706e	1470	* @name Register UART_S2, field MSBF[5] (RW)
bogdanm	82:6473597d706e	1471	*
bogdanm	82:6473597d706e	1472	* Setting this field reverses the order of the bits that are transmitted and
bogdanm	82:6473597d706e	1473	* received on the wire. This field does not affect the polarity of the bits, the
bogdanm	82:6473597d706e	1474	* location of the parity bit, or the location of the start or stop bits. This
bogdanm	82:6473597d706e	1475	* field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
bogdanm	82:6473597d706e	1476	* an initial character is detected in T = 0 protocol mode.
bogdanm	82:6473597d706e	1477	*
bogdanm	82:6473597d706e	1478	* Values:
bogdanm	82:6473597d706e	1479	* - 0 - LSB (bit0) is the first bit that is transmitted following the start
bogdanm	82:6473597d706e	1480	* bit. Further, the first bit received after the start bit is identified as
bogdanm	82:6473597d706e	1481	* bit0.
bogdanm	82:6473597d706e	1482	* - 1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted following
bogdanm	82:6473597d706e	1483	* the start bit, depending on the setting of C1[M] and C1[PE]. Further, the
bogdanm	82:6473597d706e	1484	* first bit received after the start bit is identified as bit8, bit7, or
bogdanm	82:6473597d706e	1485	* bit6, depending on the setting of C1[M] and C1[PE].
bogdanm	82:6473597d706e	1486	*/
bogdanm	82:6473597d706e	1487	//@{
bogdanm	82:6473597d706e	1488	#define BP_UART_S2_MSBF (5U) //!< Bit position for UART_S2_MSBF.
bogdanm	82:6473597d706e	1489	#define BM_UART_S2_MSBF (0x20U) //!< Bit mask for UART_S2_MSBF.
bogdanm	82:6473597d706e	1490	#define BS_UART_S2_MSBF (1U) //!< Bit field size in bits for UART_S2_MSBF.
bogdanm	82:6473597d706e	1491
bogdanm	82:6473597d706e	1492	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1493	//! @brief Read current value of the UART_S2_MSBF field.
bogdanm	82:6473597d706e	1494	#define BR_UART_S2_MSBF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF))
bogdanm	82:6473597d706e	1495	#endif
bogdanm	82:6473597d706e	1496
bogdanm	82:6473597d706e	1497	//! @brief Format value for bitfield UART_S2_MSBF.
bogdanm	82:6473597d706e	1498	#define BF_UART_S2_MSBF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_MSBF), uint8_t) & BM_UART_S2_MSBF)
bogdanm	82:6473597d706e	1499
bogdanm	82:6473597d706e	1500	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1501	//! @brief Set the MSBF field to a new value.
bogdanm	82:6473597d706e	1502	#define BW_UART_S2_MSBF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF) = (v))
bogdanm	82:6473597d706e	1503	#endif
bogdanm	82:6473597d706e	1504	//@}
bogdanm	82:6473597d706e	1505
bogdanm	82:6473597d706e	1506	/*!
bogdanm	82:6473597d706e	1507	* @name Register UART_S2, field RXEDGIF[6] (W1C)
bogdanm	82:6473597d706e	1508	*
bogdanm	82:6473597d706e	1509	* RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
bogdanm	82:6473597d706e	1510	* falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
bogdanm	82:6473597d706e	1511	* to it. See for additional details. RXEDGIF description The active edge is
bogdanm	82:6473597d706e	1512	* detected only in two wire mode and on receiving data coming from the RxD pin.
bogdanm	82:6473597d706e	1513	*
bogdanm	82:6473597d706e	1514	* Values:
bogdanm	82:6473597d706e	1515	* - 0 - No active edge on the receive pin has occurred.
bogdanm	82:6473597d706e	1516	* - 1 - An active edge on the receive pin has occurred.
bogdanm	82:6473597d706e	1517	*/
bogdanm	82:6473597d706e	1518	//@{
bogdanm	82:6473597d706e	1519	#define BP_UART_S2_RXEDGIF (6U) //!< Bit position for UART_S2_RXEDGIF.
bogdanm	82:6473597d706e	1520	#define BM_UART_S2_RXEDGIF (0x40U) //!< Bit mask for UART_S2_RXEDGIF.
bogdanm	82:6473597d706e	1521	#define BS_UART_S2_RXEDGIF (1U) //!< Bit field size in bits for UART_S2_RXEDGIF.
bogdanm	82:6473597d706e	1522
bogdanm	82:6473597d706e	1523	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1524	//! @brief Read current value of the UART_S2_RXEDGIF field.
bogdanm	82:6473597d706e	1525	#define BR_UART_S2_RXEDGIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF))
bogdanm	82:6473597d706e	1526	#endif
bogdanm	82:6473597d706e	1527
bogdanm	82:6473597d706e	1528	//! @brief Format value for bitfield UART_S2_RXEDGIF.
bogdanm	82:6473597d706e	1529	#define BF_UART_S2_RXEDGIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RXEDGIF), uint8_t) & BM_UART_S2_RXEDGIF)
bogdanm	82:6473597d706e	1530
bogdanm	82:6473597d706e	1531	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1532	//! @brief Set the RXEDGIF field to a new value.
bogdanm	82:6473597d706e	1533	#define BW_UART_S2_RXEDGIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF) = (v))
bogdanm	82:6473597d706e	1534	#endif
bogdanm	82:6473597d706e	1535	//@}
bogdanm	82:6473597d706e	1536
bogdanm	82:6473597d706e	1537	/*!
bogdanm	82:6473597d706e	1538	* @name Register UART_S2, field LBKDIF[7] (W1C)
bogdanm	82:6473597d706e	1539	*
bogdanm	82:6473597d706e	1540	* LBKDIF is set when LBKDE is set and a LIN break character is detected on the
bogdanm	82:6473597d706e	1541	* receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M]
bogdanm	82:6473597d706e	1542	* = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the
bogdanm	82:6473597d706e	1543	* last LIN break character. LBKDIF is cleared by writing a 1 to it.
bogdanm	82:6473597d706e	1544	*
bogdanm	82:6473597d706e	1545	* Values:
bogdanm	82:6473597d706e	1546	* - 0 - No LIN break character detected.
bogdanm	82:6473597d706e	1547	* - 1 - LIN break character detected.
bogdanm	82:6473597d706e	1548	*/
bogdanm	82:6473597d706e	1549	//@{
bogdanm	82:6473597d706e	1550	#define BP_UART_S2_LBKDIF (7U) //!< Bit position for UART_S2_LBKDIF.
bogdanm	82:6473597d706e	1551	#define BM_UART_S2_LBKDIF (0x80U) //!< Bit mask for UART_S2_LBKDIF.
bogdanm	82:6473597d706e	1552	#define BS_UART_S2_LBKDIF (1U) //!< Bit field size in bits for UART_S2_LBKDIF.
bogdanm	82:6473597d706e	1553
bogdanm	82:6473597d706e	1554	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1555	//! @brief Read current value of the UART_S2_LBKDIF field.
bogdanm	82:6473597d706e	1556	#define BR_UART_S2_LBKDIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF))
bogdanm	82:6473597d706e	1557	#endif
bogdanm	82:6473597d706e	1558
bogdanm	82:6473597d706e	1559	//! @brief Format value for bitfield UART_S2_LBKDIF.
bogdanm	82:6473597d706e	1560	#define BF_UART_S2_LBKDIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_LBKDIF), uint8_t) & BM_UART_S2_LBKDIF)
bogdanm	82:6473597d706e	1561
bogdanm	82:6473597d706e	1562	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1563	//! @brief Set the LBKDIF field to a new value.
bogdanm	82:6473597d706e	1564	#define BW_UART_S2_LBKDIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF) = (v))
bogdanm	82:6473597d706e	1565	#endif
bogdanm	82:6473597d706e	1566	//@}
bogdanm	82:6473597d706e	1567
bogdanm	82:6473597d706e	1568	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1569	// HW_UART_C3 - UART Control Register 3
bogdanm	82:6473597d706e	1570	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1571
bogdanm	82:6473597d706e	1572	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1573	/*!
bogdanm	82:6473597d706e	1574	* @brief HW_UART_C3 - UART Control Register 3 (RW)
bogdanm	82:6473597d706e	1575	*
bogdanm	82:6473597d706e	1576	* Reset value: 0x00U
bogdanm	82:6473597d706e	1577	*
bogdanm	82:6473597d706e	1578	* Writing R8 does not have any effect. TXDIR and TXINV can be changed only
bogdanm	82:6473597d706e	1579	* between transmit and receive packets.
bogdanm	82:6473597d706e	1580	*/
bogdanm	82:6473597d706e	1581	typedef union _hw_uart_c3
bogdanm	82:6473597d706e	1582	{
bogdanm	82:6473597d706e	1583	uint8_t U;
bogdanm	82:6473597d706e	1584	struct _hw_uart_c3_bitfields
bogdanm	82:6473597d706e	1585	{
bogdanm	82:6473597d706e	1586	uint8_t PEIE : 1; //!< [0] Parity Error Interrupt Enable
bogdanm	82:6473597d706e	1587	uint8_t FEIE : 1; //!< [1] Framing Error Interrupt Enable
bogdanm	82:6473597d706e	1588	uint8_t NEIE : 1; //!< [2] Noise Error Interrupt Enable
bogdanm	82:6473597d706e	1589	uint8_t ORIE : 1; //!< [3] Overrun Error Interrupt Enable
bogdanm	82:6473597d706e	1590	uint8_t TXINV : 1; //!< [4] Transmit Data Inversion.
bogdanm	82:6473597d706e	1591	uint8_t TXDIR : 1; //!< [5] Transmitter Pin Data Direction in
bogdanm	82:6473597d706e	1592	//! Single-Wire mode
bogdanm	82:6473597d706e	1593	uint8_t T8 : 1; //!< [6] Transmit Bit 8
bogdanm	82:6473597d706e	1594	uint8_t R8 : 1; //!< [7] Received Bit 8
bogdanm	82:6473597d706e	1595	} B;
bogdanm	82:6473597d706e	1596	} hw_uart_c3_t;
bogdanm	82:6473597d706e	1597	#endif
bogdanm	82:6473597d706e	1598
bogdanm	82:6473597d706e	1599	/*!
bogdanm	82:6473597d706e	1600	* @name Constants and macros for entire UART_C3 register
bogdanm	82:6473597d706e	1601	*/
bogdanm	82:6473597d706e	1602	//@{
bogdanm	82:6473597d706e	1603	#define HW_UART_C3_ADDR(x) (REGS_UART_BASE(x) + 0x6U)
bogdanm	82:6473597d706e	1604
bogdanm	82:6473597d706e	1605	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1606	#define HW_UART_C3(x) ((__IO hw_uart_c3_t ) HW_UART_C3_ADDR(x))
bogdanm	82:6473597d706e	1607	#define HW_UART_C3_RD(x) (HW_UART_C3(x).U)
bogdanm	82:6473597d706e	1608	#define HW_UART_C3_WR(x, v) (HW_UART_C3(x).U = (v))
bogdanm	82:6473597d706e	1609	#define HW_UART_C3_SET(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) \| (v)))
bogdanm	82:6473597d706e	1610	#define HW_UART_C3_CLR(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1611	#define HW_UART_C3_TOG(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1612	#endif
bogdanm	82:6473597d706e	1613	//@}
bogdanm	82:6473597d706e	1614
bogdanm	82:6473597d706e	1615	/*
bogdanm	82:6473597d706e	1616	* Constants & macros for individual UART_C3 bitfields
bogdanm	82:6473597d706e	1617	*/
bogdanm	82:6473597d706e	1618
bogdanm	82:6473597d706e	1619	/*!
bogdanm	82:6473597d706e	1620	* @name Register UART_C3, field PEIE[0] (RW)
bogdanm	82:6473597d706e	1621	*
bogdanm	82:6473597d706e	1622	* Enables the parity error flag, S1[PF], to generate interrupt requests.
bogdanm	82:6473597d706e	1623	*
bogdanm	82:6473597d706e	1624	* Values:
bogdanm	82:6473597d706e	1625	* - 0 - PF interrupt requests are disabled.
bogdanm	82:6473597d706e	1626	* - 1 - PF interrupt requests are enabled.
bogdanm	82:6473597d706e	1627	*/
bogdanm	82:6473597d706e	1628	//@{
bogdanm	82:6473597d706e	1629	#define BP_UART_C3_PEIE (0U) //!< Bit position for UART_C3_PEIE.
bogdanm	82:6473597d706e	1630	#define BM_UART_C3_PEIE (0x01U) //!< Bit mask for UART_C3_PEIE.
bogdanm	82:6473597d706e	1631	#define BS_UART_C3_PEIE (1U) //!< Bit field size in bits for UART_C3_PEIE.
bogdanm	82:6473597d706e	1632
bogdanm	82:6473597d706e	1633	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1634	//! @brief Read current value of the UART_C3_PEIE field.
bogdanm	82:6473597d706e	1635	#define BR_UART_C3_PEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE))
bogdanm	82:6473597d706e	1636	#endif
bogdanm	82:6473597d706e	1637
bogdanm	82:6473597d706e	1638	//! @brief Format value for bitfield UART_C3_PEIE.
bogdanm	82:6473597d706e	1639	#define BF_UART_C3_PEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_PEIE), uint8_t) & BM_UART_C3_PEIE)
bogdanm	82:6473597d706e	1640
bogdanm	82:6473597d706e	1641	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1642	//! @brief Set the PEIE field to a new value.
bogdanm	82:6473597d706e	1643	#define BW_UART_C3_PEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE) = (v))
bogdanm	82:6473597d706e	1644	#endif
bogdanm	82:6473597d706e	1645	//@}
bogdanm	82:6473597d706e	1646
bogdanm	82:6473597d706e	1647	/*!
bogdanm	82:6473597d706e	1648	* @name Register UART_C3, field FEIE[1] (RW)
bogdanm	82:6473597d706e	1649	*
bogdanm	82:6473597d706e	1650	* Enables the framing error flag, S1[FE], to generate interrupt requests.
bogdanm	82:6473597d706e	1651	*
bogdanm	82:6473597d706e	1652	* Values:
bogdanm	82:6473597d706e	1653	* - 0 - FE interrupt requests are disabled.
bogdanm	82:6473597d706e	1654	* - 1 - FE interrupt requests are enabled.
bogdanm	82:6473597d706e	1655	*/
bogdanm	82:6473597d706e	1656	//@{
bogdanm	82:6473597d706e	1657	#define BP_UART_C3_FEIE (1U) //!< Bit position for UART_C3_FEIE.
bogdanm	82:6473597d706e	1658	#define BM_UART_C3_FEIE (0x02U) //!< Bit mask for UART_C3_FEIE.
bogdanm	82:6473597d706e	1659	#define BS_UART_C3_FEIE (1U) //!< Bit field size in bits for UART_C3_FEIE.
bogdanm	82:6473597d706e	1660
bogdanm	82:6473597d706e	1661	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1662	//! @brief Read current value of the UART_C3_FEIE field.
bogdanm	82:6473597d706e	1663	#define BR_UART_C3_FEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE))
bogdanm	82:6473597d706e	1664	#endif
bogdanm	82:6473597d706e	1665
bogdanm	82:6473597d706e	1666	//! @brief Format value for bitfield UART_C3_FEIE.
bogdanm	82:6473597d706e	1667	#define BF_UART_C3_FEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_FEIE), uint8_t) & BM_UART_C3_FEIE)
bogdanm	82:6473597d706e	1668
bogdanm	82:6473597d706e	1669	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1670	//! @brief Set the FEIE field to a new value.
bogdanm	82:6473597d706e	1671	#define BW_UART_C3_FEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE) = (v))
bogdanm	82:6473597d706e	1672	#endif
bogdanm	82:6473597d706e	1673	//@}
bogdanm	82:6473597d706e	1674
bogdanm	82:6473597d706e	1675	/*!
bogdanm	82:6473597d706e	1676	* @name Register UART_C3, field NEIE[2] (RW)
bogdanm	82:6473597d706e	1677	*
bogdanm	82:6473597d706e	1678	* Enables the noise flag, S1[NF], to generate interrupt requests.
bogdanm	82:6473597d706e	1679	*
bogdanm	82:6473597d706e	1680	* Values:
bogdanm	82:6473597d706e	1681	* - 0 - NF interrupt requests are disabled.
bogdanm	82:6473597d706e	1682	* - 1 - NF interrupt requests are enabled.
bogdanm	82:6473597d706e	1683	*/
bogdanm	82:6473597d706e	1684	//@{
bogdanm	82:6473597d706e	1685	#define BP_UART_C3_NEIE (2U) //!< Bit position for UART_C3_NEIE.
bogdanm	82:6473597d706e	1686	#define BM_UART_C3_NEIE (0x04U) //!< Bit mask for UART_C3_NEIE.
bogdanm	82:6473597d706e	1687	#define BS_UART_C3_NEIE (1U) //!< Bit field size in bits for UART_C3_NEIE.
bogdanm	82:6473597d706e	1688
bogdanm	82:6473597d706e	1689	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1690	//! @brief Read current value of the UART_C3_NEIE field.
bogdanm	82:6473597d706e	1691	#define BR_UART_C3_NEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE))
bogdanm	82:6473597d706e	1692	#endif
bogdanm	82:6473597d706e	1693
bogdanm	82:6473597d706e	1694	//! @brief Format value for bitfield UART_C3_NEIE.
bogdanm	82:6473597d706e	1695	#define BF_UART_C3_NEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_NEIE), uint8_t) & BM_UART_C3_NEIE)
bogdanm	82:6473597d706e	1696
bogdanm	82:6473597d706e	1697	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1698	//! @brief Set the NEIE field to a new value.
bogdanm	82:6473597d706e	1699	#define BW_UART_C3_NEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE) = (v))
bogdanm	82:6473597d706e	1700	#endif
bogdanm	82:6473597d706e	1701	//@}
bogdanm	82:6473597d706e	1702
bogdanm	82:6473597d706e	1703	/*!
bogdanm	82:6473597d706e	1704	* @name Register UART_C3, field ORIE[3] (RW)
bogdanm	82:6473597d706e	1705	*
bogdanm	82:6473597d706e	1706	* Enables the overrun error flag, S1[OR], to generate interrupt requests.
bogdanm	82:6473597d706e	1707	*
bogdanm	82:6473597d706e	1708	* Values:
bogdanm	82:6473597d706e	1709	* - 0 - OR interrupts are disabled.
bogdanm	82:6473597d706e	1710	* - 1 - OR interrupt requests are enabled.
bogdanm	82:6473597d706e	1711	*/
bogdanm	82:6473597d706e	1712	//@{
bogdanm	82:6473597d706e	1713	#define BP_UART_C3_ORIE (3U) //!< Bit position for UART_C3_ORIE.
bogdanm	82:6473597d706e	1714	#define BM_UART_C3_ORIE (0x08U) //!< Bit mask for UART_C3_ORIE.
bogdanm	82:6473597d706e	1715	#define BS_UART_C3_ORIE (1U) //!< Bit field size in bits for UART_C3_ORIE.
bogdanm	82:6473597d706e	1716
bogdanm	82:6473597d706e	1717	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1718	//! @brief Read current value of the UART_C3_ORIE field.
bogdanm	82:6473597d706e	1719	#define BR_UART_C3_ORIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE))
bogdanm	82:6473597d706e	1720	#endif
bogdanm	82:6473597d706e	1721
bogdanm	82:6473597d706e	1722	//! @brief Format value for bitfield UART_C3_ORIE.
bogdanm	82:6473597d706e	1723	#define BF_UART_C3_ORIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_ORIE), uint8_t) & BM_UART_C3_ORIE)
bogdanm	82:6473597d706e	1724
bogdanm	82:6473597d706e	1725	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1726	//! @brief Set the ORIE field to a new value.
bogdanm	82:6473597d706e	1727	#define BW_UART_C3_ORIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE) = (v))
bogdanm	82:6473597d706e	1728	#endif
bogdanm	82:6473597d706e	1729	//@}
bogdanm	82:6473597d706e	1730
bogdanm	82:6473597d706e	1731	/*!
bogdanm	82:6473597d706e	1732	* @name Register UART_C3, field TXINV[4] (RW)
bogdanm	82:6473597d706e	1733	*
bogdanm	82:6473597d706e	1734	* Setting this field reverses the polarity of the transmitted data output. In
bogdanm	82:6473597d706e	1735	* NRZ format, a one is represented by a mark and a zero is represented by a space
bogdanm	82:6473597d706e	1736	* for normal polarity, and the opposite for inverted polarity. In IrDA format,
bogdanm	82:6473597d706e	1737	* a zero is represented by short high pulse in the middle of a bit time
bogdanm	82:6473597d706e	1738	* remaining idle low for a one for normal polarity, and a zero is represented by short
bogdanm	82:6473597d706e	1739	* low pulse in the middle of a bit time remaining idle high for a one for
bogdanm	82:6473597d706e	1740	* inverted polarity. This field is automatically set when C7816[INIT] and
bogdanm	82:6473597d706e	1741	* C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
bogdanm	82:6473597d706e	1742	* Setting TXINV inverts all transmitted values, including idle, break, start, and
bogdanm	82:6473597d706e	1743	* stop bits. In loop mode, if TXINV is set, the receiver gets the transmit
bogdanm	82:6473597d706e	1744	* inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only
bogdanm	82:6473597d706e	1745	* the transmitted data bits and parity bit are inverted.
bogdanm	82:6473597d706e	1746	*
bogdanm	82:6473597d706e	1747	* Values:
bogdanm	82:6473597d706e	1748	* - 0 - Transmit data is not inverted.
bogdanm	82:6473597d706e	1749	* - 1 - Transmit data is inverted.
bogdanm	82:6473597d706e	1750	*/
bogdanm	82:6473597d706e	1751	//@{
bogdanm	82:6473597d706e	1752	#define BP_UART_C3_TXINV (4U) //!< Bit position for UART_C3_TXINV.
bogdanm	82:6473597d706e	1753	#define BM_UART_C3_TXINV (0x10U) //!< Bit mask for UART_C3_TXINV.
bogdanm	82:6473597d706e	1754	#define BS_UART_C3_TXINV (1U) //!< Bit field size in bits for UART_C3_TXINV.
bogdanm	82:6473597d706e	1755
bogdanm	82:6473597d706e	1756	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1757	//! @brief Read current value of the UART_C3_TXINV field.
bogdanm	82:6473597d706e	1758	#define BR_UART_C3_TXINV(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV))
bogdanm	82:6473597d706e	1759	#endif
bogdanm	82:6473597d706e	1760
bogdanm	82:6473597d706e	1761	//! @brief Format value for bitfield UART_C3_TXINV.
bogdanm	82:6473597d706e	1762	#define BF_UART_C3_TXINV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_TXINV), uint8_t) & BM_UART_C3_TXINV)
bogdanm	82:6473597d706e	1763
bogdanm	82:6473597d706e	1764	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1765	//! @brief Set the TXINV field to a new value.
bogdanm	82:6473597d706e	1766	#define BW_UART_C3_TXINV(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV) = (v))
bogdanm	82:6473597d706e	1767	#endif
bogdanm	82:6473597d706e	1768	//@}
bogdanm	82:6473597d706e	1769
bogdanm	82:6473597d706e	1770	/*!
bogdanm	82:6473597d706e	1771	* @name Register UART_C3, field TXDIR[5] (RW)
bogdanm	82:6473597d706e	1772	*
bogdanm	82:6473597d706e	1773	* Determines whether the TXD pin is used as an input or output in the
bogdanm	82:6473597d706e	1774	* single-wire mode of operation. This field is relevant only to the single wire mode.
bogdanm	82:6473597d706e	1775	* When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
bogdanm	82:6473597d706e	1776	* automatically cleared after the requested block is transmitted. This condition is
bogdanm	82:6473597d706e	1777	* detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
bogdanm	82:6473597d706e	1778	* Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
bogdanm	82:6473597d706e	1779	* being transmitted, the hardware automatically overrides this field as needed. In
bogdanm	82:6473597d706e	1780	* this situation, TXDIR does not reflect the temporary state associated with
bogdanm	82:6473597d706e	1781	* the NACK.
bogdanm	82:6473597d706e	1782	*
bogdanm	82:6473597d706e	1783	* Values:
bogdanm	82:6473597d706e	1784	* - 0 - TXD pin is an input in single wire mode.
bogdanm	82:6473597d706e	1785	* - 1 - TXD pin is an output in single wire mode.
bogdanm	82:6473597d706e	1786	*/
bogdanm	82:6473597d706e	1787	//@{
bogdanm	82:6473597d706e	1788	#define BP_UART_C3_TXDIR (5U) //!< Bit position for UART_C3_TXDIR.
bogdanm	82:6473597d706e	1789	#define BM_UART_C3_TXDIR (0x20U) //!< Bit mask for UART_C3_TXDIR.
bogdanm	82:6473597d706e	1790	#define BS_UART_C3_TXDIR (1U) //!< Bit field size in bits for UART_C3_TXDIR.
bogdanm	82:6473597d706e	1791
bogdanm	82:6473597d706e	1792	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1793	//! @brief Read current value of the UART_C3_TXDIR field.
bogdanm	82:6473597d706e	1794	#define BR_UART_C3_TXDIR(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR))
bogdanm	82:6473597d706e	1795	#endif
bogdanm	82:6473597d706e	1796
bogdanm	82:6473597d706e	1797	//! @brief Format value for bitfield UART_C3_TXDIR.
bogdanm	82:6473597d706e	1798	#define BF_UART_C3_TXDIR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_TXDIR), uint8_t) & BM_UART_C3_TXDIR)
bogdanm	82:6473597d706e	1799
bogdanm	82:6473597d706e	1800	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1801	//! @brief Set the TXDIR field to a new value.
bogdanm	82:6473597d706e	1802	#define BW_UART_C3_TXDIR(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR) = (v))
bogdanm	82:6473597d706e	1803	#endif
bogdanm	82:6473597d706e	1804	//@}
bogdanm	82:6473597d706e	1805
bogdanm	82:6473597d706e	1806	/*!
bogdanm	82:6473597d706e	1807	* @name Register UART_C3, field T8[6] (RW)
bogdanm	82:6473597d706e	1808	*
bogdanm	82:6473597d706e	1809	* T8 is the ninth data bit transmitted when the UART is configured for 9-bit
bogdanm	82:6473597d706e	1810	* data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
bogdanm	82:6473597d706e	1811	* same as in the previous transmission, T8 does not have to be rewritten. The same
bogdanm	82:6473597d706e	1812	* value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
bogdanm	82:6473597d706e	1813	* write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
bogdanm	82:6473597d706e	1814	* the remaining data.
bogdanm	82:6473597d706e	1815	*/
bogdanm	82:6473597d706e	1816	//@{
bogdanm	82:6473597d706e	1817	#define BP_UART_C3_T8 (6U) //!< Bit position for UART_C3_T8.
bogdanm	82:6473597d706e	1818	#define BM_UART_C3_T8 (0x40U) //!< Bit mask for UART_C3_T8.
bogdanm	82:6473597d706e	1819	#define BS_UART_C3_T8 (1U) //!< Bit field size in bits for UART_C3_T8.
bogdanm	82:6473597d706e	1820
bogdanm	82:6473597d706e	1821	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1822	//! @brief Read current value of the UART_C3_T8 field.
bogdanm	82:6473597d706e	1823	#define BR_UART_C3_T8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8))
bogdanm	82:6473597d706e	1824	#endif
bogdanm	82:6473597d706e	1825
bogdanm	82:6473597d706e	1826	//! @brief Format value for bitfield UART_C3_T8.
bogdanm	82:6473597d706e	1827	#define BF_UART_C3_T8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_T8), uint8_t) & BM_UART_C3_T8)
bogdanm	82:6473597d706e	1828
bogdanm	82:6473597d706e	1829	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1830	//! @brief Set the T8 field to a new value.
bogdanm	82:6473597d706e	1831	#define BW_UART_C3_T8(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8) = (v))
bogdanm	82:6473597d706e	1832	#endif
bogdanm	82:6473597d706e	1833	//@}
bogdanm	82:6473597d706e	1834
bogdanm	82:6473597d706e	1835	/*!
bogdanm	82:6473597d706e	1836	* @name Register UART_C3, field R8[7] (RO)
bogdanm	82:6473597d706e	1837	*
bogdanm	82:6473597d706e	1838	* R8 is the ninth data bit received when the UART is configured for 9-bit data
bogdanm	82:6473597d706e	1839	* format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
bogdanm	82:6473597d706e	1840	* current data value in the UARTx_D register. To read the 9th bit, read the
bogdanm	82:6473597d706e	1841	* value of UARTx_C3[R8], then read the UARTx_D register.
bogdanm	82:6473597d706e	1842	*/
bogdanm	82:6473597d706e	1843	//@{
bogdanm	82:6473597d706e	1844	#define BP_UART_C3_R8 (7U) //!< Bit position for UART_C3_R8.
bogdanm	82:6473597d706e	1845	#define BM_UART_C3_R8 (0x80U) //!< Bit mask for UART_C3_R8.
bogdanm	82:6473597d706e	1846	#define BS_UART_C3_R8 (1U) //!< Bit field size in bits for UART_C3_R8.
bogdanm	82:6473597d706e	1847
bogdanm	82:6473597d706e	1848	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1849	//! @brief Read current value of the UART_C3_R8 field.
bogdanm	82:6473597d706e	1850	#define BR_UART_C3_R8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_R8))
bogdanm	82:6473597d706e	1851	#endif
bogdanm	82:6473597d706e	1852	//@}
bogdanm	82:6473597d706e	1853
bogdanm	82:6473597d706e	1854	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1855	// HW_UART_D - UART Data Register
bogdanm	82:6473597d706e	1856	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1857
bogdanm	82:6473597d706e	1858	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1859	/*!
bogdanm	82:6473597d706e	1860	* @brief HW_UART_D - UART Data Register (RW)
bogdanm	82:6473597d706e	1861	*
bogdanm	82:6473597d706e	1862	* Reset value: 0x00U
bogdanm	82:6473597d706e	1863	*
bogdanm	82:6473597d706e	1864	* This register is actually two separate registers. Reads return the contents
bogdanm	82:6473597d706e	1865	* of the read-only receive data register and writes go to the write-only transmit
bogdanm	82:6473597d706e	1866	* data register. In 8-bit or 9-bit data format, only UART data register (D)
bogdanm	82:6473597d706e	1867	* needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
bogdanm	82:6473597d706e	1868	* less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
bogdanm	82:6473597d706e	1869	* register, only if the ninth bit of data needs to be captured. Similarly, the
bogdanm	82:6473597d706e	1870	* ED register needs to be read, prior to the D register, only if the additional
bogdanm	82:6473597d706e	1871	* flag data for the dataword needs to be captured. In the normal 8-bit mode (M
bogdanm	82:6473597d706e	1872	* bit cleared) if the parity is enabled, you get seven data bits and one parity
bogdanm	82:6473597d706e	1873	* bit. That one parity bit is loaded into the D register. So, for the data bits,
bogdanm	82:6473597d706e	1874	* mask off the parity bit from the value you read out of this register. When
bogdanm	82:6473597d706e	1875	* transmitting in 9-bit data format and using 8-bit write instructions, write first
bogdanm	82:6473597d706e	1876	* to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
bogdanm	82:6473597d706e	1877	* C3[T8] stores the data in a temporary register. If D register is written first,
bogdanm	82:6473597d706e	1878	* and then the new data on data bus is stored in D, the temporary value written by
bogdanm	82:6473597d706e	1879	* the last write to C3[T8] gets stored in the C3[T8] register.
bogdanm	82:6473597d706e	1880	*/
bogdanm	82:6473597d706e	1881	typedef union _hw_uart_d
bogdanm	82:6473597d706e	1882	{
bogdanm	82:6473597d706e	1883	uint8_t U;
bogdanm	82:6473597d706e	1884	struct _hw_uart_d_bitfields
bogdanm	82:6473597d706e	1885	{
bogdanm	82:6473597d706e	1886	uint8_t RT : 8; //!< [7:0]
bogdanm	82:6473597d706e	1887	} B;
bogdanm	82:6473597d706e	1888	} hw_uart_d_t;
bogdanm	82:6473597d706e	1889	#endif
bogdanm	82:6473597d706e	1890
bogdanm	82:6473597d706e	1891	/*!
bogdanm	82:6473597d706e	1892	* @name Constants and macros for entire UART_D register
bogdanm	82:6473597d706e	1893	*/
bogdanm	82:6473597d706e	1894	//@{
bogdanm	82:6473597d706e	1895	#define HW_UART_D_ADDR(x) (REGS_UART_BASE(x) + 0x7U)
bogdanm	82:6473597d706e	1896
bogdanm	82:6473597d706e	1897	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1898	#define HW_UART_D(x) ((__IO hw_uart_d_t ) HW_UART_D_ADDR(x))
bogdanm	82:6473597d706e	1899	#define HW_UART_D_RD(x) (HW_UART_D(x).U)
bogdanm	82:6473597d706e	1900	#define HW_UART_D_WR(x, v) (HW_UART_D(x).U = (v))
bogdanm	82:6473597d706e	1901	#define HW_UART_D_SET(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) \| (v)))
bogdanm	82:6473597d706e	1902	#define HW_UART_D_CLR(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1903	#define HW_UART_D_TOG(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1904	#endif
bogdanm	82:6473597d706e	1905	//@}
bogdanm	82:6473597d706e	1906
bogdanm	82:6473597d706e	1907	/*
bogdanm	82:6473597d706e	1908	* Constants & macros for individual UART_D bitfields
bogdanm	82:6473597d706e	1909	*/
bogdanm	82:6473597d706e	1910
bogdanm	82:6473597d706e	1911	/*!
bogdanm	82:6473597d706e	1912	* @name Register UART_D, field RT[7:0] (RW)
bogdanm	82:6473597d706e	1913	*
bogdanm	82:6473597d706e	1914	* Reads return the contents of the read-only receive data register and writes
bogdanm	82:6473597d706e	1915	* go to the write-only transmit data register.
bogdanm	82:6473597d706e	1916	*/
bogdanm	82:6473597d706e	1917	//@{
bogdanm	82:6473597d706e	1918	#define BP_UART_D_RT (0U) //!< Bit position for UART_D_RT.
bogdanm	82:6473597d706e	1919	#define BM_UART_D_RT (0xFFU) //!< Bit mask for UART_D_RT.
bogdanm	82:6473597d706e	1920	#define BS_UART_D_RT (8U) //!< Bit field size in bits for UART_D_RT.
bogdanm	82:6473597d706e	1921
bogdanm	82:6473597d706e	1922	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1923	//! @brief Read current value of the UART_D_RT field.
bogdanm	82:6473597d706e	1924	#define BR_UART_D_RT(x) (HW_UART_D(x).U)
bogdanm	82:6473597d706e	1925	#endif
bogdanm	82:6473597d706e	1926
bogdanm	82:6473597d706e	1927	//! @brief Format value for bitfield UART_D_RT.
bogdanm	82:6473597d706e	1928	#define BF_UART_D_RT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_D_RT), uint8_t) & BM_UART_D_RT)
bogdanm	82:6473597d706e	1929
bogdanm	82:6473597d706e	1930	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1931	//! @brief Set the RT field to a new value.
bogdanm	82:6473597d706e	1932	#define BW_UART_D_RT(x, v) (HW_UART_D_WR(x, v))
bogdanm	82:6473597d706e	1933	#endif
bogdanm	82:6473597d706e	1934	//@}
bogdanm	82:6473597d706e	1935
bogdanm	82:6473597d706e	1936	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1937	// HW_UART_MA1 - UART Match Address Registers 1
bogdanm	82:6473597d706e	1938	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1939
bogdanm	82:6473597d706e	1940	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1941	/*!
bogdanm	82:6473597d706e	1942	* @brief HW_UART_MA1 - UART Match Address Registers 1 (RW)
bogdanm	82:6473597d706e	1943	*
bogdanm	82:6473597d706e	1944	* Reset value: 0x00U
bogdanm	82:6473597d706e	1945	*
bogdanm	82:6473597d706e	1946	* The MA1 and MA2 registers are compared to input data addresses when the most
bogdanm	82:6473597d706e	1947	* significant bit is set and the associated C4[MAEN] field is set. If a match
bogdanm	82:6473597d706e	1948	* occurs, the following data is transferred to the data register. If a match
bogdanm	82:6473597d706e	1949	* fails, the following data is discarded. These registers can be read and written at
bogdanm	82:6473597d706e	1950	* anytime.
bogdanm	82:6473597d706e	1951	*/
bogdanm	82:6473597d706e	1952	typedef union _hw_uart_ma1
bogdanm	82:6473597d706e	1953	{
bogdanm	82:6473597d706e	1954	uint8_t U;
bogdanm	82:6473597d706e	1955	struct _hw_uart_ma1_bitfields
bogdanm	82:6473597d706e	1956	{
bogdanm	82:6473597d706e	1957	uint8_t MA : 8; //!< [7:0] Match Address
bogdanm	82:6473597d706e	1958	} B;
bogdanm	82:6473597d706e	1959	} hw_uart_ma1_t;
bogdanm	82:6473597d706e	1960	#endif
bogdanm	82:6473597d706e	1961
bogdanm	82:6473597d706e	1962	/*!
bogdanm	82:6473597d706e	1963	* @name Constants and macros for entire UART_MA1 register
bogdanm	82:6473597d706e	1964	*/
bogdanm	82:6473597d706e	1965	//@{
bogdanm	82:6473597d706e	1966	#define HW_UART_MA1_ADDR(x) (REGS_UART_BASE(x) + 0x8U)
bogdanm	82:6473597d706e	1967
bogdanm	82:6473597d706e	1968	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1969	#define HW_UART_MA1(x) ((__IO hw_uart_ma1_t ) HW_UART_MA1_ADDR(x))
bogdanm	82:6473597d706e	1970	#define HW_UART_MA1_RD(x) (HW_UART_MA1(x).U)
bogdanm	82:6473597d706e	1971	#define HW_UART_MA1_WR(x, v) (HW_UART_MA1(x).U = (v))
bogdanm	82:6473597d706e	1972	#define HW_UART_MA1_SET(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) \| (v)))
bogdanm	82:6473597d706e	1973	#define HW_UART_MA1_CLR(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1974	#define HW_UART_MA1_TOG(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1975	#endif
bogdanm	82:6473597d706e	1976	//@}
bogdanm	82:6473597d706e	1977
bogdanm	82:6473597d706e	1978	/*
bogdanm	82:6473597d706e	1979	* Constants & macros for individual UART_MA1 bitfields
bogdanm	82:6473597d706e	1980	*/
bogdanm	82:6473597d706e	1981
bogdanm	82:6473597d706e	1982	/*!
bogdanm	82:6473597d706e	1983	* @name Register UART_MA1, field MA[7:0] (RW)
bogdanm	82:6473597d706e	1984	*/
bogdanm	82:6473597d706e	1985	//@{
bogdanm	82:6473597d706e	1986	#define BP_UART_MA1_MA (0U) //!< Bit position for UART_MA1_MA.
bogdanm	82:6473597d706e	1987	#define BM_UART_MA1_MA (0xFFU) //!< Bit mask for UART_MA1_MA.
bogdanm	82:6473597d706e	1988	#define BS_UART_MA1_MA (8U) //!< Bit field size in bits for UART_MA1_MA.
bogdanm	82:6473597d706e	1989
bogdanm	82:6473597d706e	1990	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1991	//! @brief Read current value of the UART_MA1_MA field.
bogdanm	82:6473597d706e	1992	#define BR_UART_MA1_MA(x) (HW_UART_MA1(x).U)
bogdanm	82:6473597d706e	1993	#endif
bogdanm	82:6473597d706e	1994
bogdanm	82:6473597d706e	1995	//! @brief Format value for bitfield UART_MA1_MA.
bogdanm	82:6473597d706e	1996	#define BF_UART_MA1_MA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MA1_MA), uint8_t) & BM_UART_MA1_MA)
bogdanm	82:6473597d706e	1997
bogdanm	82:6473597d706e	1998	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1999	//! @brief Set the MA field to a new value.
bogdanm	82:6473597d706e	2000	#define BW_UART_MA1_MA(x, v) (HW_UART_MA1_WR(x, v))
bogdanm	82:6473597d706e	2001	#endif
bogdanm	82:6473597d706e	2002	//@}
bogdanm	82:6473597d706e	2003
bogdanm	82:6473597d706e	2004	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2005	// HW_UART_MA2 - UART Match Address Registers 2
bogdanm	82:6473597d706e	2006	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2007
bogdanm	82:6473597d706e	2008	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2009	/*!
bogdanm	82:6473597d706e	2010	* @brief HW_UART_MA2 - UART Match Address Registers 2 (RW)
bogdanm	82:6473597d706e	2011	*
bogdanm	82:6473597d706e	2012	* Reset value: 0x00U
bogdanm	82:6473597d706e	2013	*
bogdanm	82:6473597d706e	2014	* These registers can be read and written at anytime. The MA1 and MA2 registers
bogdanm	82:6473597d706e	2015	* are compared to input data addresses when the most significant bit is set and
bogdanm	82:6473597d706e	2016	* the associated C4[MAEN] field is set. If a match occurs, the following data
bogdanm	82:6473597d706e	2017	* is transferred to the data register. If a match fails, the following data is
bogdanm	82:6473597d706e	2018	* discarded.
bogdanm	82:6473597d706e	2019	*/
bogdanm	82:6473597d706e	2020	typedef union _hw_uart_ma2
bogdanm	82:6473597d706e	2021	{
bogdanm	82:6473597d706e	2022	uint8_t U;
bogdanm	82:6473597d706e	2023	struct _hw_uart_ma2_bitfields
bogdanm	82:6473597d706e	2024	{
bogdanm	82:6473597d706e	2025	uint8_t MA : 8; //!< [7:0] Match Address
bogdanm	82:6473597d706e	2026	} B;
bogdanm	82:6473597d706e	2027	} hw_uart_ma2_t;
bogdanm	82:6473597d706e	2028	#endif
bogdanm	82:6473597d706e	2029
bogdanm	82:6473597d706e	2030	/*!
bogdanm	82:6473597d706e	2031	* @name Constants and macros for entire UART_MA2 register
bogdanm	82:6473597d706e	2032	*/
bogdanm	82:6473597d706e	2033	//@{
bogdanm	82:6473597d706e	2034	#define HW_UART_MA2_ADDR(x) (REGS_UART_BASE(x) + 0x9U)
bogdanm	82:6473597d706e	2035
bogdanm	82:6473597d706e	2036	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2037	#define HW_UART_MA2(x) ((__IO hw_uart_ma2_t ) HW_UART_MA2_ADDR(x))
bogdanm	82:6473597d706e	2038	#define HW_UART_MA2_RD(x) (HW_UART_MA2(x).U)
bogdanm	82:6473597d706e	2039	#define HW_UART_MA2_WR(x, v) (HW_UART_MA2(x).U = (v))
bogdanm	82:6473597d706e	2040	#define HW_UART_MA2_SET(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) \| (v)))
bogdanm	82:6473597d706e	2041	#define HW_UART_MA2_CLR(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2042	#define HW_UART_MA2_TOG(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2043	#endif
bogdanm	82:6473597d706e	2044	//@}
bogdanm	82:6473597d706e	2045
bogdanm	82:6473597d706e	2046	/*
bogdanm	82:6473597d706e	2047	* Constants & macros for individual UART_MA2 bitfields
bogdanm	82:6473597d706e	2048	*/
bogdanm	82:6473597d706e	2049
bogdanm	82:6473597d706e	2050	/*!
bogdanm	82:6473597d706e	2051	* @name Register UART_MA2, field MA[7:0] (RW)
bogdanm	82:6473597d706e	2052	*/
bogdanm	82:6473597d706e	2053	//@{
bogdanm	82:6473597d706e	2054	#define BP_UART_MA2_MA (0U) //!< Bit position for UART_MA2_MA.
bogdanm	82:6473597d706e	2055	#define BM_UART_MA2_MA (0xFFU) //!< Bit mask for UART_MA2_MA.
bogdanm	82:6473597d706e	2056	#define BS_UART_MA2_MA (8U) //!< Bit field size in bits for UART_MA2_MA.
bogdanm	82:6473597d706e	2057
bogdanm	82:6473597d706e	2058	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2059	//! @brief Read current value of the UART_MA2_MA field.
bogdanm	82:6473597d706e	2060	#define BR_UART_MA2_MA(x) (HW_UART_MA2(x).U)
bogdanm	82:6473597d706e	2061	#endif
bogdanm	82:6473597d706e	2062
bogdanm	82:6473597d706e	2063	//! @brief Format value for bitfield UART_MA2_MA.
bogdanm	82:6473597d706e	2064	#define BF_UART_MA2_MA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MA2_MA), uint8_t) & BM_UART_MA2_MA)
bogdanm	82:6473597d706e	2065
bogdanm	82:6473597d706e	2066	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2067	//! @brief Set the MA field to a new value.
bogdanm	82:6473597d706e	2068	#define BW_UART_MA2_MA(x, v) (HW_UART_MA2_WR(x, v))
bogdanm	82:6473597d706e	2069	#endif
bogdanm	82:6473597d706e	2070	//@}
bogdanm	82:6473597d706e	2071
bogdanm	82:6473597d706e	2072	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2073	// HW_UART_C4 - UART Control Register 4
bogdanm	82:6473597d706e	2074	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2075
bogdanm	82:6473597d706e	2076	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2077	/*!
bogdanm	82:6473597d706e	2078	* @brief HW_UART_C4 - UART Control Register 4 (RW)
bogdanm	82:6473597d706e	2079	*
bogdanm	82:6473597d706e	2080	* Reset value: 0x00U
bogdanm	82:6473597d706e	2081	*/
bogdanm	82:6473597d706e	2082	typedef union _hw_uart_c4
bogdanm	82:6473597d706e	2083	{
bogdanm	82:6473597d706e	2084	uint8_t U;
bogdanm	82:6473597d706e	2085	struct _hw_uart_c4_bitfields
bogdanm	82:6473597d706e	2086	{
bogdanm	82:6473597d706e	2087	uint8_t BRFA : 5; //!< [4:0] Baud Rate Fine Adjust
bogdanm	82:6473597d706e	2088	uint8_t M10 : 1; //!< [5] 10-bit Mode select
bogdanm	82:6473597d706e	2089	uint8_t MAEN2 : 1; //!< [6] Match Address Mode Enable 2
bogdanm	82:6473597d706e	2090	uint8_t MAEN1 : 1; //!< [7] Match Address Mode Enable 1
bogdanm	82:6473597d706e	2091	} B;
bogdanm	82:6473597d706e	2092	} hw_uart_c4_t;
bogdanm	82:6473597d706e	2093	#endif
bogdanm	82:6473597d706e	2094
bogdanm	82:6473597d706e	2095	/*!
bogdanm	82:6473597d706e	2096	* @name Constants and macros for entire UART_C4 register
bogdanm	82:6473597d706e	2097	*/
bogdanm	82:6473597d706e	2098	//@{
bogdanm	82:6473597d706e	2099	#define HW_UART_C4_ADDR(x) (REGS_UART_BASE(x) + 0xAU)
bogdanm	82:6473597d706e	2100
bogdanm	82:6473597d706e	2101	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2102	#define HW_UART_C4(x) ((__IO hw_uart_c4_t ) HW_UART_C4_ADDR(x))
bogdanm	82:6473597d706e	2103	#define HW_UART_C4_RD(x) (HW_UART_C4(x).U)
bogdanm	82:6473597d706e	2104	#define HW_UART_C4_WR(x, v) (HW_UART_C4(x).U = (v))
bogdanm	82:6473597d706e	2105	#define HW_UART_C4_SET(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) \| (v)))
bogdanm	82:6473597d706e	2106	#define HW_UART_C4_CLR(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2107	#define HW_UART_C4_TOG(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2108	#endif
bogdanm	82:6473597d706e	2109	//@}
bogdanm	82:6473597d706e	2110
bogdanm	82:6473597d706e	2111	/*
bogdanm	82:6473597d706e	2112	* Constants & macros for individual UART_C4 bitfields
bogdanm	82:6473597d706e	2113	*/
bogdanm	82:6473597d706e	2114
bogdanm	82:6473597d706e	2115	/*!
bogdanm	82:6473597d706e	2116	* @name Register UART_C4, field BRFA[4:0] (RW)
bogdanm	82:6473597d706e	2117	*
bogdanm	82:6473597d706e	2118	* This bit field is used to add more timing resolution to the average baud
bogdanm	82:6473597d706e	2119	* frequency, in increments of 1/32. See Baud rate generation for more information.
bogdanm	82:6473597d706e	2120	*/
bogdanm	82:6473597d706e	2121	//@{
bogdanm	82:6473597d706e	2122	#define BP_UART_C4_BRFA (0U) //!< Bit position for UART_C4_BRFA.
bogdanm	82:6473597d706e	2123	#define BM_UART_C4_BRFA (0x1FU) //!< Bit mask for UART_C4_BRFA.
bogdanm	82:6473597d706e	2124	#define BS_UART_C4_BRFA (5U) //!< Bit field size in bits for UART_C4_BRFA.
bogdanm	82:6473597d706e	2125
bogdanm	82:6473597d706e	2126	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2127	//! @brief Read current value of the UART_C4_BRFA field.
bogdanm	82:6473597d706e	2128	#define BR_UART_C4_BRFA(x) (HW_UART_C4(x).B.BRFA)
bogdanm	82:6473597d706e	2129	#endif
bogdanm	82:6473597d706e	2130
bogdanm	82:6473597d706e	2131	//! @brief Format value for bitfield UART_C4_BRFA.
bogdanm	82:6473597d706e	2132	#define BF_UART_C4_BRFA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_BRFA), uint8_t) & BM_UART_C4_BRFA)
bogdanm	82:6473597d706e	2133
bogdanm	82:6473597d706e	2134	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2135	//! @brief Set the BRFA field to a new value.
bogdanm	82:6473597d706e	2136	#define BW_UART_C4_BRFA(x, v) (HW_UART_C4_WR(x, (HW_UART_C4_RD(x) & ~BM_UART_C4_BRFA) \| BF_UART_C4_BRFA(v)))
bogdanm	82:6473597d706e	2137	#endif
bogdanm	82:6473597d706e	2138	//@}
bogdanm	82:6473597d706e	2139
bogdanm	82:6473597d706e	2140	/*!
bogdanm	82:6473597d706e	2141	* @name Register UART_C4, field M10[5] (RW)
bogdanm	82:6473597d706e	2142	*
bogdanm	82:6473597d706e	2143	* Causes a tenth, non-memory mapped bit to be part of the serial transmission.
bogdanm	82:6473597d706e	2144	* This tenth bit is generated and interpreted as a parity bit. The M10 field
bogdanm	82:6473597d706e	2145	* does not affect the LIN send or detect break behavior. If M10 is set, then both
bogdanm	82:6473597d706e	2146	* C1[M] and C1[PE] must also be set. This field must be cleared when
bogdanm	82:6473597d706e	2147	* C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
bogdanm	82:6473597d706e	2148	*
bogdanm	82:6473597d706e	2149	* Values:
bogdanm	82:6473597d706e	2150	* - 0 - The parity bit is the ninth bit in the serial transmission.
bogdanm	82:6473597d706e	2151	* - 1 - The parity bit is the tenth bit in the serial transmission.
bogdanm	82:6473597d706e	2152	*/
bogdanm	82:6473597d706e	2153	//@{
bogdanm	82:6473597d706e	2154	#define BP_UART_C4_M10 (5U) //!< Bit position for UART_C4_M10.
bogdanm	82:6473597d706e	2155	#define BM_UART_C4_M10 (0x20U) //!< Bit mask for UART_C4_M10.
bogdanm	82:6473597d706e	2156	#define BS_UART_C4_M10 (1U) //!< Bit field size in bits for UART_C4_M10.
bogdanm	82:6473597d706e	2157
bogdanm	82:6473597d706e	2158	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2159	//! @brief Read current value of the UART_C4_M10 field.
bogdanm	82:6473597d706e	2160	#define BR_UART_C4_M10(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10))
bogdanm	82:6473597d706e	2161	#endif
bogdanm	82:6473597d706e	2162
bogdanm	82:6473597d706e	2163	//! @brief Format value for bitfield UART_C4_M10.
bogdanm	82:6473597d706e	2164	#define BF_UART_C4_M10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_M10), uint8_t) & BM_UART_C4_M10)
bogdanm	82:6473597d706e	2165
bogdanm	82:6473597d706e	2166	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2167	//! @brief Set the M10 field to a new value.
bogdanm	82:6473597d706e	2168	#define BW_UART_C4_M10(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10) = (v))
bogdanm	82:6473597d706e	2169	#endif
bogdanm	82:6473597d706e	2170	//@}
bogdanm	82:6473597d706e	2171
bogdanm	82:6473597d706e	2172	/*!
bogdanm	82:6473597d706e	2173	* @name Register UART_C4, field MAEN2[6] (RW)
bogdanm	82:6473597d706e	2174	*
bogdanm	82:6473597d706e	2175	* See Match address operation for more information.
bogdanm	82:6473597d706e	2176	*
bogdanm	82:6473597d706e	2177	* Values:
bogdanm	82:6473597d706e	2178	* - 0 - All data received is transferred to the data buffer if MAEN1 is cleared.
bogdanm	82:6473597d706e	2179	* - 1 - All data received with the most significant bit cleared, is discarded.
bogdanm	82:6473597d706e	2180	* All data received with the most significant bit set, is compared with
bogdanm	82:6473597d706e	2181	* contents of MA2 register. If no match occurs, the data is discarded. If a
bogdanm	82:6473597d706e	2182	* match occurs, data is transferred to the data buffer. This field must be
bogdanm	82:6473597d706e	2183	* cleared when C7816[ISO7816E] is set/enabled.
bogdanm	82:6473597d706e	2184	*/
bogdanm	82:6473597d706e	2185	//@{
bogdanm	82:6473597d706e	2186	#define BP_UART_C4_MAEN2 (6U) //!< Bit position for UART_C4_MAEN2.
bogdanm	82:6473597d706e	2187	#define BM_UART_C4_MAEN2 (0x40U) //!< Bit mask for UART_C4_MAEN2.
bogdanm	82:6473597d706e	2188	#define BS_UART_C4_MAEN2 (1U) //!< Bit field size in bits for UART_C4_MAEN2.
bogdanm	82:6473597d706e	2189
bogdanm	82:6473597d706e	2190	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2191	//! @brief Read current value of the UART_C4_MAEN2 field.
bogdanm	82:6473597d706e	2192	#define BR_UART_C4_MAEN2(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2))
bogdanm	82:6473597d706e	2193	#endif
bogdanm	82:6473597d706e	2194
bogdanm	82:6473597d706e	2195	//! @brief Format value for bitfield UART_C4_MAEN2.
bogdanm	82:6473597d706e	2196	#define BF_UART_C4_MAEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_MAEN2), uint8_t) & BM_UART_C4_MAEN2)
bogdanm	82:6473597d706e	2197
bogdanm	82:6473597d706e	2198	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2199	//! @brief Set the MAEN2 field to a new value.
bogdanm	82:6473597d706e	2200	#define BW_UART_C4_MAEN2(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2) = (v))
bogdanm	82:6473597d706e	2201	#endif
bogdanm	82:6473597d706e	2202	//@}
bogdanm	82:6473597d706e	2203
bogdanm	82:6473597d706e	2204	/*!
bogdanm	82:6473597d706e	2205	* @name Register UART_C4, field MAEN1[7] (RW)
bogdanm	82:6473597d706e	2206	*
bogdanm	82:6473597d706e	2207	* See Match address operation for more information.
bogdanm	82:6473597d706e	2208	*
bogdanm	82:6473597d706e	2209	* Values:
bogdanm	82:6473597d706e	2210	* - 0 - All data received is transferred to the data buffer if MAEN2 is cleared.
bogdanm	82:6473597d706e	2211	* - 1 - All data received with the most significant bit cleared, is discarded.
bogdanm	82:6473597d706e	2212	* All data received with the most significant bit set, is compared with
bogdanm	82:6473597d706e	2213	* contents of MA1 register. If no match occurs, the data is discarded. If match
bogdanm	82:6473597d706e	2214	* occurs, data is transferred to the data buffer. This field must be cleared
bogdanm	82:6473597d706e	2215	* when C7816[ISO7816E] is set/enabled.
bogdanm	82:6473597d706e	2216	*/
bogdanm	82:6473597d706e	2217	//@{
bogdanm	82:6473597d706e	2218	#define BP_UART_C4_MAEN1 (7U) //!< Bit position for UART_C4_MAEN1.
bogdanm	82:6473597d706e	2219	#define BM_UART_C4_MAEN1 (0x80U) //!< Bit mask for UART_C4_MAEN1.
bogdanm	82:6473597d706e	2220	#define BS_UART_C4_MAEN1 (1U) //!< Bit field size in bits for UART_C4_MAEN1.
bogdanm	82:6473597d706e	2221
bogdanm	82:6473597d706e	2222	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2223	//! @brief Read current value of the UART_C4_MAEN1 field.
bogdanm	82:6473597d706e	2224	#define BR_UART_C4_MAEN1(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1))
bogdanm	82:6473597d706e	2225	#endif
bogdanm	82:6473597d706e	2226
bogdanm	82:6473597d706e	2227	//! @brief Format value for bitfield UART_C4_MAEN1.
bogdanm	82:6473597d706e	2228	#define BF_UART_C4_MAEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_MAEN1), uint8_t) & BM_UART_C4_MAEN1)
bogdanm	82:6473597d706e	2229
bogdanm	82:6473597d706e	2230	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2231	//! @brief Set the MAEN1 field to a new value.
bogdanm	82:6473597d706e	2232	#define BW_UART_C4_MAEN1(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1) = (v))
bogdanm	82:6473597d706e	2233	#endif
bogdanm	82:6473597d706e	2234	//@}
bogdanm	82:6473597d706e	2235
bogdanm	82:6473597d706e	2236	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2237	// HW_UART_C5 - UART Control Register 5
bogdanm	82:6473597d706e	2238	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2239
bogdanm	82:6473597d706e	2240	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2241	/*!
bogdanm	82:6473597d706e	2242	* @brief HW_UART_C5 - UART Control Register 5 (RW)
bogdanm	82:6473597d706e	2243	*
bogdanm	82:6473597d706e	2244	* Reset value: 0x00U
bogdanm	82:6473597d706e	2245	*/
bogdanm	82:6473597d706e	2246	typedef union _hw_uart_c5
bogdanm	82:6473597d706e	2247	{
bogdanm	82:6473597d706e	2248	uint8_t U;
bogdanm	82:6473597d706e	2249	struct _hw_uart_c5_bitfields
bogdanm	82:6473597d706e	2250	{
bogdanm	82:6473597d706e	2251	uint8_t RESERVED0 : 3; //!< [2:0]
bogdanm	82:6473597d706e	2252	uint8_t LBKDDMAS : 1; //!< [3] LIN Break Detect DMA Select Bit
bogdanm	82:6473597d706e	2253	uint8_t ILDMAS : 1; //!< [4] Idle Line DMA Select
bogdanm	82:6473597d706e	2254	uint8_t RDMAS : 1; //!< [5] Receiver Full DMA Select
bogdanm	82:6473597d706e	2255	uint8_t TCDMAS : 1; //!< [6] Transmission Complete DMA Select
bogdanm	82:6473597d706e	2256	uint8_t TDMAS : 1; //!< [7] Transmitter DMA Select
bogdanm	82:6473597d706e	2257	} B;
bogdanm	82:6473597d706e	2258	} hw_uart_c5_t;
bogdanm	82:6473597d706e	2259	#endif
bogdanm	82:6473597d706e	2260
bogdanm	82:6473597d706e	2261	/*!
bogdanm	82:6473597d706e	2262	* @name Constants and macros for entire UART_C5 register
bogdanm	82:6473597d706e	2263	*/
bogdanm	82:6473597d706e	2264	//@{
bogdanm	82:6473597d706e	2265	#define HW_UART_C5_ADDR(x) (REGS_UART_BASE(x) + 0xBU)
bogdanm	82:6473597d706e	2266
bogdanm	82:6473597d706e	2267	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2268	#define HW_UART_C5(x) ((__IO hw_uart_c5_t ) HW_UART_C5_ADDR(x))
bogdanm	82:6473597d706e	2269	#define HW_UART_C5_RD(x) (HW_UART_C5(x).U)
bogdanm	82:6473597d706e	2270	#define HW_UART_C5_WR(x, v) (HW_UART_C5(x).U = (v))
bogdanm	82:6473597d706e	2271	#define HW_UART_C5_SET(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) \| (v)))
bogdanm	82:6473597d706e	2272	#define HW_UART_C5_CLR(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2273	#define HW_UART_C5_TOG(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2274	#endif
bogdanm	82:6473597d706e	2275	//@}
bogdanm	82:6473597d706e	2276
bogdanm	82:6473597d706e	2277	/*
bogdanm	82:6473597d706e	2278	* Constants & macros for individual UART_C5 bitfields
bogdanm	82:6473597d706e	2279	*/
bogdanm	82:6473597d706e	2280
bogdanm	82:6473597d706e	2281	/*!
bogdanm	82:6473597d706e	2282	* @name Register UART_C5, field LBKDDMAS[3] (RW)
bogdanm	82:6473597d706e	2283	*
bogdanm	82:6473597d706e	2284	* Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or
bogdanm	82:6473597d706e	2285	* DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is
bogdanm	82:6473597d706e	2286	* set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless
bogdanm	82:6473597d706e	2287	* of the state of LBKDDMAS.
bogdanm	82:6473597d706e	2288	*
bogdanm	82:6473597d706e	2289	* Values:
bogdanm	82:6473597d706e	2290	* - 0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is
bogdanm	82:6473597d706e	2291	* asserted to request an interrupt service.
bogdanm	82:6473597d706e	2292	* - 1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is
bogdanm	82:6473597d706e	2293	* asserted to request a DMA transfer.
bogdanm	82:6473597d706e	2294	*/
bogdanm	82:6473597d706e	2295	//@{
bogdanm	82:6473597d706e	2296	#define BP_UART_C5_LBKDDMAS (3U) //!< Bit position for UART_C5_LBKDDMAS.
bogdanm	82:6473597d706e	2297	#define BM_UART_C5_LBKDDMAS (0x08U) //!< Bit mask for UART_C5_LBKDDMAS.
bogdanm	82:6473597d706e	2298	#define BS_UART_C5_LBKDDMAS (1U) //!< Bit field size in bits for UART_C5_LBKDDMAS.
bogdanm	82:6473597d706e	2299
bogdanm	82:6473597d706e	2300	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2301	//! @brief Read current value of the UART_C5_LBKDDMAS field.
bogdanm	82:6473597d706e	2302	#define BR_UART_C5_LBKDDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS))
bogdanm	82:6473597d706e	2303	#endif
bogdanm	82:6473597d706e	2304
bogdanm	82:6473597d706e	2305	//! @brief Format value for bitfield UART_C5_LBKDDMAS.
bogdanm	82:6473597d706e	2306	#define BF_UART_C5_LBKDDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_LBKDDMAS), uint8_t) & BM_UART_C5_LBKDDMAS)
bogdanm	82:6473597d706e	2307
bogdanm	82:6473597d706e	2308	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2309	//! @brief Set the LBKDDMAS field to a new value.
bogdanm	82:6473597d706e	2310	#define BW_UART_C5_LBKDDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS) = (v))
bogdanm	82:6473597d706e	2311	#endif
bogdanm	82:6473597d706e	2312	//@}
bogdanm	82:6473597d706e	2313
bogdanm	82:6473597d706e	2314	/*!
bogdanm	82:6473597d706e	2315	* @name Register UART_C5, field ILDMAS[4] (RW)
bogdanm	82:6473597d706e	2316	*
bogdanm	82:6473597d706e	2317	* Configures the idle line flag, S1[IDLE], to generate interrupt or DMA
bogdanm	82:6473597d706e	2318	* requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE
bogdanm	82:6473597d706e	2319	* DMA and IDLE interrupt request signals are not asserted, regardless of the state
bogdanm	82:6473597d706e	2320	* of ILDMAS.
bogdanm	82:6473597d706e	2321	*
bogdanm	82:6473597d706e	2322	* Values:
bogdanm	82:6473597d706e	2323	* - 0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is
bogdanm	82:6473597d706e	2324	* asserted to request an interrupt service.
bogdanm	82:6473597d706e	2325	* - 1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is
bogdanm	82:6473597d706e	2326	* asserted to request a DMA transfer.
bogdanm	82:6473597d706e	2327	*/
bogdanm	82:6473597d706e	2328	//@{
bogdanm	82:6473597d706e	2329	#define BP_UART_C5_ILDMAS (4U) //!< Bit position for UART_C5_ILDMAS.
bogdanm	82:6473597d706e	2330	#define BM_UART_C5_ILDMAS (0x10U) //!< Bit mask for UART_C5_ILDMAS.
bogdanm	82:6473597d706e	2331	#define BS_UART_C5_ILDMAS (1U) //!< Bit field size in bits for UART_C5_ILDMAS.
bogdanm	82:6473597d706e	2332
bogdanm	82:6473597d706e	2333	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2334	//! @brief Read current value of the UART_C5_ILDMAS field.
bogdanm	82:6473597d706e	2335	#define BR_UART_C5_ILDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS))
bogdanm	82:6473597d706e	2336	#endif
bogdanm	82:6473597d706e	2337
bogdanm	82:6473597d706e	2338	//! @brief Format value for bitfield UART_C5_ILDMAS.
bogdanm	82:6473597d706e	2339	#define BF_UART_C5_ILDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_ILDMAS), uint8_t) & BM_UART_C5_ILDMAS)
bogdanm	82:6473597d706e	2340
bogdanm	82:6473597d706e	2341	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2342	//! @brief Set the ILDMAS field to a new value.
bogdanm	82:6473597d706e	2343	#define BW_UART_C5_ILDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS) = (v))
bogdanm	82:6473597d706e	2344	#endif
bogdanm	82:6473597d706e	2345	//@}
bogdanm	82:6473597d706e	2346
bogdanm	82:6473597d706e	2347	/*!
bogdanm	82:6473597d706e	2348	* @name Register UART_C5, field RDMAS[5] (RW)
bogdanm	82:6473597d706e	2349	*
bogdanm	82:6473597d706e	2350	* Configures the receiver data register full flag, S1[RDRF], to generate
bogdanm	82:6473597d706e	2351	* interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
bogdanm	82:6473597d706e	2352	* set, the RDRF DMA and RDFR interrupt request signals are not asserted,
bogdanm	82:6473597d706e	2353	* regardless of the state of RDMAS.
bogdanm	82:6473597d706e	2354	*
bogdanm	82:6473597d706e	2355	* Values:
bogdanm	82:6473597d706e	2356	* - 0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
bogdanm	82:6473597d706e	2357	* asserted to request an interrupt service.
bogdanm	82:6473597d706e	2358	* - 1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
bogdanm	82:6473597d706e	2359	* asserted to request a DMA transfer.
bogdanm	82:6473597d706e	2360	*/
bogdanm	82:6473597d706e	2361	//@{
bogdanm	82:6473597d706e	2362	#define BP_UART_C5_RDMAS (5U) //!< Bit position for UART_C5_RDMAS.
bogdanm	82:6473597d706e	2363	#define BM_UART_C5_RDMAS (0x20U) //!< Bit mask for UART_C5_RDMAS.
bogdanm	82:6473597d706e	2364	#define BS_UART_C5_RDMAS (1U) //!< Bit field size in bits for UART_C5_RDMAS.
bogdanm	82:6473597d706e	2365
bogdanm	82:6473597d706e	2366	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2367	//! @brief Read current value of the UART_C5_RDMAS field.
bogdanm	82:6473597d706e	2368	#define BR_UART_C5_RDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS))
bogdanm	82:6473597d706e	2369	#endif
bogdanm	82:6473597d706e	2370
bogdanm	82:6473597d706e	2371	//! @brief Format value for bitfield UART_C5_RDMAS.
bogdanm	82:6473597d706e	2372	#define BF_UART_C5_RDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_RDMAS), uint8_t) & BM_UART_C5_RDMAS)
bogdanm	82:6473597d706e	2373
bogdanm	82:6473597d706e	2374	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2375	//! @brief Set the RDMAS field to a new value.
bogdanm	82:6473597d706e	2376	#define BW_UART_C5_RDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS) = (v))
bogdanm	82:6473597d706e	2377	#endif
bogdanm	82:6473597d706e	2378	//@}
bogdanm	82:6473597d706e	2379
bogdanm	82:6473597d706e	2380	/*!
bogdanm	82:6473597d706e	2381	* @name Register UART_C5, field TCDMAS[6] (RW)
bogdanm	82:6473597d706e	2382	*
bogdanm	82:6473597d706e	2383	* Configures the transmission complete flag, S1[TC], to generate interrupt or
bogdanm	82:6473597d706e	2384	* DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC
bogdanm	82:6473597d706e	2385	* interrupt request signals are not asserted when the S1[TC] flag is set, regardless
bogdanm	82:6473597d706e	2386	* of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE]
bogdanm	82:6473597d706e	2387	* must be cleared, and D must not be written unless a DMA request is being serviced.
bogdanm	82:6473597d706e	2388	*
bogdanm	82:6473597d706e	2389	* Values:
bogdanm	82:6473597d706e	2390	* - 0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request
bogdanm	82:6473597d706e	2391	* signal is asserted to request an interrupt service.
bogdanm	82:6473597d706e	2392	* - 1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request
bogdanm	82:6473597d706e	2393	* signal is asserted to request a DMA transfer.
bogdanm	82:6473597d706e	2394	*/
bogdanm	82:6473597d706e	2395	//@{
bogdanm	82:6473597d706e	2396	#define BP_UART_C5_TCDMAS (6U) //!< Bit position for UART_C5_TCDMAS.
bogdanm	82:6473597d706e	2397	#define BM_UART_C5_TCDMAS (0x40U) //!< Bit mask for UART_C5_TCDMAS.
bogdanm	82:6473597d706e	2398	#define BS_UART_C5_TCDMAS (1U) //!< Bit field size in bits for UART_C5_TCDMAS.
bogdanm	82:6473597d706e	2399
bogdanm	82:6473597d706e	2400	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2401	//! @brief Read current value of the UART_C5_TCDMAS field.
bogdanm	82:6473597d706e	2402	#define BR_UART_C5_TCDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS))
bogdanm	82:6473597d706e	2403	#endif
bogdanm	82:6473597d706e	2404
bogdanm	82:6473597d706e	2405	//! @brief Format value for bitfield UART_C5_TCDMAS.
bogdanm	82:6473597d706e	2406	#define BF_UART_C5_TCDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_TCDMAS), uint8_t) & BM_UART_C5_TCDMAS)
bogdanm	82:6473597d706e	2407
bogdanm	82:6473597d706e	2408	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2409	//! @brief Set the TCDMAS field to a new value.
bogdanm	82:6473597d706e	2410	#define BW_UART_C5_TCDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS) = (v))
bogdanm	82:6473597d706e	2411	#endif
bogdanm	82:6473597d706e	2412	//@}
bogdanm	82:6473597d706e	2413
bogdanm	82:6473597d706e	2414	/*!
bogdanm	82:6473597d706e	2415	* @name Register UART_C5, field TDMAS[7] (RW)
bogdanm	82:6473597d706e	2416	*
bogdanm	82:6473597d706e	2417	* Configures the transmit data register empty flag, S1[TDRE], to generate
bogdanm	82:6473597d706e	2418	* interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
bogdanm	82:6473597d706e	2419	* TDRE interrupt request signals are not asserted when the TDRE flag is set,
bogdanm	82:6473597d706e	2420	* regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
bogdanm	82:6473597d706e	2421	* must be cleared, and D must not be written unless a DMA request is being
bogdanm	82:6473597d706e	2422	* serviced.
bogdanm	82:6473597d706e	2423	*
bogdanm	82:6473597d706e	2424	* Values:
bogdanm	82:6473597d706e	2425	* - 0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
bogdanm	82:6473597d706e	2426	* request signal is asserted to request interrupt service.
bogdanm	82:6473597d706e	2427	* - 1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
bogdanm	82:6473597d706e	2428	* signal is asserted to request a DMA transfer.
bogdanm	82:6473597d706e	2429	*/
bogdanm	82:6473597d706e	2430	//@{
bogdanm	82:6473597d706e	2431	#define BP_UART_C5_TDMAS (7U) //!< Bit position for UART_C5_TDMAS.
bogdanm	82:6473597d706e	2432	#define BM_UART_C5_TDMAS (0x80U) //!< Bit mask for UART_C5_TDMAS.
bogdanm	82:6473597d706e	2433	#define BS_UART_C5_TDMAS (1U) //!< Bit field size in bits for UART_C5_TDMAS.
bogdanm	82:6473597d706e	2434
bogdanm	82:6473597d706e	2435	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2436	//! @brief Read current value of the UART_C5_TDMAS field.
bogdanm	82:6473597d706e	2437	#define BR_UART_C5_TDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS))
bogdanm	82:6473597d706e	2438	#endif
bogdanm	82:6473597d706e	2439
bogdanm	82:6473597d706e	2440	//! @brief Format value for bitfield UART_C5_TDMAS.
bogdanm	82:6473597d706e	2441	#define BF_UART_C5_TDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_TDMAS), uint8_t) & BM_UART_C5_TDMAS)
bogdanm	82:6473597d706e	2442
bogdanm	82:6473597d706e	2443	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2444	//! @brief Set the TDMAS field to a new value.
bogdanm	82:6473597d706e	2445	#define BW_UART_C5_TDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS) = (v))
bogdanm	82:6473597d706e	2446	#endif
bogdanm	82:6473597d706e	2447	//@}
bogdanm	82:6473597d706e	2448
bogdanm	82:6473597d706e	2449	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2450	// HW_UART_ED - UART Extended Data Register
bogdanm	82:6473597d706e	2451	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2452
bogdanm	82:6473597d706e	2453	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2454	/*!
bogdanm	82:6473597d706e	2455	* @brief HW_UART_ED - UART Extended Data Register (RO)
bogdanm	82:6473597d706e	2456	*
bogdanm	82:6473597d706e	2457	* Reset value: 0x00U
bogdanm	82:6473597d706e	2458	*
bogdanm	82:6473597d706e	2459	* This register contains additional information flags that are stored with a
bogdanm	82:6473597d706e	2460	* received dataword. This register may be read at any time but contains valid data
bogdanm	82:6473597d706e	2461	* only if there is a dataword in the receive FIFO. The data contained in this
bogdanm	82:6473597d706e	2462	* register represents additional information regarding the conditions on which a
bogdanm	82:6473597d706e	2463	* dataword was received. The importance of this data varies with the
bogdanm	82:6473597d706e	2464	* application, and in some cases maybe completely optional. These fields automatically
bogdanm	82:6473597d706e	2465	* update to reflect the conditions of the next dataword whenever D is read. If
bogdanm	82:6473597d706e	2466	* S1[NF] and S1[PF] have not been set since the last time the receive buffer was
bogdanm	82:6473597d706e	2467	* empty, the NOISY and PARITYE fields will be zero.
bogdanm	82:6473597d706e	2468	*/
bogdanm	82:6473597d706e	2469	typedef union _hw_uart_ed
bogdanm	82:6473597d706e	2470	{
bogdanm	82:6473597d706e	2471	uint8_t U;
bogdanm	82:6473597d706e	2472	struct _hw_uart_ed_bitfields
bogdanm	82:6473597d706e	2473	{
bogdanm	82:6473597d706e	2474	uint8_t RESERVED0 : 6; //!< [5:0]
bogdanm	82:6473597d706e	2475	uint8_t PARITYE : 1; //!< [6]
bogdanm	82:6473597d706e	2476	uint8_t NOISY : 1; //!< [7]
bogdanm	82:6473597d706e	2477	} B;
bogdanm	82:6473597d706e	2478	} hw_uart_ed_t;
bogdanm	82:6473597d706e	2479	#endif
bogdanm	82:6473597d706e	2480
bogdanm	82:6473597d706e	2481	/*!
bogdanm	82:6473597d706e	2482	* @name Constants and macros for entire UART_ED register
bogdanm	82:6473597d706e	2483	*/
bogdanm	82:6473597d706e	2484	//@{
bogdanm	82:6473597d706e	2485	#define HW_UART_ED_ADDR(x) (REGS_UART_BASE(x) + 0xCU)
bogdanm	82:6473597d706e	2486
bogdanm	82:6473597d706e	2487	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2488	#define HW_UART_ED(x) ((__I hw_uart_ed_t ) HW_UART_ED_ADDR(x))
bogdanm	82:6473597d706e	2489	#define HW_UART_ED_RD(x) (HW_UART_ED(x).U)
bogdanm	82:6473597d706e	2490	#endif
bogdanm	82:6473597d706e	2491	//@}
bogdanm	82:6473597d706e	2492
bogdanm	82:6473597d706e	2493	/*
bogdanm	82:6473597d706e	2494	* Constants & macros for individual UART_ED bitfields
bogdanm	82:6473597d706e	2495	*/
bogdanm	82:6473597d706e	2496
bogdanm	82:6473597d706e	2497	/*!
bogdanm	82:6473597d706e	2498	* @name Register UART_ED, field PARITYE[6] (RO)
bogdanm	82:6473597d706e	2499	*
bogdanm	82:6473597d706e	2500	* The current received dataword contained in D and C3[R8] was received with a
bogdanm	82:6473597d706e	2501	* parity error.
bogdanm	82:6473597d706e	2502	*
bogdanm	82:6473597d706e	2503	* Values:
bogdanm	82:6473597d706e	2504	* - 0 - The dataword was received without a parity error.
bogdanm	82:6473597d706e	2505	* - 1 - The dataword was received with a parity error.
bogdanm	82:6473597d706e	2506	*/
bogdanm	82:6473597d706e	2507	//@{
bogdanm	82:6473597d706e	2508	#define BP_UART_ED_PARITYE (6U) //!< Bit position for UART_ED_PARITYE.
bogdanm	82:6473597d706e	2509	#define BM_UART_ED_PARITYE (0x40U) //!< Bit mask for UART_ED_PARITYE.
bogdanm	82:6473597d706e	2510	#define BS_UART_ED_PARITYE (1U) //!< Bit field size in bits for UART_ED_PARITYE.
bogdanm	82:6473597d706e	2511
bogdanm	82:6473597d706e	2512	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2513	//! @brief Read current value of the UART_ED_PARITYE field.
bogdanm	82:6473597d706e	2514	#define BR_UART_ED_PARITYE(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_PARITYE))
bogdanm	82:6473597d706e	2515	#endif
bogdanm	82:6473597d706e	2516	//@}
bogdanm	82:6473597d706e	2517
bogdanm	82:6473597d706e	2518	/*!
bogdanm	82:6473597d706e	2519	* @name Register UART_ED, field NOISY[7] (RO)
bogdanm	82:6473597d706e	2520	*
bogdanm	82:6473597d706e	2521	* The current received dataword contained in D and C3[R8] was received with
bogdanm	82:6473597d706e	2522	* noise.
bogdanm	82:6473597d706e	2523	*
bogdanm	82:6473597d706e	2524	* Values:
bogdanm	82:6473597d706e	2525	* - 0 - The dataword was received without noise.
bogdanm	82:6473597d706e	2526	* - 1 - The data was received with noise.
bogdanm	82:6473597d706e	2527	*/
bogdanm	82:6473597d706e	2528	//@{
bogdanm	82:6473597d706e	2529	#define BP_UART_ED_NOISY (7U) //!< Bit position for UART_ED_NOISY.
bogdanm	82:6473597d706e	2530	#define BM_UART_ED_NOISY (0x80U) //!< Bit mask for UART_ED_NOISY.
bogdanm	82:6473597d706e	2531	#define BS_UART_ED_NOISY (1U) //!< Bit field size in bits for UART_ED_NOISY.
bogdanm	82:6473597d706e	2532
bogdanm	82:6473597d706e	2533	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2534	//! @brief Read current value of the UART_ED_NOISY field.
bogdanm	82:6473597d706e	2535	#define BR_UART_ED_NOISY(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_NOISY))
bogdanm	82:6473597d706e	2536	#endif
bogdanm	82:6473597d706e	2537	//@}
bogdanm	82:6473597d706e	2538
bogdanm	82:6473597d706e	2539	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2540	// HW_UART_MODEM - UART Modem Register
bogdanm	82:6473597d706e	2541	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2542
bogdanm	82:6473597d706e	2543	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2544	/*!
bogdanm	82:6473597d706e	2545	* @brief HW_UART_MODEM - UART Modem Register (RW)
bogdanm	82:6473597d706e	2546	*
bogdanm	82:6473597d706e	2547	* Reset value: 0x00U
bogdanm	82:6473597d706e	2548	*
bogdanm	82:6473597d706e	2549	* The MODEM register controls options for setting the modem configuration.
bogdanm	82:6473597d706e	2550	* RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is
bogdanm	82:6473597d706e	2551	* enabled. This will cause the RTS to deassert during ISO-7816 wait times. The
bogdanm	82:6473597d706e	2552	* ISO-7816 protocol does not use the RTS and CTS signals.
bogdanm	82:6473597d706e	2553	*/
bogdanm	82:6473597d706e	2554	typedef union _hw_uart_modem
bogdanm	82:6473597d706e	2555	{
bogdanm	82:6473597d706e	2556	uint8_t U;
bogdanm	82:6473597d706e	2557	struct _hw_uart_modem_bitfields
bogdanm	82:6473597d706e	2558	{
bogdanm	82:6473597d706e	2559	uint8_t TXCTSE : 1; //!< [0] Transmitter clear-to-send enable
bogdanm	82:6473597d706e	2560	uint8_t TXRTSE : 1; //!< [1] Transmitter request-to-send enable
bogdanm	82:6473597d706e	2561	uint8_t TXRTSPOL : 1; //!< [2] Transmitter request-to-send polarity
bogdanm	82:6473597d706e	2562	uint8_t RXRTSE : 1; //!< [3] Receiver request-to-send enable
bogdanm	82:6473597d706e	2563	uint8_t RESERVED0 : 4; //!< [7:4]
bogdanm	82:6473597d706e	2564	} B;
bogdanm	82:6473597d706e	2565	} hw_uart_modem_t;
bogdanm	82:6473597d706e	2566	#endif
bogdanm	82:6473597d706e	2567
bogdanm	82:6473597d706e	2568	/*!
bogdanm	82:6473597d706e	2569	* @name Constants and macros for entire UART_MODEM register
bogdanm	82:6473597d706e	2570	*/
bogdanm	82:6473597d706e	2571	//@{
bogdanm	82:6473597d706e	2572	#define HW_UART_MODEM_ADDR(x) (REGS_UART_BASE(x) + 0xDU)
bogdanm	82:6473597d706e	2573
bogdanm	82:6473597d706e	2574	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2575	#define HW_UART_MODEM(x) ((__IO hw_uart_modem_t ) HW_UART_MODEM_ADDR(x))
bogdanm	82:6473597d706e	2576	#define HW_UART_MODEM_RD(x) (HW_UART_MODEM(x).U)
bogdanm	82:6473597d706e	2577	#define HW_UART_MODEM_WR(x, v) (HW_UART_MODEM(x).U = (v))
bogdanm	82:6473597d706e	2578	#define HW_UART_MODEM_SET(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) \| (v)))
bogdanm	82:6473597d706e	2579	#define HW_UART_MODEM_CLR(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2580	#define HW_UART_MODEM_TOG(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2581	#endif
bogdanm	82:6473597d706e	2582	//@}
bogdanm	82:6473597d706e	2583
bogdanm	82:6473597d706e	2584	/*
bogdanm	82:6473597d706e	2585	* Constants & macros for individual UART_MODEM bitfields
bogdanm	82:6473597d706e	2586	*/
bogdanm	82:6473597d706e	2587
bogdanm	82:6473597d706e	2588	/*!
bogdanm	82:6473597d706e	2589	* @name Register UART_MODEM, field TXCTSE[0] (RW)
bogdanm	82:6473597d706e	2590	*
bogdanm	82:6473597d706e	2591	* TXCTSE controls the operation of the transmitter. TXCTSE can be set
bogdanm	82:6473597d706e	2592	* independently from the state of TXRTSE and RXRTSE.
bogdanm	82:6473597d706e	2593	*
bogdanm	82:6473597d706e	2594	* Values:
bogdanm	82:6473597d706e	2595	* - 0 - CTS has no effect on the transmitter.
bogdanm	82:6473597d706e	2596	* - 1 - Enables clear-to-send operation. The transmitter checks the state of
bogdanm	82:6473597d706e	2597	* CTS each time it is ready to send a character. If CTS is asserted, the
bogdanm	82:6473597d706e	2598	* character is sent. If CTS is deasserted, the signal TXD remains in the mark
bogdanm	82:6473597d706e	2599	* state and transmission is delayed until CTS is asserted. Changes in CTS as a
bogdanm	82:6473597d706e	2600	* character is being sent do not affect its transmission.
bogdanm	82:6473597d706e	2601	*/
bogdanm	82:6473597d706e	2602	//@{
bogdanm	82:6473597d706e	2603	#define BP_UART_MODEM_TXCTSE (0U) //!< Bit position for UART_MODEM_TXCTSE.
bogdanm	82:6473597d706e	2604	#define BM_UART_MODEM_TXCTSE (0x01U) //!< Bit mask for UART_MODEM_TXCTSE.
bogdanm	82:6473597d706e	2605	#define BS_UART_MODEM_TXCTSE (1U) //!< Bit field size in bits for UART_MODEM_TXCTSE.
bogdanm	82:6473597d706e	2606
bogdanm	82:6473597d706e	2607	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2608	//! @brief Read current value of the UART_MODEM_TXCTSE field.
bogdanm	82:6473597d706e	2609	#define BR_UART_MODEM_TXCTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE))
bogdanm	82:6473597d706e	2610	#endif
bogdanm	82:6473597d706e	2611
bogdanm	82:6473597d706e	2612	//! @brief Format value for bitfield UART_MODEM_TXCTSE.
bogdanm	82:6473597d706e	2613	#define BF_UART_MODEM_TXCTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXCTSE), uint8_t) & BM_UART_MODEM_TXCTSE)
bogdanm	82:6473597d706e	2614
bogdanm	82:6473597d706e	2615	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2616	//! @brief Set the TXCTSE field to a new value.
bogdanm	82:6473597d706e	2617	#define BW_UART_MODEM_TXCTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE) = (v))
bogdanm	82:6473597d706e	2618	#endif
bogdanm	82:6473597d706e	2619	//@}
bogdanm	82:6473597d706e	2620
bogdanm	82:6473597d706e	2621	/*!
bogdanm	82:6473597d706e	2622	* @name Register UART_MODEM, field TXRTSE[1] (RW)
bogdanm	82:6473597d706e	2623	*
bogdanm	82:6473597d706e	2624	* Controls RTS before and after a transmission.
bogdanm	82:6473597d706e	2625	*
bogdanm	82:6473597d706e	2626	* Values:
bogdanm	82:6473597d706e	2627	* - 0 - The transmitter has no effect on RTS.
bogdanm	82:6473597d706e	2628	* - 1 - When a character is placed into an empty transmitter data buffer , RTS
bogdanm	82:6473597d706e	2629	* asserts one bit time before the start bit is transmitted. RTS deasserts
bogdanm	82:6473597d706e	2630	* one bit time after all characters in the transmitter data buffer and shift
bogdanm	82:6473597d706e	2631	* register are completely sent, including the last stop bit. (FIFO) (FIFO)
bogdanm	82:6473597d706e	2632	*/
bogdanm	82:6473597d706e	2633	//@{
bogdanm	82:6473597d706e	2634	#define BP_UART_MODEM_TXRTSE (1U) //!< Bit position for UART_MODEM_TXRTSE.
bogdanm	82:6473597d706e	2635	#define BM_UART_MODEM_TXRTSE (0x02U) //!< Bit mask for UART_MODEM_TXRTSE.
bogdanm	82:6473597d706e	2636	#define BS_UART_MODEM_TXRTSE (1U) //!< Bit field size in bits for UART_MODEM_TXRTSE.
bogdanm	82:6473597d706e	2637
bogdanm	82:6473597d706e	2638	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2639	//! @brief Read current value of the UART_MODEM_TXRTSE field.
bogdanm	82:6473597d706e	2640	#define BR_UART_MODEM_TXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE))
bogdanm	82:6473597d706e	2641	#endif
bogdanm	82:6473597d706e	2642
bogdanm	82:6473597d706e	2643	//! @brief Format value for bitfield UART_MODEM_TXRTSE.
bogdanm	82:6473597d706e	2644	#define BF_UART_MODEM_TXRTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXRTSE), uint8_t) & BM_UART_MODEM_TXRTSE)
bogdanm	82:6473597d706e	2645
bogdanm	82:6473597d706e	2646	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2647	//! @brief Set the TXRTSE field to a new value.
bogdanm	82:6473597d706e	2648	#define BW_UART_MODEM_TXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE) = (v))
bogdanm	82:6473597d706e	2649	#endif
bogdanm	82:6473597d706e	2650	//@}
bogdanm	82:6473597d706e	2651
bogdanm	82:6473597d706e	2652	/*!
bogdanm	82:6473597d706e	2653	* @name Register UART_MODEM, field TXRTSPOL[2] (RW)
bogdanm	82:6473597d706e	2654	*
bogdanm	82:6473597d706e	2655	* Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
bogdanm	82:6473597d706e	2656	* polarity of the receiver RTS. RTS will remain negated in the active low state
bogdanm	82:6473597d706e	2657	* unless TXRTSE is set.
bogdanm	82:6473597d706e	2658	*
bogdanm	82:6473597d706e	2659	* Values:
bogdanm	82:6473597d706e	2660	* - 0 - Transmitter RTS is active low.
bogdanm	82:6473597d706e	2661	* - 1 - Transmitter RTS is active high.
bogdanm	82:6473597d706e	2662	*/
bogdanm	82:6473597d706e	2663	//@{
bogdanm	82:6473597d706e	2664	#define BP_UART_MODEM_TXRTSPOL (2U) //!< Bit position for UART_MODEM_TXRTSPOL.
bogdanm	82:6473597d706e	2665	#define BM_UART_MODEM_TXRTSPOL (0x04U) //!< Bit mask for UART_MODEM_TXRTSPOL.
bogdanm	82:6473597d706e	2666	#define BS_UART_MODEM_TXRTSPOL (1U) //!< Bit field size in bits for UART_MODEM_TXRTSPOL.
bogdanm	82:6473597d706e	2667
bogdanm	82:6473597d706e	2668	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2669	//! @brief Read current value of the UART_MODEM_TXRTSPOL field.
bogdanm	82:6473597d706e	2670	#define BR_UART_MODEM_TXRTSPOL(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL))
bogdanm	82:6473597d706e	2671	#endif
bogdanm	82:6473597d706e	2672
bogdanm	82:6473597d706e	2673	//! @brief Format value for bitfield UART_MODEM_TXRTSPOL.
bogdanm	82:6473597d706e	2674	#define BF_UART_MODEM_TXRTSPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXRTSPOL), uint8_t) & BM_UART_MODEM_TXRTSPOL)
bogdanm	82:6473597d706e	2675
bogdanm	82:6473597d706e	2676	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2677	//! @brief Set the TXRTSPOL field to a new value.
bogdanm	82:6473597d706e	2678	#define BW_UART_MODEM_TXRTSPOL(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL) = (v))
bogdanm	82:6473597d706e	2679	#endif
bogdanm	82:6473597d706e	2680	//@}
bogdanm	82:6473597d706e	2681
bogdanm	82:6473597d706e	2682	/*!
bogdanm	82:6473597d706e	2683	* @name Register UART_MODEM, field RXRTSE[3] (RW)
bogdanm	82:6473597d706e	2684	*
bogdanm	82:6473597d706e	2685	* Allows the RTS output to control the CTS input of the transmitting device to
bogdanm	82:6473597d706e	2686	* prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
bogdanm	82:6473597d706e	2687	*
bogdanm	82:6473597d706e	2688	* Values:
bogdanm	82:6473597d706e	2689	* - 0 - The receiver has no effect on RTS.
bogdanm	82:6473597d706e	2690	* - 1 - RTS is deasserted if the number of characters in the receiver data
bogdanm	82:6473597d706e	2691	* register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted
bogdanm	82:6473597d706e	2692	* when the number of characters in the receiver data register (FIFO) is less
bogdanm	82:6473597d706e	2693	* than RWFIFO[RXWATER].
bogdanm	82:6473597d706e	2694	*/
bogdanm	82:6473597d706e	2695	//@{
bogdanm	82:6473597d706e	2696	#define BP_UART_MODEM_RXRTSE (3U) //!< Bit position for UART_MODEM_RXRTSE.
bogdanm	82:6473597d706e	2697	#define BM_UART_MODEM_RXRTSE (0x08U) //!< Bit mask for UART_MODEM_RXRTSE.
bogdanm	82:6473597d706e	2698	#define BS_UART_MODEM_RXRTSE (1U) //!< Bit field size in bits for UART_MODEM_RXRTSE.
bogdanm	82:6473597d706e	2699
bogdanm	82:6473597d706e	2700	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2701	//! @brief Read current value of the UART_MODEM_RXRTSE field.
bogdanm	82:6473597d706e	2702	#define BR_UART_MODEM_RXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE))
bogdanm	82:6473597d706e	2703	#endif
bogdanm	82:6473597d706e	2704
bogdanm	82:6473597d706e	2705	//! @brief Format value for bitfield UART_MODEM_RXRTSE.
bogdanm	82:6473597d706e	2706	#define BF_UART_MODEM_RXRTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_RXRTSE), uint8_t) & BM_UART_MODEM_RXRTSE)
bogdanm	82:6473597d706e	2707
bogdanm	82:6473597d706e	2708	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2709	//! @brief Set the RXRTSE field to a new value.
bogdanm	82:6473597d706e	2710	#define BW_UART_MODEM_RXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE) = (v))
bogdanm	82:6473597d706e	2711	#endif
bogdanm	82:6473597d706e	2712	//@}
bogdanm	82:6473597d706e	2713
bogdanm	82:6473597d706e	2714	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2715	// HW_UART_IR - UART Infrared Register
bogdanm	82:6473597d706e	2716	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2717
bogdanm	82:6473597d706e	2718	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2719	/*!
bogdanm	82:6473597d706e	2720	* @brief HW_UART_IR - UART Infrared Register (RW)
bogdanm	82:6473597d706e	2721	*
bogdanm	82:6473597d706e	2722	* Reset value: 0x00U
bogdanm	82:6473597d706e	2723	*
bogdanm	82:6473597d706e	2724	* The IR register controls options for setting the infrared configuration.
bogdanm	82:6473597d706e	2725	*/
bogdanm	82:6473597d706e	2726	typedef union _hw_uart_ir
bogdanm	82:6473597d706e	2727	{
bogdanm	82:6473597d706e	2728	uint8_t U;
bogdanm	82:6473597d706e	2729	struct _hw_uart_ir_bitfields
bogdanm	82:6473597d706e	2730	{
bogdanm	82:6473597d706e	2731	uint8_t TNP : 2; //!< [1:0] Transmitter narrow pulse
bogdanm	82:6473597d706e	2732	uint8_t IREN : 1; //!< [2] Infrared enable
bogdanm	82:6473597d706e	2733	uint8_t RESERVED0 : 5; //!< [7:3]
bogdanm	82:6473597d706e	2734	} B;
bogdanm	82:6473597d706e	2735	} hw_uart_ir_t;
bogdanm	82:6473597d706e	2736	#endif
bogdanm	82:6473597d706e	2737
bogdanm	82:6473597d706e	2738	/*!
bogdanm	82:6473597d706e	2739	* @name Constants and macros for entire UART_IR register
bogdanm	82:6473597d706e	2740	*/
bogdanm	82:6473597d706e	2741	//@{
bogdanm	82:6473597d706e	2742	#define HW_UART_IR_ADDR(x) (REGS_UART_BASE(x) + 0xEU)
bogdanm	82:6473597d706e	2743
bogdanm	82:6473597d706e	2744	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2745	#define HW_UART_IR(x) ((__IO hw_uart_ir_t ) HW_UART_IR_ADDR(x))
bogdanm	82:6473597d706e	2746	#define HW_UART_IR_RD(x) (HW_UART_IR(x).U)
bogdanm	82:6473597d706e	2747	#define HW_UART_IR_WR(x, v) (HW_UART_IR(x).U = (v))
bogdanm	82:6473597d706e	2748	#define HW_UART_IR_SET(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) \| (v)))
bogdanm	82:6473597d706e	2749	#define HW_UART_IR_CLR(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2750	#define HW_UART_IR_TOG(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2751	#endif
bogdanm	82:6473597d706e	2752	//@}
bogdanm	82:6473597d706e	2753
bogdanm	82:6473597d706e	2754	/*
bogdanm	82:6473597d706e	2755	* Constants & macros for individual UART_IR bitfields
bogdanm	82:6473597d706e	2756	*/
bogdanm	82:6473597d706e	2757
bogdanm	82:6473597d706e	2758	/*!
bogdanm	82:6473597d706e	2759	* @name Register UART_IR, field TNP[1:0] (RW)
bogdanm	82:6473597d706e	2760	*
bogdanm	82:6473597d706e	2761	* Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse.
bogdanm	82:6473597d706e	2762	*
bogdanm	82:6473597d706e	2763	* Values:
bogdanm	82:6473597d706e	2764	* - 00 - 3/16.
bogdanm	82:6473597d706e	2765	* - 01 - 1/16.
bogdanm	82:6473597d706e	2766	* - 10 - 1/32.
bogdanm	82:6473597d706e	2767	* - 11 - 1/4.
bogdanm	82:6473597d706e	2768	*/
bogdanm	82:6473597d706e	2769	//@{
bogdanm	82:6473597d706e	2770	#define BP_UART_IR_TNP (0U) //!< Bit position for UART_IR_TNP.
bogdanm	82:6473597d706e	2771	#define BM_UART_IR_TNP (0x03U) //!< Bit mask for UART_IR_TNP.
bogdanm	82:6473597d706e	2772	#define BS_UART_IR_TNP (2U) //!< Bit field size in bits for UART_IR_TNP.
bogdanm	82:6473597d706e	2773
bogdanm	82:6473597d706e	2774	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2775	//! @brief Read current value of the UART_IR_TNP field.
bogdanm	82:6473597d706e	2776	#define BR_UART_IR_TNP(x) (HW_UART_IR(x).B.TNP)
bogdanm	82:6473597d706e	2777	#endif
bogdanm	82:6473597d706e	2778
bogdanm	82:6473597d706e	2779	//! @brief Format value for bitfield UART_IR_TNP.
bogdanm	82:6473597d706e	2780	#define BF_UART_IR_TNP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IR_TNP), uint8_t) & BM_UART_IR_TNP)
bogdanm	82:6473597d706e	2781
bogdanm	82:6473597d706e	2782	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2783	//! @brief Set the TNP field to a new value.
bogdanm	82:6473597d706e	2784	#define BW_UART_IR_TNP(x, v) (HW_UART_IR_WR(x, (HW_UART_IR_RD(x) & ~BM_UART_IR_TNP) \| BF_UART_IR_TNP(v)))
bogdanm	82:6473597d706e	2785	#endif
bogdanm	82:6473597d706e	2786	//@}
bogdanm	82:6473597d706e	2787
bogdanm	82:6473597d706e	2788	/*!
bogdanm	82:6473597d706e	2789	* @name Register UART_IR, field IREN[2] (RW)
bogdanm	82:6473597d706e	2790	*
bogdanm	82:6473597d706e	2791	* Enables/disables the infrared modulation/demodulation.
bogdanm	82:6473597d706e	2792	*
bogdanm	82:6473597d706e	2793	* Values:
bogdanm	82:6473597d706e	2794	* - 0 - IR disabled.
bogdanm	82:6473597d706e	2795	* - 1 - IR enabled.
bogdanm	82:6473597d706e	2796	*/
bogdanm	82:6473597d706e	2797	//@{
bogdanm	82:6473597d706e	2798	#define BP_UART_IR_IREN (2U) //!< Bit position for UART_IR_IREN.
bogdanm	82:6473597d706e	2799	#define BM_UART_IR_IREN (0x04U) //!< Bit mask for UART_IR_IREN.
bogdanm	82:6473597d706e	2800	#define BS_UART_IR_IREN (1U) //!< Bit field size in bits for UART_IR_IREN.
bogdanm	82:6473597d706e	2801
bogdanm	82:6473597d706e	2802	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2803	//! @brief Read current value of the UART_IR_IREN field.
bogdanm	82:6473597d706e	2804	#define BR_UART_IR_IREN(x) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN))
bogdanm	82:6473597d706e	2805	#endif
bogdanm	82:6473597d706e	2806
bogdanm	82:6473597d706e	2807	//! @brief Format value for bitfield UART_IR_IREN.
bogdanm	82:6473597d706e	2808	#define BF_UART_IR_IREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IR_IREN), uint8_t) & BM_UART_IR_IREN)
bogdanm	82:6473597d706e	2809
bogdanm	82:6473597d706e	2810	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2811	//! @brief Set the IREN field to a new value.
bogdanm	82:6473597d706e	2812	#define BW_UART_IR_IREN(x, v) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN) = (v))
bogdanm	82:6473597d706e	2813	#endif
bogdanm	82:6473597d706e	2814	//@}
bogdanm	82:6473597d706e	2815
bogdanm	82:6473597d706e	2816	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2817	// HW_UART_PFIFO - UART FIFO Parameters
bogdanm	82:6473597d706e	2818	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2819
bogdanm	82:6473597d706e	2820	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2821	/*!
bogdanm	82:6473597d706e	2822	* @brief HW_UART_PFIFO - UART FIFO Parameters (RW)
bogdanm	82:6473597d706e	2823	*
bogdanm	82:6473597d706e	2824	* Reset value: 0x00U
bogdanm	82:6473597d706e	2825	*
bogdanm	82:6473597d706e	2826	* This register provides the ability for the programmer to turn on and off FIFO
bogdanm	82:6473597d706e	2827	* functionality. It also provides the size of the FIFO that has been
bogdanm	82:6473597d706e	2828	* implemented. This register may be read at any time. This register must be written only
bogdanm	82:6473597d706e	2829	* when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is
bogdanm	82:6473597d706e	2830	* empty.
bogdanm	82:6473597d706e	2831	*/
bogdanm	82:6473597d706e	2832	typedef union _hw_uart_pfifo
bogdanm	82:6473597d706e	2833	{
bogdanm	82:6473597d706e	2834	uint8_t U;
bogdanm	82:6473597d706e	2835	struct _hw_uart_pfifo_bitfields
bogdanm	82:6473597d706e	2836	{
bogdanm	82:6473597d706e	2837	uint8_t RXFIFOSIZE : 3; //!< [2:0] Receive FIFO. Buffer Depth
bogdanm	82:6473597d706e	2838	uint8_t RXFE : 1; //!< [3] Receive FIFO Enable
bogdanm	82:6473597d706e	2839	uint8_t TXFIFOSIZE : 3; //!< [6:4] Transmit FIFO. Buffer Depth
bogdanm	82:6473597d706e	2840	uint8_t TXFE : 1; //!< [7] Transmit FIFO Enable
bogdanm	82:6473597d706e	2841	} B;
bogdanm	82:6473597d706e	2842	} hw_uart_pfifo_t;
bogdanm	82:6473597d706e	2843	#endif
bogdanm	82:6473597d706e	2844
bogdanm	82:6473597d706e	2845	/*!
bogdanm	82:6473597d706e	2846	* @name Constants and macros for entire UART_PFIFO register
bogdanm	82:6473597d706e	2847	*/
bogdanm	82:6473597d706e	2848	//@{
bogdanm	82:6473597d706e	2849	#define HW_UART_PFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x10U)
bogdanm	82:6473597d706e	2850
bogdanm	82:6473597d706e	2851	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2852	#define HW_UART_PFIFO(x) ((__IO hw_uart_pfifo_t ) HW_UART_PFIFO_ADDR(x))
bogdanm	82:6473597d706e	2853	#define HW_UART_PFIFO_RD(x) (HW_UART_PFIFO(x).U)
bogdanm	82:6473597d706e	2854	#define HW_UART_PFIFO_WR(x, v) (HW_UART_PFIFO(x).U = (v))
bogdanm	82:6473597d706e	2855	#define HW_UART_PFIFO_SET(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) \| (v)))
bogdanm	82:6473597d706e	2856	#define HW_UART_PFIFO_CLR(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2857	#define HW_UART_PFIFO_TOG(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2858	#endif
bogdanm	82:6473597d706e	2859	//@}
bogdanm	82:6473597d706e	2860
bogdanm	82:6473597d706e	2861	/*
bogdanm	82:6473597d706e	2862	* Constants & macros for individual UART_PFIFO bitfields
bogdanm	82:6473597d706e	2863	*/
bogdanm	82:6473597d706e	2864
bogdanm	82:6473597d706e	2865	/*!
bogdanm	82:6473597d706e	2866	* @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO)
bogdanm	82:6473597d706e	2867	*
bogdanm	82:6473597d706e	2868	* The maximum number of receive datawords that can be stored in the receive
bogdanm	82:6473597d706e	2869	* buffer before an overrun occurs. This field is read only.
bogdanm	82:6473597d706e	2870	*
bogdanm	82:6473597d706e	2871	* Values:
bogdanm	82:6473597d706e	2872	* - 000 - Receive FIFO/Buffer depth = 1 dataword.
bogdanm	82:6473597d706e	2873	* - 001 - Receive FIFO/Buffer depth = 4 datawords.
bogdanm	82:6473597d706e	2874	* - 010 - Receive FIFO/Buffer depth = 8 datawords.
bogdanm	82:6473597d706e	2875	* - 011 - Receive FIFO/Buffer depth = 16 datawords.
bogdanm	82:6473597d706e	2876	* - 100 - Receive FIFO/Buffer depth = 32 datawords.
bogdanm	82:6473597d706e	2877	* - 101 - Receive FIFO/Buffer depth = 64 datawords.
bogdanm	82:6473597d706e	2878	* - 110 - Receive FIFO/Buffer depth = 128 datawords.
bogdanm	82:6473597d706e	2879	* - 111 - Reserved.
bogdanm	82:6473597d706e	2880	*/
bogdanm	82:6473597d706e	2881	//@{
bogdanm	82:6473597d706e	2882	#define BP_UART_PFIFO_RXFIFOSIZE (0U) //!< Bit position for UART_PFIFO_RXFIFOSIZE.
bogdanm	82:6473597d706e	2883	#define BM_UART_PFIFO_RXFIFOSIZE (0x07U) //!< Bit mask for UART_PFIFO_RXFIFOSIZE.
bogdanm	82:6473597d706e	2884	#define BS_UART_PFIFO_RXFIFOSIZE (3U) //!< Bit field size in bits for UART_PFIFO_RXFIFOSIZE.
bogdanm	82:6473597d706e	2885
bogdanm	82:6473597d706e	2886	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2887	//! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field.
bogdanm	82:6473597d706e	2888	#define BR_UART_PFIFO_RXFIFOSIZE(x) (HW_UART_PFIFO(x).B.RXFIFOSIZE)
bogdanm	82:6473597d706e	2889	#endif
bogdanm	82:6473597d706e	2890	//@}
bogdanm	82:6473597d706e	2891
bogdanm	82:6473597d706e	2892	/*!
bogdanm	82:6473597d706e	2893	* @name Register UART_PFIFO, field RXFE[3] (RW)
bogdanm	82:6473597d706e	2894	*
bogdanm	82:6473597d706e	2895	* When this field is set, the built in FIFO structure for the receive buffer is
bogdanm	82:6473597d706e	2896	* enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field.
bogdanm	82:6473597d706e	2897	* If this field is not set, the receive buffer operates as a FIFO of depth one
bogdanm	82:6473597d706e	2898	* dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
bogdanm	82:6473597d706e	2899	* cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH
bogdanm	82:6473597d706e	2900	* commands must be issued immediately after changing this field.
bogdanm	82:6473597d706e	2901	*
bogdanm	82:6473597d706e	2902	* Values:
bogdanm	82:6473597d706e	2903	* - 0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
bogdanm	82:6473597d706e	2904	* - 1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
bogdanm	82:6473597d706e	2905	*/
bogdanm	82:6473597d706e	2906	//@{
bogdanm	82:6473597d706e	2907	#define BP_UART_PFIFO_RXFE (3U) //!< Bit position for UART_PFIFO_RXFE.
bogdanm	82:6473597d706e	2908	#define BM_UART_PFIFO_RXFE (0x08U) //!< Bit mask for UART_PFIFO_RXFE.
bogdanm	82:6473597d706e	2909	#define BS_UART_PFIFO_RXFE (1U) //!< Bit field size in bits for UART_PFIFO_RXFE.
bogdanm	82:6473597d706e	2910
bogdanm	82:6473597d706e	2911	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2912	//! @brief Read current value of the UART_PFIFO_RXFE field.
bogdanm	82:6473597d706e	2913	#define BR_UART_PFIFO_RXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE))
bogdanm	82:6473597d706e	2914	#endif
bogdanm	82:6473597d706e	2915
bogdanm	82:6473597d706e	2916	//! @brief Format value for bitfield UART_PFIFO_RXFE.
bogdanm	82:6473597d706e	2917	#define BF_UART_PFIFO_RXFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_PFIFO_RXFE), uint8_t) & BM_UART_PFIFO_RXFE)
bogdanm	82:6473597d706e	2918
bogdanm	82:6473597d706e	2919	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2920	//! @brief Set the RXFE field to a new value.
bogdanm	82:6473597d706e	2921	#define BW_UART_PFIFO_RXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE) = (v))
bogdanm	82:6473597d706e	2922	#endif
bogdanm	82:6473597d706e	2923	//@}
bogdanm	82:6473597d706e	2924
bogdanm	82:6473597d706e	2925	/*!
bogdanm	82:6473597d706e	2926	* @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO)
bogdanm	82:6473597d706e	2927	*
bogdanm	82:6473597d706e	2928	* The maximum number of transmit datawords that can be stored in the transmit
bogdanm	82:6473597d706e	2929	* buffer. This field is read only.
bogdanm	82:6473597d706e	2930	*
bogdanm	82:6473597d706e	2931	* Values:
bogdanm	82:6473597d706e	2932	* - 000 - Transmit FIFO/Buffer depth = 1 dataword.
bogdanm	82:6473597d706e	2933	* - 001 - Transmit FIFO/Buffer depth = 4 datawords.
bogdanm	82:6473597d706e	2934	* - 010 - Transmit FIFO/Buffer depth = 8 datawords.
bogdanm	82:6473597d706e	2935	* - 011 - Transmit FIFO/Buffer depth = 16 datawords.
bogdanm	82:6473597d706e	2936	* - 100 - Transmit FIFO/Buffer depth = 32 datawords.
bogdanm	82:6473597d706e	2937	* - 101 - Transmit FIFO/Buffer depth = 64 datawords.
bogdanm	82:6473597d706e	2938	* - 110 - Transmit FIFO/Buffer depth = 128 datawords.
bogdanm	82:6473597d706e	2939	* - 111 - Reserved.
bogdanm	82:6473597d706e	2940	*/
bogdanm	82:6473597d706e	2941	//@{
bogdanm	82:6473597d706e	2942	#define BP_UART_PFIFO_TXFIFOSIZE (4U) //!< Bit position for UART_PFIFO_TXFIFOSIZE.
bogdanm	82:6473597d706e	2943	#define BM_UART_PFIFO_TXFIFOSIZE (0x70U) //!< Bit mask for UART_PFIFO_TXFIFOSIZE.
bogdanm	82:6473597d706e	2944	#define BS_UART_PFIFO_TXFIFOSIZE (3U) //!< Bit field size in bits for UART_PFIFO_TXFIFOSIZE.
bogdanm	82:6473597d706e	2945
bogdanm	82:6473597d706e	2946	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2947	//! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field.
bogdanm	82:6473597d706e	2948	#define BR_UART_PFIFO_TXFIFOSIZE(x) (HW_UART_PFIFO(x).B.TXFIFOSIZE)
bogdanm	82:6473597d706e	2949	#endif
bogdanm	82:6473597d706e	2950	//@}
bogdanm	82:6473597d706e	2951
bogdanm	82:6473597d706e	2952	/*!
bogdanm	82:6473597d706e	2953	* @name Register UART_PFIFO, field TXFE[7] (RW)
bogdanm	82:6473597d706e	2954	*
bogdanm	82:6473597d706e	2955	* When this field is set, the built in FIFO structure for the transmit buffer
bogdanm	82:6473597d706e	2956	* is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this
bogdanm	82:6473597d706e	2957	* field is not set, the transmit buffer operates as a FIFO of depth one dataword
bogdanm	82:6473597d706e	2958	* regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared
bogdanm	82:6473597d706e	2959	* prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must
bogdanm	82:6473597d706e	2960	* be issued immediately after changing this field.
bogdanm	82:6473597d706e	2961	*
bogdanm	82:6473597d706e	2962	* Values:
bogdanm	82:6473597d706e	2963	* - 0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
bogdanm	82:6473597d706e	2964	* - 1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
bogdanm	82:6473597d706e	2965	*/
bogdanm	82:6473597d706e	2966	//@{
bogdanm	82:6473597d706e	2967	#define BP_UART_PFIFO_TXFE (7U) //!< Bit position for UART_PFIFO_TXFE.
bogdanm	82:6473597d706e	2968	#define BM_UART_PFIFO_TXFE (0x80U) //!< Bit mask for UART_PFIFO_TXFE.
bogdanm	82:6473597d706e	2969	#define BS_UART_PFIFO_TXFE (1U) //!< Bit field size in bits for UART_PFIFO_TXFE.
bogdanm	82:6473597d706e	2970
bogdanm	82:6473597d706e	2971	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2972	//! @brief Read current value of the UART_PFIFO_TXFE field.
bogdanm	82:6473597d706e	2973	#define BR_UART_PFIFO_TXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE))
bogdanm	82:6473597d706e	2974	#endif
bogdanm	82:6473597d706e	2975
bogdanm	82:6473597d706e	2976	//! @brief Format value for bitfield UART_PFIFO_TXFE.
bogdanm	82:6473597d706e	2977	#define BF_UART_PFIFO_TXFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_PFIFO_TXFE), uint8_t) & BM_UART_PFIFO_TXFE)
bogdanm	82:6473597d706e	2978
bogdanm	82:6473597d706e	2979	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2980	//! @brief Set the TXFE field to a new value.
bogdanm	82:6473597d706e	2981	#define BW_UART_PFIFO_TXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE) = (v))
bogdanm	82:6473597d706e	2982	#endif
bogdanm	82:6473597d706e	2983	//@}
bogdanm	82:6473597d706e	2984
bogdanm	82:6473597d706e	2985	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2986	// HW_UART_CFIFO - UART FIFO Control Register
bogdanm	82:6473597d706e	2987	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2988
bogdanm	82:6473597d706e	2989	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2990	/*!
bogdanm	82:6473597d706e	2991	* @brief HW_UART_CFIFO - UART FIFO Control Register (RW)
bogdanm	82:6473597d706e	2992	*
bogdanm	82:6473597d706e	2993	* Reset value: 0x00U
bogdanm	82:6473597d706e	2994	*
bogdanm	82:6473597d706e	2995	* This register provides the ability to program various control fields for FIFO
bogdanm	82:6473597d706e	2996	* operation. This register may be read or written at any time. Note that
bogdanm	82:6473597d706e	2997	* writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action
bogdanm	82:6473597d706e	2998	* to prevent unintended/unpredictable behavior. Therefore, it is recommended that
bogdanm	82:6473597d706e	2999	* TE and RE be cleared prior to flushing the corresponding FIFO.
bogdanm	82:6473597d706e	3000	*/
bogdanm	82:6473597d706e	3001	typedef union _hw_uart_cfifo
bogdanm	82:6473597d706e	3002	{
bogdanm	82:6473597d706e	3003	uint8_t U;
bogdanm	82:6473597d706e	3004	struct _hw_uart_cfifo_bitfields
bogdanm	82:6473597d706e	3005	{
bogdanm	82:6473597d706e	3006	uint8_t RXUFE : 1; //!< [0] Receive FIFO Underflow Interrupt Enable
bogdanm	82:6473597d706e	3007	uint8_t TXOFE : 1; //!< [1] Transmit FIFO Overflow Interrupt Enable
bogdanm	82:6473597d706e	3008	uint8_t RXOFE : 1; //!< [2] Receive FIFO Overflow Interrupt Enable
bogdanm	82:6473597d706e	3009	uint8_t RESERVED0 : 3; //!< [5:3]
bogdanm	82:6473597d706e	3010	uint8_t RXFLUSH : 1; //!< [6] Receive FIFO/Buffer Flush
bogdanm	82:6473597d706e	3011	uint8_t TXFLUSH : 1; //!< [7] Transmit FIFO/Buffer Flush
bogdanm	82:6473597d706e	3012	} B;
bogdanm	82:6473597d706e	3013	} hw_uart_cfifo_t;
bogdanm	82:6473597d706e	3014	#endif
bogdanm	82:6473597d706e	3015
bogdanm	82:6473597d706e	3016	/*!
bogdanm	82:6473597d706e	3017	* @name Constants and macros for entire UART_CFIFO register
bogdanm	82:6473597d706e	3018	*/
bogdanm	82:6473597d706e	3019	//@{
bogdanm	82:6473597d706e	3020	#define HW_UART_CFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x11U)
bogdanm	82:6473597d706e	3021
bogdanm	82:6473597d706e	3022	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3023	#define HW_UART_CFIFO(x) ((__IO hw_uart_cfifo_t ) HW_UART_CFIFO_ADDR(x))
bogdanm	82:6473597d706e	3024	#define HW_UART_CFIFO_RD(x) (HW_UART_CFIFO(x).U)
bogdanm	82:6473597d706e	3025	#define HW_UART_CFIFO_WR(x, v) (HW_UART_CFIFO(x).U = (v))
bogdanm	82:6473597d706e	3026	#define HW_UART_CFIFO_SET(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) \| (v)))
bogdanm	82:6473597d706e	3027	#define HW_UART_CFIFO_CLR(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3028	#define HW_UART_CFIFO_TOG(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3029	#endif
bogdanm	82:6473597d706e	3030	//@}
bogdanm	82:6473597d706e	3031
bogdanm	82:6473597d706e	3032	/*
bogdanm	82:6473597d706e	3033	* Constants & macros for individual UART_CFIFO bitfields
bogdanm	82:6473597d706e	3034	*/
bogdanm	82:6473597d706e	3035
bogdanm	82:6473597d706e	3036	/*!
bogdanm	82:6473597d706e	3037	* @name Register UART_CFIFO, field RXUFE[0] (RW)
bogdanm	82:6473597d706e	3038	*
bogdanm	82:6473597d706e	3039	* When this field is set, the RXUF flag generates an interrupt to the host.
bogdanm	82:6473597d706e	3040	*
bogdanm	82:6473597d706e	3041	* Values:
bogdanm	82:6473597d706e	3042	* - 0 - RXUF flag does not generate an interrupt to the host.
bogdanm	82:6473597d706e	3043	* - 1 - RXUF flag generates an interrupt to the host.
bogdanm	82:6473597d706e	3044	*/
bogdanm	82:6473597d706e	3045	//@{
bogdanm	82:6473597d706e	3046	#define BP_UART_CFIFO_RXUFE (0U) //!< Bit position for UART_CFIFO_RXUFE.
bogdanm	82:6473597d706e	3047	#define BM_UART_CFIFO_RXUFE (0x01U) //!< Bit mask for UART_CFIFO_RXUFE.
bogdanm	82:6473597d706e	3048	#define BS_UART_CFIFO_RXUFE (1U) //!< Bit field size in bits for UART_CFIFO_RXUFE.
bogdanm	82:6473597d706e	3049
bogdanm	82:6473597d706e	3050	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3051	//! @brief Read current value of the UART_CFIFO_RXUFE field.
bogdanm	82:6473597d706e	3052	#define BR_UART_CFIFO_RXUFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE))
bogdanm	82:6473597d706e	3053	#endif
bogdanm	82:6473597d706e	3054
bogdanm	82:6473597d706e	3055	//! @brief Format value for bitfield UART_CFIFO_RXUFE.
bogdanm	82:6473597d706e	3056	#define BF_UART_CFIFO_RXUFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXUFE), uint8_t) & BM_UART_CFIFO_RXUFE)
bogdanm	82:6473597d706e	3057
bogdanm	82:6473597d706e	3058	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3059	//! @brief Set the RXUFE field to a new value.
bogdanm	82:6473597d706e	3060	#define BW_UART_CFIFO_RXUFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE) = (v))
bogdanm	82:6473597d706e	3061	#endif
bogdanm	82:6473597d706e	3062	//@}
bogdanm	82:6473597d706e	3063
bogdanm	82:6473597d706e	3064	/*!
bogdanm	82:6473597d706e	3065	* @name Register UART_CFIFO, field TXOFE[1] (RW)
bogdanm	82:6473597d706e	3066	*
bogdanm	82:6473597d706e	3067	* When this field is set, the TXOF flag generates an interrupt to the host.
bogdanm	82:6473597d706e	3068	*
bogdanm	82:6473597d706e	3069	* Values:
bogdanm	82:6473597d706e	3070	* - 0 - TXOF flag does not generate an interrupt to the host.
bogdanm	82:6473597d706e	3071	* - 1 - TXOF flag generates an interrupt to the host.
bogdanm	82:6473597d706e	3072	*/
bogdanm	82:6473597d706e	3073	//@{
bogdanm	82:6473597d706e	3074	#define BP_UART_CFIFO_TXOFE (1U) //!< Bit position for UART_CFIFO_TXOFE.
bogdanm	82:6473597d706e	3075	#define BM_UART_CFIFO_TXOFE (0x02U) //!< Bit mask for UART_CFIFO_TXOFE.
bogdanm	82:6473597d706e	3076	#define BS_UART_CFIFO_TXOFE (1U) //!< Bit field size in bits for UART_CFIFO_TXOFE.
bogdanm	82:6473597d706e	3077
bogdanm	82:6473597d706e	3078	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3079	//! @brief Read current value of the UART_CFIFO_TXOFE field.
bogdanm	82:6473597d706e	3080	#define BR_UART_CFIFO_TXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE))
bogdanm	82:6473597d706e	3081	#endif
bogdanm	82:6473597d706e	3082
bogdanm	82:6473597d706e	3083	//! @brief Format value for bitfield UART_CFIFO_TXOFE.
bogdanm	82:6473597d706e	3084	#define BF_UART_CFIFO_TXOFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_TXOFE), uint8_t) & BM_UART_CFIFO_TXOFE)
bogdanm	82:6473597d706e	3085
bogdanm	82:6473597d706e	3086	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3087	//! @brief Set the TXOFE field to a new value.
bogdanm	82:6473597d706e	3088	#define BW_UART_CFIFO_TXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE) = (v))
bogdanm	82:6473597d706e	3089	#endif
bogdanm	82:6473597d706e	3090	//@}
bogdanm	82:6473597d706e	3091
bogdanm	82:6473597d706e	3092	/*!
bogdanm	82:6473597d706e	3093	* @name Register UART_CFIFO, field RXOFE[2] (RW)
bogdanm	82:6473597d706e	3094	*
bogdanm	82:6473597d706e	3095	* When this field is set, the RXOF flag generates an interrupt to the host.
bogdanm	82:6473597d706e	3096	*
bogdanm	82:6473597d706e	3097	* Values:
bogdanm	82:6473597d706e	3098	* - 0 - RXOF flag does not generate an interrupt to the host.
bogdanm	82:6473597d706e	3099	* - 1 - RXOF flag generates an interrupt to the host.
bogdanm	82:6473597d706e	3100	*/
bogdanm	82:6473597d706e	3101	//@{
bogdanm	82:6473597d706e	3102	#define BP_UART_CFIFO_RXOFE (2U) //!< Bit position for UART_CFIFO_RXOFE.
bogdanm	82:6473597d706e	3103	#define BM_UART_CFIFO_RXOFE (0x04U) //!< Bit mask for UART_CFIFO_RXOFE.
bogdanm	82:6473597d706e	3104	#define BS_UART_CFIFO_RXOFE (1U) //!< Bit field size in bits for UART_CFIFO_RXOFE.
bogdanm	82:6473597d706e	3105
bogdanm	82:6473597d706e	3106	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3107	//! @brief Read current value of the UART_CFIFO_RXOFE field.
bogdanm	82:6473597d706e	3108	#define BR_UART_CFIFO_RXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE))
bogdanm	82:6473597d706e	3109	#endif
bogdanm	82:6473597d706e	3110
bogdanm	82:6473597d706e	3111	//! @brief Format value for bitfield UART_CFIFO_RXOFE.
bogdanm	82:6473597d706e	3112	#define BF_UART_CFIFO_RXOFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXOFE), uint8_t) & BM_UART_CFIFO_RXOFE)
bogdanm	82:6473597d706e	3113
bogdanm	82:6473597d706e	3114	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3115	//! @brief Set the RXOFE field to a new value.
bogdanm	82:6473597d706e	3116	#define BW_UART_CFIFO_RXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE) = (v))
bogdanm	82:6473597d706e	3117	#endif
bogdanm	82:6473597d706e	3118	//@}
bogdanm	82:6473597d706e	3119
bogdanm	82:6473597d706e	3120	/*!
bogdanm	82:6473597d706e	3121	* @name Register UART_CFIFO, field RXFLUSH[6] (WORZ)
bogdanm	82:6473597d706e	3122	*
bogdanm	82:6473597d706e	3123	* Writing to this field causes all data that is stored in the receive
bogdanm	82:6473597d706e	3124	* FIFO/buffer to be flushed. This does not affect data that is in the receive shift
bogdanm	82:6473597d706e	3125	* register.
bogdanm	82:6473597d706e	3126	*
bogdanm	82:6473597d706e	3127	* Values:
bogdanm	82:6473597d706e	3128	* - 0 - No flush operation occurs.
bogdanm	82:6473597d706e	3129	* - 1 - All data in the receive FIFO/buffer is cleared out.
bogdanm	82:6473597d706e	3130	*/
bogdanm	82:6473597d706e	3131	//@{
bogdanm	82:6473597d706e	3132	#define BP_UART_CFIFO_RXFLUSH (6U) //!< Bit position for UART_CFIFO_RXFLUSH.
bogdanm	82:6473597d706e	3133	#define BM_UART_CFIFO_RXFLUSH (0x40U) //!< Bit mask for UART_CFIFO_RXFLUSH.
bogdanm	82:6473597d706e	3134	#define BS_UART_CFIFO_RXFLUSH (1U) //!< Bit field size in bits for UART_CFIFO_RXFLUSH.
bogdanm	82:6473597d706e	3135
bogdanm	82:6473597d706e	3136	//! @brief Format value for bitfield UART_CFIFO_RXFLUSH.
bogdanm	82:6473597d706e	3137	#define BF_UART_CFIFO_RXFLUSH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXFLUSH), uint8_t) & BM_UART_CFIFO_RXFLUSH)
bogdanm	82:6473597d706e	3138
bogdanm	82:6473597d706e	3139	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3140	//! @brief Set the RXFLUSH field to a new value.
bogdanm	82:6473597d706e	3141	#define BW_UART_CFIFO_RXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXFLUSH) = (v))
bogdanm	82:6473597d706e	3142	#endif
bogdanm	82:6473597d706e	3143	//@}
bogdanm	82:6473597d706e	3144
bogdanm	82:6473597d706e	3145	/*!
bogdanm	82:6473597d706e	3146	* @name Register UART_CFIFO, field TXFLUSH[7] (WORZ)
bogdanm	82:6473597d706e	3147	*
bogdanm	82:6473597d706e	3148	* Writing to this field causes all data that is stored in the transmit
bogdanm	82:6473597d706e	3149	* FIFO/buffer to be flushed. This does not affect data that is in the transmit shift
bogdanm	82:6473597d706e	3150	* register.
bogdanm	82:6473597d706e	3151	*
bogdanm	82:6473597d706e	3152	* Values:
bogdanm	82:6473597d706e	3153	* - 0 - No flush operation occurs.
bogdanm	82:6473597d706e	3154	* - 1 - All data in the transmit FIFO/Buffer is cleared out.
bogdanm	82:6473597d706e	3155	*/
bogdanm	82:6473597d706e	3156	//@{
bogdanm	82:6473597d706e	3157	#define BP_UART_CFIFO_TXFLUSH (7U) //!< Bit position for UART_CFIFO_TXFLUSH.
bogdanm	82:6473597d706e	3158	#define BM_UART_CFIFO_TXFLUSH (0x80U) //!< Bit mask for UART_CFIFO_TXFLUSH.
bogdanm	82:6473597d706e	3159	#define BS_UART_CFIFO_TXFLUSH (1U) //!< Bit field size in bits for UART_CFIFO_TXFLUSH.
bogdanm	82:6473597d706e	3160
bogdanm	82:6473597d706e	3161	//! @brief Format value for bitfield UART_CFIFO_TXFLUSH.
bogdanm	82:6473597d706e	3162	#define BF_UART_CFIFO_TXFLUSH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_TXFLUSH), uint8_t) & BM_UART_CFIFO_TXFLUSH)
bogdanm	82:6473597d706e	3163
bogdanm	82:6473597d706e	3164	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3165	//! @brief Set the TXFLUSH field to a new value.
bogdanm	82:6473597d706e	3166	#define BW_UART_CFIFO_TXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXFLUSH) = (v))
bogdanm	82:6473597d706e	3167	#endif
bogdanm	82:6473597d706e	3168	//@}
bogdanm	82:6473597d706e	3169
bogdanm	82:6473597d706e	3170	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3171	// HW_UART_SFIFO - UART FIFO Status Register
bogdanm	82:6473597d706e	3172	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3173
bogdanm	82:6473597d706e	3174	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3175	/*!
bogdanm	82:6473597d706e	3176	* @brief HW_UART_SFIFO - UART FIFO Status Register (RW)
bogdanm	82:6473597d706e	3177	*
bogdanm	82:6473597d706e	3178	* Reset value: 0xC0U
bogdanm	82:6473597d706e	3179	*
bogdanm	82:6473597d706e	3180	* This register provides status information regarding the transmit and receiver
bogdanm	82:6473597d706e	3181	* buffers/FIFOs, including interrupt information. This register may be written
bogdanm	82:6473597d706e	3182	* to or read at any time.
bogdanm	82:6473597d706e	3183	*/
bogdanm	82:6473597d706e	3184	typedef union _hw_uart_sfifo
bogdanm	82:6473597d706e	3185	{
bogdanm	82:6473597d706e	3186	uint8_t U;
bogdanm	82:6473597d706e	3187	struct _hw_uart_sfifo_bitfields
bogdanm	82:6473597d706e	3188	{
bogdanm	82:6473597d706e	3189	uint8_t RXUF : 1; //!< [0] Receiver Buffer Underflow Flag
bogdanm	82:6473597d706e	3190	uint8_t TXOF : 1; //!< [1] Transmitter Buffer Overflow Flag
bogdanm	82:6473597d706e	3191	uint8_t RXOF : 1; //!< [2] Receiver Buffer Overflow Flag
bogdanm	82:6473597d706e	3192	uint8_t RESERVED0 : 3; //!< [5:3]
bogdanm	82:6473597d706e	3193	uint8_t RXEMPT : 1; //!< [6] Receive Buffer/FIFO Empty
bogdanm	82:6473597d706e	3194	uint8_t TXEMPT : 1; //!< [7] Transmit Buffer/FIFO Empty
bogdanm	82:6473597d706e	3195	} B;
bogdanm	82:6473597d706e	3196	} hw_uart_sfifo_t;
bogdanm	82:6473597d706e	3197	#endif
bogdanm	82:6473597d706e	3198
bogdanm	82:6473597d706e	3199	/*!
bogdanm	82:6473597d706e	3200	* @name Constants and macros for entire UART_SFIFO register
bogdanm	82:6473597d706e	3201	*/
bogdanm	82:6473597d706e	3202	//@{
bogdanm	82:6473597d706e	3203	#define HW_UART_SFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x12U)
bogdanm	82:6473597d706e	3204
bogdanm	82:6473597d706e	3205	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3206	#define HW_UART_SFIFO(x) ((__IO hw_uart_sfifo_t ) HW_UART_SFIFO_ADDR(x))
bogdanm	82:6473597d706e	3207	#define HW_UART_SFIFO_RD(x) (HW_UART_SFIFO(x).U)
bogdanm	82:6473597d706e	3208	#define HW_UART_SFIFO_WR(x, v) (HW_UART_SFIFO(x).U = (v))
bogdanm	82:6473597d706e	3209	#define HW_UART_SFIFO_SET(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) \| (v)))
bogdanm	82:6473597d706e	3210	#define HW_UART_SFIFO_CLR(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3211	#define HW_UART_SFIFO_TOG(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3212	#endif
bogdanm	82:6473597d706e	3213	//@}
bogdanm	82:6473597d706e	3214
bogdanm	82:6473597d706e	3215	/*
bogdanm	82:6473597d706e	3216	* Constants & macros for individual UART_SFIFO bitfields
bogdanm	82:6473597d706e	3217	*/
bogdanm	82:6473597d706e	3218
bogdanm	82:6473597d706e	3219	/*!
bogdanm	82:6473597d706e	3220	* @name Register UART_SFIFO, field RXUF[0] (W1C)
bogdanm	82:6473597d706e	3221	*
bogdanm	82:6473597d706e	3222	* Indicates that more data has been read from the receive buffer than was
bogdanm	82:6473597d706e	3223	* present. This field will assert regardless of the value of CFIFO[RXUFE]. However,
bogdanm	82:6473597d706e	3224	* an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag
bogdanm	82:6473597d706e	3225	* is cleared by writing a 1.
bogdanm	82:6473597d706e	3226	*
bogdanm	82:6473597d706e	3227	* Values:
bogdanm	82:6473597d706e	3228	* - 0 - No receive buffer underflow has occurred since the last time the flag
bogdanm	82:6473597d706e	3229	* was cleared.
bogdanm	82:6473597d706e	3230	* - 1 - At least one receive buffer underflow has occurred since the last time
bogdanm	82:6473597d706e	3231	* the flag was cleared.
bogdanm	82:6473597d706e	3232	*/
bogdanm	82:6473597d706e	3233	//@{
bogdanm	82:6473597d706e	3234	#define BP_UART_SFIFO_RXUF (0U) //!< Bit position for UART_SFIFO_RXUF.
bogdanm	82:6473597d706e	3235	#define BM_UART_SFIFO_RXUF (0x01U) //!< Bit mask for UART_SFIFO_RXUF.
bogdanm	82:6473597d706e	3236	#define BS_UART_SFIFO_RXUF (1U) //!< Bit field size in bits for UART_SFIFO_RXUF.
bogdanm	82:6473597d706e	3237
bogdanm	82:6473597d706e	3238	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3239	//! @brief Read current value of the UART_SFIFO_RXUF field.
bogdanm	82:6473597d706e	3240	#define BR_UART_SFIFO_RXUF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF))
bogdanm	82:6473597d706e	3241	#endif
bogdanm	82:6473597d706e	3242
bogdanm	82:6473597d706e	3243	//! @brief Format value for bitfield UART_SFIFO_RXUF.
bogdanm	82:6473597d706e	3244	#define BF_UART_SFIFO_RXUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_RXUF), uint8_t) & BM_UART_SFIFO_RXUF)
bogdanm	82:6473597d706e	3245
bogdanm	82:6473597d706e	3246	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3247	//! @brief Set the RXUF field to a new value.
bogdanm	82:6473597d706e	3248	#define BW_UART_SFIFO_RXUF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF) = (v))
bogdanm	82:6473597d706e	3249	#endif
bogdanm	82:6473597d706e	3250	//@}
bogdanm	82:6473597d706e	3251
bogdanm	82:6473597d706e	3252	/*!
bogdanm	82:6473597d706e	3253	* @name Register UART_SFIFO, field TXOF[1] (W1C)
bogdanm	82:6473597d706e	3254	*
bogdanm	82:6473597d706e	3255	* Indicates that more data has been written to the transmit buffer than it can
bogdanm	82:6473597d706e	3256	* hold. This field will assert regardless of the value of CFIFO[TXOFE]. However,
bogdanm	82:6473597d706e	3257	* an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This
bogdanm	82:6473597d706e	3258	* flag is cleared by writing a 1.
bogdanm	82:6473597d706e	3259	*
bogdanm	82:6473597d706e	3260	* Values:
bogdanm	82:6473597d706e	3261	* - 0 - No transmit buffer overflow has occurred since the last time the flag
bogdanm	82:6473597d706e	3262	* was cleared.
bogdanm	82:6473597d706e	3263	* - 1 - At least one transmit buffer overflow has occurred since the last time
bogdanm	82:6473597d706e	3264	* the flag was cleared.
bogdanm	82:6473597d706e	3265	*/
bogdanm	82:6473597d706e	3266	//@{
bogdanm	82:6473597d706e	3267	#define BP_UART_SFIFO_TXOF (1U) //!< Bit position for UART_SFIFO_TXOF.
bogdanm	82:6473597d706e	3268	#define BM_UART_SFIFO_TXOF (0x02U) //!< Bit mask for UART_SFIFO_TXOF.
bogdanm	82:6473597d706e	3269	#define BS_UART_SFIFO_TXOF (1U) //!< Bit field size in bits for UART_SFIFO_TXOF.
bogdanm	82:6473597d706e	3270
bogdanm	82:6473597d706e	3271	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3272	//! @brief Read current value of the UART_SFIFO_TXOF field.
bogdanm	82:6473597d706e	3273	#define BR_UART_SFIFO_TXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF))
bogdanm	82:6473597d706e	3274	#endif
bogdanm	82:6473597d706e	3275
bogdanm	82:6473597d706e	3276	//! @brief Format value for bitfield UART_SFIFO_TXOF.
bogdanm	82:6473597d706e	3277	#define BF_UART_SFIFO_TXOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_TXOF), uint8_t) & BM_UART_SFIFO_TXOF)
bogdanm	82:6473597d706e	3278
bogdanm	82:6473597d706e	3279	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3280	//! @brief Set the TXOF field to a new value.
bogdanm	82:6473597d706e	3281	#define BW_UART_SFIFO_TXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF) = (v))
bogdanm	82:6473597d706e	3282	#endif
bogdanm	82:6473597d706e	3283	//@}
bogdanm	82:6473597d706e	3284
bogdanm	82:6473597d706e	3285	/*!
bogdanm	82:6473597d706e	3286	* @name Register UART_SFIFO, field RXOF[2] (W1C)
bogdanm	82:6473597d706e	3287	*
bogdanm	82:6473597d706e	3288	* Indicates that more data has been written to the receive buffer than it can
bogdanm	82:6473597d706e	3289	* hold. This field will assert regardless of the value of CFIFO[RXOFE]. However,
bogdanm	82:6473597d706e	3290	* an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag
bogdanm	82:6473597d706e	3291	* is cleared by writing a 1.
bogdanm	82:6473597d706e	3292	*
bogdanm	82:6473597d706e	3293	* Values:
bogdanm	82:6473597d706e	3294	* - 0 - No receive buffer overflow has occurred since the last time the flag
bogdanm	82:6473597d706e	3295	* was cleared.
bogdanm	82:6473597d706e	3296	* - 1 - At least one receive buffer overflow has occurred since the last time
bogdanm	82:6473597d706e	3297	* the flag was cleared.
bogdanm	82:6473597d706e	3298	*/
bogdanm	82:6473597d706e	3299	//@{
bogdanm	82:6473597d706e	3300	#define BP_UART_SFIFO_RXOF (2U) //!< Bit position for UART_SFIFO_RXOF.
bogdanm	82:6473597d706e	3301	#define BM_UART_SFIFO_RXOF (0x04U) //!< Bit mask for UART_SFIFO_RXOF.
bogdanm	82:6473597d706e	3302	#define BS_UART_SFIFO_RXOF (1U) //!< Bit field size in bits for UART_SFIFO_RXOF.
bogdanm	82:6473597d706e	3303
bogdanm	82:6473597d706e	3304	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3305	//! @brief Read current value of the UART_SFIFO_RXOF field.
bogdanm	82:6473597d706e	3306	#define BR_UART_SFIFO_RXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF))
bogdanm	82:6473597d706e	3307	#endif
bogdanm	82:6473597d706e	3308
bogdanm	82:6473597d706e	3309	//! @brief Format value for bitfield UART_SFIFO_RXOF.
bogdanm	82:6473597d706e	3310	#define BF_UART_SFIFO_RXOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_RXOF), uint8_t) & BM_UART_SFIFO_RXOF)
bogdanm	82:6473597d706e	3311
bogdanm	82:6473597d706e	3312	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3313	//! @brief Set the RXOF field to a new value.
bogdanm	82:6473597d706e	3314	#define BW_UART_SFIFO_RXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF) = (v))
bogdanm	82:6473597d706e	3315	#endif
bogdanm	82:6473597d706e	3316	//@}
bogdanm	82:6473597d706e	3317
bogdanm	82:6473597d706e	3318	/*!
bogdanm	82:6473597d706e	3319	* @name Register UART_SFIFO, field RXEMPT[6] (RO)
bogdanm	82:6473597d706e	3320	*
bogdanm	82:6473597d706e	3321	* Asserts when there is no data in the receive FIFO/Buffer. This field does not
bogdanm	82:6473597d706e	3322	* take into account data that is in the receive shift register.
bogdanm	82:6473597d706e	3323	*
bogdanm	82:6473597d706e	3324	* Values:
bogdanm	82:6473597d706e	3325	* - 0 - Receive buffer is not empty.
bogdanm	82:6473597d706e	3326	* - 1 - Receive buffer is empty.
bogdanm	82:6473597d706e	3327	*/
bogdanm	82:6473597d706e	3328	//@{
bogdanm	82:6473597d706e	3329	#define BP_UART_SFIFO_RXEMPT (6U) //!< Bit position for UART_SFIFO_RXEMPT.
bogdanm	82:6473597d706e	3330	#define BM_UART_SFIFO_RXEMPT (0x40U) //!< Bit mask for UART_SFIFO_RXEMPT.
bogdanm	82:6473597d706e	3331	#define BS_UART_SFIFO_RXEMPT (1U) //!< Bit field size in bits for UART_SFIFO_RXEMPT.
bogdanm	82:6473597d706e	3332
bogdanm	82:6473597d706e	3333	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3334	//! @brief Read current value of the UART_SFIFO_RXEMPT field.
bogdanm	82:6473597d706e	3335	#define BR_UART_SFIFO_RXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXEMPT))
bogdanm	82:6473597d706e	3336	#endif
bogdanm	82:6473597d706e	3337	//@}
bogdanm	82:6473597d706e	3338
bogdanm	82:6473597d706e	3339	/*!
bogdanm	82:6473597d706e	3340	* @name Register UART_SFIFO, field TXEMPT[7] (RO)
bogdanm	82:6473597d706e	3341	*
bogdanm	82:6473597d706e	3342	* Asserts when there is no data in the Transmit FIFO/buffer. This field does
bogdanm	82:6473597d706e	3343	* not take into account data that is in the transmit shift register.
bogdanm	82:6473597d706e	3344	*
bogdanm	82:6473597d706e	3345	* Values:
bogdanm	82:6473597d706e	3346	* - 0 - Transmit buffer is not empty.
bogdanm	82:6473597d706e	3347	* - 1 - Transmit buffer is empty.
bogdanm	82:6473597d706e	3348	*/
bogdanm	82:6473597d706e	3349	//@{
bogdanm	82:6473597d706e	3350	#define BP_UART_SFIFO_TXEMPT (7U) //!< Bit position for UART_SFIFO_TXEMPT.
bogdanm	82:6473597d706e	3351	#define BM_UART_SFIFO_TXEMPT (0x80U) //!< Bit mask for UART_SFIFO_TXEMPT.
bogdanm	82:6473597d706e	3352	#define BS_UART_SFIFO_TXEMPT (1U) //!< Bit field size in bits for UART_SFIFO_TXEMPT.
bogdanm	82:6473597d706e	3353
bogdanm	82:6473597d706e	3354	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3355	//! @brief Read current value of the UART_SFIFO_TXEMPT field.
bogdanm	82:6473597d706e	3356	#define BR_UART_SFIFO_TXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXEMPT))
bogdanm	82:6473597d706e	3357	#endif
bogdanm	82:6473597d706e	3358	//@}
bogdanm	82:6473597d706e	3359
bogdanm	82:6473597d706e	3360	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3361	// HW_UART_TWFIFO - UART FIFO Transmit Watermark
bogdanm	82:6473597d706e	3362	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3363
bogdanm	82:6473597d706e	3364	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3365	/*!
bogdanm	82:6473597d706e	3366	* @brief HW_UART_TWFIFO - UART FIFO Transmit Watermark (RW)
bogdanm	82:6473597d706e	3367	*
bogdanm	82:6473597d706e	3368	* Reset value: 0x00U
bogdanm	82:6473597d706e	3369	*
bogdanm	82:6473597d706e	3370	* This register provides the ability to set a programmable threshold for
bogdanm	82:6473597d706e	3371	* notification of needing additional transmit data. This register may be read at any
bogdanm	82:6473597d706e	3372	* time but must be written only when C2[TE] is not set. Changing the value of the
bogdanm	82:6473597d706e	3373	* watermark will not clear the S1[TDRE] flag.
bogdanm	82:6473597d706e	3374	*/
bogdanm	82:6473597d706e	3375	typedef union _hw_uart_twfifo
bogdanm	82:6473597d706e	3376	{
bogdanm	82:6473597d706e	3377	uint8_t U;
bogdanm	82:6473597d706e	3378	struct _hw_uart_twfifo_bitfields
bogdanm	82:6473597d706e	3379	{
bogdanm	82:6473597d706e	3380	uint8_t TXWATER : 8; //!< [7:0] Transmit Watermark
bogdanm	82:6473597d706e	3381	} B;
bogdanm	82:6473597d706e	3382	} hw_uart_twfifo_t;
bogdanm	82:6473597d706e	3383	#endif
bogdanm	82:6473597d706e	3384
bogdanm	82:6473597d706e	3385	/*!
bogdanm	82:6473597d706e	3386	* @name Constants and macros for entire UART_TWFIFO register
bogdanm	82:6473597d706e	3387	*/
bogdanm	82:6473597d706e	3388	//@{
bogdanm	82:6473597d706e	3389	#define HW_UART_TWFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x13U)
bogdanm	82:6473597d706e	3390
bogdanm	82:6473597d706e	3391	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3392	#define HW_UART_TWFIFO(x) ((__IO hw_uart_twfifo_t ) HW_UART_TWFIFO_ADDR(x))
bogdanm	82:6473597d706e	3393	#define HW_UART_TWFIFO_RD(x) (HW_UART_TWFIFO(x).U)
bogdanm	82:6473597d706e	3394	#define HW_UART_TWFIFO_WR(x, v) (HW_UART_TWFIFO(x).U = (v))
bogdanm	82:6473597d706e	3395	#define HW_UART_TWFIFO_SET(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) \| (v)))
bogdanm	82:6473597d706e	3396	#define HW_UART_TWFIFO_CLR(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3397	#define HW_UART_TWFIFO_TOG(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3398	#endif
bogdanm	82:6473597d706e	3399	//@}
bogdanm	82:6473597d706e	3400
bogdanm	82:6473597d706e	3401	/*
bogdanm	82:6473597d706e	3402	* Constants & macros for individual UART_TWFIFO bitfields
bogdanm	82:6473597d706e	3403	*/
bogdanm	82:6473597d706e	3404
bogdanm	82:6473597d706e	3405	/*!
bogdanm	82:6473597d706e	3406	* @name Register UART_TWFIFO, field TXWATER[7:0] (RW)
bogdanm	82:6473597d706e	3407	*
bogdanm	82:6473597d706e	3408	* When the number of datawords in the transmit FIFO/buffer is equal to or less
bogdanm	82:6473597d706e	3409	* than the value in this register field, an interrupt via S1[TDRE] or a DMA
bogdanm	82:6473597d706e	3410	* request via C5[TDMAS] is generated as determined by C5[TDMAS] and C2[TIE]. For
bogdanm	82:6473597d706e	3411	* proper operation, the value in TXWATER must be set to be less than the size of
bogdanm	82:6473597d706e	3412	* the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE].
bogdanm	82:6473597d706e	3413	*/
bogdanm	82:6473597d706e	3414	//@{
bogdanm	82:6473597d706e	3415	#define BP_UART_TWFIFO_TXWATER (0U) //!< Bit position for UART_TWFIFO_TXWATER.
bogdanm	82:6473597d706e	3416	#define BM_UART_TWFIFO_TXWATER (0xFFU) //!< Bit mask for UART_TWFIFO_TXWATER.
bogdanm	82:6473597d706e	3417	#define BS_UART_TWFIFO_TXWATER (8U) //!< Bit field size in bits for UART_TWFIFO_TXWATER.
bogdanm	82:6473597d706e	3418
bogdanm	82:6473597d706e	3419	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3420	//! @brief Read current value of the UART_TWFIFO_TXWATER field.
bogdanm	82:6473597d706e	3421	#define BR_UART_TWFIFO_TXWATER(x) (HW_UART_TWFIFO(x).U)
bogdanm	82:6473597d706e	3422	#endif
bogdanm	82:6473597d706e	3423
bogdanm	82:6473597d706e	3424	//! @brief Format value for bitfield UART_TWFIFO_TXWATER.
bogdanm	82:6473597d706e	3425	#define BF_UART_TWFIFO_TXWATER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_TWFIFO_TXWATER), uint8_t) & BM_UART_TWFIFO_TXWATER)
bogdanm	82:6473597d706e	3426
bogdanm	82:6473597d706e	3427	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3428	//! @brief Set the TXWATER field to a new value.
bogdanm	82:6473597d706e	3429	#define BW_UART_TWFIFO_TXWATER(x, v) (HW_UART_TWFIFO_WR(x, v))
bogdanm	82:6473597d706e	3430	#endif
bogdanm	82:6473597d706e	3431	//@}
bogdanm	82:6473597d706e	3432
bogdanm	82:6473597d706e	3433	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3434	// HW_UART_TCFIFO - UART FIFO Transmit Count
bogdanm	82:6473597d706e	3435	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3436
bogdanm	82:6473597d706e	3437	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3438	/*!
bogdanm	82:6473597d706e	3439	* @brief HW_UART_TCFIFO - UART FIFO Transmit Count (RO)
bogdanm	82:6473597d706e	3440	*
bogdanm	82:6473597d706e	3441	* Reset value: 0x00U
bogdanm	82:6473597d706e	3442	*
bogdanm	82:6473597d706e	3443	* This is a read only register that indicates how many datawords are currently
bogdanm	82:6473597d706e	3444	* in the transmit buffer/FIFO. It may be read at any time.
bogdanm	82:6473597d706e	3445	*/
bogdanm	82:6473597d706e	3446	typedef union _hw_uart_tcfifo
bogdanm	82:6473597d706e	3447	{
bogdanm	82:6473597d706e	3448	uint8_t U;
bogdanm	82:6473597d706e	3449	struct _hw_uart_tcfifo_bitfields
bogdanm	82:6473597d706e	3450	{
bogdanm	82:6473597d706e	3451	uint8_t TXCOUNT : 8; //!< [7:0] Transmit Counter
bogdanm	82:6473597d706e	3452	} B;
bogdanm	82:6473597d706e	3453	} hw_uart_tcfifo_t;
bogdanm	82:6473597d706e	3454	#endif
bogdanm	82:6473597d706e	3455
bogdanm	82:6473597d706e	3456	/*!
bogdanm	82:6473597d706e	3457	* @name Constants and macros for entire UART_TCFIFO register
bogdanm	82:6473597d706e	3458	*/
bogdanm	82:6473597d706e	3459	//@{
bogdanm	82:6473597d706e	3460	#define HW_UART_TCFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x14U)
bogdanm	82:6473597d706e	3461
bogdanm	82:6473597d706e	3462	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3463	#define HW_UART_TCFIFO(x) ((__I hw_uart_tcfifo_t ) HW_UART_TCFIFO_ADDR(x))
bogdanm	82:6473597d706e	3464	#define HW_UART_TCFIFO_RD(x) (HW_UART_TCFIFO(x).U)
bogdanm	82:6473597d706e	3465	#endif
bogdanm	82:6473597d706e	3466	//@}
bogdanm	82:6473597d706e	3467
bogdanm	82:6473597d706e	3468	/*
bogdanm	82:6473597d706e	3469	* Constants & macros for individual UART_TCFIFO bitfields
bogdanm	82:6473597d706e	3470	*/
bogdanm	82:6473597d706e	3471
bogdanm	82:6473597d706e	3472	/*!
bogdanm	82:6473597d706e	3473	* @name Register UART_TCFIFO, field TXCOUNT[7:0] (RO)
bogdanm	82:6473597d706e	3474	*
bogdanm	82:6473597d706e	3475	* The value in this register indicates the number of datawords that are in the
bogdanm	82:6473597d706e	3476	* transmit FIFO/buffer. If a dataword is being transmitted, that is, in the
bogdanm	82:6473597d706e	3477	* transmit shift register, it is not included in the count. This value may be used
bogdanm	82:6473597d706e	3478	* in conjunction with PFIFO[TXFIFOSIZE] to calculate how much room is left in the
bogdanm	82:6473597d706e	3479	* transmit FIFO/buffer.
bogdanm	82:6473597d706e	3480	*/
bogdanm	82:6473597d706e	3481	//@{
bogdanm	82:6473597d706e	3482	#define BP_UART_TCFIFO_TXCOUNT (0U) //!< Bit position for UART_TCFIFO_TXCOUNT.
bogdanm	82:6473597d706e	3483	#define BM_UART_TCFIFO_TXCOUNT (0xFFU) //!< Bit mask for UART_TCFIFO_TXCOUNT.
bogdanm	82:6473597d706e	3484	#define BS_UART_TCFIFO_TXCOUNT (8U) //!< Bit field size in bits for UART_TCFIFO_TXCOUNT.
bogdanm	82:6473597d706e	3485
bogdanm	82:6473597d706e	3486	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3487	//! @brief Read current value of the UART_TCFIFO_TXCOUNT field.
bogdanm	82:6473597d706e	3488	#define BR_UART_TCFIFO_TXCOUNT(x) (HW_UART_TCFIFO(x).U)
bogdanm	82:6473597d706e	3489	#endif
bogdanm	82:6473597d706e	3490	//@}
bogdanm	82:6473597d706e	3491
bogdanm	82:6473597d706e	3492	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3493	// HW_UART_RWFIFO - UART FIFO Receive Watermark
bogdanm	82:6473597d706e	3494	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3495
bogdanm	82:6473597d706e	3496	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3497	/*!
bogdanm	82:6473597d706e	3498	* @brief HW_UART_RWFIFO - UART FIFO Receive Watermark (RW)
bogdanm	82:6473597d706e	3499	*
bogdanm	82:6473597d706e	3500	* Reset value: 0x01U
bogdanm	82:6473597d706e	3501	*
bogdanm	82:6473597d706e	3502	* This register provides the ability to set a programmable threshold for
bogdanm	82:6473597d706e	3503	* notification of the need to remove data from the receiver FIFO/buffer. This register
bogdanm	82:6473597d706e	3504	* may be read at any time but must be written only when C2[RE] is not asserted.
bogdanm	82:6473597d706e	3505	* Changing the value in this register will not clear S1[RDRF].
bogdanm	82:6473597d706e	3506	*/
bogdanm	82:6473597d706e	3507	typedef union _hw_uart_rwfifo
bogdanm	82:6473597d706e	3508	{
bogdanm	82:6473597d706e	3509	uint8_t U;
bogdanm	82:6473597d706e	3510	struct _hw_uart_rwfifo_bitfields
bogdanm	82:6473597d706e	3511	{
bogdanm	82:6473597d706e	3512	uint8_t RXWATER : 8; //!< [7:0] Receive Watermark
bogdanm	82:6473597d706e	3513	} B;
bogdanm	82:6473597d706e	3514	} hw_uart_rwfifo_t;
bogdanm	82:6473597d706e	3515	#endif
bogdanm	82:6473597d706e	3516
bogdanm	82:6473597d706e	3517	/*!
bogdanm	82:6473597d706e	3518	* @name Constants and macros for entire UART_RWFIFO register
bogdanm	82:6473597d706e	3519	*/
bogdanm	82:6473597d706e	3520	//@{
bogdanm	82:6473597d706e	3521	#define HW_UART_RWFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x15U)
bogdanm	82:6473597d706e	3522
bogdanm	82:6473597d706e	3523	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3524	#define HW_UART_RWFIFO(x) ((__IO hw_uart_rwfifo_t ) HW_UART_RWFIFO_ADDR(x))
bogdanm	82:6473597d706e	3525	#define HW_UART_RWFIFO_RD(x) (HW_UART_RWFIFO(x).U)
bogdanm	82:6473597d706e	3526	#define HW_UART_RWFIFO_WR(x, v) (HW_UART_RWFIFO(x).U = (v))
bogdanm	82:6473597d706e	3527	#define HW_UART_RWFIFO_SET(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) \| (v)))
bogdanm	82:6473597d706e	3528	#define HW_UART_RWFIFO_CLR(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3529	#define HW_UART_RWFIFO_TOG(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3530	#endif
bogdanm	82:6473597d706e	3531	//@}
bogdanm	82:6473597d706e	3532
bogdanm	82:6473597d706e	3533	/*
bogdanm	82:6473597d706e	3534	* Constants & macros for individual UART_RWFIFO bitfields
bogdanm	82:6473597d706e	3535	*/
bogdanm	82:6473597d706e	3536
bogdanm	82:6473597d706e	3537	/*!
bogdanm	82:6473597d706e	3538	* @name Register UART_RWFIFO, field RXWATER[7:0] (RW)
bogdanm	82:6473597d706e	3539	*
bogdanm	82:6473597d706e	3540	* When the number of datawords in the receive FIFO/buffer is equal to or
bogdanm	82:6473597d706e	3541	* greater than the value in this register field, an interrupt via S1[RDRF] or a DMA
bogdanm	82:6473597d706e	3542	* request via C5[RDMAS] is generated as determined by C5[RDMAS] and C2[RIE]. For
bogdanm	82:6473597d706e	3543	* proper operation, the value in RXWATER must be set to be less than the receive
bogdanm	82:6473597d706e	3544	* FIFO/buffer size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and must be
bogdanm	82:6473597d706e	3545	* greater than 0.
bogdanm	82:6473597d706e	3546	*/
bogdanm	82:6473597d706e	3547	//@{
bogdanm	82:6473597d706e	3548	#define BP_UART_RWFIFO_RXWATER (0U) //!< Bit position for UART_RWFIFO_RXWATER.
bogdanm	82:6473597d706e	3549	#define BM_UART_RWFIFO_RXWATER (0xFFU) //!< Bit mask for UART_RWFIFO_RXWATER.
bogdanm	82:6473597d706e	3550	#define BS_UART_RWFIFO_RXWATER (8U) //!< Bit field size in bits for UART_RWFIFO_RXWATER.
bogdanm	82:6473597d706e	3551
bogdanm	82:6473597d706e	3552	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3553	//! @brief Read current value of the UART_RWFIFO_RXWATER field.
bogdanm	82:6473597d706e	3554	#define BR_UART_RWFIFO_RXWATER(x) (HW_UART_RWFIFO(x).U)
bogdanm	82:6473597d706e	3555	#endif
bogdanm	82:6473597d706e	3556
bogdanm	82:6473597d706e	3557	//! @brief Format value for bitfield UART_RWFIFO_RXWATER.
bogdanm	82:6473597d706e	3558	#define BF_UART_RWFIFO_RXWATER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_RWFIFO_RXWATER), uint8_t) & BM_UART_RWFIFO_RXWATER)
bogdanm	82:6473597d706e	3559
bogdanm	82:6473597d706e	3560	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3561	//! @brief Set the RXWATER field to a new value.
bogdanm	82:6473597d706e	3562	#define BW_UART_RWFIFO_RXWATER(x, v) (HW_UART_RWFIFO_WR(x, v))
bogdanm	82:6473597d706e	3563	#endif
bogdanm	82:6473597d706e	3564	//@}
bogdanm	82:6473597d706e	3565
bogdanm	82:6473597d706e	3566	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3567	// HW_UART_RCFIFO - UART FIFO Receive Count
bogdanm	82:6473597d706e	3568	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3569
bogdanm	82:6473597d706e	3570	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3571	/*!
bogdanm	82:6473597d706e	3572	* @brief HW_UART_RCFIFO - UART FIFO Receive Count (RO)
bogdanm	82:6473597d706e	3573	*
bogdanm	82:6473597d706e	3574	* Reset value: 0x00U
bogdanm	82:6473597d706e	3575	*
bogdanm	82:6473597d706e	3576	* This is a read only register that indicates how many datawords are currently
bogdanm	82:6473597d706e	3577	* in the receive FIFO/buffer. It may be read at any time.
bogdanm	82:6473597d706e	3578	*/
bogdanm	82:6473597d706e	3579	typedef union _hw_uart_rcfifo
bogdanm	82:6473597d706e	3580	{
bogdanm	82:6473597d706e	3581	uint8_t U;
bogdanm	82:6473597d706e	3582	struct _hw_uart_rcfifo_bitfields
bogdanm	82:6473597d706e	3583	{
bogdanm	82:6473597d706e	3584	uint8_t RXCOUNT : 8; //!< [7:0] Receive Counter
bogdanm	82:6473597d706e	3585	} B;
bogdanm	82:6473597d706e	3586	} hw_uart_rcfifo_t;
bogdanm	82:6473597d706e	3587	#endif
bogdanm	82:6473597d706e	3588
bogdanm	82:6473597d706e	3589	/*!
bogdanm	82:6473597d706e	3590	* @name Constants and macros for entire UART_RCFIFO register
bogdanm	82:6473597d706e	3591	*/
bogdanm	82:6473597d706e	3592	//@{
bogdanm	82:6473597d706e	3593	#define HW_UART_RCFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x16U)
bogdanm	82:6473597d706e	3594
bogdanm	82:6473597d706e	3595	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3596	#define HW_UART_RCFIFO(x) ((__I hw_uart_rcfifo_t ) HW_UART_RCFIFO_ADDR(x))
bogdanm	82:6473597d706e	3597	#define HW_UART_RCFIFO_RD(x) (HW_UART_RCFIFO(x).U)
bogdanm	82:6473597d706e	3598	#endif
bogdanm	82:6473597d706e	3599	//@}
bogdanm	82:6473597d706e	3600
bogdanm	82:6473597d706e	3601	/*
bogdanm	82:6473597d706e	3602	* Constants & macros for individual UART_RCFIFO bitfields
bogdanm	82:6473597d706e	3603	*/
bogdanm	82:6473597d706e	3604
bogdanm	82:6473597d706e	3605	/*!
bogdanm	82:6473597d706e	3606	* @name Register UART_RCFIFO, field RXCOUNT[7:0] (RO)
bogdanm	82:6473597d706e	3607	*
bogdanm	82:6473597d706e	3608	* The value in this register indicates the number of datawords that are in the
bogdanm	82:6473597d706e	3609	* receive FIFO/buffer. If a dataword is being received, that is, in the receive
bogdanm	82:6473597d706e	3610	* shift register, it is not included in the count. This value may be used in
bogdanm	82:6473597d706e	3611	* conjunction with PFIFO[RXFIFOSIZE] to calculate how much room is left in the
bogdanm	82:6473597d706e	3612	* receive FIFO/buffer.
bogdanm	82:6473597d706e	3613	*/
bogdanm	82:6473597d706e	3614	//@{
bogdanm	82:6473597d706e	3615	#define BP_UART_RCFIFO_RXCOUNT (0U) //!< Bit position for UART_RCFIFO_RXCOUNT.
bogdanm	82:6473597d706e	3616	#define BM_UART_RCFIFO_RXCOUNT (0xFFU) //!< Bit mask for UART_RCFIFO_RXCOUNT.
bogdanm	82:6473597d706e	3617	#define BS_UART_RCFIFO_RXCOUNT (8U) //!< Bit field size in bits for UART_RCFIFO_RXCOUNT.
bogdanm	82:6473597d706e	3618
bogdanm	82:6473597d706e	3619	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3620	//! @brief Read current value of the UART_RCFIFO_RXCOUNT field.
bogdanm	82:6473597d706e	3621	#define BR_UART_RCFIFO_RXCOUNT(x) (HW_UART_RCFIFO(x).U)
bogdanm	82:6473597d706e	3622	#endif
bogdanm	82:6473597d706e	3623	//@}
bogdanm	82:6473597d706e	3624
bogdanm	82:6473597d706e	3625	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3626	// HW_UART_C7816 - UART 7816 Control Register
bogdanm	82:6473597d706e	3627	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3628
bogdanm	82:6473597d706e	3629	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3630	/*!
bogdanm	82:6473597d706e	3631	* @brief HW_UART_C7816 - UART 7816 Control Register (RW)
bogdanm	82:6473597d706e	3632	*
bogdanm	82:6473597d706e	3633	* Reset value: 0x00U
bogdanm	82:6473597d706e	3634	*
bogdanm	82:6473597d706e	3635	* The C7816 register is the primary control register for ISO-7816 specific
bogdanm	82:6473597d706e	3636	* functionality. This register is specific to 7816 functionality and the values in
bogdanm	82:6473597d706e	3637	* this register have no effect on UART operation and should be ignored if
bogdanm	82:6473597d706e	3638	* ISO_7816E is not set/enabled. This register may be read at any time but values must
bogdanm	82:6473597d706e	3639	* be changed only when ISO_7816E is not set.
bogdanm	82:6473597d706e	3640	*/
bogdanm	82:6473597d706e	3641	typedef union _hw_uart_c7816
bogdanm	82:6473597d706e	3642	{
bogdanm	82:6473597d706e	3643	uint8_t U;
bogdanm	82:6473597d706e	3644	struct _hw_uart_c7816_bitfields
bogdanm	82:6473597d706e	3645	{
bogdanm	82:6473597d706e	3646	uint8_t ISO_7816E : 1; //!< [0] ISO-7816 Functionality Enabled
bogdanm	82:6473597d706e	3647	uint8_t TTYPE : 1; //!< [1] Transfer Type
bogdanm	82:6473597d706e	3648	uint8_t INIT : 1; //!< [2] Detect Initial Character
bogdanm	82:6473597d706e	3649	uint8_t ANACK : 1; //!< [3] Generate NACK on Error
bogdanm	82:6473597d706e	3650	uint8_t ONACK : 1; //!< [4] Generate NACK on Overflow
bogdanm	82:6473597d706e	3651	uint8_t RESERVED0 : 3; //!< [7:5]
bogdanm	82:6473597d706e	3652	} B;
bogdanm	82:6473597d706e	3653	} hw_uart_c7816_t;
bogdanm	82:6473597d706e	3654	#endif
bogdanm	82:6473597d706e	3655
bogdanm	82:6473597d706e	3656	/*!
bogdanm	82:6473597d706e	3657	* @name Constants and macros for entire UART_C7816 register
bogdanm	82:6473597d706e	3658	*/
bogdanm	82:6473597d706e	3659	//@{
bogdanm	82:6473597d706e	3660	#define HW_UART_C7816_ADDR(x) (REGS_UART_BASE(x) + 0x18U)
bogdanm	82:6473597d706e	3661
bogdanm	82:6473597d706e	3662	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3663	#define HW_UART_C7816(x) ((__IO hw_uart_c7816_t ) HW_UART_C7816_ADDR(x))
bogdanm	82:6473597d706e	3664	#define HW_UART_C7816_RD(x) (HW_UART_C7816(x).U)
bogdanm	82:6473597d706e	3665	#define HW_UART_C7816_WR(x, v) (HW_UART_C7816(x).U = (v))
bogdanm	82:6473597d706e	3666	#define HW_UART_C7816_SET(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) \| (v)))
bogdanm	82:6473597d706e	3667	#define HW_UART_C7816_CLR(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3668	#define HW_UART_C7816_TOG(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3669	#endif
bogdanm	82:6473597d706e	3670	//@}
bogdanm	82:6473597d706e	3671
bogdanm	82:6473597d706e	3672	/*
bogdanm	82:6473597d706e	3673	* Constants & macros for individual UART_C7816 bitfields
bogdanm	82:6473597d706e	3674	*/
bogdanm	82:6473597d706e	3675
bogdanm	82:6473597d706e	3676	/*!
bogdanm	82:6473597d706e	3677	* @name Register UART_C7816, field ISO_7816E[0] (RW)
bogdanm	82:6473597d706e	3678	*
bogdanm	82:6473597d706e	3679	* Indicates that the UART is operating according to the ISO-7816 protocol. This
bogdanm	82:6473597d706e	3680	* field must be modified only when no transmit or receive is occurring. If this
bogdanm	82:6473597d706e	3681	* field is changed during a data transfer, the data being transmitted or
bogdanm	82:6473597d706e	3682	* received may be transferred incorrectly.
bogdanm	82:6473597d706e	3683	*
bogdanm	82:6473597d706e	3684	* Values:
bogdanm	82:6473597d706e	3685	* - 0 - ISO-7816 functionality is turned off/not enabled.
bogdanm	82:6473597d706e	3686	* - 1 - ISO-7816 functionality is turned on/enabled.
bogdanm	82:6473597d706e	3687	*/
bogdanm	82:6473597d706e	3688	//@{
bogdanm	82:6473597d706e	3689	#define BP_UART_C7816_ISO_7816E (0U) //!< Bit position for UART_C7816_ISO_7816E.
bogdanm	82:6473597d706e	3690	#define BM_UART_C7816_ISO_7816E (0x01U) //!< Bit mask for UART_C7816_ISO_7816E.
bogdanm	82:6473597d706e	3691	#define BS_UART_C7816_ISO_7816E (1U) //!< Bit field size in bits for UART_C7816_ISO_7816E.
bogdanm	82:6473597d706e	3692
bogdanm	82:6473597d706e	3693	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3694	//! @brief Read current value of the UART_C7816_ISO_7816E field.
bogdanm	82:6473597d706e	3695	#define BR_UART_C7816_ISO_7816E(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E))
bogdanm	82:6473597d706e	3696	#endif
bogdanm	82:6473597d706e	3697
bogdanm	82:6473597d706e	3698	//! @brief Format value for bitfield UART_C7816_ISO_7816E.
bogdanm	82:6473597d706e	3699	#define BF_UART_C7816_ISO_7816E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ISO_7816E), uint8_t) & BM_UART_C7816_ISO_7816E)
bogdanm	82:6473597d706e	3700
bogdanm	82:6473597d706e	3701	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3702	//! @brief Set the ISO_7816E field to a new value.
bogdanm	82:6473597d706e	3703	#define BW_UART_C7816_ISO_7816E(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E) = (v))
bogdanm	82:6473597d706e	3704	#endif
bogdanm	82:6473597d706e	3705	//@}
bogdanm	82:6473597d706e	3706
bogdanm	82:6473597d706e	3707	/*!
bogdanm	82:6473597d706e	3708	* @name Register UART_C7816, field TTYPE[1] (RW)
bogdanm	82:6473597d706e	3709	*
bogdanm	82:6473597d706e	3710	* Indicates the transfer protocol being used. See ISO-7816 / smartcard support
bogdanm	82:6473597d706e	3711	* for more details.
bogdanm	82:6473597d706e	3712	*
bogdanm	82:6473597d706e	3713	* Values:
bogdanm	82:6473597d706e	3714	* - 0 - T = 0 per the ISO-7816 specification.
bogdanm	82:6473597d706e	3715	* - 1 - T = 1 per the ISO-7816 specification.
bogdanm	82:6473597d706e	3716	*/
bogdanm	82:6473597d706e	3717	//@{
bogdanm	82:6473597d706e	3718	#define BP_UART_C7816_TTYPE (1U) //!< Bit position for UART_C7816_TTYPE.
bogdanm	82:6473597d706e	3719	#define BM_UART_C7816_TTYPE (0x02U) //!< Bit mask for UART_C7816_TTYPE.
bogdanm	82:6473597d706e	3720	#define BS_UART_C7816_TTYPE (1U) //!< Bit field size in bits for UART_C7816_TTYPE.
bogdanm	82:6473597d706e	3721
bogdanm	82:6473597d706e	3722	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3723	//! @brief Read current value of the UART_C7816_TTYPE field.
bogdanm	82:6473597d706e	3724	#define BR_UART_C7816_TTYPE(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE))
bogdanm	82:6473597d706e	3725	#endif
bogdanm	82:6473597d706e	3726
bogdanm	82:6473597d706e	3727	//! @brief Format value for bitfield UART_C7816_TTYPE.
bogdanm	82:6473597d706e	3728	#define BF_UART_C7816_TTYPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_TTYPE), uint8_t) & BM_UART_C7816_TTYPE)
bogdanm	82:6473597d706e	3729
bogdanm	82:6473597d706e	3730	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3731	//! @brief Set the TTYPE field to a new value.
bogdanm	82:6473597d706e	3732	#define BW_UART_C7816_TTYPE(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE) = (v))
bogdanm	82:6473597d706e	3733	#endif
bogdanm	82:6473597d706e	3734	//@}
bogdanm	82:6473597d706e	3735
bogdanm	82:6473597d706e	3736	/*!
bogdanm	82:6473597d706e	3737	* @name Register UART_C7816, field INIT[2] (RW)
bogdanm	82:6473597d706e	3738	*
bogdanm	82:6473597d706e	3739	* When this field is set, all received characters are searched for a valid
bogdanm	82:6473597d706e	3740	* initial character. If an invalid initial character is identified, and ANACK is
bogdanm	82:6473597d706e	3741	* set, a NACK is sent. All received data is discarded and error flags blocked
bogdanm	82:6473597d706e	3742	* (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV])
bogdanm	82:6473597d706e	3743	* until a valid initial character is detected. Upon detecting a valid initial
bogdanm	82:6473597d706e	3744	* character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are
bogdanm	82:6473597d706e	3745	* automatically updated to reflect the initial character that was received. The
bogdanm	82:6473597d706e	3746	* actual INIT data value is not stored in the receive buffer. Additionally, upon
bogdanm	82:6473597d706e	3747	* detection of a valid initial character, IS7816[INITD] is set and an interrupt
bogdanm	82:6473597d706e	3748	* issued as programmed by IE7816[INITDE]. When a valid initial character is
bogdanm	82:6473597d706e	3749	* detected, INIT is automatically cleared. This Initial Character Detect feature is
bogdanm	82:6473597d706e	3750	* supported only in T = 0 protocol mode.
bogdanm	82:6473597d706e	3751	*
bogdanm	82:6473597d706e	3752	* Values:
bogdanm	82:6473597d706e	3753	* - 0 - Normal operating mode. Receiver does not seek to identify initial
bogdanm	82:6473597d706e	3754	* character.
bogdanm	82:6473597d706e	3755	* - 1 - Receiver searches for initial character.
bogdanm	82:6473597d706e	3756	*/
bogdanm	82:6473597d706e	3757	//@{
bogdanm	82:6473597d706e	3758	#define BP_UART_C7816_INIT (2U) //!< Bit position for UART_C7816_INIT.
bogdanm	82:6473597d706e	3759	#define BM_UART_C7816_INIT (0x04U) //!< Bit mask for UART_C7816_INIT.
bogdanm	82:6473597d706e	3760	#define BS_UART_C7816_INIT (1U) //!< Bit field size in bits for UART_C7816_INIT.
bogdanm	82:6473597d706e	3761
bogdanm	82:6473597d706e	3762	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3763	//! @brief Read current value of the UART_C7816_INIT field.
bogdanm	82:6473597d706e	3764	#define BR_UART_C7816_INIT(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT))
bogdanm	82:6473597d706e	3765	#endif
bogdanm	82:6473597d706e	3766
bogdanm	82:6473597d706e	3767	//! @brief Format value for bitfield UART_C7816_INIT.
bogdanm	82:6473597d706e	3768	#define BF_UART_C7816_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_INIT), uint8_t) & BM_UART_C7816_INIT)
bogdanm	82:6473597d706e	3769
bogdanm	82:6473597d706e	3770	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3771	//! @brief Set the INIT field to a new value.
bogdanm	82:6473597d706e	3772	#define BW_UART_C7816_INIT(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT) = (v))
bogdanm	82:6473597d706e	3773	#endif
bogdanm	82:6473597d706e	3774	//@}
bogdanm	82:6473597d706e	3775
bogdanm	82:6473597d706e	3776	/*!
bogdanm	82:6473597d706e	3777	* @name Register UART_C7816, field ANACK[3] (RW)
bogdanm	82:6473597d706e	3778	*
bogdanm	82:6473597d706e	3779	* When this field is set, the receiver automatically generates a NACK response
bogdanm	82:6473597d706e	3780	* if a parity error occurs or if INIT is set and an invalid initial character is
bogdanm	82:6473597d706e	3781	* detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
bogdanm	82:6473597d706e	3782	* attempts to retransmit the data indefinitely. To stop retransmission attempts,
bogdanm	82:6473597d706e	3783	* clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
bogdanm	82:6473597d706e	3784	*
bogdanm	82:6473597d706e	3785	* Values:
bogdanm	82:6473597d706e	3786	* - 0 - No NACK is automatically generated.
bogdanm	82:6473597d706e	3787	* - 1 - A NACK is automatically generated if a parity error is detected or if
bogdanm	82:6473597d706e	3788	* an invalid initial character is detected.
bogdanm	82:6473597d706e	3789	*/
bogdanm	82:6473597d706e	3790	//@{
bogdanm	82:6473597d706e	3791	#define BP_UART_C7816_ANACK (3U) //!< Bit position for UART_C7816_ANACK.
bogdanm	82:6473597d706e	3792	#define BM_UART_C7816_ANACK (0x08U) //!< Bit mask for UART_C7816_ANACK.
bogdanm	82:6473597d706e	3793	#define BS_UART_C7816_ANACK (1U) //!< Bit field size in bits for UART_C7816_ANACK.
bogdanm	82:6473597d706e	3794
bogdanm	82:6473597d706e	3795	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3796	//! @brief Read current value of the UART_C7816_ANACK field.
bogdanm	82:6473597d706e	3797	#define BR_UART_C7816_ANACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK))
bogdanm	82:6473597d706e	3798	#endif
bogdanm	82:6473597d706e	3799
bogdanm	82:6473597d706e	3800	//! @brief Format value for bitfield UART_C7816_ANACK.
bogdanm	82:6473597d706e	3801	#define BF_UART_C7816_ANACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ANACK), uint8_t) & BM_UART_C7816_ANACK)
bogdanm	82:6473597d706e	3802
bogdanm	82:6473597d706e	3803	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3804	//! @brief Set the ANACK field to a new value.
bogdanm	82:6473597d706e	3805	#define BW_UART_C7816_ANACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK) = (v))
bogdanm	82:6473597d706e	3806	#endif
bogdanm	82:6473597d706e	3807	//@}
bogdanm	82:6473597d706e	3808
bogdanm	82:6473597d706e	3809	/*!
bogdanm	82:6473597d706e	3810	* @name Register UART_C7816, field ONACK[4] (RW)
bogdanm	82:6473597d706e	3811	*
bogdanm	82:6473597d706e	3812	* When this field is set, the receiver automatically generates a NACK response
bogdanm	82:6473597d706e	3813	* if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
bogdanm	82:6473597d706e	3814	* this results in the transmitter resending the packet that overflowed until the
bogdanm	82:6473597d706e	3815	* retransmit threshold for that transmitter is reached. A NACK is generated only
bogdanm	82:6473597d706e	3816	* if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
bogdanm	82:6473597d706e	3817	* considerations
bogdanm	82:6473597d706e	3818	*
bogdanm	82:6473597d706e	3819	* Values:
bogdanm	82:6473597d706e	3820	* - 0 - The received data does not generate a NACK when the receipt of the data
bogdanm	82:6473597d706e	3821	* results in an overflow event.
bogdanm	82:6473597d706e	3822	* - 1 - If the receiver buffer overflows, a NACK is automatically sent on a
bogdanm	82:6473597d706e	3823	* received character.
bogdanm	82:6473597d706e	3824	*/
bogdanm	82:6473597d706e	3825	//@{
bogdanm	82:6473597d706e	3826	#define BP_UART_C7816_ONACK (4U) //!< Bit position for UART_C7816_ONACK.
bogdanm	82:6473597d706e	3827	#define BM_UART_C7816_ONACK (0x10U) //!< Bit mask for UART_C7816_ONACK.
bogdanm	82:6473597d706e	3828	#define BS_UART_C7816_ONACK (1U) //!< Bit field size in bits for UART_C7816_ONACK.
bogdanm	82:6473597d706e	3829
bogdanm	82:6473597d706e	3830	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3831	//! @brief Read current value of the UART_C7816_ONACK field.
bogdanm	82:6473597d706e	3832	#define BR_UART_C7816_ONACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK))
bogdanm	82:6473597d706e	3833	#endif
bogdanm	82:6473597d706e	3834
bogdanm	82:6473597d706e	3835	//! @brief Format value for bitfield UART_C7816_ONACK.
bogdanm	82:6473597d706e	3836	#define BF_UART_C7816_ONACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ONACK), uint8_t) & BM_UART_C7816_ONACK)
bogdanm	82:6473597d706e	3837
bogdanm	82:6473597d706e	3838	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3839	//! @brief Set the ONACK field to a new value.
bogdanm	82:6473597d706e	3840	#define BW_UART_C7816_ONACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK) = (v))
bogdanm	82:6473597d706e	3841	#endif
bogdanm	82:6473597d706e	3842	//@}
bogdanm	82:6473597d706e	3843
bogdanm	82:6473597d706e	3844	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3845	// HW_UART_IE7816 - UART 7816 Interrupt Enable Register
bogdanm	82:6473597d706e	3846	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3847
bogdanm	82:6473597d706e	3848	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3849	/*!
bogdanm	82:6473597d706e	3850	* @brief HW_UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
bogdanm	82:6473597d706e	3851	*
bogdanm	82:6473597d706e	3852	* Reset value: 0x00U
bogdanm	82:6473597d706e	3853	*
bogdanm	82:6473597d706e	3854	* The IE7816 register controls which flags result in an interrupt being issued.
bogdanm	82:6473597d706e	3855	* This register is specific to 7816 functionality, the corresponding flags that
bogdanm	82:6473597d706e	3856	* drive the interrupts are not asserted when 7816E is not set/enabled. However,
bogdanm	82:6473597d706e	3857	* these flags may remain set if they are asserted while 7816E was set and not
bogdanm	82:6473597d706e	3858	* subsequently cleared. This register may be read or written to at any time.
bogdanm	82:6473597d706e	3859	*/
bogdanm	82:6473597d706e	3860	typedef union _hw_uart_ie7816
bogdanm	82:6473597d706e	3861	{
bogdanm	82:6473597d706e	3862	uint8_t U;
bogdanm	82:6473597d706e	3863	struct _hw_uart_ie7816_bitfields
bogdanm	82:6473597d706e	3864	{
bogdanm	82:6473597d706e	3865	uint8_t RXTE : 1; //!< [0] Receive Threshold Exceeded Interrupt Enable
bogdanm	82:6473597d706e	3866	uint8_t TXTE : 1; //!< [1] Transmit Threshold Exceeded Interrupt
bogdanm	82:6473597d706e	3867	//! Enable
bogdanm	82:6473597d706e	3868	uint8_t GTVE : 1; //!< [2] Guard Timer Violated Interrupt Enable
bogdanm	82:6473597d706e	3869	uint8_t RESERVED0 : 1; //!< [3]
bogdanm	82:6473597d706e	3870	uint8_t INITDE : 1; //!< [4] Initial Character Detected Interrupt
bogdanm	82:6473597d706e	3871	//! Enable
bogdanm	82:6473597d706e	3872	uint8_t BWTE : 1; //!< [5] Block Wait Timer Interrupt Enable
bogdanm	82:6473597d706e	3873	uint8_t CWTE : 1; //!< [6] Character Wait Timer Interrupt Enable
bogdanm	82:6473597d706e	3874	uint8_t WTE : 1; //!< [7] Wait Timer Interrupt Enable
bogdanm	82:6473597d706e	3875	} B;
bogdanm	82:6473597d706e	3876	} hw_uart_ie7816_t;
bogdanm	82:6473597d706e	3877	#endif
bogdanm	82:6473597d706e	3878
bogdanm	82:6473597d706e	3879	/*!
bogdanm	82:6473597d706e	3880	* @name Constants and macros for entire UART_IE7816 register
bogdanm	82:6473597d706e	3881	*/
bogdanm	82:6473597d706e	3882	//@{
bogdanm	82:6473597d706e	3883	#define HW_UART_IE7816_ADDR(x) (REGS_UART_BASE(x) + 0x19U)
bogdanm	82:6473597d706e	3884
bogdanm	82:6473597d706e	3885	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3886	#define HW_UART_IE7816(x) ((__IO hw_uart_ie7816_t ) HW_UART_IE7816_ADDR(x))
bogdanm	82:6473597d706e	3887	#define HW_UART_IE7816_RD(x) (HW_UART_IE7816(x).U)
bogdanm	82:6473597d706e	3888	#define HW_UART_IE7816_WR(x, v) (HW_UART_IE7816(x).U = (v))
bogdanm	82:6473597d706e	3889	#define HW_UART_IE7816_SET(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) \| (v)))
bogdanm	82:6473597d706e	3890	#define HW_UART_IE7816_CLR(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3891	#define HW_UART_IE7816_TOG(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3892	#endif
bogdanm	82:6473597d706e	3893	//@}
bogdanm	82:6473597d706e	3894
bogdanm	82:6473597d706e	3895	/*
bogdanm	82:6473597d706e	3896	* Constants & macros for individual UART_IE7816 bitfields
bogdanm	82:6473597d706e	3897	*/
bogdanm	82:6473597d706e	3898
bogdanm	82:6473597d706e	3899	/*!
bogdanm	82:6473597d706e	3900	* @name Register UART_IE7816, field RXTE[0] (RW)
bogdanm	82:6473597d706e	3901	*
bogdanm	82:6473597d706e	3902	* Values:
bogdanm	82:6473597d706e	3903	* - 0 - The assertion of IS7816[RXT] does not result in the generation of an
bogdanm	82:6473597d706e	3904	* interrupt.
bogdanm	82:6473597d706e	3905	* - 1 - The assertion of IS7816[RXT] results in the generation of an interrupt.
bogdanm	82:6473597d706e	3906	*/
bogdanm	82:6473597d706e	3907	//@{
bogdanm	82:6473597d706e	3908	#define BP_UART_IE7816_RXTE (0U) //!< Bit position for UART_IE7816_RXTE.
bogdanm	82:6473597d706e	3909	#define BM_UART_IE7816_RXTE (0x01U) //!< Bit mask for UART_IE7816_RXTE.
bogdanm	82:6473597d706e	3910	#define BS_UART_IE7816_RXTE (1U) //!< Bit field size in bits for UART_IE7816_RXTE.
bogdanm	82:6473597d706e	3911
bogdanm	82:6473597d706e	3912	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3913	//! @brief Read current value of the UART_IE7816_RXTE field.
bogdanm	82:6473597d706e	3914	#define BR_UART_IE7816_RXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE))
bogdanm	82:6473597d706e	3915	#endif
bogdanm	82:6473597d706e	3916
bogdanm	82:6473597d706e	3917	//! @brief Format value for bitfield UART_IE7816_RXTE.
bogdanm	82:6473597d706e	3918	#define BF_UART_IE7816_RXTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_RXTE), uint8_t) & BM_UART_IE7816_RXTE)
bogdanm	82:6473597d706e	3919
bogdanm	82:6473597d706e	3920	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3921	//! @brief Set the RXTE field to a new value.
bogdanm	82:6473597d706e	3922	#define BW_UART_IE7816_RXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE) = (v))
bogdanm	82:6473597d706e	3923	#endif
bogdanm	82:6473597d706e	3924	//@}
bogdanm	82:6473597d706e	3925
bogdanm	82:6473597d706e	3926	/*!
bogdanm	82:6473597d706e	3927	* @name Register UART_IE7816, field TXTE[1] (RW)
bogdanm	82:6473597d706e	3928	*
bogdanm	82:6473597d706e	3929	* Values:
bogdanm	82:6473597d706e	3930	* - 0 - The assertion of IS7816[TXT] does not result in the generation of an
bogdanm	82:6473597d706e	3931	* interrupt.
bogdanm	82:6473597d706e	3932	* - 1 - The assertion of IS7816[TXT] results in the generation of an interrupt.
bogdanm	82:6473597d706e	3933	*/
bogdanm	82:6473597d706e	3934	//@{
bogdanm	82:6473597d706e	3935	#define BP_UART_IE7816_TXTE (1U) //!< Bit position for UART_IE7816_TXTE.
bogdanm	82:6473597d706e	3936	#define BM_UART_IE7816_TXTE (0x02U) //!< Bit mask for UART_IE7816_TXTE.
bogdanm	82:6473597d706e	3937	#define BS_UART_IE7816_TXTE (1U) //!< Bit field size in bits for UART_IE7816_TXTE.
bogdanm	82:6473597d706e	3938
bogdanm	82:6473597d706e	3939	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3940	//! @brief Read current value of the UART_IE7816_TXTE field.
bogdanm	82:6473597d706e	3941	#define BR_UART_IE7816_TXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE))
bogdanm	82:6473597d706e	3942	#endif
bogdanm	82:6473597d706e	3943
bogdanm	82:6473597d706e	3944	//! @brief Format value for bitfield UART_IE7816_TXTE.
bogdanm	82:6473597d706e	3945	#define BF_UART_IE7816_TXTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_TXTE), uint8_t) & BM_UART_IE7816_TXTE)
bogdanm	82:6473597d706e	3946
bogdanm	82:6473597d706e	3947	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3948	//! @brief Set the TXTE field to a new value.
bogdanm	82:6473597d706e	3949	#define BW_UART_IE7816_TXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE) = (v))
bogdanm	82:6473597d706e	3950	#endif
bogdanm	82:6473597d706e	3951	//@}
bogdanm	82:6473597d706e	3952
bogdanm	82:6473597d706e	3953	/*!
bogdanm	82:6473597d706e	3954	* @name Register UART_IE7816, field GTVE[2] (RW)
bogdanm	82:6473597d706e	3955	*
bogdanm	82:6473597d706e	3956	* Values:
bogdanm	82:6473597d706e	3957	* - 0 - The assertion of IS7816[GTV] does not result in the generation of an
bogdanm	82:6473597d706e	3958	* interrupt.
bogdanm	82:6473597d706e	3959	* - 1 - The assertion of IS7816[GTV] results in the generation of an interrupt.
bogdanm	82:6473597d706e	3960	*/
bogdanm	82:6473597d706e	3961	//@{
bogdanm	82:6473597d706e	3962	#define BP_UART_IE7816_GTVE (2U) //!< Bit position for UART_IE7816_GTVE.
bogdanm	82:6473597d706e	3963	#define BM_UART_IE7816_GTVE (0x04U) //!< Bit mask for UART_IE7816_GTVE.
bogdanm	82:6473597d706e	3964	#define BS_UART_IE7816_GTVE (1U) //!< Bit field size in bits for UART_IE7816_GTVE.
bogdanm	82:6473597d706e	3965
bogdanm	82:6473597d706e	3966	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3967	//! @brief Read current value of the UART_IE7816_GTVE field.
bogdanm	82:6473597d706e	3968	#define BR_UART_IE7816_GTVE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE))
bogdanm	82:6473597d706e	3969	#endif
bogdanm	82:6473597d706e	3970
bogdanm	82:6473597d706e	3971	//! @brief Format value for bitfield UART_IE7816_GTVE.
bogdanm	82:6473597d706e	3972	#define BF_UART_IE7816_GTVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_GTVE), uint8_t) & BM_UART_IE7816_GTVE)
bogdanm	82:6473597d706e	3973
bogdanm	82:6473597d706e	3974	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3975	//! @brief Set the GTVE field to a new value.
bogdanm	82:6473597d706e	3976	#define BW_UART_IE7816_GTVE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE) = (v))
bogdanm	82:6473597d706e	3977	#endif
bogdanm	82:6473597d706e	3978	//@}
bogdanm	82:6473597d706e	3979
bogdanm	82:6473597d706e	3980	/*!
bogdanm	82:6473597d706e	3981	* @name Register UART_IE7816, field INITDE[4] (RW)
bogdanm	82:6473597d706e	3982	*
bogdanm	82:6473597d706e	3983	* Values:
bogdanm	82:6473597d706e	3984	* - 0 - The assertion of IS7816[INITD] does not result in the generation of an
bogdanm	82:6473597d706e	3985	* interrupt.
bogdanm	82:6473597d706e	3986	* - 1 - The assertion of IS7816[INITD] results in the generation of an
bogdanm	82:6473597d706e	3987	* interrupt.
bogdanm	82:6473597d706e	3988	*/
bogdanm	82:6473597d706e	3989	//@{
bogdanm	82:6473597d706e	3990	#define BP_UART_IE7816_INITDE (4U) //!< Bit position for UART_IE7816_INITDE.
bogdanm	82:6473597d706e	3991	#define BM_UART_IE7816_INITDE (0x10U) //!< Bit mask for UART_IE7816_INITDE.
bogdanm	82:6473597d706e	3992	#define BS_UART_IE7816_INITDE (1U) //!< Bit field size in bits for UART_IE7816_INITDE.
bogdanm	82:6473597d706e	3993
bogdanm	82:6473597d706e	3994	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3995	//! @brief Read current value of the UART_IE7816_INITDE field.
bogdanm	82:6473597d706e	3996	#define BR_UART_IE7816_INITDE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE))
bogdanm	82:6473597d706e	3997	#endif
bogdanm	82:6473597d706e	3998
bogdanm	82:6473597d706e	3999	//! @brief Format value for bitfield UART_IE7816_INITDE.
bogdanm	82:6473597d706e	4000	#define BF_UART_IE7816_INITDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_INITDE), uint8_t) & BM_UART_IE7816_INITDE)
bogdanm	82:6473597d706e	4001
bogdanm	82:6473597d706e	4002	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4003	//! @brief Set the INITDE field to a new value.
bogdanm	82:6473597d706e	4004	#define BW_UART_IE7816_INITDE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE) = (v))
bogdanm	82:6473597d706e	4005	#endif
bogdanm	82:6473597d706e	4006	//@}
bogdanm	82:6473597d706e	4007
bogdanm	82:6473597d706e	4008	/*!
bogdanm	82:6473597d706e	4009	* @name Register UART_IE7816, field BWTE[5] (RW)
bogdanm	82:6473597d706e	4010	*
bogdanm	82:6473597d706e	4011	* Values:
bogdanm	82:6473597d706e	4012	* - 0 - The assertion of IS7816[BWT] does not result in the generation of an
bogdanm	82:6473597d706e	4013	* interrupt.
bogdanm	82:6473597d706e	4014	* - 1 - The assertion of IS7816[BWT] results in the generation of an interrupt.
bogdanm	82:6473597d706e	4015	*/
bogdanm	82:6473597d706e	4016	//@{
bogdanm	82:6473597d706e	4017	#define BP_UART_IE7816_BWTE (5U) //!< Bit position for UART_IE7816_BWTE.
bogdanm	82:6473597d706e	4018	#define BM_UART_IE7816_BWTE (0x20U) //!< Bit mask for UART_IE7816_BWTE.
bogdanm	82:6473597d706e	4019	#define BS_UART_IE7816_BWTE (1U) //!< Bit field size in bits for UART_IE7816_BWTE.
bogdanm	82:6473597d706e	4020
bogdanm	82:6473597d706e	4021	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4022	//! @brief Read current value of the UART_IE7816_BWTE field.
bogdanm	82:6473597d706e	4023	#define BR_UART_IE7816_BWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE))
bogdanm	82:6473597d706e	4024	#endif
bogdanm	82:6473597d706e	4025
bogdanm	82:6473597d706e	4026	//! @brief Format value for bitfield UART_IE7816_BWTE.
bogdanm	82:6473597d706e	4027	#define BF_UART_IE7816_BWTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_BWTE), uint8_t) & BM_UART_IE7816_BWTE)
bogdanm	82:6473597d706e	4028
bogdanm	82:6473597d706e	4029	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4030	//! @brief Set the BWTE field to a new value.
bogdanm	82:6473597d706e	4031	#define BW_UART_IE7816_BWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE) = (v))
bogdanm	82:6473597d706e	4032	#endif
bogdanm	82:6473597d706e	4033	//@}
bogdanm	82:6473597d706e	4034
bogdanm	82:6473597d706e	4035	/*!
bogdanm	82:6473597d706e	4036	* @name Register UART_IE7816, field CWTE[6] (RW)
bogdanm	82:6473597d706e	4037	*
bogdanm	82:6473597d706e	4038	* Values:
bogdanm	82:6473597d706e	4039	* - 0 - The assertion of IS7816[CWT] does not result in the generation of an
bogdanm	82:6473597d706e	4040	* interrupt.
bogdanm	82:6473597d706e	4041	* - 1 - The assertion of IS7816[CWT] results in the generation of an interrupt.
bogdanm	82:6473597d706e	4042	*/
bogdanm	82:6473597d706e	4043	//@{
bogdanm	82:6473597d706e	4044	#define BP_UART_IE7816_CWTE (6U) //!< Bit position for UART_IE7816_CWTE.
bogdanm	82:6473597d706e	4045	#define BM_UART_IE7816_CWTE (0x40U) //!< Bit mask for UART_IE7816_CWTE.
bogdanm	82:6473597d706e	4046	#define BS_UART_IE7816_CWTE (1U) //!< Bit field size in bits for UART_IE7816_CWTE.
bogdanm	82:6473597d706e	4047
bogdanm	82:6473597d706e	4048	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4049	//! @brief Read current value of the UART_IE7816_CWTE field.
bogdanm	82:6473597d706e	4050	#define BR_UART_IE7816_CWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE))
bogdanm	82:6473597d706e	4051	#endif
bogdanm	82:6473597d706e	4052
bogdanm	82:6473597d706e	4053	//! @brief Format value for bitfield UART_IE7816_CWTE.
bogdanm	82:6473597d706e	4054	#define BF_UART_IE7816_CWTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_CWTE), uint8_t) & BM_UART_IE7816_CWTE)
bogdanm	82:6473597d706e	4055
bogdanm	82:6473597d706e	4056	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4057	//! @brief Set the CWTE field to a new value.
bogdanm	82:6473597d706e	4058	#define BW_UART_IE7816_CWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE) = (v))
bogdanm	82:6473597d706e	4059	#endif
bogdanm	82:6473597d706e	4060	//@}
bogdanm	82:6473597d706e	4061
bogdanm	82:6473597d706e	4062	/*!
bogdanm	82:6473597d706e	4063	* @name Register UART_IE7816, field WTE[7] (RW)
bogdanm	82:6473597d706e	4064	*
bogdanm	82:6473597d706e	4065	* Values:
bogdanm	82:6473597d706e	4066	* - 0 - The assertion of IS7816[WT] does not result in the generation of an
bogdanm	82:6473597d706e	4067	* interrupt.
bogdanm	82:6473597d706e	4068	* - 1 - The assertion of IS7816[WT] results in the generation of an interrupt.
bogdanm	82:6473597d706e	4069	*/
bogdanm	82:6473597d706e	4070	//@{
bogdanm	82:6473597d706e	4071	#define BP_UART_IE7816_WTE (7U) //!< Bit position for UART_IE7816_WTE.
bogdanm	82:6473597d706e	4072	#define BM_UART_IE7816_WTE (0x80U) //!< Bit mask for UART_IE7816_WTE.
bogdanm	82:6473597d706e	4073	#define BS_UART_IE7816_WTE (1U) //!< Bit field size in bits for UART_IE7816_WTE.
bogdanm	82:6473597d706e	4074
bogdanm	82:6473597d706e	4075	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4076	//! @brief Read current value of the UART_IE7816_WTE field.
bogdanm	82:6473597d706e	4077	#define BR_UART_IE7816_WTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE))
bogdanm	82:6473597d706e	4078	#endif
bogdanm	82:6473597d706e	4079
bogdanm	82:6473597d706e	4080	//! @brief Format value for bitfield UART_IE7816_WTE.
bogdanm	82:6473597d706e	4081	#define BF_UART_IE7816_WTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_WTE), uint8_t) & BM_UART_IE7816_WTE)
bogdanm	82:6473597d706e	4082
bogdanm	82:6473597d706e	4083	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4084	//! @brief Set the WTE field to a new value.
bogdanm	82:6473597d706e	4085	#define BW_UART_IE7816_WTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE) = (v))
bogdanm	82:6473597d706e	4086	#endif
bogdanm	82:6473597d706e	4087	//@}
bogdanm	82:6473597d706e	4088
bogdanm	82:6473597d706e	4089	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4090	// HW_UART_IS7816 - UART 7816 Interrupt Status Register
bogdanm	82:6473597d706e	4091	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4092
bogdanm	82:6473597d706e	4093	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4094	/*!
bogdanm	82:6473597d706e	4095	* @brief HW_UART_IS7816 - UART 7816 Interrupt Status Register (RW)
bogdanm	82:6473597d706e	4096	*
bogdanm	82:6473597d706e	4097	* Reset value: 0x00U
bogdanm	82:6473597d706e	4098	*
bogdanm	82:6473597d706e	4099	* The IS7816 register provides a mechanism to read and clear the interrupt
bogdanm	82:6473597d706e	4100	* flags. All flags/interrupts are cleared by writing a 1 to the field location.
bogdanm	82:6473597d706e	4101	* Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
bogdanm	82:6473597d706e	4102	* the flag condition that occurred since the last time the bit was cleared, not
bogdanm	82:6473597d706e	4103	* that the condition currently exists. The status flags are set regardless of
bogdanm	82:6473597d706e	4104	* whether the corresponding field in the IE7816 is set or cleared. The IE7816
bogdanm	82:6473597d706e	4105	* controls only if an interrupt is issued to the host processor. This register is
bogdanm	82:6473597d706e	4106	* specific to 7816 functionality and the values in this register have no affect on
bogdanm	82:6473597d706e	4107	* UART operation and should be ignored if 7816E is not set/enabled. This
bogdanm	82:6473597d706e	4108	* register may be read or written at anytime.
bogdanm	82:6473597d706e	4109	*/
bogdanm	82:6473597d706e	4110	typedef union _hw_uart_is7816
bogdanm	82:6473597d706e	4111	{
bogdanm	82:6473597d706e	4112	uint8_t U;
bogdanm	82:6473597d706e	4113	struct _hw_uart_is7816_bitfields
bogdanm	82:6473597d706e	4114	{
bogdanm	82:6473597d706e	4115	uint8_t RXT : 1; //!< [0] Receive Threshold Exceeded Interrupt
bogdanm	82:6473597d706e	4116	uint8_t TXT : 1; //!< [1] Transmit Threshold Exceeded Interrupt
bogdanm	82:6473597d706e	4117	uint8_t GTV : 1; //!< [2] Guard Timer Violated Interrupt
bogdanm	82:6473597d706e	4118	uint8_t RESERVED0 : 1; //!< [3]
bogdanm	82:6473597d706e	4119	uint8_t INITD : 1; //!< [4] Initial Character Detected Interrupt
bogdanm	82:6473597d706e	4120	uint8_t BWT : 1; //!< [5] Block Wait Timer Interrupt
bogdanm	82:6473597d706e	4121	uint8_t CWT : 1; //!< [6] Character Wait Timer Interrupt
bogdanm	82:6473597d706e	4122	uint8_t WT : 1; //!< [7] Wait Timer Interrupt
bogdanm	82:6473597d706e	4123	} B;
bogdanm	82:6473597d706e	4124	} hw_uart_is7816_t;
bogdanm	82:6473597d706e	4125	#endif
bogdanm	82:6473597d706e	4126
bogdanm	82:6473597d706e	4127	/*!
bogdanm	82:6473597d706e	4128	* @name Constants and macros for entire UART_IS7816 register
bogdanm	82:6473597d706e	4129	*/
bogdanm	82:6473597d706e	4130	//@{
bogdanm	82:6473597d706e	4131	#define HW_UART_IS7816_ADDR(x) (REGS_UART_BASE(x) + 0x1AU)
bogdanm	82:6473597d706e	4132
bogdanm	82:6473597d706e	4133	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4134	#define HW_UART_IS7816(x) ((__IO hw_uart_is7816_t ) HW_UART_IS7816_ADDR(x))
bogdanm	82:6473597d706e	4135	#define HW_UART_IS7816_RD(x) (HW_UART_IS7816(x).U)
bogdanm	82:6473597d706e	4136	#define HW_UART_IS7816_WR(x, v) (HW_UART_IS7816(x).U = (v))
bogdanm	82:6473597d706e	4137	#define HW_UART_IS7816_SET(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) \| (v)))
bogdanm	82:6473597d706e	4138	#define HW_UART_IS7816_CLR(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) & ~(v)))
bogdanm	82:6473597d706e	4139	#define HW_UART_IS7816_TOG(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) ^ (v)))
bogdanm	82:6473597d706e	4140	#endif
bogdanm	82:6473597d706e	4141	//@}
bogdanm	82:6473597d706e	4142
bogdanm	82:6473597d706e	4143	/*
bogdanm	82:6473597d706e	4144	* Constants & macros for individual UART_IS7816 bitfields
bogdanm	82:6473597d706e	4145	*/
bogdanm	82:6473597d706e	4146
bogdanm	82:6473597d706e	4147	/*!
bogdanm	82:6473597d706e	4148	* @name Register UART_IS7816, field RXT[0] (W1C)
bogdanm	82:6473597d706e	4149	*
bogdanm	82:6473597d706e	4150	* Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
bogdanm	82:6473597d706e	4151	* generated in response to parity errors on received data. This flag requires ANACK
bogdanm	82:6473597d706e	4152	* to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
bogdanm	82:6473597d706e	4153	* Clearing this field also resets the counter keeping track of consecutive NACKS. The
bogdanm	82:6473597d706e	4154	* UART will continue to attempt to receive data regardless of whether this flag
bogdanm	82:6473597d706e	4155	* is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
bogdanm	82:6473597d706e	4156	* or packet is received without needing to issue a NACK, the internal NACK
bogdanm	82:6473597d706e	4157	* detection counter is cleared and the count restarts from zero on the next
bogdanm	82:6473597d706e	4158	* transmitted NACK. This interrupt is cleared by writing 1.
bogdanm	82:6473597d706e	4159	*
bogdanm	82:6473597d706e	4160	* Values:
bogdanm	82:6473597d706e	4161	* - 0 - The number of consecutive NACKS generated as a result of parity errors
bogdanm	82:6473597d706e	4162	* and buffer overruns is less than or equal to the value in
bogdanm	82:6473597d706e	4163	* ET7816[RXTHRESHOLD].
bogdanm	82:6473597d706e	4164	* - 1 - The number of consecutive NACKS generated as a result of parity errors
bogdanm	82:6473597d706e	4165	* and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
bogdanm	82:6473597d706e	4166	*/
bogdanm	82:6473597d706e	4167	//@{
bogdanm	82:6473597d706e	4168	#define BP_UART_IS7816_RXT (0U) //!< Bit position for UART_IS7816_RXT.
bogdanm	82:6473597d706e	4169	#define BM_UART_IS7816_RXT (0x01U) //!< Bit mask for UART_IS7816_RXT.
bogdanm	82:6473597d706e	4170	#define BS_UART_IS7816_RXT (1U) //!< Bit field size in bits for UART_IS7816_RXT.
bogdanm	82:6473597d706e	4171
bogdanm	82:6473597d706e	4172	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4173	//! @brief Read current value of the UART_IS7816_RXT field.
bogdanm	82:6473597d706e	4174	#define BR_UART_IS7816_RXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT))
bogdanm	82:6473597d706e	4175	#endif
bogdanm	82:6473597d706e	4176
bogdanm	82:6473597d706e	4177	//! @brief Format value for bitfield UART_IS7816_RXT.
bogdanm	82:6473597d706e	4178	#define BF_UART_IS7816_RXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_RXT), uint8_t) & BM_UART_IS7816_RXT)
bogdanm	82:6473597d706e	4179
bogdanm	82:6473597d706e	4180	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4181	//! @brief Set the RXT field to a new value.
bogdanm	82:6473597d706e	4182	#define BW_UART_IS7816_RXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT) = (v))
bogdanm	82:6473597d706e	4183	#endif
bogdanm	82:6473597d706e	4184	//@}
bogdanm	82:6473597d706e	4185
bogdanm	82:6473597d706e	4186	/*!
bogdanm	82:6473597d706e	4187	* @name Register UART_IS7816, field TXT[1] (W1C)
bogdanm	82:6473597d706e	4188	*
bogdanm	82:6473597d706e	4189	* Indicates that the transmit NACK threshold has been exceeded as indicated by
bogdanm	82:6473597d706e	4190	* ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
bogdanm	82:6473597d706e	4191	* continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
bogdanm	82:6473597d706e	4192	* 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
bogdanm	82:6473597d706e	4193	* cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
bogdanm	82:6473597d706e	4194	* internal NACK detection counter is cleared and the count restarts from zero on
bogdanm	82:6473597d706e	4195	* the next received NACK. This interrupt is cleared by writing 1.
bogdanm	82:6473597d706e	4196	*
bogdanm	82:6473597d706e	4197	* Values:
bogdanm	82:6473597d706e	4198	* - 0 - The number of retries and corresponding NACKS does not exceed the value
bogdanm	82:6473597d706e	4199	* in ET7816[TXTHRESHOLD].
bogdanm	82:6473597d706e	4200	* - 1 - The number of retries and corresponding NACKS exceeds the value in
bogdanm	82:6473597d706e	4201	* ET7816[TXTHRESHOLD].
bogdanm	82:6473597d706e	4202	*/
bogdanm	82:6473597d706e	4203	//@{
bogdanm	82:6473597d706e	4204	#define BP_UART_IS7816_TXT (1U) //!< Bit position for UART_IS7816_TXT.
bogdanm	82:6473597d706e	4205	#define BM_UART_IS7816_TXT (0x02U) //!< Bit mask for UART_IS7816_TXT.
bogdanm	82:6473597d706e	4206	#define BS_UART_IS7816_TXT (1U) //!< Bit field size in bits for UART_IS7816_TXT.
bogdanm	82:6473597d706e	4207
bogdanm	82:6473597d706e	4208	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4209	//! @brief Read current value of the UART_IS7816_TXT field.
bogdanm	82:6473597d706e	4210	#define BR_UART_IS7816_TXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT))
bogdanm	82:6473597d706e	4211	#endif
bogdanm	82:6473597d706e	4212
bogdanm	82:6473597d706e	4213	//! @brief Format value for bitfield UART_IS7816_TXT.
bogdanm	82:6473597d706e	4214	#define BF_UART_IS7816_TXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_TXT), uint8_t) & BM_UART_IS7816_TXT)
bogdanm	82:6473597d706e	4215
bogdanm	82:6473597d706e	4216	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4217	//! @brief Set the TXT field to a new value.
bogdanm	82:6473597d706e	4218	#define BW_UART_IS7816_TXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT) = (v))
bogdanm	82:6473597d706e	4219	#endif
bogdanm	82:6473597d706e	4220	//@}
bogdanm	82:6473597d706e	4221
bogdanm	82:6473597d706e	4222	/*!
bogdanm	82:6473597d706e	4223	* @name Register UART_IS7816, field GTV[2] (W1C)
bogdanm	82:6473597d706e	4224	*
bogdanm	82:6473597d706e	4225	* Indicates that one or more of the character guard time, block guard time, or
bogdanm	82:6473597d706e	4226	* guard time are violated. This interrupt is cleared by writing 1.
bogdanm	82:6473597d706e	4227	*
bogdanm	82:6473597d706e	4228	* Values:
bogdanm	82:6473597d706e	4229	* - 0 - A guard time (GT, CGT, or BGT) has not been violated.
bogdanm	82:6473597d706e	4230	* - 1 - A guard time (GT, CGT, or BGT) has been violated.
bogdanm	82:6473597d706e	4231	*/
bogdanm	82:6473597d706e	4232	//@{
bogdanm	82:6473597d706e	4233	#define BP_UART_IS7816_GTV (2U) //!< Bit position for UART_IS7816_GTV.
bogdanm	82:6473597d706e	4234	#define BM_UART_IS7816_GTV (0x04U) //!< Bit mask for UART_IS7816_GTV.
bogdanm	82:6473597d706e	4235	#define BS_UART_IS7816_GTV (1U) //!< Bit field size in bits for UART_IS7816_GTV.
bogdanm	82:6473597d706e	4236
bogdanm	82:6473597d706e	4237	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4238	//! @brief Read current value of the UART_IS7816_GTV field.
bogdanm	82:6473597d706e	4239	#define BR_UART_IS7816_GTV(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV))
bogdanm	82:6473597d706e	4240	#endif
bogdanm	82:6473597d706e	4241
bogdanm	82:6473597d706e	4242	//! @brief Format value for bitfield UART_IS7816_GTV.
bogdanm	82:6473597d706e	4243	#define BF_UART_IS7816_GTV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_GTV), uint8_t) & BM_UART_IS7816_GTV)
bogdanm	82:6473597d706e	4244
bogdanm	82:6473597d706e	4245	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4246	//! @brief Set the GTV field to a new value.
bogdanm	82:6473597d706e	4247	#define BW_UART_IS7816_GTV(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV) = (v))
bogdanm	82:6473597d706e	4248	#endif
bogdanm	82:6473597d706e	4249	//@}
bogdanm	82:6473597d706e	4250
bogdanm	82:6473597d706e	4251	/*!
bogdanm	82:6473597d706e	4252	* @name Register UART_IS7816, field INITD[4] (W1C)
bogdanm	82:6473597d706e	4253	*
bogdanm	82:6473597d706e	4254	* Indicates that a valid initial character is received. This interrupt is
bogdanm	82:6473597d706e	4255	* cleared by writing 1.
bogdanm	82:6473597d706e	4256	*
bogdanm	82:6473597d706e	4257	* Values:
bogdanm	82:6473597d706e	4258	* - 0 - A valid initial character has not been received.
bogdanm	82:6473597d706e	4259	* - 1 - A valid initial character has been received.
bogdanm	82:6473597d706e	4260	*/
bogdanm	82:6473597d706e	4261	//@{
bogdanm	82:6473597d706e	4262	#define BP_UART_IS7816_INITD (4U) //!< Bit position for UART_IS7816_INITD.
bogdanm	82:6473597d706e	4263	#define BM_UART_IS7816_INITD (0x10U) //!< Bit mask for UART_IS7816_INITD.
bogdanm	82:6473597d706e	4264	#define BS_UART_IS7816_INITD (1U) //!< Bit field size in bits for UART_IS7816_INITD.
bogdanm	82:6473597d706e	4265
bogdanm	82:6473597d706e	4266	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4267	//! @brief Read current value of the UART_IS7816_INITD field.
bogdanm	82:6473597d706e	4268	#define BR_UART_IS7816_INITD(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD))
bogdanm	82:6473597d706e	4269	#endif
bogdanm	82:6473597d706e	4270
bogdanm	82:6473597d706e	4271	//! @brief Format value for bitfield UART_IS7816_INITD.
bogdanm	82:6473597d706e	4272	#define BF_UART_IS7816_INITD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_INITD), uint8_t) & BM_UART_IS7816_INITD)
bogdanm	82:6473597d706e	4273
bogdanm	82:6473597d706e	4274	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4275	//! @brief Set the INITD field to a new value.
bogdanm	82:6473597d706e	4276	#define BW_UART_IS7816_INITD(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD) = (v))
bogdanm	82:6473597d706e	4277	#endif
bogdanm	82:6473597d706e	4278	//@}
bogdanm	82:6473597d706e	4279
bogdanm	82:6473597d706e	4280	/*!
bogdanm	82:6473597d706e	4281	* @name Register UART_IS7816, field BWT[5] (W1C)
bogdanm	82:6473597d706e	4282	*
bogdanm	82:6473597d706e	4283	* Indicates that the block wait time, the time between the leading edge of
bogdanm	82:6473597d706e	4284	* first received character of a block and the leading edge of the last character the
bogdanm	82:6473597d706e	4285	* previously transmitted block, has exceeded the programmed value. This flag
bogdanm	82:6473597d706e	4286	* asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
bogdanm	82:6473597d706e	4287	*
bogdanm	82:6473597d706e	4288	* Values:
bogdanm	82:6473597d706e	4289	* - 0 - Block wait time (BWT) has not been violated.
bogdanm	82:6473597d706e	4290	* - 1 - Block wait time (BWT) has been violated.
bogdanm	82:6473597d706e	4291	*/
bogdanm	82:6473597d706e	4292	//@{
bogdanm	82:6473597d706e	4293	#define BP_UART_IS7816_BWT (5U) //!< Bit position for UART_IS7816_BWT.
bogdanm	82:6473597d706e	4294	#define BM_UART_IS7816_BWT (0x20U) //!< Bit mask for UART_IS7816_BWT.
bogdanm	82:6473597d706e	4295	#define BS_UART_IS7816_BWT (1U) //!< Bit field size in bits for UART_IS7816_BWT.
bogdanm	82:6473597d706e	4296
bogdanm	82:6473597d706e	4297	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4298	//! @brief Read current value of the UART_IS7816_BWT field.
bogdanm	82:6473597d706e	4299	#define BR_UART_IS7816_BWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT))
bogdanm	82:6473597d706e	4300	#endif
bogdanm	82:6473597d706e	4301
bogdanm	82:6473597d706e	4302	//! @brief Format value for bitfield UART_IS7816_BWT.
bogdanm	82:6473597d706e	4303	#define BF_UART_IS7816_BWT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_BWT), uint8_t) & BM_UART_IS7816_BWT)
bogdanm	82:6473597d706e	4304
bogdanm	82:6473597d706e	4305	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4306	//! @brief Set the BWT field to a new value.
bogdanm	82:6473597d706e	4307	#define BW_UART_IS7816_BWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT) = (v))
bogdanm	82:6473597d706e	4308	#endif
bogdanm	82:6473597d706e	4309	//@}
bogdanm	82:6473597d706e	4310
bogdanm	82:6473597d706e	4311	/*!
bogdanm	82:6473597d706e	4312	* @name Register UART_IS7816, field CWT[6] (W1C)
bogdanm	82:6473597d706e	4313	*
bogdanm	82:6473597d706e	4314	* Indicates that the character wait time, the time between the leading edges of
bogdanm	82:6473597d706e	4315	* two consecutive characters in a block, has exceeded the programmed value.
bogdanm	82:6473597d706e	4316	* This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
bogdanm	82:6473597d706e	4317	* writing 1.
bogdanm	82:6473597d706e	4318	*
bogdanm	82:6473597d706e	4319	* Values:
bogdanm	82:6473597d706e	4320	* - 0 - Character wait time (CWT) has not been violated.
bogdanm	82:6473597d706e	4321	* - 1 - Character wait time (CWT) has been violated.
bogdanm	82:6473597d706e	4322	*/
bogdanm	82:6473597d706e	4323	//@{
bogdanm	82:6473597d706e	4324	#define BP_UART_IS7816_CWT (6U) //!< Bit position for UART_IS7816_CWT.
bogdanm	82:6473597d706e	4325	#define BM_UART_IS7816_CWT (0x40U) //!< Bit mask for UART_IS7816_CWT.
bogdanm	82:6473597d706e	4326	#define BS_UART_IS7816_CWT (1U) //!< Bit field size in bits for UART_IS7816_CWT.
bogdanm	82:6473597d706e	4327
bogdanm	82:6473597d706e	4328	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4329	//! @brief Read current value of the UART_IS7816_CWT field.
bogdanm	82:6473597d706e	4330	#define BR_UART_IS7816_CWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT))
bogdanm	82:6473597d706e	4331	#endif
bogdanm	82:6473597d706e	4332
bogdanm	82:6473597d706e	4333	//! @brief Format value for bitfield UART_IS7816_CWT.
bogdanm	82:6473597d706e	4334	#define BF_UART_IS7816_CWT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_CWT), uint8_t) & BM_UART_IS7816_CWT)
bogdanm	82:6473597d706e	4335
bogdanm	82:6473597d706e	4336	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4337	//! @brief Set the CWT field to a new value.
bogdanm	82:6473597d706e	4338	#define BW_UART_IS7816_CWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT) = (v))
bogdanm	82:6473597d706e	4339	#endif
bogdanm	82:6473597d706e	4340	//@}
bogdanm	82:6473597d706e	4341
bogdanm	82:6473597d706e	4342	/*!
bogdanm	82:6473597d706e	4343	* @name Register UART_IS7816, field WT[7] (W1C)
bogdanm	82:6473597d706e	4344	*
bogdanm	82:6473597d706e	4345	* Indicates that the wait time, the time between the leading edge of a
bogdanm	82:6473597d706e	4346	* character being transmitted and the leading edge of the next response character, has
bogdanm	82:6473597d706e	4347	* exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
bogdanm	82:6473597d706e	4348	* This interrupt is cleared by writing 1.
bogdanm	82:6473597d706e	4349	*
bogdanm	82:6473597d706e	4350	* Values:
bogdanm	82:6473597d706e	4351	* - 0 - Wait time (WT) has not been violated.
bogdanm	82:6473597d706e	4352	* - 1 - Wait time (WT) has been violated.
bogdanm	82:6473597d706e	4353	*/
bogdanm	82:6473597d706e	4354	//@{
bogdanm	82:6473597d706e	4355	#define BP_UART_IS7816_WT (7U) //!< Bit position for UART_IS7816_WT.
bogdanm	82:6473597d706e	4356	#define BM_UART_IS7816_WT (0x80U) //!< Bit mask for UART_IS7816_WT.
bogdanm	82:6473597d706e	4357	#define BS_UART_IS7816_WT (1U) //!< Bit field size in bits for UART_IS7816_WT.
bogdanm	82:6473597d706e	4358
bogdanm	82:6473597d706e	4359	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4360	//! @brief Read current value of the UART_IS7816_WT field.
bogdanm	82:6473597d706e	4361	#define BR_UART_IS7816_WT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT))
bogdanm	82:6473597d706e	4362	#endif
bogdanm	82:6473597d706e	4363
bogdanm	82:6473597d706e	4364	//! @brief Format value for bitfield UART_IS7816_WT.
bogdanm	82:6473597d706e	4365	#define BF_UART_IS7816_WT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_WT), uint8_t) & BM_UART_IS7816_WT)
bogdanm	82:6473597d706e	4366
bogdanm	82:6473597d706e	4367	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4368	//! @brief Set the WT field to a new value.
bogdanm	82:6473597d706e	4369	#define BW_UART_IS7816_WT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT) = (v))
bogdanm	82:6473597d706e	4370	#endif
bogdanm	82:6473597d706e	4371	//@}
bogdanm	82:6473597d706e	4372
bogdanm	82:6473597d706e	4373	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4374	// HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register
bogdanm	82:6473597d706e	4375	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4376
bogdanm	82:6473597d706e	4377	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4378	/*!
bogdanm	82:6473597d706e	4379	* @brief HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register (RW)
bogdanm	82:6473597d706e	4380	*
bogdanm	82:6473597d706e	4381	* Reset value: 0x0AU
bogdanm	82:6473597d706e	4382	*
bogdanm	82:6473597d706e	4383	* The WP7816 register contains constants used in the generation of various wait
bogdanm	82:6473597d706e	4384	* timer counters. To save register space, this register is used differently
bogdanm	82:6473597d706e	4385	* when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
bogdanm	82:6473597d706e	4386	* time. This register must be written to only when C7816[ISO_7816E] is not set.
bogdanm	82:6473597d706e	4387	*/
bogdanm	82:6473597d706e	4388	typedef union _hw_uart_wp7816_t_type0
bogdanm	82:6473597d706e	4389	{
bogdanm	82:6473597d706e	4390	uint8_t U;
bogdanm	82:6473597d706e	4391	struct _hw_uart_wp7816_t_type0_bitfields
bogdanm	82:6473597d706e	4392	{
bogdanm	82:6473597d706e	4393	uint8_t WI : 8; //!< [7:0] Wait Time Integer (C7816[TTYPE] = 0)
bogdanm	82:6473597d706e	4394	} B;
bogdanm	82:6473597d706e	4395	} hw_uart_wp7816_t_type0_t;
bogdanm	82:6473597d706e	4396	#endif
bogdanm	82:6473597d706e	4397
bogdanm	82:6473597d706e	4398	/*!
bogdanm	82:6473597d706e	4399	* @name Constants and macros for entire UART_WP7816_T_TYPE0 register
bogdanm	82:6473597d706e	4400	*/
bogdanm	82:6473597d706e	4401	//@{
bogdanm	82:6473597d706e	4402	#define HW_UART_WP7816_T_TYPE0_ADDR(x) (REGS_UART_BASE(x) + 0x1BU)
bogdanm	82:6473597d706e	4403
bogdanm	82:6473597d706e	4404	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4405	#define HW_UART_WP7816_T_TYPE0(x) ((__IO hw_uart_wp7816_t_type0_t ) HW_UART_WP7816_T_TYPE0_ADDR(x))
bogdanm	82:6473597d706e	4406	#define HW_UART_WP7816_T_TYPE0_RD(x) (HW_UART_WP7816_T_TYPE0(x).U)
bogdanm	82:6473597d706e	4407	#define HW_UART_WP7816_T_TYPE0_WR(x, v) (HW_UART_WP7816_T_TYPE0(x).U = (v))
bogdanm	82:6473597d706e	4408	#define HW_UART_WP7816_T_TYPE0_SET(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) \| (v)))
bogdanm	82:6473597d706e	4409	#define HW_UART_WP7816_T_TYPE0_CLR(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) & ~(v)))
bogdanm	82:6473597d706e	4410	#define HW_UART_WP7816_T_TYPE0_TOG(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) ^ (v)))
bogdanm	82:6473597d706e	4411	#endif
bogdanm	82:6473597d706e	4412	//@}
bogdanm	82:6473597d706e	4413
bogdanm	82:6473597d706e	4414	/*
bogdanm	82:6473597d706e	4415	* Constants & macros for individual UART_WP7816_T_TYPE0 bitfields
bogdanm	82:6473597d706e	4416	*/
bogdanm	82:6473597d706e	4417
bogdanm	82:6473597d706e	4418	/*!
bogdanm	82:6473597d706e	4419	* @name Register UART_WP7816_T_TYPE0, field WI[7:0] (RW)
bogdanm	82:6473597d706e	4420	*
bogdanm	82:6473597d706e	4421	* Used to calculate the value used for the WT counter. It represents a value
bogdanm	82:6473597d706e	4422	* between 1 and 255. The value of zero is not valid. This value is used only when
bogdanm	82:6473597d706e	4423	* C7816[TTYPE] = 0. See Wait time and guard time parameters.
bogdanm	82:6473597d706e	4424	*/
bogdanm	82:6473597d706e	4425	//@{
bogdanm	82:6473597d706e	4426	#define BP_UART_WP7816_T_TYPE0_WI (0U) //!< Bit position for UART_WP7816_T_TYPE0_WI.
bogdanm	82:6473597d706e	4427	#define BM_UART_WP7816_T_TYPE0_WI (0xFFU) //!< Bit mask for UART_WP7816_T_TYPE0_WI.
bogdanm	82:6473597d706e	4428	#define BS_UART_WP7816_T_TYPE0_WI (8U) //!< Bit field size in bits for UART_WP7816_T_TYPE0_WI.
bogdanm	82:6473597d706e	4429
bogdanm	82:6473597d706e	4430	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4431	//! @brief Read current value of the UART_WP7816_T_TYPE0_WI field.
bogdanm	82:6473597d706e	4432	#define BR_UART_WP7816_T_TYPE0_WI(x) (HW_UART_WP7816_T_TYPE0(x).U)
bogdanm	82:6473597d706e	4433	#endif
bogdanm	82:6473597d706e	4434
bogdanm	82:6473597d706e	4435	//! @brief Format value for bitfield UART_WP7816_T_TYPE0_WI.
bogdanm	82:6473597d706e	4436	#define BF_UART_WP7816_T_TYPE0_WI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE0_WI), uint8_t) & BM_UART_WP7816_T_TYPE0_WI)
bogdanm	82:6473597d706e	4437
bogdanm	82:6473597d706e	4438	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4439	//! @brief Set the WI field to a new value.
bogdanm	82:6473597d706e	4440	#define BW_UART_WP7816_T_TYPE0_WI(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, v))
bogdanm	82:6473597d706e	4441	#endif
bogdanm	82:6473597d706e	4442	//@}
bogdanm	82:6473597d706e	4443	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4444	// HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register
bogdanm	82:6473597d706e	4445	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4446
bogdanm	82:6473597d706e	4447	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4448	/*!
bogdanm	82:6473597d706e	4449	* @brief HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register (RW)
bogdanm	82:6473597d706e	4450	*
bogdanm	82:6473597d706e	4451	* Reset value: 0x0AU
bogdanm	82:6473597d706e	4452	*
bogdanm	82:6473597d706e	4453	* The WP7816 register contains constants used in the generation of various wait
bogdanm	82:6473597d706e	4454	* timer counters. To save register space, this register is used differently
bogdanm	82:6473597d706e	4455	* when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
bogdanm	82:6473597d706e	4456	* time. This register must be written to only when C7816[ISO_7816E] is not set.
bogdanm	82:6473597d706e	4457	*/
bogdanm	82:6473597d706e	4458	typedef union _hw_uart_wp7816_t_type1
bogdanm	82:6473597d706e	4459	{
bogdanm	82:6473597d706e	4460	uint8_t U;
bogdanm	82:6473597d706e	4461	struct _hw_uart_wp7816_t_type1_bitfields
bogdanm	82:6473597d706e	4462	{
bogdanm	82:6473597d706e	4463	uint8_t BWI : 4; //!< [3:0] Block Wait Time Integer(C7816[TTYPE] = 1)
bogdanm	82:6473597d706e	4464	uint8_t CWI : 4; //!< [7:4] Character Wait Time Integer (C7816[TTYPE]
bogdanm	82:6473597d706e	4465	//! = 1)
bogdanm	82:6473597d706e	4466	} B;
bogdanm	82:6473597d706e	4467	} hw_uart_wp7816_t_type1_t;
bogdanm	82:6473597d706e	4468	#endif
bogdanm	82:6473597d706e	4469
bogdanm	82:6473597d706e	4470	/*!
bogdanm	82:6473597d706e	4471	* @name Constants and macros for entire UART_WP7816_T_TYPE1 register
bogdanm	82:6473597d706e	4472	*/
bogdanm	82:6473597d706e	4473	//@{
bogdanm	82:6473597d706e	4474	#define HW_UART_WP7816_T_TYPE1_ADDR(x) (REGS_UART_BASE(x) + 0x1BU)
bogdanm	82:6473597d706e	4475
bogdanm	82:6473597d706e	4476	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4477	#define HW_UART_WP7816_T_TYPE1(x) ((__IO hw_uart_wp7816_t_type1_t ) HW_UART_WP7816_T_TYPE1_ADDR(x))
bogdanm	82:6473597d706e	4478	#define HW_UART_WP7816_T_TYPE1_RD(x) (HW_UART_WP7816_T_TYPE1(x).U)
bogdanm	82:6473597d706e	4479	#define HW_UART_WP7816_T_TYPE1_WR(x, v) (HW_UART_WP7816_T_TYPE1(x).U = (v))
bogdanm	82:6473597d706e	4480	#define HW_UART_WP7816_T_TYPE1_SET(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) \| (v)))
bogdanm	82:6473597d706e	4481	#define HW_UART_WP7816_T_TYPE1_CLR(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	4482	#define HW_UART_WP7816_T_TYPE1_TOG(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	4483	#endif
bogdanm	82:6473597d706e	4484	//@}
bogdanm	82:6473597d706e	4485
bogdanm	82:6473597d706e	4486	/*
bogdanm	82:6473597d706e	4487	* Constants & macros for individual UART_WP7816_T_TYPE1 bitfields
bogdanm	82:6473597d706e	4488	*/
bogdanm	82:6473597d706e	4489
bogdanm	82:6473597d706e	4490	/*!
bogdanm	82:6473597d706e	4491	* @name Register UART_WP7816_T_TYPE1, field BWI[3:0] (RW)
bogdanm	82:6473597d706e	4492	*
bogdanm	82:6473597d706e	4493	* Used to calculate the value used for the BWT counter. It represent a value
bogdanm	82:6473597d706e	4494	* between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
bogdanm	82:6473597d706e	4495	* and guard time parameters .
bogdanm	82:6473597d706e	4496	*/
bogdanm	82:6473597d706e	4497	//@{
bogdanm	82:6473597d706e	4498	#define BP_UART_WP7816_T_TYPE1_BWI (0U) //!< Bit position for UART_WP7816_T_TYPE1_BWI.
bogdanm	82:6473597d706e	4499	#define BM_UART_WP7816_T_TYPE1_BWI (0x0FU) //!< Bit mask for UART_WP7816_T_TYPE1_BWI.
bogdanm	82:6473597d706e	4500	#define BS_UART_WP7816_T_TYPE1_BWI (4U) //!< Bit field size in bits for UART_WP7816_T_TYPE1_BWI.
bogdanm	82:6473597d706e	4501
bogdanm	82:6473597d706e	4502	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4503	//! @brief Read current value of the UART_WP7816_T_TYPE1_BWI field.
bogdanm	82:6473597d706e	4504	#define BR_UART_WP7816_T_TYPE1_BWI(x) (HW_UART_WP7816_T_TYPE1(x).B.BWI)
bogdanm	82:6473597d706e	4505	#endif
bogdanm	82:6473597d706e	4506
bogdanm	82:6473597d706e	4507	//! @brief Format value for bitfield UART_WP7816_T_TYPE1_BWI.
bogdanm	82:6473597d706e	4508	#define BF_UART_WP7816_T_TYPE1_BWI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE1_BWI), uint8_t) & BM_UART_WP7816_T_TYPE1_BWI)
bogdanm	82:6473597d706e	4509
bogdanm	82:6473597d706e	4510	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4511	//! @brief Set the BWI field to a new value.
bogdanm	82:6473597d706e	4512	#define BW_UART_WP7816_T_TYPE1_BWI(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, (HW_UART_WP7816_T_TYPE1_RD(x) & ~BM_UART_WP7816_T_TYPE1_BWI) \| BF_UART_WP7816_T_TYPE1_BWI(v)))
bogdanm	82:6473597d706e	4513	#endif
bogdanm	82:6473597d706e	4514	//@}
bogdanm	82:6473597d706e	4515
bogdanm	82:6473597d706e	4516	/*!
bogdanm	82:6473597d706e	4517	* @name Register UART_WP7816_T_TYPE1, field CWI[7:4] (RW)
bogdanm	82:6473597d706e	4518	*
bogdanm	82:6473597d706e	4519	* Used to calculate the value used for the CWT counter. It represents a value
bogdanm	82:6473597d706e	4520	* between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
bogdanm	82:6473597d706e	4521	* and guard time parameters .
bogdanm	82:6473597d706e	4522	*/
bogdanm	82:6473597d706e	4523	//@{
bogdanm	82:6473597d706e	4524	#define BP_UART_WP7816_T_TYPE1_CWI (4U) //!< Bit position for UART_WP7816_T_TYPE1_CWI.
bogdanm	82:6473597d706e	4525	#define BM_UART_WP7816_T_TYPE1_CWI (0xF0U) //!< Bit mask for UART_WP7816_T_TYPE1_CWI.
bogdanm	82:6473597d706e	4526	#define BS_UART_WP7816_T_TYPE1_CWI (4U) //!< Bit field size in bits for UART_WP7816_T_TYPE1_CWI.
bogdanm	82:6473597d706e	4527
bogdanm	82:6473597d706e	4528	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4529	//! @brief Read current value of the UART_WP7816_T_TYPE1_CWI field.
bogdanm	82:6473597d706e	4530	#define BR_UART_WP7816_T_TYPE1_CWI(x) (HW_UART_WP7816_T_TYPE1(x).B.CWI)
bogdanm	82:6473597d706e	4531	#endif
bogdanm	82:6473597d706e	4532
bogdanm	82:6473597d706e	4533	//! @brief Format value for bitfield UART_WP7816_T_TYPE1_CWI.
bogdanm	82:6473597d706e	4534	#define BF_UART_WP7816_T_TYPE1_CWI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE1_CWI), uint8_t) & BM_UART_WP7816_T_TYPE1_CWI)
bogdanm	82:6473597d706e	4535
bogdanm	82:6473597d706e	4536	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4537	//! @brief Set the CWI field to a new value.
bogdanm	82:6473597d706e	4538	#define BW_UART_WP7816_T_TYPE1_CWI(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, (HW_UART_WP7816_T_TYPE1_RD(x) & ~BM_UART_WP7816_T_TYPE1_CWI) \| BF_UART_WP7816_T_TYPE1_CWI(v)))
bogdanm	82:6473597d706e	4539	#endif
bogdanm	82:6473597d706e	4540	//@}
bogdanm	82:6473597d706e	4541
bogdanm	82:6473597d706e	4542	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4543	// HW_UART_WN7816 - UART 7816 Wait N Register
bogdanm	82:6473597d706e	4544	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4545
bogdanm	82:6473597d706e	4546	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4547	/*!
bogdanm	82:6473597d706e	4548	* @brief HW_UART_WN7816 - UART 7816 Wait N Register (RW)
bogdanm	82:6473597d706e	4549	*
bogdanm	82:6473597d706e	4550	* Reset value: 0x00U
bogdanm	82:6473597d706e	4551	*
bogdanm	82:6473597d706e	4552	* The WN7816 register contains a parameter that is used in the calculation of
bogdanm	82:6473597d706e	4553	* the guard time counter. This register may be read at any time. This register
bogdanm	82:6473597d706e	4554	* must be written to only when C7816[ISO_7816E] is not set.
bogdanm	82:6473597d706e	4555	*/
bogdanm	82:6473597d706e	4556	typedef union _hw_uart_wn7816
bogdanm	82:6473597d706e	4557	{
bogdanm	82:6473597d706e	4558	uint8_t U;
bogdanm	82:6473597d706e	4559	struct _hw_uart_wn7816_bitfields
bogdanm	82:6473597d706e	4560	{
bogdanm	82:6473597d706e	4561	uint8_t GTN : 8; //!< [7:0] Guard Band N
bogdanm	82:6473597d706e	4562	} B;
bogdanm	82:6473597d706e	4563	} hw_uart_wn7816_t;
bogdanm	82:6473597d706e	4564	#endif
bogdanm	82:6473597d706e	4565
bogdanm	82:6473597d706e	4566	/*!
bogdanm	82:6473597d706e	4567	* @name Constants and macros for entire UART_WN7816 register
bogdanm	82:6473597d706e	4568	*/
bogdanm	82:6473597d706e	4569	//@{
bogdanm	82:6473597d706e	4570	#define HW_UART_WN7816_ADDR(x) (REGS_UART_BASE(x) + 0x1CU)
bogdanm	82:6473597d706e	4571
bogdanm	82:6473597d706e	4572	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4573	#define HW_UART_WN7816(x) ((__IO hw_uart_wn7816_t ) HW_UART_WN7816_ADDR(x))
bogdanm	82:6473597d706e	4574	#define HW_UART_WN7816_RD(x) (HW_UART_WN7816(x).U)
bogdanm	82:6473597d706e	4575	#define HW_UART_WN7816_WR(x, v) (HW_UART_WN7816(x).U = (v))
bogdanm	82:6473597d706e	4576	#define HW_UART_WN7816_SET(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) \| (v)))
bogdanm	82:6473597d706e	4577	#define HW_UART_WN7816_CLR(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) & ~(v)))
bogdanm	82:6473597d706e	4578	#define HW_UART_WN7816_TOG(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) ^ (v)))
bogdanm	82:6473597d706e	4579	#endif
bogdanm	82:6473597d706e	4580	//@}
bogdanm	82:6473597d706e	4581
bogdanm	82:6473597d706e	4582	/*
bogdanm	82:6473597d706e	4583	* Constants & macros for individual UART_WN7816 bitfields
bogdanm	82:6473597d706e	4584	*/
bogdanm	82:6473597d706e	4585
bogdanm	82:6473597d706e	4586	/*!
bogdanm	82:6473597d706e	4587	* @name Register UART_WN7816, field GTN[7:0] (RW)
bogdanm	82:6473597d706e	4588	*
bogdanm	82:6473597d706e	4589	* Defines a parameter used in the calculation of GT, CGT, and BGT counters. The
bogdanm	82:6473597d706e	4590	* value represents an integer number between 0 and 255. See Wait time and guard
bogdanm	82:6473597d706e	4591	* time parameters .
bogdanm	82:6473597d706e	4592	*/
bogdanm	82:6473597d706e	4593	//@{
bogdanm	82:6473597d706e	4594	#define BP_UART_WN7816_GTN (0U) //!< Bit position for UART_WN7816_GTN.
bogdanm	82:6473597d706e	4595	#define BM_UART_WN7816_GTN (0xFFU) //!< Bit mask for UART_WN7816_GTN.
bogdanm	82:6473597d706e	4596	#define BS_UART_WN7816_GTN (8U) //!< Bit field size in bits for UART_WN7816_GTN.
bogdanm	82:6473597d706e	4597
bogdanm	82:6473597d706e	4598	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4599	//! @brief Read current value of the UART_WN7816_GTN field.
bogdanm	82:6473597d706e	4600	#define BR_UART_WN7816_GTN(x) (HW_UART_WN7816(x).U)
bogdanm	82:6473597d706e	4601	#endif
bogdanm	82:6473597d706e	4602
bogdanm	82:6473597d706e	4603	//! @brief Format value for bitfield UART_WN7816_GTN.
bogdanm	82:6473597d706e	4604	#define BF_UART_WN7816_GTN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WN7816_GTN), uint8_t) & BM_UART_WN7816_GTN)
bogdanm	82:6473597d706e	4605
bogdanm	82:6473597d706e	4606	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4607	//! @brief Set the GTN field to a new value.
bogdanm	82:6473597d706e	4608	#define BW_UART_WN7816_GTN(x, v) (HW_UART_WN7816_WR(x, v))
bogdanm	82:6473597d706e	4609	#endif
bogdanm	82:6473597d706e	4610	//@}
bogdanm	82:6473597d706e	4611
bogdanm	82:6473597d706e	4612	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4613	// HW_UART_WF7816 - UART 7816 Wait FD Register
bogdanm	82:6473597d706e	4614	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4615
bogdanm	82:6473597d706e	4616	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4617	/*!
bogdanm	82:6473597d706e	4618	* @brief HW_UART_WF7816 - UART 7816 Wait FD Register (RW)
bogdanm	82:6473597d706e	4619	*
bogdanm	82:6473597d706e	4620	* Reset value: 0x01U
bogdanm	82:6473597d706e	4621	*
bogdanm	82:6473597d706e	4622	* The WF7816 contains parameters that are used in the generation of various
bogdanm	82:6473597d706e	4623	* counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
bogdanm	82:6473597d706e	4624	* time. This register must be written to only when C7816[ISO_7816E] is not set.
bogdanm	82:6473597d706e	4625	*/
bogdanm	82:6473597d706e	4626	typedef union _hw_uart_wf7816
bogdanm	82:6473597d706e	4627	{
bogdanm	82:6473597d706e	4628	uint8_t U;
bogdanm	82:6473597d706e	4629	struct _hw_uart_wf7816_bitfields
bogdanm	82:6473597d706e	4630	{
bogdanm	82:6473597d706e	4631	uint8_t GTFD : 8; //!< [7:0] FD Multiplier
bogdanm	82:6473597d706e	4632	} B;
bogdanm	82:6473597d706e	4633	} hw_uart_wf7816_t;
bogdanm	82:6473597d706e	4634	#endif
bogdanm	82:6473597d706e	4635
bogdanm	82:6473597d706e	4636	/*!
bogdanm	82:6473597d706e	4637	* @name Constants and macros for entire UART_WF7816 register
bogdanm	82:6473597d706e	4638	*/
bogdanm	82:6473597d706e	4639	//@{
bogdanm	82:6473597d706e	4640	#define HW_UART_WF7816_ADDR(x) (REGS_UART_BASE(x) + 0x1DU)
bogdanm	82:6473597d706e	4641
bogdanm	82:6473597d706e	4642	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4643	#define HW_UART_WF7816(x) ((__IO hw_uart_wf7816_t ) HW_UART_WF7816_ADDR(x))
bogdanm	82:6473597d706e	4644	#define HW_UART_WF7816_RD(x) (HW_UART_WF7816(x).U)
bogdanm	82:6473597d706e	4645	#define HW_UART_WF7816_WR(x, v) (HW_UART_WF7816(x).U = (v))
bogdanm	82:6473597d706e	4646	#define HW_UART_WF7816_SET(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) \| (v)))
bogdanm	82:6473597d706e	4647	#define HW_UART_WF7816_CLR(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) & ~(v)))
bogdanm	82:6473597d706e	4648	#define HW_UART_WF7816_TOG(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) ^ (v)))
bogdanm	82:6473597d706e	4649	#endif
bogdanm	82:6473597d706e	4650	//@}
bogdanm	82:6473597d706e	4651
bogdanm	82:6473597d706e	4652	/*
bogdanm	82:6473597d706e	4653	* Constants & macros for individual UART_WF7816 bitfields
bogdanm	82:6473597d706e	4654	*/
bogdanm	82:6473597d706e	4655
bogdanm	82:6473597d706e	4656	/*!
bogdanm	82:6473597d706e	4657	* @name Register UART_WF7816, field GTFD[7:0] (RW)
bogdanm	82:6473597d706e	4658	*
bogdanm	82:6473597d706e	4659	* Used as another multiplier in the calculation of WT and BWT. This value
bogdanm	82:6473597d706e	4660	* represents a number between 1 and 255. The value of 0 is invalid. This value is not
bogdanm	82:6473597d706e	4661	* used in baud rate generation. See Wait time and guard time parameters and
bogdanm	82:6473597d706e	4662	* Baud rate generation .
bogdanm	82:6473597d706e	4663	*/
bogdanm	82:6473597d706e	4664	//@{
bogdanm	82:6473597d706e	4665	#define BP_UART_WF7816_GTFD (0U) //!< Bit position for UART_WF7816_GTFD.
bogdanm	82:6473597d706e	4666	#define BM_UART_WF7816_GTFD (0xFFU) //!< Bit mask for UART_WF7816_GTFD.
bogdanm	82:6473597d706e	4667	#define BS_UART_WF7816_GTFD (8U) //!< Bit field size in bits for UART_WF7816_GTFD.
bogdanm	82:6473597d706e	4668
bogdanm	82:6473597d706e	4669	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4670	//! @brief Read current value of the UART_WF7816_GTFD field.
bogdanm	82:6473597d706e	4671	#define BR_UART_WF7816_GTFD(x) (HW_UART_WF7816(x).U)
bogdanm	82:6473597d706e	4672	#endif
bogdanm	82:6473597d706e	4673
bogdanm	82:6473597d706e	4674	//! @brief Format value for bitfield UART_WF7816_GTFD.
bogdanm	82:6473597d706e	4675	#define BF_UART_WF7816_GTFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WF7816_GTFD), uint8_t) & BM_UART_WF7816_GTFD)
bogdanm	82:6473597d706e	4676
bogdanm	82:6473597d706e	4677	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4678	//! @brief Set the GTFD field to a new value.
bogdanm	82:6473597d706e	4679	#define BW_UART_WF7816_GTFD(x, v) (HW_UART_WF7816_WR(x, v))
bogdanm	82:6473597d706e	4680	#endif
bogdanm	82:6473597d706e	4681	//@}
bogdanm	82:6473597d706e	4682
bogdanm	82:6473597d706e	4683	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4684	// HW_UART_ET7816 - UART 7816 Error Threshold Register
bogdanm	82:6473597d706e	4685	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4686
bogdanm	82:6473597d706e	4687	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4688	/*!
bogdanm	82:6473597d706e	4689	* @brief HW_UART_ET7816 - UART 7816 Error Threshold Register (RW)
bogdanm	82:6473597d706e	4690	*
bogdanm	82:6473597d706e	4691	* Reset value: 0x00U
bogdanm	82:6473597d706e	4692	*
bogdanm	82:6473597d706e	4693	* The ET7816 register contains fields that determine the number of NACKs that
bogdanm	82:6473597d706e	4694	* must be received or transmitted before the host processor is notified. This
bogdanm	82:6473597d706e	4695	* register may be read at anytime. This register must be written to only when
bogdanm	82:6473597d706e	4696	* C7816[ISO_7816E] is not set.
bogdanm	82:6473597d706e	4697	*/
bogdanm	82:6473597d706e	4698	typedef union _hw_uart_et7816
bogdanm	82:6473597d706e	4699	{
bogdanm	82:6473597d706e	4700	uint8_t U;
bogdanm	82:6473597d706e	4701	struct _hw_uart_et7816_bitfields
bogdanm	82:6473597d706e	4702	{
bogdanm	82:6473597d706e	4703	uint8_t RXTHRESHOLD : 4; //!< [3:0] Receive NACK Threshold
bogdanm	82:6473597d706e	4704	uint8_t TXTHRESHOLD : 4; //!< [7:4] Transmit NACK Threshold
bogdanm	82:6473597d706e	4705	} B;
bogdanm	82:6473597d706e	4706	} hw_uart_et7816_t;
bogdanm	82:6473597d706e	4707	#endif
bogdanm	82:6473597d706e	4708
bogdanm	82:6473597d706e	4709	/*!
bogdanm	82:6473597d706e	4710	* @name Constants and macros for entire UART_ET7816 register
bogdanm	82:6473597d706e	4711	*/
bogdanm	82:6473597d706e	4712	//@{
bogdanm	82:6473597d706e	4713	#define HW_UART_ET7816_ADDR(x) (REGS_UART_BASE(x) + 0x1EU)
bogdanm	82:6473597d706e	4714
bogdanm	82:6473597d706e	4715	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4716	#define HW_UART_ET7816(x) ((__IO hw_uart_et7816_t ) HW_UART_ET7816_ADDR(x))
bogdanm	82:6473597d706e	4717	#define HW_UART_ET7816_RD(x) (HW_UART_ET7816(x).U)
bogdanm	82:6473597d706e	4718	#define HW_UART_ET7816_WR(x, v) (HW_UART_ET7816(x).U = (v))
bogdanm	82:6473597d706e	4719	#define HW_UART_ET7816_SET(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) \| (v)))
bogdanm	82:6473597d706e	4720	#define HW_UART_ET7816_CLR(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) & ~(v)))
bogdanm	82:6473597d706e	4721	#define HW_UART_ET7816_TOG(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) ^ (v)))
bogdanm	82:6473597d706e	4722	#endif
bogdanm	82:6473597d706e	4723	//@}
bogdanm	82:6473597d706e	4724
bogdanm	82:6473597d706e	4725	/*
bogdanm	82:6473597d706e	4726	* Constants & macros for individual UART_ET7816 bitfields
bogdanm	82:6473597d706e	4727	*/
bogdanm	82:6473597d706e	4728
bogdanm	82:6473597d706e	4729	/*!
bogdanm	82:6473597d706e	4730	* @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
bogdanm	82:6473597d706e	4731	*
bogdanm	82:6473597d706e	4732	* The value written to this field indicates the maximum number of consecutive
bogdanm	82:6473597d706e	4733	* NACKs generated as a result of a parity error or receiver buffer overruns
bogdanm	82:6473597d706e	4734	* before the host processor is notified. After the counter exceeds that value in the
bogdanm	82:6473597d706e	4735	* field, the IS7816[RXT] is asserted. This field is meaningful only when
bogdanm	82:6473597d706e	4736	* C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
bogdanm	82:6473597d706e	4737	* NACKs that have been transmitted since the last successful reception. This
bogdanm	82:6473597d706e	4738	* counter saturates at 4'hF and does not wrap around. Regardless of the number of
bogdanm	82:6473597d706e	4739	* NACKs sent, the UART continues to receive valid packets indefinitely. For
bogdanm	82:6473597d706e	4740	* additional information, see IS7816[RXT] field description.
bogdanm	82:6473597d706e	4741	*/
bogdanm	82:6473597d706e	4742	//@{
bogdanm	82:6473597d706e	4743	#define BP_UART_ET7816_RXTHRESHOLD (0U) //!< Bit position for UART_ET7816_RXTHRESHOLD.
bogdanm	82:6473597d706e	4744	#define BM_UART_ET7816_RXTHRESHOLD (0x0FU) //!< Bit mask for UART_ET7816_RXTHRESHOLD.
bogdanm	82:6473597d706e	4745	#define BS_UART_ET7816_RXTHRESHOLD (4U) //!< Bit field size in bits for UART_ET7816_RXTHRESHOLD.
bogdanm	82:6473597d706e	4746
bogdanm	82:6473597d706e	4747	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4748	//! @brief Read current value of the UART_ET7816_RXTHRESHOLD field.
bogdanm	82:6473597d706e	4749	#define BR_UART_ET7816_RXTHRESHOLD(x) (HW_UART_ET7816(x).B.RXTHRESHOLD)
bogdanm	82:6473597d706e	4750	#endif
bogdanm	82:6473597d706e	4751
bogdanm	82:6473597d706e	4752	//! @brief Format value for bitfield UART_ET7816_RXTHRESHOLD.
bogdanm	82:6473597d706e	4753	#define BF_UART_ET7816_RXTHRESHOLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_ET7816_RXTHRESHOLD), uint8_t) & BM_UART_ET7816_RXTHRESHOLD)
bogdanm	82:6473597d706e	4754
bogdanm	82:6473597d706e	4755	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4756	//! @brief Set the RXTHRESHOLD field to a new value.
bogdanm	82:6473597d706e	4757	#define BW_UART_ET7816_RXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_RXTHRESHOLD) \| BF_UART_ET7816_RXTHRESHOLD(v)))
bogdanm	82:6473597d706e	4758	#endif
bogdanm	82:6473597d706e	4759	//@}
bogdanm	82:6473597d706e	4760
bogdanm	82:6473597d706e	4761	/*!
bogdanm	82:6473597d706e	4762	* @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
bogdanm	82:6473597d706e	4763	*
bogdanm	82:6473597d706e	4764	* The value written to this field indicates the maximum number of failed
bogdanm	82:6473597d706e	4765	* attempts (NACKs) a transmitted character can have before the host processor is
bogdanm	82:6473597d706e	4766	* notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
bogdanm	82:6473597d706e	4767	* The value read from this field represents the number of consecutive NACKs
bogdanm	82:6473597d706e	4768	* that have been received since the last successful transmission. This counter
bogdanm	82:6473597d706e	4769	* saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
bogdanm	82:6473597d706e	4770	* received, the UART continues to retransmit indefinitely. This flag only
bogdanm	82:6473597d706e	4771	* asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
bogdanm	82:6473597d706e	4772	* description.
bogdanm	82:6473597d706e	4773	*
bogdanm	82:6473597d706e	4774	* Values:
bogdanm	82:6473597d706e	4775	* - 0 - TXT asserts on the first NACK that is received.
bogdanm	82:6473597d706e	4776	* - 1 - TXT asserts on the second NACK that is received.
bogdanm	82:6473597d706e	4777	*/
bogdanm	82:6473597d706e	4778	//@{
bogdanm	82:6473597d706e	4779	#define BP_UART_ET7816_TXTHRESHOLD (4U) //!< Bit position for UART_ET7816_TXTHRESHOLD.
bogdanm	82:6473597d706e	4780	#define BM_UART_ET7816_TXTHRESHOLD (0xF0U) //!< Bit mask for UART_ET7816_TXTHRESHOLD.
bogdanm	82:6473597d706e	4781	#define BS_UART_ET7816_TXTHRESHOLD (4U) //!< Bit field size in bits for UART_ET7816_TXTHRESHOLD.
bogdanm	82:6473597d706e	4782
bogdanm	82:6473597d706e	4783	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4784	//! @brief Read current value of the UART_ET7816_TXTHRESHOLD field.
bogdanm	82:6473597d706e	4785	#define BR_UART_ET7816_TXTHRESHOLD(x) (HW_UART_ET7816(x).B.TXTHRESHOLD)
bogdanm	82:6473597d706e	4786	#endif
bogdanm	82:6473597d706e	4787
bogdanm	82:6473597d706e	4788	//! @brief Format value for bitfield UART_ET7816_TXTHRESHOLD.
bogdanm	82:6473597d706e	4789	#define BF_UART_ET7816_TXTHRESHOLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_ET7816_TXTHRESHOLD), uint8_t) & BM_UART_ET7816_TXTHRESHOLD)
bogdanm	82:6473597d706e	4790
bogdanm	82:6473597d706e	4791	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4792	//! @brief Set the TXTHRESHOLD field to a new value.
bogdanm	82:6473597d706e	4793	#define BW_UART_ET7816_TXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_TXTHRESHOLD) \| BF_UART_ET7816_TXTHRESHOLD(v)))
bogdanm	82:6473597d706e	4794	#endif
bogdanm	82:6473597d706e	4795	//@}
bogdanm	82:6473597d706e	4796
bogdanm	82:6473597d706e	4797	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4798	// HW_UART_TL7816 - UART 7816 Transmit Length Register
bogdanm	82:6473597d706e	4799	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4800
bogdanm	82:6473597d706e	4801	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4802	/*!
bogdanm	82:6473597d706e	4803	* @brief HW_UART_TL7816 - UART 7816 Transmit Length Register (RW)
bogdanm	82:6473597d706e	4804	*
bogdanm	82:6473597d706e	4805	* Reset value: 0x00U
bogdanm	82:6473597d706e	4806	*
bogdanm	82:6473597d706e	4807	* The TL7816 register is used to indicate the number of characters contained in
bogdanm	82:6473597d706e	4808	* the block being transmitted. This register is used only when C7816[TTYPE] =
bogdanm	82:6473597d706e	4809	* 1. This register may be read at anytime. This register must be written only
bogdanm	82:6473597d706e	4810	* when C2[TE] is not enabled.
bogdanm	82:6473597d706e	4811	*/
bogdanm	82:6473597d706e	4812	typedef union _hw_uart_tl7816
bogdanm	82:6473597d706e	4813	{
bogdanm	82:6473597d706e	4814	uint8_t U;
bogdanm	82:6473597d706e	4815	struct _hw_uart_tl7816_bitfields
bogdanm	82:6473597d706e	4816	{
bogdanm	82:6473597d706e	4817	uint8_t TLEN : 8; //!< [7:0] Transmit Length
bogdanm	82:6473597d706e	4818	} B;
bogdanm	82:6473597d706e	4819	} hw_uart_tl7816_t;
bogdanm	82:6473597d706e	4820	#endif
bogdanm	82:6473597d706e	4821
bogdanm	82:6473597d706e	4822	/*!
bogdanm	82:6473597d706e	4823	* @name Constants and macros for entire UART_TL7816 register
bogdanm	82:6473597d706e	4824	*/
bogdanm	82:6473597d706e	4825	//@{
bogdanm	82:6473597d706e	4826	#define HW_UART_TL7816_ADDR(x) (REGS_UART_BASE(x) + 0x1FU)
bogdanm	82:6473597d706e	4827
bogdanm	82:6473597d706e	4828	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4829	#define HW_UART_TL7816(x) ((__IO hw_uart_tl7816_t ) HW_UART_TL7816_ADDR(x))
bogdanm	82:6473597d706e	4830	#define HW_UART_TL7816_RD(x) (HW_UART_TL7816(x).U)
bogdanm	82:6473597d706e	4831	#define HW_UART_TL7816_WR(x, v) (HW_UART_TL7816(x).U = (v))
bogdanm	82:6473597d706e	4832	#define HW_UART_TL7816_SET(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) \| (v)))
bogdanm	82:6473597d706e	4833	#define HW_UART_TL7816_CLR(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) & ~(v)))
bogdanm	82:6473597d706e	4834	#define HW_UART_TL7816_TOG(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) ^ (v)))
bogdanm	82:6473597d706e	4835	#endif
bogdanm	82:6473597d706e	4836	//@}
bogdanm	82:6473597d706e	4837
bogdanm	82:6473597d706e	4838	/*
bogdanm	82:6473597d706e	4839	* Constants & macros for individual UART_TL7816 bitfields
bogdanm	82:6473597d706e	4840	*/
bogdanm	82:6473597d706e	4841
bogdanm	82:6473597d706e	4842	/*!
bogdanm	82:6473597d706e	4843	* @name Register UART_TL7816, field TLEN[7:0] (RW)
bogdanm	82:6473597d706e	4844	*
bogdanm	82:6473597d706e	4845	* This value plus four indicates the number of characters contained in the
bogdanm	82:6473597d706e	4846	* block being transmitted. This register is automatically decremented by 1 for each
bogdanm	82:6473597d706e	4847	* character in the information field portion of the block. Additionally, this
bogdanm	82:6473597d706e	4848	* register is automatically decremented by 1 for the first character of a CRC in
bogdanm	82:6473597d706e	4849	* the epilogue field. Therefore, this register must be programmed with the number
bogdanm	82:6473597d706e	4850	* of bytes in the data packet if an LRC is being transmitted, and the number of
bogdanm	82:6473597d706e	4851	* bytes + 1 if a CRC is being transmitted. This register is not decremented for
bogdanm	82:6473597d706e	4852	* characters that are assumed to be part of the Prologue field, that is, the
bogdanm	82:6473597d706e	4853	* first three characters transmitted in a block, or the LRC or last CRC character
bogdanm	82:6473597d706e	4854	* in the Epilogue field, that is, the last character transmitted. This field
bogdanm	82:6473597d706e	4855	* must be programed or adjusted only when C2[TE] is cleared.
bogdanm	82:6473597d706e	4856	*/
bogdanm	82:6473597d706e	4857	//@{
bogdanm	82:6473597d706e	4858	#define BP_UART_TL7816_TLEN (0U) //!< Bit position for UART_TL7816_TLEN.
bogdanm	82:6473597d706e	4859	#define BM_UART_TL7816_TLEN (0xFFU) //!< Bit mask for UART_TL7816_TLEN.
bogdanm	82:6473597d706e	4860	#define BS_UART_TL7816_TLEN (8U) //!< Bit field size in bits for UART_TL7816_TLEN.
bogdanm	82:6473597d706e	4861
bogdanm	82:6473597d706e	4862	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4863	//! @brief Read current value of the UART_TL7816_TLEN field.
bogdanm	82:6473597d706e	4864	#define BR_UART_TL7816_TLEN(x) (HW_UART_TL7816(x).U)
bogdanm	82:6473597d706e	4865	#endif
bogdanm	82:6473597d706e	4866
bogdanm	82:6473597d706e	4867	//! @brief Format value for bitfield UART_TL7816_TLEN.
bogdanm	82:6473597d706e	4868	#define BF_UART_TL7816_TLEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_TL7816_TLEN), uint8_t) & BM_UART_TL7816_TLEN)
bogdanm	82:6473597d706e	4869
bogdanm	82:6473597d706e	4870	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4871	//! @brief Set the TLEN field to a new value.
bogdanm	82:6473597d706e	4872	#define BW_UART_TL7816_TLEN(x, v) (HW_UART_TL7816_WR(x, v))
bogdanm	82:6473597d706e	4873	#endif
bogdanm	82:6473597d706e	4874	//@}
bogdanm	82:6473597d706e	4875
bogdanm	82:6473597d706e	4876	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4877	// hw_uart_t - module struct
bogdanm	82:6473597d706e	4878	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4879	/*!
bogdanm	82:6473597d706e	4880	* @brief All UART module registers.
bogdanm	82:6473597d706e	4881	*/
bogdanm	82:6473597d706e	4882	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4883	#pragma pack(1)
bogdanm	82:6473597d706e	4884	typedef struct _hw_uart
bogdanm	82:6473597d706e	4885	{
bogdanm	82:6473597d706e	4886	__IO hw_uart_bdh_t BDH; //!< [0x0] UART Baud Rate Registers: High
bogdanm	82:6473597d706e	4887	__IO hw_uart_bdl_t BDL; //!< [0x1] UART Baud Rate Registers: Low
bogdanm	82:6473597d706e	4888	__IO hw_uart_c1_t C1; //!< [0x2] UART Control Register 1
bogdanm	82:6473597d706e	4889	__IO hw_uart_c2_t C2; //!< [0x3] UART Control Register 2
bogdanm	82:6473597d706e	4890	__I hw_uart_s1_t S1; //!< [0x4] UART Status Register 1
bogdanm	82:6473597d706e	4891	__IO hw_uart_s2_t S2; //!< [0x5] UART Status Register 2
bogdanm	82:6473597d706e	4892	__IO hw_uart_c3_t C3; //!< [0x6] UART Control Register 3
bogdanm	82:6473597d706e	4893	__IO hw_uart_d_t D; //!< [0x7] UART Data Register
bogdanm	82:6473597d706e	4894	__IO hw_uart_ma1_t MA1; //!< [0x8] UART Match Address Registers 1
bogdanm	82:6473597d706e	4895	__IO hw_uart_ma2_t MA2; //!< [0x9] UART Match Address Registers 2
bogdanm	82:6473597d706e	4896	__IO hw_uart_c4_t C4; //!< [0xA] UART Control Register 4
bogdanm	82:6473597d706e	4897	__IO hw_uart_c5_t C5; //!< [0xB] UART Control Register 5
bogdanm	82:6473597d706e	4898	__I hw_uart_ed_t ED; //!< [0xC] UART Extended Data Register
bogdanm	82:6473597d706e	4899	__IO hw_uart_modem_t MODEM; //!< [0xD] UART Modem Register
bogdanm	82:6473597d706e	4900	__IO hw_uart_ir_t IR; //!< [0xE] UART Infrared Register
bogdanm	82:6473597d706e	4901	uint8_t _reserved0[1];
bogdanm	82:6473597d706e	4902	__IO hw_uart_pfifo_t PFIFO; //!< [0x10] UART FIFO Parameters
bogdanm	82:6473597d706e	4903	__IO hw_uart_cfifo_t CFIFO; //!< [0x11] UART FIFO Control Register
bogdanm	82:6473597d706e	4904	__IO hw_uart_sfifo_t SFIFO; //!< [0x12] UART FIFO Status Register
bogdanm	82:6473597d706e	4905	__IO hw_uart_twfifo_t TWFIFO; //!< [0x13] UART FIFO Transmit Watermark
bogdanm	82:6473597d706e	4906	__I hw_uart_tcfifo_t TCFIFO; //!< [0x14] UART FIFO Transmit Count
bogdanm	82:6473597d706e	4907	__IO hw_uart_rwfifo_t RWFIFO; //!< [0x15] UART FIFO Receive Watermark
bogdanm	82:6473597d706e	4908	__I hw_uart_rcfifo_t RCFIFO; //!< [0x16] UART FIFO Receive Count
bogdanm	82:6473597d706e	4909	uint8_t _reserved1[1];
bogdanm	82:6473597d706e	4910	__IO hw_uart_c7816_t C7816; //!< [0x18] UART 7816 Control Register
bogdanm	82:6473597d706e	4911	__IO hw_uart_ie7816_t IE7816; //!< [0x19] UART 7816 Interrupt Enable Register
bogdanm	82:6473597d706e	4912	__IO hw_uart_is7816_t IS7816; //!< [0x1A] UART 7816 Interrupt Status Register
bogdanm	82:6473597d706e	4913	union {
bogdanm	82:6473597d706e	4914	__IO hw_uart_wp7816_t_type0_t WP7816_T_TYPE0; //!< [0x1B] UART 7816 Wait Parameter Register
bogdanm	82:6473597d706e	4915	__IO hw_uart_wp7816_t_type1_t WP7816_T_TYPE1; //!< [0x1B] UART 7816 Wait Parameter Register
bogdanm	82:6473597d706e	4916	};
bogdanm	82:6473597d706e	4917	__IO hw_uart_wn7816_t WN7816; //!< [0x1C] UART 7816 Wait N Register
bogdanm	82:6473597d706e	4918	__IO hw_uart_wf7816_t WF7816; //!< [0x1D] UART 7816 Wait FD Register
bogdanm	82:6473597d706e	4919	__IO hw_uart_et7816_t ET7816; //!< [0x1E] UART 7816 Error Threshold Register
bogdanm	82:6473597d706e	4920	__IO hw_uart_tl7816_t TL7816; //!< [0x1F] UART 7816 Transmit Length Register
bogdanm	82:6473597d706e	4921	} hw_uart_t;
bogdanm	82:6473597d706e	4922	#pragma pack()
bogdanm	82:6473597d706e	4923
bogdanm	82:6473597d706e	4924	//! @brief Macro to access all UART registers.
bogdanm	82:6473597d706e	4925	//! @param x UART instance number.
bogdanm	82:6473597d706e	4926	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	4927	//! use the '&' operator, like <code>&HW_UART(0)</code>.
bogdanm	82:6473597d706e	4928	#define HW_UART(x) ((hw_uart_t ) REGS_UART_BASE(x))
bogdanm	82:6473597d706e	4929	#endif
bogdanm	82:6473597d706e	4930
bogdanm	82:6473597d706e	4931	#endif // __HW_UART_REGISTERS_H__
bogdanm	82:6473597d706e	4932	// v22/130726/0.9
bogdanm	82:6473597d706e	4933	// EOF

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	25 Jun 2015
Imports:	24
Forks:	0
Commits:	103
Dependents:	1
Dependencies:	0
Followers:	1

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_uart.h@89:552587b429a1, 2014-09-12 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning