mbed - mbed library

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mbed library

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_spi.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_spi.h@82:6473597d706e

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_SPI_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_SPI_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 SPI
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Serial Peripheral Interface
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_SPI_MCR - Module Configuration Register
bogdanm	82:6473597d706e	33	* - HW_SPI_TCR - Transfer Count Register
bogdanm	82:6473597d706e	34	* - HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
bogdanm	82:6473597d706e	35	* - HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
bogdanm	82:6473597d706e	36	* - HW_SPI_SR - Status Register
bogdanm	82:6473597d706e	37	* - HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
bogdanm	82:6473597d706e	38	* - HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
bogdanm	82:6473597d706e	39	* - HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
bogdanm	82:6473597d706e	40	* - HW_SPI_POPR - POP RX FIFO Register
bogdanm	82:6473597d706e	41	* - HW_SPI_TXFRn - Transmit FIFO Registers
bogdanm	82:6473597d706e	42	* - HW_SPI_RXFRn - Receive FIFO Registers
bogdanm	82:6473597d706e	43	*
bogdanm	82:6473597d706e	44	* - hw_spi_t - Struct containing all module registers.
bogdanm	82:6473597d706e	45	*/
bogdanm	82:6473597d706e	46
bogdanm	82:6473597d706e	47	//! @name Module base addresses
bogdanm	82:6473597d706e	48	//@{
bogdanm	82:6473597d706e	49	#ifndef REGS_SPI_BASE
bogdanm	82:6473597d706e	50	#define HW_SPI_INSTANCE_COUNT (3U) //!< Number of instances of the SPI module.
bogdanm	82:6473597d706e	51	#define HW_SPI0 (0U) //!< Instance number for SPI0.
bogdanm	82:6473597d706e	52	#define HW_SPI1 (1U) //!< Instance number for SPI1.
bogdanm	82:6473597d706e	53	#define HW_SPI2 (2U) //!< Instance number for SPI2.
bogdanm	82:6473597d706e	54	#define REGS_SPI0_BASE (0x4002C000U) //!< Base address for SPI0.
bogdanm	82:6473597d706e	55	#define REGS_SPI1_BASE (0x4002D000U) //!< Base address for SPI1.
bogdanm	82:6473597d706e	56	#define REGS_SPI2_BASE (0x400AC000U) //!< Base address for SPI2.
bogdanm	82:6473597d706e	57
bogdanm	82:6473597d706e	58	//! @brief Table of base addresses for SPI instances.
bogdanm	82:6473597d706e	59	static const uint32_t __g_regs_SPI_base_addresses[] = {
bogdanm	82:6473597d706e	60	REGS_SPI0_BASE,
bogdanm	82:6473597d706e	61	REGS_SPI1_BASE,
bogdanm	82:6473597d706e	62	REGS_SPI2_BASE,
bogdanm	82:6473597d706e	63	};
bogdanm	82:6473597d706e	64
bogdanm	82:6473597d706e	65	//! @brief Get the base address of SPI by instance number.
bogdanm	82:6473597d706e	66	//! @param x SPI instance number, from 0 through 2.
bogdanm	82:6473597d706e	67	#define REGS_SPI_BASE(x) (__g_regs_SPI_base_addresses[(x)])
bogdanm	82:6473597d706e	68
bogdanm	82:6473597d706e	69	//! @brief Get the instance number given a base address.
bogdanm	82:6473597d706e	70	//! @param b Base address for an instance of SPI.
bogdanm	82:6473597d706e	71	#define REGS_SPI_INSTANCE(b) ((b) == REGS_SPI0_BASE ? HW_SPI0 : (b) == REGS_SPI1_BASE ? HW_SPI1 : (b) == REGS_SPI2_BASE ? HW_SPI2 : 0)
bogdanm	82:6473597d706e	72	#endif
bogdanm	82:6473597d706e	73	//@}
bogdanm	82:6473597d706e	74
bogdanm	82:6473597d706e	75	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	76	// HW_SPI_MCR - Module Configuration Register
bogdanm	82:6473597d706e	77	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	78
bogdanm	82:6473597d706e	79	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	80	/*!
bogdanm	82:6473597d706e	81	* @brief HW_SPI_MCR - Module Configuration Register (RW)
bogdanm	82:6473597d706e	82	*
bogdanm	82:6473597d706e	83	* Reset value: 0x00004001U
bogdanm	82:6473597d706e	84	*
bogdanm	82:6473597d706e	85	* Contains bits to configure various attributes associated with the module
bogdanm	82:6473597d706e	86	* operations. The HALT and MDIS bits can be changed at any time, but the effect
bogdanm	82:6473597d706e	87	* takes place only on the next frame boundary. Only the HALT and MDIS bits in the
bogdanm	82:6473597d706e	88	* MCR can be changed, while the module is in the Running state.
bogdanm	82:6473597d706e	89	*/
bogdanm	82:6473597d706e	90	typedef union _hw_spi_mcr
bogdanm	82:6473597d706e	91	{
bogdanm	82:6473597d706e	92	uint32_t U;
bogdanm	82:6473597d706e	93	struct _hw_spi_mcr_bitfields
bogdanm	82:6473597d706e	94	{
bogdanm	82:6473597d706e	95	uint32_t HALT : 1; //!< [0] Halt
bogdanm	82:6473597d706e	96	uint32_t RESERVED0 : 7; //!< [7:1]
bogdanm	82:6473597d706e	97	uint32_t SMPL_PT : 2; //!< [9:8] Sample Point
bogdanm	82:6473597d706e	98	uint32_t CLR_RXF : 1; //!< [10]
bogdanm	82:6473597d706e	99	uint32_t CLR_TXF : 1; //!< [11] Clear TX FIFO
bogdanm	82:6473597d706e	100	uint32_t DIS_RXF : 1; //!< [12] Disable Receive FIFO
bogdanm	82:6473597d706e	101	uint32_t DIS_TXF : 1; //!< [13] Disable Transmit FIFO
bogdanm	82:6473597d706e	102	uint32_t MDIS : 1; //!< [14] Module Disable
bogdanm	82:6473597d706e	103	uint32_t DOZE : 1; //!< [15] Doze Enable
bogdanm	82:6473597d706e	104	uint32_t PCSIS : 6; //!< [21:16] Peripheral Chip Select x Inactive
bogdanm	82:6473597d706e	105	//! State
bogdanm	82:6473597d706e	106	uint32_t RESERVED1 : 2; //!< [23:22]
bogdanm	82:6473597d706e	107	uint32_t ROOE : 1; //!< [24] Receive FIFO Overflow Overwrite Enable
bogdanm	82:6473597d706e	108	uint32_t PCSSE : 1; //!< [25] Peripheral Chip Select Strobe Enable
bogdanm	82:6473597d706e	109	uint32_t MTFE : 1; //!< [26] Modified Timing Format Enable
bogdanm	82:6473597d706e	110	uint32_t FRZ : 1; //!< [27] Freeze
bogdanm	82:6473597d706e	111	uint32_t DCONF : 2; //!< [29:28] SPI Configuration.
bogdanm	82:6473597d706e	112	uint32_t CONT_SCKE : 1; //!< [30] Continuous SCK Enable
bogdanm	82:6473597d706e	113	uint32_t MSTR : 1; //!< [31] Master/Slave Mode Select
bogdanm	82:6473597d706e	114	} B;
bogdanm	82:6473597d706e	115	} hw_spi_mcr_t;
bogdanm	82:6473597d706e	116	#endif
bogdanm	82:6473597d706e	117
bogdanm	82:6473597d706e	118	/*!
bogdanm	82:6473597d706e	119	* @name Constants and macros for entire SPI_MCR register
bogdanm	82:6473597d706e	120	*/
bogdanm	82:6473597d706e	121	//@{
bogdanm	82:6473597d706e	122	#define HW_SPI_MCR_ADDR(x) (REGS_SPI_BASE(x) + 0x0U)
bogdanm	82:6473597d706e	123
bogdanm	82:6473597d706e	124	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	125	#define HW_SPI_MCR(x) ((__IO hw_spi_mcr_t ) HW_SPI_MCR_ADDR(x))
bogdanm	82:6473597d706e	126	#define HW_SPI_MCR_RD(x) (HW_SPI_MCR(x).U)
bogdanm	82:6473597d706e	127	#define HW_SPI_MCR_WR(x, v) (HW_SPI_MCR(x).U = (v))
bogdanm	82:6473597d706e	128	#define HW_SPI_MCR_SET(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) \| (v)))
bogdanm	82:6473597d706e	129	#define HW_SPI_MCR_CLR(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	130	#define HW_SPI_MCR_TOG(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	131	#endif
bogdanm	82:6473597d706e	132	//@}
bogdanm	82:6473597d706e	133
bogdanm	82:6473597d706e	134	/*
bogdanm	82:6473597d706e	135	* Constants & macros for individual SPI_MCR bitfields
bogdanm	82:6473597d706e	136	*/
bogdanm	82:6473597d706e	137
bogdanm	82:6473597d706e	138	/*!
bogdanm	82:6473597d706e	139	* @name Register SPI_MCR, field HALT[0] (RW)
bogdanm	82:6473597d706e	140	*
bogdanm	82:6473597d706e	141	* The HALT bit starts and stops frame transfers. See Start and Stop of Module
bogdanm	82:6473597d706e	142	* transfers
bogdanm	82:6473597d706e	143	*
bogdanm	82:6473597d706e	144	* Values:
bogdanm	82:6473597d706e	145	* - 0 - Start transfers.
bogdanm	82:6473597d706e	146	* - 1 - Stop transfers.
bogdanm	82:6473597d706e	147	*/
bogdanm	82:6473597d706e	148	//@{
bogdanm	82:6473597d706e	149	#define BP_SPI_MCR_HALT (0U) //!< Bit position for SPI_MCR_HALT.
bogdanm	82:6473597d706e	150	#define BM_SPI_MCR_HALT (0x00000001U) //!< Bit mask for SPI_MCR_HALT.
bogdanm	82:6473597d706e	151	#define BS_SPI_MCR_HALT (1U) //!< Bit field size in bits for SPI_MCR_HALT.
bogdanm	82:6473597d706e	152
bogdanm	82:6473597d706e	153	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	154	//! @brief Read current value of the SPI_MCR_HALT field.
bogdanm	82:6473597d706e	155	#define BR_SPI_MCR_HALT(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT))
bogdanm	82:6473597d706e	156	#endif
bogdanm	82:6473597d706e	157
bogdanm	82:6473597d706e	158	//! @brief Format value for bitfield SPI_MCR_HALT.
bogdanm	82:6473597d706e	159	#define BF_SPI_MCR_HALT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_HALT), uint32_t) & BM_SPI_MCR_HALT)
bogdanm	82:6473597d706e	160
bogdanm	82:6473597d706e	161	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	162	//! @brief Set the HALT field to a new value.
bogdanm	82:6473597d706e	163	#define BW_SPI_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT) = (v))
bogdanm	82:6473597d706e	164	#endif
bogdanm	82:6473597d706e	165	//@}
bogdanm	82:6473597d706e	166
bogdanm	82:6473597d706e	167	/*!
bogdanm	82:6473597d706e	168	* @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
bogdanm	82:6473597d706e	169	*
bogdanm	82:6473597d706e	170	* Controls when the module master samples SIN in Modified Transfer Format. This
bogdanm	82:6473597d706e	171	* field is valid only when CPHA bit in CTARn[CPHA] is 0.
bogdanm	82:6473597d706e	172	*
bogdanm	82:6473597d706e	173	* Values:
bogdanm	82:6473597d706e	174	* - 00 - 0 protocol clock cycles between SCK edge and SIN sample
bogdanm	82:6473597d706e	175	* - 01 - 1 protocol clock cycle between SCK edge and SIN sample
bogdanm	82:6473597d706e	176	* - 10 - 2 protocol clock cycles between SCK edge and SIN sample
bogdanm	82:6473597d706e	177	* - 11 - Reserved
bogdanm	82:6473597d706e	178	*/
bogdanm	82:6473597d706e	179	//@{
bogdanm	82:6473597d706e	180	#define BP_SPI_MCR_SMPL_PT (8U) //!< Bit position for SPI_MCR_SMPL_PT.
bogdanm	82:6473597d706e	181	#define BM_SPI_MCR_SMPL_PT (0x00000300U) //!< Bit mask for SPI_MCR_SMPL_PT.
bogdanm	82:6473597d706e	182	#define BS_SPI_MCR_SMPL_PT (2U) //!< Bit field size in bits for SPI_MCR_SMPL_PT.
bogdanm	82:6473597d706e	183
bogdanm	82:6473597d706e	184	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	185	//! @brief Read current value of the SPI_MCR_SMPL_PT field.
bogdanm	82:6473597d706e	186	#define BR_SPI_MCR_SMPL_PT(x) (HW_SPI_MCR(x).B.SMPL_PT)
bogdanm	82:6473597d706e	187	#endif
bogdanm	82:6473597d706e	188
bogdanm	82:6473597d706e	189	//! @brief Format value for bitfield SPI_MCR_SMPL_PT.
bogdanm	82:6473597d706e	190	#define BF_SPI_MCR_SMPL_PT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_SMPL_PT), uint32_t) & BM_SPI_MCR_SMPL_PT)
bogdanm	82:6473597d706e	191
bogdanm	82:6473597d706e	192	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	193	//! @brief Set the SMPL_PT field to a new value.
bogdanm	82:6473597d706e	194	#define BW_SPI_MCR_SMPL_PT(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_SMPL_PT) \| BF_SPI_MCR_SMPL_PT(v)))
bogdanm	82:6473597d706e	195	#endif
bogdanm	82:6473597d706e	196	//@}
bogdanm	82:6473597d706e	197
bogdanm	82:6473597d706e	198	/*!
bogdanm	82:6473597d706e	199	* @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
bogdanm	82:6473597d706e	200	*
bogdanm	82:6473597d706e	201	* Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
bogdanm	82:6473597d706e	202	* CLR_RXF bit is always read as zero.
bogdanm	82:6473597d706e	203	*
bogdanm	82:6473597d706e	204	* Values:
bogdanm	82:6473597d706e	205	* - 0 - Do not clear the RX FIFO counter.
bogdanm	82:6473597d706e	206	* - 1 - Clear the RX FIFO counter.
bogdanm	82:6473597d706e	207	*/
bogdanm	82:6473597d706e	208	//@{
bogdanm	82:6473597d706e	209	#define BP_SPI_MCR_CLR_RXF (10U) //!< Bit position for SPI_MCR_CLR_RXF.
bogdanm	82:6473597d706e	210	#define BM_SPI_MCR_CLR_RXF (0x00000400U) //!< Bit mask for SPI_MCR_CLR_RXF.
bogdanm	82:6473597d706e	211	#define BS_SPI_MCR_CLR_RXF (1U) //!< Bit field size in bits for SPI_MCR_CLR_RXF.
bogdanm	82:6473597d706e	212
bogdanm	82:6473597d706e	213	//! @brief Format value for bitfield SPI_MCR_CLR_RXF.
bogdanm	82:6473597d706e	214	#define BF_SPI_MCR_CLR_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CLR_RXF), uint32_t) & BM_SPI_MCR_CLR_RXF)
bogdanm	82:6473597d706e	215
bogdanm	82:6473597d706e	216	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	217	//! @brief Set the CLR_RXF field to a new value.
bogdanm	82:6473597d706e	218	#define BW_SPI_MCR_CLR_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_RXF) = (v))
bogdanm	82:6473597d706e	219	#endif
bogdanm	82:6473597d706e	220	//@}
bogdanm	82:6473597d706e	221
bogdanm	82:6473597d706e	222	/*!
bogdanm	82:6473597d706e	223	* @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
bogdanm	82:6473597d706e	224	*
bogdanm	82:6473597d706e	225	* Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
bogdanm	82:6473597d706e	226	* CLR_TXF bit is always read as zero.
bogdanm	82:6473597d706e	227	*
bogdanm	82:6473597d706e	228	* Values:
bogdanm	82:6473597d706e	229	* - 0 - Do not clear the TX FIFO counter.
bogdanm	82:6473597d706e	230	* - 1 - Clear the TX FIFO counter.
bogdanm	82:6473597d706e	231	*/
bogdanm	82:6473597d706e	232	//@{
bogdanm	82:6473597d706e	233	#define BP_SPI_MCR_CLR_TXF (11U) //!< Bit position for SPI_MCR_CLR_TXF.
bogdanm	82:6473597d706e	234	#define BM_SPI_MCR_CLR_TXF (0x00000800U) //!< Bit mask for SPI_MCR_CLR_TXF.
bogdanm	82:6473597d706e	235	#define BS_SPI_MCR_CLR_TXF (1U) //!< Bit field size in bits for SPI_MCR_CLR_TXF.
bogdanm	82:6473597d706e	236
bogdanm	82:6473597d706e	237	//! @brief Format value for bitfield SPI_MCR_CLR_TXF.
bogdanm	82:6473597d706e	238	#define BF_SPI_MCR_CLR_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CLR_TXF), uint32_t) & BM_SPI_MCR_CLR_TXF)
bogdanm	82:6473597d706e	239
bogdanm	82:6473597d706e	240	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	241	//! @brief Set the CLR_TXF field to a new value.
bogdanm	82:6473597d706e	242	#define BW_SPI_MCR_CLR_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_TXF) = (v))
bogdanm	82:6473597d706e	243	#endif
bogdanm	82:6473597d706e	244	//@}
bogdanm	82:6473597d706e	245
bogdanm	82:6473597d706e	246	/*!
bogdanm	82:6473597d706e	247	* @name Register SPI_MCR, field DIS_RXF[12] (RW)
bogdanm	82:6473597d706e	248	*
bogdanm	82:6473597d706e	249	* When the RX FIFO is disabled, the receive part of the module operates as a
bogdanm	82:6473597d706e	250	* simplified double-buffered SPI. This bit can only be written when the MDIS bit
bogdanm	82:6473597d706e	251	* is cleared.
bogdanm	82:6473597d706e	252	*
bogdanm	82:6473597d706e	253	* Values:
bogdanm	82:6473597d706e	254	* - 0 - RX FIFO is enabled.
bogdanm	82:6473597d706e	255	* - 1 - RX FIFO is disabled.
bogdanm	82:6473597d706e	256	*/
bogdanm	82:6473597d706e	257	//@{
bogdanm	82:6473597d706e	258	#define BP_SPI_MCR_DIS_RXF (12U) //!< Bit position for SPI_MCR_DIS_RXF.
bogdanm	82:6473597d706e	259	#define BM_SPI_MCR_DIS_RXF (0x00001000U) //!< Bit mask for SPI_MCR_DIS_RXF.
bogdanm	82:6473597d706e	260	#define BS_SPI_MCR_DIS_RXF (1U) //!< Bit field size in bits for SPI_MCR_DIS_RXF.
bogdanm	82:6473597d706e	261
bogdanm	82:6473597d706e	262	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	263	//! @brief Read current value of the SPI_MCR_DIS_RXF field.
bogdanm	82:6473597d706e	264	#define BR_SPI_MCR_DIS_RXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF))
bogdanm	82:6473597d706e	265	#endif
bogdanm	82:6473597d706e	266
bogdanm	82:6473597d706e	267	//! @brief Format value for bitfield SPI_MCR_DIS_RXF.
bogdanm	82:6473597d706e	268	#define BF_SPI_MCR_DIS_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DIS_RXF), uint32_t) & BM_SPI_MCR_DIS_RXF)
bogdanm	82:6473597d706e	269
bogdanm	82:6473597d706e	270	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	271	//! @brief Set the DIS_RXF field to a new value.
bogdanm	82:6473597d706e	272	#define BW_SPI_MCR_DIS_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF) = (v))
bogdanm	82:6473597d706e	273	#endif
bogdanm	82:6473597d706e	274	//@}
bogdanm	82:6473597d706e	275
bogdanm	82:6473597d706e	276	/*!
bogdanm	82:6473597d706e	277	* @name Register SPI_MCR, field DIS_TXF[13] (RW)
bogdanm	82:6473597d706e	278	*
bogdanm	82:6473597d706e	279	* When the TX FIFO is disabled, the transmit part of the module operates as a
bogdanm	82:6473597d706e	280	* simplified double-buffered SPI. This bit can be written only when the MDIS bit
bogdanm	82:6473597d706e	281	* is cleared.
bogdanm	82:6473597d706e	282	*
bogdanm	82:6473597d706e	283	* Values:
bogdanm	82:6473597d706e	284	* - 0 - TX FIFO is enabled.
bogdanm	82:6473597d706e	285	* - 1 - TX FIFO is disabled.
bogdanm	82:6473597d706e	286	*/
bogdanm	82:6473597d706e	287	//@{
bogdanm	82:6473597d706e	288	#define BP_SPI_MCR_DIS_TXF (13U) //!< Bit position for SPI_MCR_DIS_TXF.
bogdanm	82:6473597d706e	289	#define BM_SPI_MCR_DIS_TXF (0x00002000U) //!< Bit mask for SPI_MCR_DIS_TXF.
bogdanm	82:6473597d706e	290	#define BS_SPI_MCR_DIS_TXF (1U) //!< Bit field size in bits for SPI_MCR_DIS_TXF.
bogdanm	82:6473597d706e	291
bogdanm	82:6473597d706e	292	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	293	//! @brief Read current value of the SPI_MCR_DIS_TXF field.
bogdanm	82:6473597d706e	294	#define BR_SPI_MCR_DIS_TXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF))
bogdanm	82:6473597d706e	295	#endif
bogdanm	82:6473597d706e	296
bogdanm	82:6473597d706e	297	//! @brief Format value for bitfield SPI_MCR_DIS_TXF.
bogdanm	82:6473597d706e	298	#define BF_SPI_MCR_DIS_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DIS_TXF), uint32_t) & BM_SPI_MCR_DIS_TXF)
bogdanm	82:6473597d706e	299
bogdanm	82:6473597d706e	300	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	301	//! @brief Set the DIS_TXF field to a new value.
bogdanm	82:6473597d706e	302	#define BW_SPI_MCR_DIS_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF) = (v))
bogdanm	82:6473597d706e	303	#endif
bogdanm	82:6473597d706e	304	//@}
bogdanm	82:6473597d706e	305
bogdanm	82:6473597d706e	306	/*!
bogdanm	82:6473597d706e	307	* @name Register SPI_MCR, field MDIS[14] (RW)
bogdanm	82:6473597d706e	308	*
bogdanm	82:6473597d706e	309	* Allows the clock to be stopped to the non-memory mapped logic in the module
bogdanm	82:6473597d706e	310	* effectively putting it in a software-controlled power-saving state. The reset
bogdanm	82:6473597d706e	311	* value of the MDIS bit is parameterized, with a default reset value of 0. When
bogdanm	82:6473597d706e	312	* the module is used in Slave Mode, we recommend leaving this bit 0, because a
bogdanm	82:6473597d706e	313	* slave doesn't have control over master transactions.
bogdanm	82:6473597d706e	314	*
bogdanm	82:6473597d706e	315	* Values:
bogdanm	82:6473597d706e	316	* - 0 - Enables the module clocks.
bogdanm	82:6473597d706e	317	* - 1 - Allows external logic to disable the module clocks.
bogdanm	82:6473597d706e	318	*/
bogdanm	82:6473597d706e	319	//@{
bogdanm	82:6473597d706e	320	#define BP_SPI_MCR_MDIS (14U) //!< Bit position for SPI_MCR_MDIS.
bogdanm	82:6473597d706e	321	#define BM_SPI_MCR_MDIS (0x00004000U) //!< Bit mask for SPI_MCR_MDIS.
bogdanm	82:6473597d706e	322	#define BS_SPI_MCR_MDIS (1U) //!< Bit field size in bits for SPI_MCR_MDIS.
bogdanm	82:6473597d706e	323
bogdanm	82:6473597d706e	324	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	325	//! @brief Read current value of the SPI_MCR_MDIS field.
bogdanm	82:6473597d706e	326	#define BR_SPI_MCR_MDIS(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS))
bogdanm	82:6473597d706e	327	#endif
bogdanm	82:6473597d706e	328
bogdanm	82:6473597d706e	329	//! @brief Format value for bitfield SPI_MCR_MDIS.
bogdanm	82:6473597d706e	330	#define BF_SPI_MCR_MDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MDIS), uint32_t) & BM_SPI_MCR_MDIS)
bogdanm	82:6473597d706e	331
bogdanm	82:6473597d706e	332	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	333	//! @brief Set the MDIS field to a new value.
bogdanm	82:6473597d706e	334	#define BW_SPI_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS) = (v))
bogdanm	82:6473597d706e	335	#endif
bogdanm	82:6473597d706e	336	//@}
bogdanm	82:6473597d706e	337
bogdanm	82:6473597d706e	338	/*!
bogdanm	82:6473597d706e	339	* @name Register SPI_MCR, field DOZE[15] (RW)
bogdanm	82:6473597d706e	340	*
bogdanm	82:6473597d706e	341	* Provides support for an externally controlled Doze mode power-saving
bogdanm	82:6473597d706e	342	* mechanism.
bogdanm	82:6473597d706e	343	*
bogdanm	82:6473597d706e	344	* Values:
bogdanm	82:6473597d706e	345	* - 0 - Doze mode has no effect on the module.
bogdanm	82:6473597d706e	346	* - 1 - Doze mode disables the module.
bogdanm	82:6473597d706e	347	*/
bogdanm	82:6473597d706e	348	//@{
bogdanm	82:6473597d706e	349	#define BP_SPI_MCR_DOZE (15U) //!< Bit position for SPI_MCR_DOZE.
bogdanm	82:6473597d706e	350	#define BM_SPI_MCR_DOZE (0x00008000U) //!< Bit mask for SPI_MCR_DOZE.
bogdanm	82:6473597d706e	351	#define BS_SPI_MCR_DOZE (1U) //!< Bit field size in bits for SPI_MCR_DOZE.
bogdanm	82:6473597d706e	352
bogdanm	82:6473597d706e	353	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	354	//! @brief Read current value of the SPI_MCR_DOZE field.
bogdanm	82:6473597d706e	355	#define BR_SPI_MCR_DOZE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE))
bogdanm	82:6473597d706e	356	#endif
bogdanm	82:6473597d706e	357
bogdanm	82:6473597d706e	358	//! @brief Format value for bitfield SPI_MCR_DOZE.
bogdanm	82:6473597d706e	359	#define BF_SPI_MCR_DOZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DOZE), uint32_t) & BM_SPI_MCR_DOZE)
bogdanm	82:6473597d706e	360
bogdanm	82:6473597d706e	361	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	362	//! @brief Set the DOZE field to a new value.
bogdanm	82:6473597d706e	363	#define BW_SPI_MCR_DOZE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE) = (v))
bogdanm	82:6473597d706e	364	#endif
bogdanm	82:6473597d706e	365	//@}
bogdanm	82:6473597d706e	366
bogdanm	82:6473597d706e	367	/*!
bogdanm	82:6473597d706e	368	* @name Register SPI_MCR, field PCSIS[21:16] (RW)
bogdanm	82:6473597d706e	369	*
bogdanm	82:6473597d706e	370	* Determines the inactive state of PCSx.
bogdanm	82:6473597d706e	371	*
bogdanm	82:6473597d706e	372	* Values:
bogdanm	82:6473597d706e	373	* - 0 - The inactive state of PCSx is low.
bogdanm	82:6473597d706e	374	* - 1 - The inactive state of PCSx is high.
bogdanm	82:6473597d706e	375	*/
bogdanm	82:6473597d706e	376	//@{
bogdanm	82:6473597d706e	377	#define BP_SPI_MCR_PCSIS (16U) //!< Bit position for SPI_MCR_PCSIS.
bogdanm	82:6473597d706e	378	#define BM_SPI_MCR_PCSIS (0x003F0000U) //!< Bit mask for SPI_MCR_PCSIS.
bogdanm	82:6473597d706e	379	#define BS_SPI_MCR_PCSIS (6U) //!< Bit field size in bits for SPI_MCR_PCSIS.
bogdanm	82:6473597d706e	380
bogdanm	82:6473597d706e	381	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	382	//! @brief Read current value of the SPI_MCR_PCSIS field.
bogdanm	82:6473597d706e	383	#define BR_SPI_MCR_PCSIS(x) (HW_SPI_MCR(x).B.PCSIS)
bogdanm	82:6473597d706e	384	#endif
bogdanm	82:6473597d706e	385
bogdanm	82:6473597d706e	386	//! @brief Format value for bitfield SPI_MCR_PCSIS.
bogdanm	82:6473597d706e	387	#define BF_SPI_MCR_PCSIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_PCSIS), uint32_t) & BM_SPI_MCR_PCSIS)
bogdanm	82:6473597d706e	388
bogdanm	82:6473597d706e	389	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	390	//! @brief Set the PCSIS field to a new value.
bogdanm	82:6473597d706e	391	#define BW_SPI_MCR_PCSIS(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_PCSIS) \| BF_SPI_MCR_PCSIS(v)))
bogdanm	82:6473597d706e	392	#endif
bogdanm	82:6473597d706e	393	//@}
bogdanm	82:6473597d706e	394
bogdanm	82:6473597d706e	395	/*!
bogdanm	82:6473597d706e	396	* @name Register SPI_MCR, field ROOE[24] (RW)
bogdanm	82:6473597d706e	397	*
bogdanm	82:6473597d706e	398	* In the RX FIFO overflow condition, configures the module to ignore the
bogdanm	82:6473597d706e	399	* incoming serial data or overwrite existing data. If the RX FIFO is full and new data
bogdanm	82:6473597d706e	400	* is received, the data from the transfer, generating the overflow, is ignored
bogdanm	82:6473597d706e	401	* or shifted into the shift register.
bogdanm	82:6473597d706e	402	*
bogdanm	82:6473597d706e	403	* Values:
bogdanm	82:6473597d706e	404	* - 0 - Incoming data is ignored.
bogdanm	82:6473597d706e	405	* - 1 - Incoming data is shifted into the shift register.
bogdanm	82:6473597d706e	406	*/
bogdanm	82:6473597d706e	407	//@{
bogdanm	82:6473597d706e	408	#define BP_SPI_MCR_ROOE (24U) //!< Bit position for SPI_MCR_ROOE.
bogdanm	82:6473597d706e	409	#define BM_SPI_MCR_ROOE (0x01000000U) //!< Bit mask for SPI_MCR_ROOE.
bogdanm	82:6473597d706e	410	#define BS_SPI_MCR_ROOE (1U) //!< Bit field size in bits for SPI_MCR_ROOE.
bogdanm	82:6473597d706e	411
bogdanm	82:6473597d706e	412	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	413	//! @brief Read current value of the SPI_MCR_ROOE field.
bogdanm	82:6473597d706e	414	#define BR_SPI_MCR_ROOE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE))
bogdanm	82:6473597d706e	415	#endif
bogdanm	82:6473597d706e	416
bogdanm	82:6473597d706e	417	//! @brief Format value for bitfield SPI_MCR_ROOE.
bogdanm	82:6473597d706e	418	#define BF_SPI_MCR_ROOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_ROOE), uint32_t) & BM_SPI_MCR_ROOE)
bogdanm	82:6473597d706e	419
bogdanm	82:6473597d706e	420	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	421	//! @brief Set the ROOE field to a new value.
bogdanm	82:6473597d706e	422	#define BW_SPI_MCR_ROOE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE) = (v))
bogdanm	82:6473597d706e	423	#endif
bogdanm	82:6473597d706e	424	//@}
bogdanm	82:6473597d706e	425
bogdanm	82:6473597d706e	426	/*!
bogdanm	82:6473597d706e	427	* @name Register SPI_MCR, field PCSSE[25] (RW)
bogdanm	82:6473597d706e	428	*
bogdanm	82:6473597d706e	429	* Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
bogdanm	82:6473597d706e	430	*
bogdanm	82:6473597d706e	431	* Values:
bogdanm	82:6473597d706e	432	* - 0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
bogdanm	82:6473597d706e	433	* - 1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
bogdanm	82:6473597d706e	434	*/
bogdanm	82:6473597d706e	435	//@{
bogdanm	82:6473597d706e	436	#define BP_SPI_MCR_PCSSE (25U) //!< Bit position for SPI_MCR_PCSSE.
bogdanm	82:6473597d706e	437	#define BM_SPI_MCR_PCSSE (0x02000000U) //!< Bit mask for SPI_MCR_PCSSE.
bogdanm	82:6473597d706e	438	#define BS_SPI_MCR_PCSSE (1U) //!< Bit field size in bits for SPI_MCR_PCSSE.
bogdanm	82:6473597d706e	439
bogdanm	82:6473597d706e	440	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	441	//! @brief Read current value of the SPI_MCR_PCSSE field.
bogdanm	82:6473597d706e	442	#define BR_SPI_MCR_PCSSE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE))
bogdanm	82:6473597d706e	443	#endif
bogdanm	82:6473597d706e	444
bogdanm	82:6473597d706e	445	//! @brief Format value for bitfield SPI_MCR_PCSSE.
bogdanm	82:6473597d706e	446	#define BF_SPI_MCR_PCSSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_PCSSE), uint32_t) & BM_SPI_MCR_PCSSE)
bogdanm	82:6473597d706e	447
bogdanm	82:6473597d706e	448	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	449	//! @brief Set the PCSSE field to a new value.
bogdanm	82:6473597d706e	450	#define BW_SPI_MCR_PCSSE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE) = (v))
bogdanm	82:6473597d706e	451	#endif
bogdanm	82:6473597d706e	452	//@}
bogdanm	82:6473597d706e	453
bogdanm	82:6473597d706e	454	/*!
bogdanm	82:6473597d706e	455	* @name Register SPI_MCR, field MTFE[26] (RW)
bogdanm	82:6473597d706e	456	*
bogdanm	82:6473597d706e	457	* Enables a modified transfer format to be used.
bogdanm	82:6473597d706e	458	*
bogdanm	82:6473597d706e	459	* Values:
bogdanm	82:6473597d706e	460	* - 0 - Modified SPI transfer format disabled.
bogdanm	82:6473597d706e	461	* - 1 - Modified SPI transfer format enabled.
bogdanm	82:6473597d706e	462	*/
bogdanm	82:6473597d706e	463	//@{
bogdanm	82:6473597d706e	464	#define BP_SPI_MCR_MTFE (26U) //!< Bit position for SPI_MCR_MTFE.
bogdanm	82:6473597d706e	465	#define BM_SPI_MCR_MTFE (0x04000000U) //!< Bit mask for SPI_MCR_MTFE.
bogdanm	82:6473597d706e	466	#define BS_SPI_MCR_MTFE (1U) //!< Bit field size in bits for SPI_MCR_MTFE.
bogdanm	82:6473597d706e	467
bogdanm	82:6473597d706e	468	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	469	//! @brief Read current value of the SPI_MCR_MTFE field.
bogdanm	82:6473597d706e	470	#define BR_SPI_MCR_MTFE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE))
bogdanm	82:6473597d706e	471	#endif
bogdanm	82:6473597d706e	472
bogdanm	82:6473597d706e	473	//! @brief Format value for bitfield SPI_MCR_MTFE.
bogdanm	82:6473597d706e	474	#define BF_SPI_MCR_MTFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MTFE), uint32_t) & BM_SPI_MCR_MTFE)
bogdanm	82:6473597d706e	475
bogdanm	82:6473597d706e	476	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	477	//! @brief Set the MTFE field to a new value.
bogdanm	82:6473597d706e	478	#define BW_SPI_MCR_MTFE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE) = (v))
bogdanm	82:6473597d706e	479	#endif
bogdanm	82:6473597d706e	480	//@}
bogdanm	82:6473597d706e	481
bogdanm	82:6473597d706e	482	/*!
bogdanm	82:6473597d706e	483	* @name Register SPI_MCR, field FRZ[27] (RW)
bogdanm	82:6473597d706e	484	*
bogdanm	82:6473597d706e	485	* Enables transfers to be stopped on the next frame boundary when the device
bogdanm	82:6473597d706e	486	* enters Debug mode.
bogdanm	82:6473597d706e	487	*
bogdanm	82:6473597d706e	488	* Values:
bogdanm	82:6473597d706e	489	* - 0 - Do not halt serial transfers in Debug mode.
bogdanm	82:6473597d706e	490	* - 1 - Halt serial transfers in Debug mode.
bogdanm	82:6473597d706e	491	*/
bogdanm	82:6473597d706e	492	//@{
bogdanm	82:6473597d706e	493	#define BP_SPI_MCR_FRZ (27U) //!< Bit position for SPI_MCR_FRZ.
bogdanm	82:6473597d706e	494	#define BM_SPI_MCR_FRZ (0x08000000U) //!< Bit mask for SPI_MCR_FRZ.
bogdanm	82:6473597d706e	495	#define BS_SPI_MCR_FRZ (1U) //!< Bit field size in bits for SPI_MCR_FRZ.
bogdanm	82:6473597d706e	496
bogdanm	82:6473597d706e	497	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	498	//! @brief Read current value of the SPI_MCR_FRZ field.
bogdanm	82:6473597d706e	499	#define BR_SPI_MCR_FRZ(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ))
bogdanm	82:6473597d706e	500	#endif
bogdanm	82:6473597d706e	501
bogdanm	82:6473597d706e	502	//! @brief Format value for bitfield SPI_MCR_FRZ.
bogdanm	82:6473597d706e	503	#define BF_SPI_MCR_FRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_FRZ), uint32_t) & BM_SPI_MCR_FRZ)
bogdanm	82:6473597d706e	504
bogdanm	82:6473597d706e	505	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	506	//! @brief Set the FRZ field to a new value.
bogdanm	82:6473597d706e	507	#define BW_SPI_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ) = (v))
bogdanm	82:6473597d706e	508	#endif
bogdanm	82:6473597d706e	509	//@}
bogdanm	82:6473597d706e	510
bogdanm	82:6473597d706e	511	/*!
bogdanm	82:6473597d706e	512	* @name Register SPI_MCR, field DCONF[29:28] (RO)
bogdanm	82:6473597d706e	513	*
bogdanm	82:6473597d706e	514	* Selects among the different configurations of the module.
bogdanm	82:6473597d706e	515	*
bogdanm	82:6473597d706e	516	* Values:
bogdanm	82:6473597d706e	517	* - 00 - SPI
bogdanm	82:6473597d706e	518	* - 01 - Reserved
bogdanm	82:6473597d706e	519	* - 10 - Reserved
bogdanm	82:6473597d706e	520	* - 11 - Reserved
bogdanm	82:6473597d706e	521	*/
bogdanm	82:6473597d706e	522	//@{
bogdanm	82:6473597d706e	523	#define BP_SPI_MCR_DCONF (28U) //!< Bit position for SPI_MCR_DCONF.
bogdanm	82:6473597d706e	524	#define BM_SPI_MCR_DCONF (0x30000000U) //!< Bit mask for SPI_MCR_DCONF.
bogdanm	82:6473597d706e	525	#define BS_SPI_MCR_DCONF (2U) //!< Bit field size in bits for SPI_MCR_DCONF.
bogdanm	82:6473597d706e	526
bogdanm	82:6473597d706e	527	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	528	//! @brief Read current value of the SPI_MCR_DCONF field.
bogdanm	82:6473597d706e	529	#define BR_SPI_MCR_DCONF(x) (HW_SPI_MCR(x).B.DCONF)
bogdanm	82:6473597d706e	530	#endif
bogdanm	82:6473597d706e	531	//@}
bogdanm	82:6473597d706e	532
bogdanm	82:6473597d706e	533	/*!
bogdanm	82:6473597d706e	534	* @name Register SPI_MCR, field CONT_SCKE[30] (RW)
bogdanm	82:6473597d706e	535	*
bogdanm	82:6473597d706e	536	* Enables the Serial Communication Clock (SCK) to run continuously.
bogdanm	82:6473597d706e	537	*
bogdanm	82:6473597d706e	538	* Values:
bogdanm	82:6473597d706e	539	* - 0 - Continuous SCK disabled.
bogdanm	82:6473597d706e	540	* - 1 - Continuous SCK enabled.
bogdanm	82:6473597d706e	541	*/
bogdanm	82:6473597d706e	542	//@{
bogdanm	82:6473597d706e	543	#define BP_SPI_MCR_CONT_SCKE (30U) //!< Bit position for SPI_MCR_CONT_SCKE.
bogdanm	82:6473597d706e	544	#define BM_SPI_MCR_CONT_SCKE (0x40000000U) //!< Bit mask for SPI_MCR_CONT_SCKE.
bogdanm	82:6473597d706e	545	#define BS_SPI_MCR_CONT_SCKE (1U) //!< Bit field size in bits for SPI_MCR_CONT_SCKE.
bogdanm	82:6473597d706e	546
bogdanm	82:6473597d706e	547	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	548	//! @brief Read current value of the SPI_MCR_CONT_SCKE field.
bogdanm	82:6473597d706e	549	#define BR_SPI_MCR_CONT_SCKE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE))
bogdanm	82:6473597d706e	550	#endif
bogdanm	82:6473597d706e	551
bogdanm	82:6473597d706e	552	//! @brief Format value for bitfield SPI_MCR_CONT_SCKE.
bogdanm	82:6473597d706e	553	#define BF_SPI_MCR_CONT_SCKE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CONT_SCKE), uint32_t) & BM_SPI_MCR_CONT_SCKE)
bogdanm	82:6473597d706e	554
bogdanm	82:6473597d706e	555	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	556	//! @brief Set the CONT_SCKE field to a new value.
bogdanm	82:6473597d706e	557	#define BW_SPI_MCR_CONT_SCKE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE) = (v))
bogdanm	82:6473597d706e	558	#endif
bogdanm	82:6473597d706e	559	//@}
bogdanm	82:6473597d706e	560
bogdanm	82:6473597d706e	561	/*!
bogdanm	82:6473597d706e	562	* @name Register SPI_MCR, field MSTR[31] (RW)
bogdanm	82:6473597d706e	563	*
bogdanm	82:6473597d706e	564	* Enables either Master mode (if supported) or Slave mode (if supported)
bogdanm	82:6473597d706e	565	* operation.
bogdanm	82:6473597d706e	566	*
bogdanm	82:6473597d706e	567	* Values:
bogdanm	82:6473597d706e	568	* - 0 - Enables Slave mode
bogdanm	82:6473597d706e	569	* - 1 - Enables Master mode
bogdanm	82:6473597d706e	570	*/
bogdanm	82:6473597d706e	571	//@{
bogdanm	82:6473597d706e	572	#define BP_SPI_MCR_MSTR (31U) //!< Bit position for SPI_MCR_MSTR.
bogdanm	82:6473597d706e	573	#define BM_SPI_MCR_MSTR (0x80000000U) //!< Bit mask for SPI_MCR_MSTR.
bogdanm	82:6473597d706e	574	#define BS_SPI_MCR_MSTR (1U) //!< Bit field size in bits for SPI_MCR_MSTR.
bogdanm	82:6473597d706e	575
bogdanm	82:6473597d706e	576	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	577	//! @brief Read current value of the SPI_MCR_MSTR field.
bogdanm	82:6473597d706e	578	#define BR_SPI_MCR_MSTR(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR))
bogdanm	82:6473597d706e	579	#endif
bogdanm	82:6473597d706e	580
bogdanm	82:6473597d706e	581	//! @brief Format value for bitfield SPI_MCR_MSTR.
bogdanm	82:6473597d706e	582	#define BF_SPI_MCR_MSTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MSTR), uint32_t) & BM_SPI_MCR_MSTR)
bogdanm	82:6473597d706e	583
bogdanm	82:6473597d706e	584	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	585	//! @brief Set the MSTR field to a new value.
bogdanm	82:6473597d706e	586	#define BW_SPI_MCR_MSTR(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR) = (v))
bogdanm	82:6473597d706e	587	#endif
bogdanm	82:6473597d706e	588	//@}
bogdanm	82:6473597d706e	589
bogdanm	82:6473597d706e	590	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	591	// HW_SPI_TCR - Transfer Count Register
bogdanm	82:6473597d706e	592	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	593
bogdanm	82:6473597d706e	594	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	595	/*!
bogdanm	82:6473597d706e	596	* @brief HW_SPI_TCR - Transfer Count Register (RW)
bogdanm	82:6473597d706e	597	*
bogdanm	82:6473597d706e	598	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	599	*
bogdanm	82:6473597d706e	600	* TCR contains a counter that indicates the number of SPI transfers made. The
bogdanm	82:6473597d706e	601	* transfer counter is intended to assist in queue management. Do not write the
bogdanm	82:6473597d706e	602	* TCR when the module is in the Running state.
bogdanm	82:6473597d706e	603	*/
bogdanm	82:6473597d706e	604	typedef union _hw_spi_tcr
bogdanm	82:6473597d706e	605	{
bogdanm	82:6473597d706e	606	uint32_t U;
bogdanm	82:6473597d706e	607	struct _hw_spi_tcr_bitfields
bogdanm	82:6473597d706e	608	{
bogdanm	82:6473597d706e	609	uint32_t RESERVED0 : 16; //!< [15:0]
bogdanm	82:6473597d706e	610	uint32_t SPI_TCNT : 16; //!< [31:16] SPI Transfer Counter
bogdanm	82:6473597d706e	611	} B;
bogdanm	82:6473597d706e	612	} hw_spi_tcr_t;
bogdanm	82:6473597d706e	613	#endif
bogdanm	82:6473597d706e	614
bogdanm	82:6473597d706e	615	/*!
bogdanm	82:6473597d706e	616	* @name Constants and macros for entire SPI_TCR register
bogdanm	82:6473597d706e	617	*/
bogdanm	82:6473597d706e	618	//@{
bogdanm	82:6473597d706e	619	#define HW_SPI_TCR_ADDR(x) (REGS_SPI_BASE(x) + 0x8U)
bogdanm	82:6473597d706e	620
bogdanm	82:6473597d706e	621	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	622	#define HW_SPI_TCR(x) ((__IO hw_spi_tcr_t ) HW_SPI_TCR_ADDR(x))
bogdanm	82:6473597d706e	623	#define HW_SPI_TCR_RD(x) (HW_SPI_TCR(x).U)
bogdanm	82:6473597d706e	624	#define HW_SPI_TCR_WR(x, v) (HW_SPI_TCR(x).U = (v))
bogdanm	82:6473597d706e	625	#define HW_SPI_TCR_SET(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) \| (v)))
bogdanm	82:6473597d706e	626	#define HW_SPI_TCR_CLR(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	627	#define HW_SPI_TCR_TOG(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	628	#endif
bogdanm	82:6473597d706e	629	//@}
bogdanm	82:6473597d706e	630
bogdanm	82:6473597d706e	631	/*
bogdanm	82:6473597d706e	632	* Constants & macros for individual SPI_TCR bitfields
bogdanm	82:6473597d706e	633	*/
bogdanm	82:6473597d706e	634
bogdanm	82:6473597d706e	635	/*!
bogdanm	82:6473597d706e	636	* @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
bogdanm	82:6473597d706e	637	*
bogdanm	82:6473597d706e	638	* Counts the number of SPI transfers the module makes. The SPI_TCNT field
bogdanm	82:6473597d706e	639	* increments every time the last bit of an SPI frame is transmitted. A value written
bogdanm	82:6473597d706e	640	* to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
bogdanm	82:6473597d706e	641	* the beginning of the frame when the CTCNT field is set in the executing SPI
bogdanm	82:6473597d706e	642	* command. The Transfer Counter wraps around; incrementing the counter past 65535
bogdanm	82:6473597d706e	643	* resets the counter to zero.
bogdanm	82:6473597d706e	644	*/
bogdanm	82:6473597d706e	645	//@{
bogdanm	82:6473597d706e	646	#define BP_SPI_TCR_SPI_TCNT (16U) //!< Bit position for SPI_TCR_SPI_TCNT.
bogdanm	82:6473597d706e	647	#define BM_SPI_TCR_SPI_TCNT (0xFFFF0000U) //!< Bit mask for SPI_TCR_SPI_TCNT.
bogdanm	82:6473597d706e	648	#define BS_SPI_TCR_SPI_TCNT (16U) //!< Bit field size in bits for SPI_TCR_SPI_TCNT.
bogdanm	82:6473597d706e	649
bogdanm	82:6473597d706e	650	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	651	//! @brief Read current value of the SPI_TCR_SPI_TCNT field.
bogdanm	82:6473597d706e	652	#define BR_SPI_TCR_SPI_TCNT(x) (HW_SPI_TCR(x).B.SPI_TCNT)
bogdanm	82:6473597d706e	653	#endif
bogdanm	82:6473597d706e	654
bogdanm	82:6473597d706e	655	//! @brief Format value for bitfield SPI_TCR_SPI_TCNT.
bogdanm	82:6473597d706e	656	#define BF_SPI_TCR_SPI_TCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_TCR_SPI_TCNT), uint32_t) & BM_SPI_TCR_SPI_TCNT)
bogdanm	82:6473597d706e	657
bogdanm	82:6473597d706e	658	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	659	//! @brief Set the SPI_TCNT field to a new value.
bogdanm	82:6473597d706e	660	#define BW_SPI_TCR_SPI_TCNT(x, v) (HW_SPI_TCR_WR(x, (HW_SPI_TCR_RD(x) & ~BM_SPI_TCR_SPI_TCNT) \| BF_SPI_TCR_SPI_TCNT(v)))
bogdanm	82:6473597d706e	661	#endif
bogdanm	82:6473597d706e	662	//@}
bogdanm	82:6473597d706e	663
bogdanm	82:6473597d706e	664	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	665	// HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
bogdanm	82:6473597d706e	666	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	667
bogdanm	82:6473597d706e	668	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	669	/*!
bogdanm	82:6473597d706e	670	* @brief HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) (RW)
bogdanm	82:6473597d706e	671	*
bogdanm	82:6473597d706e	672	* Reset value: 0x78000000U
bogdanm	82:6473597d706e	673	*
bogdanm	82:6473597d706e	674	* CTAR registers are used to define different transfer attributes. Do not write
bogdanm	82:6473597d706e	675	* to the CTAR registers while the module is in the Running state. In Master
bogdanm	82:6473597d706e	676	* mode, the CTAR registers define combinations of transfer attributes such as frame
bogdanm	82:6473597d706e	677	* size, clock phase and polarity, data bit ordering, baud rate, and various
bogdanm	82:6473597d706e	678	* delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
bogdanm	82:6473597d706e	679	* slave transfer attributes. When the module is configured as an SPI master, the
bogdanm	82:6473597d706e	680	* CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
bogdanm	82:6473597d706e	681	* registers is used. When the module is configured as an SPI bus slave, it uses
bogdanm	82:6473597d706e	682	* the CTAR0 register.
bogdanm	82:6473597d706e	683	*/
bogdanm	82:6473597d706e	684	typedef union _hw_spi_ctarn
bogdanm	82:6473597d706e	685	{
bogdanm	82:6473597d706e	686	uint32_t U;
bogdanm	82:6473597d706e	687	struct _hw_spi_ctarn_bitfields
bogdanm	82:6473597d706e	688	{
bogdanm	82:6473597d706e	689	uint32_t BR : 4; //!< [3:0] Baud Rate Scaler
bogdanm	82:6473597d706e	690	uint32_t DT : 4; //!< [7:4] Delay After Transfer Scaler
bogdanm	82:6473597d706e	691	uint32_t ASC : 4; //!< [11:8] After SCK Delay Scaler
bogdanm	82:6473597d706e	692	uint32_t CSSCK : 4; //!< [15:12] PCS to SCK Delay Scaler
bogdanm	82:6473597d706e	693	uint32_t PBR : 2; //!< [17:16] Baud Rate Prescaler
bogdanm	82:6473597d706e	694	uint32_t PDT : 2; //!< [19:18] Delay after Transfer Prescaler
bogdanm	82:6473597d706e	695	uint32_t PASC : 2; //!< [21:20] After SCK Delay Prescaler
bogdanm	82:6473597d706e	696	uint32_t PCSSCK : 2; //!< [23:22] PCS to SCK Delay Prescaler
bogdanm	82:6473597d706e	697	uint32_t LSBFE : 1; //!< [24] LSB First
bogdanm	82:6473597d706e	698	uint32_t CPHA : 1; //!< [25] Clock Phase
bogdanm	82:6473597d706e	699	uint32_t CPOL : 1; //!< [26] Clock Polarity
bogdanm	82:6473597d706e	700	uint32_t FMSZ : 4; //!< [30:27] Frame Size
bogdanm	82:6473597d706e	701	uint32_t DBR : 1; //!< [31] Double Baud Rate
bogdanm	82:6473597d706e	702	} B;
bogdanm	82:6473597d706e	703	} hw_spi_ctarn_t;
bogdanm	82:6473597d706e	704	#endif
bogdanm	82:6473597d706e	705
bogdanm	82:6473597d706e	706	/*!
bogdanm	82:6473597d706e	707	* @name Constants and macros for entire SPI_CTARn register
bogdanm	82:6473597d706e	708	*/
bogdanm	82:6473597d706e	709	//@{
bogdanm	82:6473597d706e	710	#define HW_SPI_CTARn_COUNT (2U)
bogdanm	82:6473597d706e	711
bogdanm	82:6473597d706e	712	#define HW_SPI_CTARn_ADDR(x, n) (REGS_SPI_BASE(x) + 0xCU + (0x4U * n))
bogdanm	82:6473597d706e	713
bogdanm	82:6473597d706e	714	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	715	#define HW_SPI_CTARn(x, n) ((__IO hw_spi_ctarn_t ) HW_SPI_CTARn_ADDR(x, n))
bogdanm	82:6473597d706e	716	#define HW_SPI_CTARn_RD(x, n) (HW_SPI_CTARn(x, n).U)
bogdanm	82:6473597d706e	717	#define HW_SPI_CTARn_WR(x, n, v) (HW_SPI_CTARn(x, n).U = (v))
bogdanm	82:6473597d706e	718	#define HW_SPI_CTARn_SET(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	719	#define HW_SPI_CTARn_CLR(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	720	#define HW_SPI_CTARn_TOG(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	721	#endif
bogdanm	82:6473597d706e	722	//@}
bogdanm	82:6473597d706e	723
bogdanm	82:6473597d706e	724	/*
bogdanm	82:6473597d706e	725	* Constants & macros for individual SPI_CTARn bitfields
bogdanm	82:6473597d706e	726	*/
bogdanm	82:6473597d706e	727
bogdanm	82:6473597d706e	728	/*!
bogdanm	82:6473597d706e	729	* @name Register SPI_CTARn, field BR[3:0] (RW)
bogdanm	82:6473597d706e	730	*
bogdanm	82:6473597d706e	731	* Selects the scaler value for the baud rate. This field is used only in master
bogdanm	82:6473597d706e	732	* mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
bogdanm	82:6473597d706e	733	* generate the frequency of the SCK. The baud rate is computed according to the
bogdanm	82:6473597d706e	734	* following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
bogdanm	82:6473597d706e	735	* lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
bogdanm	82:6473597d706e	736	* Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
bogdanm	82:6473597d706e	737	* 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
bogdanm	82:6473597d706e	738	*/
bogdanm	82:6473597d706e	739	//@{
bogdanm	82:6473597d706e	740	#define BP_SPI_CTARn_BR (0U) //!< Bit position for SPI_CTARn_BR.
bogdanm	82:6473597d706e	741	#define BM_SPI_CTARn_BR (0x0000000FU) //!< Bit mask for SPI_CTARn_BR.
bogdanm	82:6473597d706e	742	#define BS_SPI_CTARn_BR (4U) //!< Bit field size in bits for SPI_CTARn_BR.
bogdanm	82:6473597d706e	743
bogdanm	82:6473597d706e	744	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	745	//! @brief Read current value of the SPI_CTARn_BR field.
bogdanm	82:6473597d706e	746	#define BR_SPI_CTARn_BR(x, n) (HW_SPI_CTARn(x, n).B.BR)
bogdanm	82:6473597d706e	747	#endif
bogdanm	82:6473597d706e	748
bogdanm	82:6473597d706e	749	//! @brief Format value for bitfield SPI_CTARn_BR.
bogdanm	82:6473597d706e	750	#define BF_SPI_CTARn_BR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_BR), uint32_t) & BM_SPI_CTARn_BR)
bogdanm	82:6473597d706e	751
bogdanm	82:6473597d706e	752	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	753	//! @brief Set the BR field to a new value.
bogdanm	82:6473597d706e	754	#define BW_SPI_CTARn_BR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_BR) \| BF_SPI_CTARn_BR(v)))
bogdanm	82:6473597d706e	755	#endif
bogdanm	82:6473597d706e	756	//@}
bogdanm	82:6473597d706e	757
bogdanm	82:6473597d706e	758	/*!
bogdanm	82:6473597d706e	759	* @name Register SPI_CTARn, field DT[7:4] (RW)
bogdanm	82:6473597d706e	760	*
bogdanm	82:6473597d706e	761	* Selects the Delay after Transfer Scaler. This field is used only in master
bogdanm	82:6473597d706e	762	* mode. The Delay after Transfer is the time between the negation of the PCS
bogdanm	82:6473597d706e	763	* signal at the end of a frame and the assertion of PCS at the beginning of the next
bogdanm	82:6473597d706e	764	* frame. In the Continuous Serial Communications Clock operation, the DT value
bogdanm	82:6473597d706e	765	* is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
bogdanm	82:6473597d706e	766	* protocol clock period, and it is computed according to the following
bogdanm	82:6473597d706e	767	* equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
bogdanm	82:6473597d706e	768	* field description for scaler values.
bogdanm	82:6473597d706e	769	*/
bogdanm	82:6473597d706e	770	//@{
bogdanm	82:6473597d706e	771	#define BP_SPI_CTARn_DT (4U) //!< Bit position for SPI_CTARn_DT.
bogdanm	82:6473597d706e	772	#define BM_SPI_CTARn_DT (0x000000F0U) //!< Bit mask for SPI_CTARn_DT.
bogdanm	82:6473597d706e	773	#define BS_SPI_CTARn_DT (4U) //!< Bit field size in bits for SPI_CTARn_DT.
bogdanm	82:6473597d706e	774
bogdanm	82:6473597d706e	775	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	776	//! @brief Read current value of the SPI_CTARn_DT field.
bogdanm	82:6473597d706e	777	#define BR_SPI_CTARn_DT(x, n) (HW_SPI_CTARn(x, n).B.DT)
bogdanm	82:6473597d706e	778	#endif
bogdanm	82:6473597d706e	779
bogdanm	82:6473597d706e	780	//! @brief Format value for bitfield SPI_CTARn_DT.
bogdanm	82:6473597d706e	781	#define BF_SPI_CTARn_DT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_DT), uint32_t) & BM_SPI_CTARn_DT)
bogdanm	82:6473597d706e	782
bogdanm	82:6473597d706e	783	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	784	//! @brief Set the DT field to a new value.
bogdanm	82:6473597d706e	785	#define BW_SPI_CTARn_DT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_DT) \| BF_SPI_CTARn_DT(v)))
bogdanm	82:6473597d706e	786	#endif
bogdanm	82:6473597d706e	787	//@}
bogdanm	82:6473597d706e	788
bogdanm	82:6473597d706e	789	/*!
bogdanm	82:6473597d706e	790	* @name Register SPI_CTARn, field ASC[11:8] (RW)
bogdanm	82:6473597d706e	791	*
bogdanm	82:6473597d706e	792	* Selects the scaler value for the After SCK Delay. This field is used only in
bogdanm	82:6473597d706e	793	* master mode. The After SCK Delay is the delay between the last edge of SCK and
bogdanm	82:6473597d706e	794	* the negation of PCS. The delay is a multiple of the protocol clock period,
bogdanm	82:6473597d706e	795	* and it is computed according to the following equation: t ASC = (1/fP) x PASC x
bogdanm	82:6473597d706e	796	* ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
bogdanm	82:6473597d706e	797	* scaler values. Refer After SCK Delay (tASC ) for more details.
bogdanm	82:6473597d706e	798	*/
bogdanm	82:6473597d706e	799	//@{
bogdanm	82:6473597d706e	800	#define BP_SPI_CTARn_ASC (8U) //!< Bit position for SPI_CTARn_ASC.
bogdanm	82:6473597d706e	801	#define BM_SPI_CTARn_ASC (0x00000F00U) //!< Bit mask for SPI_CTARn_ASC.
bogdanm	82:6473597d706e	802	#define BS_SPI_CTARn_ASC (4U) //!< Bit field size in bits for SPI_CTARn_ASC.
bogdanm	82:6473597d706e	803
bogdanm	82:6473597d706e	804	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	805	//! @brief Read current value of the SPI_CTARn_ASC field.
bogdanm	82:6473597d706e	806	#define BR_SPI_CTARn_ASC(x, n) (HW_SPI_CTARn(x, n).B.ASC)
bogdanm	82:6473597d706e	807	#endif
bogdanm	82:6473597d706e	808
bogdanm	82:6473597d706e	809	//! @brief Format value for bitfield SPI_CTARn_ASC.
bogdanm	82:6473597d706e	810	#define BF_SPI_CTARn_ASC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_ASC), uint32_t) & BM_SPI_CTARn_ASC)
bogdanm	82:6473597d706e	811
bogdanm	82:6473597d706e	812	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	813	//! @brief Set the ASC field to a new value.
bogdanm	82:6473597d706e	814	#define BW_SPI_CTARn_ASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_ASC) \| BF_SPI_CTARn_ASC(v)))
bogdanm	82:6473597d706e	815	#endif
bogdanm	82:6473597d706e	816	//@}
bogdanm	82:6473597d706e	817
bogdanm	82:6473597d706e	818	/*!
bogdanm	82:6473597d706e	819	* @name Register SPI_CTARn, field CSSCK[15:12] (RW)
bogdanm	82:6473597d706e	820	*
bogdanm	82:6473597d706e	821	* Selects the scaler value for the PCS to SCK delay. This field is used only in
bogdanm	82:6473597d706e	822	* master mode. The PCS to SCK Delay is the delay between the assertion of PCS
bogdanm	82:6473597d706e	823	* and the first edge of the SCK. The delay is a multiple of the protocol clock
bogdanm	82:6473597d706e	824	* period, and it is computed according to the following equation: t CSC = (1/fP )
bogdanm	82:6473597d706e	825	* x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
bogdanm	82:6473597d706e	826	* Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
bogdanm	82:6473597d706e	827	* 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
bogdanm	82:6473597d706e	828	* 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
bogdanm	82:6473597d706e	829	* details.
bogdanm	82:6473597d706e	830	*/
bogdanm	82:6473597d706e	831	//@{
bogdanm	82:6473597d706e	832	#define BP_SPI_CTARn_CSSCK (12U) //!< Bit position for SPI_CTARn_CSSCK.
bogdanm	82:6473597d706e	833	#define BM_SPI_CTARn_CSSCK (0x0000F000U) //!< Bit mask for SPI_CTARn_CSSCK.
bogdanm	82:6473597d706e	834	#define BS_SPI_CTARn_CSSCK (4U) //!< Bit field size in bits for SPI_CTARn_CSSCK.
bogdanm	82:6473597d706e	835
bogdanm	82:6473597d706e	836	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	837	//! @brief Read current value of the SPI_CTARn_CSSCK field.
bogdanm	82:6473597d706e	838	#define BR_SPI_CTARn_CSSCK(x, n) (HW_SPI_CTARn(x, n).B.CSSCK)
bogdanm	82:6473597d706e	839	#endif
bogdanm	82:6473597d706e	840
bogdanm	82:6473597d706e	841	//! @brief Format value for bitfield SPI_CTARn_CSSCK.
bogdanm	82:6473597d706e	842	#define BF_SPI_CTARn_CSSCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CSSCK), uint32_t) & BM_SPI_CTARn_CSSCK)
bogdanm	82:6473597d706e	843
bogdanm	82:6473597d706e	844	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	845	//! @brief Set the CSSCK field to a new value.
bogdanm	82:6473597d706e	846	#define BW_SPI_CTARn_CSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_CSSCK) \| BF_SPI_CTARn_CSSCK(v)))
bogdanm	82:6473597d706e	847	#endif
bogdanm	82:6473597d706e	848	//@}
bogdanm	82:6473597d706e	849
bogdanm	82:6473597d706e	850	/*!
bogdanm	82:6473597d706e	851	* @name Register SPI_CTARn, field PBR[17:16] (RW)
bogdanm	82:6473597d706e	852	*
bogdanm	82:6473597d706e	853	* Selects the prescaler value for the baud rate. This field is used only in
bogdanm	82:6473597d706e	854	* master mode. The baud rate is the frequency of the SCK. The protocol clock is
bogdanm	82:6473597d706e	855	* divided by the prescaler value before the baud rate selection takes place. See
bogdanm	82:6473597d706e	856	* the BR field description for details on how to compute the baud rate.
bogdanm	82:6473597d706e	857	*
bogdanm	82:6473597d706e	858	* Values:
bogdanm	82:6473597d706e	859	* - 00 - Baud Rate Prescaler value is 2.
bogdanm	82:6473597d706e	860	* - 01 - Baud Rate Prescaler value is 3.
bogdanm	82:6473597d706e	861	* - 10 - Baud Rate Prescaler value is 5.
bogdanm	82:6473597d706e	862	* - 11 - Baud Rate Prescaler value is 7.
bogdanm	82:6473597d706e	863	*/
bogdanm	82:6473597d706e	864	//@{
bogdanm	82:6473597d706e	865	#define BP_SPI_CTARn_PBR (16U) //!< Bit position for SPI_CTARn_PBR.
bogdanm	82:6473597d706e	866	#define BM_SPI_CTARn_PBR (0x00030000U) //!< Bit mask for SPI_CTARn_PBR.
bogdanm	82:6473597d706e	867	#define BS_SPI_CTARn_PBR (2U) //!< Bit field size in bits for SPI_CTARn_PBR.
bogdanm	82:6473597d706e	868
bogdanm	82:6473597d706e	869	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	870	//! @brief Read current value of the SPI_CTARn_PBR field.
bogdanm	82:6473597d706e	871	#define BR_SPI_CTARn_PBR(x, n) (HW_SPI_CTARn(x, n).B.PBR)
bogdanm	82:6473597d706e	872	#endif
bogdanm	82:6473597d706e	873
bogdanm	82:6473597d706e	874	//! @brief Format value for bitfield SPI_CTARn_PBR.
bogdanm	82:6473597d706e	875	#define BF_SPI_CTARn_PBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PBR), uint32_t) & BM_SPI_CTARn_PBR)
bogdanm	82:6473597d706e	876
bogdanm	82:6473597d706e	877	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	878	//! @brief Set the PBR field to a new value.
bogdanm	82:6473597d706e	879	#define BW_SPI_CTARn_PBR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PBR) \| BF_SPI_CTARn_PBR(v)))
bogdanm	82:6473597d706e	880	#endif
bogdanm	82:6473597d706e	881	//@}
bogdanm	82:6473597d706e	882
bogdanm	82:6473597d706e	883	/*!
bogdanm	82:6473597d706e	884	* @name Register SPI_CTARn, field PDT[19:18] (RW)
bogdanm	82:6473597d706e	885	*
bogdanm	82:6473597d706e	886	* Selects the prescaler value for the delay between the negation of the PCS
bogdanm	82:6473597d706e	887	* signal at the end of a frame and the assertion of PCS at the beginning of the
bogdanm	82:6473597d706e	888	* next frame. The PDT field is only used in master mode. See the DT field
bogdanm	82:6473597d706e	889	* description for details on how to compute the Delay after Transfer. Refer Delay after
bogdanm	82:6473597d706e	890	* Transfer (tDT ) for more details.
bogdanm	82:6473597d706e	891	*
bogdanm	82:6473597d706e	892	* Values:
bogdanm	82:6473597d706e	893	* - 00 - Delay after Transfer Prescaler value is 1.
bogdanm	82:6473597d706e	894	* - 01 - Delay after Transfer Prescaler value is 3.
bogdanm	82:6473597d706e	895	* - 10 - Delay after Transfer Prescaler value is 5.
bogdanm	82:6473597d706e	896	* - 11 - Delay after Transfer Prescaler value is 7.
bogdanm	82:6473597d706e	897	*/
bogdanm	82:6473597d706e	898	//@{
bogdanm	82:6473597d706e	899	#define BP_SPI_CTARn_PDT (18U) //!< Bit position for SPI_CTARn_PDT.
bogdanm	82:6473597d706e	900	#define BM_SPI_CTARn_PDT (0x000C0000U) //!< Bit mask for SPI_CTARn_PDT.
bogdanm	82:6473597d706e	901	#define BS_SPI_CTARn_PDT (2U) //!< Bit field size in bits for SPI_CTARn_PDT.
bogdanm	82:6473597d706e	902
bogdanm	82:6473597d706e	903	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	904	//! @brief Read current value of the SPI_CTARn_PDT field.
bogdanm	82:6473597d706e	905	#define BR_SPI_CTARn_PDT(x, n) (HW_SPI_CTARn(x, n).B.PDT)
bogdanm	82:6473597d706e	906	#endif
bogdanm	82:6473597d706e	907
bogdanm	82:6473597d706e	908	//! @brief Format value for bitfield SPI_CTARn_PDT.
bogdanm	82:6473597d706e	909	#define BF_SPI_CTARn_PDT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PDT), uint32_t) & BM_SPI_CTARn_PDT)
bogdanm	82:6473597d706e	910
bogdanm	82:6473597d706e	911	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	912	//! @brief Set the PDT field to a new value.
bogdanm	82:6473597d706e	913	#define BW_SPI_CTARn_PDT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PDT) \| BF_SPI_CTARn_PDT(v)))
bogdanm	82:6473597d706e	914	#endif
bogdanm	82:6473597d706e	915	//@}
bogdanm	82:6473597d706e	916
bogdanm	82:6473597d706e	917	/*!
bogdanm	82:6473597d706e	918	* @name Register SPI_CTARn, field PASC[21:20] (RW)
bogdanm	82:6473597d706e	919	*
bogdanm	82:6473597d706e	920	* Selects the prescaler value for the delay between the last edge of SCK and
bogdanm	82:6473597d706e	921	* the negation of PCS. See the ASC field description for information on how to
bogdanm	82:6473597d706e	922	* compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
bogdanm	82:6473597d706e	923	*
bogdanm	82:6473597d706e	924	* Values:
bogdanm	82:6473597d706e	925	* - 00 - Delay after Transfer Prescaler value is 1.
bogdanm	82:6473597d706e	926	* - 01 - Delay after Transfer Prescaler value is 3.
bogdanm	82:6473597d706e	927	* - 10 - Delay after Transfer Prescaler value is 5.
bogdanm	82:6473597d706e	928	* - 11 - Delay after Transfer Prescaler value is 7.
bogdanm	82:6473597d706e	929	*/
bogdanm	82:6473597d706e	930	//@{
bogdanm	82:6473597d706e	931	#define BP_SPI_CTARn_PASC (20U) //!< Bit position for SPI_CTARn_PASC.
bogdanm	82:6473597d706e	932	#define BM_SPI_CTARn_PASC (0x00300000U) //!< Bit mask for SPI_CTARn_PASC.
bogdanm	82:6473597d706e	933	#define BS_SPI_CTARn_PASC (2U) //!< Bit field size in bits for SPI_CTARn_PASC.
bogdanm	82:6473597d706e	934
bogdanm	82:6473597d706e	935	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	936	//! @brief Read current value of the SPI_CTARn_PASC field.
bogdanm	82:6473597d706e	937	#define BR_SPI_CTARn_PASC(x, n) (HW_SPI_CTARn(x, n).B.PASC)
bogdanm	82:6473597d706e	938	#endif
bogdanm	82:6473597d706e	939
bogdanm	82:6473597d706e	940	//! @brief Format value for bitfield SPI_CTARn_PASC.
bogdanm	82:6473597d706e	941	#define BF_SPI_CTARn_PASC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PASC), uint32_t) & BM_SPI_CTARn_PASC)
bogdanm	82:6473597d706e	942
bogdanm	82:6473597d706e	943	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	944	//! @brief Set the PASC field to a new value.
bogdanm	82:6473597d706e	945	#define BW_SPI_CTARn_PASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PASC) \| BF_SPI_CTARn_PASC(v)))
bogdanm	82:6473597d706e	946	#endif
bogdanm	82:6473597d706e	947	//@}
bogdanm	82:6473597d706e	948
bogdanm	82:6473597d706e	949	/*!
bogdanm	82:6473597d706e	950	* @name Register SPI_CTARn, field PCSSCK[23:22] (RW)
bogdanm	82:6473597d706e	951	*
bogdanm	82:6473597d706e	952	* Selects the prescaler value for the delay between assertion of PCS and the
bogdanm	82:6473597d706e	953	* first edge of the SCK. See the CSSCK field description for information on how to
bogdanm	82:6473597d706e	954	* compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
bogdanm	82:6473597d706e	955	*
bogdanm	82:6473597d706e	956	* Values:
bogdanm	82:6473597d706e	957	* - 00 - PCS to SCK Prescaler value is 1.
bogdanm	82:6473597d706e	958	* - 01 - PCS to SCK Prescaler value is 3.
bogdanm	82:6473597d706e	959	* - 10 - PCS to SCK Prescaler value is 5.
bogdanm	82:6473597d706e	960	* - 11 - PCS to SCK Prescaler value is 7.
bogdanm	82:6473597d706e	961	*/
bogdanm	82:6473597d706e	962	//@{
bogdanm	82:6473597d706e	963	#define BP_SPI_CTARn_PCSSCK (22U) //!< Bit position for SPI_CTARn_PCSSCK.
bogdanm	82:6473597d706e	964	#define BM_SPI_CTARn_PCSSCK (0x00C00000U) //!< Bit mask for SPI_CTARn_PCSSCK.
bogdanm	82:6473597d706e	965	#define BS_SPI_CTARn_PCSSCK (2U) //!< Bit field size in bits for SPI_CTARn_PCSSCK.
bogdanm	82:6473597d706e	966
bogdanm	82:6473597d706e	967	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	968	//! @brief Read current value of the SPI_CTARn_PCSSCK field.
bogdanm	82:6473597d706e	969	#define BR_SPI_CTARn_PCSSCK(x, n) (HW_SPI_CTARn(x, n).B.PCSSCK)
bogdanm	82:6473597d706e	970	#endif
bogdanm	82:6473597d706e	971
bogdanm	82:6473597d706e	972	//! @brief Format value for bitfield SPI_CTARn_PCSSCK.
bogdanm	82:6473597d706e	973	#define BF_SPI_CTARn_PCSSCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PCSSCK), uint32_t) & BM_SPI_CTARn_PCSSCK)
bogdanm	82:6473597d706e	974
bogdanm	82:6473597d706e	975	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	976	//! @brief Set the PCSSCK field to a new value.
bogdanm	82:6473597d706e	977	#define BW_SPI_CTARn_PCSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PCSSCK) \| BF_SPI_CTARn_PCSSCK(v)))
bogdanm	82:6473597d706e	978	#endif
bogdanm	82:6473597d706e	979	//@}
bogdanm	82:6473597d706e	980
bogdanm	82:6473597d706e	981	/*!
bogdanm	82:6473597d706e	982	* @name Register SPI_CTARn, field LSBFE[24] (RW)
bogdanm	82:6473597d706e	983	*
bogdanm	82:6473597d706e	984	* Specifies whether the LSB or MSB of the frame is transferred first.
bogdanm	82:6473597d706e	985	*
bogdanm	82:6473597d706e	986	* Values:
bogdanm	82:6473597d706e	987	* - 0 - Data is transferred MSB first.
bogdanm	82:6473597d706e	988	* - 1 - Data is transferred LSB first.
bogdanm	82:6473597d706e	989	*/
bogdanm	82:6473597d706e	990	//@{
bogdanm	82:6473597d706e	991	#define BP_SPI_CTARn_LSBFE (24U) //!< Bit position for SPI_CTARn_LSBFE.
bogdanm	82:6473597d706e	992	#define BM_SPI_CTARn_LSBFE (0x01000000U) //!< Bit mask for SPI_CTARn_LSBFE.
bogdanm	82:6473597d706e	993	#define BS_SPI_CTARn_LSBFE (1U) //!< Bit field size in bits for SPI_CTARn_LSBFE.
bogdanm	82:6473597d706e	994
bogdanm	82:6473597d706e	995	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	996	//! @brief Read current value of the SPI_CTARn_LSBFE field.
bogdanm	82:6473597d706e	997	#define BR_SPI_CTARn_LSBFE(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE))
bogdanm	82:6473597d706e	998	#endif
bogdanm	82:6473597d706e	999
bogdanm	82:6473597d706e	1000	//! @brief Format value for bitfield SPI_CTARn_LSBFE.
bogdanm	82:6473597d706e	1001	#define BF_SPI_CTARn_LSBFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_LSBFE), uint32_t) & BM_SPI_CTARn_LSBFE)
bogdanm	82:6473597d706e	1002
bogdanm	82:6473597d706e	1003	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1004	//! @brief Set the LSBFE field to a new value.
bogdanm	82:6473597d706e	1005	#define BW_SPI_CTARn_LSBFE(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE) = (v))
bogdanm	82:6473597d706e	1006	#endif
bogdanm	82:6473597d706e	1007	//@}
bogdanm	82:6473597d706e	1008
bogdanm	82:6473597d706e	1009	/*!
bogdanm	82:6473597d706e	1010	* @name Register SPI_CTARn, field CPHA[25] (RW)
bogdanm	82:6473597d706e	1011	*
bogdanm	82:6473597d706e	1012	* Selects which edge of SCK causes data to change and which edge causes data to
bogdanm	82:6473597d706e	1013	* be captured. This bit is used in both master and slave mode. For successful
bogdanm	82:6473597d706e	1014	* communication between serial devices, the devices must have identical clock
bogdanm	82:6473597d706e	1015	* phase settings. In Continuous SCK mode, the bit value is ignored and the
bogdanm	82:6473597d706e	1016	* transfers are done as if the CPHA bit is set to 1.
bogdanm	82:6473597d706e	1017	*
bogdanm	82:6473597d706e	1018	* Values:
bogdanm	82:6473597d706e	1019	* - 0 - Data is captured on the leading edge of SCK and changed on the
bogdanm	82:6473597d706e	1020	* following edge.
bogdanm	82:6473597d706e	1021	* - 1 - Data is changed on the leading edge of SCK and captured on the
bogdanm	82:6473597d706e	1022	* following edge.
bogdanm	82:6473597d706e	1023	*/
bogdanm	82:6473597d706e	1024	//@{
bogdanm	82:6473597d706e	1025	#define BP_SPI_CTARn_CPHA (25U) //!< Bit position for SPI_CTARn_CPHA.
bogdanm	82:6473597d706e	1026	#define BM_SPI_CTARn_CPHA (0x02000000U) //!< Bit mask for SPI_CTARn_CPHA.
bogdanm	82:6473597d706e	1027	#define BS_SPI_CTARn_CPHA (1U) //!< Bit field size in bits for SPI_CTARn_CPHA.
bogdanm	82:6473597d706e	1028
bogdanm	82:6473597d706e	1029	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1030	//! @brief Read current value of the SPI_CTARn_CPHA field.
bogdanm	82:6473597d706e	1031	#define BR_SPI_CTARn_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA))
bogdanm	82:6473597d706e	1032	#endif
bogdanm	82:6473597d706e	1033
bogdanm	82:6473597d706e	1034	//! @brief Format value for bitfield SPI_CTARn_CPHA.
bogdanm	82:6473597d706e	1035	#define BF_SPI_CTARn_CPHA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CPHA), uint32_t) & BM_SPI_CTARn_CPHA)
bogdanm	82:6473597d706e	1036
bogdanm	82:6473597d706e	1037	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1038	//! @brief Set the CPHA field to a new value.
bogdanm	82:6473597d706e	1039	#define BW_SPI_CTARn_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA) = (v))
bogdanm	82:6473597d706e	1040	#endif
bogdanm	82:6473597d706e	1041	//@}
bogdanm	82:6473597d706e	1042
bogdanm	82:6473597d706e	1043	/*!
bogdanm	82:6473597d706e	1044	* @name Register SPI_CTARn, field CPOL[26] (RW)
bogdanm	82:6473597d706e	1045	*
bogdanm	82:6473597d706e	1046	* Selects the inactive state of the Serial Communications Clock (SCK). This bit
bogdanm	82:6473597d706e	1047	* is used in both master and slave mode. For successful communication between
bogdanm	82:6473597d706e	1048	* serial devices, the devices must have identical clock polarities. When the
bogdanm	82:6473597d706e	1049	* Continuous Selection Format is selected, switching between clock polarities
bogdanm	82:6473597d706e	1050	* without stopping the module can cause errors in the transfer due to the peripheral
bogdanm	82:6473597d706e	1051	* device interpreting the switch of clock polarity as a valid clock edge. In case
bogdanm	82:6473597d706e	1052	* of continous sck mode, when the module goes in low power mode(disabled),
bogdanm	82:6473597d706e	1053	* inactive state of sck is not guaranted.
bogdanm	82:6473597d706e	1054	*
bogdanm	82:6473597d706e	1055	* Values:
bogdanm	82:6473597d706e	1056	* - 0 - The inactive state value of SCK is low.
bogdanm	82:6473597d706e	1057	* - 1 - The inactive state value of SCK is high.
bogdanm	82:6473597d706e	1058	*/
bogdanm	82:6473597d706e	1059	//@{
bogdanm	82:6473597d706e	1060	#define BP_SPI_CTARn_CPOL (26U) //!< Bit position for SPI_CTARn_CPOL.
bogdanm	82:6473597d706e	1061	#define BM_SPI_CTARn_CPOL (0x04000000U) //!< Bit mask for SPI_CTARn_CPOL.
bogdanm	82:6473597d706e	1062	#define BS_SPI_CTARn_CPOL (1U) //!< Bit field size in bits for SPI_CTARn_CPOL.
bogdanm	82:6473597d706e	1063
bogdanm	82:6473597d706e	1064	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1065	//! @brief Read current value of the SPI_CTARn_CPOL field.
bogdanm	82:6473597d706e	1066	#define BR_SPI_CTARn_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL))
bogdanm	82:6473597d706e	1067	#endif
bogdanm	82:6473597d706e	1068
bogdanm	82:6473597d706e	1069	//! @brief Format value for bitfield SPI_CTARn_CPOL.
bogdanm	82:6473597d706e	1070	#define BF_SPI_CTARn_CPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CPOL), uint32_t) & BM_SPI_CTARn_CPOL)
bogdanm	82:6473597d706e	1071
bogdanm	82:6473597d706e	1072	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1073	//! @brief Set the CPOL field to a new value.
bogdanm	82:6473597d706e	1074	#define BW_SPI_CTARn_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL) = (v))
bogdanm	82:6473597d706e	1075	#endif
bogdanm	82:6473597d706e	1076	//@}
bogdanm	82:6473597d706e	1077
bogdanm	82:6473597d706e	1078	/*!
bogdanm	82:6473597d706e	1079	* @name Register SPI_CTARn, field FMSZ[30:27] (RW)
bogdanm	82:6473597d706e	1080	*
bogdanm	82:6473597d706e	1081	* The number of bits transferred per frame is equal to the FMSZ value plus 1.
bogdanm	82:6473597d706e	1082	* Regardless of the transmission mode, the minimum valid frame size value is 4.
bogdanm	82:6473597d706e	1083	*/
bogdanm	82:6473597d706e	1084	//@{
bogdanm	82:6473597d706e	1085	#define BP_SPI_CTARn_FMSZ (27U) //!< Bit position for SPI_CTARn_FMSZ.
bogdanm	82:6473597d706e	1086	#define BM_SPI_CTARn_FMSZ (0x78000000U) //!< Bit mask for SPI_CTARn_FMSZ.
bogdanm	82:6473597d706e	1087	#define BS_SPI_CTARn_FMSZ (4U) //!< Bit field size in bits for SPI_CTARn_FMSZ.
bogdanm	82:6473597d706e	1088
bogdanm	82:6473597d706e	1089	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1090	//! @brief Read current value of the SPI_CTARn_FMSZ field.
bogdanm	82:6473597d706e	1091	#define BR_SPI_CTARn_FMSZ(x, n) (HW_SPI_CTARn(x, n).B.FMSZ)
bogdanm	82:6473597d706e	1092	#endif
bogdanm	82:6473597d706e	1093
bogdanm	82:6473597d706e	1094	//! @brief Format value for bitfield SPI_CTARn_FMSZ.
bogdanm	82:6473597d706e	1095	#define BF_SPI_CTARn_FMSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_FMSZ), uint32_t) & BM_SPI_CTARn_FMSZ)
bogdanm	82:6473597d706e	1096
bogdanm	82:6473597d706e	1097	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1098	//! @brief Set the FMSZ field to a new value.
bogdanm	82:6473597d706e	1099	#define BW_SPI_CTARn_FMSZ(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_FMSZ) \| BF_SPI_CTARn_FMSZ(v)))
bogdanm	82:6473597d706e	1100	#endif
bogdanm	82:6473597d706e	1101	//@}
bogdanm	82:6473597d706e	1102
bogdanm	82:6473597d706e	1103	/*!
bogdanm	82:6473597d706e	1104	* @name Register SPI_CTARn, field DBR[31] (RW)
bogdanm	82:6473597d706e	1105	*
bogdanm	82:6473597d706e	1106	* Doubles the effective baud rate of the Serial Communications Clock (SCK).
bogdanm	82:6473597d706e	1107	* This field is used only in master mode. It effectively halves the Baud Rate
bogdanm	82:6473597d706e	1108	* division ratio, supporting faster frequencies, and odd division ratios for the
bogdanm	82:6473597d706e	1109	* Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
bogdanm	82:6473597d706e	1110	* Serial Communications Clock (SCK) depends on the value in the Baud Rate
bogdanm	82:6473597d706e	1111	* Prescaler and the Clock Phase bit as listed in the following table. See the BR field
bogdanm	82:6473597d706e	1112	* description for details on how to compute the baud rate. SPI SCK Duty Cycle
bogdanm	82:6473597d706e	1113	* DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
bogdanm	82:6473597d706e	1114	* 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
bogdanm	82:6473597d706e	1115	*
bogdanm	82:6473597d706e	1116	* Values:
bogdanm	82:6473597d706e	1117	* - 0 - The baud rate is computed normally with a 50/50 duty cycle.
bogdanm	82:6473597d706e	1118	* - 1 - The baud rate is doubled with the duty cycle depending on the Baud Rate
bogdanm	82:6473597d706e	1119	* Prescaler.
bogdanm	82:6473597d706e	1120	*/
bogdanm	82:6473597d706e	1121	//@{
bogdanm	82:6473597d706e	1122	#define BP_SPI_CTARn_DBR (31U) //!< Bit position for SPI_CTARn_DBR.
bogdanm	82:6473597d706e	1123	#define BM_SPI_CTARn_DBR (0x80000000U) //!< Bit mask for SPI_CTARn_DBR.
bogdanm	82:6473597d706e	1124	#define BS_SPI_CTARn_DBR (1U) //!< Bit field size in bits for SPI_CTARn_DBR.
bogdanm	82:6473597d706e	1125
bogdanm	82:6473597d706e	1126	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1127	//! @brief Read current value of the SPI_CTARn_DBR field.
bogdanm	82:6473597d706e	1128	#define BR_SPI_CTARn_DBR(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR))
bogdanm	82:6473597d706e	1129	#endif
bogdanm	82:6473597d706e	1130
bogdanm	82:6473597d706e	1131	//! @brief Format value for bitfield SPI_CTARn_DBR.
bogdanm	82:6473597d706e	1132	#define BF_SPI_CTARn_DBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_DBR), uint32_t) & BM_SPI_CTARn_DBR)
bogdanm	82:6473597d706e	1133
bogdanm	82:6473597d706e	1134	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1135	//! @brief Set the DBR field to a new value.
bogdanm	82:6473597d706e	1136	#define BW_SPI_CTARn_DBR(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR) = (v))
bogdanm	82:6473597d706e	1137	#endif
bogdanm	82:6473597d706e	1138	//@}
bogdanm	82:6473597d706e	1139	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1140	// HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
bogdanm	82:6473597d706e	1141	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1142
bogdanm	82:6473597d706e	1143	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1144	/*!
bogdanm	82:6473597d706e	1145	* @brief HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
bogdanm	82:6473597d706e	1146	*
bogdanm	82:6473597d706e	1147	* Reset value: 0x78000000U
bogdanm	82:6473597d706e	1148	*
bogdanm	82:6473597d706e	1149	* When the module is configured as an SPI bus slave, the CTAR0 register is used.
bogdanm	82:6473597d706e	1150	*/
bogdanm	82:6473597d706e	1151	typedef union _hw_spi_ctarn_slave
bogdanm	82:6473597d706e	1152	{
bogdanm	82:6473597d706e	1153	uint32_t U;
bogdanm	82:6473597d706e	1154	struct _hw_spi_ctarn_slave_bitfields
bogdanm	82:6473597d706e	1155	{
bogdanm	82:6473597d706e	1156	uint32_t RESERVED0 : 25; //!< [24:0]
bogdanm	82:6473597d706e	1157	uint32_t CPHA : 1; //!< [25] Clock Phase
bogdanm	82:6473597d706e	1158	uint32_t CPOL : 1; //!< [26] Clock Polarity
bogdanm	82:6473597d706e	1159	uint32_t FMSZ : 5; //!< [31:27] Frame Size
bogdanm	82:6473597d706e	1160	} B;
bogdanm	82:6473597d706e	1161	} hw_spi_ctarn_slave_t;
bogdanm	82:6473597d706e	1162	#endif
bogdanm	82:6473597d706e	1163
bogdanm	82:6473597d706e	1164	/*!
bogdanm	82:6473597d706e	1165	* @name Constants and macros for entire SPI_CTARn_SLAVE register
bogdanm	82:6473597d706e	1166	*/
bogdanm	82:6473597d706e	1167	//@{
bogdanm	82:6473597d706e	1168	#define HW_SPI_CTARn_SLAVE_COUNT (1U)
bogdanm	82:6473597d706e	1169
bogdanm	82:6473597d706e	1170	#define HW_SPI_CTARn_SLAVE_ADDR(x, n) (REGS_SPI_BASE(x) + 0xCU + (0x4U * n))
bogdanm	82:6473597d706e	1171
bogdanm	82:6473597d706e	1172	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1173	#define HW_SPI_CTARn_SLAVE(x, n) ((__IO hw_spi_ctarn_slave_t ) HW_SPI_CTARn_SLAVE_ADDR(x, n))
bogdanm	82:6473597d706e	1174	#define HW_SPI_CTARn_SLAVE_RD(x, n) (HW_SPI_CTARn_SLAVE(x, n).U)
bogdanm	82:6473597d706e	1175	#define HW_SPI_CTARn_SLAVE_WR(x, n, v) (HW_SPI_CTARn_SLAVE(x, n).U = (v))
bogdanm	82:6473597d706e	1176	#define HW_SPI_CTARn_SLAVE_SET(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	1177	#define HW_SPI_CTARn_SLAVE_CLR(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	1178	#define HW_SPI_CTARn_SLAVE_TOG(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	1179	#endif
bogdanm	82:6473597d706e	1180	//@}
bogdanm	82:6473597d706e	1181
bogdanm	82:6473597d706e	1182	/*
bogdanm	82:6473597d706e	1183	* Constants & macros for individual SPI_CTARn_SLAVE bitfields
bogdanm	82:6473597d706e	1184	*/
bogdanm	82:6473597d706e	1185
bogdanm	82:6473597d706e	1186	/*!
bogdanm	82:6473597d706e	1187	* @name Register SPI_CTARn_SLAVE, field CPHA[25] (RW)
bogdanm	82:6473597d706e	1188	*
bogdanm	82:6473597d706e	1189	* Selects which edge of SCK causes data to change and which edge causes data to
bogdanm	82:6473597d706e	1190	* be captured. This bit is used in both master and slave mode. For successful
bogdanm	82:6473597d706e	1191	* communication between serial devices, the devices must have identical clock
bogdanm	82:6473597d706e	1192	* phase settings. In Continuous SCK mode, the bit value is ignored and the
bogdanm	82:6473597d706e	1193	* transfers are done as if the CPHA bit is set to 1.
bogdanm	82:6473597d706e	1194	*
bogdanm	82:6473597d706e	1195	* Values:
bogdanm	82:6473597d706e	1196	* - 0 - Data is captured on the leading edge of SCK and changed on the
bogdanm	82:6473597d706e	1197	* following edge.
bogdanm	82:6473597d706e	1198	* - 1 - Data is changed on the leading edge of SCK and captured on the
bogdanm	82:6473597d706e	1199	* following edge.
bogdanm	82:6473597d706e	1200	*/
bogdanm	82:6473597d706e	1201	//@{
bogdanm	82:6473597d706e	1202	#define BP_SPI_CTARn_SLAVE_CPHA (25U) //!< Bit position for SPI_CTARn_SLAVE_CPHA.
bogdanm	82:6473597d706e	1203	#define BM_SPI_CTARn_SLAVE_CPHA (0x02000000U) //!< Bit mask for SPI_CTARn_SLAVE_CPHA.
bogdanm	82:6473597d706e	1204	#define BS_SPI_CTARn_SLAVE_CPHA (1U) //!< Bit field size in bits for SPI_CTARn_SLAVE_CPHA.
bogdanm	82:6473597d706e	1205
bogdanm	82:6473597d706e	1206	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1207	//! @brief Read current value of the SPI_CTARn_SLAVE_CPHA field.
bogdanm	82:6473597d706e	1208	#define BR_SPI_CTARn_SLAVE_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA))
bogdanm	82:6473597d706e	1209	#endif
bogdanm	82:6473597d706e	1210
bogdanm	82:6473597d706e	1211	//! @brief Format value for bitfield SPI_CTARn_SLAVE_CPHA.
bogdanm	82:6473597d706e	1212	#define BF_SPI_CTARn_SLAVE_CPHA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_CPHA), uint32_t) & BM_SPI_CTARn_SLAVE_CPHA)
bogdanm	82:6473597d706e	1213
bogdanm	82:6473597d706e	1214	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1215	//! @brief Set the CPHA field to a new value.
bogdanm	82:6473597d706e	1216	#define BW_SPI_CTARn_SLAVE_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA) = (v))
bogdanm	82:6473597d706e	1217	#endif
bogdanm	82:6473597d706e	1218	//@}
bogdanm	82:6473597d706e	1219
bogdanm	82:6473597d706e	1220	/*!
bogdanm	82:6473597d706e	1221	* @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW)
bogdanm	82:6473597d706e	1222	*
bogdanm	82:6473597d706e	1223	* Selects the inactive state of the Serial Communications Clock (SCK). In case
bogdanm	82:6473597d706e	1224	* of continous sck mode, when the module goes in low power mode(disabled),
bogdanm	82:6473597d706e	1225	* inactive state of sck is not guaranted.
bogdanm	82:6473597d706e	1226	*
bogdanm	82:6473597d706e	1227	* Values:
bogdanm	82:6473597d706e	1228	* - 0 - The inactive state value of SCK is low.
bogdanm	82:6473597d706e	1229	* - 1 - The inactive state value of SCK is high.
bogdanm	82:6473597d706e	1230	*/
bogdanm	82:6473597d706e	1231	//@{
bogdanm	82:6473597d706e	1232	#define BP_SPI_CTARn_SLAVE_CPOL (26U) //!< Bit position for SPI_CTARn_SLAVE_CPOL.
bogdanm	82:6473597d706e	1233	#define BM_SPI_CTARn_SLAVE_CPOL (0x04000000U) //!< Bit mask for SPI_CTARn_SLAVE_CPOL.
bogdanm	82:6473597d706e	1234	#define BS_SPI_CTARn_SLAVE_CPOL (1U) //!< Bit field size in bits for SPI_CTARn_SLAVE_CPOL.
bogdanm	82:6473597d706e	1235
bogdanm	82:6473597d706e	1236	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1237	//! @brief Read current value of the SPI_CTARn_SLAVE_CPOL field.
bogdanm	82:6473597d706e	1238	#define BR_SPI_CTARn_SLAVE_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL))
bogdanm	82:6473597d706e	1239	#endif
bogdanm	82:6473597d706e	1240
bogdanm	82:6473597d706e	1241	//! @brief Format value for bitfield SPI_CTARn_SLAVE_CPOL.
bogdanm	82:6473597d706e	1242	#define BF_SPI_CTARn_SLAVE_CPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_CPOL), uint32_t) & BM_SPI_CTARn_SLAVE_CPOL)
bogdanm	82:6473597d706e	1243
bogdanm	82:6473597d706e	1244	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1245	//! @brief Set the CPOL field to a new value.
bogdanm	82:6473597d706e	1246	#define BW_SPI_CTARn_SLAVE_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL) = (v))
bogdanm	82:6473597d706e	1247	#endif
bogdanm	82:6473597d706e	1248	//@}
bogdanm	82:6473597d706e	1249
bogdanm	82:6473597d706e	1250	/*!
bogdanm	82:6473597d706e	1251	* @name Register SPI_CTARn_SLAVE, field FMSZ[31:27] (RW)
bogdanm	82:6473597d706e	1252	*
bogdanm	82:6473597d706e	1253	* The number of bits transfered per frame is equal to the FMSZ field value plus
bogdanm	82:6473597d706e	1254	* 1. Note that the minimum valid value of frame size is 4.
bogdanm	82:6473597d706e	1255	*/
bogdanm	82:6473597d706e	1256	//@{
bogdanm	82:6473597d706e	1257	#define BP_SPI_CTARn_SLAVE_FMSZ (27U) //!< Bit position for SPI_CTARn_SLAVE_FMSZ.
bogdanm	82:6473597d706e	1258	#define BM_SPI_CTARn_SLAVE_FMSZ (0xF8000000U) //!< Bit mask for SPI_CTARn_SLAVE_FMSZ.
bogdanm	82:6473597d706e	1259	#define BS_SPI_CTARn_SLAVE_FMSZ (5U) //!< Bit field size in bits for SPI_CTARn_SLAVE_FMSZ.
bogdanm	82:6473597d706e	1260
bogdanm	82:6473597d706e	1261	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1262	//! @brief Read current value of the SPI_CTARn_SLAVE_FMSZ field.
bogdanm	82:6473597d706e	1263	#define BR_SPI_CTARn_SLAVE_FMSZ(x, n) (HW_SPI_CTARn_SLAVE(x, n).B.FMSZ)
bogdanm	82:6473597d706e	1264	#endif
bogdanm	82:6473597d706e	1265
bogdanm	82:6473597d706e	1266	//! @brief Format value for bitfield SPI_CTARn_SLAVE_FMSZ.
bogdanm	82:6473597d706e	1267	#define BF_SPI_CTARn_SLAVE_FMSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_FMSZ), uint32_t) & BM_SPI_CTARn_SLAVE_FMSZ)
bogdanm	82:6473597d706e	1268
bogdanm	82:6473597d706e	1269	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1270	//! @brief Set the FMSZ field to a new value.
bogdanm	82:6473597d706e	1271	#define BW_SPI_CTARn_SLAVE_FMSZ(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, (HW_SPI_CTARn_SLAVE_RD(x, n) & ~BM_SPI_CTARn_SLAVE_FMSZ) \| BF_SPI_CTARn_SLAVE_FMSZ(v)))
bogdanm	82:6473597d706e	1272	#endif
bogdanm	82:6473597d706e	1273	//@}
bogdanm	82:6473597d706e	1274
bogdanm	82:6473597d706e	1275	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1276	// HW_SPI_SR - Status Register
bogdanm	82:6473597d706e	1277	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1278
bogdanm	82:6473597d706e	1279	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1280	/*!
bogdanm	82:6473597d706e	1281	* @brief HW_SPI_SR - Status Register (RW)
bogdanm	82:6473597d706e	1282	*
bogdanm	82:6473597d706e	1283	* Reset value: 0x02000000U
bogdanm	82:6473597d706e	1284	*
bogdanm	82:6473597d706e	1285	* SR contains status and flag bits. The bits reflect the status of the module
bogdanm	82:6473597d706e	1286	* and indicate the occurrence of events that can generate interrupt or DMA
bogdanm	82:6473597d706e	1287	* requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
bogdanm	82:6473597d706e	1288	* to a flag bit has no effect. This register may not be writable in Module
bogdanm	82:6473597d706e	1289	* Disable mode due to the use of power saving mechanisms.
bogdanm	82:6473597d706e	1290	*/
bogdanm	82:6473597d706e	1291	typedef union _hw_spi_sr
bogdanm	82:6473597d706e	1292	{
bogdanm	82:6473597d706e	1293	uint32_t U;
bogdanm	82:6473597d706e	1294	struct _hw_spi_sr_bitfields
bogdanm	82:6473597d706e	1295	{
bogdanm	82:6473597d706e	1296	uint32_t POPNXTPTR : 4; //!< [3:0] Pop Next Pointer
bogdanm	82:6473597d706e	1297	uint32_t RXCTR : 4; //!< [7:4] RX FIFO Counter
bogdanm	82:6473597d706e	1298	uint32_t TXNXTPTR : 4; //!< [11:8] Transmit Next Pointer
bogdanm	82:6473597d706e	1299	uint32_t TXCTR : 4; //!< [15:12] TX FIFO Counter
bogdanm	82:6473597d706e	1300	uint32_t RESERVED0 : 1; //!< [16]
bogdanm	82:6473597d706e	1301	uint32_t RFDF : 1; //!< [17] Receive FIFO Drain Flag
bogdanm	82:6473597d706e	1302	uint32_t RESERVED1 : 1; //!< [18]
bogdanm	82:6473597d706e	1303	uint32_t RFOF : 1; //!< [19] Receive FIFO Overflow Flag
bogdanm	82:6473597d706e	1304	uint32_t RESERVED2 : 5; //!< [24:20]
bogdanm	82:6473597d706e	1305	uint32_t TFFF : 1; //!< [25] Transmit FIFO Fill Flag
bogdanm	82:6473597d706e	1306	uint32_t RESERVED3 : 1; //!< [26]
bogdanm	82:6473597d706e	1307	uint32_t TFUF : 1; //!< [27] Transmit FIFO Underflow Flag
bogdanm	82:6473597d706e	1308	uint32_t EOQF : 1; //!< [28] End of Queue Flag
bogdanm	82:6473597d706e	1309	uint32_t RESERVED4 : 1; //!< [29]
bogdanm	82:6473597d706e	1310	uint32_t TXRXS : 1; //!< [30] TX and RX Status
bogdanm	82:6473597d706e	1311	uint32_t TCF : 1; //!< [31] Transfer Complete Flag
bogdanm	82:6473597d706e	1312	} B;
bogdanm	82:6473597d706e	1313	} hw_spi_sr_t;
bogdanm	82:6473597d706e	1314	#endif
bogdanm	82:6473597d706e	1315
bogdanm	82:6473597d706e	1316	/*!
bogdanm	82:6473597d706e	1317	* @name Constants and macros for entire SPI_SR register
bogdanm	82:6473597d706e	1318	*/
bogdanm	82:6473597d706e	1319	//@{
bogdanm	82:6473597d706e	1320	#define HW_SPI_SR_ADDR(x) (REGS_SPI_BASE(x) + 0x2CU)
bogdanm	82:6473597d706e	1321
bogdanm	82:6473597d706e	1322	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1323	#define HW_SPI_SR(x) ((__IO hw_spi_sr_t ) HW_SPI_SR_ADDR(x))
bogdanm	82:6473597d706e	1324	#define HW_SPI_SR_RD(x) (HW_SPI_SR(x).U)
bogdanm	82:6473597d706e	1325	#define HW_SPI_SR_WR(x, v) (HW_SPI_SR(x).U = (v))
bogdanm	82:6473597d706e	1326	#define HW_SPI_SR_SET(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) \| (v)))
bogdanm	82:6473597d706e	1327	#define HW_SPI_SR_CLR(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1328	#define HW_SPI_SR_TOG(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1329	#endif
bogdanm	82:6473597d706e	1330	//@}
bogdanm	82:6473597d706e	1331
bogdanm	82:6473597d706e	1332	/*
bogdanm	82:6473597d706e	1333	* Constants & macros for individual SPI_SR bitfields
bogdanm	82:6473597d706e	1334	*/
bogdanm	82:6473597d706e	1335
bogdanm	82:6473597d706e	1336	/*!
bogdanm	82:6473597d706e	1337	* @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
bogdanm	82:6473597d706e	1338	*
bogdanm	82:6473597d706e	1339	* Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
bogdanm	82:6473597d706e	1340	* The POPNXTPTR is updated when the POPR is read.
bogdanm	82:6473597d706e	1341	*/
bogdanm	82:6473597d706e	1342	//@{
bogdanm	82:6473597d706e	1343	#define BP_SPI_SR_POPNXTPTR (0U) //!< Bit position for SPI_SR_POPNXTPTR.
bogdanm	82:6473597d706e	1344	#define BM_SPI_SR_POPNXTPTR (0x0000000FU) //!< Bit mask for SPI_SR_POPNXTPTR.
bogdanm	82:6473597d706e	1345	#define BS_SPI_SR_POPNXTPTR (4U) //!< Bit field size in bits for SPI_SR_POPNXTPTR.
bogdanm	82:6473597d706e	1346
bogdanm	82:6473597d706e	1347	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1348	//! @brief Read current value of the SPI_SR_POPNXTPTR field.
bogdanm	82:6473597d706e	1349	#define BR_SPI_SR_POPNXTPTR(x) (HW_SPI_SR(x).B.POPNXTPTR)
bogdanm	82:6473597d706e	1350	#endif
bogdanm	82:6473597d706e	1351	//@}
bogdanm	82:6473597d706e	1352
bogdanm	82:6473597d706e	1353	/*!
bogdanm	82:6473597d706e	1354	* @name Register SPI_SR, field RXCTR[7:4] (RO)
bogdanm	82:6473597d706e	1355	*
bogdanm	82:6473597d706e	1356	* Indicates the number of entries in the RX FIFO. The RXCTR is decremented
bogdanm	82:6473597d706e	1357	* every time the POPR is read. The RXCTR is incremented every time data is
bogdanm	82:6473597d706e	1358	* transferred from the shift register to the RX FIFO.
bogdanm	82:6473597d706e	1359	*/
bogdanm	82:6473597d706e	1360	//@{
bogdanm	82:6473597d706e	1361	#define BP_SPI_SR_RXCTR (4U) //!< Bit position for SPI_SR_RXCTR.
bogdanm	82:6473597d706e	1362	#define BM_SPI_SR_RXCTR (0x000000F0U) //!< Bit mask for SPI_SR_RXCTR.
bogdanm	82:6473597d706e	1363	#define BS_SPI_SR_RXCTR (4U) //!< Bit field size in bits for SPI_SR_RXCTR.
bogdanm	82:6473597d706e	1364
bogdanm	82:6473597d706e	1365	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1366	//! @brief Read current value of the SPI_SR_RXCTR field.
bogdanm	82:6473597d706e	1367	#define BR_SPI_SR_RXCTR(x) (HW_SPI_SR(x).B.RXCTR)
bogdanm	82:6473597d706e	1368	#endif
bogdanm	82:6473597d706e	1369	//@}
bogdanm	82:6473597d706e	1370
bogdanm	82:6473597d706e	1371	/*!
bogdanm	82:6473597d706e	1372	* @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
bogdanm	82:6473597d706e	1373	*
bogdanm	82:6473597d706e	1374	* Indicates which TX FIFO entry is transmitted during the next transfer. The
bogdanm	82:6473597d706e	1375	* TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
bogdanm	82:6473597d706e	1376	* the shift register.
bogdanm	82:6473597d706e	1377	*/
bogdanm	82:6473597d706e	1378	//@{
bogdanm	82:6473597d706e	1379	#define BP_SPI_SR_TXNXTPTR (8U) //!< Bit position for SPI_SR_TXNXTPTR.
bogdanm	82:6473597d706e	1380	#define BM_SPI_SR_TXNXTPTR (0x00000F00U) //!< Bit mask for SPI_SR_TXNXTPTR.
bogdanm	82:6473597d706e	1381	#define BS_SPI_SR_TXNXTPTR (4U) //!< Bit field size in bits for SPI_SR_TXNXTPTR.
bogdanm	82:6473597d706e	1382
bogdanm	82:6473597d706e	1383	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1384	//! @brief Read current value of the SPI_SR_TXNXTPTR field.
bogdanm	82:6473597d706e	1385	#define BR_SPI_SR_TXNXTPTR(x) (HW_SPI_SR(x).B.TXNXTPTR)
bogdanm	82:6473597d706e	1386	#endif
bogdanm	82:6473597d706e	1387	//@}
bogdanm	82:6473597d706e	1388
bogdanm	82:6473597d706e	1389	/*!
bogdanm	82:6473597d706e	1390	* @name Register SPI_SR, field TXCTR[15:12] (RO)
bogdanm	82:6473597d706e	1391	*
bogdanm	82:6473597d706e	1392	* Indicates the number of valid entries in the TX FIFO. The TXCTR is
bogdanm	82:6473597d706e	1393	* incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
bogdanm	82:6473597d706e	1394	* command is executed and the SPI data is transferred to the shift register.
bogdanm	82:6473597d706e	1395	*/
bogdanm	82:6473597d706e	1396	//@{
bogdanm	82:6473597d706e	1397	#define BP_SPI_SR_TXCTR (12U) //!< Bit position for SPI_SR_TXCTR.
bogdanm	82:6473597d706e	1398	#define BM_SPI_SR_TXCTR (0x0000F000U) //!< Bit mask for SPI_SR_TXCTR.
bogdanm	82:6473597d706e	1399	#define BS_SPI_SR_TXCTR (4U) //!< Bit field size in bits for SPI_SR_TXCTR.
bogdanm	82:6473597d706e	1400
bogdanm	82:6473597d706e	1401	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1402	//! @brief Read current value of the SPI_SR_TXCTR field.
bogdanm	82:6473597d706e	1403	#define BR_SPI_SR_TXCTR(x) (HW_SPI_SR(x).B.TXCTR)
bogdanm	82:6473597d706e	1404	#endif
bogdanm	82:6473597d706e	1405	//@}
bogdanm	82:6473597d706e	1406
bogdanm	82:6473597d706e	1407	/*!
bogdanm	82:6473597d706e	1408	* @name Register SPI_SR, field RFDF[17] (W1C)
bogdanm	82:6473597d706e	1409	*
bogdanm	82:6473597d706e	1410	* Provides a method for the module to request that entries be removed from the
bogdanm	82:6473597d706e	1411	* RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
bogdanm	82:6473597d706e	1412	* cleared by writing 1 to it or by acknowledgement from the DMA controller when
bogdanm	82:6473597d706e	1413	* the RX FIFO is empty.
bogdanm	82:6473597d706e	1414	*
bogdanm	82:6473597d706e	1415	* Values:
bogdanm	82:6473597d706e	1416	* - 0 - RX FIFO is empty.
bogdanm	82:6473597d706e	1417	* - 1 - RX FIFO is not empty.
bogdanm	82:6473597d706e	1418	*/
bogdanm	82:6473597d706e	1419	//@{
bogdanm	82:6473597d706e	1420	#define BP_SPI_SR_RFDF (17U) //!< Bit position for SPI_SR_RFDF.
bogdanm	82:6473597d706e	1421	#define BM_SPI_SR_RFDF (0x00020000U) //!< Bit mask for SPI_SR_RFDF.
bogdanm	82:6473597d706e	1422	#define BS_SPI_SR_RFDF (1U) //!< Bit field size in bits for SPI_SR_RFDF.
bogdanm	82:6473597d706e	1423
bogdanm	82:6473597d706e	1424	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1425	//! @brief Read current value of the SPI_SR_RFDF field.
bogdanm	82:6473597d706e	1426	#define BR_SPI_SR_RFDF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF))
bogdanm	82:6473597d706e	1427	#endif
bogdanm	82:6473597d706e	1428
bogdanm	82:6473597d706e	1429	//! @brief Format value for bitfield SPI_SR_RFDF.
bogdanm	82:6473597d706e	1430	#define BF_SPI_SR_RFDF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_RFDF), uint32_t) & BM_SPI_SR_RFDF)
bogdanm	82:6473597d706e	1431
bogdanm	82:6473597d706e	1432	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1433	//! @brief Set the RFDF field to a new value.
bogdanm	82:6473597d706e	1434	#define BW_SPI_SR_RFDF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF) = (v))
bogdanm	82:6473597d706e	1435	#endif
bogdanm	82:6473597d706e	1436	//@}
bogdanm	82:6473597d706e	1437
bogdanm	82:6473597d706e	1438	/*!
bogdanm	82:6473597d706e	1439	* @name Register SPI_SR, field RFOF[19] (W1C)
bogdanm	82:6473597d706e	1440	*
bogdanm	82:6473597d706e	1441	* Indicates an overflow condition in the RX FIFO. The field is set when the RX
bogdanm	82:6473597d706e	1442	* FIFO and shift register are full and a transfer is initiated. The bit remains
bogdanm	82:6473597d706e	1443	* set until it is cleared by writing a 1 to it.
bogdanm	82:6473597d706e	1444	*
bogdanm	82:6473597d706e	1445	* Values:
bogdanm	82:6473597d706e	1446	* - 0 - No Rx FIFO overflow.
bogdanm	82:6473597d706e	1447	* - 1 - Rx FIFO overflow has occurred.
bogdanm	82:6473597d706e	1448	*/
bogdanm	82:6473597d706e	1449	//@{
bogdanm	82:6473597d706e	1450	#define BP_SPI_SR_RFOF (19U) //!< Bit position for SPI_SR_RFOF.
bogdanm	82:6473597d706e	1451	#define BM_SPI_SR_RFOF (0x00080000U) //!< Bit mask for SPI_SR_RFOF.
bogdanm	82:6473597d706e	1452	#define BS_SPI_SR_RFOF (1U) //!< Bit field size in bits for SPI_SR_RFOF.
bogdanm	82:6473597d706e	1453
bogdanm	82:6473597d706e	1454	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1455	//! @brief Read current value of the SPI_SR_RFOF field.
bogdanm	82:6473597d706e	1456	#define BR_SPI_SR_RFOF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF))
bogdanm	82:6473597d706e	1457	#endif
bogdanm	82:6473597d706e	1458
bogdanm	82:6473597d706e	1459	//! @brief Format value for bitfield SPI_SR_RFOF.
bogdanm	82:6473597d706e	1460	#define BF_SPI_SR_RFOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_RFOF), uint32_t) & BM_SPI_SR_RFOF)
bogdanm	82:6473597d706e	1461
bogdanm	82:6473597d706e	1462	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1463	//! @brief Set the RFOF field to a new value.
bogdanm	82:6473597d706e	1464	#define BW_SPI_SR_RFOF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF) = (v))
bogdanm	82:6473597d706e	1465	#endif
bogdanm	82:6473597d706e	1466	//@}
bogdanm	82:6473597d706e	1467
bogdanm	82:6473597d706e	1468	/*!
bogdanm	82:6473597d706e	1469	* @name Register SPI_SR, field TFFF[25] (W1C)
bogdanm	82:6473597d706e	1470	*
bogdanm	82:6473597d706e	1471	* Provides a method for the module to request more entries to be added to the
bogdanm	82:6473597d706e	1472	* TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
bogdanm	82:6473597d706e	1473	* cleared by writing 1 to it or by acknowledgement from the DMA controller to
bogdanm	82:6473597d706e	1474	* the TX FIFO full request.
bogdanm	82:6473597d706e	1475	*
bogdanm	82:6473597d706e	1476	* Values:
bogdanm	82:6473597d706e	1477	* - 0 - TX FIFO is full.
bogdanm	82:6473597d706e	1478	* - 1 - TX FIFO is not full.
bogdanm	82:6473597d706e	1479	*/
bogdanm	82:6473597d706e	1480	//@{
bogdanm	82:6473597d706e	1481	#define BP_SPI_SR_TFFF (25U) //!< Bit position for SPI_SR_TFFF.
bogdanm	82:6473597d706e	1482	#define BM_SPI_SR_TFFF (0x02000000U) //!< Bit mask for SPI_SR_TFFF.
bogdanm	82:6473597d706e	1483	#define BS_SPI_SR_TFFF (1U) //!< Bit field size in bits for SPI_SR_TFFF.
bogdanm	82:6473597d706e	1484
bogdanm	82:6473597d706e	1485	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1486	//! @brief Read current value of the SPI_SR_TFFF field.
bogdanm	82:6473597d706e	1487	#define BR_SPI_SR_TFFF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF))
bogdanm	82:6473597d706e	1488	#endif
bogdanm	82:6473597d706e	1489
bogdanm	82:6473597d706e	1490	//! @brief Format value for bitfield SPI_SR_TFFF.
bogdanm	82:6473597d706e	1491	#define BF_SPI_SR_TFFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TFFF), uint32_t) & BM_SPI_SR_TFFF)
bogdanm	82:6473597d706e	1492
bogdanm	82:6473597d706e	1493	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1494	//! @brief Set the TFFF field to a new value.
bogdanm	82:6473597d706e	1495	#define BW_SPI_SR_TFFF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF) = (v))
bogdanm	82:6473597d706e	1496	#endif
bogdanm	82:6473597d706e	1497	//@}
bogdanm	82:6473597d706e	1498
bogdanm	82:6473597d706e	1499	/*!
bogdanm	82:6473597d706e	1500	* @name Register SPI_SR, field TFUF[27] (W1C)
bogdanm	82:6473597d706e	1501	*
bogdanm	82:6473597d706e	1502	* Indicates an underflow condition in the TX FIFO. The transmit underflow
bogdanm	82:6473597d706e	1503	* condition is detected only for SPI blocks operating in Slave mode and SPI
bogdanm	82:6473597d706e	1504	* configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
bogdanm	82:6473597d706e	1505	* is empty and an external SPI master initiates a transfer. The TFUF bit remains
bogdanm	82:6473597d706e	1506	* set until cleared by writing 1 to it.
bogdanm	82:6473597d706e	1507	*
bogdanm	82:6473597d706e	1508	* Values:
bogdanm	82:6473597d706e	1509	* - 0 - No TX FIFO underflow.
bogdanm	82:6473597d706e	1510	* - 1 - TX FIFO underflow has occurred.
bogdanm	82:6473597d706e	1511	*/
bogdanm	82:6473597d706e	1512	//@{
bogdanm	82:6473597d706e	1513	#define BP_SPI_SR_TFUF (27U) //!< Bit position for SPI_SR_TFUF.
bogdanm	82:6473597d706e	1514	#define BM_SPI_SR_TFUF (0x08000000U) //!< Bit mask for SPI_SR_TFUF.
bogdanm	82:6473597d706e	1515	#define BS_SPI_SR_TFUF (1U) //!< Bit field size in bits for SPI_SR_TFUF.
bogdanm	82:6473597d706e	1516
bogdanm	82:6473597d706e	1517	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1518	//! @brief Read current value of the SPI_SR_TFUF field.
bogdanm	82:6473597d706e	1519	#define BR_SPI_SR_TFUF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF))
bogdanm	82:6473597d706e	1520	#endif
bogdanm	82:6473597d706e	1521
bogdanm	82:6473597d706e	1522	//! @brief Format value for bitfield SPI_SR_TFUF.
bogdanm	82:6473597d706e	1523	#define BF_SPI_SR_TFUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TFUF), uint32_t) & BM_SPI_SR_TFUF)
bogdanm	82:6473597d706e	1524
bogdanm	82:6473597d706e	1525	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1526	//! @brief Set the TFUF field to a new value.
bogdanm	82:6473597d706e	1527	#define BW_SPI_SR_TFUF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF) = (v))
bogdanm	82:6473597d706e	1528	#endif
bogdanm	82:6473597d706e	1529	//@}
bogdanm	82:6473597d706e	1530
bogdanm	82:6473597d706e	1531	/*!
bogdanm	82:6473597d706e	1532	* @name Register SPI_SR, field EOQF[28] (W1C)
bogdanm	82:6473597d706e	1533	*
bogdanm	82:6473597d706e	1534	* Indicates that the last entry in a queue has been transmitted when the module
bogdanm	82:6473597d706e	1535	* is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
bogdanm	82:6473597d706e	1536	* set in the command halfword and the end of the transfer is reached. The EOQF
bogdanm	82:6473597d706e	1537	* bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
bogdanm	82:6473597d706e	1538	* the TXRXS bit is automatically cleared.
bogdanm	82:6473597d706e	1539	*
bogdanm	82:6473597d706e	1540	* Values:
bogdanm	82:6473597d706e	1541	* - 0 - EOQ is not set in the executing command.
bogdanm	82:6473597d706e	1542	* - 1 - EOQ is set in the executing SPI command.
bogdanm	82:6473597d706e	1543	*/
bogdanm	82:6473597d706e	1544	//@{
bogdanm	82:6473597d706e	1545	#define BP_SPI_SR_EOQF (28U) //!< Bit position for SPI_SR_EOQF.
bogdanm	82:6473597d706e	1546	#define BM_SPI_SR_EOQF (0x10000000U) //!< Bit mask for SPI_SR_EOQF.
bogdanm	82:6473597d706e	1547	#define BS_SPI_SR_EOQF (1U) //!< Bit field size in bits for SPI_SR_EOQF.
bogdanm	82:6473597d706e	1548
bogdanm	82:6473597d706e	1549	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1550	//! @brief Read current value of the SPI_SR_EOQF field.
bogdanm	82:6473597d706e	1551	#define BR_SPI_SR_EOQF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF))
bogdanm	82:6473597d706e	1552	#endif
bogdanm	82:6473597d706e	1553
bogdanm	82:6473597d706e	1554	//! @brief Format value for bitfield SPI_SR_EOQF.
bogdanm	82:6473597d706e	1555	#define BF_SPI_SR_EOQF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_EOQF), uint32_t) & BM_SPI_SR_EOQF)
bogdanm	82:6473597d706e	1556
bogdanm	82:6473597d706e	1557	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1558	//! @brief Set the EOQF field to a new value.
bogdanm	82:6473597d706e	1559	#define BW_SPI_SR_EOQF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF) = (v))
bogdanm	82:6473597d706e	1560	#endif
bogdanm	82:6473597d706e	1561	//@}
bogdanm	82:6473597d706e	1562
bogdanm	82:6473597d706e	1563	/*!
bogdanm	82:6473597d706e	1564	* @name Register SPI_SR, field TXRXS[30] (W1C)
bogdanm	82:6473597d706e	1565	*
bogdanm	82:6473597d706e	1566	* Reflects the run status of the module.
bogdanm	82:6473597d706e	1567	*
bogdanm	82:6473597d706e	1568	* Values:
bogdanm	82:6473597d706e	1569	* - 0 - Transmit and receive operations are disabled (The module is in Stopped
bogdanm	82:6473597d706e	1570	* state).
bogdanm	82:6473597d706e	1571	* - 1 - Transmit and receive operations are enabled (The module is in Running
bogdanm	82:6473597d706e	1572	* state).
bogdanm	82:6473597d706e	1573	*/
bogdanm	82:6473597d706e	1574	//@{
bogdanm	82:6473597d706e	1575	#define BP_SPI_SR_TXRXS (30U) //!< Bit position for SPI_SR_TXRXS.
bogdanm	82:6473597d706e	1576	#define BM_SPI_SR_TXRXS (0x40000000U) //!< Bit mask for SPI_SR_TXRXS.
bogdanm	82:6473597d706e	1577	#define BS_SPI_SR_TXRXS (1U) //!< Bit field size in bits for SPI_SR_TXRXS.
bogdanm	82:6473597d706e	1578
bogdanm	82:6473597d706e	1579	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1580	//! @brief Read current value of the SPI_SR_TXRXS field.
bogdanm	82:6473597d706e	1581	#define BR_SPI_SR_TXRXS(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS))
bogdanm	82:6473597d706e	1582	#endif
bogdanm	82:6473597d706e	1583
bogdanm	82:6473597d706e	1584	//! @brief Format value for bitfield SPI_SR_TXRXS.
bogdanm	82:6473597d706e	1585	#define BF_SPI_SR_TXRXS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TXRXS), uint32_t) & BM_SPI_SR_TXRXS)
bogdanm	82:6473597d706e	1586
bogdanm	82:6473597d706e	1587	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1588	//! @brief Set the TXRXS field to a new value.
bogdanm	82:6473597d706e	1589	#define BW_SPI_SR_TXRXS(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS) = (v))
bogdanm	82:6473597d706e	1590	#endif
bogdanm	82:6473597d706e	1591	//@}
bogdanm	82:6473597d706e	1592
bogdanm	82:6473597d706e	1593	/*!
bogdanm	82:6473597d706e	1594	* @name Register SPI_SR, field TCF[31] (W1C)
bogdanm	82:6473597d706e	1595	*
bogdanm	82:6473597d706e	1596	* Indicates that all bits in a frame have been shifted out. TCF remains set
bogdanm	82:6473597d706e	1597	* until it is cleared by writing a 1 to it.
bogdanm	82:6473597d706e	1598	*
bogdanm	82:6473597d706e	1599	* Values:
bogdanm	82:6473597d706e	1600	* - 0 - Transfer not complete.
bogdanm	82:6473597d706e	1601	* - 1 - Transfer complete.
bogdanm	82:6473597d706e	1602	*/
bogdanm	82:6473597d706e	1603	//@{
bogdanm	82:6473597d706e	1604	#define BP_SPI_SR_TCF (31U) //!< Bit position for SPI_SR_TCF.
bogdanm	82:6473597d706e	1605	#define BM_SPI_SR_TCF (0x80000000U) //!< Bit mask for SPI_SR_TCF.
bogdanm	82:6473597d706e	1606	#define BS_SPI_SR_TCF (1U) //!< Bit field size in bits for SPI_SR_TCF.
bogdanm	82:6473597d706e	1607
bogdanm	82:6473597d706e	1608	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1609	//! @brief Read current value of the SPI_SR_TCF field.
bogdanm	82:6473597d706e	1610	#define BR_SPI_SR_TCF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF))
bogdanm	82:6473597d706e	1611	#endif
bogdanm	82:6473597d706e	1612
bogdanm	82:6473597d706e	1613	//! @brief Format value for bitfield SPI_SR_TCF.
bogdanm	82:6473597d706e	1614	#define BF_SPI_SR_TCF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TCF), uint32_t) & BM_SPI_SR_TCF)
bogdanm	82:6473597d706e	1615
bogdanm	82:6473597d706e	1616	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1617	//! @brief Set the TCF field to a new value.
bogdanm	82:6473597d706e	1618	#define BW_SPI_SR_TCF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF) = (v))
bogdanm	82:6473597d706e	1619	#endif
bogdanm	82:6473597d706e	1620	//@}
bogdanm	82:6473597d706e	1621
bogdanm	82:6473597d706e	1622	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1623	// HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
bogdanm	82:6473597d706e	1624	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1625
bogdanm	82:6473597d706e	1626	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1627	/*!
bogdanm	82:6473597d706e	1628	* @brief HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
bogdanm	82:6473597d706e	1629	*
bogdanm	82:6473597d706e	1630	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1631	*
bogdanm	82:6473597d706e	1632	* RSER controls DMA and interrupt requests. Do not write to the RSER while the
bogdanm	82:6473597d706e	1633	* module is in the Running state.
bogdanm	82:6473597d706e	1634	*/
bogdanm	82:6473597d706e	1635	typedef union _hw_spi_rser
bogdanm	82:6473597d706e	1636	{
bogdanm	82:6473597d706e	1637	uint32_t U;
bogdanm	82:6473597d706e	1638	struct _hw_spi_rser_bitfields
bogdanm	82:6473597d706e	1639	{
bogdanm	82:6473597d706e	1640	uint32_t RESERVED0 : 16; //!< [15:0]
bogdanm	82:6473597d706e	1641	uint32_t RFDF_DIRS : 1; //!< [16] Receive FIFO Drain DMA or Interrupt
bogdanm	82:6473597d706e	1642	//! Request Select
bogdanm	82:6473597d706e	1643	uint32_t RFDF_RE : 1; //!< [17] Receive FIFO Drain Request Enable
bogdanm	82:6473597d706e	1644	uint32_t RESERVED1 : 1; //!< [18]
bogdanm	82:6473597d706e	1645	uint32_t RFOF_RE : 1; //!< [19] Receive FIFO Overflow Request Enable
bogdanm	82:6473597d706e	1646	uint32_t RESERVED2 : 4; //!< [23:20]
bogdanm	82:6473597d706e	1647	uint32_t TFFF_DIRS : 1; //!< [24] Transmit FIFO Fill DMA or Interrupt
bogdanm	82:6473597d706e	1648	//! Request Select
bogdanm	82:6473597d706e	1649	uint32_t TFFF_RE : 1; //!< [25] Transmit FIFO Fill Request Enable
bogdanm	82:6473597d706e	1650	uint32_t RESERVED3 : 1; //!< [26]
bogdanm	82:6473597d706e	1651	uint32_t TFUF_RE : 1; //!< [27] Transmit FIFO Underflow Request Enable
bogdanm	82:6473597d706e	1652	uint32_t EOQF_RE : 1; //!< [28] Finished Request Enable
bogdanm	82:6473597d706e	1653	uint32_t RESERVED4 : 2; //!< [30:29]
bogdanm	82:6473597d706e	1654	uint32_t TCF_RE : 1; //!< [31] Transmission Complete Request Enable
bogdanm	82:6473597d706e	1655	} B;
bogdanm	82:6473597d706e	1656	} hw_spi_rser_t;
bogdanm	82:6473597d706e	1657	#endif
bogdanm	82:6473597d706e	1658
bogdanm	82:6473597d706e	1659	/*!
bogdanm	82:6473597d706e	1660	* @name Constants and macros for entire SPI_RSER register
bogdanm	82:6473597d706e	1661	*/
bogdanm	82:6473597d706e	1662	//@{
bogdanm	82:6473597d706e	1663	#define HW_SPI_RSER_ADDR(x) (REGS_SPI_BASE(x) + 0x30U)
bogdanm	82:6473597d706e	1664
bogdanm	82:6473597d706e	1665	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1666	#define HW_SPI_RSER(x) ((__IO hw_spi_rser_t ) HW_SPI_RSER_ADDR(x))
bogdanm	82:6473597d706e	1667	#define HW_SPI_RSER_RD(x) (HW_SPI_RSER(x).U)
bogdanm	82:6473597d706e	1668	#define HW_SPI_RSER_WR(x, v) (HW_SPI_RSER(x).U = (v))
bogdanm	82:6473597d706e	1669	#define HW_SPI_RSER_SET(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) \| (v)))
bogdanm	82:6473597d706e	1670	#define HW_SPI_RSER_CLR(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1671	#define HW_SPI_RSER_TOG(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1672	#endif
bogdanm	82:6473597d706e	1673	//@}
bogdanm	82:6473597d706e	1674
bogdanm	82:6473597d706e	1675	/*
bogdanm	82:6473597d706e	1676	* Constants & macros for individual SPI_RSER bitfields
bogdanm	82:6473597d706e	1677	*/
bogdanm	82:6473597d706e	1678
bogdanm	82:6473597d706e	1679	/*!
bogdanm	82:6473597d706e	1680	* @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
bogdanm	82:6473597d706e	1681	*
bogdanm	82:6473597d706e	1682	* Selects between generating a DMA request or an interrupt request. When the
bogdanm	82:6473597d706e	1683	* RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
bogdanm	82:6473597d706e	1684	* RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
bogdanm	82:6473597d706e	1685	*
bogdanm	82:6473597d706e	1686	* Values:
bogdanm	82:6473597d706e	1687	* - 0 - Interrupt request.
bogdanm	82:6473597d706e	1688	* - 1 - DMA request.
bogdanm	82:6473597d706e	1689	*/
bogdanm	82:6473597d706e	1690	//@{
bogdanm	82:6473597d706e	1691	#define BP_SPI_RSER_RFDF_DIRS (16U) //!< Bit position for SPI_RSER_RFDF_DIRS.
bogdanm	82:6473597d706e	1692	#define BM_SPI_RSER_RFDF_DIRS (0x00010000U) //!< Bit mask for SPI_RSER_RFDF_DIRS.
bogdanm	82:6473597d706e	1693	#define BS_SPI_RSER_RFDF_DIRS (1U) //!< Bit field size in bits for SPI_RSER_RFDF_DIRS.
bogdanm	82:6473597d706e	1694
bogdanm	82:6473597d706e	1695	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1696	//! @brief Read current value of the SPI_RSER_RFDF_DIRS field.
bogdanm	82:6473597d706e	1697	#define BR_SPI_RSER_RFDF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS))
bogdanm	82:6473597d706e	1698	#endif
bogdanm	82:6473597d706e	1699
bogdanm	82:6473597d706e	1700	//! @brief Format value for bitfield SPI_RSER_RFDF_DIRS.
bogdanm	82:6473597d706e	1701	#define BF_SPI_RSER_RFDF_DIRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFDF_DIRS), uint32_t) & BM_SPI_RSER_RFDF_DIRS)
bogdanm	82:6473597d706e	1702
bogdanm	82:6473597d706e	1703	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1704	//! @brief Set the RFDF_DIRS field to a new value.
bogdanm	82:6473597d706e	1705	#define BW_SPI_RSER_RFDF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS) = (v))
bogdanm	82:6473597d706e	1706	#endif
bogdanm	82:6473597d706e	1707	//@}
bogdanm	82:6473597d706e	1708
bogdanm	82:6473597d706e	1709	/*!
bogdanm	82:6473597d706e	1710	* @name Register SPI_RSER, field RFDF_RE[17] (RW)
bogdanm	82:6473597d706e	1711	*
bogdanm	82:6473597d706e	1712	* Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
bogdanm	82:6473597d706e	1713	* selects between generating an interrupt request or a DMA request.
bogdanm	82:6473597d706e	1714	*
bogdanm	82:6473597d706e	1715	* Values:
bogdanm	82:6473597d706e	1716	* - 0 - RFDF interrupt or DMA requests are disabled.
bogdanm	82:6473597d706e	1717	* - 1 - RFDF interrupt or DMA requests are enabled.
bogdanm	82:6473597d706e	1718	*/
bogdanm	82:6473597d706e	1719	//@{
bogdanm	82:6473597d706e	1720	#define BP_SPI_RSER_RFDF_RE (17U) //!< Bit position for SPI_RSER_RFDF_RE.
bogdanm	82:6473597d706e	1721	#define BM_SPI_RSER_RFDF_RE (0x00020000U) //!< Bit mask for SPI_RSER_RFDF_RE.
bogdanm	82:6473597d706e	1722	#define BS_SPI_RSER_RFDF_RE (1U) //!< Bit field size in bits for SPI_RSER_RFDF_RE.
bogdanm	82:6473597d706e	1723
bogdanm	82:6473597d706e	1724	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1725	//! @brief Read current value of the SPI_RSER_RFDF_RE field.
bogdanm	82:6473597d706e	1726	#define BR_SPI_RSER_RFDF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE))
bogdanm	82:6473597d706e	1727	#endif
bogdanm	82:6473597d706e	1728
bogdanm	82:6473597d706e	1729	//! @brief Format value for bitfield SPI_RSER_RFDF_RE.
bogdanm	82:6473597d706e	1730	#define BF_SPI_RSER_RFDF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFDF_RE), uint32_t) & BM_SPI_RSER_RFDF_RE)
bogdanm	82:6473597d706e	1731
bogdanm	82:6473597d706e	1732	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1733	//! @brief Set the RFDF_RE field to a new value.
bogdanm	82:6473597d706e	1734	#define BW_SPI_RSER_RFDF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE) = (v))
bogdanm	82:6473597d706e	1735	#endif
bogdanm	82:6473597d706e	1736	//@}
bogdanm	82:6473597d706e	1737
bogdanm	82:6473597d706e	1738	/*!
bogdanm	82:6473597d706e	1739	* @name Register SPI_RSER, field RFOF_RE[19] (RW)
bogdanm	82:6473597d706e	1740	*
bogdanm	82:6473597d706e	1741	* Enables the RFOF flag in the SR to generate an interrupt request.
bogdanm	82:6473597d706e	1742	*
bogdanm	82:6473597d706e	1743	* Values:
bogdanm	82:6473597d706e	1744	* - 0 - RFOF interrupt requests are disabled.
bogdanm	82:6473597d706e	1745	* - 1 - RFOF interrupt requests are enabled.
bogdanm	82:6473597d706e	1746	*/
bogdanm	82:6473597d706e	1747	//@{
bogdanm	82:6473597d706e	1748	#define BP_SPI_RSER_RFOF_RE (19U) //!< Bit position for SPI_RSER_RFOF_RE.
bogdanm	82:6473597d706e	1749	#define BM_SPI_RSER_RFOF_RE (0x00080000U) //!< Bit mask for SPI_RSER_RFOF_RE.
bogdanm	82:6473597d706e	1750	#define BS_SPI_RSER_RFOF_RE (1U) //!< Bit field size in bits for SPI_RSER_RFOF_RE.
bogdanm	82:6473597d706e	1751
bogdanm	82:6473597d706e	1752	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1753	//! @brief Read current value of the SPI_RSER_RFOF_RE field.
bogdanm	82:6473597d706e	1754	#define BR_SPI_RSER_RFOF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE))
bogdanm	82:6473597d706e	1755	#endif
bogdanm	82:6473597d706e	1756
bogdanm	82:6473597d706e	1757	//! @brief Format value for bitfield SPI_RSER_RFOF_RE.
bogdanm	82:6473597d706e	1758	#define BF_SPI_RSER_RFOF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFOF_RE), uint32_t) & BM_SPI_RSER_RFOF_RE)
bogdanm	82:6473597d706e	1759
bogdanm	82:6473597d706e	1760	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1761	//! @brief Set the RFOF_RE field to a new value.
bogdanm	82:6473597d706e	1762	#define BW_SPI_RSER_RFOF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE) = (v))
bogdanm	82:6473597d706e	1763	#endif
bogdanm	82:6473597d706e	1764	//@}
bogdanm	82:6473597d706e	1765
bogdanm	82:6473597d706e	1766	/*!
bogdanm	82:6473597d706e	1767	* @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
bogdanm	82:6473597d706e	1768	*
bogdanm	82:6473597d706e	1769	* Selects between generating a DMA request or an interrupt request. When
bogdanm	82:6473597d706e	1770	* SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
bogdanm	82:6473597d706e	1771	* interrupt request or a DMA request.
bogdanm	82:6473597d706e	1772	*
bogdanm	82:6473597d706e	1773	* Values:
bogdanm	82:6473597d706e	1774	* - 0 - TFFF flag generates interrupt requests.
bogdanm	82:6473597d706e	1775	* - 1 - TFFF flag generates DMA requests.
bogdanm	82:6473597d706e	1776	*/
bogdanm	82:6473597d706e	1777	//@{
bogdanm	82:6473597d706e	1778	#define BP_SPI_RSER_TFFF_DIRS (24U) //!< Bit position for SPI_RSER_TFFF_DIRS.
bogdanm	82:6473597d706e	1779	#define BM_SPI_RSER_TFFF_DIRS (0x01000000U) //!< Bit mask for SPI_RSER_TFFF_DIRS.
bogdanm	82:6473597d706e	1780	#define BS_SPI_RSER_TFFF_DIRS (1U) //!< Bit field size in bits for SPI_RSER_TFFF_DIRS.
bogdanm	82:6473597d706e	1781
bogdanm	82:6473597d706e	1782	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1783	//! @brief Read current value of the SPI_RSER_TFFF_DIRS field.
bogdanm	82:6473597d706e	1784	#define BR_SPI_RSER_TFFF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS))
bogdanm	82:6473597d706e	1785	#endif
bogdanm	82:6473597d706e	1786
bogdanm	82:6473597d706e	1787	//! @brief Format value for bitfield SPI_RSER_TFFF_DIRS.
bogdanm	82:6473597d706e	1788	#define BF_SPI_RSER_TFFF_DIRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFFF_DIRS), uint32_t) & BM_SPI_RSER_TFFF_DIRS)
bogdanm	82:6473597d706e	1789
bogdanm	82:6473597d706e	1790	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1791	//! @brief Set the TFFF_DIRS field to a new value.
bogdanm	82:6473597d706e	1792	#define BW_SPI_RSER_TFFF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS) = (v))
bogdanm	82:6473597d706e	1793	#endif
bogdanm	82:6473597d706e	1794	//@}
bogdanm	82:6473597d706e	1795
bogdanm	82:6473597d706e	1796	/*!
bogdanm	82:6473597d706e	1797	* @name Register SPI_RSER, field TFFF_RE[25] (RW)
bogdanm	82:6473597d706e	1798	*
bogdanm	82:6473597d706e	1799	* Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
bogdanm	82:6473597d706e	1800	* selects between generating an interrupt request or a DMA request.
bogdanm	82:6473597d706e	1801	*
bogdanm	82:6473597d706e	1802	* Values:
bogdanm	82:6473597d706e	1803	* - 0 - TFFF interrupts or DMA requests are disabled.
bogdanm	82:6473597d706e	1804	* - 1 - TFFF interrupts or DMA requests are enabled.
bogdanm	82:6473597d706e	1805	*/
bogdanm	82:6473597d706e	1806	//@{
bogdanm	82:6473597d706e	1807	#define BP_SPI_RSER_TFFF_RE (25U) //!< Bit position for SPI_RSER_TFFF_RE.
bogdanm	82:6473597d706e	1808	#define BM_SPI_RSER_TFFF_RE (0x02000000U) //!< Bit mask for SPI_RSER_TFFF_RE.
bogdanm	82:6473597d706e	1809	#define BS_SPI_RSER_TFFF_RE (1U) //!< Bit field size in bits for SPI_RSER_TFFF_RE.
bogdanm	82:6473597d706e	1810
bogdanm	82:6473597d706e	1811	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1812	//! @brief Read current value of the SPI_RSER_TFFF_RE field.
bogdanm	82:6473597d706e	1813	#define BR_SPI_RSER_TFFF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE))
bogdanm	82:6473597d706e	1814	#endif
bogdanm	82:6473597d706e	1815
bogdanm	82:6473597d706e	1816	//! @brief Format value for bitfield SPI_RSER_TFFF_RE.
bogdanm	82:6473597d706e	1817	#define BF_SPI_RSER_TFFF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFFF_RE), uint32_t) & BM_SPI_RSER_TFFF_RE)
bogdanm	82:6473597d706e	1818
bogdanm	82:6473597d706e	1819	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1820	//! @brief Set the TFFF_RE field to a new value.
bogdanm	82:6473597d706e	1821	#define BW_SPI_RSER_TFFF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE) = (v))
bogdanm	82:6473597d706e	1822	#endif
bogdanm	82:6473597d706e	1823	//@}
bogdanm	82:6473597d706e	1824
bogdanm	82:6473597d706e	1825	/*!
bogdanm	82:6473597d706e	1826	* @name Register SPI_RSER, field TFUF_RE[27] (RW)
bogdanm	82:6473597d706e	1827	*
bogdanm	82:6473597d706e	1828	* Enables the TFUF flag in the SR to generate an interrupt request.
bogdanm	82:6473597d706e	1829	*
bogdanm	82:6473597d706e	1830	* Values:
bogdanm	82:6473597d706e	1831	* - 0 - TFUF interrupt requests are disabled.
bogdanm	82:6473597d706e	1832	* - 1 - TFUF interrupt requests are enabled.
bogdanm	82:6473597d706e	1833	*/
bogdanm	82:6473597d706e	1834	//@{
bogdanm	82:6473597d706e	1835	#define BP_SPI_RSER_TFUF_RE (27U) //!< Bit position for SPI_RSER_TFUF_RE.
bogdanm	82:6473597d706e	1836	#define BM_SPI_RSER_TFUF_RE (0x08000000U) //!< Bit mask for SPI_RSER_TFUF_RE.
bogdanm	82:6473597d706e	1837	#define BS_SPI_RSER_TFUF_RE (1U) //!< Bit field size in bits for SPI_RSER_TFUF_RE.
bogdanm	82:6473597d706e	1838
bogdanm	82:6473597d706e	1839	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1840	//! @brief Read current value of the SPI_RSER_TFUF_RE field.
bogdanm	82:6473597d706e	1841	#define BR_SPI_RSER_TFUF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE))
bogdanm	82:6473597d706e	1842	#endif
bogdanm	82:6473597d706e	1843
bogdanm	82:6473597d706e	1844	//! @brief Format value for bitfield SPI_RSER_TFUF_RE.
bogdanm	82:6473597d706e	1845	#define BF_SPI_RSER_TFUF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFUF_RE), uint32_t) & BM_SPI_RSER_TFUF_RE)
bogdanm	82:6473597d706e	1846
bogdanm	82:6473597d706e	1847	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1848	//! @brief Set the TFUF_RE field to a new value.
bogdanm	82:6473597d706e	1849	#define BW_SPI_RSER_TFUF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE) = (v))
bogdanm	82:6473597d706e	1850	#endif
bogdanm	82:6473597d706e	1851	//@}
bogdanm	82:6473597d706e	1852
bogdanm	82:6473597d706e	1853	/*!
bogdanm	82:6473597d706e	1854	* @name Register SPI_RSER, field EOQF_RE[28] (RW)
bogdanm	82:6473597d706e	1855	*
bogdanm	82:6473597d706e	1856	* Enables the EOQF flag in the SR to generate an interrupt request.
bogdanm	82:6473597d706e	1857	*
bogdanm	82:6473597d706e	1858	* Values:
bogdanm	82:6473597d706e	1859	* - 0 - EOQF interrupt requests are disabled.
bogdanm	82:6473597d706e	1860	* - 1 - EOQF interrupt requests are enabled.
bogdanm	82:6473597d706e	1861	*/
bogdanm	82:6473597d706e	1862	//@{
bogdanm	82:6473597d706e	1863	#define BP_SPI_RSER_EOQF_RE (28U) //!< Bit position for SPI_RSER_EOQF_RE.
bogdanm	82:6473597d706e	1864	#define BM_SPI_RSER_EOQF_RE (0x10000000U) //!< Bit mask for SPI_RSER_EOQF_RE.
bogdanm	82:6473597d706e	1865	#define BS_SPI_RSER_EOQF_RE (1U) //!< Bit field size in bits for SPI_RSER_EOQF_RE.
bogdanm	82:6473597d706e	1866
bogdanm	82:6473597d706e	1867	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1868	//! @brief Read current value of the SPI_RSER_EOQF_RE field.
bogdanm	82:6473597d706e	1869	#define BR_SPI_RSER_EOQF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE))
bogdanm	82:6473597d706e	1870	#endif
bogdanm	82:6473597d706e	1871
bogdanm	82:6473597d706e	1872	//! @brief Format value for bitfield SPI_RSER_EOQF_RE.
bogdanm	82:6473597d706e	1873	#define BF_SPI_RSER_EOQF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_EOQF_RE), uint32_t) & BM_SPI_RSER_EOQF_RE)
bogdanm	82:6473597d706e	1874
bogdanm	82:6473597d706e	1875	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1876	//! @brief Set the EOQF_RE field to a new value.
bogdanm	82:6473597d706e	1877	#define BW_SPI_RSER_EOQF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE) = (v))
bogdanm	82:6473597d706e	1878	#endif
bogdanm	82:6473597d706e	1879	//@}
bogdanm	82:6473597d706e	1880
bogdanm	82:6473597d706e	1881	/*!
bogdanm	82:6473597d706e	1882	* @name Register SPI_RSER, field TCF_RE[31] (RW)
bogdanm	82:6473597d706e	1883	*
bogdanm	82:6473597d706e	1884	* Enables TCF flag in the SR to generate an interrupt request.
bogdanm	82:6473597d706e	1885	*
bogdanm	82:6473597d706e	1886	* Values:
bogdanm	82:6473597d706e	1887	* - 0 - TCF interrupt requests are disabled.
bogdanm	82:6473597d706e	1888	* - 1 - TCF interrupt requests are enabled.
bogdanm	82:6473597d706e	1889	*/
bogdanm	82:6473597d706e	1890	//@{
bogdanm	82:6473597d706e	1891	#define BP_SPI_RSER_TCF_RE (31U) //!< Bit position for SPI_RSER_TCF_RE.
bogdanm	82:6473597d706e	1892	#define BM_SPI_RSER_TCF_RE (0x80000000U) //!< Bit mask for SPI_RSER_TCF_RE.
bogdanm	82:6473597d706e	1893	#define BS_SPI_RSER_TCF_RE (1U) //!< Bit field size in bits for SPI_RSER_TCF_RE.
bogdanm	82:6473597d706e	1894
bogdanm	82:6473597d706e	1895	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1896	//! @brief Read current value of the SPI_RSER_TCF_RE field.
bogdanm	82:6473597d706e	1897	#define BR_SPI_RSER_TCF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE))
bogdanm	82:6473597d706e	1898	#endif
bogdanm	82:6473597d706e	1899
bogdanm	82:6473597d706e	1900	//! @brief Format value for bitfield SPI_RSER_TCF_RE.
bogdanm	82:6473597d706e	1901	#define BF_SPI_RSER_TCF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TCF_RE), uint32_t) & BM_SPI_RSER_TCF_RE)
bogdanm	82:6473597d706e	1902
bogdanm	82:6473597d706e	1903	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1904	//! @brief Set the TCF_RE field to a new value.
bogdanm	82:6473597d706e	1905	#define BW_SPI_RSER_TCF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE) = (v))
bogdanm	82:6473597d706e	1906	#endif
bogdanm	82:6473597d706e	1907	//@}
bogdanm	82:6473597d706e	1908
bogdanm	82:6473597d706e	1909	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1910	// HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
bogdanm	82:6473597d706e	1911	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1912
bogdanm	82:6473597d706e	1913	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1914	/*!
bogdanm	82:6473597d706e	1915	* @brief HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
bogdanm	82:6473597d706e	1916	*
bogdanm	82:6473597d706e	1917	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1918	*
bogdanm	82:6473597d706e	1919	* Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
bogdanm	82:6473597d706e	1920	* transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
bogdanm	82:6473597d706e	1921	* 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
bogdanm	82:6473597d706e	1922	* can be used as data, supporting up to 32-bit frame operation. A read access
bogdanm	82:6473597d706e	1923	* of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
bogdanm	82:6473597d706e	1924	* writing to this register does not update the FIFO. Therefore, any reads performed
bogdanm	82:6473597d706e	1925	* while the module is disabled return the last PUSHR write performed while the
bogdanm	82:6473597d706e	1926	* module was still enabled.
bogdanm	82:6473597d706e	1927	*/
bogdanm	82:6473597d706e	1928	typedef union _hw_spi_pushr
bogdanm	82:6473597d706e	1929	{
bogdanm	82:6473597d706e	1930	uint32_t U;
bogdanm	82:6473597d706e	1931	struct _hw_spi_pushr_bitfields
bogdanm	82:6473597d706e	1932	{
bogdanm	82:6473597d706e	1933	uint32_t TXDATA : 16; //!< [15:0] Transmit Data
bogdanm	82:6473597d706e	1934	uint32_t PCS : 6; //!< [21:16]
bogdanm	82:6473597d706e	1935	uint32_t RESERVED0 : 4; //!< [25:22]
bogdanm	82:6473597d706e	1936	uint32_t CTCNT : 1; //!< [26] Clear Transfer Counter
bogdanm	82:6473597d706e	1937	uint32_t EOQ : 1; //!< [27] End Of Queue
bogdanm	82:6473597d706e	1938	uint32_t CTAS : 3; //!< [30:28] Clock and Transfer Attributes Select
bogdanm	82:6473597d706e	1939	uint32_t CONT : 1; //!< [31] Continuous Peripheral Chip Select Enable
bogdanm	82:6473597d706e	1940	} B;
bogdanm	82:6473597d706e	1941	} hw_spi_pushr_t;
bogdanm	82:6473597d706e	1942	#endif
bogdanm	82:6473597d706e	1943
bogdanm	82:6473597d706e	1944	/*!
bogdanm	82:6473597d706e	1945	* @name Constants and macros for entire SPI_PUSHR register
bogdanm	82:6473597d706e	1946	*/
bogdanm	82:6473597d706e	1947	//@{
bogdanm	82:6473597d706e	1948	#define HW_SPI_PUSHR_ADDR(x) (REGS_SPI_BASE(x) + 0x34U)
bogdanm	82:6473597d706e	1949
bogdanm	82:6473597d706e	1950	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1951	#define HW_SPI_PUSHR(x) ((__IO hw_spi_pushr_t ) HW_SPI_PUSHR_ADDR(x))
bogdanm	82:6473597d706e	1952	#define HW_SPI_PUSHR_RD(x) (HW_SPI_PUSHR(x).U)
bogdanm	82:6473597d706e	1953	#define HW_SPI_PUSHR_WR(x, v) (HW_SPI_PUSHR(x).U = (v))
bogdanm	82:6473597d706e	1954	#define HW_SPI_PUSHR_SET(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) \| (v)))
bogdanm	82:6473597d706e	1955	#define HW_SPI_PUSHR_CLR(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1956	#define HW_SPI_PUSHR_TOG(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1957	#endif
bogdanm	82:6473597d706e	1958	//@}
bogdanm	82:6473597d706e	1959
bogdanm	82:6473597d706e	1960	/*
bogdanm	82:6473597d706e	1961	* Constants & macros for individual SPI_PUSHR bitfields
bogdanm	82:6473597d706e	1962	*/
bogdanm	82:6473597d706e	1963
bogdanm	82:6473597d706e	1964	/*!
bogdanm	82:6473597d706e	1965	* @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
bogdanm	82:6473597d706e	1966	*
bogdanm	82:6473597d706e	1967	* Holds SPI data to be transferred according to the associated SPI command.
bogdanm	82:6473597d706e	1968	*/
bogdanm	82:6473597d706e	1969	//@{
bogdanm	82:6473597d706e	1970	#define BP_SPI_PUSHR_TXDATA (0U) //!< Bit position for SPI_PUSHR_TXDATA.
bogdanm	82:6473597d706e	1971	#define BM_SPI_PUSHR_TXDATA (0x0000FFFFU) //!< Bit mask for SPI_PUSHR_TXDATA.
bogdanm	82:6473597d706e	1972	#define BS_SPI_PUSHR_TXDATA (16U) //!< Bit field size in bits for SPI_PUSHR_TXDATA.
bogdanm	82:6473597d706e	1973
bogdanm	82:6473597d706e	1974	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1975	//! @brief Read current value of the SPI_PUSHR_TXDATA field.
bogdanm	82:6473597d706e	1976	#define BR_SPI_PUSHR_TXDATA(x) (HW_SPI_PUSHR(x).B.TXDATA)
bogdanm	82:6473597d706e	1977	#endif
bogdanm	82:6473597d706e	1978
bogdanm	82:6473597d706e	1979	//! @brief Format value for bitfield SPI_PUSHR_TXDATA.
bogdanm	82:6473597d706e	1980	#define BF_SPI_PUSHR_TXDATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_TXDATA), uint32_t) & BM_SPI_PUSHR_TXDATA)
bogdanm	82:6473597d706e	1981
bogdanm	82:6473597d706e	1982	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1983	//! @brief Set the TXDATA field to a new value.
bogdanm	82:6473597d706e	1984	#define BW_SPI_PUSHR_TXDATA(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_TXDATA) \| BF_SPI_PUSHR_TXDATA(v)))
bogdanm	82:6473597d706e	1985	#endif
bogdanm	82:6473597d706e	1986	//@}
bogdanm	82:6473597d706e	1987
bogdanm	82:6473597d706e	1988	/*!
bogdanm	82:6473597d706e	1989	* @name Register SPI_PUSHR, field PCS[21:16] (RW)
bogdanm	82:6473597d706e	1990	*
bogdanm	82:6473597d706e	1991	* Select which PCS signals are to be asserted for the transfer. Refer to the
bogdanm	82:6473597d706e	1992	* chip configuration details for the number of PCS signals used in this MCU.
bogdanm	82:6473597d706e	1993	*
bogdanm	82:6473597d706e	1994	* Values:
bogdanm	82:6473597d706e	1995	* - 0 - Negate the PCS[x] signal.
bogdanm	82:6473597d706e	1996	* - 1 - Assert the PCS[x] signal.
bogdanm	82:6473597d706e	1997	*/
bogdanm	82:6473597d706e	1998	//@{
bogdanm	82:6473597d706e	1999	#define BP_SPI_PUSHR_PCS (16U) //!< Bit position for SPI_PUSHR_PCS.
bogdanm	82:6473597d706e	2000	#define BM_SPI_PUSHR_PCS (0x003F0000U) //!< Bit mask for SPI_PUSHR_PCS.
bogdanm	82:6473597d706e	2001	#define BS_SPI_PUSHR_PCS (6U) //!< Bit field size in bits for SPI_PUSHR_PCS.
bogdanm	82:6473597d706e	2002
bogdanm	82:6473597d706e	2003	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2004	//! @brief Read current value of the SPI_PUSHR_PCS field.
bogdanm	82:6473597d706e	2005	#define BR_SPI_PUSHR_PCS(x) (HW_SPI_PUSHR(x).B.PCS)
bogdanm	82:6473597d706e	2006	#endif
bogdanm	82:6473597d706e	2007
bogdanm	82:6473597d706e	2008	//! @brief Format value for bitfield SPI_PUSHR_PCS.
bogdanm	82:6473597d706e	2009	#define BF_SPI_PUSHR_PCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_PCS), uint32_t) & BM_SPI_PUSHR_PCS)
bogdanm	82:6473597d706e	2010
bogdanm	82:6473597d706e	2011	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2012	//! @brief Set the PCS field to a new value.
bogdanm	82:6473597d706e	2013	#define BW_SPI_PUSHR_PCS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_PCS) \| BF_SPI_PUSHR_PCS(v)))
bogdanm	82:6473597d706e	2014	#endif
bogdanm	82:6473597d706e	2015	//@}
bogdanm	82:6473597d706e	2016
bogdanm	82:6473597d706e	2017	/*!
bogdanm	82:6473597d706e	2018	* @name Register SPI_PUSHR, field CTCNT[26] (RW)
bogdanm	82:6473597d706e	2019	*
bogdanm	82:6473597d706e	2020	* Clears the TCNT field in the TCR register. The TCNT field is cleared before
bogdanm	82:6473597d706e	2021	* the module starts transmitting the current SPI frame.
bogdanm	82:6473597d706e	2022	*
bogdanm	82:6473597d706e	2023	* Values:
bogdanm	82:6473597d706e	2024	* - 0 - Do not clear the TCR[TCNT] field.
bogdanm	82:6473597d706e	2025	* - 1 - Clear the TCR[TCNT] field.
bogdanm	82:6473597d706e	2026	*/
bogdanm	82:6473597d706e	2027	//@{
bogdanm	82:6473597d706e	2028	#define BP_SPI_PUSHR_CTCNT (26U) //!< Bit position for SPI_PUSHR_CTCNT.
bogdanm	82:6473597d706e	2029	#define BM_SPI_PUSHR_CTCNT (0x04000000U) //!< Bit mask for SPI_PUSHR_CTCNT.
bogdanm	82:6473597d706e	2030	#define BS_SPI_PUSHR_CTCNT (1U) //!< Bit field size in bits for SPI_PUSHR_CTCNT.
bogdanm	82:6473597d706e	2031
bogdanm	82:6473597d706e	2032	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2033	//! @brief Read current value of the SPI_PUSHR_CTCNT field.
bogdanm	82:6473597d706e	2034	#define BR_SPI_PUSHR_CTCNT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT))
bogdanm	82:6473597d706e	2035	#endif
bogdanm	82:6473597d706e	2036
bogdanm	82:6473597d706e	2037	//! @brief Format value for bitfield SPI_PUSHR_CTCNT.
bogdanm	82:6473597d706e	2038	#define BF_SPI_PUSHR_CTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CTCNT), uint32_t) & BM_SPI_PUSHR_CTCNT)
bogdanm	82:6473597d706e	2039
bogdanm	82:6473597d706e	2040	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2041	//! @brief Set the CTCNT field to a new value.
bogdanm	82:6473597d706e	2042	#define BW_SPI_PUSHR_CTCNT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT) = (v))
bogdanm	82:6473597d706e	2043	#endif
bogdanm	82:6473597d706e	2044	//@}
bogdanm	82:6473597d706e	2045
bogdanm	82:6473597d706e	2046	/*!
bogdanm	82:6473597d706e	2047	* @name Register SPI_PUSHR, field EOQ[27] (RW)
bogdanm	82:6473597d706e	2048	*
bogdanm	82:6473597d706e	2049	* Host software uses this bit to signal to the module that the current SPI
bogdanm	82:6473597d706e	2050	* transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
bogdanm	82:6473597d706e	2051	* SR is set.
bogdanm	82:6473597d706e	2052	*
bogdanm	82:6473597d706e	2053	* Values:
bogdanm	82:6473597d706e	2054	* - 0 - The SPI data is not the last data to transfer.
bogdanm	82:6473597d706e	2055	* - 1 - The SPI data is the last data to transfer.
bogdanm	82:6473597d706e	2056	*/
bogdanm	82:6473597d706e	2057	//@{
bogdanm	82:6473597d706e	2058	#define BP_SPI_PUSHR_EOQ (27U) //!< Bit position for SPI_PUSHR_EOQ.
bogdanm	82:6473597d706e	2059	#define BM_SPI_PUSHR_EOQ (0x08000000U) //!< Bit mask for SPI_PUSHR_EOQ.
bogdanm	82:6473597d706e	2060	#define BS_SPI_PUSHR_EOQ (1U) //!< Bit field size in bits for SPI_PUSHR_EOQ.
bogdanm	82:6473597d706e	2061
bogdanm	82:6473597d706e	2062	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2063	//! @brief Read current value of the SPI_PUSHR_EOQ field.
bogdanm	82:6473597d706e	2064	#define BR_SPI_PUSHR_EOQ(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ))
bogdanm	82:6473597d706e	2065	#endif
bogdanm	82:6473597d706e	2066
bogdanm	82:6473597d706e	2067	//! @brief Format value for bitfield SPI_PUSHR_EOQ.
bogdanm	82:6473597d706e	2068	#define BF_SPI_PUSHR_EOQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_EOQ), uint32_t) & BM_SPI_PUSHR_EOQ)
bogdanm	82:6473597d706e	2069
bogdanm	82:6473597d706e	2070	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2071	//! @brief Set the EOQ field to a new value.
bogdanm	82:6473597d706e	2072	#define BW_SPI_PUSHR_EOQ(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ) = (v))
bogdanm	82:6473597d706e	2073	#endif
bogdanm	82:6473597d706e	2074	//@}
bogdanm	82:6473597d706e	2075
bogdanm	82:6473597d706e	2076	/*!
bogdanm	82:6473597d706e	2077	* @name Register SPI_PUSHR, field CTAS[30:28] (RW)
bogdanm	82:6473597d706e	2078	*
bogdanm	82:6473597d706e	2079	* Selects which CTAR to use in master mode to specify the transfer attributes
bogdanm	82:6473597d706e	2080	* for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
bogdanm	82:6473597d706e	2081	* configuration details to determine how many CTARs this device has. You should
bogdanm	82:6473597d706e	2082	* not program a value in this field for a register that is not present.
bogdanm	82:6473597d706e	2083	*
bogdanm	82:6473597d706e	2084	* Values:
bogdanm	82:6473597d706e	2085	* - 000 - CTAR0
bogdanm	82:6473597d706e	2086	* - 001 - CTAR1
bogdanm	82:6473597d706e	2087	* - 010 - Reserved
bogdanm	82:6473597d706e	2088	* - 011 - Reserved
bogdanm	82:6473597d706e	2089	* - 100 - Reserved
bogdanm	82:6473597d706e	2090	* - 101 - Reserved
bogdanm	82:6473597d706e	2091	* - 110 - Reserved
bogdanm	82:6473597d706e	2092	* - 111 - Reserved
bogdanm	82:6473597d706e	2093	*/
bogdanm	82:6473597d706e	2094	//@{
bogdanm	82:6473597d706e	2095	#define BP_SPI_PUSHR_CTAS (28U) //!< Bit position for SPI_PUSHR_CTAS.
bogdanm	82:6473597d706e	2096	#define BM_SPI_PUSHR_CTAS (0x70000000U) //!< Bit mask for SPI_PUSHR_CTAS.
bogdanm	82:6473597d706e	2097	#define BS_SPI_PUSHR_CTAS (3U) //!< Bit field size in bits for SPI_PUSHR_CTAS.
bogdanm	82:6473597d706e	2098
bogdanm	82:6473597d706e	2099	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2100	//! @brief Read current value of the SPI_PUSHR_CTAS field.
bogdanm	82:6473597d706e	2101	#define BR_SPI_PUSHR_CTAS(x) (HW_SPI_PUSHR(x).B.CTAS)
bogdanm	82:6473597d706e	2102	#endif
bogdanm	82:6473597d706e	2103
bogdanm	82:6473597d706e	2104	//! @brief Format value for bitfield SPI_PUSHR_CTAS.
bogdanm	82:6473597d706e	2105	#define BF_SPI_PUSHR_CTAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CTAS), uint32_t) & BM_SPI_PUSHR_CTAS)
bogdanm	82:6473597d706e	2106
bogdanm	82:6473597d706e	2107	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2108	//! @brief Set the CTAS field to a new value.
bogdanm	82:6473597d706e	2109	#define BW_SPI_PUSHR_CTAS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_CTAS) \| BF_SPI_PUSHR_CTAS(v)))
bogdanm	82:6473597d706e	2110	#endif
bogdanm	82:6473597d706e	2111	//@}
bogdanm	82:6473597d706e	2112
bogdanm	82:6473597d706e	2113	/*!
bogdanm	82:6473597d706e	2114	* @name Register SPI_PUSHR, field CONT[31] (RW)
bogdanm	82:6473597d706e	2115	*
bogdanm	82:6473597d706e	2116	* Selects a continuous selection format. The bit is used in SPI Master mode.
bogdanm	82:6473597d706e	2117	* The bit enables the selected PCS signals to remain asserted between transfers.
bogdanm	82:6473597d706e	2118	*
bogdanm	82:6473597d706e	2119	* Values:
bogdanm	82:6473597d706e	2120	* - 0 - Return PCSn signals to their inactive state between transfers.
bogdanm	82:6473597d706e	2121	* - 1 - Keep PCSn signals asserted between transfers.
bogdanm	82:6473597d706e	2122	*/
bogdanm	82:6473597d706e	2123	//@{
bogdanm	82:6473597d706e	2124	#define BP_SPI_PUSHR_CONT (31U) //!< Bit position for SPI_PUSHR_CONT.
bogdanm	82:6473597d706e	2125	#define BM_SPI_PUSHR_CONT (0x80000000U) //!< Bit mask for SPI_PUSHR_CONT.
bogdanm	82:6473597d706e	2126	#define BS_SPI_PUSHR_CONT (1U) //!< Bit field size in bits for SPI_PUSHR_CONT.
bogdanm	82:6473597d706e	2127
bogdanm	82:6473597d706e	2128	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2129	//! @brief Read current value of the SPI_PUSHR_CONT field.
bogdanm	82:6473597d706e	2130	#define BR_SPI_PUSHR_CONT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT))
bogdanm	82:6473597d706e	2131	#endif
bogdanm	82:6473597d706e	2132
bogdanm	82:6473597d706e	2133	//! @brief Format value for bitfield SPI_PUSHR_CONT.
bogdanm	82:6473597d706e	2134	#define BF_SPI_PUSHR_CONT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CONT), uint32_t) & BM_SPI_PUSHR_CONT)
bogdanm	82:6473597d706e	2135
bogdanm	82:6473597d706e	2136	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2137	//! @brief Set the CONT field to a new value.
bogdanm	82:6473597d706e	2138	#define BW_SPI_PUSHR_CONT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT) = (v))
bogdanm	82:6473597d706e	2139	#endif
bogdanm	82:6473597d706e	2140	//@}
bogdanm	82:6473597d706e	2141	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2142	// HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
bogdanm	82:6473597d706e	2143	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2144
bogdanm	82:6473597d706e	2145	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2146	/*!
bogdanm	82:6473597d706e	2147	* @brief HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
bogdanm	82:6473597d706e	2148	*
bogdanm	82:6473597d706e	2149	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2150	*
bogdanm	82:6473597d706e	2151	* Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
bogdanm	82:6473597d706e	2152	* to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
bogdanm	82:6473597d706e	2153	* transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
bogdanm	82:6473597d706e	2154	* slave mode, all 32 register bits can be used as data, supporting up to 32-bit
bogdanm	82:6473597d706e	2155	* SPI Frame operation.
bogdanm	82:6473597d706e	2156	*/
bogdanm	82:6473597d706e	2157	typedef union _hw_spi_pushr_slave
bogdanm	82:6473597d706e	2158	{
bogdanm	82:6473597d706e	2159	uint32_t U;
bogdanm	82:6473597d706e	2160	struct _hw_spi_pushr_slave_bitfields
bogdanm	82:6473597d706e	2161	{
bogdanm	82:6473597d706e	2162	uint32_t TXDATA : 32; //!< [31:0] Transmit Data
bogdanm	82:6473597d706e	2163	} B;
bogdanm	82:6473597d706e	2164	} hw_spi_pushr_slave_t;
bogdanm	82:6473597d706e	2165	#endif
bogdanm	82:6473597d706e	2166
bogdanm	82:6473597d706e	2167	/*!
bogdanm	82:6473597d706e	2168	* @name Constants and macros for entire SPI_PUSHR_SLAVE register
bogdanm	82:6473597d706e	2169	*/
bogdanm	82:6473597d706e	2170	//@{
bogdanm	82:6473597d706e	2171	#define HW_SPI_PUSHR_SLAVE_ADDR(x) (REGS_SPI_BASE(x) + 0x34U)
bogdanm	82:6473597d706e	2172
bogdanm	82:6473597d706e	2173	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2174	#define HW_SPI_PUSHR_SLAVE(x) ((__IO hw_spi_pushr_slave_t ) HW_SPI_PUSHR_SLAVE_ADDR(x))
bogdanm	82:6473597d706e	2175	#define HW_SPI_PUSHR_SLAVE_RD(x) (HW_SPI_PUSHR_SLAVE(x).U)
bogdanm	82:6473597d706e	2176	#define HW_SPI_PUSHR_SLAVE_WR(x, v) (HW_SPI_PUSHR_SLAVE(x).U = (v))
bogdanm	82:6473597d706e	2177	#define HW_SPI_PUSHR_SLAVE_SET(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) \| (v)))
bogdanm	82:6473597d706e	2178	#define HW_SPI_PUSHR_SLAVE_CLR(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2179	#define HW_SPI_PUSHR_SLAVE_TOG(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2180	#endif
bogdanm	82:6473597d706e	2181	//@}
bogdanm	82:6473597d706e	2182
bogdanm	82:6473597d706e	2183	/*
bogdanm	82:6473597d706e	2184	* Constants & macros for individual SPI_PUSHR_SLAVE bitfields
bogdanm	82:6473597d706e	2185	*/
bogdanm	82:6473597d706e	2186
bogdanm	82:6473597d706e	2187	/*!
bogdanm	82:6473597d706e	2188	* @name Register SPI_PUSHR_SLAVE, field TXDATA[31:0] (RW)
bogdanm	82:6473597d706e	2189	*
bogdanm	82:6473597d706e	2190	* Holds SPI data to be transferred according to the associated SPI command.
bogdanm	82:6473597d706e	2191	*/
bogdanm	82:6473597d706e	2192	//@{
bogdanm	82:6473597d706e	2193	#define BP_SPI_PUSHR_SLAVE_TXDATA (0U) //!< Bit position for SPI_PUSHR_SLAVE_TXDATA.
bogdanm	82:6473597d706e	2194	#define BM_SPI_PUSHR_SLAVE_TXDATA (0xFFFFFFFFU) //!< Bit mask for SPI_PUSHR_SLAVE_TXDATA.
bogdanm	82:6473597d706e	2195	#define BS_SPI_PUSHR_SLAVE_TXDATA (32U) //!< Bit field size in bits for SPI_PUSHR_SLAVE_TXDATA.
bogdanm	82:6473597d706e	2196
bogdanm	82:6473597d706e	2197	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2198	//! @brief Read current value of the SPI_PUSHR_SLAVE_TXDATA field.
bogdanm	82:6473597d706e	2199	#define BR_SPI_PUSHR_SLAVE_TXDATA(x) (HW_SPI_PUSHR_SLAVE(x).U)
bogdanm	82:6473597d706e	2200	#endif
bogdanm	82:6473597d706e	2201
bogdanm	82:6473597d706e	2202	//! @brief Format value for bitfield SPI_PUSHR_SLAVE_TXDATA.
bogdanm	82:6473597d706e	2203	#define BF_SPI_PUSHR_SLAVE_TXDATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_SLAVE_TXDATA), uint32_t) & BM_SPI_PUSHR_SLAVE_TXDATA)
bogdanm	82:6473597d706e	2204
bogdanm	82:6473597d706e	2205	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2206	//! @brief Set the TXDATA field to a new value.
bogdanm	82:6473597d706e	2207	#define BW_SPI_PUSHR_SLAVE_TXDATA(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, v))
bogdanm	82:6473597d706e	2208	#endif
bogdanm	82:6473597d706e	2209	//@}
bogdanm	82:6473597d706e	2210
bogdanm	82:6473597d706e	2211	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2212	// HW_SPI_POPR - POP RX FIFO Register
bogdanm	82:6473597d706e	2213	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2214
bogdanm	82:6473597d706e	2215	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2216	/*!
bogdanm	82:6473597d706e	2217	* @brief HW_SPI_POPR - POP RX FIFO Register (RO)
bogdanm	82:6473597d706e	2218	*
bogdanm	82:6473597d706e	2219	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2220	*
bogdanm	82:6473597d706e	2221	* POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
bogdanm	82:6473597d706e	2222	* POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
bogdanm	82:6473597d706e	2223	* this register will generate a Transfer Error.
bogdanm	82:6473597d706e	2224	*/
bogdanm	82:6473597d706e	2225	typedef union _hw_spi_popr
bogdanm	82:6473597d706e	2226	{
bogdanm	82:6473597d706e	2227	uint32_t U;
bogdanm	82:6473597d706e	2228	struct _hw_spi_popr_bitfields
bogdanm	82:6473597d706e	2229	{
bogdanm	82:6473597d706e	2230	uint32_t RXDATA : 32; //!< [31:0] Received Data
bogdanm	82:6473597d706e	2231	} B;
bogdanm	82:6473597d706e	2232	} hw_spi_popr_t;
bogdanm	82:6473597d706e	2233	#endif
bogdanm	82:6473597d706e	2234
bogdanm	82:6473597d706e	2235	/*!
bogdanm	82:6473597d706e	2236	* @name Constants and macros for entire SPI_POPR register
bogdanm	82:6473597d706e	2237	*/
bogdanm	82:6473597d706e	2238	//@{
bogdanm	82:6473597d706e	2239	#define HW_SPI_POPR_ADDR(x) (REGS_SPI_BASE(x) + 0x38U)
bogdanm	82:6473597d706e	2240
bogdanm	82:6473597d706e	2241	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2242	#define HW_SPI_POPR(x) ((__I hw_spi_popr_t ) HW_SPI_POPR_ADDR(x))
bogdanm	82:6473597d706e	2243	#define HW_SPI_POPR_RD(x) (HW_SPI_POPR(x).U)
bogdanm	82:6473597d706e	2244	#endif
bogdanm	82:6473597d706e	2245	//@}
bogdanm	82:6473597d706e	2246
bogdanm	82:6473597d706e	2247	/*
bogdanm	82:6473597d706e	2248	* Constants & macros for individual SPI_POPR bitfields
bogdanm	82:6473597d706e	2249	*/
bogdanm	82:6473597d706e	2250
bogdanm	82:6473597d706e	2251	/*!
bogdanm	82:6473597d706e	2252	* @name Register SPI_POPR, field RXDATA[31:0] (RO)
bogdanm	82:6473597d706e	2253	*
bogdanm	82:6473597d706e	2254	* Contains the SPI data from the RX FIFO entry to which the Pop Next Data
bogdanm	82:6473597d706e	2255	* Pointer points.
bogdanm	82:6473597d706e	2256	*/
bogdanm	82:6473597d706e	2257	//@{
bogdanm	82:6473597d706e	2258	#define BP_SPI_POPR_RXDATA (0U) //!< Bit position for SPI_POPR_RXDATA.
bogdanm	82:6473597d706e	2259	#define BM_SPI_POPR_RXDATA (0xFFFFFFFFU) //!< Bit mask for SPI_POPR_RXDATA.
bogdanm	82:6473597d706e	2260	#define BS_SPI_POPR_RXDATA (32U) //!< Bit field size in bits for SPI_POPR_RXDATA.
bogdanm	82:6473597d706e	2261
bogdanm	82:6473597d706e	2262	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2263	//! @brief Read current value of the SPI_POPR_RXDATA field.
bogdanm	82:6473597d706e	2264	#define BR_SPI_POPR_RXDATA(x) (HW_SPI_POPR(x).U)
bogdanm	82:6473597d706e	2265	#endif
bogdanm	82:6473597d706e	2266	//@}
bogdanm	82:6473597d706e	2267
bogdanm	82:6473597d706e	2268	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2269	// HW_SPI_TXFRn - Transmit FIFO Registers
bogdanm	82:6473597d706e	2270	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2271
bogdanm	82:6473597d706e	2272	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2273	/*!
bogdanm	82:6473597d706e	2274	* @brief HW_SPI_TXFRn - Transmit FIFO Registers (RO)
bogdanm	82:6473597d706e	2275	*
bogdanm	82:6473597d706e	2276	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2277	*
bogdanm	82:6473597d706e	2278	* TXFRn registers provide visibility into the TX FIFO for debugging purposes.
bogdanm	82:6473597d706e	2279	* Each register is an entry in the TX FIFO. The registers are read-only and
bogdanm	82:6473597d706e	2280	* cannot be modified. Reading the TXFRx registers does not alter the state of the TX
bogdanm	82:6473597d706e	2281	* FIFO.
bogdanm	82:6473597d706e	2282	*/
bogdanm	82:6473597d706e	2283	typedef union _hw_spi_txfrn
bogdanm	82:6473597d706e	2284	{
bogdanm	82:6473597d706e	2285	uint32_t U;
bogdanm	82:6473597d706e	2286	struct _hw_spi_txfrn_bitfields
bogdanm	82:6473597d706e	2287	{
bogdanm	82:6473597d706e	2288	uint32_t TXDATA : 16; //!< [15:0] Transmit Data
bogdanm	82:6473597d706e	2289	uint32_t TXCMD_TXDATA : 16; //!< [31:16] Transmit Command or Transmit
bogdanm	82:6473597d706e	2290	//! Data
bogdanm	82:6473597d706e	2291	} B;
bogdanm	82:6473597d706e	2292	} hw_spi_txfrn_t;
bogdanm	82:6473597d706e	2293	#endif
bogdanm	82:6473597d706e	2294
bogdanm	82:6473597d706e	2295	/*!
bogdanm	82:6473597d706e	2296	* @name Constants and macros for entire SPI_TXFRn register
bogdanm	82:6473597d706e	2297	*/
bogdanm	82:6473597d706e	2298	//@{
bogdanm	82:6473597d706e	2299	#define HW_SPI_TXFRn_COUNT (4U)
bogdanm	82:6473597d706e	2300
bogdanm	82:6473597d706e	2301	#define HW_SPI_TXFRn_ADDR(x, n) (REGS_SPI_BASE(x) + 0x3CU + (0x4U * n))
bogdanm	82:6473597d706e	2302
bogdanm	82:6473597d706e	2303	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2304	#define HW_SPI_TXFRn(x, n) ((__I hw_spi_txfrn_t ) HW_SPI_TXFRn_ADDR(x, n))
bogdanm	82:6473597d706e	2305	#define HW_SPI_TXFRn_RD(x, n) (HW_SPI_TXFRn(x, n).U)
bogdanm	82:6473597d706e	2306	#endif
bogdanm	82:6473597d706e	2307	//@}
bogdanm	82:6473597d706e	2308
bogdanm	82:6473597d706e	2309	/*
bogdanm	82:6473597d706e	2310	* Constants & macros for individual SPI_TXFRn bitfields
bogdanm	82:6473597d706e	2311	*/
bogdanm	82:6473597d706e	2312
bogdanm	82:6473597d706e	2313	/*!
bogdanm	82:6473597d706e	2314	* @name Register SPI_TXFRn, field TXDATA[15:0] (RO)
bogdanm	82:6473597d706e	2315	*
bogdanm	82:6473597d706e	2316	* Contains the SPI data to be shifted out.
bogdanm	82:6473597d706e	2317	*/
bogdanm	82:6473597d706e	2318	//@{
bogdanm	82:6473597d706e	2319	#define BP_SPI_TXFRn_TXDATA (0U) //!< Bit position for SPI_TXFRn_TXDATA.
bogdanm	82:6473597d706e	2320	#define BM_SPI_TXFRn_TXDATA (0x0000FFFFU) //!< Bit mask for SPI_TXFRn_TXDATA.
bogdanm	82:6473597d706e	2321	#define BS_SPI_TXFRn_TXDATA (16U) //!< Bit field size in bits for SPI_TXFRn_TXDATA.
bogdanm	82:6473597d706e	2322
bogdanm	82:6473597d706e	2323	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2324	//! @brief Read current value of the SPI_TXFRn_TXDATA field.
bogdanm	82:6473597d706e	2325	#define BR_SPI_TXFRn_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXDATA)
bogdanm	82:6473597d706e	2326	#endif
bogdanm	82:6473597d706e	2327	//@}
bogdanm	82:6473597d706e	2328
bogdanm	82:6473597d706e	2329	/*!
bogdanm	82:6473597d706e	2330	* @name Register SPI_TXFRn, field TXCMD_TXDATA[31:16] (RO)
bogdanm	82:6473597d706e	2331	*
bogdanm	82:6473597d706e	2332	* In Master mode the TXCMD field contains the command that sets the transfer
bogdanm	82:6473597d706e	2333	* attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
bogdanm	82:6473597d706e	2334	* the SPI data to be shifted out.
bogdanm	82:6473597d706e	2335	*/
bogdanm	82:6473597d706e	2336	//@{
bogdanm	82:6473597d706e	2337	#define BP_SPI_TXFRn_TXCMD_TXDATA (16U) //!< Bit position for SPI_TXFRn_TXCMD_TXDATA.
bogdanm	82:6473597d706e	2338	#define BM_SPI_TXFRn_TXCMD_TXDATA (0xFFFF0000U) //!< Bit mask for SPI_TXFRn_TXCMD_TXDATA.
bogdanm	82:6473597d706e	2339	#define BS_SPI_TXFRn_TXCMD_TXDATA (16U) //!< Bit field size in bits for SPI_TXFRn_TXCMD_TXDATA.
bogdanm	82:6473597d706e	2340
bogdanm	82:6473597d706e	2341	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2342	//! @brief Read current value of the SPI_TXFRn_TXCMD_TXDATA field.
bogdanm	82:6473597d706e	2343	#define BR_SPI_TXFRn_TXCMD_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXCMD_TXDATA)
bogdanm	82:6473597d706e	2344	#endif
bogdanm	82:6473597d706e	2345	//@}
bogdanm	82:6473597d706e	2346
bogdanm	82:6473597d706e	2347	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2348	// HW_SPI_RXFRn - Receive FIFO Registers
bogdanm	82:6473597d706e	2349	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2350
bogdanm	82:6473597d706e	2351	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2352	/*!
bogdanm	82:6473597d706e	2353	* @brief HW_SPI_RXFRn - Receive FIFO Registers (RO)
bogdanm	82:6473597d706e	2354	*
bogdanm	82:6473597d706e	2355	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2356	*
bogdanm	82:6473597d706e	2357	* RXFRn provide visibility into the RX FIFO for debugging purposes. Each
bogdanm	82:6473597d706e	2358	* register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
bogdanm	82:6473597d706e	2359	* RXFRx registers does not alter the state of the RX FIFO.
bogdanm	82:6473597d706e	2360	*/
bogdanm	82:6473597d706e	2361	typedef union _hw_spi_rxfrn
bogdanm	82:6473597d706e	2362	{
bogdanm	82:6473597d706e	2363	uint32_t U;
bogdanm	82:6473597d706e	2364	struct _hw_spi_rxfrn_bitfields
bogdanm	82:6473597d706e	2365	{
bogdanm	82:6473597d706e	2366	uint32_t RXDATA : 32; //!< [31:0] Receive Data
bogdanm	82:6473597d706e	2367	} B;
bogdanm	82:6473597d706e	2368	} hw_spi_rxfrn_t;
bogdanm	82:6473597d706e	2369	#endif
bogdanm	82:6473597d706e	2370
bogdanm	82:6473597d706e	2371	/*!
bogdanm	82:6473597d706e	2372	* @name Constants and macros for entire SPI_RXFRn register
bogdanm	82:6473597d706e	2373	*/
bogdanm	82:6473597d706e	2374	//@{
bogdanm	82:6473597d706e	2375	#define HW_SPI_RXFRn_COUNT (4U)
bogdanm	82:6473597d706e	2376
bogdanm	82:6473597d706e	2377	#define HW_SPI_RXFRn_ADDR(x, n) (REGS_SPI_BASE(x) + 0x7CU + (0x4U * n))
bogdanm	82:6473597d706e	2378
bogdanm	82:6473597d706e	2379	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2380	#define HW_SPI_RXFRn(x, n) ((__I hw_spi_rxfrn_t ) HW_SPI_RXFRn_ADDR(x, n))
bogdanm	82:6473597d706e	2381	#define HW_SPI_RXFRn_RD(x, n) (HW_SPI_RXFRn(x, n).U)
bogdanm	82:6473597d706e	2382	#endif
bogdanm	82:6473597d706e	2383	//@}
bogdanm	82:6473597d706e	2384
bogdanm	82:6473597d706e	2385	/*
bogdanm	82:6473597d706e	2386	* Constants & macros for individual SPI_RXFRn bitfields
bogdanm	82:6473597d706e	2387	*/
bogdanm	82:6473597d706e	2388
bogdanm	82:6473597d706e	2389	/*!
bogdanm	82:6473597d706e	2390	* @name Register SPI_RXFRn, field RXDATA[31:0] (RO)
bogdanm	82:6473597d706e	2391	*
bogdanm	82:6473597d706e	2392	* Contains the received SPI data.
bogdanm	82:6473597d706e	2393	*/
bogdanm	82:6473597d706e	2394	//@{
bogdanm	82:6473597d706e	2395	#define BP_SPI_RXFRn_RXDATA (0U) //!< Bit position for SPI_RXFRn_RXDATA.
bogdanm	82:6473597d706e	2396	#define BM_SPI_RXFRn_RXDATA (0xFFFFFFFFU) //!< Bit mask for SPI_RXFRn_RXDATA.
bogdanm	82:6473597d706e	2397	#define BS_SPI_RXFRn_RXDATA (32U) //!< Bit field size in bits for SPI_RXFRn_RXDATA.
bogdanm	82:6473597d706e	2398
bogdanm	82:6473597d706e	2399	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2400	//! @brief Read current value of the SPI_RXFRn_RXDATA field.
bogdanm	82:6473597d706e	2401	#define BR_SPI_RXFRn_RXDATA(x, n) (HW_SPI_RXFRn(x, n).U)
bogdanm	82:6473597d706e	2402	#endif
bogdanm	82:6473597d706e	2403	//@}
bogdanm	82:6473597d706e	2404
bogdanm	82:6473597d706e	2405	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2406	// hw_spi_t - module struct
bogdanm	82:6473597d706e	2407	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2408	/*!
bogdanm	82:6473597d706e	2409	* @brief All SPI module registers.
bogdanm	82:6473597d706e	2410	*/
bogdanm	82:6473597d706e	2411	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2412	#pragma pack(1)
bogdanm	82:6473597d706e	2413	typedef struct _hw_spi
bogdanm	82:6473597d706e	2414	{
bogdanm	82:6473597d706e	2415	__IO hw_spi_mcr_t MCR; //!< [0x0] Module Configuration Register
bogdanm	82:6473597d706e	2416	uint8_t _reserved0[4];
bogdanm	82:6473597d706e	2417	__IO hw_spi_tcr_t TCR; //!< [0x8] Transfer Count Register
bogdanm	82:6473597d706e	2418	union {
bogdanm	82:6473597d706e	2419	__IO hw_spi_ctarn_t CTARn[2]; //!< [0xC] Clock and Transfer Attributes Register (In Master Mode)
bogdanm	82:6473597d706e	2420	__IO hw_spi_ctarn_slave_t CTARn_SLAVE[1]; //!< [0xC] Clock and Transfer Attributes Register (In Slave Mode)
bogdanm	82:6473597d706e	2421	};
bogdanm	82:6473597d706e	2422	uint8_t _reserved1[24];
bogdanm	82:6473597d706e	2423	__IO hw_spi_sr_t SR; //!< [0x2C] Status Register
bogdanm	82:6473597d706e	2424	__IO hw_spi_rser_t RSER; //!< [0x30] DMA/Interrupt Request Select and Enable Register
bogdanm	82:6473597d706e	2425	union {
bogdanm	82:6473597d706e	2426	__IO hw_spi_pushr_t PUSHR; //!< [0x34] PUSH TX FIFO Register In Master Mode
bogdanm	82:6473597d706e	2427	__IO hw_spi_pushr_slave_t PUSHR_SLAVE; //!< [0x34] PUSH TX FIFO Register In Slave Mode
bogdanm	82:6473597d706e	2428	};
bogdanm	82:6473597d706e	2429	__I hw_spi_popr_t POPR; //!< [0x38] POP RX FIFO Register
bogdanm	82:6473597d706e	2430	__I hw_spi_txfrn_t TXFRn[4]; //!< [0x3C] Transmit FIFO Registers
bogdanm	82:6473597d706e	2431	uint8_t _reserved2[48];
bogdanm	82:6473597d706e	2432	__I hw_spi_rxfrn_t RXFRn[4]; //!< [0x7C] Receive FIFO Registers
bogdanm	82:6473597d706e	2433	} hw_spi_t;
bogdanm	82:6473597d706e	2434	#pragma pack()
bogdanm	82:6473597d706e	2435
bogdanm	82:6473597d706e	2436	//! @brief Macro to access all SPI registers.
bogdanm	82:6473597d706e	2437	//! @param x SPI instance number.
bogdanm	82:6473597d706e	2438	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	2439	//! use the '&' operator, like <code>&HW_SPI(0)</code>.
bogdanm	82:6473597d706e	2440	#define HW_SPI(x) ((hw_spi_t ) REGS_SPI_BASE(x))
bogdanm	82:6473597d706e	2441	#endif
bogdanm	82:6473597d706e	2442
bogdanm	82:6473597d706e	2443	#endif // __HW_SPI_REGISTERS_H__
bogdanm	82:6473597d706e	2444	// v22/130726/0.9
bogdanm	82:6473597d706e	2445	// EOF

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Type:	Library
Created:	25 Jun 2015
Imports:	24
Forks:	0
Commits:	103
Dependents:	1
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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_spi.h@89:552587b429a1, 2014-09-12 (annotated)

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