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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_smc.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:
bogdanm
Date:
Fri Sep 12 16:41:52 2014 +0100
Revision:
89:552587b429a1
Parent:
TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_smc.h@82:6473597d706e 
Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_SMC_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_SMC_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 SMC
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * System Mode Controller
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_SMC_PMPROT - Power Mode Protection register
bogdanm 82:6473597d706e 33 * - HW_SMC_PMCTRL - Power Mode Control register
bogdanm 82:6473597d706e 34 * - HW_SMC_VLLSCTRL - VLLS Control register
bogdanm 82:6473597d706e 35 * - HW_SMC_PMSTAT - Power Mode Status register
bogdanm 82:6473597d706e 36 *
bogdanm 82:6473597d706e 37 * - hw_smc_t - Struct containing all module registers.
bogdanm 82:6473597d706e 38 */
bogdanm 82:6473597d706e 39
bogdanm 82:6473597d706e 40 //! @name Module base addresses
bogdanm 82:6473597d706e 41 //@{
bogdanm 82:6473597d706e 42 #ifndef REGS_SMC_BASE
bogdanm 82:6473597d706e 43 #define HW_SMC_INSTANCE_COUNT (1U) //!< Number of instances of the SMC module.
bogdanm 82:6473597d706e 44 #define REGS_SMC_BASE (0x4007E000U) //!< Base address for SMC.
bogdanm 82:6473597d706e 45 #endif
bogdanm 82:6473597d706e 46 //@}
bogdanm 82:6473597d706e 47
bogdanm 82:6473597d706e 48 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 49 // HW_SMC_PMPROT - Power Mode Protection register
bogdanm 82:6473597d706e 50 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 51
bogdanm 82:6473597d706e 52 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 53 /*!
bogdanm 82:6473597d706e 54 * @brief HW_SMC_PMPROT - Power Mode Protection register (RW)
bogdanm 82:6473597d706e 55 *
bogdanm 82:6473597d706e 56 * Reset value: 0x00U
bogdanm 82:6473597d706e 57 *
bogdanm 82:6473597d706e 58 * This register provides protection for entry into any low-power run or stop
bogdanm 82:6473597d706e 59 * mode. The enabling of the low-power run or stop mode occurs by configuring the
bogdanm 82:6473597d706e 60 * Power Mode Control register (PMCTRL). The PMPROT register can be written only
bogdanm 82:6473597d706e 61 * once after any system reset. If the MCU is configured for a disallowed or
bogdanm 82:6473597d706e 62 * reserved power mode, the MCU remains in its current power mode. For example, if the
bogdanm 82:6473597d706e 63 * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
bogdanm 82:6473597d706e 64 * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
bogdanm 82:6473597d706e 65 * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
bogdanm 82:6473597d706e 66 * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
bogdanm 82:6473597d706e 67 * that do not trigger Chip Reset not VLLS. See the Reset section details for more
bogdanm 82:6473597d706e 68 * information.
bogdanm 82:6473597d706e 69 */
bogdanm 82:6473597d706e 70 typedef union _hw_smc_pmprot
bogdanm 82:6473597d706e 71 {
bogdanm 82:6473597d706e 72 uint8_t U;
bogdanm 82:6473597d706e 73 struct _hw_smc_pmprot_bitfields
bogdanm 82:6473597d706e 74 {
bogdanm 82:6473597d706e 75 uint8_t RESERVED0 : 1; //!< [0]
bogdanm 82:6473597d706e 76 uint8_t AVLLS : 1; //!< [1] Allow Very-Low-Leakage Stop Mode
bogdanm 82:6473597d706e 77 uint8_t RESERVED1 : 1; //!< [2]
bogdanm 82:6473597d706e 78 uint8_t ALLS : 1; //!< [3] Allow Low-Leakage Stop Mode
bogdanm 82:6473597d706e 79 uint8_t RESERVED2 : 1; //!< [4]
bogdanm 82:6473597d706e 80 uint8_t AVLP : 1; //!< [5] Allow Very-Low-Power Modes
bogdanm 82:6473597d706e 81 uint8_t RESERVED3 : 2; //!< [7:6]
bogdanm 82:6473597d706e 82 } B;
bogdanm 82:6473597d706e 83 } hw_smc_pmprot_t;
bogdanm 82:6473597d706e 84 #endif
bogdanm 82:6473597d706e 85
bogdanm 82:6473597d706e 86 /*!
bogdanm 82:6473597d706e 87 * @name Constants and macros for entire SMC_PMPROT register
bogdanm 82:6473597d706e 88 */
bogdanm 82:6473597d706e 89 //@{
bogdanm 82:6473597d706e 90 #define HW_SMC_PMPROT_ADDR (REGS_SMC_BASE + 0x0U)
bogdanm 82:6473597d706e 91
bogdanm 82:6473597d706e 92 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 93 #define HW_SMC_PMPROT (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR)
bogdanm 82:6473597d706e 94 #define HW_SMC_PMPROT_RD() (HW_SMC_PMPROT.U)
bogdanm 82:6473597d706e 95 #define HW_SMC_PMPROT_WR(v) (HW_SMC_PMPROT.U = (v))
bogdanm 82:6473597d706e 96 #define HW_SMC_PMPROT_SET(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() | (v)))
bogdanm 82:6473597d706e 97 #define HW_SMC_PMPROT_CLR(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() & ~(v)))
bogdanm 82:6473597d706e 98 #define HW_SMC_PMPROT_TOG(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() ^ (v)))
bogdanm 82:6473597d706e 99 #endif
bogdanm 82:6473597d706e 100 //@}
bogdanm 82:6473597d706e 101
bogdanm 82:6473597d706e 102 /*
bogdanm 82:6473597d706e 103 * Constants & macros for individual SMC_PMPROT bitfields
bogdanm 82:6473597d706e 104 */
bogdanm 82:6473597d706e 105
bogdanm 82:6473597d706e 106 /*!
bogdanm 82:6473597d706e 107 * @name Register SMC_PMPROT, field AVLLS[1] (RW)
bogdanm 82:6473597d706e 108 *
bogdanm 82:6473597d706e 109 * Provided the appropriate control bits are set up in PMCTRL, this write once
bogdanm 82:6473597d706e 110 * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
bogdanm 82:6473597d706e 111 *
bogdanm 82:6473597d706e 112 * Values:
bogdanm 82:6473597d706e 113 * - 0 - Any VLLSx mode is not allowed
bogdanm 82:6473597d706e 114 * - 1 - Any VLLSx mode is allowed
bogdanm 82:6473597d706e 115 */
bogdanm 82:6473597d706e 116 //@{
bogdanm 82:6473597d706e 117 #define BP_SMC_PMPROT_AVLLS (1U) //!< Bit position for SMC_PMPROT_AVLLS.
bogdanm 82:6473597d706e 118 #define BM_SMC_PMPROT_AVLLS (0x02U) //!< Bit mask for SMC_PMPROT_AVLLS.
bogdanm 82:6473597d706e 119 #define BS_SMC_PMPROT_AVLLS (1U) //!< Bit field size in bits for SMC_PMPROT_AVLLS.
bogdanm 82:6473597d706e 120
bogdanm 82:6473597d706e 121 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 122 //! @brief Read current value of the SMC_PMPROT_AVLLS field.
bogdanm 82:6473597d706e 123 #define BR_SMC_PMPROT_AVLLS (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLLS))
bogdanm 82:6473597d706e 124 #endif
bogdanm 82:6473597d706e 125
bogdanm 82:6473597d706e 126 //! @brief Format value for bitfield SMC_PMPROT_AVLLS.
bogdanm 82:6473597d706e 127 #define BF_SMC_PMPROT_AVLLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_AVLLS), uint8_t) & BM_SMC_PMPROT_AVLLS)
bogdanm 82:6473597d706e 128
bogdanm 82:6473597d706e 129 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 130 //! @brief Set the AVLLS field to a new value.
bogdanm 82:6473597d706e 131 #define BW_SMC_PMPROT_AVLLS(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLLS) = (v))
bogdanm 82:6473597d706e 132 #endif
bogdanm 82:6473597d706e 133 //@}
bogdanm 82:6473597d706e 134
bogdanm 82:6473597d706e 135 /*!
bogdanm 82:6473597d706e 136 * @name Register SMC_PMPROT, field ALLS[3] (RW)
bogdanm 82:6473597d706e 137 *
bogdanm 82:6473597d706e 138 * Provided the appropriate control bits are set up in PMCTRL, this write-once
bogdanm 82:6473597d706e 139 * field allows the MCU to enter any low-leakage stop mode (LLS).
bogdanm 82:6473597d706e 140 *
bogdanm 82:6473597d706e 141 * Values:
bogdanm 82:6473597d706e 142 * - 0 - LLS is not allowed
bogdanm 82:6473597d706e 143 * - 1 - LLS is allowed
bogdanm 82:6473597d706e 144 */
bogdanm 82:6473597d706e 145 //@{
bogdanm 82:6473597d706e 146 #define BP_SMC_PMPROT_ALLS (3U) //!< Bit position for SMC_PMPROT_ALLS.
bogdanm 82:6473597d706e 147 #define BM_SMC_PMPROT_ALLS (0x08U) //!< Bit mask for SMC_PMPROT_ALLS.
bogdanm 82:6473597d706e 148 #define BS_SMC_PMPROT_ALLS (1U) //!< Bit field size in bits for SMC_PMPROT_ALLS.
bogdanm 82:6473597d706e 149
bogdanm 82:6473597d706e 150 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 151 //! @brief Read current value of the SMC_PMPROT_ALLS field.
bogdanm 82:6473597d706e 152 #define BR_SMC_PMPROT_ALLS (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_ALLS))
bogdanm 82:6473597d706e 153 #endif
bogdanm 82:6473597d706e 154
bogdanm 82:6473597d706e 155 //! @brief Format value for bitfield SMC_PMPROT_ALLS.
bogdanm 82:6473597d706e 156 #define BF_SMC_PMPROT_ALLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_ALLS), uint8_t) & BM_SMC_PMPROT_ALLS)
bogdanm 82:6473597d706e 157
bogdanm 82:6473597d706e 158 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 159 //! @brief Set the ALLS field to a new value.
bogdanm 82:6473597d706e 160 #define BW_SMC_PMPROT_ALLS(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_ALLS) = (v))
bogdanm 82:6473597d706e 161 #endif
bogdanm 82:6473597d706e 162 //@}
bogdanm 82:6473597d706e 163
bogdanm 82:6473597d706e 164 /*!
bogdanm 82:6473597d706e 165 * @name Register SMC_PMPROT, field AVLP[5] (RW)
bogdanm 82:6473597d706e 166 *
bogdanm 82:6473597d706e 167 * Provided the appropriate control bits are set up in PMCTRL, this write-once
bogdanm 82:6473597d706e 168 * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
bogdanm 82:6473597d706e 169 *
bogdanm 82:6473597d706e 170 * Values:
bogdanm 82:6473597d706e 171 * - 0 - VLPR, VLPW, and VLPS are not allowed.
bogdanm 82:6473597d706e 172 * - 1 - VLPR, VLPW, and VLPS are allowed.
bogdanm 82:6473597d706e 173 */
bogdanm 82:6473597d706e 174 //@{
bogdanm 82:6473597d706e 175 #define BP_SMC_PMPROT_AVLP (5U) //!< Bit position for SMC_PMPROT_AVLP.
bogdanm 82:6473597d706e 176 #define BM_SMC_PMPROT_AVLP (0x20U) //!< Bit mask for SMC_PMPROT_AVLP.
bogdanm 82:6473597d706e 177 #define BS_SMC_PMPROT_AVLP (1U) //!< Bit field size in bits for SMC_PMPROT_AVLP.
bogdanm 82:6473597d706e 178
bogdanm 82:6473597d706e 179 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 180 //! @brief Read current value of the SMC_PMPROT_AVLP field.
bogdanm 82:6473597d706e 181 #define BR_SMC_PMPROT_AVLP (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLP))
bogdanm 82:6473597d706e 182 #endif
bogdanm 82:6473597d706e 183
bogdanm 82:6473597d706e 184 //! @brief Format value for bitfield SMC_PMPROT_AVLP.
bogdanm 82:6473597d706e 185 #define BF_SMC_PMPROT_AVLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_AVLP), uint8_t) & BM_SMC_PMPROT_AVLP)
bogdanm 82:6473597d706e 186
bogdanm 82:6473597d706e 187 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 188 //! @brief Set the AVLP field to a new value.
bogdanm 82:6473597d706e 189 #define BW_SMC_PMPROT_AVLP(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLP) = (v))
bogdanm 82:6473597d706e 190 #endif
bogdanm 82:6473597d706e 191 //@}
bogdanm 82:6473597d706e 192
bogdanm 82:6473597d706e 193 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 194 // HW_SMC_PMCTRL - Power Mode Control register
bogdanm 82:6473597d706e 195 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 196
bogdanm 82:6473597d706e 197 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 198 /*!
bogdanm 82:6473597d706e 199 * @brief HW_SMC_PMCTRL - Power Mode Control register (RW)
bogdanm 82:6473597d706e 200 *
bogdanm 82:6473597d706e 201 * Reset value: 0x00U
bogdanm 82:6473597d706e 202 *
bogdanm 82:6473597d706e 203 * The PMCTRL register controls entry into low-power Run and Stop modes,
bogdanm 82:6473597d706e 204 * provided that the selected power mode is allowed via an appropriate setting of the
bogdanm 82:6473597d706e 205 * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
bogdanm 82:6473597d706e 206 * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
bogdanm 82:6473597d706e 207 * that do not trigger Chip POR not VLLS. See the Reset section details for more
bogdanm 82:6473597d706e 208 * information.
bogdanm 82:6473597d706e 209 */
bogdanm 82:6473597d706e 210 typedef union _hw_smc_pmctrl
bogdanm 82:6473597d706e 211 {
bogdanm 82:6473597d706e 212 uint8_t U;
bogdanm 82:6473597d706e 213 struct _hw_smc_pmctrl_bitfields
bogdanm 82:6473597d706e 214 {
bogdanm 82:6473597d706e 215 uint8_t STOPM : 3; //!< [2:0] Stop Mode Control
bogdanm 82:6473597d706e 216 uint8_t STOPA : 1; //!< [3] Stop Aborted
bogdanm 82:6473597d706e 217 uint8_t RESERVED0 : 1; //!< [4]
bogdanm 82:6473597d706e 218 uint8_t RUNM : 2; //!< [6:5] Run Mode Control
bogdanm 82:6473597d706e 219 uint8_t LPWUI : 1; //!< [7] Low-Power Wake Up On Interrupt
bogdanm 82:6473597d706e 220 } B;
bogdanm 82:6473597d706e 221 } hw_smc_pmctrl_t;
bogdanm 82:6473597d706e 222 #endif
bogdanm 82:6473597d706e 223
bogdanm 82:6473597d706e 224 /*!
bogdanm 82:6473597d706e 225 * @name Constants and macros for entire SMC_PMCTRL register
bogdanm 82:6473597d706e 226 */
bogdanm 82:6473597d706e 227 //@{
bogdanm 82:6473597d706e 228 #define HW_SMC_PMCTRL_ADDR (REGS_SMC_BASE + 0x1U)
bogdanm 82:6473597d706e 229
bogdanm 82:6473597d706e 230 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 231 #define HW_SMC_PMCTRL (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR)
bogdanm 82:6473597d706e 232 #define HW_SMC_PMCTRL_RD() (HW_SMC_PMCTRL.U)
bogdanm 82:6473597d706e 233 #define HW_SMC_PMCTRL_WR(v) (HW_SMC_PMCTRL.U = (v))
bogdanm 82:6473597d706e 234 #define HW_SMC_PMCTRL_SET(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() | (v)))
bogdanm 82:6473597d706e 235 #define HW_SMC_PMCTRL_CLR(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() & ~(v)))
bogdanm 82:6473597d706e 236 #define HW_SMC_PMCTRL_TOG(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() ^ (v)))
bogdanm 82:6473597d706e 237 #endif
bogdanm 82:6473597d706e 238 //@}
bogdanm 82:6473597d706e 239
bogdanm 82:6473597d706e 240 /*
bogdanm 82:6473597d706e 241 * Constants & macros for individual SMC_PMCTRL bitfields
bogdanm 82:6473597d706e 242 */
bogdanm 82:6473597d706e 243
bogdanm 82:6473597d706e 244 /*!
bogdanm 82:6473597d706e 245 * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
bogdanm 82:6473597d706e 246 *
bogdanm 82:6473597d706e 247 * When written, controls entry into the selected stop mode when Sleep-Now or
bogdanm 82:6473597d706e 248 * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
bogdanm 82:6473597d706e 249 * blocked if the protection level has not been enabled using the PMPROT register.
bogdanm 82:6473597d706e 250 * After any system reset, this field is cleared by hardware on any successful write
bogdanm 82:6473597d706e 251 * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
bogdanm 82:6473597d706e 252 * register is used to further select the particular VLLS submode which will be
bogdanm 82:6473597d706e 253 * entered.
bogdanm 82:6473597d706e 254 *
bogdanm 82:6473597d706e 255 * Values:
bogdanm 82:6473597d706e 256 * - 000 - Normal Stop (STOP)
bogdanm 82:6473597d706e 257 * - 001 - Reserved
bogdanm 82:6473597d706e 258 * - 010 - Very-Low-Power Stop (VLPS)
bogdanm 82:6473597d706e 259 * - 011 - Low-Leakage Stop (LLS)
bogdanm 82:6473597d706e 260 * - 100 - Very-Low-Leakage Stop (VLLSx)
bogdanm 82:6473597d706e 261 * - 101 - Reserved
bogdanm 82:6473597d706e 262 * - 110 - Reseved
bogdanm 82:6473597d706e 263 * - 111 - Reserved
bogdanm 82:6473597d706e 264 */
bogdanm 82:6473597d706e 265 //@{
bogdanm 82:6473597d706e 266 #define BP_SMC_PMCTRL_STOPM (0U) //!< Bit position for SMC_PMCTRL_STOPM.
bogdanm 82:6473597d706e 267 #define BM_SMC_PMCTRL_STOPM (0x07U) //!< Bit mask for SMC_PMCTRL_STOPM.
bogdanm 82:6473597d706e 268 #define BS_SMC_PMCTRL_STOPM (3U) //!< Bit field size in bits for SMC_PMCTRL_STOPM.
bogdanm 82:6473597d706e 269
bogdanm 82:6473597d706e 270 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 271 //! @brief Read current value of the SMC_PMCTRL_STOPM field.
bogdanm 82:6473597d706e 272 #define BR_SMC_PMCTRL_STOPM (HW_SMC_PMCTRL.B.STOPM)
bogdanm 82:6473597d706e 273 #endif
bogdanm 82:6473597d706e 274
bogdanm 82:6473597d706e 275 //! @brief Format value for bitfield SMC_PMCTRL_STOPM.
bogdanm 82:6473597d706e 276 #define BF_SMC_PMCTRL_STOPM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_STOPM), uint8_t) & BM_SMC_PMCTRL_STOPM)
bogdanm 82:6473597d706e 277
bogdanm 82:6473597d706e 278 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 279 //! @brief Set the STOPM field to a new value.
bogdanm 82:6473597d706e 280 #define BW_SMC_PMCTRL_STOPM(v) (HW_SMC_PMCTRL_WR((HW_SMC_PMCTRL_RD() & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v)))
bogdanm 82:6473597d706e 281 #endif
bogdanm 82:6473597d706e 282 //@}
bogdanm 82:6473597d706e 283
bogdanm 82:6473597d706e 284 /*!
bogdanm 82:6473597d706e 285 * @name Register SMC_PMCTRL, field STOPA[3] (RO)
bogdanm 82:6473597d706e 286 *
bogdanm 82:6473597d706e 287 * When set, this read-only status bit indicates an interrupt or reset occured
bogdanm 82:6473597d706e 288 * during the previous stop mode entry sequence, preventing the system from
bogdanm 82:6473597d706e 289 * entering that mode. This field is cleared by hardware at the beginning of any stop
bogdanm 82:6473597d706e 290 * mode entry sequence and is set if the sequence was aborted.
bogdanm 82:6473597d706e 291 *
bogdanm 82:6473597d706e 292 * Values:
bogdanm 82:6473597d706e 293 * - 0 - The previous stop mode entry was successsful.
bogdanm 82:6473597d706e 294 * - 1 - The previous stop mode entry was aborted.
bogdanm 82:6473597d706e 295 */
bogdanm 82:6473597d706e 296 //@{
bogdanm 82:6473597d706e 297 #define BP_SMC_PMCTRL_STOPA (3U) //!< Bit position for SMC_PMCTRL_STOPA.
bogdanm 82:6473597d706e 298 #define BM_SMC_PMCTRL_STOPA (0x08U) //!< Bit mask for SMC_PMCTRL_STOPA.
bogdanm 82:6473597d706e 299 #define BS_SMC_PMCTRL_STOPA (1U) //!< Bit field size in bits for SMC_PMCTRL_STOPA.
bogdanm 82:6473597d706e 300
bogdanm 82:6473597d706e 301 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 302 //! @brief Read current value of the SMC_PMCTRL_STOPA field.
bogdanm 82:6473597d706e 303 #define BR_SMC_PMCTRL_STOPA (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_STOPA))
bogdanm 82:6473597d706e 304 #endif
bogdanm 82:6473597d706e 305 //@}
bogdanm 82:6473597d706e 306
bogdanm 82:6473597d706e 307 /*!
bogdanm 82:6473597d706e 308 * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
bogdanm 82:6473597d706e 309 *
bogdanm 82:6473597d706e 310 * When written, causes entry into the selected run mode. Writes to this field
bogdanm 82:6473597d706e 311 * are blocked if the protection level has not been enabled using the PMPROT
bogdanm 82:6473597d706e 312 * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
bogdanm 82:6473597d706e 313 * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
bogdanm 82:6473597d706e 314 *
bogdanm 82:6473597d706e 315 * Values:
bogdanm 82:6473597d706e 316 * - 00 - Normal Run mode (RUN)
bogdanm 82:6473597d706e 317 * - 01 - Reserved
bogdanm 82:6473597d706e 318 * - 10 - Very-Low-Power Run mode (VLPR)
bogdanm 82:6473597d706e 319 * - 11 - Reserved
bogdanm 82:6473597d706e 320 */
bogdanm 82:6473597d706e 321 //@{
bogdanm 82:6473597d706e 322 #define BP_SMC_PMCTRL_RUNM (5U) //!< Bit position for SMC_PMCTRL_RUNM.
bogdanm 82:6473597d706e 323 #define BM_SMC_PMCTRL_RUNM (0x60U) //!< Bit mask for SMC_PMCTRL_RUNM.
bogdanm 82:6473597d706e 324 #define BS_SMC_PMCTRL_RUNM (2U) //!< Bit field size in bits for SMC_PMCTRL_RUNM.
bogdanm 82:6473597d706e 325
bogdanm 82:6473597d706e 326 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 327 //! @brief Read current value of the SMC_PMCTRL_RUNM field.
bogdanm 82:6473597d706e 328 #define BR_SMC_PMCTRL_RUNM (HW_SMC_PMCTRL.B.RUNM)
bogdanm 82:6473597d706e 329 #endif
bogdanm 82:6473597d706e 330
bogdanm 82:6473597d706e 331 //! @brief Format value for bitfield SMC_PMCTRL_RUNM.
bogdanm 82:6473597d706e 332 #define BF_SMC_PMCTRL_RUNM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_RUNM), uint8_t) & BM_SMC_PMCTRL_RUNM)
bogdanm 82:6473597d706e 333
bogdanm 82:6473597d706e 334 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 335 //! @brief Set the RUNM field to a new value.
bogdanm 82:6473597d706e 336 #define BW_SMC_PMCTRL_RUNM(v) (HW_SMC_PMCTRL_WR((HW_SMC_PMCTRL_RD() & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v)))
bogdanm 82:6473597d706e 337 #endif
bogdanm 82:6473597d706e 338 //@}
bogdanm 82:6473597d706e 339
bogdanm 82:6473597d706e 340 /*!
bogdanm 82:6473597d706e 341 * @name Register SMC_PMCTRL, field LPWUI[7] (RW)
bogdanm 82:6473597d706e 342 *
bogdanm 82:6473597d706e 343 * Causes the SMC to exit to normal RUN mode when any active MCU interrupt
bogdanm 82:6473597d706e 344 * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
bogdanm 82:6473597d706e 345 * from RUN mode, the SMC will always exit back to normal RUN mode regardless of
bogdanm 82:6473597d706e 346 * the LPWUI setting. LPWUI must be modified only while the system is in RUN
bogdanm 82:6473597d706e 347 * mode, that is, when PMSTAT=RUN.
bogdanm 82:6473597d706e 348 *
bogdanm 82:6473597d706e 349 * Values:
bogdanm 82:6473597d706e 350 * - 0 - The system remains in a VLP mode on an interrupt
bogdanm 82:6473597d706e 351 * - 1 - The system exits to Normal RUN mode on an interrupt
bogdanm 82:6473597d706e 352 */
bogdanm 82:6473597d706e 353 //@{
bogdanm 82:6473597d706e 354 #define BP_SMC_PMCTRL_LPWUI (7U) //!< Bit position for SMC_PMCTRL_LPWUI.
bogdanm 82:6473597d706e 355 #define BM_SMC_PMCTRL_LPWUI (0x80U) //!< Bit mask for SMC_PMCTRL_LPWUI.
bogdanm 82:6473597d706e 356 #define BS_SMC_PMCTRL_LPWUI (1U) //!< Bit field size in bits for SMC_PMCTRL_LPWUI.
bogdanm 82:6473597d706e 357
bogdanm 82:6473597d706e 358 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 359 //! @brief Read current value of the SMC_PMCTRL_LPWUI field.
bogdanm 82:6473597d706e 360 #define BR_SMC_PMCTRL_LPWUI (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_LPWUI))
bogdanm 82:6473597d706e 361 #endif
bogdanm 82:6473597d706e 362
bogdanm 82:6473597d706e 363 //! @brief Format value for bitfield SMC_PMCTRL_LPWUI.
bogdanm 82:6473597d706e 364 #define BF_SMC_PMCTRL_LPWUI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_LPWUI), uint8_t) & BM_SMC_PMCTRL_LPWUI)
bogdanm 82:6473597d706e 365
bogdanm 82:6473597d706e 366 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 367 //! @brief Set the LPWUI field to a new value.
bogdanm 82:6473597d706e 368 #define BW_SMC_PMCTRL_LPWUI(v) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_LPWUI) = (v))
bogdanm 82:6473597d706e 369 #endif
bogdanm 82:6473597d706e 370 //@}
bogdanm 82:6473597d706e 371
bogdanm 82:6473597d706e 372 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 373 // HW_SMC_VLLSCTRL - VLLS Control register
bogdanm 82:6473597d706e 374 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 375
bogdanm 82:6473597d706e 376 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 377 /*!
bogdanm 82:6473597d706e 378 * @brief HW_SMC_VLLSCTRL - VLLS Control register (RW)
bogdanm 82:6473597d706e 379 *
bogdanm 82:6473597d706e 380 * Reset value: 0x03U
bogdanm 82:6473597d706e 381 *
bogdanm 82:6473597d706e 382 * The VLLSCTRL register controls features related to VLLS modes. This register
bogdanm 82:6473597d706e 383 * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
bogdanm 82:6473597d706e 384 * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
bogdanm 82:6473597d706e 385 * the Reset section details for more information.
bogdanm 82:6473597d706e 386 */
bogdanm 82:6473597d706e 387 typedef union _hw_smc_vllsctrl
bogdanm 82:6473597d706e 388 {
bogdanm 82:6473597d706e 389 uint8_t U;
bogdanm 82:6473597d706e 390 struct _hw_smc_vllsctrl_bitfields
bogdanm 82:6473597d706e 391 {
bogdanm 82:6473597d706e 392 uint8_t VLLSM : 3; //!< [2:0] VLLS Mode Control
bogdanm 82:6473597d706e 393 uint8_t RESERVED0 : 2; //!< [4:3]
bogdanm 82:6473597d706e 394 uint8_t PORPO : 1; //!< [5] POR Power Option
bogdanm 82:6473597d706e 395 uint8_t RESERVED1 : 2; //!< [7:6]
bogdanm 82:6473597d706e 396 } B;
bogdanm 82:6473597d706e 397 } hw_smc_vllsctrl_t;
bogdanm 82:6473597d706e 398 #endif
bogdanm 82:6473597d706e 399
bogdanm 82:6473597d706e 400 /*!
bogdanm 82:6473597d706e 401 * @name Constants and macros for entire SMC_VLLSCTRL register
bogdanm 82:6473597d706e 402 */
bogdanm 82:6473597d706e 403 //@{
bogdanm 82:6473597d706e 404 #define HW_SMC_VLLSCTRL_ADDR (REGS_SMC_BASE + 0x2U)
bogdanm 82:6473597d706e 405
bogdanm 82:6473597d706e 406 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 407 #define HW_SMC_VLLSCTRL (*(__IO hw_smc_vllsctrl_t *) HW_SMC_VLLSCTRL_ADDR)
bogdanm 82:6473597d706e 408 #define HW_SMC_VLLSCTRL_RD() (HW_SMC_VLLSCTRL.U)
bogdanm 82:6473597d706e 409 #define HW_SMC_VLLSCTRL_WR(v) (HW_SMC_VLLSCTRL.U = (v))
bogdanm 82:6473597d706e 410 #define HW_SMC_VLLSCTRL_SET(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() | (v)))
bogdanm 82:6473597d706e 411 #define HW_SMC_VLLSCTRL_CLR(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() & ~(v)))
bogdanm 82:6473597d706e 412 #define HW_SMC_VLLSCTRL_TOG(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() ^ (v)))
bogdanm 82:6473597d706e 413 #endif
bogdanm 82:6473597d706e 414 //@}
bogdanm 82:6473597d706e 415
bogdanm 82:6473597d706e 416 /*
bogdanm 82:6473597d706e 417 * Constants & macros for individual SMC_VLLSCTRL bitfields
bogdanm 82:6473597d706e 418 */
bogdanm 82:6473597d706e 419
bogdanm 82:6473597d706e 420 /*!
bogdanm 82:6473597d706e 421 * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
bogdanm 82:6473597d706e 422 *
bogdanm 82:6473597d706e 423 * Controls which VLLS sub-mode to enter if STOPM=VLLS.
bogdanm 82:6473597d706e 424 *
bogdanm 82:6473597d706e 425 * Values:
bogdanm 82:6473597d706e 426 * - 000 - VLLS0
bogdanm 82:6473597d706e 427 * - 001 - VLLS1
bogdanm 82:6473597d706e 428 * - 010 - VLLS2
bogdanm 82:6473597d706e 429 * - 011 - VLLS3
bogdanm 82:6473597d706e 430 * - 100 - Reserved
bogdanm 82:6473597d706e 431 * - 101 - Reserved
bogdanm 82:6473597d706e 432 * - 110 - Reserved
bogdanm 82:6473597d706e 433 * - 111 - Reserved
bogdanm 82:6473597d706e 434 */
bogdanm 82:6473597d706e 435 //@{
bogdanm 82:6473597d706e 436 #define BP_SMC_VLLSCTRL_VLLSM (0U) //!< Bit position for SMC_VLLSCTRL_VLLSM.
bogdanm 82:6473597d706e 437 #define BM_SMC_VLLSCTRL_VLLSM (0x07U) //!< Bit mask for SMC_VLLSCTRL_VLLSM.
bogdanm 82:6473597d706e 438 #define BS_SMC_VLLSCTRL_VLLSM (3U) //!< Bit field size in bits for SMC_VLLSCTRL_VLLSM.
bogdanm 82:6473597d706e 439
bogdanm 82:6473597d706e 440 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 441 //! @brief Read current value of the SMC_VLLSCTRL_VLLSM field.
bogdanm 82:6473597d706e 442 #define BR_SMC_VLLSCTRL_VLLSM (HW_SMC_VLLSCTRL.B.VLLSM)
bogdanm 82:6473597d706e 443 #endif
bogdanm 82:6473597d706e 444
bogdanm 82:6473597d706e 445 //! @brief Format value for bitfield SMC_VLLSCTRL_VLLSM.
bogdanm 82:6473597d706e 446 #define BF_SMC_VLLSCTRL_VLLSM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_VLLSCTRL_VLLSM), uint8_t) & BM_SMC_VLLSCTRL_VLLSM)
bogdanm 82:6473597d706e 447
bogdanm 82:6473597d706e 448 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 449 //! @brief Set the VLLSM field to a new value.
bogdanm 82:6473597d706e 450 #define BW_SMC_VLLSCTRL_VLLSM(v) (HW_SMC_VLLSCTRL_WR((HW_SMC_VLLSCTRL_RD() & ~BM_SMC_VLLSCTRL_VLLSM) | BF_SMC_VLLSCTRL_VLLSM(v)))
bogdanm 82:6473597d706e 451 #endif
bogdanm 82:6473597d706e 452 //@}
bogdanm 82:6473597d706e 453
bogdanm 82:6473597d706e 454 /*!
bogdanm 82:6473597d706e 455 * @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
bogdanm 82:6473597d706e 456 *
bogdanm 82:6473597d706e 457 * Controls whether the POR detect circuit (for brown-out detection) is enabled
bogdanm 82:6473597d706e 458 * in VLLS0 mode.
bogdanm 82:6473597d706e 459 *
bogdanm 82:6473597d706e 460 * Values:
bogdanm 82:6473597d706e 461 * - 0 - POR detect circuit is enabled in VLLS0.
bogdanm 82:6473597d706e 462 * - 1 - POR detect circuit is disabled in VLLS0.
bogdanm 82:6473597d706e 463 */
bogdanm 82:6473597d706e 464 //@{
bogdanm 82:6473597d706e 465 #define BP_SMC_VLLSCTRL_PORPO (5U) //!< Bit position for SMC_VLLSCTRL_PORPO.
bogdanm 82:6473597d706e 466 #define BM_SMC_VLLSCTRL_PORPO (0x20U) //!< Bit mask for SMC_VLLSCTRL_PORPO.
bogdanm 82:6473597d706e 467 #define BS_SMC_VLLSCTRL_PORPO (1U) //!< Bit field size in bits for SMC_VLLSCTRL_PORPO.
bogdanm 82:6473597d706e 468
bogdanm 82:6473597d706e 469 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 470 //! @brief Read current value of the SMC_VLLSCTRL_PORPO field.
bogdanm 82:6473597d706e 471 #define BR_SMC_VLLSCTRL_PORPO (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR, BP_SMC_VLLSCTRL_PORPO))
bogdanm 82:6473597d706e 472 #endif
bogdanm 82:6473597d706e 473
bogdanm 82:6473597d706e 474 //! @brief Format value for bitfield SMC_VLLSCTRL_PORPO.
bogdanm 82:6473597d706e 475 #define BF_SMC_VLLSCTRL_PORPO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_VLLSCTRL_PORPO), uint8_t) & BM_SMC_VLLSCTRL_PORPO)
bogdanm 82:6473597d706e 476
bogdanm 82:6473597d706e 477 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 478 //! @brief Set the PORPO field to a new value.
bogdanm 82:6473597d706e 479 #define BW_SMC_VLLSCTRL_PORPO(v) (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR, BP_SMC_VLLSCTRL_PORPO) = (v))
bogdanm 82:6473597d706e 480 #endif
bogdanm 82:6473597d706e 481 //@}
bogdanm 82:6473597d706e 482
bogdanm 82:6473597d706e 483 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 484 // HW_SMC_PMSTAT - Power Mode Status register
bogdanm 82:6473597d706e 485 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 486
bogdanm 82:6473597d706e 487 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 488 /*!
bogdanm 82:6473597d706e 489 * @brief HW_SMC_PMSTAT - Power Mode Status register (RO)
bogdanm 82:6473597d706e 490 *
bogdanm 82:6473597d706e 491 * Reset value: 0x01U
bogdanm 82:6473597d706e 492 *
bogdanm 82:6473597d706e 493 * PMSTAT is a read-only, one-hot register which indicates the current power
bogdanm 82:6473597d706e 494 * mode of the system. This register is reset on Chip POR not VLLS and by reset
bogdanm 82:6473597d706e 495 * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
bogdanm 82:6473597d706e 496 * trigger Chip POR not VLLS. See the Reset section details for more information.
bogdanm 82:6473597d706e 497 */
bogdanm 82:6473597d706e 498 typedef union _hw_smc_pmstat
bogdanm 82:6473597d706e 499 {
bogdanm 82:6473597d706e 500 uint8_t U;
bogdanm 82:6473597d706e 501 struct _hw_smc_pmstat_bitfields
bogdanm 82:6473597d706e 502 {
bogdanm 82:6473597d706e 503 uint8_t PMSTAT : 7; //!< [6:0]
bogdanm 82:6473597d706e 504 uint8_t RESERVED0 : 1; //!< [7]
bogdanm 82:6473597d706e 505 } B;
bogdanm 82:6473597d706e 506 } hw_smc_pmstat_t;
bogdanm 82:6473597d706e 507 #endif
bogdanm 82:6473597d706e 508
bogdanm 82:6473597d706e 509 /*!
bogdanm 82:6473597d706e 510 * @name Constants and macros for entire SMC_PMSTAT register
bogdanm 82:6473597d706e 511 */
bogdanm 82:6473597d706e 512 //@{
bogdanm 82:6473597d706e 513 #define HW_SMC_PMSTAT_ADDR (REGS_SMC_BASE + 0x3U)
bogdanm 82:6473597d706e 514
bogdanm 82:6473597d706e 515 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 516 #define HW_SMC_PMSTAT (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR)
bogdanm 82:6473597d706e 517 #define HW_SMC_PMSTAT_RD() (HW_SMC_PMSTAT.U)
bogdanm 82:6473597d706e 518 #endif
bogdanm 82:6473597d706e 519 //@}
bogdanm 82:6473597d706e 520
bogdanm 82:6473597d706e 521 /*
bogdanm 82:6473597d706e 522 * Constants & macros for individual SMC_PMSTAT bitfields
bogdanm 82:6473597d706e 523 */
bogdanm 82:6473597d706e 524
bogdanm 82:6473597d706e 525 /*!
bogdanm 82:6473597d706e 526 * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
bogdanm 82:6473597d706e 527 *
bogdanm 82:6473597d706e 528 * When debug is enabled, the PMSTAT will not update to STOP or VLPS
bogdanm 82:6473597d706e 529 */
bogdanm 82:6473597d706e 530 //@{
bogdanm 82:6473597d706e 531 #define BP_SMC_PMSTAT_PMSTAT (0U) //!< Bit position for SMC_PMSTAT_PMSTAT.
bogdanm 82:6473597d706e 532 #define BM_SMC_PMSTAT_PMSTAT (0x7FU) //!< Bit mask for SMC_PMSTAT_PMSTAT.
bogdanm 82:6473597d706e 533 #define BS_SMC_PMSTAT_PMSTAT (7U) //!< Bit field size in bits for SMC_PMSTAT_PMSTAT.
bogdanm 82:6473597d706e 534
bogdanm 82:6473597d706e 535 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 536 //! @brief Read current value of the SMC_PMSTAT_PMSTAT field.
bogdanm 82:6473597d706e 537 #define BR_SMC_PMSTAT_PMSTAT (HW_SMC_PMSTAT.B.PMSTAT)
bogdanm 82:6473597d706e 538 #endif
bogdanm 82:6473597d706e 539 //@}
bogdanm 82:6473597d706e 540
bogdanm 82:6473597d706e 541 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 542 // hw_smc_t - module struct
bogdanm 82:6473597d706e 543 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 544 /*!
bogdanm 82:6473597d706e 545 * @brief All SMC module registers.
bogdanm 82:6473597d706e 546 */
bogdanm 82:6473597d706e 547 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 548 #pragma pack(1)
bogdanm 82:6473597d706e 549 typedef struct _hw_smc
bogdanm 82:6473597d706e 550 {
bogdanm 82:6473597d706e 551 __IO hw_smc_pmprot_t PMPROT; //!< [0x0] Power Mode Protection register
bogdanm 82:6473597d706e 552 __IO hw_smc_pmctrl_t PMCTRL; //!< [0x1] Power Mode Control register
bogdanm 82:6473597d706e 553 __IO hw_smc_vllsctrl_t VLLSCTRL; //!< [0x2] VLLS Control register
bogdanm 82:6473597d706e 554 __I hw_smc_pmstat_t PMSTAT; //!< [0x3] Power Mode Status register
bogdanm 82:6473597d706e 555 } hw_smc_t;
bogdanm 82:6473597d706e 556 #pragma pack()
bogdanm 82:6473597d706e 557
bogdanm 82:6473597d706e 558 //! @brief Macro to access all SMC registers.
bogdanm 82:6473597d706e 559 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 560 //! use the '&' operator, like <code>&HW_SMC</code>.
bogdanm 82:6473597d706e 561 #define HW_SMC (*(hw_smc_t *) REGS_SMC_BASE)
bogdanm 82:6473597d706e 562 #endif
bogdanm 82:6473597d706e 563
bogdanm 82:6473597d706e 564 #endif // __HW_SMC_REGISTERS_H__
bogdanm 82:6473597d706e 565 // v22/130726/0.9
bogdanm 82:6473597d706e 566 // EOF