mbed - mbed library

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mbed library

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_mpu.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_mpu.h@82:6473597d706e

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_MPU_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_MPU_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 MPU
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Memory protection unit
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_MPU_CESR - Control/Error Status Register
bogdanm	82:6473597d706e	33	* - HW_MPU_EARn - Error Address Register, slave port n
bogdanm	82:6473597d706e	34	* - HW_MPU_EDRn - Error Detail Register, slave port n
bogdanm	82:6473597d706e	35	* - HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0
bogdanm	82:6473597d706e	36	* - HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1
bogdanm	82:6473597d706e	37	* - HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2
bogdanm	82:6473597d706e	38	* - HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3
bogdanm	82:6473597d706e	39	* - HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n
bogdanm	82:6473597d706e	40	*
bogdanm	82:6473597d706e	41	* - hw_mpu_t - Struct containing all module registers.
bogdanm	82:6473597d706e	42	*/
bogdanm	82:6473597d706e	43
bogdanm	82:6473597d706e	44	//! @name Module base addresses
bogdanm	82:6473597d706e	45	//@{
bogdanm	82:6473597d706e	46	#ifndef REGS_MPU_BASE
bogdanm	82:6473597d706e	47	#define HW_MPU_INSTANCE_COUNT (1U) //!< Number of instances of the MPU module.
bogdanm	82:6473597d706e	48	#define REGS_MPU_BASE (0x4000D000U) //!< Base address for MPU.
bogdanm	82:6473597d706e	49	#endif
bogdanm	82:6473597d706e	50	//@}
bogdanm	82:6473597d706e	51
bogdanm	82:6473597d706e	52	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	53	// HW_MPU_CESR - Control/Error Status Register
bogdanm	82:6473597d706e	54	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	55
bogdanm	82:6473597d706e	56	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	57	/*!
bogdanm	82:6473597d706e	58	* @brief HW_MPU_CESR - Control/Error Status Register (RW)
bogdanm	82:6473597d706e	59	*
bogdanm	82:6473597d706e	60	* Reset value: 0x00815101U
bogdanm	82:6473597d706e	61	*/
bogdanm	82:6473597d706e	62	typedef union _hw_mpu_cesr
bogdanm	82:6473597d706e	63	{
bogdanm	82:6473597d706e	64	uint32_t U;
bogdanm	82:6473597d706e	65	struct _hw_mpu_cesr_bitfields
bogdanm	82:6473597d706e	66	{
bogdanm	82:6473597d706e	67	uint32_t VLD : 1; //!< [0] Valid
bogdanm	82:6473597d706e	68	uint32_t RESERVED0 : 7; //!< [7:1]
bogdanm	82:6473597d706e	69	uint32_t NRGD : 4; //!< [11:8] Number Of Region Descriptors
bogdanm	82:6473597d706e	70	uint32_t NSP : 4; //!< [15:12] Number Of Slave Ports
bogdanm	82:6473597d706e	71	uint32_t HRL : 4; //!< [19:16] Hardware Revision Level
bogdanm	82:6473597d706e	72	uint32_t RESERVED1 : 7; //!< [26:20]
bogdanm	82:6473597d706e	73	uint32_t SPERR : 5; //!< [31:27] Slave Port n Error
bogdanm	82:6473597d706e	74	} B;
bogdanm	82:6473597d706e	75	} hw_mpu_cesr_t;
bogdanm	82:6473597d706e	76	#endif
bogdanm	82:6473597d706e	77
bogdanm	82:6473597d706e	78	/*!
bogdanm	82:6473597d706e	79	* @name Constants and macros for entire MPU_CESR register
bogdanm	82:6473597d706e	80	*/
bogdanm	82:6473597d706e	81	//@{
bogdanm	82:6473597d706e	82	#define HW_MPU_CESR_ADDR (REGS_MPU_BASE + 0x0U)
bogdanm	82:6473597d706e	83
bogdanm	82:6473597d706e	84	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	85	#define HW_MPU_CESR ((__IO hw_mpu_cesr_t ) HW_MPU_CESR_ADDR)
bogdanm	82:6473597d706e	86	#define HW_MPU_CESR_RD() (HW_MPU_CESR.U)
bogdanm	82:6473597d706e	87	#define HW_MPU_CESR_WR(v) (HW_MPU_CESR.U = (v))
bogdanm	82:6473597d706e	88	#define HW_MPU_CESR_SET(v) (HW_MPU_CESR_WR(HW_MPU_CESR_RD() \| (v)))
bogdanm	82:6473597d706e	89	#define HW_MPU_CESR_CLR(v) (HW_MPU_CESR_WR(HW_MPU_CESR_RD() & ~(v)))
bogdanm	82:6473597d706e	90	#define HW_MPU_CESR_TOG(v) (HW_MPU_CESR_WR(HW_MPU_CESR_RD() ^ (v)))
bogdanm	82:6473597d706e	91	#endif
bogdanm	82:6473597d706e	92	//@}
bogdanm	82:6473597d706e	93
bogdanm	82:6473597d706e	94	/*
bogdanm	82:6473597d706e	95	* Constants & macros for individual MPU_CESR bitfields
bogdanm	82:6473597d706e	96	*/
bogdanm	82:6473597d706e	97
bogdanm	82:6473597d706e	98	/*!
bogdanm	82:6473597d706e	99	* @name Register MPU_CESR, field VLD[0] (RW)
bogdanm	82:6473597d706e	100	*
bogdanm	82:6473597d706e	101	* Global enable/disable for the MPU.
bogdanm	82:6473597d706e	102	*
bogdanm	82:6473597d706e	103	* Values:
bogdanm	82:6473597d706e	104	* - 0 - MPU is disabled. All accesses from all bus masters are allowed.
bogdanm	82:6473597d706e	105	* - 1 - MPU is enabled
bogdanm	82:6473597d706e	106	*/
bogdanm	82:6473597d706e	107	//@{
bogdanm	82:6473597d706e	108	#define BP_MPU_CESR_VLD (0U) //!< Bit position for MPU_CESR_VLD.
bogdanm	82:6473597d706e	109	#define BM_MPU_CESR_VLD (0x00000001U) //!< Bit mask for MPU_CESR_VLD.
bogdanm	82:6473597d706e	110	#define BS_MPU_CESR_VLD (1U) //!< Bit field size in bits for MPU_CESR_VLD.
bogdanm	82:6473597d706e	111
bogdanm	82:6473597d706e	112	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	113	//! @brief Read current value of the MPU_CESR_VLD field.
bogdanm	82:6473597d706e	114	#define BR_MPU_CESR_VLD (BITBAND_ACCESS32(HW_MPU_CESR_ADDR, BP_MPU_CESR_VLD))
bogdanm	82:6473597d706e	115	#endif
bogdanm	82:6473597d706e	116
bogdanm	82:6473597d706e	117	//! @brief Format value for bitfield MPU_CESR_VLD.
bogdanm	82:6473597d706e	118	#define BF_MPU_CESR_VLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_CESR_VLD), uint32_t) & BM_MPU_CESR_VLD)
bogdanm	82:6473597d706e	119
bogdanm	82:6473597d706e	120	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	121	//! @brief Set the VLD field to a new value.
bogdanm	82:6473597d706e	122	#define BW_MPU_CESR_VLD(v) (BITBAND_ACCESS32(HW_MPU_CESR_ADDR, BP_MPU_CESR_VLD) = (v))
bogdanm	82:6473597d706e	123	#endif
bogdanm	82:6473597d706e	124	//@}
bogdanm	82:6473597d706e	125
bogdanm	82:6473597d706e	126	/*!
bogdanm	82:6473597d706e	127	* @name Register MPU_CESR, field NRGD[11:8] (RO)
bogdanm	82:6473597d706e	128	*
bogdanm	82:6473597d706e	129	* Indicates the number of region descriptors implemented in the MPU.
bogdanm	82:6473597d706e	130	*
bogdanm	82:6473597d706e	131	* Values:
bogdanm	82:6473597d706e	132	* - 0000 - 8 region descriptors
bogdanm	82:6473597d706e	133	* - 0001 - 12 region descriptors
bogdanm	82:6473597d706e	134	* - 0010 - 16 region descriptors
bogdanm	82:6473597d706e	135	*/
bogdanm	82:6473597d706e	136	//@{
bogdanm	82:6473597d706e	137	#define BP_MPU_CESR_NRGD (8U) //!< Bit position for MPU_CESR_NRGD.
bogdanm	82:6473597d706e	138	#define BM_MPU_CESR_NRGD (0x00000F00U) //!< Bit mask for MPU_CESR_NRGD.
bogdanm	82:6473597d706e	139	#define BS_MPU_CESR_NRGD (4U) //!< Bit field size in bits for MPU_CESR_NRGD.
bogdanm	82:6473597d706e	140
bogdanm	82:6473597d706e	141	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	142	//! @brief Read current value of the MPU_CESR_NRGD field.
bogdanm	82:6473597d706e	143	#define BR_MPU_CESR_NRGD (HW_MPU_CESR.B.NRGD)
bogdanm	82:6473597d706e	144	#endif
bogdanm	82:6473597d706e	145	//@}
bogdanm	82:6473597d706e	146
bogdanm	82:6473597d706e	147	/*!
bogdanm	82:6473597d706e	148	* @name Register MPU_CESR, field NSP[15:12] (RO)
bogdanm	82:6473597d706e	149	*
bogdanm	82:6473597d706e	150	* Specifies the number of slave ports connected to the MPU.
bogdanm	82:6473597d706e	151	*/
bogdanm	82:6473597d706e	152	//@{
bogdanm	82:6473597d706e	153	#define BP_MPU_CESR_NSP (12U) //!< Bit position for MPU_CESR_NSP.
bogdanm	82:6473597d706e	154	#define BM_MPU_CESR_NSP (0x0000F000U) //!< Bit mask for MPU_CESR_NSP.
bogdanm	82:6473597d706e	155	#define BS_MPU_CESR_NSP (4U) //!< Bit field size in bits for MPU_CESR_NSP.
bogdanm	82:6473597d706e	156
bogdanm	82:6473597d706e	157	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	158	//! @brief Read current value of the MPU_CESR_NSP field.
bogdanm	82:6473597d706e	159	#define BR_MPU_CESR_NSP (HW_MPU_CESR.B.NSP)
bogdanm	82:6473597d706e	160	#endif
bogdanm	82:6473597d706e	161	//@}
bogdanm	82:6473597d706e	162
bogdanm	82:6473597d706e	163	/*!
bogdanm	82:6473597d706e	164	* @name Register MPU_CESR, field HRL[19:16] (RO)
bogdanm	82:6473597d706e	165	*
bogdanm	82:6473597d706e	166	* Specifies the MPU's hardware and definition revision level. It can be read by
bogdanm	82:6473597d706e	167	* software to determine the functional definition of the module.
bogdanm	82:6473597d706e	168	*/
bogdanm	82:6473597d706e	169	//@{
bogdanm	82:6473597d706e	170	#define BP_MPU_CESR_HRL (16U) //!< Bit position for MPU_CESR_HRL.
bogdanm	82:6473597d706e	171	#define BM_MPU_CESR_HRL (0x000F0000U) //!< Bit mask for MPU_CESR_HRL.
bogdanm	82:6473597d706e	172	#define BS_MPU_CESR_HRL (4U) //!< Bit field size in bits for MPU_CESR_HRL.
bogdanm	82:6473597d706e	173
bogdanm	82:6473597d706e	174	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	175	//! @brief Read current value of the MPU_CESR_HRL field.
bogdanm	82:6473597d706e	176	#define BR_MPU_CESR_HRL (HW_MPU_CESR.B.HRL)
bogdanm	82:6473597d706e	177	#endif
bogdanm	82:6473597d706e	178	//@}
bogdanm	82:6473597d706e	179
bogdanm	82:6473597d706e	180	/*!
bogdanm	82:6473597d706e	181	* @name Register MPU_CESR, field SPERR[31:27] (W1C)
bogdanm	82:6473597d706e	182	*
bogdanm	82:6473597d706e	183	* Indicates a captured error in EARn and EDRn. This bit is set when the
bogdanm	82:6473597d706e	184	* hardware detects an error and records the faulting address and attributes. It is
bogdanm	82:6473597d706e	185	* cleared by writing one to it. If another error is captured at the exact same cycle
bogdanm	82:6473597d706e	186	* as the write, the flag remains set. A find-first-one instruction or
bogdanm	82:6473597d706e	187	* equivalent can detect the presence of a captured error. The following shows the
bogdanm	82:6473597d706e	188	* correspondence between the bit number and slave port number: Bit 31 corresponds to
bogdanm	82:6473597d706e	189	* slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave
bogdanm	82:6473597d706e	190	* port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4.
bogdanm	82:6473597d706e	191	*
bogdanm	82:6473597d706e	192	* Values:
bogdanm	82:6473597d706e	193	* - 0 - No error has occurred for slave port n.
bogdanm	82:6473597d706e	194	* - 1 - An error has occurred for slave port n.
bogdanm	82:6473597d706e	195	*/
bogdanm	82:6473597d706e	196	//@{
bogdanm	82:6473597d706e	197	#define BP_MPU_CESR_SPERR (27U) //!< Bit position for MPU_CESR_SPERR.
bogdanm	82:6473597d706e	198	#define BM_MPU_CESR_SPERR (0xF8000000U) //!< Bit mask for MPU_CESR_SPERR.
bogdanm	82:6473597d706e	199	#define BS_MPU_CESR_SPERR (5U) //!< Bit field size in bits for MPU_CESR_SPERR.
bogdanm	82:6473597d706e	200
bogdanm	82:6473597d706e	201	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	202	//! @brief Read current value of the MPU_CESR_SPERR field.
bogdanm	82:6473597d706e	203	#define BR_MPU_CESR_SPERR (HW_MPU_CESR.B.SPERR)
bogdanm	82:6473597d706e	204	#endif
bogdanm	82:6473597d706e	205
bogdanm	82:6473597d706e	206	//! @brief Format value for bitfield MPU_CESR_SPERR.
bogdanm	82:6473597d706e	207	#define BF_MPU_CESR_SPERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_CESR_SPERR), uint32_t) & BM_MPU_CESR_SPERR)
bogdanm	82:6473597d706e	208
bogdanm	82:6473597d706e	209	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	210	//! @brief Set the SPERR field to a new value.
bogdanm	82:6473597d706e	211	#define BW_MPU_CESR_SPERR(v) (HW_MPU_CESR_WR((HW_MPU_CESR_RD() & ~BM_MPU_CESR_SPERR) \| BF_MPU_CESR_SPERR(v)))
bogdanm	82:6473597d706e	212	#endif
bogdanm	82:6473597d706e	213	//@}
bogdanm	82:6473597d706e	214
bogdanm	82:6473597d706e	215	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	216	// HW_MPU_EARn - Error Address Register, slave port n
bogdanm	82:6473597d706e	217	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	218
bogdanm	82:6473597d706e	219	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	220	/*!
bogdanm	82:6473597d706e	221	* @brief HW_MPU_EARn - Error Address Register, slave port n (RO)
bogdanm	82:6473597d706e	222	*
bogdanm	82:6473597d706e	223	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	224	*
bogdanm	82:6473597d706e	225	* When the MPU detects an access error on slave port n, the 32-bit reference
bogdanm	82:6473597d706e	226	* address is captured in this read-only register and the corresponding bit in
bogdanm	82:6473597d706e	227	* CESR[SPERR] set. Additional information about the faulting access is captured in
bogdanm	82:6473597d706e	228	* the corresponding EDRn at the same time. This register and the corresponding
bogdanm	82:6473597d706e	229	* EDRn contain the most recent access error; there are no hardware interlocks with
bogdanm	82:6473597d706e	230	* CESR[SPERR], as the error registers are always loaded upon the occurrence of
bogdanm	82:6473597d706e	231	* each protection violation.
bogdanm	82:6473597d706e	232	*/
bogdanm	82:6473597d706e	233	typedef union _hw_mpu_earn
bogdanm	82:6473597d706e	234	{
bogdanm	82:6473597d706e	235	uint32_t U;
bogdanm	82:6473597d706e	236	struct _hw_mpu_earn_bitfields
bogdanm	82:6473597d706e	237	{
bogdanm	82:6473597d706e	238	uint32_t EADDR : 32; //!< [31:0] Error Address
bogdanm	82:6473597d706e	239	} B;
bogdanm	82:6473597d706e	240	} hw_mpu_earn_t;
bogdanm	82:6473597d706e	241	#endif
bogdanm	82:6473597d706e	242
bogdanm	82:6473597d706e	243	/*!
bogdanm	82:6473597d706e	244	* @name Constants and macros for entire MPU_EARn register
bogdanm	82:6473597d706e	245	*/
bogdanm	82:6473597d706e	246	//@{
bogdanm	82:6473597d706e	247	#define HW_MPU_EARn_COUNT (5U)
bogdanm	82:6473597d706e	248
bogdanm	82:6473597d706e	249	#define HW_MPU_EARn_ADDR(n) (REGS_MPU_BASE + 0x10U + (0x8U * n))
bogdanm	82:6473597d706e	250
bogdanm	82:6473597d706e	251	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	252	#define HW_MPU_EARn(n) ((__I hw_mpu_earn_t ) HW_MPU_EARn_ADDR(n))
bogdanm	82:6473597d706e	253	#define HW_MPU_EARn_RD(n) (HW_MPU_EARn(n).U)
bogdanm	82:6473597d706e	254	#endif
bogdanm	82:6473597d706e	255	//@}
bogdanm	82:6473597d706e	256
bogdanm	82:6473597d706e	257	/*
bogdanm	82:6473597d706e	258	* Constants & macros for individual MPU_EARn bitfields
bogdanm	82:6473597d706e	259	*/
bogdanm	82:6473597d706e	260
bogdanm	82:6473597d706e	261	/*!
bogdanm	82:6473597d706e	262	* @name Register MPU_EARn, field EADDR[31:0] (RO)
bogdanm	82:6473597d706e	263	*
bogdanm	82:6473597d706e	264	* Indicates the reference address from slave port n that generated the access
bogdanm	82:6473597d706e	265	* error
bogdanm	82:6473597d706e	266	*/
bogdanm	82:6473597d706e	267	//@{
bogdanm	82:6473597d706e	268	#define BP_MPU_EARn_EADDR (0U) //!< Bit position for MPU_EARn_EADDR.
bogdanm	82:6473597d706e	269	#define BM_MPU_EARn_EADDR (0xFFFFFFFFU) //!< Bit mask for MPU_EARn_EADDR.
bogdanm	82:6473597d706e	270	#define BS_MPU_EARn_EADDR (32U) //!< Bit field size in bits for MPU_EARn_EADDR.
bogdanm	82:6473597d706e	271
bogdanm	82:6473597d706e	272	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	273	//! @brief Read current value of the MPU_EARn_EADDR field.
bogdanm	82:6473597d706e	274	#define BR_MPU_EARn_EADDR(n) (HW_MPU_EARn(n).U)
bogdanm	82:6473597d706e	275	#endif
bogdanm	82:6473597d706e	276	//@}
bogdanm	82:6473597d706e	277	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	278	// HW_MPU_EDRn - Error Detail Register, slave port n
bogdanm	82:6473597d706e	279	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	280
bogdanm	82:6473597d706e	281	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	282	/*!
bogdanm	82:6473597d706e	283	* @brief HW_MPU_EDRn - Error Detail Register, slave port n (RO)
bogdanm	82:6473597d706e	284	*
bogdanm	82:6473597d706e	285	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	286	*
bogdanm	82:6473597d706e	287	* When the MPU detects an access error on slave port n, 32 bits of error detail
bogdanm	82:6473597d706e	288	* are captured in this read-only register and the corresponding bit in
bogdanm	82:6473597d706e	289	* CESR[SPERR] is set. Information on the faulting address is captured in the
bogdanm	82:6473597d706e	290	* corresponding EARn register at the same time. This register and the corresponding EARn
bogdanm	82:6473597d706e	291	* register contain the most recent access error; there are no hardware interlocks
bogdanm	82:6473597d706e	292	* with CESR[SPERR] as the error registers are always loaded upon the occurrence
bogdanm	82:6473597d706e	293	* of each protection violation.
bogdanm	82:6473597d706e	294	*/
bogdanm	82:6473597d706e	295	typedef union _hw_mpu_edrn
bogdanm	82:6473597d706e	296	{
bogdanm	82:6473597d706e	297	uint32_t U;
bogdanm	82:6473597d706e	298	struct _hw_mpu_edrn_bitfields
bogdanm	82:6473597d706e	299	{
bogdanm	82:6473597d706e	300	uint32_t ERW : 1; //!< [0] Error Read/Write
bogdanm	82:6473597d706e	301	uint32_t EATTR : 3; //!< [3:1] Error Attributes
bogdanm	82:6473597d706e	302	uint32_t EMN : 4; //!< [7:4] Error Master Number
bogdanm	82:6473597d706e	303	uint32_t EPID : 8; //!< [15:8] Error Process Identification
bogdanm	82:6473597d706e	304	uint32_t EACD : 16; //!< [31:16] Error Access Control Detail
bogdanm	82:6473597d706e	305	} B;
bogdanm	82:6473597d706e	306	} hw_mpu_edrn_t;
bogdanm	82:6473597d706e	307	#endif
bogdanm	82:6473597d706e	308
bogdanm	82:6473597d706e	309	/*!
bogdanm	82:6473597d706e	310	* @name Constants and macros for entire MPU_EDRn register
bogdanm	82:6473597d706e	311	*/
bogdanm	82:6473597d706e	312	//@{
bogdanm	82:6473597d706e	313	#define HW_MPU_EDRn_COUNT (5U)
bogdanm	82:6473597d706e	314
bogdanm	82:6473597d706e	315	#define HW_MPU_EDRn_ADDR(n) (REGS_MPU_BASE + 0x14U + (0x8U * n))
bogdanm	82:6473597d706e	316
bogdanm	82:6473597d706e	317	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	318	#define HW_MPU_EDRn(n) ((__I hw_mpu_edrn_t ) HW_MPU_EDRn_ADDR(n))
bogdanm	82:6473597d706e	319	#define HW_MPU_EDRn_RD(n) (HW_MPU_EDRn(n).U)
bogdanm	82:6473597d706e	320	#endif
bogdanm	82:6473597d706e	321	//@}
bogdanm	82:6473597d706e	322
bogdanm	82:6473597d706e	323	/*
bogdanm	82:6473597d706e	324	* Constants & macros for individual MPU_EDRn bitfields
bogdanm	82:6473597d706e	325	*/
bogdanm	82:6473597d706e	326
bogdanm	82:6473597d706e	327	/*!
bogdanm	82:6473597d706e	328	* @name Register MPU_EDRn, field ERW[0] (RO)
bogdanm	82:6473597d706e	329	*
bogdanm	82:6473597d706e	330	* Indicates the access type of the faulting reference.
bogdanm	82:6473597d706e	331	*
bogdanm	82:6473597d706e	332	* Values:
bogdanm	82:6473597d706e	333	* - 0 - Read
bogdanm	82:6473597d706e	334	* - 1 - Write
bogdanm	82:6473597d706e	335	*/
bogdanm	82:6473597d706e	336	//@{
bogdanm	82:6473597d706e	337	#define BP_MPU_EDRn_ERW (0U) //!< Bit position for MPU_EDRn_ERW.
bogdanm	82:6473597d706e	338	#define BM_MPU_EDRn_ERW (0x00000001U) //!< Bit mask for MPU_EDRn_ERW.
bogdanm	82:6473597d706e	339	#define BS_MPU_EDRn_ERW (1U) //!< Bit field size in bits for MPU_EDRn_ERW.
bogdanm	82:6473597d706e	340
bogdanm	82:6473597d706e	341	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	342	//! @brief Read current value of the MPU_EDRn_ERW field.
bogdanm	82:6473597d706e	343	#define BR_MPU_EDRn_ERW(n) (BITBAND_ACCESS32(HW_MPU_EDRn_ADDR(n), BP_MPU_EDRn_ERW))
bogdanm	82:6473597d706e	344	#endif
bogdanm	82:6473597d706e	345	//@}
bogdanm	82:6473597d706e	346
bogdanm	82:6473597d706e	347	/*!
bogdanm	82:6473597d706e	348	* @name Register MPU_EDRn, field EATTR[3:1] (RO)
bogdanm	82:6473597d706e	349	*
bogdanm	82:6473597d706e	350	* Indicates attribute information about the faulting reference. All other
bogdanm	82:6473597d706e	351	* encodings are reserved.
bogdanm	82:6473597d706e	352	*
bogdanm	82:6473597d706e	353	* Values:
bogdanm	82:6473597d706e	354	* - 000 - User mode, instruction access
bogdanm	82:6473597d706e	355	* - 001 - User mode, data access
bogdanm	82:6473597d706e	356	* - 010 - Supervisor mode, instruction access
bogdanm	82:6473597d706e	357	* - 011 - Supervisor mode, data access
bogdanm	82:6473597d706e	358	*/
bogdanm	82:6473597d706e	359	//@{
bogdanm	82:6473597d706e	360	#define BP_MPU_EDRn_EATTR (1U) //!< Bit position for MPU_EDRn_EATTR.
bogdanm	82:6473597d706e	361	#define BM_MPU_EDRn_EATTR (0x0000000EU) //!< Bit mask for MPU_EDRn_EATTR.
bogdanm	82:6473597d706e	362	#define BS_MPU_EDRn_EATTR (3U) //!< Bit field size in bits for MPU_EDRn_EATTR.
bogdanm	82:6473597d706e	363
bogdanm	82:6473597d706e	364	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	365	//! @brief Read current value of the MPU_EDRn_EATTR field.
bogdanm	82:6473597d706e	366	#define BR_MPU_EDRn_EATTR(n) (HW_MPU_EDRn(n).B.EATTR)
bogdanm	82:6473597d706e	367	#endif
bogdanm	82:6473597d706e	368	//@}
bogdanm	82:6473597d706e	369
bogdanm	82:6473597d706e	370	/*!
bogdanm	82:6473597d706e	371	* @name Register MPU_EDRn, field EMN[7:4] (RO)
bogdanm	82:6473597d706e	372	*
bogdanm	82:6473597d706e	373	* Indicates the bus master that generated the access error.
bogdanm	82:6473597d706e	374	*/
bogdanm	82:6473597d706e	375	//@{
bogdanm	82:6473597d706e	376	#define BP_MPU_EDRn_EMN (4U) //!< Bit position for MPU_EDRn_EMN.
bogdanm	82:6473597d706e	377	#define BM_MPU_EDRn_EMN (0x000000F0U) //!< Bit mask for MPU_EDRn_EMN.
bogdanm	82:6473597d706e	378	#define BS_MPU_EDRn_EMN (4U) //!< Bit field size in bits for MPU_EDRn_EMN.
bogdanm	82:6473597d706e	379
bogdanm	82:6473597d706e	380	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	381	//! @brief Read current value of the MPU_EDRn_EMN field.
bogdanm	82:6473597d706e	382	#define BR_MPU_EDRn_EMN(n) (HW_MPU_EDRn(n).B.EMN)
bogdanm	82:6473597d706e	383	#endif
bogdanm	82:6473597d706e	384	//@}
bogdanm	82:6473597d706e	385
bogdanm	82:6473597d706e	386	/*!
bogdanm	82:6473597d706e	387	* @name Register MPU_EDRn, field EPID[15:8] (RO)
bogdanm	82:6473597d706e	388	*
bogdanm	82:6473597d706e	389	* Records the process identifier of the faulting reference. The process
bogdanm	82:6473597d706e	390	* identifier is typically driven only by processor cores; for other bus masters, this
bogdanm	82:6473597d706e	391	* field is cleared.
bogdanm	82:6473597d706e	392	*/
bogdanm	82:6473597d706e	393	//@{
bogdanm	82:6473597d706e	394	#define BP_MPU_EDRn_EPID (8U) //!< Bit position for MPU_EDRn_EPID.
bogdanm	82:6473597d706e	395	#define BM_MPU_EDRn_EPID (0x0000FF00U) //!< Bit mask for MPU_EDRn_EPID.
bogdanm	82:6473597d706e	396	#define BS_MPU_EDRn_EPID (8U) //!< Bit field size in bits for MPU_EDRn_EPID.
bogdanm	82:6473597d706e	397
bogdanm	82:6473597d706e	398	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	399	//! @brief Read current value of the MPU_EDRn_EPID field.
bogdanm	82:6473597d706e	400	#define BR_MPU_EDRn_EPID(n) (HW_MPU_EDRn(n).B.EPID)
bogdanm	82:6473597d706e	401	#endif
bogdanm	82:6473597d706e	402	//@}
bogdanm	82:6473597d706e	403
bogdanm	82:6473597d706e	404	/*!
bogdanm	82:6473597d706e	405	* @name Register MPU_EDRn, field EACD[31:16] (RO)
bogdanm	82:6473597d706e	406	*
bogdanm	82:6473597d706e	407	* Indicates the region descriptor with the access error. If EDRn contains a
bogdanm	82:6473597d706e	408	* captured error and EACD is cleared, an access did not hit in any region
bogdanm	82:6473597d706e	409	* descriptor. If only a single EACD bit is set, the protection error was caused by a
bogdanm	82:6473597d706e	410	* single non-overlapping region descriptor. If two or more EACD bits are set, the
bogdanm	82:6473597d706e	411	* protection error was caused by an overlapping set of region descriptors.
bogdanm	82:6473597d706e	412	*/
bogdanm	82:6473597d706e	413	//@{
bogdanm	82:6473597d706e	414	#define BP_MPU_EDRn_EACD (16U) //!< Bit position for MPU_EDRn_EACD.
bogdanm	82:6473597d706e	415	#define BM_MPU_EDRn_EACD (0xFFFF0000U) //!< Bit mask for MPU_EDRn_EACD.
bogdanm	82:6473597d706e	416	#define BS_MPU_EDRn_EACD (16U) //!< Bit field size in bits for MPU_EDRn_EACD.
bogdanm	82:6473597d706e	417
bogdanm	82:6473597d706e	418	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	419	//! @brief Read current value of the MPU_EDRn_EACD field.
bogdanm	82:6473597d706e	420	#define BR_MPU_EDRn_EACD(n) (HW_MPU_EDRn(n).B.EACD)
bogdanm	82:6473597d706e	421	#endif
bogdanm	82:6473597d706e	422	//@}
bogdanm	82:6473597d706e	423
bogdanm	82:6473597d706e	424	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	425	// HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0
bogdanm	82:6473597d706e	426	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	427
bogdanm	82:6473597d706e	428	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	429	/*!
bogdanm	82:6473597d706e	430	* @brief HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0 (RW)
bogdanm	82:6473597d706e	431	*
bogdanm	82:6473597d706e	432	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	433	*
bogdanm	82:6473597d706e	434	* The first word of the region descriptor defines the 0-modulo-32 byte start
bogdanm	82:6473597d706e	435	* address of the memory region. Writes to this register clear the region
bogdanm	82:6473597d706e	436	* descriptor's valid bit (RGDn_WORD3[VLD]).
bogdanm	82:6473597d706e	437	*/
bogdanm	82:6473597d706e	438	typedef union _hw_mpu_rgdn_word0
bogdanm	82:6473597d706e	439	{
bogdanm	82:6473597d706e	440	uint32_t U;
bogdanm	82:6473597d706e	441	struct _hw_mpu_rgdn_word0_bitfields
bogdanm	82:6473597d706e	442	{
bogdanm	82:6473597d706e	443	uint32_t RESERVED0 : 5; //!< [4:0]
bogdanm	82:6473597d706e	444	uint32_t SRTADDR : 27; //!< [31:5] Start Address
bogdanm	82:6473597d706e	445	} B;
bogdanm	82:6473597d706e	446	} hw_mpu_rgdn_word0_t;
bogdanm	82:6473597d706e	447	#endif
bogdanm	82:6473597d706e	448
bogdanm	82:6473597d706e	449	/*!
bogdanm	82:6473597d706e	450	* @name Constants and macros for entire MPU_RGDn_WORD0 register
bogdanm	82:6473597d706e	451	*/
bogdanm	82:6473597d706e	452	//@{
bogdanm	82:6473597d706e	453	#define HW_MPU_RGDn_WORD0_COUNT (12U)
bogdanm	82:6473597d706e	454
bogdanm	82:6473597d706e	455	#define HW_MPU_RGDn_WORD0_ADDR(n) (REGS_MPU_BASE + 0x400U + (0x10U * n))
bogdanm	82:6473597d706e	456
bogdanm	82:6473597d706e	457	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	458	#define HW_MPU_RGDn_WORD0(n) ((__IO hw_mpu_rgdn_word0_t ) HW_MPU_RGDn_WORD0_ADDR(n))
bogdanm	82:6473597d706e	459	#define HW_MPU_RGDn_WORD0_RD(n) (HW_MPU_RGDn_WORD0(n).U)
bogdanm	82:6473597d706e	460	#define HW_MPU_RGDn_WORD0_WR(n, v) (HW_MPU_RGDn_WORD0(n).U = (v))
bogdanm	82:6473597d706e	461	#define HW_MPU_RGDn_WORD0_SET(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) \| (v)))
bogdanm	82:6473597d706e	462	#define HW_MPU_RGDn_WORD0_CLR(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) & ~(v)))
bogdanm	82:6473597d706e	463	#define HW_MPU_RGDn_WORD0_TOG(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) ^ (v)))
bogdanm	82:6473597d706e	464	#endif
bogdanm	82:6473597d706e	465	//@}
bogdanm	82:6473597d706e	466
bogdanm	82:6473597d706e	467	/*
bogdanm	82:6473597d706e	468	* Constants & macros for individual MPU_RGDn_WORD0 bitfields
bogdanm	82:6473597d706e	469	*/
bogdanm	82:6473597d706e	470
bogdanm	82:6473597d706e	471	/*!
bogdanm	82:6473597d706e	472	* @name Register MPU_RGDn_WORD0, field SRTADDR[31:5] (RW)
bogdanm	82:6473597d706e	473	*
bogdanm	82:6473597d706e	474	* Defines the most significant bits of the 0-modulo-32 byte start address of
bogdanm	82:6473597d706e	475	* the memory region.
bogdanm	82:6473597d706e	476	*/
bogdanm	82:6473597d706e	477	//@{
bogdanm	82:6473597d706e	478	#define BP_MPU_RGDn_WORD0_SRTADDR (5U) //!< Bit position for MPU_RGDn_WORD0_SRTADDR.
bogdanm	82:6473597d706e	479	#define BM_MPU_RGDn_WORD0_SRTADDR (0xFFFFFFE0U) //!< Bit mask for MPU_RGDn_WORD0_SRTADDR.
bogdanm	82:6473597d706e	480	#define BS_MPU_RGDn_WORD0_SRTADDR (27U) //!< Bit field size in bits for MPU_RGDn_WORD0_SRTADDR.
bogdanm	82:6473597d706e	481
bogdanm	82:6473597d706e	482	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	483	//! @brief Read current value of the MPU_RGDn_WORD0_SRTADDR field.
bogdanm	82:6473597d706e	484	#define BR_MPU_RGDn_WORD0_SRTADDR(n) (HW_MPU_RGDn_WORD0(n).B.SRTADDR)
bogdanm	82:6473597d706e	485	#endif
bogdanm	82:6473597d706e	486
bogdanm	82:6473597d706e	487	//! @brief Format value for bitfield MPU_RGDn_WORD0_SRTADDR.
bogdanm	82:6473597d706e	488	#define BF_MPU_RGDn_WORD0_SRTADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD0_SRTADDR), uint32_t) & BM_MPU_RGDn_WORD0_SRTADDR)
bogdanm	82:6473597d706e	489
bogdanm	82:6473597d706e	490	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	491	//! @brief Set the SRTADDR field to a new value.
bogdanm	82:6473597d706e	492	#define BW_MPU_RGDn_WORD0_SRTADDR(n, v) (HW_MPU_RGDn_WORD0_WR(n, (HW_MPU_RGDn_WORD0_RD(n) & ~BM_MPU_RGDn_WORD0_SRTADDR) \| BF_MPU_RGDn_WORD0_SRTADDR(v)))
bogdanm	82:6473597d706e	493	#endif
bogdanm	82:6473597d706e	494	//@}
bogdanm	82:6473597d706e	495	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	496	// HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1
bogdanm	82:6473597d706e	497	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	498
bogdanm	82:6473597d706e	499	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	500	/*!
bogdanm	82:6473597d706e	501	* @brief HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1 (RW)
bogdanm	82:6473597d706e	502	*
bogdanm	82:6473597d706e	503	* Reset value: 0xFFFFFFFFU
bogdanm	82:6473597d706e	504	*
bogdanm	82:6473597d706e	505	* The second word of the region descriptor defines the 31-modulo-32 byte end
bogdanm	82:6473597d706e	506	* address of the memory region. Writes to this register clear the region
bogdanm	82:6473597d706e	507	* descriptor's valid bit (RGDn_WORD3[VLD]).
bogdanm	82:6473597d706e	508	*/
bogdanm	82:6473597d706e	509	typedef union _hw_mpu_rgdn_word1
bogdanm	82:6473597d706e	510	{
bogdanm	82:6473597d706e	511	uint32_t U;
bogdanm	82:6473597d706e	512	struct _hw_mpu_rgdn_word1_bitfields
bogdanm	82:6473597d706e	513	{
bogdanm	82:6473597d706e	514	uint32_t RESERVED0 : 5; //!< [4:0]
bogdanm	82:6473597d706e	515	uint32_t ENDADDR : 27; //!< [31:5] End Address
bogdanm	82:6473597d706e	516	} B;
bogdanm	82:6473597d706e	517	} hw_mpu_rgdn_word1_t;
bogdanm	82:6473597d706e	518	#endif
bogdanm	82:6473597d706e	519
bogdanm	82:6473597d706e	520	/*!
bogdanm	82:6473597d706e	521	* @name Constants and macros for entire MPU_RGDn_WORD1 register
bogdanm	82:6473597d706e	522	*/
bogdanm	82:6473597d706e	523	//@{
bogdanm	82:6473597d706e	524	#define HW_MPU_RGDn_WORD1_COUNT (12U)
bogdanm	82:6473597d706e	525
bogdanm	82:6473597d706e	526	#define HW_MPU_RGDn_WORD1_ADDR(n) (REGS_MPU_BASE + 0x404U + (0x10U * n))
bogdanm	82:6473597d706e	527
bogdanm	82:6473597d706e	528	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	529	#define HW_MPU_RGDn_WORD1(n) ((__IO hw_mpu_rgdn_word1_t ) HW_MPU_RGDn_WORD1_ADDR(n))
bogdanm	82:6473597d706e	530	#define HW_MPU_RGDn_WORD1_RD(n) (HW_MPU_RGDn_WORD1(n).U)
bogdanm	82:6473597d706e	531	#define HW_MPU_RGDn_WORD1_WR(n, v) (HW_MPU_RGDn_WORD1(n).U = (v))
bogdanm	82:6473597d706e	532	#define HW_MPU_RGDn_WORD1_SET(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) \| (v)))
bogdanm	82:6473597d706e	533	#define HW_MPU_RGDn_WORD1_CLR(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) & ~(v)))
bogdanm	82:6473597d706e	534	#define HW_MPU_RGDn_WORD1_TOG(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) ^ (v)))
bogdanm	82:6473597d706e	535	#endif
bogdanm	82:6473597d706e	536	//@}
bogdanm	82:6473597d706e	537
bogdanm	82:6473597d706e	538	/*
bogdanm	82:6473597d706e	539	* Constants & macros for individual MPU_RGDn_WORD1 bitfields
bogdanm	82:6473597d706e	540	*/
bogdanm	82:6473597d706e	541
bogdanm	82:6473597d706e	542	/*!
bogdanm	82:6473597d706e	543	* @name Register MPU_RGDn_WORD1, field ENDADDR[31:5] (RW)
bogdanm	82:6473597d706e	544	*
bogdanm	82:6473597d706e	545	* Defines the most significant bits of the 31-modulo-32 byte end address of the
bogdanm	82:6473597d706e	546	* memory region. The MPU does not verify that ENDADDR >= SRTADDR.
bogdanm	82:6473597d706e	547	*/
bogdanm	82:6473597d706e	548	//@{
bogdanm	82:6473597d706e	549	#define BP_MPU_RGDn_WORD1_ENDADDR (5U) //!< Bit position for MPU_RGDn_WORD1_ENDADDR.
bogdanm	82:6473597d706e	550	#define BM_MPU_RGDn_WORD1_ENDADDR (0xFFFFFFE0U) //!< Bit mask for MPU_RGDn_WORD1_ENDADDR.
bogdanm	82:6473597d706e	551	#define BS_MPU_RGDn_WORD1_ENDADDR (27U) //!< Bit field size in bits for MPU_RGDn_WORD1_ENDADDR.
bogdanm	82:6473597d706e	552
bogdanm	82:6473597d706e	553	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	554	//! @brief Read current value of the MPU_RGDn_WORD1_ENDADDR field.
bogdanm	82:6473597d706e	555	#define BR_MPU_RGDn_WORD1_ENDADDR(n) (HW_MPU_RGDn_WORD1(n).B.ENDADDR)
bogdanm	82:6473597d706e	556	#endif
bogdanm	82:6473597d706e	557
bogdanm	82:6473597d706e	558	//! @brief Format value for bitfield MPU_RGDn_WORD1_ENDADDR.
bogdanm	82:6473597d706e	559	#define BF_MPU_RGDn_WORD1_ENDADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD1_ENDADDR), uint32_t) & BM_MPU_RGDn_WORD1_ENDADDR)
bogdanm	82:6473597d706e	560
bogdanm	82:6473597d706e	561	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	562	//! @brief Set the ENDADDR field to a new value.
bogdanm	82:6473597d706e	563	#define BW_MPU_RGDn_WORD1_ENDADDR(n, v) (HW_MPU_RGDn_WORD1_WR(n, (HW_MPU_RGDn_WORD1_RD(n) & ~BM_MPU_RGDn_WORD1_ENDADDR) \| BF_MPU_RGDn_WORD1_ENDADDR(v)))
bogdanm	82:6473597d706e	564	#endif
bogdanm	82:6473597d706e	565	//@}
bogdanm	82:6473597d706e	566	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	567	// HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2
bogdanm	82:6473597d706e	568	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	569
bogdanm	82:6473597d706e	570	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	571	/*!
bogdanm	82:6473597d706e	572	* @brief HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2 (RW)
bogdanm	82:6473597d706e	573	*
bogdanm	82:6473597d706e	574	* Reset value: 0x0061F7DFU
bogdanm	82:6473597d706e	575	*
bogdanm	82:6473597d706e	576	* The third word of the region descriptor defines the access control rights of
bogdanm	82:6473597d706e	577	* the memory region. The access control privileges depend on two broad
bogdanm	82:6473597d706e	578	* classifications of bus masters: Bus masters 0-3 have a 5-bit field defining separate
bogdanm	82:6473597d706e	579	* privilege rights for user and supervisor mode accesses, as well as the optional
bogdanm	82:6473597d706e	580	* inclusion of a process identification field within the definition. Bus masters
bogdanm	82:6473597d706e	581	* 4-7 are limited to separate read and write permissions. For the privilege
bogdanm	82:6473597d706e	582	* rights of bus masters 0-3, there are three flags associated with this function:
bogdanm	82:6473597d706e	583	* Read (r) refers to accessing the referenced memory address using an operand
bogdanm	82:6473597d706e	584	* (data) fetch Write (w) refers to updating the referenced memory address using a
bogdanm	82:6473597d706e	585	* store (data) instruction Execute (x) refers to reading the referenced memory
bogdanm	82:6473597d706e	586	* address using an instruction fetch Writes to RGDn_WORD2 clear the region
bogdanm	82:6473597d706e	587	* descriptor's valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write
bogdanm	82:6473597d706e	588	* to RGDAACn instead because stores to these locations do not affect the
bogdanm	82:6473597d706e	589	* descriptor's valid bit.
bogdanm	82:6473597d706e	590	*/
bogdanm	82:6473597d706e	591	typedef union _hw_mpu_rgdn_word2
bogdanm	82:6473597d706e	592	{
bogdanm	82:6473597d706e	593	uint32_t U;
bogdanm	82:6473597d706e	594	struct _hw_mpu_rgdn_word2_bitfields
bogdanm	82:6473597d706e	595	{
bogdanm	82:6473597d706e	596	uint32_t M0UM : 3; //!< [2:0] Bus Master 0 User Mode Access Control
bogdanm	82:6473597d706e	597	uint32_t M0SM : 2; //!< [4:3] Bus Master 0 Supervisor Mode Access
bogdanm	82:6473597d706e	598	//! Control
bogdanm	82:6473597d706e	599	uint32_t M0PE : 1; //!< [5] Bus Master 0 Process Identifier enable
bogdanm	82:6473597d706e	600	uint32_t M1UM : 3; //!< [8:6] Bus Master 1 User Mode Access Control
bogdanm	82:6473597d706e	601	uint32_t M1SM : 2; //!< [10:9] Bus Master 1 Supervisor Mode Access
bogdanm	82:6473597d706e	602	//! Control
bogdanm	82:6473597d706e	603	uint32_t M1PE : 1; //!< [11] Bus Master 1 Process Identifier enable
bogdanm	82:6473597d706e	604	uint32_t M2UM : 3; //!< [14:12] Bus Master 2 User Mode Access control
bogdanm	82:6473597d706e	605	uint32_t M2SM : 2; //!< [16:15] Bus Master 2 Supervisor Mode Access
bogdanm	82:6473597d706e	606	//! Control
bogdanm	82:6473597d706e	607	uint32_t M2PE : 1; //!< [17] Bus Master 2 Process Identifier Enable
bogdanm	82:6473597d706e	608	uint32_t M3UM : 3; //!< [20:18] Bus Master 3 User Mode Access Control
bogdanm	82:6473597d706e	609	uint32_t M3SM : 2; //!< [22:21] Bus Master 3 Supervisor Mode Access
bogdanm	82:6473597d706e	610	//! Control
bogdanm	82:6473597d706e	611	uint32_t M3PE : 1; //!< [23] Bus Master 3 Process Identifier Enable
bogdanm	82:6473597d706e	612	uint32_t M4WE : 1; //!< [24] Bus Master 4 Write Enable
bogdanm	82:6473597d706e	613	uint32_t M4RE : 1; //!< [25] Bus Master 4 Read Enable
bogdanm	82:6473597d706e	614	uint32_t M5WE : 1; //!< [26] Bus Master 5 Write Enable
bogdanm	82:6473597d706e	615	uint32_t M5RE : 1; //!< [27] Bus Master 5 Read Enable
bogdanm	82:6473597d706e	616	uint32_t M6WE : 1; //!< [28] Bus Master 6 Write Enable
bogdanm	82:6473597d706e	617	uint32_t M6RE : 1; //!< [29] Bus Master 6 Read Enable
bogdanm	82:6473597d706e	618	uint32_t M7WE : 1; //!< [30] Bus Master 7 Write Enable
bogdanm	82:6473597d706e	619	uint32_t M7RE : 1; //!< [31] Bus Master 7 Read Enable
bogdanm	82:6473597d706e	620	} B;
bogdanm	82:6473597d706e	621	} hw_mpu_rgdn_word2_t;
bogdanm	82:6473597d706e	622	#endif
bogdanm	82:6473597d706e	623
bogdanm	82:6473597d706e	624	/*!
bogdanm	82:6473597d706e	625	* @name Constants and macros for entire MPU_RGDn_WORD2 register
bogdanm	82:6473597d706e	626	*/
bogdanm	82:6473597d706e	627	//@{
bogdanm	82:6473597d706e	628	#define HW_MPU_RGDn_WORD2_COUNT (12U)
bogdanm	82:6473597d706e	629
bogdanm	82:6473597d706e	630	#define HW_MPU_RGDn_WORD2_ADDR(n) (REGS_MPU_BASE + 0x408U + (0x10U * n))
bogdanm	82:6473597d706e	631
bogdanm	82:6473597d706e	632	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	633	#define HW_MPU_RGDn_WORD2(n) ((__IO hw_mpu_rgdn_word2_t ) HW_MPU_RGDn_WORD2_ADDR(n))
bogdanm	82:6473597d706e	634	#define HW_MPU_RGDn_WORD2_RD(n) (HW_MPU_RGDn_WORD2(n).U)
bogdanm	82:6473597d706e	635	#define HW_MPU_RGDn_WORD2_WR(n, v) (HW_MPU_RGDn_WORD2(n).U = (v))
bogdanm	82:6473597d706e	636	#define HW_MPU_RGDn_WORD2_SET(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) \| (v)))
bogdanm	82:6473597d706e	637	#define HW_MPU_RGDn_WORD2_CLR(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) & ~(v)))
bogdanm	82:6473597d706e	638	#define HW_MPU_RGDn_WORD2_TOG(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) ^ (v)))
bogdanm	82:6473597d706e	639	#endif
bogdanm	82:6473597d706e	640	//@}
bogdanm	82:6473597d706e	641
bogdanm	82:6473597d706e	642	/*
bogdanm	82:6473597d706e	643	* Constants & macros for individual MPU_RGDn_WORD2 bitfields
bogdanm	82:6473597d706e	644	*/
bogdanm	82:6473597d706e	645
bogdanm	82:6473597d706e	646	/*!
bogdanm	82:6473597d706e	647	* @name Register MPU_RGDn_WORD2, field M0UM[2:0] (RW)
bogdanm	82:6473597d706e	648	*
bogdanm	82:6473597d706e	649	* See M3UM description.
bogdanm	82:6473597d706e	650	*/
bogdanm	82:6473597d706e	651	//@{
bogdanm	82:6473597d706e	652	#define BP_MPU_RGDn_WORD2_M0UM (0U) //!< Bit position for MPU_RGDn_WORD2_M0UM.
bogdanm	82:6473597d706e	653	#define BM_MPU_RGDn_WORD2_M0UM (0x00000007U) //!< Bit mask for MPU_RGDn_WORD2_M0UM.
bogdanm	82:6473597d706e	654	#define BS_MPU_RGDn_WORD2_M0UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M0UM.
bogdanm	82:6473597d706e	655
bogdanm	82:6473597d706e	656	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	657	//! @brief Read current value of the MPU_RGDn_WORD2_M0UM field.
bogdanm	82:6473597d706e	658	#define BR_MPU_RGDn_WORD2_M0UM(n) (HW_MPU_RGDn_WORD2(n).B.M0UM)
bogdanm	82:6473597d706e	659	#endif
bogdanm	82:6473597d706e	660
bogdanm	82:6473597d706e	661	//! @brief Format value for bitfield MPU_RGDn_WORD2_M0UM.
bogdanm	82:6473597d706e	662	#define BF_MPU_RGDn_WORD2_M0UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0UM), uint32_t) & BM_MPU_RGDn_WORD2_M0UM)
bogdanm	82:6473597d706e	663
bogdanm	82:6473597d706e	664	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	665	//! @brief Set the M0UM field to a new value.
bogdanm	82:6473597d706e	666	#define BW_MPU_RGDn_WORD2_M0UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M0UM) \| BF_MPU_RGDn_WORD2_M0UM(v)))
bogdanm	82:6473597d706e	667	#endif
bogdanm	82:6473597d706e	668	//@}
bogdanm	82:6473597d706e	669
bogdanm	82:6473597d706e	670	/*!
bogdanm	82:6473597d706e	671	* @name Register MPU_RGDn_WORD2, field M0SM[4:3] (RW)
bogdanm	82:6473597d706e	672	*
bogdanm	82:6473597d706e	673	* See M3SM description.
bogdanm	82:6473597d706e	674	*/
bogdanm	82:6473597d706e	675	//@{
bogdanm	82:6473597d706e	676	#define BP_MPU_RGDn_WORD2_M0SM (3U) //!< Bit position for MPU_RGDn_WORD2_M0SM.
bogdanm	82:6473597d706e	677	#define BM_MPU_RGDn_WORD2_M0SM (0x00000018U) //!< Bit mask for MPU_RGDn_WORD2_M0SM.
bogdanm	82:6473597d706e	678	#define BS_MPU_RGDn_WORD2_M0SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M0SM.
bogdanm	82:6473597d706e	679
bogdanm	82:6473597d706e	680	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	681	//! @brief Read current value of the MPU_RGDn_WORD2_M0SM field.
bogdanm	82:6473597d706e	682	#define BR_MPU_RGDn_WORD2_M0SM(n) (HW_MPU_RGDn_WORD2(n).B.M0SM)
bogdanm	82:6473597d706e	683	#endif
bogdanm	82:6473597d706e	684
bogdanm	82:6473597d706e	685	//! @brief Format value for bitfield MPU_RGDn_WORD2_M0SM.
bogdanm	82:6473597d706e	686	#define BF_MPU_RGDn_WORD2_M0SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0SM), uint32_t) & BM_MPU_RGDn_WORD2_M0SM)
bogdanm	82:6473597d706e	687
bogdanm	82:6473597d706e	688	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	689	//! @brief Set the M0SM field to a new value.
bogdanm	82:6473597d706e	690	#define BW_MPU_RGDn_WORD2_M0SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M0SM) \| BF_MPU_RGDn_WORD2_M0SM(v)))
bogdanm	82:6473597d706e	691	#endif
bogdanm	82:6473597d706e	692	//@}
bogdanm	82:6473597d706e	693
bogdanm	82:6473597d706e	694	/*!
bogdanm	82:6473597d706e	695	* @name Register MPU_RGDn_WORD2, field M0PE[5] (RW)
bogdanm	82:6473597d706e	696	*
bogdanm	82:6473597d706e	697	* See M0PE description.
bogdanm	82:6473597d706e	698	*/
bogdanm	82:6473597d706e	699	//@{
bogdanm	82:6473597d706e	700	#define BP_MPU_RGDn_WORD2_M0PE (5U) //!< Bit position for MPU_RGDn_WORD2_M0PE.
bogdanm	82:6473597d706e	701	#define BM_MPU_RGDn_WORD2_M0PE (0x00000020U) //!< Bit mask for MPU_RGDn_WORD2_M0PE.
bogdanm	82:6473597d706e	702	#define BS_MPU_RGDn_WORD2_M0PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M0PE.
bogdanm	82:6473597d706e	703
bogdanm	82:6473597d706e	704	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	705	//! @brief Read current value of the MPU_RGDn_WORD2_M0PE field.
bogdanm	82:6473597d706e	706	#define BR_MPU_RGDn_WORD2_M0PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M0PE))
bogdanm	82:6473597d706e	707	#endif
bogdanm	82:6473597d706e	708
bogdanm	82:6473597d706e	709	//! @brief Format value for bitfield MPU_RGDn_WORD2_M0PE.
bogdanm	82:6473597d706e	710	#define BF_MPU_RGDn_WORD2_M0PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0PE), uint32_t) & BM_MPU_RGDn_WORD2_M0PE)
bogdanm	82:6473597d706e	711
bogdanm	82:6473597d706e	712	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	713	//! @brief Set the M0PE field to a new value.
bogdanm	82:6473597d706e	714	#define BW_MPU_RGDn_WORD2_M0PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M0PE) = (v))
bogdanm	82:6473597d706e	715	#endif
bogdanm	82:6473597d706e	716	//@}
bogdanm	82:6473597d706e	717
bogdanm	82:6473597d706e	718	/*!
bogdanm	82:6473597d706e	719	* @name Register MPU_RGDn_WORD2, field M1UM[8:6] (RW)
bogdanm	82:6473597d706e	720	*
bogdanm	82:6473597d706e	721	* See M3UM description.
bogdanm	82:6473597d706e	722	*/
bogdanm	82:6473597d706e	723	//@{
bogdanm	82:6473597d706e	724	#define BP_MPU_RGDn_WORD2_M1UM (6U) //!< Bit position for MPU_RGDn_WORD2_M1UM.
bogdanm	82:6473597d706e	725	#define BM_MPU_RGDn_WORD2_M1UM (0x000001C0U) //!< Bit mask for MPU_RGDn_WORD2_M1UM.
bogdanm	82:6473597d706e	726	#define BS_MPU_RGDn_WORD2_M1UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M1UM.
bogdanm	82:6473597d706e	727
bogdanm	82:6473597d706e	728	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	729	//! @brief Read current value of the MPU_RGDn_WORD2_M1UM field.
bogdanm	82:6473597d706e	730	#define BR_MPU_RGDn_WORD2_M1UM(n) (HW_MPU_RGDn_WORD2(n).B.M1UM)
bogdanm	82:6473597d706e	731	#endif
bogdanm	82:6473597d706e	732
bogdanm	82:6473597d706e	733	//! @brief Format value for bitfield MPU_RGDn_WORD2_M1UM.
bogdanm	82:6473597d706e	734	#define BF_MPU_RGDn_WORD2_M1UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1UM), uint32_t) & BM_MPU_RGDn_WORD2_M1UM)
bogdanm	82:6473597d706e	735
bogdanm	82:6473597d706e	736	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	737	//! @brief Set the M1UM field to a new value.
bogdanm	82:6473597d706e	738	#define BW_MPU_RGDn_WORD2_M1UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M1UM) \| BF_MPU_RGDn_WORD2_M1UM(v)))
bogdanm	82:6473597d706e	739	#endif
bogdanm	82:6473597d706e	740	//@}
bogdanm	82:6473597d706e	741
bogdanm	82:6473597d706e	742	/*!
bogdanm	82:6473597d706e	743	* @name Register MPU_RGDn_WORD2, field M1SM[10:9] (RW)
bogdanm	82:6473597d706e	744	*
bogdanm	82:6473597d706e	745	* See M3SM description.
bogdanm	82:6473597d706e	746	*/
bogdanm	82:6473597d706e	747	//@{
bogdanm	82:6473597d706e	748	#define BP_MPU_RGDn_WORD2_M1SM (9U) //!< Bit position for MPU_RGDn_WORD2_M1SM.
bogdanm	82:6473597d706e	749	#define BM_MPU_RGDn_WORD2_M1SM (0x00000600U) //!< Bit mask for MPU_RGDn_WORD2_M1SM.
bogdanm	82:6473597d706e	750	#define BS_MPU_RGDn_WORD2_M1SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M1SM.
bogdanm	82:6473597d706e	751
bogdanm	82:6473597d706e	752	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	753	//! @brief Read current value of the MPU_RGDn_WORD2_M1SM field.
bogdanm	82:6473597d706e	754	#define BR_MPU_RGDn_WORD2_M1SM(n) (HW_MPU_RGDn_WORD2(n).B.M1SM)
bogdanm	82:6473597d706e	755	#endif
bogdanm	82:6473597d706e	756
bogdanm	82:6473597d706e	757	//! @brief Format value for bitfield MPU_RGDn_WORD2_M1SM.
bogdanm	82:6473597d706e	758	#define BF_MPU_RGDn_WORD2_M1SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1SM), uint32_t) & BM_MPU_RGDn_WORD2_M1SM)
bogdanm	82:6473597d706e	759
bogdanm	82:6473597d706e	760	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	761	//! @brief Set the M1SM field to a new value.
bogdanm	82:6473597d706e	762	#define BW_MPU_RGDn_WORD2_M1SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M1SM) \| BF_MPU_RGDn_WORD2_M1SM(v)))
bogdanm	82:6473597d706e	763	#endif
bogdanm	82:6473597d706e	764	//@}
bogdanm	82:6473597d706e	765
bogdanm	82:6473597d706e	766	/*!
bogdanm	82:6473597d706e	767	* @name Register MPU_RGDn_WORD2, field M1PE[11] (RW)
bogdanm	82:6473597d706e	768	*
bogdanm	82:6473597d706e	769	* See M3PE description.
bogdanm	82:6473597d706e	770	*/
bogdanm	82:6473597d706e	771	//@{
bogdanm	82:6473597d706e	772	#define BP_MPU_RGDn_WORD2_M1PE (11U) //!< Bit position for MPU_RGDn_WORD2_M1PE.
bogdanm	82:6473597d706e	773	#define BM_MPU_RGDn_WORD2_M1PE (0x00000800U) //!< Bit mask for MPU_RGDn_WORD2_M1PE.
bogdanm	82:6473597d706e	774	#define BS_MPU_RGDn_WORD2_M1PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M1PE.
bogdanm	82:6473597d706e	775
bogdanm	82:6473597d706e	776	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	777	//! @brief Read current value of the MPU_RGDn_WORD2_M1PE field.
bogdanm	82:6473597d706e	778	#define BR_MPU_RGDn_WORD2_M1PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M1PE))
bogdanm	82:6473597d706e	779	#endif
bogdanm	82:6473597d706e	780
bogdanm	82:6473597d706e	781	//! @brief Format value for bitfield MPU_RGDn_WORD2_M1PE.
bogdanm	82:6473597d706e	782	#define BF_MPU_RGDn_WORD2_M1PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1PE), uint32_t) & BM_MPU_RGDn_WORD2_M1PE)
bogdanm	82:6473597d706e	783
bogdanm	82:6473597d706e	784	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	785	//! @brief Set the M1PE field to a new value.
bogdanm	82:6473597d706e	786	#define BW_MPU_RGDn_WORD2_M1PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M1PE) = (v))
bogdanm	82:6473597d706e	787	#endif
bogdanm	82:6473597d706e	788	//@}
bogdanm	82:6473597d706e	789
bogdanm	82:6473597d706e	790	/*!
bogdanm	82:6473597d706e	791	* @name Register MPU_RGDn_WORD2, field M2UM[14:12] (RW)
bogdanm	82:6473597d706e	792	*
bogdanm	82:6473597d706e	793	* See M3UM description.
bogdanm	82:6473597d706e	794	*/
bogdanm	82:6473597d706e	795	//@{
bogdanm	82:6473597d706e	796	#define BP_MPU_RGDn_WORD2_M2UM (12U) //!< Bit position for MPU_RGDn_WORD2_M2UM.
bogdanm	82:6473597d706e	797	#define BM_MPU_RGDn_WORD2_M2UM (0x00007000U) //!< Bit mask for MPU_RGDn_WORD2_M2UM.
bogdanm	82:6473597d706e	798	#define BS_MPU_RGDn_WORD2_M2UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M2UM.
bogdanm	82:6473597d706e	799
bogdanm	82:6473597d706e	800	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	801	//! @brief Read current value of the MPU_RGDn_WORD2_M2UM field.
bogdanm	82:6473597d706e	802	#define BR_MPU_RGDn_WORD2_M2UM(n) (HW_MPU_RGDn_WORD2(n).B.M2UM)
bogdanm	82:6473597d706e	803	#endif
bogdanm	82:6473597d706e	804
bogdanm	82:6473597d706e	805	//! @brief Format value for bitfield MPU_RGDn_WORD2_M2UM.
bogdanm	82:6473597d706e	806	#define BF_MPU_RGDn_WORD2_M2UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2UM), uint32_t) & BM_MPU_RGDn_WORD2_M2UM)
bogdanm	82:6473597d706e	807
bogdanm	82:6473597d706e	808	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	809	//! @brief Set the M2UM field to a new value.
bogdanm	82:6473597d706e	810	#define BW_MPU_RGDn_WORD2_M2UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M2UM) \| BF_MPU_RGDn_WORD2_M2UM(v)))
bogdanm	82:6473597d706e	811	#endif
bogdanm	82:6473597d706e	812	//@}
bogdanm	82:6473597d706e	813
bogdanm	82:6473597d706e	814	/*!
bogdanm	82:6473597d706e	815	* @name Register MPU_RGDn_WORD2, field M2SM[16:15] (RW)
bogdanm	82:6473597d706e	816	*
bogdanm	82:6473597d706e	817	* See M3SM description.
bogdanm	82:6473597d706e	818	*/
bogdanm	82:6473597d706e	819	//@{
bogdanm	82:6473597d706e	820	#define BP_MPU_RGDn_WORD2_M2SM (15U) //!< Bit position for MPU_RGDn_WORD2_M2SM.
bogdanm	82:6473597d706e	821	#define BM_MPU_RGDn_WORD2_M2SM (0x00018000U) //!< Bit mask for MPU_RGDn_WORD2_M2SM.
bogdanm	82:6473597d706e	822	#define BS_MPU_RGDn_WORD2_M2SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M2SM.
bogdanm	82:6473597d706e	823
bogdanm	82:6473597d706e	824	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	825	//! @brief Read current value of the MPU_RGDn_WORD2_M2SM field.
bogdanm	82:6473597d706e	826	#define BR_MPU_RGDn_WORD2_M2SM(n) (HW_MPU_RGDn_WORD2(n).B.M2SM)
bogdanm	82:6473597d706e	827	#endif
bogdanm	82:6473597d706e	828
bogdanm	82:6473597d706e	829	//! @brief Format value for bitfield MPU_RGDn_WORD2_M2SM.
bogdanm	82:6473597d706e	830	#define BF_MPU_RGDn_WORD2_M2SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2SM), uint32_t) & BM_MPU_RGDn_WORD2_M2SM)
bogdanm	82:6473597d706e	831
bogdanm	82:6473597d706e	832	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	833	//! @brief Set the M2SM field to a new value.
bogdanm	82:6473597d706e	834	#define BW_MPU_RGDn_WORD2_M2SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M2SM) \| BF_MPU_RGDn_WORD2_M2SM(v)))
bogdanm	82:6473597d706e	835	#endif
bogdanm	82:6473597d706e	836	//@}
bogdanm	82:6473597d706e	837
bogdanm	82:6473597d706e	838	/*!
bogdanm	82:6473597d706e	839	* @name Register MPU_RGDn_WORD2, field M2PE[17] (RW)
bogdanm	82:6473597d706e	840	*
bogdanm	82:6473597d706e	841	* See M3PE description.
bogdanm	82:6473597d706e	842	*/
bogdanm	82:6473597d706e	843	//@{
bogdanm	82:6473597d706e	844	#define BP_MPU_RGDn_WORD2_M2PE (17U) //!< Bit position for MPU_RGDn_WORD2_M2PE.
bogdanm	82:6473597d706e	845	#define BM_MPU_RGDn_WORD2_M2PE (0x00020000U) //!< Bit mask for MPU_RGDn_WORD2_M2PE.
bogdanm	82:6473597d706e	846	#define BS_MPU_RGDn_WORD2_M2PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M2PE.
bogdanm	82:6473597d706e	847
bogdanm	82:6473597d706e	848	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	849	//! @brief Read current value of the MPU_RGDn_WORD2_M2PE field.
bogdanm	82:6473597d706e	850	#define BR_MPU_RGDn_WORD2_M2PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M2PE))
bogdanm	82:6473597d706e	851	#endif
bogdanm	82:6473597d706e	852
bogdanm	82:6473597d706e	853	//! @brief Format value for bitfield MPU_RGDn_WORD2_M2PE.
bogdanm	82:6473597d706e	854	#define BF_MPU_RGDn_WORD2_M2PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2PE), uint32_t) & BM_MPU_RGDn_WORD2_M2PE)
bogdanm	82:6473597d706e	855
bogdanm	82:6473597d706e	856	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	857	//! @brief Set the M2PE field to a new value.
bogdanm	82:6473597d706e	858	#define BW_MPU_RGDn_WORD2_M2PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M2PE) = (v))
bogdanm	82:6473597d706e	859	#endif
bogdanm	82:6473597d706e	860	//@}
bogdanm	82:6473597d706e	861
bogdanm	82:6473597d706e	862	/*!
bogdanm	82:6473597d706e	863	* @name Register MPU_RGDn_WORD2, field M3UM[20:18] (RW)
bogdanm	82:6473597d706e	864	*
bogdanm	82:6473597d706e	865	* Defines the access controls for bus master 3 in User mode. M3UM consists of
bogdanm	82:6473597d706e	866	* three independent bits, enabling read (r), write (w), and execute (x)
bogdanm	82:6473597d706e	867	* permissions.
bogdanm	82:6473597d706e	868	*
bogdanm	82:6473597d706e	869	* Values:
bogdanm	82:6473597d706e	870	* - 0 - An attempted access of that mode may be terminated with an access error
bogdanm	82:6473597d706e	871	* (if not allowed by another descriptor) and the access not performed.
bogdanm	82:6473597d706e	872	* - 1 - Allows the given access type to occur
bogdanm	82:6473597d706e	873	*/
bogdanm	82:6473597d706e	874	//@{
bogdanm	82:6473597d706e	875	#define BP_MPU_RGDn_WORD2_M3UM (18U) //!< Bit position for MPU_RGDn_WORD2_M3UM.
bogdanm	82:6473597d706e	876	#define BM_MPU_RGDn_WORD2_M3UM (0x001C0000U) //!< Bit mask for MPU_RGDn_WORD2_M3UM.
bogdanm	82:6473597d706e	877	#define BS_MPU_RGDn_WORD2_M3UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M3UM.
bogdanm	82:6473597d706e	878
bogdanm	82:6473597d706e	879	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	880	//! @brief Read current value of the MPU_RGDn_WORD2_M3UM field.
bogdanm	82:6473597d706e	881	#define BR_MPU_RGDn_WORD2_M3UM(n) (HW_MPU_RGDn_WORD2(n).B.M3UM)
bogdanm	82:6473597d706e	882	#endif
bogdanm	82:6473597d706e	883
bogdanm	82:6473597d706e	884	//! @brief Format value for bitfield MPU_RGDn_WORD2_M3UM.
bogdanm	82:6473597d706e	885	#define BF_MPU_RGDn_WORD2_M3UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3UM), uint32_t) & BM_MPU_RGDn_WORD2_M3UM)
bogdanm	82:6473597d706e	886
bogdanm	82:6473597d706e	887	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	888	//! @brief Set the M3UM field to a new value.
bogdanm	82:6473597d706e	889	#define BW_MPU_RGDn_WORD2_M3UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M3UM) \| BF_MPU_RGDn_WORD2_M3UM(v)))
bogdanm	82:6473597d706e	890	#endif
bogdanm	82:6473597d706e	891	//@}
bogdanm	82:6473597d706e	892
bogdanm	82:6473597d706e	893	/*!
bogdanm	82:6473597d706e	894	* @name Register MPU_RGDn_WORD2, field M3SM[22:21] (RW)
bogdanm	82:6473597d706e	895	*
bogdanm	82:6473597d706e	896	* Defines the access controls for bus master 3 in Supervisor mode.
bogdanm	82:6473597d706e	897	*
bogdanm	82:6473597d706e	898	* Values:
bogdanm	82:6473597d706e	899	* - 00 - r/w/x; read, write and execute allowed
bogdanm	82:6473597d706e	900	* - 01 - r/x; read and execute allowed, but no write
bogdanm	82:6473597d706e	901	* - 10 - r/w; read and write allowed, but no execute
bogdanm	82:6473597d706e	902	* - 11 - Same as User mode defined in M3UM
bogdanm	82:6473597d706e	903	*/
bogdanm	82:6473597d706e	904	//@{
bogdanm	82:6473597d706e	905	#define BP_MPU_RGDn_WORD2_M3SM (21U) //!< Bit position for MPU_RGDn_WORD2_M3SM.
bogdanm	82:6473597d706e	906	#define BM_MPU_RGDn_WORD2_M3SM (0x00600000U) //!< Bit mask for MPU_RGDn_WORD2_M3SM.
bogdanm	82:6473597d706e	907	#define BS_MPU_RGDn_WORD2_M3SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M3SM.
bogdanm	82:6473597d706e	908
bogdanm	82:6473597d706e	909	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	910	//! @brief Read current value of the MPU_RGDn_WORD2_M3SM field.
bogdanm	82:6473597d706e	911	#define BR_MPU_RGDn_WORD2_M3SM(n) (HW_MPU_RGDn_WORD2(n).B.M3SM)
bogdanm	82:6473597d706e	912	#endif
bogdanm	82:6473597d706e	913
bogdanm	82:6473597d706e	914	//! @brief Format value for bitfield MPU_RGDn_WORD2_M3SM.
bogdanm	82:6473597d706e	915	#define BF_MPU_RGDn_WORD2_M3SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3SM), uint32_t) & BM_MPU_RGDn_WORD2_M3SM)
bogdanm	82:6473597d706e	916
bogdanm	82:6473597d706e	917	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	918	//! @brief Set the M3SM field to a new value.
bogdanm	82:6473597d706e	919	#define BW_MPU_RGDn_WORD2_M3SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M3SM) \| BF_MPU_RGDn_WORD2_M3SM(v)))
bogdanm	82:6473597d706e	920	#endif
bogdanm	82:6473597d706e	921	//@}
bogdanm	82:6473597d706e	922
bogdanm	82:6473597d706e	923	/*!
bogdanm	82:6473597d706e	924	* @name Register MPU_RGDn_WORD2, field M3PE[23] (RW)
bogdanm	82:6473597d706e	925	*
bogdanm	82:6473597d706e	926	* Values:
bogdanm	82:6473597d706e	927	* - 0 - Do not include the process identifier in the evaluation
bogdanm	82:6473597d706e	928	* - 1 - Include the process identifier and mask (RGDn_WORD3) in the region hit
bogdanm	82:6473597d706e	929	* evaluation
bogdanm	82:6473597d706e	930	*/
bogdanm	82:6473597d706e	931	//@{
bogdanm	82:6473597d706e	932	#define BP_MPU_RGDn_WORD2_M3PE (23U) //!< Bit position for MPU_RGDn_WORD2_M3PE.
bogdanm	82:6473597d706e	933	#define BM_MPU_RGDn_WORD2_M3PE (0x00800000U) //!< Bit mask for MPU_RGDn_WORD2_M3PE.
bogdanm	82:6473597d706e	934	#define BS_MPU_RGDn_WORD2_M3PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M3PE.
bogdanm	82:6473597d706e	935
bogdanm	82:6473597d706e	936	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	937	//! @brief Read current value of the MPU_RGDn_WORD2_M3PE field.
bogdanm	82:6473597d706e	938	#define BR_MPU_RGDn_WORD2_M3PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M3PE))
bogdanm	82:6473597d706e	939	#endif
bogdanm	82:6473597d706e	940
bogdanm	82:6473597d706e	941	//! @brief Format value for bitfield MPU_RGDn_WORD2_M3PE.
bogdanm	82:6473597d706e	942	#define BF_MPU_RGDn_WORD2_M3PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3PE), uint32_t) & BM_MPU_RGDn_WORD2_M3PE)
bogdanm	82:6473597d706e	943
bogdanm	82:6473597d706e	944	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	945	//! @brief Set the M3PE field to a new value.
bogdanm	82:6473597d706e	946	#define BW_MPU_RGDn_WORD2_M3PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M3PE) = (v))
bogdanm	82:6473597d706e	947	#endif
bogdanm	82:6473597d706e	948	//@}
bogdanm	82:6473597d706e	949
bogdanm	82:6473597d706e	950	/*!
bogdanm	82:6473597d706e	951	* @name Register MPU_RGDn_WORD2, field M4WE[24] (RW)
bogdanm	82:6473597d706e	952	*
bogdanm	82:6473597d706e	953	* Values:
bogdanm	82:6473597d706e	954	* - 0 - Bus master 4 writes terminate with an access error and the write is not
bogdanm	82:6473597d706e	955	* performed
bogdanm	82:6473597d706e	956	* - 1 - Bus master 4 writes allowed
bogdanm	82:6473597d706e	957	*/
bogdanm	82:6473597d706e	958	//@{
bogdanm	82:6473597d706e	959	#define BP_MPU_RGDn_WORD2_M4WE (24U) //!< Bit position for MPU_RGDn_WORD2_M4WE.
bogdanm	82:6473597d706e	960	#define BM_MPU_RGDn_WORD2_M4WE (0x01000000U) //!< Bit mask for MPU_RGDn_WORD2_M4WE.
bogdanm	82:6473597d706e	961	#define BS_MPU_RGDn_WORD2_M4WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M4WE.
bogdanm	82:6473597d706e	962
bogdanm	82:6473597d706e	963	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	964	//! @brief Read current value of the MPU_RGDn_WORD2_M4WE field.
bogdanm	82:6473597d706e	965	#define BR_MPU_RGDn_WORD2_M4WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4WE))
bogdanm	82:6473597d706e	966	#endif
bogdanm	82:6473597d706e	967
bogdanm	82:6473597d706e	968	//! @brief Format value for bitfield MPU_RGDn_WORD2_M4WE.
bogdanm	82:6473597d706e	969	#define BF_MPU_RGDn_WORD2_M4WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M4WE), uint32_t) & BM_MPU_RGDn_WORD2_M4WE)
bogdanm	82:6473597d706e	970
bogdanm	82:6473597d706e	971	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	972	//! @brief Set the M4WE field to a new value.
bogdanm	82:6473597d706e	973	#define BW_MPU_RGDn_WORD2_M4WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4WE) = (v))
bogdanm	82:6473597d706e	974	#endif
bogdanm	82:6473597d706e	975	//@}
bogdanm	82:6473597d706e	976
bogdanm	82:6473597d706e	977	/*!
bogdanm	82:6473597d706e	978	* @name Register MPU_RGDn_WORD2, field M4RE[25] (RW)
bogdanm	82:6473597d706e	979	*
bogdanm	82:6473597d706e	980	* Values:
bogdanm	82:6473597d706e	981	* - 0 - Bus master 4 reads terminate with an access error and the read is not
bogdanm	82:6473597d706e	982	* performed
bogdanm	82:6473597d706e	983	* - 1 - Bus master 4 reads allowed
bogdanm	82:6473597d706e	984	*/
bogdanm	82:6473597d706e	985	//@{
bogdanm	82:6473597d706e	986	#define BP_MPU_RGDn_WORD2_M4RE (25U) //!< Bit position for MPU_RGDn_WORD2_M4RE.
bogdanm	82:6473597d706e	987	#define BM_MPU_RGDn_WORD2_M4RE (0x02000000U) //!< Bit mask for MPU_RGDn_WORD2_M4RE.
bogdanm	82:6473597d706e	988	#define BS_MPU_RGDn_WORD2_M4RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M4RE.
bogdanm	82:6473597d706e	989
bogdanm	82:6473597d706e	990	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	991	//! @brief Read current value of the MPU_RGDn_WORD2_M4RE field.
bogdanm	82:6473597d706e	992	#define BR_MPU_RGDn_WORD2_M4RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4RE))
bogdanm	82:6473597d706e	993	#endif
bogdanm	82:6473597d706e	994
bogdanm	82:6473597d706e	995	//! @brief Format value for bitfield MPU_RGDn_WORD2_M4RE.
bogdanm	82:6473597d706e	996	#define BF_MPU_RGDn_WORD2_M4RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M4RE), uint32_t) & BM_MPU_RGDn_WORD2_M4RE)
bogdanm	82:6473597d706e	997
bogdanm	82:6473597d706e	998	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	999	//! @brief Set the M4RE field to a new value.
bogdanm	82:6473597d706e	1000	#define BW_MPU_RGDn_WORD2_M4RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4RE) = (v))
bogdanm	82:6473597d706e	1001	#endif
bogdanm	82:6473597d706e	1002	//@}
bogdanm	82:6473597d706e	1003
bogdanm	82:6473597d706e	1004	/*!
bogdanm	82:6473597d706e	1005	* @name Register MPU_RGDn_WORD2, field M5WE[26] (RW)
bogdanm	82:6473597d706e	1006	*
bogdanm	82:6473597d706e	1007	* Values:
bogdanm	82:6473597d706e	1008	* - 0 - Bus master 5 writes terminate with an access error and the write is not
bogdanm	82:6473597d706e	1009	* performed
bogdanm	82:6473597d706e	1010	* - 1 - Bus master 5 writes allowed
bogdanm	82:6473597d706e	1011	*/
bogdanm	82:6473597d706e	1012	//@{
bogdanm	82:6473597d706e	1013	#define BP_MPU_RGDn_WORD2_M5WE (26U) //!< Bit position for MPU_RGDn_WORD2_M5WE.
bogdanm	82:6473597d706e	1014	#define BM_MPU_RGDn_WORD2_M5WE (0x04000000U) //!< Bit mask for MPU_RGDn_WORD2_M5WE.
bogdanm	82:6473597d706e	1015	#define BS_MPU_RGDn_WORD2_M5WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M5WE.
bogdanm	82:6473597d706e	1016
bogdanm	82:6473597d706e	1017	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1018	//! @brief Read current value of the MPU_RGDn_WORD2_M5WE field.
bogdanm	82:6473597d706e	1019	#define BR_MPU_RGDn_WORD2_M5WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5WE))
bogdanm	82:6473597d706e	1020	#endif
bogdanm	82:6473597d706e	1021
bogdanm	82:6473597d706e	1022	//! @brief Format value for bitfield MPU_RGDn_WORD2_M5WE.
bogdanm	82:6473597d706e	1023	#define BF_MPU_RGDn_WORD2_M5WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M5WE), uint32_t) & BM_MPU_RGDn_WORD2_M5WE)
bogdanm	82:6473597d706e	1024
bogdanm	82:6473597d706e	1025	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1026	//! @brief Set the M5WE field to a new value.
bogdanm	82:6473597d706e	1027	#define BW_MPU_RGDn_WORD2_M5WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5WE) = (v))
bogdanm	82:6473597d706e	1028	#endif
bogdanm	82:6473597d706e	1029	//@}
bogdanm	82:6473597d706e	1030
bogdanm	82:6473597d706e	1031	/*!
bogdanm	82:6473597d706e	1032	* @name Register MPU_RGDn_WORD2, field M5RE[27] (RW)
bogdanm	82:6473597d706e	1033	*
bogdanm	82:6473597d706e	1034	* Values:
bogdanm	82:6473597d706e	1035	* - 0 - Bus master 5 reads terminate with an access error and the read is not
bogdanm	82:6473597d706e	1036	* performed
bogdanm	82:6473597d706e	1037	* - 1 - Bus master 5 reads allowed
bogdanm	82:6473597d706e	1038	*/
bogdanm	82:6473597d706e	1039	//@{
bogdanm	82:6473597d706e	1040	#define BP_MPU_RGDn_WORD2_M5RE (27U) //!< Bit position for MPU_RGDn_WORD2_M5RE.
bogdanm	82:6473597d706e	1041	#define BM_MPU_RGDn_WORD2_M5RE (0x08000000U) //!< Bit mask for MPU_RGDn_WORD2_M5RE.
bogdanm	82:6473597d706e	1042	#define BS_MPU_RGDn_WORD2_M5RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M5RE.
bogdanm	82:6473597d706e	1043
bogdanm	82:6473597d706e	1044	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1045	//! @brief Read current value of the MPU_RGDn_WORD2_M5RE field.
bogdanm	82:6473597d706e	1046	#define BR_MPU_RGDn_WORD2_M5RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5RE))
bogdanm	82:6473597d706e	1047	#endif
bogdanm	82:6473597d706e	1048
bogdanm	82:6473597d706e	1049	//! @brief Format value for bitfield MPU_RGDn_WORD2_M5RE.
bogdanm	82:6473597d706e	1050	#define BF_MPU_RGDn_WORD2_M5RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M5RE), uint32_t) & BM_MPU_RGDn_WORD2_M5RE)
bogdanm	82:6473597d706e	1051
bogdanm	82:6473597d706e	1052	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1053	//! @brief Set the M5RE field to a new value.
bogdanm	82:6473597d706e	1054	#define BW_MPU_RGDn_WORD2_M5RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5RE) = (v))
bogdanm	82:6473597d706e	1055	#endif
bogdanm	82:6473597d706e	1056	//@}
bogdanm	82:6473597d706e	1057
bogdanm	82:6473597d706e	1058	/*!
bogdanm	82:6473597d706e	1059	* @name Register MPU_RGDn_WORD2, field M6WE[28] (RW)
bogdanm	82:6473597d706e	1060	*
bogdanm	82:6473597d706e	1061	* Values:
bogdanm	82:6473597d706e	1062	* - 0 - Bus master 6 writes terminate with an access error and the write is not
bogdanm	82:6473597d706e	1063	* performed
bogdanm	82:6473597d706e	1064	* - 1 - Bus master 6 writes allowed
bogdanm	82:6473597d706e	1065	*/
bogdanm	82:6473597d706e	1066	//@{
bogdanm	82:6473597d706e	1067	#define BP_MPU_RGDn_WORD2_M6WE (28U) //!< Bit position for MPU_RGDn_WORD2_M6WE.
bogdanm	82:6473597d706e	1068	#define BM_MPU_RGDn_WORD2_M6WE (0x10000000U) //!< Bit mask for MPU_RGDn_WORD2_M6WE.
bogdanm	82:6473597d706e	1069	#define BS_MPU_RGDn_WORD2_M6WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M6WE.
bogdanm	82:6473597d706e	1070
bogdanm	82:6473597d706e	1071	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1072	//! @brief Read current value of the MPU_RGDn_WORD2_M6WE field.
bogdanm	82:6473597d706e	1073	#define BR_MPU_RGDn_WORD2_M6WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6WE))
bogdanm	82:6473597d706e	1074	#endif
bogdanm	82:6473597d706e	1075
bogdanm	82:6473597d706e	1076	//! @brief Format value for bitfield MPU_RGDn_WORD2_M6WE.
bogdanm	82:6473597d706e	1077	#define BF_MPU_RGDn_WORD2_M6WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M6WE), uint32_t) & BM_MPU_RGDn_WORD2_M6WE)
bogdanm	82:6473597d706e	1078
bogdanm	82:6473597d706e	1079	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1080	//! @brief Set the M6WE field to a new value.
bogdanm	82:6473597d706e	1081	#define BW_MPU_RGDn_WORD2_M6WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6WE) = (v))
bogdanm	82:6473597d706e	1082	#endif
bogdanm	82:6473597d706e	1083	//@}
bogdanm	82:6473597d706e	1084
bogdanm	82:6473597d706e	1085	/*!
bogdanm	82:6473597d706e	1086	* @name Register MPU_RGDn_WORD2, field M6RE[29] (RW)
bogdanm	82:6473597d706e	1087	*
bogdanm	82:6473597d706e	1088	* Values:
bogdanm	82:6473597d706e	1089	* - 0 - Bus master 6 reads terminate with an access error and the read is not
bogdanm	82:6473597d706e	1090	* performed
bogdanm	82:6473597d706e	1091	* - 1 - Bus master 6 reads allowed
bogdanm	82:6473597d706e	1092	*/
bogdanm	82:6473597d706e	1093	//@{
bogdanm	82:6473597d706e	1094	#define BP_MPU_RGDn_WORD2_M6RE (29U) //!< Bit position for MPU_RGDn_WORD2_M6RE.
bogdanm	82:6473597d706e	1095	#define BM_MPU_RGDn_WORD2_M6RE (0x20000000U) //!< Bit mask for MPU_RGDn_WORD2_M6RE.
bogdanm	82:6473597d706e	1096	#define BS_MPU_RGDn_WORD2_M6RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M6RE.
bogdanm	82:6473597d706e	1097
bogdanm	82:6473597d706e	1098	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1099	//! @brief Read current value of the MPU_RGDn_WORD2_M6RE field.
bogdanm	82:6473597d706e	1100	#define BR_MPU_RGDn_WORD2_M6RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6RE))
bogdanm	82:6473597d706e	1101	#endif
bogdanm	82:6473597d706e	1102
bogdanm	82:6473597d706e	1103	//! @brief Format value for bitfield MPU_RGDn_WORD2_M6RE.
bogdanm	82:6473597d706e	1104	#define BF_MPU_RGDn_WORD2_M6RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M6RE), uint32_t) & BM_MPU_RGDn_WORD2_M6RE)
bogdanm	82:6473597d706e	1105
bogdanm	82:6473597d706e	1106	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1107	//! @brief Set the M6RE field to a new value.
bogdanm	82:6473597d706e	1108	#define BW_MPU_RGDn_WORD2_M6RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6RE) = (v))
bogdanm	82:6473597d706e	1109	#endif
bogdanm	82:6473597d706e	1110	//@}
bogdanm	82:6473597d706e	1111
bogdanm	82:6473597d706e	1112	/*!
bogdanm	82:6473597d706e	1113	* @name Register MPU_RGDn_WORD2, field M7WE[30] (RW)
bogdanm	82:6473597d706e	1114	*
bogdanm	82:6473597d706e	1115	* Values:
bogdanm	82:6473597d706e	1116	* - 0 - Bus master 7 writes terminate with an access error and the write is not
bogdanm	82:6473597d706e	1117	* performed
bogdanm	82:6473597d706e	1118	* - 1 - Bus master 7 writes allowed
bogdanm	82:6473597d706e	1119	*/
bogdanm	82:6473597d706e	1120	//@{
bogdanm	82:6473597d706e	1121	#define BP_MPU_RGDn_WORD2_M7WE (30U) //!< Bit position for MPU_RGDn_WORD2_M7WE.
bogdanm	82:6473597d706e	1122	#define BM_MPU_RGDn_WORD2_M7WE (0x40000000U) //!< Bit mask for MPU_RGDn_WORD2_M7WE.
bogdanm	82:6473597d706e	1123	#define BS_MPU_RGDn_WORD2_M7WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M7WE.
bogdanm	82:6473597d706e	1124
bogdanm	82:6473597d706e	1125	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1126	//! @brief Read current value of the MPU_RGDn_WORD2_M7WE field.
bogdanm	82:6473597d706e	1127	#define BR_MPU_RGDn_WORD2_M7WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7WE))
bogdanm	82:6473597d706e	1128	#endif
bogdanm	82:6473597d706e	1129
bogdanm	82:6473597d706e	1130	//! @brief Format value for bitfield MPU_RGDn_WORD2_M7WE.
bogdanm	82:6473597d706e	1131	#define BF_MPU_RGDn_WORD2_M7WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M7WE), uint32_t) & BM_MPU_RGDn_WORD2_M7WE)
bogdanm	82:6473597d706e	1132
bogdanm	82:6473597d706e	1133	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1134	//! @brief Set the M7WE field to a new value.
bogdanm	82:6473597d706e	1135	#define BW_MPU_RGDn_WORD2_M7WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7WE) = (v))
bogdanm	82:6473597d706e	1136	#endif
bogdanm	82:6473597d706e	1137	//@}
bogdanm	82:6473597d706e	1138
bogdanm	82:6473597d706e	1139	/*!
bogdanm	82:6473597d706e	1140	* @name Register MPU_RGDn_WORD2, field M7RE[31] (RW)
bogdanm	82:6473597d706e	1141	*
bogdanm	82:6473597d706e	1142	* Values:
bogdanm	82:6473597d706e	1143	* - 0 - Bus master 7 reads terminate with an access error and the read is not
bogdanm	82:6473597d706e	1144	* performed
bogdanm	82:6473597d706e	1145	* - 1 - Bus master 7 reads allowed
bogdanm	82:6473597d706e	1146	*/
bogdanm	82:6473597d706e	1147	//@{
bogdanm	82:6473597d706e	1148	#define BP_MPU_RGDn_WORD2_M7RE (31U) //!< Bit position for MPU_RGDn_WORD2_M7RE.
bogdanm	82:6473597d706e	1149	#define BM_MPU_RGDn_WORD2_M7RE (0x80000000U) //!< Bit mask for MPU_RGDn_WORD2_M7RE.
bogdanm	82:6473597d706e	1150	#define BS_MPU_RGDn_WORD2_M7RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M7RE.
bogdanm	82:6473597d706e	1151
bogdanm	82:6473597d706e	1152	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1153	//! @brief Read current value of the MPU_RGDn_WORD2_M7RE field.
bogdanm	82:6473597d706e	1154	#define BR_MPU_RGDn_WORD2_M7RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7RE))
bogdanm	82:6473597d706e	1155	#endif
bogdanm	82:6473597d706e	1156
bogdanm	82:6473597d706e	1157	//! @brief Format value for bitfield MPU_RGDn_WORD2_M7RE.
bogdanm	82:6473597d706e	1158	#define BF_MPU_RGDn_WORD2_M7RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M7RE), uint32_t) & BM_MPU_RGDn_WORD2_M7RE)
bogdanm	82:6473597d706e	1159
bogdanm	82:6473597d706e	1160	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1161	//! @brief Set the M7RE field to a new value.
bogdanm	82:6473597d706e	1162	#define BW_MPU_RGDn_WORD2_M7RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7RE) = (v))
bogdanm	82:6473597d706e	1163	#endif
bogdanm	82:6473597d706e	1164	//@}
bogdanm	82:6473597d706e	1165	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1166	// HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3
bogdanm	82:6473597d706e	1167	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1168
bogdanm	82:6473597d706e	1169	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1170	/*!
bogdanm	82:6473597d706e	1171	* @brief HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3 (RW)
bogdanm	82:6473597d706e	1172	*
bogdanm	82:6473597d706e	1173	* Reset value: 0x00000001U
bogdanm	82:6473597d706e	1174	*
bogdanm	82:6473597d706e	1175	* The fourth word of the region descriptor contains the optional process
bogdanm	82:6473597d706e	1176	* identifier and mask, plus the region descriptor's valid bit.
bogdanm	82:6473597d706e	1177	*/
bogdanm	82:6473597d706e	1178	typedef union _hw_mpu_rgdn_word3
bogdanm	82:6473597d706e	1179	{
bogdanm	82:6473597d706e	1180	uint32_t U;
bogdanm	82:6473597d706e	1181	struct _hw_mpu_rgdn_word3_bitfields
bogdanm	82:6473597d706e	1182	{
bogdanm	82:6473597d706e	1183	uint32_t VLD : 1; //!< [0] Valid
bogdanm	82:6473597d706e	1184	uint32_t RESERVED0 : 15; //!< [15:1]
bogdanm	82:6473597d706e	1185	uint32_t PIDMASK : 8; //!< [23:16] Process Identifier Mask
bogdanm	82:6473597d706e	1186	uint32_t PID : 8; //!< [31:24] Process Identifier
bogdanm	82:6473597d706e	1187	} B;
bogdanm	82:6473597d706e	1188	} hw_mpu_rgdn_word3_t;
bogdanm	82:6473597d706e	1189	#endif
bogdanm	82:6473597d706e	1190
bogdanm	82:6473597d706e	1191	/*!
bogdanm	82:6473597d706e	1192	* @name Constants and macros for entire MPU_RGDn_WORD3 register
bogdanm	82:6473597d706e	1193	*/
bogdanm	82:6473597d706e	1194	//@{
bogdanm	82:6473597d706e	1195	#define HW_MPU_RGDn_WORD3_COUNT (12U)
bogdanm	82:6473597d706e	1196
bogdanm	82:6473597d706e	1197	#define HW_MPU_RGDn_WORD3_ADDR(n) (REGS_MPU_BASE + 0x40CU + (0x10U * n))
bogdanm	82:6473597d706e	1198
bogdanm	82:6473597d706e	1199	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1200	#define HW_MPU_RGDn_WORD3(n) ((__IO hw_mpu_rgdn_word3_t ) HW_MPU_RGDn_WORD3_ADDR(n))
bogdanm	82:6473597d706e	1201	#define HW_MPU_RGDn_WORD3_RD(n) (HW_MPU_RGDn_WORD3(n).U)
bogdanm	82:6473597d706e	1202	#define HW_MPU_RGDn_WORD3_WR(n, v) (HW_MPU_RGDn_WORD3(n).U = (v))
bogdanm	82:6473597d706e	1203	#define HW_MPU_RGDn_WORD3_SET(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) \| (v)))
bogdanm	82:6473597d706e	1204	#define HW_MPU_RGDn_WORD3_CLR(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1205	#define HW_MPU_RGDn_WORD3_TOG(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1206	#endif
bogdanm	82:6473597d706e	1207	//@}
bogdanm	82:6473597d706e	1208
bogdanm	82:6473597d706e	1209	/*
bogdanm	82:6473597d706e	1210	* Constants & macros for individual MPU_RGDn_WORD3 bitfields
bogdanm	82:6473597d706e	1211	*/
bogdanm	82:6473597d706e	1212
bogdanm	82:6473597d706e	1213	/*!
bogdanm	82:6473597d706e	1214	* @name Register MPU_RGDn_WORD3, field VLD[0] (RW)
bogdanm	82:6473597d706e	1215	*
bogdanm	82:6473597d706e	1216	* Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this
bogdanm	82:6473597d706e	1217	* bit.
bogdanm	82:6473597d706e	1218	*
bogdanm	82:6473597d706e	1219	* Values:
bogdanm	82:6473597d706e	1220	* - 0 - Region descriptor is invalid
bogdanm	82:6473597d706e	1221	* - 1 - Region descriptor is valid
bogdanm	82:6473597d706e	1222	*/
bogdanm	82:6473597d706e	1223	//@{
bogdanm	82:6473597d706e	1224	#define BP_MPU_RGDn_WORD3_VLD (0U) //!< Bit position for MPU_RGDn_WORD3_VLD.
bogdanm	82:6473597d706e	1225	#define BM_MPU_RGDn_WORD3_VLD (0x00000001U) //!< Bit mask for MPU_RGDn_WORD3_VLD.
bogdanm	82:6473597d706e	1226	#define BS_MPU_RGDn_WORD3_VLD (1U) //!< Bit field size in bits for MPU_RGDn_WORD3_VLD.
bogdanm	82:6473597d706e	1227
bogdanm	82:6473597d706e	1228	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1229	//! @brief Read current value of the MPU_RGDn_WORD3_VLD field.
bogdanm	82:6473597d706e	1230	#define BR_MPU_RGDn_WORD3_VLD(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(n), BP_MPU_RGDn_WORD3_VLD))
bogdanm	82:6473597d706e	1231	#endif
bogdanm	82:6473597d706e	1232
bogdanm	82:6473597d706e	1233	//! @brief Format value for bitfield MPU_RGDn_WORD3_VLD.
bogdanm	82:6473597d706e	1234	#define BF_MPU_RGDn_WORD3_VLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_VLD), uint32_t) & BM_MPU_RGDn_WORD3_VLD)
bogdanm	82:6473597d706e	1235
bogdanm	82:6473597d706e	1236	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1237	//! @brief Set the VLD field to a new value.
bogdanm	82:6473597d706e	1238	#define BW_MPU_RGDn_WORD3_VLD(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(n), BP_MPU_RGDn_WORD3_VLD) = (v))
bogdanm	82:6473597d706e	1239	#endif
bogdanm	82:6473597d706e	1240	//@}
bogdanm	82:6473597d706e	1241
bogdanm	82:6473597d706e	1242	/*!
bogdanm	82:6473597d706e	1243	* @name Register MPU_RGDn_WORD3, field PIDMASK[23:16] (RW)
bogdanm	82:6473597d706e	1244	*
bogdanm	82:6473597d706e	1245	* Provides a masking capability so that multiple process identifiers can be
bogdanm	82:6473597d706e	1246	* included as part of the region hit determination. If a bit in PIDMASK is set,
bogdanm	82:6473597d706e	1247	* then the corresponding PID bit is ignored in the comparison. This field and PID
bogdanm	82:6473597d706e	1248	* are included in the region hit determination if RGDn_WORD2[MxPE] is set. For
bogdanm	82:6473597d706e	1249	* more information on the handling of the PID and PIDMASK, see "Access Evaluation
bogdanm	82:6473597d706e	1250	* - Hit Determination."
bogdanm	82:6473597d706e	1251	*/
bogdanm	82:6473597d706e	1252	//@{
bogdanm	82:6473597d706e	1253	#define BP_MPU_RGDn_WORD3_PIDMASK (16U) //!< Bit position for MPU_RGDn_WORD3_PIDMASK.
bogdanm	82:6473597d706e	1254	#define BM_MPU_RGDn_WORD3_PIDMASK (0x00FF0000U) //!< Bit mask for MPU_RGDn_WORD3_PIDMASK.
bogdanm	82:6473597d706e	1255	#define BS_MPU_RGDn_WORD3_PIDMASK (8U) //!< Bit field size in bits for MPU_RGDn_WORD3_PIDMASK.
bogdanm	82:6473597d706e	1256
bogdanm	82:6473597d706e	1257	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1258	//! @brief Read current value of the MPU_RGDn_WORD3_PIDMASK field.
bogdanm	82:6473597d706e	1259	#define BR_MPU_RGDn_WORD3_PIDMASK(n) (HW_MPU_RGDn_WORD3(n).B.PIDMASK)
bogdanm	82:6473597d706e	1260	#endif
bogdanm	82:6473597d706e	1261
bogdanm	82:6473597d706e	1262	//! @brief Format value for bitfield MPU_RGDn_WORD3_PIDMASK.
bogdanm	82:6473597d706e	1263	#define BF_MPU_RGDn_WORD3_PIDMASK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_PIDMASK), uint32_t) & BM_MPU_RGDn_WORD3_PIDMASK)
bogdanm	82:6473597d706e	1264
bogdanm	82:6473597d706e	1265	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1266	//! @brief Set the PIDMASK field to a new value.
bogdanm	82:6473597d706e	1267	#define BW_MPU_RGDn_WORD3_PIDMASK(n, v) (HW_MPU_RGDn_WORD3_WR(n, (HW_MPU_RGDn_WORD3_RD(n) & ~BM_MPU_RGDn_WORD3_PIDMASK) \| BF_MPU_RGDn_WORD3_PIDMASK(v)))
bogdanm	82:6473597d706e	1268	#endif
bogdanm	82:6473597d706e	1269	//@}
bogdanm	82:6473597d706e	1270
bogdanm	82:6473597d706e	1271	/*!
bogdanm	82:6473597d706e	1272	* @name Register MPU_RGDn_WORD3, field PID[31:24] (RW)
bogdanm	82:6473597d706e	1273	*
bogdanm	82:6473597d706e	1274	* Specifies the process identifier that is included in the region hit
bogdanm	82:6473597d706e	1275	* determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this
bogdanm	82:6473597d706e	1276	* field.
bogdanm	82:6473597d706e	1277	*/
bogdanm	82:6473597d706e	1278	//@{
bogdanm	82:6473597d706e	1279	#define BP_MPU_RGDn_WORD3_PID (24U) //!< Bit position for MPU_RGDn_WORD3_PID.
bogdanm	82:6473597d706e	1280	#define BM_MPU_RGDn_WORD3_PID (0xFF000000U) //!< Bit mask for MPU_RGDn_WORD3_PID.
bogdanm	82:6473597d706e	1281	#define BS_MPU_RGDn_WORD3_PID (8U) //!< Bit field size in bits for MPU_RGDn_WORD3_PID.
bogdanm	82:6473597d706e	1282
bogdanm	82:6473597d706e	1283	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1284	//! @brief Read current value of the MPU_RGDn_WORD3_PID field.
bogdanm	82:6473597d706e	1285	#define BR_MPU_RGDn_WORD3_PID(n) (HW_MPU_RGDn_WORD3(n).B.PID)
bogdanm	82:6473597d706e	1286	#endif
bogdanm	82:6473597d706e	1287
bogdanm	82:6473597d706e	1288	//! @brief Format value for bitfield MPU_RGDn_WORD3_PID.
bogdanm	82:6473597d706e	1289	#define BF_MPU_RGDn_WORD3_PID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_PID), uint32_t) & BM_MPU_RGDn_WORD3_PID)
bogdanm	82:6473597d706e	1290
bogdanm	82:6473597d706e	1291	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1292	//! @brief Set the PID field to a new value.
bogdanm	82:6473597d706e	1293	#define BW_MPU_RGDn_WORD3_PID(n, v) (HW_MPU_RGDn_WORD3_WR(n, (HW_MPU_RGDn_WORD3_RD(n) & ~BM_MPU_RGDn_WORD3_PID) \| BF_MPU_RGDn_WORD3_PID(v)))
bogdanm	82:6473597d706e	1294	#endif
bogdanm	82:6473597d706e	1295	//@}
bogdanm	82:6473597d706e	1296
bogdanm	82:6473597d706e	1297	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1298	// HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n
bogdanm	82:6473597d706e	1299	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1300
bogdanm	82:6473597d706e	1301	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1302	/*!
bogdanm	82:6473597d706e	1303	* @brief HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n (RW)
bogdanm	82:6473597d706e	1304	*
bogdanm	82:6473597d706e	1305	* Reset value: 0x0061F7DFU
bogdanm	82:6473597d706e	1306	*
bogdanm	82:6473597d706e	1307	* Because software may adjust only the access controls within a region
bogdanm	82:6473597d706e	1308	* descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of
bogdanm	82:6473597d706e	1309	* this 32-bit entity is available. Writing to this register does not affect the
bogdanm	82:6473597d706e	1310	* descriptor's valid bit.
bogdanm	82:6473597d706e	1311	*/
bogdanm	82:6473597d706e	1312	typedef union _hw_mpu_rgdaacn
bogdanm	82:6473597d706e	1313	{
bogdanm	82:6473597d706e	1314	uint32_t U;
bogdanm	82:6473597d706e	1315	struct _hw_mpu_rgdaacn_bitfields
bogdanm	82:6473597d706e	1316	{
bogdanm	82:6473597d706e	1317	uint32_t M0UM : 3; //!< [2:0] Bus Master 0 User Mode Access Control
bogdanm	82:6473597d706e	1318	uint32_t M0SM : 2; //!< [4:3] Bus Master 0 Supervisor Mode Access
bogdanm	82:6473597d706e	1319	//! Control
bogdanm	82:6473597d706e	1320	uint32_t M0PE : 1; //!< [5] Bus Master 0 Process Identifier Enable
bogdanm	82:6473597d706e	1321	uint32_t M1UM : 3; //!< [8:6] Bus Master 1 User Mode Access Control
bogdanm	82:6473597d706e	1322	uint32_t M1SM : 2; //!< [10:9] Bus Master 1 Supervisor Mode Access
bogdanm	82:6473597d706e	1323	//! Control
bogdanm	82:6473597d706e	1324	uint32_t M1PE : 1; //!< [11] Bus Master 1 Process Identifier Enable
bogdanm	82:6473597d706e	1325	uint32_t M2UM : 3; //!< [14:12] Bus Master 2 User Mode Access Control
bogdanm	82:6473597d706e	1326	uint32_t M2SM : 2; //!< [16:15] Bus Master 2 Supervisor Mode Access
bogdanm	82:6473597d706e	1327	//! Control
bogdanm	82:6473597d706e	1328	uint32_t M2PE : 1; //!< [17] Bus Master 2 Process Identifier Enable
bogdanm	82:6473597d706e	1329	uint32_t M3UM : 3; //!< [20:18] Bus Master 3 User Mode Access Control
bogdanm	82:6473597d706e	1330	uint32_t M3SM : 2; //!< [22:21] Bus Master 3 Supervisor Mode Access
bogdanm	82:6473597d706e	1331	//! Control
bogdanm	82:6473597d706e	1332	uint32_t M3PE : 1; //!< [23] Bus Master 3 Process Identifier Enable
bogdanm	82:6473597d706e	1333	uint32_t M4WE : 1; //!< [24] Bus Master 4 Write Enable
bogdanm	82:6473597d706e	1334	uint32_t M4RE : 1; //!< [25] Bus Master 4 Read Enable
bogdanm	82:6473597d706e	1335	uint32_t M5WE : 1; //!< [26] Bus Master 5 Write Enable
bogdanm	82:6473597d706e	1336	uint32_t M5RE : 1; //!< [27] Bus Master 5 Read Enable
bogdanm	82:6473597d706e	1337	uint32_t M6WE : 1; //!< [28] Bus Master 6 Write Enable
bogdanm	82:6473597d706e	1338	uint32_t M6RE : 1; //!< [29] Bus Master 6 Read Enable
bogdanm	82:6473597d706e	1339	uint32_t M7WE : 1; //!< [30] Bus Master 7 Write Enable
bogdanm	82:6473597d706e	1340	uint32_t M7RE : 1; //!< [31] Bus Master 7 Read Enable
bogdanm	82:6473597d706e	1341	} B;
bogdanm	82:6473597d706e	1342	} hw_mpu_rgdaacn_t;
bogdanm	82:6473597d706e	1343	#endif
bogdanm	82:6473597d706e	1344
bogdanm	82:6473597d706e	1345	/*!
bogdanm	82:6473597d706e	1346	* @name Constants and macros for entire MPU_RGDAACn register
bogdanm	82:6473597d706e	1347	*/
bogdanm	82:6473597d706e	1348	//@{
bogdanm	82:6473597d706e	1349	#define HW_MPU_RGDAACn_COUNT (12U)
bogdanm	82:6473597d706e	1350
bogdanm	82:6473597d706e	1351	#define HW_MPU_RGDAACn_ADDR(n) (REGS_MPU_BASE + 0x800U + (0x4U * n))
bogdanm	82:6473597d706e	1352
bogdanm	82:6473597d706e	1353	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1354	#define HW_MPU_RGDAACn(n) ((__IO hw_mpu_rgdaacn_t ) HW_MPU_RGDAACn_ADDR(n))
bogdanm	82:6473597d706e	1355	#define HW_MPU_RGDAACn_RD(n) (HW_MPU_RGDAACn(n).U)
bogdanm	82:6473597d706e	1356	#define HW_MPU_RGDAACn_WR(n, v) (HW_MPU_RGDAACn(n).U = (v))
bogdanm	82:6473597d706e	1357	#define HW_MPU_RGDAACn_SET(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) \| (v)))
bogdanm	82:6473597d706e	1358	#define HW_MPU_RGDAACn_CLR(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1359	#define HW_MPU_RGDAACn_TOG(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1360	#endif
bogdanm	82:6473597d706e	1361	//@}
bogdanm	82:6473597d706e	1362
bogdanm	82:6473597d706e	1363	/*
bogdanm	82:6473597d706e	1364	* Constants & macros for individual MPU_RGDAACn bitfields
bogdanm	82:6473597d706e	1365	*/
bogdanm	82:6473597d706e	1366
bogdanm	82:6473597d706e	1367	/*!
bogdanm	82:6473597d706e	1368	* @name Register MPU_RGDAACn, field M0UM[2:0] (RW)
bogdanm	82:6473597d706e	1369	*
bogdanm	82:6473597d706e	1370	* See M3UM description.
bogdanm	82:6473597d706e	1371	*/
bogdanm	82:6473597d706e	1372	//@{
bogdanm	82:6473597d706e	1373	#define BP_MPU_RGDAACn_M0UM (0U) //!< Bit position for MPU_RGDAACn_M0UM.
bogdanm	82:6473597d706e	1374	#define BM_MPU_RGDAACn_M0UM (0x00000007U) //!< Bit mask for MPU_RGDAACn_M0UM.
bogdanm	82:6473597d706e	1375	#define BS_MPU_RGDAACn_M0UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M0UM.
bogdanm	82:6473597d706e	1376
bogdanm	82:6473597d706e	1377	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1378	//! @brief Read current value of the MPU_RGDAACn_M0UM field.
bogdanm	82:6473597d706e	1379	#define BR_MPU_RGDAACn_M0UM(n) (HW_MPU_RGDAACn(n).B.M0UM)
bogdanm	82:6473597d706e	1380	#endif
bogdanm	82:6473597d706e	1381
bogdanm	82:6473597d706e	1382	//! @brief Format value for bitfield MPU_RGDAACn_M0UM.
bogdanm	82:6473597d706e	1383	#define BF_MPU_RGDAACn_M0UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0UM), uint32_t) & BM_MPU_RGDAACn_M0UM)
bogdanm	82:6473597d706e	1384
bogdanm	82:6473597d706e	1385	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1386	//! @brief Set the M0UM field to a new value.
bogdanm	82:6473597d706e	1387	#define BW_MPU_RGDAACn_M0UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M0UM) \| BF_MPU_RGDAACn_M0UM(v)))
bogdanm	82:6473597d706e	1388	#endif
bogdanm	82:6473597d706e	1389	//@}
bogdanm	82:6473597d706e	1390
bogdanm	82:6473597d706e	1391	/*!
bogdanm	82:6473597d706e	1392	* @name Register MPU_RGDAACn, field M0SM[4:3] (RW)
bogdanm	82:6473597d706e	1393	*
bogdanm	82:6473597d706e	1394	* See M3SM description.
bogdanm	82:6473597d706e	1395	*/
bogdanm	82:6473597d706e	1396	//@{
bogdanm	82:6473597d706e	1397	#define BP_MPU_RGDAACn_M0SM (3U) //!< Bit position for MPU_RGDAACn_M0SM.
bogdanm	82:6473597d706e	1398	#define BM_MPU_RGDAACn_M0SM (0x00000018U) //!< Bit mask for MPU_RGDAACn_M0SM.
bogdanm	82:6473597d706e	1399	#define BS_MPU_RGDAACn_M0SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M0SM.
bogdanm	82:6473597d706e	1400
bogdanm	82:6473597d706e	1401	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1402	//! @brief Read current value of the MPU_RGDAACn_M0SM field.
bogdanm	82:6473597d706e	1403	#define BR_MPU_RGDAACn_M0SM(n) (HW_MPU_RGDAACn(n).B.M0SM)
bogdanm	82:6473597d706e	1404	#endif
bogdanm	82:6473597d706e	1405
bogdanm	82:6473597d706e	1406	//! @brief Format value for bitfield MPU_RGDAACn_M0SM.
bogdanm	82:6473597d706e	1407	#define BF_MPU_RGDAACn_M0SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0SM), uint32_t) & BM_MPU_RGDAACn_M0SM)
bogdanm	82:6473597d706e	1408
bogdanm	82:6473597d706e	1409	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1410	//! @brief Set the M0SM field to a new value.
bogdanm	82:6473597d706e	1411	#define BW_MPU_RGDAACn_M0SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M0SM) \| BF_MPU_RGDAACn_M0SM(v)))
bogdanm	82:6473597d706e	1412	#endif
bogdanm	82:6473597d706e	1413	//@}
bogdanm	82:6473597d706e	1414
bogdanm	82:6473597d706e	1415	/*!
bogdanm	82:6473597d706e	1416	* @name Register MPU_RGDAACn, field M0PE[5] (RW)
bogdanm	82:6473597d706e	1417	*
bogdanm	82:6473597d706e	1418	* See M3PE description.
bogdanm	82:6473597d706e	1419	*/
bogdanm	82:6473597d706e	1420	//@{
bogdanm	82:6473597d706e	1421	#define BP_MPU_RGDAACn_M0PE (5U) //!< Bit position for MPU_RGDAACn_M0PE.
bogdanm	82:6473597d706e	1422	#define BM_MPU_RGDAACn_M0PE (0x00000020U) //!< Bit mask for MPU_RGDAACn_M0PE.
bogdanm	82:6473597d706e	1423	#define BS_MPU_RGDAACn_M0PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M0PE.
bogdanm	82:6473597d706e	1424
bogdanm	82:6473597d706e	1425	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1426	//! @brief Read current value of the MPU_RGDAACn_M0PE field.
bogdanm	82:6473597d706e	1427	#define BR_MPU_RGDAACn_M0PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M0PE))
bogdanm	82:6473597d706e	1428	#endif
bogdanm	82:6473597d706e	1429
bogdanm	82:6473597d706e	1430	//! @brief Format value for bitfield MPU_RGDAACn_M0PE.
bogdanm	82:6473597d706e	1431	#define BF_MPU_RGDAACn_M0PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0PE), uint32_t) & BM_MPU_RGDAACn_M0PE)
bogdanm	82:6473597d706e	1432
bogdanm	82:6473597d706e	1433	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1434	//! @brief Set the M0PE field to a new value.
bogdanm	82:6473597d706e	1435	#define BW_MPU_RGDAACn_M0PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M0PE) = (v))
bogdanm	82:6473597d706e	1436	#endif
bogdanm	82:6473597d706e	1437	//@}
bogdanm	82:6473597d706e	1438
bogdanm	82:6473597d706e	1439	/*!
bogdanm	82:6473597d706e	1440	* @name Register MPU_RGDAACn, field M1UM[8:6] (RW)
bogdanm	82:6473597d706e	1441	*
bogdanm	82:6473597d706e	1442	* See M3UM description.
bogdanm	82:6473597d706e	1443	*/
bogdanm	82:6473597d706e	1444	//@{
bogdanm	82:6473597d706e	1445	#define BP_MPU_RGDAACn_M1UM (6U) //!< Bit position for MPU_RGDAACn_M1UM.
bogdanm	82:6473597d706e	1446	#define BM_MPU_RGDAACn_M1UM (0x000001C0U) //!< Bit mask for MPU_RGDAACn_M1UM.
bogdanm	82:6473597d706e	1447	#define BS_MPU_RGDAACn_M1UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M1UM.
bogdanm	82:6473597d706e	1448
bogdanm	82:6473597d706e	1449	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1450	//! @brief Read current value of the MPU_RGDAACn_M1UM field.
bogdanm	82:6473597d706e	1451	#define BR_MPU_RGDAACn_M1UM(n) (HW_MPU_RGDAACn(n).B.M1UM)
bogdanm	82:6473597d706e	1452	#endif
bogdanm	82:6473597d706e	1453
bogdanm	82:6473597d706e	1454	//! @brief Format value for bitfield MPU_RGDAACn_M1UM.
bogdanm	82:6473597d706e	1455	#define BF_MPU_RGDAACn_M1UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1UM), uint32_t) & BM_MPU_RGDAACn_M1UM)
bogdanm	82:6473597d706e	1456
bogdanm	82:6473597d706e	1457	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1458	//! @brief Set the M1UM field to a new value.
bogdanm	82:6473597d706e	1459	#define BW_MPU_RGDAACn_M1UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M1UM) \| BF_MPU_RGDAACn_M1UM(v)))
bogdanm	82:6473597d706e	1460	#endif
bogdanm	82:6473597d706e	1461	//@}
bogdanm	82:6473597d706e	1462
bogdanm	82:6473597d706e	1463	/*!
bogdanm	82:6473597d706e	1464	* @name Register MPU_RGDAACn, field M1SM[10:9] (RW)
bogdanm	82:6473597d706e	1465	*
bogdanm	82:6473597d706e	1466	* See M3SM description.
bogdanm	82:6473597d706e	1467	*/
bogdanm	82:6473597d706e	1468	//@{
bogdanm	82:6473597d706e	1469	#define BP_MPU_RGDAACn_M1SM (9U) //!< Bit position for MPU_RGDAACn_M1SM.
bogdanm	82:6473597d706e	1470	#define BM_MPU_RGDAACn_M1SM (0x00000600U) //!< Bit mask for MPU_RGDAACn_M1SM.
bogdanm	82:6473597d706e	1471	#define BS_MPU_RGDAACn_M1SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M1SM.
bogdanm	82:6473597d706e	1472
bogdanm	82:6473597d706e	1473	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1474	//! @brief Read current value of the MPU_RGDAACn_M1SM field.
bogdanm	82:6473597d706e	1475	#define BR_MPU_RGDAACn_M1SM(n) (HW_MPU_RGDAACn(n).B.M1SM)
bogdanm	82:6473597d706e	1476	#endif
bogdanm	82:6473597d706e	1477
bogdanm	82:6473597d706e	1478	//! @brief Format value for bitfield MPU_RGDAACn_M1SM.
bogdanm	82:6473597d706e	1479	#define BF_MPU_RGDAACn_M1SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1SM), uint32_t) & BM_MPU_RGDAACn_M1SM)
bogdanm	82:6473597d706e	1480
bogdanm	82:6473597d706e	1481	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1482	//! @brief Set the M1SM field to a new value.
bogdanm	82:6473597d706e	1483	#define BW_MPU_RGDAACn_M1SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M1SM) \| BF_MPU_RGDAACn_M1SM(v)))
bogdanm	82:6473597d706e	1484	#endif
bogdanm	82:6473597d706e	1485	//@}
bogdanm	82:6473597d706e	1486
bogdanm	82:6473597d706e	1487	/*!
bogdanm	82:6473597d706e	1488	* @name Register MPU_RGDAACn, field M1PE[11] (RW)
bogdanm	82:6473597d706e	1489	*
bogdanm	82:6473597d706e	1490	* See M3PE description.
bogdanm	82:6473597d706e	1491	*/
bogdanm	82:6473597d706e	1492	//@{
bogdanm	82:6473597d706e	1493	#define BP_MPU_RGDAACn_M1PE (11U) //!< Bit position for MPU_RGDAACn_M1PE.
bogdanm	82:6473597d706e	1494	#define BM_MPU_RGDAACn_M1PE (0x00000800U) //!< Bit mask for MPU_RGDAACn_M1PE.
bogdanm	82:6473597d706e	1495	#define BS_MPU_RGDAACn_M1PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M1PE.
bogdanm	82:6473597d706e	1496
bogdanm	82:6473597d706e	1497	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1498	//! @brief Read current value of the MPU_RGDAACn_M1PE field.
bogdanm	82:6473597d706e	1499	#define BR_MPU_RGDAACn_M1PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M1PE))
bogdanm	82:6473597d706e	1500	#endif
bogdanm	82:6473597d706e	1501
bogdanm	82:6473597d706e	1502	//! @brief Format value for bitfield MPU_RGDAACn_M1PE.
bogdanm	82:6473597d706e	1503	#define BF_MPU_RGDAACn_M1PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1PE), uint32_t) & BM_MPU_RGDAACn_M1PE)
bogdanm	82:6473597d706e	1504
bogdanm	82:6473597d706e	1505	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1506	//! @brief Set the M1PE field to a new value.
bogdanm	82:6473597d706e	1507	#define BW_MPU_RGDAACn_M1PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M1PE) = (v))
bogdanm	82:6473597d706e	1508	#endif
bogdanm	82:6473597d706e	1509	//@}
bogdanm	82:6473597d706e	1510
bogdanm	82:6473597d706e	1511	/*!
bogdanm	82:6473597d706e	1512	* @name Register MPU_RGDAACn, field M2UM[14:12] (RW)
bogdanm	82:6473597d706e	1513	*
bogdanm	82:6473597d706e	1514	* See M3UM description.
bogdanm	82:6473597d706e	1515	*/
bogdanm	82:6473597d706e	1516	//@{
bogdanm	82:6473597d706e	1517	#define BP_MPU_RGDAACn_M2UM (12U) //!< Bit position for MPU_RGDAACn_M2UM.
bogdanm	82:6473597d706e	1518	#define BM_MPU_RGDAACn_M2UM (0x00007000U) //!< Bit mask for MPU_RGDAACn_M2UM.
bogdanm	82:6473597d706e	1519	#define BS_MPU_RGDAACn_M2UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M2UM.
bogdanm	82:6473597d706e	1520
bogdanm	82:6473597d706e	1521	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1522	//! @brief Read current value of the MPU_RGDAACn_M2UM field.
bogdanm	82:6473597d706e	1523	#define BR_MPU_RGDAACn_M2UM(n) (HW_MPU_RGDAACn(n).B.M2UM)
bogdanm	82:6473597d706e	1524	#endif
bogdanm	82:6473597d706e	1525
bogdanm	82:6473597d706e	1526	//! @brief Format value for bitfield MPU_RGDAACn_M2UM.
bogdanm	82:6473597d706e	1527	#define BF_MPU_RGDAACn_M2UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2UM), uint32_t) & BM_MPU_RGDAACn_M2UM)
bogdanm	82:6473597d706e	1528
bogdanm	82:6473597d706e	1529	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1530	//! @brief Set the M2UM field to a new value.
bogdanm	82:6473597d706e	1531	#define BW_MPU_RGDAACn_M2UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M2UM) \| BF_MPU_RGDAACn_M2UM(v)))
bogdanm	82:6473597d706e	1532	#endif
bogdanm	82:6473597d706e	1533	//@}
bogdanm	82:6473597d706e	1534
bogdanm	82:6473597d706e	1535	/*!
bogdanm	82:6473597d706e	1536	* @name Register MPU_RGDAACn, field M2SM[16:15] (RW)
bogdanm	82:6473597d706e	1537	*
bogdanm	82:6473597d706e	1538	* See M3SM description.
bogdanm	82:6473597d706e	1539	*/
bogdanm	82:6473597d706e	1540	//@{
bogdanm	82:6473597d706e	1541	#define BP_MPU_RGDAACn_M2SM (15U) //!< Bit position for MPU_RGDAACn_M2SM.
bogdanm	82:6473597d706e	1542	#define BM_MPU_RGDAACn_M2SM (0x00018000U) //!< Bit mask for MPU_RGDAACn_M2SM.
bogdanm	82:6473597d706e	1543	#define BS_MPU_RGDAACn_M2SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M2SM.
bogdanm	82:6473597d706e	1544
bogdanm	82:6473597d706e	1545	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1546	//! @brief Read current value of the MPU_RGDAACn_M2SM field.
bogdanm	82:6473597d706e	1547	#define BR_MPU_RGDAACn_M2SM(n) (HW_MPU_RGDAACn(n).B.M2SM)
bogdanm	82:6473597d706e	1548	#endif
bogdanm	82:6473597d706e	1549
bogdanm	82:6473597d706e	1550	//! @brief Format value for bitfield MPU_RGDAACn_M2SM.
bogdanm	82:6473597d706e	1551	#define BF_MPU_RGDAACn_M2SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2SM), uint32_t) & BM_MPU_RGDAACn_M2SM)
bogdanm	82:6473597d706e	1552
bogdanm	82:6473597d706e	1553	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1554	//! @brief Set the M2SM field to a new value.
bogdanm	82:6473597d706e	1555	#define BW_MPU_RGDAACn_M2SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M2SM) \| BF_MPU_RGDAACn_M2SM(v)))
bogdanm	82:6473597d706e	1556	#endif
bogdanm	82:6473597d706e	1557	//@}
bogdanm	82:6473597d706e	1558
bogdanm	82:6473597d706e	1559	/*!
bogdanm	82:6473597d706e	1560	* @name Register MPU_RGDAACn, field M2PE[17] (RW)
bogdanm	82:6473597d706e	1561	*
bogdanm	82:6473597d706e	1562	* See M3PE description.
bogdanm	82:6473597d706e	1563	*/
bogdanm	82:6473597d706e	1564	//@{
bogdanm	82:6473597d706e	1565	#define BP_MPU_RGDAACn_M2PE (17U) //!< Bit position for MPU_RGDAACn_M2PE.
bogdanm	82:6473597d706e	1566	#define BM_MPU_RGDAACn_M2PE (0x00020000U) //!< Bit mask for MPU_RGDAACn_M2PE.
bogdanm	82:6473597d706e	1567	#define BS_MPU_RGDAACn_M2PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M2PE.
bogdanm	82:6473597d706e	1568
bogdanm	82:6473597d706e	1569	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1570	//! @brief Read current value of the MPU_RGDAACn_M2PE field.
bogdanm	82:6473597d706e	1571	#define BR_MPU_RGDAACn_M2PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M2PE))
bogdanm	82:6473597d706e	1572	#endif
bogdanm	82:6473597d706e	1573
bogdanm	82:6473597d706e	1574	//! @brief Format value for bitfield MPU_RGDAACn_M2PE.
bogdanm	82:6473597d706e	1575	#define BF_MPU_RGDAACn_M2PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2PE), uint32_t) & BM_MPU_RGDAACn_M2PE)
bogdanm	82:6473597d706e	1576
bogdanm	82:6473597d706e	1577	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1578	//! @brief Set the M2PE field to a new value.
bogdanm	82:6473597d706e	1579	#define BW_MPU_RGDAACn_M2PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M2PE) = (v))
bogdanm	82:6473597d706e	1580	#endif
bogdanm	82:6473597d706e	1581	//@}
bogdanm	82:6473597d706e	1582
bogdanm	82:6473597d706e	1583	/*!
bogdanm	82:6473597d706e	1584	* @name Register MPU_RGDAACn, field M3UM[20:18] (RW)
bogdanm	82:6473597d706e	1585	*
bogdanm	82:6473597d706e	1586	* Defines the access controls for bus master 3 in user mode. M3UM consists of
bogdanm	82:6473597d706e	1587	* three independent bits, enabling read (r), write (w), and execute (x)
bogdanm	82:6473597d706e	1588	* permissions.
bogdanm	82:6473597d706e	1589	*
bogdanm	82:6473597d706e	1590	* Values:
bogdanm	82:6473597d706e	1591	* - 0 - An attempted access of that mode may be terminated with an access error
bogdanm	82:6473597d706e	1592	* (if not allowed by another descriptor) and the access not performed.
bogdanm	82:6473597d706e	1593	* - 1 - Allows the given access type to occur
bogdanm	82:6473597d706e	1594	*/
bogdanm	82:6473597d706e	1595	//@{
bogdanm	82:6473597d706e	1596	#define BP_MPU_RGDAACn_M3UM (18U) //!< Bit position for MPU_RGDAACn_M3UM.
bogdanm	82:6473597d706e	1597	#define BM_MPU_RGDAACn_M3UM (0x001C0000U) //!< Bit mask for MPU_RGDAACn_M3UM.
bogdanm	82:6473597d706e	1598	#define BS_MPU_RGDAACn_M3UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M3UM.
bogdanm	82:6473597d706e	1599
bogdanm	82:6473597d706e	1600	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1601	//! @brief Read current value of the MPU_RGDAACn_M3UM field.
bogdanm	82:6473597d706e	1602	#define BR_MPU_RGDAACn_M3UM(n) (HW_MPU_RGDAACn(n).B.M3UM)
bogdanm	82:6473597d706e	1603	#endif
bogdanm	82:6473597d706e	1604
bogdanm	82:6473597d706e	1605	//! @brief Format value for bitfield MPU_RGDAACn_M3UM.
bogdanm	82:6473597d706e	1606	#define BF_MPU_RGDAACn_M3UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3UM), uint32_t) & BM_MPU_RGDAACn_M3UM)
bogdanm	82:6473597d706e	1607
bogdanm	82:6473597d706e	1608	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1609	//! @brief Set the M3UM field to a new value.
bogdanm	82:6473597d706e	1610	#define BW_MPU_RGDAACn_M3UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M3UM) \| BF_MPU_RGDAACn_M3UM(v)))
bogdanm	82:6473597d706e	1611	#endif
bogdanm	82:6473597d706e	1612	//@}
bogdanm	82:6473597d706e	1613
bogdanm	82:6473597d706e	1614	/*!
bogdanm	82:6473597d706e	1615	* @name Register MPU_RGDAACn, field M3SM[22:21] (RW)
bogdanm	82:6473597d706e	1616	*
bogdanm	82:6473597d706e	1617	* Defines the access controls for bus master 3 in Supervisor mode.
bogdanm	82:6473597d706e	1618	*
bogdanm	82:6473597d706e	1619	* Values:
bogdanm	82:6473597d706e	1620	* - 00 - r/w/x; read, write and execute allowed
bogdanm	82:6473597d706e	1621	* - 01 - r/x; read and execute allowed, but no write
bogdanm	82:6473597d706e	1622	* - 10 - r/w; read and write allowed, but no execute
bogdanm	82:6473597d706e	1623	* - 11 - Same as User mode defined in M3UM
bogdanm	82:6473597d706e	1624	*/
bogdanm	82:6473597d706e	1625	//@{
bogdanm	82:6473597d706e	1626	#define BP_MPU_RGDAACn_M3SM (21U) //!< Bit position for MPU_RGDAACn_M3SM.
bogdanm	82:6473597d706e	1627	#define BM_MPU_RGDAACn_M3SM (0x00600000U) //!< Bit mask for MPU_RGDAACn_M3SM.
bogdanm	82:6473597d706e	1628	#define BS_MPU_RGDAACn_M3SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M3SM.
bogdanm	82:6473597d706e	1629
bogdanm	82:6473597d706e	1630	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1631	//! @brief Read current value of the MPU_RGDAACn_M3SM field.
bogdanm	82:6473597d706e	1632	#define BR_MPU_RGDAACn_M3SM(n) (HW_MPU_RGDAACn(n).B.M3SM)
bogdanm	82:6473597d706e	1633	#endif
bogdanm	82:6473597d706e	1634
bogdanm	82:6473597d706e	1635	//! @brief Format value for bitfield MPU_RGDAACn_M3SM.
bogdanm	82:6473597d706e	1636	#define BF_MPU_RGDAACn_M3SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3SM), uint32_t) & BM_MPU_RGDAACn_M3SM)
bogdanm	82:6473597d706e	1637
bogdanm	82:6473597d706e	1638	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1639	//! @brief Set the M3SM field to a new value.
bogdanm	82:6473597d706e	1640	#define BW_MPU_RGDAACn_M3SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M3SM) \| BF_MPU_RGDAACn_M3SM(v)))
bogdanm	82:6473597d706e	1641	#endif
bogdanm	82:6473597d706e	1642	//@}
bogdanm	82:6473597d706e	1643
bogdanm	82:6473597d706e	1644	/*!
bogdanm	82:6473597d706e	1645	* @name Register MPU_RGDAACn, field M3PE[23] (RW)
bogdanm	82:6473597d706e	1646	*
bogdanm	82:6473597d706e	1647	* Values:
bogdanm	82:6473597d706e	1648	* - 0 - Do not include the process identifier in the evaluation
bogdanm	82:6473597d706e	1649	* - 1 - Include the process identifier and mask (RGDn.RGDAAC) in the region hit
bogdanm	82:6473597d706e	1650	* evaluation
bogdanm	82:6473597d706e	1651	*/
bogdanm	82:6473597d706e	1652	//@{
bogdanm	82:6473597d706e	1653	#define BP_MPU_RGDAACn_M3PE (23U) //!< Bit position for MPU_RGDAACn_M3PE.
bogdanm	82:6473597d706e	1654	#define BM_MPU_RGDAACn_M3PE (0x00800000U) //!< Bit mask for MPU_RGDAACn_M3PE.
bogdanm	82:6473597d706e	1655	#define BS_MPU_RGDAACn_M3PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M3PE.
bogdanm	82:6473597d706e	1656
bogdanm	82:6473597d706e	1657	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1658	//! @brief Read current value of the MPU_RGDAACn_M3PE field.
bogdanm	82:6473597d706e	1659	#define BR_MPU_RGDAACn_M3PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M3PE))
bogdanm	82:6473597d706e	1660	#endif
bogdanm	82:6473597d706e	1661
bogdanm	82:6473597d706e	1662	//! @brief Format value for bitfield MPU_RGDAACn_M3PE.
bogdanm	82:6473597d706e	1663	#define BF_MPU_RGDAACn_M3PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3PE), uint32_t) & BM_MPU_RGDAACn_M3PE)
bogdanm	82:6473597d706e	1664
bogdanm	82:6473597d706e	1665	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1666	//! @brief Set the M3PE field to a new value.
bogdanm	82:6473597d706e	1667	#define BW_MPU_RGDAACn_M3PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M3PE) = (v))
bogdanm	82:6473597d706e	1668	#endif
bogdanm	82:6473597d706e	1669	//@}
bogdanm	82:6473597d706e	1670
bogdanm	82:6473597d706e	1671	/*!
bogdanm	82:6473597d706e	1672	* @name Register MPU_RGDAACn, field M4WE[24] (RW)
bogdanm	82:6473597d706e	1673	*
bogdanm	82:6473597d706e	1674	* Values:
bogdanm	82:6473597d706e	1675	* - 0 - Bus master 4 writes terminate with an access error and the write is not
bogdanm	82:6473597d706e	1676	* performed
bogdanm	82:6473597d706e	1677	* - 1 - Bus master 4 writes allowed
bogdanm	82:6473597d706e	1678	*/
bogdanm	82:6473597d706e	1679	//@{
bogdanm	82:6473597d706e	1680	#define BP_MPU_RGDAACn_M4WE (24U) //!< Bit position for MPU_RGDAACn_M4WE.
bogdanm	82:6473597d706e	1681	#define BM_MPU_RGDAACn_M4WE (0x01000000U) //!< Bit mask for MPU_RGDAACn_M4WE.
bogdanm	82:6473597d706e	1682	#define BS_MPU_RGDAACn_M4WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M4WE.
bogdanm	82:6473597d706e	1683
bogdanm	82:6473597d706e	1684	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1685	//! @brief Read current value of the MPU_RGDAACn_M4WE field.
bogdanm	82:6473597d706e	1686	#define BR_MPU_RGDAACn_M4WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4WE))
bogdanm	82:6473597d706e	1687	#endif
bogdanm	82:6473597d706e	1688
bogdanm	82:6473597d706e	1689	//! @brief Format value for bitfield MPU_RGDAACn_M4WE.
bogdanm	82:6473597d706e	1690	#define BF_MPU_RGDAACn_M4WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M4WE), uint32_t) & BM_MPU_RGDAACn_M4WE)
bogdanm	82:6473597d706e	1691
bogdanm	82:6473597d706e	1692	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1693	//! @brief Set the M4WE field to a new value.
bogdanm	82:6473597d706e	1694	#define BW_MPU_RGDAACn_M4WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4WE) = (v))
bogdanm	82:6473597d706e	1695	#endif
bogdanm	82:6473597d706e	1696	//@}
bogdanm	82:6473597d706e	1697
bogdanm	82:6473597d706e	1698	/*!
bogdanm	82:6473597d706e	1699	* @name Register MPU_RGDAACn, field M4RE[25] (RW)
bogdanm	82:6473597d706e	1700	*
bogdanm	82:6473597d706e	1701	* Values:
bogdanm	82:6473597d706e	1702	* - 0 - Bus master 4 reads terminate with an access error and the read is not
bogdanm	82:6473597d706e	1703	* performed
bogdanm	82:6473597d706e	1704	* - 1 - Bus master 4 reads allowed
bogdanm	82:6473597d706e	1705	*/
bogdanm	82:6473597d706e	1706	//@{
bogdanm	82:6473597d706e	1707	#define BP_MPU_RGDAACn_M4RE (25U) //!< Bit position for MPU_RGDAACn_M4RE.
bogdanm	82:6473597d706e	1708	#define BM_MPU_RGDAACn_M4RE (0x02000000U) //!< Bit mask for MPU_RGDAACn_M4RE.
bogdanm	82:6473597d706e	1709	#define BS_MPU_RGDAACn_M4RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M4RE.
bogdanm	82:6473597d706e	1710
bogdanm	82:6473597d706e	1711	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1712	//! @brief Read current value of the MPU_RGDAACn_M4RE field.
bogdanm	82:6473597d706e	1713	#define BR_MPU_RGDAACn_M4RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4RE))
bogdanm	82:6473597d706e	1714	#endif
bogdanm	82:6473597d706e	1715
bogdanm	82:6473597d706e	1716	//! @brief Format value for bitfield MPU_RGDAACn_M4RE.
bogdanm	82:6473597d706e	1717	#define BF_MPU_RGDAACn_M4RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M4RE), uint32_t) & BM_MPU_RGDAACn_M4RE)
bogdanm	82:6473597d706e	1718
bogdanm	82:6473597d706e	1719	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1720	//! @brief Set the M4RE field to a new value.
bogdanm	82:6473597d706e	1721	#define BW_MPU_RGDAACn_M4RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4RE) = (v))
bogdanm	82:6473597d706e	1722	#endif
bogdanm	82:6473597d706e	1723	//@}
bogdanm	82:6473597d706e	1724
bogdanm	82:6473597d706e	1725	/*!
bogdanm	82:6473597d706e	1726	* @name Register MPU_RGDAACn, field M5WE[26] (RW)
bogdanm	82:6473597d706e	1727	*
bogdanm	82:6473597d706e	1728	* Values:
bogdanm	82:6473597d706e	1729	* - 0 - Bus master 5 writes terminate with an access error and the write is not
bogdanm	82:6473597d706e	1730	* performed
bogdanm	82:6473597d706e	1731	* - 1 - Bus master 5 writes allowed
bogdanm	82:6473597d706e	1732	*/
bogdanm	82:6473597d706e	1733	//@{
bogdanm	82:6473597d706e	1734	#define BP_MPU_RGDAACn_M5WE (26U) //!< Bit position for MPU_RGDAACn_M5WE.
bogdanm	82:6473597d706e	1735	#define BM_MPU_RGDAACn_M5WE (0x04000000U) //!< Bit mask for MPU_RGDAACn_M5WE.
bogdanm	82:6473597d706e	1736	#define BS_MPU_RGDAACn_M5WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M5WE.
bogdanm	82:6473597d706e	1737
bogdanm	82:6473597d706e	1738	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1739	//! @brief Read current value of the MPU_RGDAACn_M5WE field.
bogdanm	82:6473597d706e	1740	#define BR_MPU_RGDAACn_M5WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5WE))
bogdanm	82:6473597d706e	1741	#endif
bogdanm	82:6473597d706e	1742
bogdanm	82:6473597d706e	1743	//! @brief Format value for bitfield MPU_RGDAACn_M5WE.
bogdanm	82:6473597d706e	1744	#define BF_MPU_RGDAACn_M5WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M5WE), uint32_t) & BM_MPU_RGDAACn_M5WE)
bogdanm	82:6473597d706e	1745
bogdanm	82:6473597d706e	1746	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1747	//! @brief Set the M5WE field to a new value.
bogdanm	82:6473597d706e	1748	#define BW_MPU_RGDAACn_M5WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5WE) = (v))
bogdanm	82:6473597d706e	1749	#endif
bogdanm	82:6473597d706e	1750	//@}
bogdanm	82:6473597d706e	1751
bogdanm	82:6473597d706e	1752	/*!
bogdanm	82:6473597d706e	1753	* @name Register MPU_RGDAACn, field M5RE[27] (RW)
bogdanm	82:6473597d706e	1754	*
bogdanm	82:6473597d706e	1755	* Values:
bogdanm	82:6473597d706e	1756	* - 0 - Bus master 5 reads terminate with an access error and the read is not
bogdanm	82:6473597d706e	1757	* performed
bogdanm	82:6473597d706e	1758	* - 1 - Bus master 5 reads allowed
bogdanm	82:6473597d706e	1759	*/
bogdanm	82:6473597d706e	1760	//@{
bogdanm	82:6473597d706e	1761	#define BP_MPU_RGDAACn_M5RE (27U) //!< Bit position for MPU_RGDAACn_M5RE.
bogdanm	82:6473597d706e	1762	#define BM_MPU_RGDAACn_M5RE (0x08000000U) //!< Bit mask for MPU_RGDAACn_M5RE.
bogdanm	82:6473597d706e	1763	#define BS_MPU_RGDAACn_M5RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M5RE.
bogdanm	82:6473597d706e	1764
bogdanm	82:6473597d706e	1765	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1766	//! @brief Read current value of the MPU_RGDAACn_M5RE field.
bogdanm	82:6473597d706e	1767	#define BR_MPU_RGDAACn_M5RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5RE))
bogdanm	82:6473597d706e	1768	#endif
bogdanm	82:6473597d706e	1769
bogdanm	82:6473597d706e	1770	//! @brief Format value for bitfield MPU_RGDAACn_M5RE.
bogdanm	82:6473597d706e	1771	#define BF_MPU_RGDAACn_M5RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M5RE), uint32_t) & BM_MPU_RGDAACn_M5RE)
bogdanm	82:6473597d706e	1772
bogdanm	82:6473597d706e	1773	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1774	//! @brief Set the M5RE field to a new value.
bogdanm	82:6473597d706e	1775	#define BW_MPU_RGDAACn_M5RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5RE) = (v))
bogdanm	82:6473597d706e	1776	#endif
bogdanm	82:6473597d706e	1777	//@}
bogdanm	82:6473597d706e	1778
bogdanm	82:6473597d706e	1779	/*!
bogdanm	82:6473597d706e	1780	* @name Register MPU_RGDAACn, field M6WE[28] (RW)
bogdanm	82:6473597d706e	1781	*
bogdanm	82:6473597d706e	1782	* Values:
bogdanm	82:6473597d706e	1783	* - 0 - Bus master 6 writes terminate with an access error and the write is not
bogdanm	82:6473597d706e	1784	* performed
bogdanm	82:6473597d706e	1785	* - 1 - Bus master 6 writes allowed
bogdanm	82:6473597d706e	1786	*/
bogdanm	82:6473597d706e	1787	//@{
bogdanm	82:6473597d706e	1788	#define BP_MPU_RGDAACn_M6WE (28U) //!< Bit position for MPU_RGDAACn_M6WE.
bogdanm	82:6473597d706e	1789	#define BM_MPU_RGDAACn_M6WE (0x10000000U) //!< Bit mask for MPU_RGDAACn_M6WE.
bogdanm	82:6473597d706e	1790	#define BS_MPU_RGDAACn_M6WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M6WE.
bogdanm	82:6473597d706e	1791
bogdanm	82:6473597d706e	1792	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1793	//! @brief Read current value of the MPU_RGDAACn_M6WE field.
bogdanm	82:6473597d706e	1794	#define BR_MPU_RGDAACn_M6WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6WE))
bogdanm	82:6473597d706e	1795	#endif
bogdanm	82:6473597d706e	1796
bogdanm	82:6473597d706e	1797	//! @brief Format value for bitfield MPU_RGDAACn_M6WE.
bogdanm	82:6473597d706e	1798	#define BF_MPU_RGDAACn_M6WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M6WE), uint32_t) & BM_MPU_RGDAACn_M6WE)
bogdanm	82:6473597d706e	1799
bogdanm	82:6473597d706e	1800	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1801	//! @brief Set the M6WE field to a new value.
bogdanm	82:6473597d706e	1802	#define BW_MPU_RGDAACn_M6WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6WE) = (v))
bogdanm	82:6473597d706e	1803	#endif
bogdanm	82:6473597d706e	1804	//@}
bogdanm	82:6473597d706e	1805
bogdanm	82:6473597d706e	1806	/*!
bogdanm	82:6473597d706e	1807	* @name Register MPU_RGDAACn, field M6RE[29] (RW)
bogdanm	82:6473597d706e	1808	*
bogdanm	82:6473597d706e	1809	* Values:
bogdanm	82:6473597d706e	1810	* - 0 - Bus master 6 reads terminate with an access error and the read is not
bogdanm	82:6473597d706e	1811	* performed
bogdanm	82:6473597d706e	1812	* - 1 - Bus master 6 reads allowed
bogdanm	82:6473597d706e	1813	*/
bogdanm	82:6473597d706e	1814	//@{
bogdanm	82:6473597d706e	1815	#define BP_MPU_RGDAACn_M6RE (29U) //!< Bit position for MPU_RGDAACn_M6RE.
bogdanm	82:6473597d706e	1816	#define BM_MPU_RGDAACn_M6RE (0x20000000U) //!< Bit mask for MPU_RGDAACn_M6RE.
bogdanm	82:6473597d706e	1817	#define BS_MPU_RGDAACn_M6RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M6RE.
bogdanm	82:6473597d706e	1818
bogdanm	82:6473597d706e	1819	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1820	//! @brief Read current value of the MPU_RGDAACn_M6RE field.
bogdanm	82:6473597d706e	1821	#define BR_MPU_RGDAACn_M6RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6RE))
bogdanm	82:6473597d706e	1822	#endif
bogdanm	82:6473597d706e	1823
bogdanm	82:6473597d706e	1824	//! @brief Format value for bitfield MPU_RGDAACn_M6RE.
bogdanm	82:6473597d706e	1825	#define BF_MPU_RGDAACn_M6RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M6RE), uint32_t) & BM_MPU_RGDAACn_M6RE)
bogdanm	82:6473597d706e	1826
bogdanm	82:6473597d706e	1827	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1828	//! @brief Set the M6RE field to a new value.
bogdanm	82:6473597d706e	1829	#define BW_MPU_RGDAACn_M6RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6RE) = (v))
bogdanm	82:6473597d706e	1830	#endif
bogdanm	82:6473597d706e	1831	//@}
bogdanm	82:6473597d706e	1832
bogdanm	82:6473597d706e	1833	/*!
bogdanm	82:6473597d706e	1834	* @name Register MPU_RGDAACn, field M7WE[30] (RW)
bogdanm	82:6473597d706e	1835	*
bogdanm	82:6473597d706e	1836	* Values:
bogdanm	82:6473597d706e	1837	* - 0 - Bus master 7 writes terminate with an access error and the write is not
bogdanm	82:6473597d706e	1838	* performed
bogdanm	82:6473597d706e	1839	* - 1 - Bus master 7 writes allowed
bogdanm	82:6473597d706e	1840	*/
bogdanm	82:6473597d706e	1841	//@{
bogdanm	82:6473597d706e	1842	#define BP_MPU_RGDAACn_M7WE (30U) //!< Bit position for MPU_RGDAACn_M7WE.
bogdanm	82:6473597d706e	1843	#define BM_MPU_RGDAACn_M7WE (0x40000000U) //!< Bit mask for MPU_RGDAACn_M7WE.
bogdanm	82:6473597d706e	1844	#define BS_MPU_RGDAACn_M7WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M7WE.
bogdanm	82:6473597d706e	1845
bogdanm	82:6473597d706e	1846	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1847	//! @brief Read current value of the MPU_RGDAACn_M7WE field.
bogdanm	82:6473597d706e	1848	#define BR_MPU_RGDAACn_M7WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7WE))
bogdanm	82:6473597d706e	1849	#endif
bogdanm	82:6473597d706e	1850
bogdanm	82:6473597d706e	1851	//! @brief Format value for bitfield MPU_RGDAACn_M7WE.
bogdanm	82:6473597d706e	1852	#define BF_MPU_RGDAACn_M7WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M7WE), uint32_t) & BM_MPU_RGDAACn_M7WE)
bogdanm	82:6473597d706e	1853
bogdanm	82:6473597d706e	1854	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1855	//! @brief Set the M7WE field to a new value.
bogdanm	82:6473597d706e	1856	#define BW_MPU_RGDAACn_M7WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7WE) = (v))
bogdanm	82:6473597d706e	1857	#endif
bogdanm	82:6473597d706e	1858	//@}
bogdanm	82:6473597d706e	1859
bogdanm	82:6473597d706e	1860	/*!
bogdanm	82:6473597d706e	1861	* @name Register MPU_RGDAACn, field M7RE[31] (RW)
bogdanm	82:6473597d706e	1862	*
bogdanm	82:6473597d706e	1863	* Values:
bogdanm	82:6473597d706e	1864	* - 0 - Bus master 7 reads terminate with an access error and the read is not
bogdanm	82:6473597d706e	1865	* performed
bogdanm	82:6473597d706e	1866	* - 1 - Bus master 7 reads allowed
bogdanm	82:6473597d706e	1867	*/
bogdanm	82:6473597d706e	1868	//@{
bogdanm	82:6473597d706e	1869	#define BP_MPU_RGDAACn_M7RE (31U) //!< Bit position for MPU_RGDAACn_M7RE.
bogdanm	82:6473597d706e	1870	#define BM_MPU_RGDAACn_M7RE (0x80000000U) //!< Bit mask for MPU_RGDAACn_M7RE.
bogdanm	82:6473597d706e	1871	#define BS_MPU_RGDAACn_M7RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M7RE.
bogdanm	82:6473597d706e	1872
bogdanm	82:6473597d706e	1873	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1874	//! @brief Read current value of the MPU_RGDAACn_M7RE field.
bogdanm	82:6473597d706e	1875	#define BR_MPU_RGDAACn_M7RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7RE))
bogdanm	82:6473597d706e	1876	#endif
bogdanm	82:6473597d706e	1877
bogdanm	82:6473597d706e	1878	//! @brief Format value for bitfield MPU_RGDAACn_M7RE.
bogdanm	82:6473597d706e	1879	#define BF_MPU_RGDAACn_M7RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M7RE), uint32_t) & BM_MPU_RGDAACn_M7RE)
bogdanm	82:6473597d706e	1880
bogdanm	82:6473597d706e	1881	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1882	//! @brief Set the M7RE field to a new value.
bogdanm	82:6473597d706e	1883	#define BW_MPU_RGDAACn_M7RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7RE) = (v))
bogdanm	82:6473597d706e	1884	#endif
bogdanm	82:6473597d706e	1885	//@}
bogdanm	82:6473597d706e	1886
bogdanm	82:6473597d706e	1887	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1888	// hw_mpu_t - module struct
bogdanm	82:6473597d706e	1889	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1890	/*!
bogdanm	82:6473597d706e	1891	* @brief All MPU module registers.
bogdanm	82:6473597d706e	1892	*/
bogdanm	82:6473597d706e	1893	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1894	#pragma pack(1)
bogdanm	82:6473597d706e	1895	typedef struct _hw_mpu
bogdanm	82:6473597d706e	1896	{
bogdanm	82:6473597d706e	1897	__IO hw_mpu_cesr_t CESR; //!< [0x0] Control/Error Status Register
bogdanm	82:6473597d706e	1898	uint8_t _reserved0[12];
bogdanm	82:6473597d706e	1899	struct {
bogdanm	82:6473597d706e	1900	__I hw_mpu_earn_t EARn; //!< [0x10] Error Address Register, slave port n
bogdanm	82:6473597d706e	1901	__I hw_mpu_edrn_t EDRn; //!< [0x14] Error Detail Register, slave port n
bogdanm	82:6473597d706e	1902	} SP[5];
bogdanm	82:6473597d706e	1903	uint8_t _reserved1[968];
bogdanm	82:6473597d706e	1904	struct {
bogdanm	82:6473597d706e	1905	__IO hw_mpu_rgdn_word0_t RGDn_WORD0; //!< [0x400] Region Descriptor n, Word 0
bogdanm	82:6473597d706e	1906	__IO hw_mpu_rgdn_word1_t RGDn_WORD1; //!< [0x404] Region Descriptor n, Word 1
bogdanm	82:6473597d706e	1907	__IO hw_mpu_rgdn_word2_t RGDn_WORD2; //!< [0x408] Region Descriptor n, Word 2
bogdanm	82:6473597d706e	1908	__IO hw_mpu_rgdn_word3_t RGDn_WORD3; //!< [0x40C] Region Descriptor n, Word 3
bogdanm	82:6473597d706e	1909	} RGD[12];
bogdanm	82:6473597d706e	1910	uint8_t _reserved2[832];
bogdanm	82:6473597d706e	1911	__IO hw_mpu_rgdaacn_t RGDAACn[12]; //!< [0x800] Region Descriptor Alternate Access Control n
bogdanm	82:6473597d706e	1912	} hw_mpu_t;
bogdanm	82:6473597d706e	1913	#pragma pack()
bogdanm	82:6473597d706e	1914
bogdanm	82:6473597d706e	1915	//! @brief Macro to access all MPU registers.
bogdanm	82:6473597d706e	1916	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	1917	//! use the '&' operator, like <code>&HW_MPU</code>.
bogdanm	82:6473597d706e	1918	#define HW_MPU ((hw_mpu_t ) REGS_MPU_BASE)
bogdanm	82:6473597d706e	1919	#endif
bogdanm	82:6473597d706e	1920
bogdanm	82:6473597d706e	1921	#endif // __HW_MPU_REGISTERS_H__
bogdanm	82:6473597d706e	1922	// v22/130726/0.9
bogdanm	82:6473597d706e	1923	// EOF

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Type:	Library
Created:	25 Jun 2015
Imports:	24
Forks:	0
Commits:	103
Dependents:	1
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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_mpu.h@89:552587b429a1, 2014-09-12 (annotated)

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