mbed - mbed library

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mbed library

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_mcg.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_mcg.h@82:6473597d706e

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_MCG_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_MCG_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 MCG
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Multipurpose Clock Generator module
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_MCG_C1 - MCG Control 1 Register
bogdanm	82:6473597d706e	33	* - HW_MCG_C2 - MCG Control 2 Register
bogdanm	82:6473597d706e	34	* - HW_MCG_C3 - MCG Control 3 Register
bogdanm	82:6473597d706e	35	* - HW_MCG_C4 - MCG Control 4 Register
bogdanm	82:6473597d706e	36	* - HW_MCG_C5 - MCG Control 5 Register
bogdanm	82:6473597d706e	37	* - HW_MCG_C6 - MCG Control 6 Register
bogdanm	82:6473597d706e	38	* - HW_MCG_S - MCG Status Register
bogdanm	82:6473597d706e	39	* - HW_MCG_SC - MCG Status and Control Register
bogdanm	82:6473597d706e	40	* - HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
bogdanm	82:6473597d706e	41	* - HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
bogdanm	82:6473597d706e	42	* - HW_MCG_C7 - MCG Control 7 Register
bogdanm	82:6473597d706e	43	* - HW_MCG_C8 - MCG Control 8 Register
bogdanm	82:6473597d706e	44	*
bogdanm	82:6473597d706e	45	* - hw_mcg_t - Struct containing all module registers.
bogdanm	82:6473597d706e	46	*/
bogdanm	82:6473597d706e	47
bogdanm	82:6473597d706e	48	//! @name Module base addresses
bogdanm	82:6473597d706e	49	//@{
bogdanm	82:6473597d706e	50	#ifndef REGS_MCG_BASE
bogdanm	82:6473597d706e	51	#define HW_MCG_INSTANCE_COUNT (1U) //!< Number of instances of the MCG module.
bogdanm	82:6473597d706e	52	#define REGS_MCG_BASE (0x40064000U) //!< Base address for MCG.
bogdanm	82:6473597d706e	53	#endif
bogdanm	82:6473597d706e	54	//@}
bogdanm	82:6473597d706e	55
bogdanm	82:6473597d706e	56	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	57	// HW_MCG_C1 - MCG Control 1 Register
bogdanm	82:6473597d706e	58	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	59
bogdanm	82:6473597d706e	60	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	61	/*!
bogdanm	82:6473597d706e	62	* @brief HW_MCG_C1 - MCG Control 1 Register (RW)
bogdanm	82:6473597d706e	63	*
bogdanm	82:6473597d706e	64	* Reset value: 0x04U
bogdanm	82:6473597d706e	65	*/
bogdanm	82:6473597d706e	66	typedef union _hw_mcg_c1
bogdanm	82:6473597d706e	67	{
bogdanm	82:6473597d706e	68	uint8_t U;
bogdanm	82:6473597d706e	69	struct _hw_mcg_c1_bitfields
bogdanm	82:6473597d706e	70	{
bogdanm	82:6473597d706e	71	uint8_t IREFSTEN : 1; //!< [0] Internal Reference Stop Enable
bogdanm	82:6473597d706e	72	uint8_t IRCLKEN : 1; //!< [1] Internal Reference Clock Enable
bogdanm	82:6473597d706e	73	uint8_t IREFS : 1; //!< [2] Internal Reference Select
bogdanm	82:6473597d706e	74	uint8_t FRDIV : 3; //!< [5:3] FLL External Reference Divider
bogdanm	82:6473597d706e	75	uint8_t CLKS : 2; //!< [7:6] Clock Source Select
bogdanm	82:6473597d706e	76	} B;
bogdanm	82:6473597d706e	77	} hw_mcg_c1_t;
bogdanm	82:6473597d706e	78	#endif
bogdanm	82:6473597d706e	79
bogdanm	82:6473597d706e	80	/*!
bogdanm	82:6473597d706e	81	* @name Constants and macros for entire MCG_C1 register
bogdanm	82:6473597d706e	82	*/
bogdanm	82:6473597d706e	83	//@{
bogdanm	82:6473597d706e	84	#define HW_MCG_C1_ADDR (REGS_MCG_BASE + 0x0U)
bogdanm	82:6473597d706e	85
bogdanm	82:6473597d706e	86	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	87	#define HW_MCG_C1 ((__IO hw_mcg_c1_t ) HW_MCG_C1_ADDR)
bogdanm	82:6473597d706e	88	#define HW_MCG_C1_RD() (HW_MCG_C1.U)
bogdanm	82:6473597d706e	89	#define HW_MCG_C1_WR(v) (HW_MCG_C1.U = (v))
bogdanm	82:6473597d706e	90	#define HW_MCG_C1_SET(v) (HW_MCG_C1_WR(HW_MCG_C1_RD() \| (v)))
bogdanm	82:6473597d706e	91	#define HW_MCG_C1_CLR(v) (HW_MCG_C1_WR(HW_MCG_C1_RD() & ~(v)))
bogdanm	82:6473597d706e	92	#define HW_MCG_C1_TOG(v) (HW_MCG_C1_WR(HW_MCG_C1_RD() ^ (v)))
bogdanm	82:6473597d706e	93	#endif
bogdanm	82:6473597d706e	94	//@}
bogdanm	82:6473597d706e	95
bogdanm	82:6473597d706e	96	/*
bogdanm	82:6473597d706e	97	* Constants & macros for individual MCG_C1 bitfields
bogdanm	82:6473597d706e	98	*/
bogdanm	82:6473597d706e	99
bogdanm	82:6473597d706e	100	/*!
bogdanm	82:6473597d706e	101	* @name Register MCG_C1, field IREFSTEN[0] (RW)
bogdanm	82:6473597d706e	102	*
bogdanm	82:6473597d706e	103	* Controls whether or not the internal reference clock remains enabled when the
bogdanm	82:6473597d706e	104	* MCG enters Stop mode.
bogdanm	82:6473597d706e	105	*
bogdanm	82:6473597d706e	106	* Values:
bogdanm	82:6473597d706e	107	* - 0 - Internal reference clock is disabled in Stop mode.
bogdanm	82:6473597d706e	108	* - 1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
bogdanm	82:6473597d706e	109	* if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
bogdanm	82:6473597d706e	110	*/
bogdanm	82:6473597d706e	111	//@{
bogdanm	82:6473597d706e	112	#define BP_MCG_C1_IREFSTEN (0U) //!< Bit position for MCG_C1_IREFSTEN.
bogdanm	82:6473597d706e	113	#define BM_MCG_C1_IREFSTEN (0x01U) //!< Bit mask for MCG_C1_IREFSTEN.
bogdanm	82:6473597d706e	114	#define BS_MCG_C1_IREFSTEN (1U) //!< Bit field size in bits for MCG_C1_IREFSTEN.
bogdanm	82:6473597d706e	115
bogdanm	82:6473597d706e	116	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	117	//! @brief Read current value of the MCG_C1_IREFSTEN field.
bogdanm	82:6473597d706e	118	#define BR_MCG_C1_IREFSTEN (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFSTEN))
bogdanm	82:6473597d706e	119	#endif
bogdanm	82:6473597d706e	120
bogdanm	82:6473597d706e	121	//! @brief Format value for bitfield MCG_C1_IREFSTEN.
bogdanm	82:6473597d706e	122	#define BF_MCG_C1_IREFSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IREFSTEN), uint8_t) & BM_MCG_C1_IREFSTEN)
bogdanm	82:6473597d706e	123
bogdanm	82:6473597d706e	124	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	125	//! @brief Set the IREFSTEN field to a new value.
bogdanm	82:6473597d706e	126	#define BW_MCG_C1_IREFSTEN(v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFSTEN) = (v))
bogdanm	82:6473597d706e	127	#endif
bogdanm	82:6473597d706e	128	//@}
bogdanm	82:6473597d706e	129
bogdanm	82:6473597d706e	130	/*!
bogdanm	82:6473597d706e	131	* @name Register MCG_C1, field IRCLKEN[1] (RW)
bogdanm	82:6473597d706e	132	*
bogdanm	82:6473597d706e	133	* Enables the internal reference clock for use as MCGIRCLK.
bogdanm	82:6473597d706e	134	*
bogdanm	82:6473597d706e	135	* Values:
bogdanm	82:6473597d706e	136	* - 0 - MCGIRCLK inactive.
bogdanm	82:6473597d706e	137	* - 1 - MCGIRCLK active.
bogdanm	82:6473597d706e	138	*/
bogdanm	82:6473597d706e	139	//@{
bogdanm	82:6473597d706e	140	#define BP_MCG_C1_IRCLKEN (1U) //!< Bit position for MCG_C1_IRCLKEN.
bogdanm	82:6473597d706e	141	#define BM_MCG_C1_IRCLKEN (0x02U) //!< Bit mask for MCG_C1_IRCLKEN.
bogdanm	82:6473597d706e	142	#define BS_MCG_C1_IRCLKEN (1U) //!< Bit field size in bits for MCG_C1_IRCLKEN.
bogdanm	82:6473597d706e	143
bogdanm	82:6473597d706e	144	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	145	//! @brief Read current value of the MCG_C1_IRCLKEN field.
bogdanm	82:6473597d706e	146	#define BR_MCG_C1_IRCLKEN (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IRCLKEN))
bogdanm	82:6473597d706e	147	#endif
bogdanm	82:6473597d706e	148
bogdanm	82:6473597d706e	149	//! @brief Format value for bitfield MCG_C1_IRCLKEN.
bogdanm	82:6473597d706e	150	#define BF_MCG_C1_IRCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IRCLKEN), uint8_t) & BM_MCG_C1_IRCLKEN)
bogdanm	82:6473597d706e	151
bogdanm	82:6473597d706e	152	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	153	//! @brief Set the IRCLKEN field to a new value.
bogdanm	82:6473597d706e	154	#define BW_MCG_C1_IRCLKEN(v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IRCLKEN) = (v))
bogdanm	82:6473597d706e	155	#endif
bogdanm	82:6473597d706e	156	//@}
bogdanm	82:6473597d706e	157
bogdanm	82:6473597d706e	158	/*!
bogdanm	82:6473597d706e	159	* @name Register MCG_C1, field IREFS[2] (RW)
bogdanm	82:6473597d706e	160	*
bogdanm	82:6473597d706e	161	* Selects the reference clock source for the FLL.
bogdanm	82:6473597d706e	162	*
bogdanm	82:6473597d706e	163	* Values:
bogdanm	82:6473597d706e	164	* - 0 - External reference clock is selected.
bogdanm	82:6473597d706e	165	* - 1 - The slow internal reference clock is selected.
bogdanm	82:6473597d706e	166	*/
bogdanm	82:6473597d706e	167	//@{
bogdanm	82:6473597d706e	168	#define BP_MCG_C1_IREFS (2U) //!< Bit position for MCG_C1_IREFS.
bogdanm	82:6473597d706e	169	#define BM_MCG_C1_IREFS (0x04U) //!< Bit mask for MCG_C1_IREFS.
bogdanm	82:6473597d706e	170	#define BS_MCG_C1_IREFS (1U) //!< Bit field size in bits for MCG_C1_IREFS.
bogdanm	82:6473597d706e	171
bogdanm	82:6473597d706e	172	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	173	//! @brief Read current value of the MCG_C1_IREFS field.
bogdanm	82:6473597d706e	174	#define BR_MCG_C1_IREFS (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFS))
bogdanm	82:6473597d706e	175	#endif
bogdanm	82:6473597d706e	176
bogdanm	82:6473597d706e	177	//! @brief Format value for bitfield MCG_C1_IREFS.
bogdanm	82:6473597d706e	178	#define BF_MCG_C1_IREFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IREFS), uint8_t) & BM_MCG_C1_IREFS)
bogdanm	82:6473597d706e	179
bogdanm	82:6473597d706e	180	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	181	//! @brief Set the IREFS field to a new value.
bogdanm	82:6473597d706e	182	#define BW_MCG_C1_IREFS(v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFS) = (v))
bogdanm	82:6473597d706e	183	#endif
bogdanm	82:6473597d706e	184	//@}
bogdanm	82:6473597d706e	185
bogdanm	82:6473597d706e	186	/*!
bogdanm	82:6473597d706e	187	* @name Register MCG_C1, field FRDIV[5:3] (RW)
bogdanm	82:6473597d706e	188	*
bogdanm	82:6473597d706e	189	* Selects the amount to divide down the external reference clock for the FLL.
bogdanm	82:6473597d706e	190	* The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
bogdanm	82:6473597d706e	191	* required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is
bogdanm	82:6473597d706e	192	* not required to meet this range, but it is recommended in the cases when trying
bogdanm	82:6473597d706e	193	* to enter a FLL mode from FBE).
bogdanm	82:6473597d706e	194	*
bogdanm	82:6473597d706e	195	* Values:
bogdanm	82:6473597d706e	196	* - 000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
bogdanm	82:6473597d706e	197	* values, Divide Factor is 32.
bogdanm	82:6473597d706e	198	* - 001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
bogdanm	82:6473597d706e	199	* values, Divide Factor is 64.
bogdanm	82:6473597d706e	200	* - 010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
bogdanm	82:6473597d706e	201	* values, Divide Factor is 128.
bogdanm	82:6473597d706e	202	* - 011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
bogdanm	82:6473597d706e	203	* values, Divide Factor is 256.
bogdanm	82:6473597d706e	204	* - 100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
bogdanm	82:6473597d706e	205	* values, Divide Factor is 512.
bogdanm	82:6473597d706e	206	* - 101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
bogdanm	82:6473597d706e	207	* values, Divide Factor is 1024.
bogdanm	82:6473597d706e	208	* - 110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
bogdanm	82:6473597d706e	209	* values, Divide Factor is 1280 .
bogdanm	82:6473597d706e	210	* - 111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE
bogdanm	82:6473597d706e	211	* values, Divide Factor is 1536 .
bogdanm	82:6473597d706e	212	*/
bogdanm	82:6473597d706e	213	//@{
bogdanm	82:6473597d706e	214	#define BP_MCG_C1_FRDIV (3U) //!< Bit position for MCG_C1_FRDIV.
bogdanm	82:6473597d706e	215	#define BM_MCG_C1_FRDIV (0x38U) //!< Bit mask for MCG_C1_FRDIV.
bogdanm	82:6473597d706e	216	#define BS_MCG_C1_FRDIV (3U) //!< Bit field size in bits for MCG_C1_FRDIV.
bogdanm	82:6473597d706e	217
bogdanm	82:6473597d706e	218	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	219	//! @brief Read current value of the MCG_C1_FRDIV field.
bogdanm	82:6473597d706e	220	#define BR_MCG_C1_FRDIV (HW_MCG_C1.B.FRDIV)
bogdanm	82:6473597d706e	221	#endif
bogdanm	82:6473597d706e	222
bogdanm	82:6473597d706e	223	//! @brief Format value for bitfield MCG_C1_FRDIV.
bogdanm	82:6473597d706e	224	#define BF_MCG_C1_FRDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_FRDIV), uint8_t) & BM_MCG_C1_FRDIV)
bogdanm	82:6473597d706e	225
bogdanm	82:6473597d706e	226	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	227	//! @brief Set the FRDIV field to a new value.
bogdanm	82:6473597d706e	228	#define BW_MCG_C1_FRDIV(v) (HW_MCG_C1_WR((HW_MCG_C1_RD() & ~BM_MCG_C1_FRDIV) \| BF_MCG_C1_FRDIV(v)))
bogdanm	82:6473597d706e	229	#endif
bogdanm	82:6473597d706e	230	//@}
bogdanm	82:6473597d706e	231
bogdanm	82:6473597d706e	232	/*!
bogdanm	82:6473597d706e	233	* @name Register MCG_C1, field CLKS[7:6] (RW)
bogdanm	82:6473597d706e	234	*
bogdanm	82:6473597d706e	235	* Selects the clock source for MCGOUTCLK .
bogdanm	82:6473597d706e	236	*
bogdanm	82:6473597d706e	237	* Values:
bogdanm	82:6473597d706e	238	* - 00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control
bogdanm	82:6473597d706e	239	* bit).
bogdanm	82:6473597d706e	240	* - 01 - Encoding 1 - Internal reference clock is selected.
bogdanm	82:6473597d706e	241	* - 10 - Encoding 2 - External reference clock is selected.
bogdanm	82:6473597d706e	242	* - 11 - Encoding 3 - Reserved.
bogdanm	82:6473597d706e	243	*/
bogdanm	82:6473597d706e	244	//@{
bogdanm	82:6473597d706e	245	#define BP_MCG_C1_CLKS (6U) //!< Bit position for MCG_C1_CLKS.
bogdanm	82:6473597d706e	246	#define BM_MCG_C1_CLKS (0xC0U) //!< Bit mask for MCG_C1_CLKS.
bogdanm	82:6473597d706e	247	#define BS_MCG_C1_CLKS (2U) //!< Bit field size in bits for MCG_C1_CLKS.
bogdanm	82:6473597d706e	248
bogdanm	82:6473597d706e	249	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	250	//! @brief Read current value of the MCG_C1_CLKS field.
bogdanm	82:6473597d706e	251	#define BR_MCG_C1_CLKS (HW_MCG_C1.B.CLKS)
bogdanm	82:6473597d706e	252	#endif
bogdanm	82:6473597d706e	253
bogdanm	82:6473597d706e	254	//! @brief Format value for bitfield MCG_C1_CLKS.
bogdanm	82:6473597d706e	255	#define BF_MCG_C1_CLKS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_CLKS), uint8_t) & BM_MCG_C1_CLKS)
bogdanm	82:6473597d706e	256
bogdanm	82:6473597d706e	257	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	258	//! @brief Set the CLKS field to a new value.
bogdanm	82:6473597d706e	259	#define BW_MCG_C1_CLKS(v) (HW_MCG_C1_WR((HW_MCG_C1_RD() & ~BM_MCG_C1_CLKS) \| BF_MCG_C1_CLKS(v)))
bogdanm	82:6473597d706e	260	#endif
bogdanm	82:6473597d706e	261	//@}
bogdanm	82:6473597d706e	262
bogdanm	82:6473597d706e	263	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	264	// HW_MCG_C2 - MCG Control 2 Register
bogdanm	82:6473597d706e	265	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	266
bogdanm	82:6473597d706e	267	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	268	/*!
bogdanm	82:6473597d706e	269	* @brief HW_MCG_C2 - MCG Control 2 Register (RW)
bogdanm	82:6473597d706e	270	*
bogdanm	82:6473597d706e	271	* Reset value: 0x80U
bogdanm	82:6473597d706e	272	*/
bogdanm	82:6473597d706e	273	typedef union _hw_mcg_c2
bogdanm	82:6473597d706e	274	{
bogdanm	82:6473597d706e	275	uint8_t U;
bogdanm	82:6473597d706e	276	struct _hw_mcg_c2_bitfields
bogdanm	82:6473597d706e	277	{
bogdanm	82:6473597d706e	278	uint8_t IRCS : 1; //!< [0] Internal Reference Clock Select
bogdanm	82:6473597d706e	279	uint8_t LP : 1; //!< [1] Low Power Select
bogdanm	82:6473597d706e	280	uint8_t EREFS : 1; //!< [2] External Reference Select
bogdanm	82:6473597d706e	281	uint8_t HGO : 1; //!< [3] High Gain Oscillator Select
bogdanm	82:6473597d706e	282	uint8_t RANGE : 2; //!< [5:4] Frequency Range Select
bogdanm	82:6473597d706e	283	uint8_t FCFTRIM : 1; //!< [6] Fast Internal Reference Clock Fine Trim
bogdanm	82:6473597d706e	284	uint8_t LOCRE0 : 1; //!< [7] Loss of Clock Reset Enable
bogdanm	82:6473597d706e	285	} B;
bogdanm	82:6473597d706e	286	} hw_mcg_c2_t;
bogdanm	82:6473597d706e	287	#endif
bogdanm	82:6473597d706e	288
bogdanm	82:6473597d706e	289	/*!
bogdanm	82:6473597d706e	290	* @name Constants and macros for entire MCG_C2 register
bogdanm	82:6473597d706e	291	*/
bogdanm	82:6473597d706e	292	//@{
bogdanm	82:6473597d706e	293	#define HW_MCG_C2_ADDR (REGS_MCG_BASE + 0x1U)
bogdanm	82:6473597d706e	294
bogdanm	82:6473597d706e	295	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	296	#define HW_MCG_C2 ((__IO hw_mcg_c2_t ) HW_MCG_C2_ADDR)
bogdanm	82:6473597d706e	297	#define HW_MCG_C2_RD() (HW_MCG_C2.U)
bogdanm	82:6473597d706e	298	#define HW_MCG_C2_WR(v) (HW_MCG_C2.U = (v))
bogdanm	82:6473597d706e	299	#define HW_MCG_C2_SET(v) (HW_MCG_C2_WR(HW_MCG_C2_RD() \| (v)))
bogdanm	82:6473597d706e	300	#define HW_MCG_C2_CLR(v) (HW_MCG_C2_WR(HW_MCG_C2_RD() & ~(v)))
bogdanm	82:6473597d706e	301	#define HW_MCG_C2_TOG(v) (HW_MCG_C2_WR(HW_MCG_C2_RD() ^ (v)))
bogdanm	82:6473597d706e	302	#endif
bogdanm	82:6473597d706e	303	//@}
bogdanm	82:6473597d706e	304
bogdanm	82:6473597d706e	305	/*
bogdanm	82:6473597d706e	306	* Constants & macros for individual MCG_C2 bitfields
bogdanm	82:6473597d706e	307	*/
bogdanm	82:6473597d706e	308
bogdanm	82:6473597d706e	309	/*!
bogdanm	82:6473597d706e	310	* @name Register MCG_C2, field IRCS[0] (RW)
bogdanm	82:6473597d706e	311	*
bogdanm	82:6473597d706e	312	* Selects between the fast or slow internal reference clock source.
bogdanm	82:6473597d706e	313	*
bogdanm	82:6473597d706e	314	* Values:
bogdanm	82:6473597d706e	315	* - 0 - Slow internal reference clock selected.
bogdanm	82:6473597d706e	316	* - 1 - Fast internal reference clock selected.
bogdanm	82:6473597d706e	317	*/
bogdanm	82:6473597d706e	318	//@{
bogdanm	82:6473597d706e	319	#define BP_MCG_C2_IRCS (0U) //!< Bit position for MCG_C2_IRCS.
bogdanm	82:6473597d706e	320	#define BM_MCG_C2_IRCS (0x01U) //!< Bit mask for MCG_C2_IRCS.
bogdanm	82:6473597d706e	321	#define BS_MCG_C2_IRCS (1U) //!< Bit field size in bits for MCG_C2_IRCS.
bogdanm	82:6473597d706e	322
bogdanm	82:6473597d706e	323	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	324	//! @brief Read current value of the MCG_C2_IRCS field.
bogdanm	82:6473597d706e	325	#define BR_MCG_C2_IRCS (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_IRCS))
bogdanm	82:6473597d706e	326	#endif
bogdanm	82:6473597d706e	327
bogdanm	82:6473597d706e	328	//! @brief Format value for bitfield MCG_C2_IRCS.
bogdanm	82:6473597d706e	329	#define BF_MCG_C2_IRCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_IRCS), uint8_t) & BM_MCG_C2_IRCS)
bogdanm	82:6473597d706e	330
bogdanm	82:6473597d706e	331	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	332	//! @brief Set the IRCS field to a new value.
bogdanm	82:6473597d706e	333	#define BW_MCG_C2_IRCS(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_IRCS) = (v))
bogdanm	82:6473597d706e	334	#endif
bogdanm	82:6473597d706e	335	//@}
bogdanm	82:6473597d706e	336
bogdanm	82:6473597d706e	337	/*!
bogdanm	82:6473597d706e	338	* @name Register MCG_C2, field LP[1] (RW)
bogdanm	82:6473597d706e	339	*
bogdanm	82:6473597d706e	340	* Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
bogdanm	82:6473597d706e	341	* PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
bogdanm	82:6473597d706e	342	* FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
bogdanm	82:6473597d706e	343	* other MCG mode, LP bit has no affect.
bogdanm	82:6473597d706e	344	*
bogdanm	82:6473597d706e	345	* Values:
bogdanm	82:6473597d706e	346	* - 0 - FLL or PLL is not disabled in bypass modes.
bogdanm	82:6473597d706e	347	* - 1 - FLL or PLL is disabled in bypass modes (lower power)
bogdanm	82:6473597d706e	348	*/
bogdanm	82:6473597d706e	349	//@{
bogdanm	82:6473597d706e	350	#define BP_MCG_C2_LP (1U) //!< Bit position for MCG_C2_LP.
bogdanm	82:6473597d706e	351	#define BM_MCG_C2_LP (0x02U) //!< Bit mask for MCG_C2_LP.
bogdanm	82:6473597d706e	352	#define BS_MCG_C2_LP (1U) //!< Bit field size in bits for MCG_C2_LP.
bogdanm	82:6473597d706e	353
bogdanm	82:6473597d706e	354	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	355	//! @brief Read current value of the MCG_C2_LP field.
bogdanm	82:6473597d706e	356	#define BR_MCG_C2_LP (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LP))
bogdanm	82:6473597d706e	357	#endif
bogdanm	82:6473597d706e	358
bogdanm	82:6473597d706e	359	//! @brief Format value for bitfield MCG_C2_LP.
bogdanm	82:6473597d706e	360	#define BF_MCG_C2_LP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_LP), uint8_t) & BM_MCG_C2_LP)
bogdanm	82:6473597d706e	361
bogdanm	82:6473597d706e	362	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	363	//! @brief Set the LP field to a new value.
bogdanm	82:6473597d706e	364	#define BW_MCG_C2_LP(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LP) = (v))
bogdanm	82:6473597d706e	365	#endif
bogdanm	82:6473597d706e	366	//@}
bogdanm	82:6473597d706e	367
bogdanm	82:6473597d706e	368	/*!
bogdanm	82:6473597d706e	369	* @name Register MCG_C2, field EREFS[2] (RW)
bogdanm	82:6473597d706e	370	*
bogdanm	82:6473597d706e	371	* Selects the source for the external reference clock. See the Oscillator (OSC)
bogdanm	82:6473597d706e	372	* chapter for more details.
bogdanm	82:6473597d706e	373	*
bogdanm	82:6473597d706e	374	* Values:
bogdanm	82:6473597d706e	375	* - 0 - External reference clock requested.
bogdanm	82:6473597d706e	376	* - 1 - Oscillator requested.
bogdanm	82:6473597d706e	377	*/
bogdanm	82:6473597d706e	378	//@{
bogdanm	82:6473597d706e	379	#define BP_MCG_C2_EREFS (2U) //!< Bit position for MCG_C2_EREFS.
bogdanm	82:6473597d706e	380	#define BM_MCG_C2_EREFS (0x04U) //!< Bit mask for MCG_C2_EREFS.
bogdanm	82:6473597d706e	381	#define BS_MCG_C2_EREFS (1U) //!< Bit field size in bits for MCG_C2_EREFS.
bogdanm	82:6473597d706e	382
bogdanm	82:6473597d706e	383	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	384	//! @brief Read current value of the MCG_C2_EREFS field.
bogdanm	82:6473597d706e	385	#define BR_MCG_C2_EREFS (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_EREFS))
bogdanm	82:6473597d706e	386	#endif
bogdanm	82:6473597d706e	387
bogdanm	82:6473597d706e	388	//! @brief Format value for bitfield MCG_C2_EREFS.
bogdanm	82:6473597d706e	389	#define BF_MCG_C2_EREFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_EREFS), uint8_t) & BM_MCG_C2_EREFS)
bogdanm	82:6473597d706e	390
bogdanm	82:6473597d706e	391	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	392	//! @brief Set the EREFS field to a new value.
bogdanm	82:6473597d706e	393	#define BW_MCG_C2_EREFS(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_EREFS) = (v))
bogdanm	82:6473597d706e	394	#endif
bogdanm	82:6473597d706e	395	//@}
bogdanm	82:6473597d706e	396
bogdanm	82:6473597d706e	397	/*!
bogdanm	82:6473597d706e	398	* @name Register MCG_C2, field HGO[3] (RW)
bogdanm	82:6473597d706e	399	*
bogdanm	82:6473597d706e	400	* Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
bogdanm	82:6473597d706e	401	* chapter for more details.
bogdanm	82:6473597d706e	402	*
bogdanm	82:6473597d706e	403	* Values:
bogdanm	82:6473597d706e	404	* - 0 - Configure crystal oscillator for low-power operation.
bogdanm	82:6473597d706e	405	* - 1 - Configure crystal oscillator for high-gain operation.
bogdanm	82:6473597d706e	406	*/
bogdanm	82:6473597d706e	407	//@{
bogdanm	82:6473597d706e	408	#define BP_MCG_C2_HGO (3U) //!< Bit position for MCG_C2_HGO.
bogdanm	82:6473597d706e	409	#define BM_MCG_C2_HGO (0x08U) //!< Bit mask for MCG_C2_HGO.
bogdanm	82:6473597d706e	410	#define BS_MCG_C2_HGO (1U) //!< Bit field size in bits for MCG_C2_HGO.
bogdanm	82:6473597d706e	411
bogdanm	82:6473597d706e	412	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	413	//! @brief Read current value of the MCG_C2_HGO field.
bogdanm	82:6473597d706e	414	#define BR_MCG_C2_HGO (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_HGO))
bogdanm	82:6473597d706e	415	#endif
bogdanm	82:6473597d706e	416
bogdanm	82:6473597d706e	417	//! @brief Format value for bitfield MCG_C2_HGO.
bogdanm	82:6473597d706e	418	#define BF_MCG_C2_HGO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_HGO), uint8_t) & BM_MCG_C2_HGO)
bogdanm	82:6473597d706e	419
bogdanm	82:6473597d706e	420	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	421	//! @brief Set the HGO field to a new value.
bogdanm	82:6473597d706e	422	#define BW_MCG_C2_HGO(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_HGO) = (v))
bogdanm	82:6473597d706e	423	#endif
bogdanm	82:6473597d706e	424	//@}
bogdanm	82:6473597d706e	425
bogdanm	82:6473597d706e	426	/*!
bogdanm	82:6473597d706e	427	* @name Register MCG_C2, field RANGE[5:4] (RW)
bogdanm	82:6473597d706e	428	*
bogdanm	82:6473597d706e	429	* Selects the frequency range for the crystal oscillator or external clock
bogdanm	82:6473597d706e	430	* source. See the Oscillator (OSC) chapter for more details and the device data
bogdanm	82:6473597d706e	431	* sheet for the frequency ranges used.
bogdanm	82:6473597d706e	432	*
bogdanm	82:6473597d706e	433	* Values:
bogdanm	82:6473597d706e	434	* - 00 - Encoding 0 - Low frequency range selected for the crystal oscillator .
bogdanm	82:6473597d706e	435	* - 01 - Encoding 1 - High frequency range selected for the crystal oscillator .
bogdanm	82:6473597d706e	436	*/
bogdanm	82:6473597d706e	437	//@{
bogdanm	82:6473597d706e	438	#define BP_MCG_C2_RANGE (4U) //!< Bit position for MCG_C2_RANGE.
bogdanm	82:6473597d706e	439	#define BM_MCG_C2_RANGE (0x30U) //!< Bit mask for MCG_C2_RANGE.
bogdanm	82:6473597d706e	440	#define BS_MCG_C2_RANGE (2U) //!< Bit field size in bits for MCG_C2_RANGE.
bogdanm	82:6473597d706e	441
bogdanm	82:6473597d706e	442	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	443	//! @brief Read current value of the MCG_C2_RANGE field.
bogdanm	82:6473597d706e	444	#define BR_MCG_C2_RANGE (HW_MCG_C2.B.RANGE)
bogdanm	82:6473597d706e	445	#endif
bogdanm	82:6473597d706e	446
bogdanm	82:6473597d706e	447	//! @brief Format value for bitfield MCG_C2_RANGE.
bogdanm	82:6473597d706e	448	#define BF_MCG_C2_RANGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_RANGE), uint8_t) & BM_MCG_C2_RANGE)
bogdanm	82:6473597d706e	449
bogdanm	82:6473597d706e	450	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	451	//! @brief Set the RANGE field to a new value.
bogdanm	82:6473597d706e	452	#define BW_MCG_C2_RANGE(v) (HW_MCG_C2_WR((HW_MCG_C2_RD() & ~BM_MCG_C2_RANGE) \| BF_MCG_C2_RANGE(v)))
bogdanm	82:6473597d706e	453	#endif
bogdanm	82:6473597d706e	454	//@}
bogdanm	82:6473597d706e	455
bogdanm	82:6473597d706e	456	/*!
bogdanm	82:6473597d706e	457	* @name Register MCG_C2, field FCFTRIM[6] (RW)
bogdanm	82:6473597d706e	458	*
bogdanm	82:6473597d706e	459	* FCFTRIM controls the smallest adjustment of the fast internal reference clock
bogdanm	82:6473597d706e	460	* frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
bogdanm	82:6473597d706e	461	* decreases the period by the smallest amount possible. If an FCFTRIM value stored in
bogdanm	82:6473597d706e	462	* nonvolatile memory is to be used, it is your responsibility to copy that value
bogdanm	82:6473597d706e	463	* from the nonvolatile memory location to this bit.
bogdanm	82:6473597d706e	464	*/
bogdanm	82:6473597d706e	465	//@{
bogdanm	82:6473597d706e	466	#define BP_MCG_C2_FCFTRIM (6U) //!< Bit position for MCG_C2_FCFTRIM.
bogdanm	82:6473597d706e	467	#define BM_MCG_C2_FCFTRIM (0x40U) //!< Bit mask for MCG_C2_FCFTRIM.
bogdanm	82:6473597d706e	468	#define BS_MCG_C2_FCFTRIM (1U) //!< Bit field size in bits for MCG_C2_FCFTRIM.
bogdanm	82:6473597d706e	469
bogdanm	82:6473597d706e	470	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	471	//! @brief Read current value of the MCG_C2_FCFTRIM field.
bogdanm	82:6473597d706e	472	#define BR_MCG_C2_FCFTRIM (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_FCFTRIM))
bogdanm	82:6473597d706e	473	#endif
bogdanm	82:6473597d706e	474
bogdanm	82:6473597d706e	475	//! @brief Format value for bitfield MCG_C2_FCFTRIM.
bogdanm	82:6473597d706e	476	#define BF_MCG_C2_FCFTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_FCFTRIM), uint8_t) & BM_MCG_C2_FCFTRIM)
bogdanm	82:6473597d706e	477
bogdanm	82:6473597d706e	478	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	479	//! @brief Set the FCFTRIM field to a new value.
bogdanm	82:6473597d706e	480	#define BW_MCG_C2_FCFTRIM(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_FCFTRIM) = (v))
bogdanm	82:6473597d706e	481	#endif
bogdanm	82:6473597d706e	482	//@}
bogdanm	82:6473597d706e	483
bogdanm	82:6473597d706e	484	/*!
bogdanm	82:6473597d706e	485	* @name Register MCG_C2, field LOCRE0[7] (RW)
bogdanm	82:6473597d706e	486	*
bogdanm	82:6473597d706e	487	* Determines whether an interrupt or a reset request is made following a loss
bogdanm	82:6473597d706e	488	* of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
bogdanm	82:6473597d706e	489	* set.
bogdanm	82:6473597d706e	490	*
bogdanm	82:6473597d706e	491	* Values:
bogdanm	82:6473597d706e	492	* - 0 - Interrupt request is generated on a loss of OSC0 external reference
bogdanm	82:6473597d706e	493	* clock.
bogdanm	82:6473597d706e	494	* - 1 - Generate a reset request on a loss of OSC0 external reference clock.
bogdanm	82:6473597d706e	495	*/
bogdanm	82:6473597d706e	496	//@{
bogdanm	82:6473597d706e	497	#define BP_MCG_C2_LOCRE0 (7U) //!< Bit position for MCG_C2_LOCRE0.
bogdanm	82:6473597d706e	498	#define BM_MCG_C2_LOCRE0 (0x80U) //!< Bit mask for MCG_C2_LOCRE0.
bogdanm	82:6473597d706e	499	#define BS_MCG_C2_LOCRE0 (1U) //!< Bit field size in bits for MCG_C2_LOCRE0.
bogdanm	82:6473597d706e	500
bogdanm	82:6473597d706e	501	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	502	//! @brief Read current value of the MCG_C2_LOCRE0 field.
bogdanm	82:6473597d706e	503	#define BR_MCG_C2_LOCRE0 (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LOCRE0))
bogdanm	82:6473597d706e	504	#endif
bogdanm	82:6473597d706e	505
bogdanm	82:6473597d706e	506	//! @brief Format value for bitfield MCG_C2_LOCRE0.
bogdanm	82:6473597d706e	507	#define BF_MCG_C2_LOCRE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_LOCRE0), uint8_t) & BM_MCG_C2_LOCRE0)
bogdanm	82:6473597d706e	508
bogdanm	82:6473597d706e	509	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	510	//! @brief Set the LOCRE0 field to a new value.
bogdanm	82:6473597d706e	511	#define BW_MCG_C2_LOCRE0(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LOCRE0) = (v))
bogdanm	82:6473597d706e	512	#endif
bogdanm	82:6473597d706e	513	//@}
bogdanm	82:6473597d706e	514
bogdanm	82:6473597d706e	515	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	516	// HW_MCG_C3 - MCG Control 3 Register
bogdanm	82:6473597d706e	517	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	518
bogdanm	82:6473597d706e	519	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	520	/*!
bogdanm	82:6473597d706e	521	* @brief HW_MCG_C3 - MCG Control 3 Register (RW)
bogdanm	82:6473597d706e	522	*
bogdanm	82:6473597d706e	523	* Reset value: 0x00U
bogdanm	82:6473597d706e	524	*/
bogdanm	82:6473597d706e	525	typedef union _hw_mcg_c3
bogdanm	82:6473597d706e	526	{
bogdanm	82:6473597d706e	527	uint8_t U;
bogdanm	82:6473597d706e	528	struct _hw_mcg_c3_bitfields
bogdanm	82:6473597d706e	529	{
bogdanm	82:6473597d706e	530	uint8_t SCTRIM : 8; //!< [7:0] Slow Internal Reference Clock Trim
bogdanm	82:6473597d706e	531	//! Setting
bogdanm	82:6473597d706e	532	} B;
bogdanm	82:6473597d706e	533	} hw_mcg_c3_t;
bogdanm	82:6473597d706e	534	#endif
bogdanm	82:6473597d706e	535
bogdanm	82:6473597d706e	536	/*!
bogdanm	82:6473597d706e	537	* @name Constants and macros for entire MCG_C3 register
bogdanm	82:6473597d706e	538	*/
bogdanm	82:6473597d706e	539	//@{
bogdanm	82:6473597d706e	540	#define HW_MCG_C3_ADDR (REGS_MCG_BASE + 0x2U)
bogdanm	82:6473597d706e	541
bogdanm	82:6473597d706e	542	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	543	#define HW_MCG_C3 ((__IO hw_mcg_c3_t ) HW_MCG_C3_ADDR)
bogdanm	82:6473597d706e	544	#define HW_MCG_C3_RD() (HW_MCG_C3.U)
bogdanm	82:6473597d706e	545	#define HW_MCG_C3_WR(v) (HW_MCG_C3.U = (v))
bogdanm	82:6473597d706e	546	#define HW_MCG_C3_SET(v) (HW_MCG_C3_WR(HW_MCG_C3_RD() \| (v)))
bogdanm	82:6473597d706e	547	#define HW_MCG_C3_CLR(v) (HW_MCG_C3_WR(HW_MCG_C3_RD() & ~(v)))
bogdanm	82:6473597d706e	548	#define HW_MCG_C3_TOG(v) (HW_MCG_C3_WR(HW_MCG_C3_RD() ^ (v)))
bogdanm	82:6473597d706e	549	#endif
bogdanm	82:6473597d706e	550	//@}
bogdanm	82:6473597d706e	551
bogdanm	82:6473597d706e	552	/*
bogdanm	82:6473597d706e	553	* Constants & macros for individual MCG_C3 bitfields
bogdanm	82:6473597d706e	554	*/
bogdanm	82:6473597d706e	555
bogdanm	82:6473597d706e	556	/*!
bogdanm	82:6473597d706e	557	* @name Register MCG_C3, field SCTRIM[7:0] (RW)
bogdanm	82:6473597d706e	558	*
bogdanm	82:6473597d706e	559	* SCTRIM A value for SCTRIM is loaded during reset from a factory programmed
bogdanm	82:6473597d706e	560	* location. controls the slow internal reference clock frequency by controlling
bogdanm	82:6473597d706e	561	* the slow internal reference clock period. The SCTRIM bits are binary weighted,
bogdanm	82:6473597d706e	562	* that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
bogdanm	82:6473597d706e	563	* increases the period, and decreasing the value decreases the period. An additional
bogdanm	82:6473597d706e	564	* fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset,
bogdanm	82:6473597d706e	565	* this value is loaded with a factory trim value. If an SCTRIM value stored in
bogdanm	82:6473597d706e	566	* nonvolatile memory is to be used, it is your responsibility to copy that value
bogdanm	82:6473597d706e	567	* from the nonvolatile memory location to this register.
bogdanm	82:6473597d706e	568	*/
bogdanm	82:6473597d706e	569	//@{
bogdanm	82:6473597d706e	570	#define BP_MCG_C3_SCTRIM (0U) //!< Bit position for MCG_C3_SCTRIM.
bogdanm	82:6473597d706e	571	#define BM_MCG_C3_SCTRIM (0xFFU) //!< Bit mask for MCG_C3_SCTRIM.
bogdanm	82:6473597d706e	572	#define BS_MCG_C3_SCTRIM (8U) //!< Bit field size in bits for MCG_C3_SCTRIM.
bogdanm	82:6473597d706e	573
bogdanm	82:6473597d706e	574	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	575	//! @brief Read current value of the MCG_C3_SCTRIM field.
bogdanm	82:6473597d706e	576	#define BR_MCG_C3_SCTRIM (HW_MCG_C3.U)
bogdanm	82:6473597d706e	577	#endif
bogdanm	82:6473597d706e	578
bogdanm	82:6473597d706e	579	//! @brief Format value for bitfield MCG_C3_SCTRIM.
bogdanm	82:6473597d706e	580	#define BF_MCG_C3_SCTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C3_SCTRIM), uint8_t) & BM_MCG_C3_SCTRIM)
bogdanm	82:6473597d706e	581
bogdanm	82:6473597d706e	582	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	583	//! @brief Set the SCTRIM field to a new value.
bogdanm	82:6473597d706e	584	#define BW_MCG_C3_SCTRIM(v) (HW_MCG_C3_WR(v))
bogdanm	82:6473597d706e	585	#endif
bogdanm	82:6473597d706e	586	//@}
bogdanm	82:6473597d706e	587
bogdanm	82:6473597d706e	588	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	589	// HW_MCG_C4 - MCG Control 4 Register
bogdanm	82:6473597d706e	590	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	591
bogdanm	82:6473597d706e	592	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	593	/*!
bogdanm	82:6473597d706e	594	* @brief HW_MCG_C4 - MCG Control 4 Register (RW)
bogdanm	82:6473597d706e	595	*
bogdanm	82:6473597d706e	596	* Reset value: 0x00U
bogdanm	82:6473597d706e	597	*
bogdanm	82:6473597d706e	598	* Reset values for DRST and DMX32 bits are 0.
bogdanm	82:6473597d706e	599	*/
bogdanm	82:6473597d706e	600	typedef union _hw_mcg_c4
bogdanm	82:6473597d706e	601	{
bogdanm	82:6473597d706e	602	uint8_t U;
bogdanm	82:6473597d706e	603	struct _hw_mcg_c4_bitfields
bogdanm	82:6473597d706e	604	{
bogdanm	82:6473597d706e	605	uint8_t SCFTRIM : 1; //!< [0] Slow Internal Reference Clock Fine Trim
bogdanm	82:6473597d706e	606	uint8_t FCTRIM : 4; //!< [4:1] Fast Internal Reference Clock Trim
bogdanm	82:6473597d706e	607	//! Setting
bogdanm	82:6473597d706e	608	uint8_t DRST_DRS : 2; //!< [6:5] DCO Range Select
bogdanm	82:6473597d706e	609	uint8_t DMX32 : 1; //!< [7] DCO Maximum Frequency with 32.768 kHz
bogdanm	82:6473597d706e	610	//! Reference
bogdanm	82:6473597d706e	611	} B;
bogdanm	82:6473597d706e	612	} hw_mcg_c4_t;
bogdanm	82:6473597d706e	613	#endif
bogdanm	82:6473597d706e	614
bogdanm	82:6473597d706e	615	/*!
bogdanm	82:6473597d706e	616	* @name Constants and macros for entire MCG_C4 register
bogdanm	82:6473597d706e	617	*/
bogdanm	82:6473597d706e	618	//@{
bogdanm	82:6473597d706e	619	#define HW_MCG_C4_ADDR (REGS_MCG_BASE + 0x3U)
bogdanm	82:6473597d706e	620
bogdanm	82:6473597d706e	621	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	622	#define HW_MCG_C4 ((__IO hw_mcg_c4_t ) HW_MCG_C4_ADDR)
bogdanm	82:6473597d706e	623	#define HW_MCG_C4_RD() (HW_MCG_C4.U)
bogdanm	82:6473597d706e	624	#define HW_MCG_C4_WR(v) (HW_MCG_C4.U = (v))
bogdanm	82:6473597d706e	625	#define HW_MCG_C4_SET(v) (HW_MCG_C4_WR(HW_MCG_C4_RD() \| (v)))
bogdanm	82:6473597d706e	626	#define HW_MCG_C4_CLR(v) (HW_MCG_C4_WR(HW_MCG_C4_RD() & ~(v)))
bogdanm	82:6473597d706e	627	#define HW_MCG_C4_TOG(v) (HW_MCG_C4_WR(HW_MCG_C4_RD() ^ (v)))
bogdanm	82:6473597d706e	628	#endif
bogdanm	82:6473597d706e	629	//@}
bogdanm	82:6473597d706e	630
bogdanm	82:6473597d706e	631	/*
bogdanm	82:6473597d706e	632	* Constants & macros for individual MCG_C4 bitfields
bogdanm	82:6473597d706e	633	*/
bogdanm	82:6473597d706e	634
bogdanm	82:6473597d706e	635	/*!
bogdanm	82:6473597d706e	636	* @name Register MCG_C4, field SCFTRIM[0] (RW)
bogdanm	82:6473597d706e	637	*
bogdanm	82:6473597d706e	638	* SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
bogdanm	82:6473597d706e	639	* location . controls the smallest adjustment of the slow internal reference
bogdanm	82:6473597d706e	640	* clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM
bogdanm	82:6473597d706e	641	* decreases the period by the smallest amount possible. If an SCFTRIM value stored in
bogdanm	82:6473597d706e	642	* nonvolatile memory is to be used, it is your responsibility to copy that value
bogdanm	82:6473597d706e	643	* from the nonvolatile memory location to this bit.
bogdanm	82:6473597d706e	644	*/
bogdanm	82:6473597d706e	645	//@{
bogdanm	82:6473597d706e	646	#define BP_MCG_C4_SCFTRIM (0U) //!< Bit position for MCG_C4_SCFTRIM.
bogdanm	82:6473597d706e	647	#define BM_MCG_C4_SCFTRIM (0x01U) //!< Bit mask for MCG_C4_SCFTRIM.
bogdanm	82:6473597d706e	648	#define BS_MCG_C4_SCFTRIM (1U) //!< Bit field size in bits for MCG_C4_SCFTRIM.
bogdanm	82:6473597d706e	649
bogdanm	82:6473597d706e	650	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	651	//! @brief Read current value of the MCG_C4_SCFTRIM field.
bogdanm	82:6473597d706e	652	#define BR_MCG_C4_SCFTRIM (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_SCFTRIM))
bogdanm	82:6473597d706e	653	#endif
bogdanm	82:6473597d706e	654
bogdanm	82:6473597d706e	655	//! @brief Format value for bitfield MCG_C4_SCFTRIM.
bogdanm	82:6473597d706e	656	#define BF_MCG_C4_SCFTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_SCFTRIM), uint8_t) & BM_MCG_C4_SCFTRIM)
bogdanm	82:6473597d706e	657
bogdanm	82:6473597d706e	658	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	659	//! @brief Set the SCFTRIM field to a new value.
bogdanm	82:6473597d706e	660	#define BW_MCG_C4_SCFTRIM(v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_SCFTRIM) = (v))
bogdanm	82:6473597d706e	661	#endif
bogdanm	82:6473597d706e	662	//@}
bogdanm	82:6473597d706e	663
bogdanm	82:6473597d706e	664	/*!
bogdanm	82:6473597d706e	665	* @name Register MCG_C4, field FCTRIM[4:1] (RW)
bogdanm	82:6473597d706e	666	*
bogdanm	82:6473597d706e	667	* FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
bogdanm	82:6473597d706e	668	* location. controls the fast internal reference clock frequency by controlling
bogdanm	82:6473597d706e	669	* the fast internal reference clock period. The FCTRIM bits are binary weighted,
bogdanm	82:6473597d706e	670	* that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
bogdanm	82:6473597d706e	671	* increases the period, and decreasing the value decreases the period. If an
bogdanm	82:6473597d706e	672	* FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your
bogdanm	82:6473597d706e	673	* responsibility to copy that value from the nonvolatile memory location to this register.
bogdanm	82:6473597d706e	674	*/
bogdanm	82:6473597d706e	675	//@{
bogdanm	82:6473597d706e	676	#define BP_MCG_C4_FCTRIM (1U) //!< Bit position for MCG_C4_FCTRIM.
bogdanm	82:6473597d706e	677	#define BM_MCG_C4_FCTRIM (0x1EU) //!< Bit mask for MCG_C4_FCTRIM.
bogdanm	82:6473597d706e	678	#define BS_MCG_C4_FCTRIM (4U) //!< Bit field size in bits for MCG_C4_FCTRIM.
bogdanm	82:6473597d706e	679
bogdanm	82:6473597d706e	680	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	681	//! @brief Read current value of the MCG_C4_FCTRIM field.
bogdanm	82:6473597d706e	682	#define BR_MCG_C4_FCTRIM (HW_MCG_C4.B.FCTRIM)
bogdanm	82:6473597d706e	683	#endif
bogdanm	82:6473597d706e	684
bogdanm	82:6473597d706e	685	//! @brief Format value for bitfield MCG_C4_FCTRIM.
bogdanm	82:6473597d706e	686	#define BF_MCG_C4_FCTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_FCTRIM), uint8_t) & BM_MCG_C4_FCTRIM)
bogdanm	82:6473597d706e	687
bogdanm	82:6473597d706e	688	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	689	//! @brief Set the FCTRIM field to a new value.
bogdanm	82:6473597d706e	690	#define BW_MCG_C4_FCTRIM(v) (HW_MCG_C4_WR((HW_MCG_C4_RD() & ~BM_MCG_C4_FCTRIM) \| BF_MCG_C4_FCTRIM(v)))
bogdanm	82:6473597d706e	691	#endif
bogdanm	82:6473597d706e	692	//@}
bogdanm	82:6473597d706e	693
bogdanm	82:6473597d706e	694	/*!
bogdanm	82:6473597d706e	695	* @name Register MCG_C4, field DRST_DRS[6:5] (RW)
bogdanm	82:6473597d706e	696	*
bogdanm	82:6473597d706e	697	* The DRS bits select the frequency range for the FLL output, DCOOUT. When the
bogdanm	82:6473597d706e	698	* LP bit is set, writes to the DRS bits are ignored. The DRST read field
bogdanm	82:6473597d706e	699	* indicates the current frequency range for DCOOUT. The DRST field does not update
bogdanm	82:6473597d706e	700	* immediately after a write to the DRS field due to internal synchronization between
bogdanm	82:6473597d706e	701	* clock domains. See the DCO Frequency Range table for more details.
bogdanm	82:6473597d706e	702	*
bogdanm	82:6473597d706e	703	* Values:
bogdanm	82:6473597d706e	704	* - 00 - Encoding 0 - Low range (reset default).
bogdanm	82:6473597d706e	705	* - 01 - Encoding 1 - Mid range.
bogdanm	82:6473597d706e	706	* - 10 - Encoding 2 - Mid-high range.
bogdanm	82:6473597d706e	707	* - 11 - Encoding 3 - High range.
bogdanm	82:6473597d706e	708	*/
bogdanm	82:6473597d706e	709	//@{
bogdanm	82:6473597d706e	710	#define BP_MCG_C4_DRST_DRS (5U) //!< Bit position for MCG_C4_DRST_DRS.
bogdanm	82:6473597d706e	711	#define BM_MCG_C4_DRST_DRS (0x60U) //!< Bit mask for MCG_C4_DRST_DRS.
bogdanm	82:6473597d706e	712	#define BS_MCG_C4_DRST_DRS (2U) //!< Bit field size in bits for MCG_C4_DRST_DRS.
bogdanm	82:6473597d706e	713
bogdanm	82:6473597d706e	714	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	715	//! @brief Read current value of the MCG_C4_DRST_DRS field.
bogdanm	82:6473597d706e	716	#define BR_MCG_C4_DRST_DRS (HW_MCG_C4.B.DRST_DRS)
bogdanm	82:6473597d706e	717	#endif
bogdanm	82:6473597d706e	718
bogdanm	82:6473597d706e	719	//! @brief Format value for bitfield MCG_C4_DRST_DRS.
bogdanm	82:6473597d706e	720	#define BF_MCG_C4_DRST_DRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_DRST_DRS), uint8_t) & BM_MCG_C4_DRST_DRS)
bogdanm	82:6473597d706e	721
bogdanm	82:6473597d706e	722	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	723	//! @brief Set the DRST_DRS field to a new value.
bogdanm	82:6473597d706e	724	#define BW_MCG_C4_DRST_DRS(v) (HW_MCG_C4_WR((HW_MCG_C4_RD() & ~BM_MCG_C4_DRST_DRS) \| BF_MCG_C4_DRST_DRS(v)))
bogdanm	82:6473597d706e	725	#endif
bogdanm	82:6473597d706e	726	//@}
bogdanm	82:6473597d706e	727
bogdanm	82:6473597d706e	728	/*!
bogdanm	82:6473597d706e	729	* @name Register MCG_C4, field DMX32[7] (RW)
bogdanm	82:6473597d706e	730	*
bogdanm	82:6473597d706e	731	* The DMX32 bit controls whether the DCO frequency range is narrowed to its
bogdanm	82:6473597d706e	732	* maximum frequency with a 32.768 kHz reference. The following table identifies
bogdanm	82:6473597d706e	733	* settings for the DCO frequency range. The system clocks derived from this source
bogdanm	82:6473597d706e	734	* should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
bogdanm	82:6473597d706e	735	* Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
bogdanm	82:6473597d706e	736	* 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
bogdanm	82:6473597d706e	737	* 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
bogdanm	82:6473597d706e	738	* 80-100 MHz 1 32.768 kHz 2929 96 MHz
bogdanm	82:6473597d706e	739	*
bogdanm	82:6473597d706e	740	* Values:
bogdanm	82:6473597d706e	741	* - 0 - DCO has a default range of 25%.
bogdanm	82:6473597d706e	742	* - 1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
bogdanm	82:6473597d706e	743	*/
bogdanm	82:6473597d706e	744	//@{
bogdanm	82:6473597d706e	745	#define BP_MCG_C4_DMX32 (7U) //!< Bit position for MCG_C4_DMX32.
bogdanm	82:6473597d706e	746	#define BM_MCG_C4_DMX32 (0x80U) //!< Bit mask for MCG_C4_DMX32.
bogdanm	82:6473597d706e	747	#define BS_MCG_C4_DMX32 (1U) //!< Bit field size in bits for MCG_C4_DMX32.
bogdanm	82:6473597d706e	748
bogdanm	82:6473597d706e	749	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	750	//! @brief Read current value of the MCG_C4_DMX32 field.
bogdanm	82:6473597d706e	751	#define BR_MCG_C4_DMX32 (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_DMX32))
bogdanm	82:6473597d706e	752	#endif
bogdanm	82:6473597d706e	753
bogdanm	82:6473597d706e	754	//! @brief Format value for bitfield MCG_C4_DMX32.
bogdanm	82:6473597d706e	755	#define BF_MCG_C4_DMX32(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_DMX32), uint8_t) & BM_MCG_C4_DMX32)
bogdanm	82:6473597d706e	756
bogdanm	82:6473597d706e	757	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	758	//! @brief Set the DMX32 field to a new value.
bogdanm	82:6473597d706e	759	#define BW_MCG_C4_DMX32(v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_DMX32) = (v))
bogdanm	82:6473597d706e	760	#endif
bogdanm	82:6473597d706e	761	//@}
bogdanm	82:6473597d706e	762
bogdanm	82:6473597d706e	763	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	764	// HW_MCG_C5 - MCG Control 5 Register
bogdanm	82:6473597d706e	765	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	766
bogdanm	82:6473597d706e	767	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	768	/*!
bogdanm	82:6473597d706e	769	* @brief HW_MCG_C5 - MCG Control 5 Register (RW)
bogdanm	82:6473597d706e	770	*
bogdanm	82:6473597d706e	771	* Reset value: 0x00U
bogdanm	82:6473597d706e	772	*/
bogdanm	82:6473597d706e	773	typedef union _hw_mcg_c5
bogdanm	82:6473597d706e	774	{
bogdanm	82:6473597d706e	775	uint8_t U;
bogdanm	82:6473597d706e	776	struct _hw_mcg_c5_bitfields
bogdanm	82:6473597d706e	777	{
bogdanm	82:6473597d706e	778	uint8_t PRDIV0 : 5; //!< [4:0] PLL External Reference Divider
bogdanm	82:6473597d706e	779	uint8_t PLLSTEN0 : 1; //!< [5] PLL Stop Enable
bogdanm	82:6473597d706e	780	uint8_t PLLCLKEN0 : 1; //!< [6] PLL Clock Enable
bogdanm	82:6473597d706e	781	uint8_t RESERVED0 : 1; //!< [7]
bogdanm	82:6473597d706e	782	} B;
bogdanm	82:6473597d706e	783	} hw_mcg_c5_t;
bogdanm	82:6473597d706e	784	#endif
bogdanm	82:6473597d706e	785
bogdanm	82:6473597d706e	786	/*!
bogdanm	82:6473597d706e	787	* @name Constants and macros for entire MCG_C5 register
bogdanm	82:6473597d706e	788	*/
bogdanm	82:6473597d706e	789	//@{
bogdanm	82:6473597d706e	790	#define HW_MCG_C5_ADDR (REGS_MCG_BASE + 0x4U)
bogdanm	82:6473597d706e	791
bogdanm	82:6473597d706e	792	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	793	#define HW_MCG_C5 ((__IO hw_mcg_c5_t ) HW_MCG_C5_ADDR)
bogdanm	82:6473597d706e	794	#define HW_MCG_C5_RD() (HW_MCG_C5.U)
bogdanm	82:6473597d706e	795	#define HW_MCG_C5_WR(v) (HW_MCG_C5.U = (v))
bogdanm	82:6473597d706e	796	#define HW_MCG_C5_SET(v) (HW_MCG_C5_WR(HW_MCG_C5_RD() \| (v)))
bogdanm	82:6473597d706e	797	#define HW_MCG_C5_CLR(v) (HW_MCG_C5_WR(HW_MCG_C5_RD() & ~(v)))
bogdanm	82:6473597d706e	798	#define HW_MCG_C5_TOG(v) (HW_MCG_C5_WR(HW_MCG_C5_RD() ^ (v)))
bogdanm	82:6473597d706e	799	#endif
bogdanm	82:6473597d706e	800	//@}
bogdanm	82:6473597d706e	801
bogdanm	82:6473597d706e	802	/*
bogdanm	82:6473597d706e	803	* Constants & macros for individual MCG_C5 bitfields
bogdanm	82:6473597d706e	804	*/
bogdanm	82:6473597d706e	805
bogdanm	82:6473597d706e	806	/*!
bogdanm	82:6473597d706e	807	* @name Register MCG_C5, field PRDIV0[4:0] (RW)
bogdanm	82:6473597d706e	808	*
bogdanm	82:6473597d706e	809	* Selects the amount to divide down the external reference clock for the PLL.
bogdanm	82:6473597d706e	810	* The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
bogdanm	82:6473597d706e	811	* is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
bogdanm	82:6473597d706e	812	* be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
bogdanm	82:6473597d706e	813	* Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
bogdanm	82:6473597d706e	814	* 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
bogdanm	82:6473597d706e	815	* 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
bogdanm	82:6473597d706e	816	* 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
bogdanm	82:6473597d706e	817	* Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
bogdanm	82:6473597d706e	818	* Reserved
bogdanm	82:6473597d706e	819	*/
bogdanm	82:6473597d706e	820	//@{
bogdanm	82:6473597d706e	821	#define BP_MCG_C5_PRDIV0 (0U) //!< Bit position for MCG_C5_PRDIV0.
bogdanm	82:6473597d706e	822	#define BM_MCG_C5_PRDIV0 (0x1FU) //!< Bit mask for MCG_C5_PRDIV0.
bogdanm	82:6473597d706e	823	#define BS_MCG_C5_PRDIV0 (5U) //!< Bit field size in bits for MCG_C5_PRDIV0.
bogdanm	82:6473597d706e	824
bogdanm	82:6473597d706e	825	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	826	//! @brief Read current value of the MCG_C5_PRDIV0 field.
bogdanm	82:6473597d706e	827	#define BR_MCG_C5_PRDIV0 (HW_MCG_C5.B.PRDIV0)
bogdanm	82:6473597d706e	828	#endif
bogdanm	82:6473597d706e	829
bogdanm	82:6473597d706e	830	//! @brief Format value for bitfield MCG_C5_PRDIV0.
bogdanm	82:6473597d706e	831	#define BF_MCG_C5_PRDIV0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PRDIV0), uint8_t) & BM_MCG_C5_PRDIV0)
bogdanm	82:6473597d706e	832
bogdanm	82:6473597d706e	833	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	834	//! @brief Set the PRDIV0 field to a new value.
bogdanm	82:6473597d706e	835	#define BW_MCG_C5_PRDIV0(v) (HW_MCG_C5_WR((HW_MCG_C5_RD() & ~BM_MCG_C5_PRDIV0) \| BF_MCG_C5_PRDIV0(v)))
bogdanm	82:6473597d706e	836	#endif
bogdanm	82:6473597d706e	837	//@}
bogdanm	82:6473597d706e	838
bogdanm	82:6473597d706e	839	/*!
bogdanm	82:6473597d706e	840	* @name Register MCG_C5, field PLLSTEN0[5] (RW)
bogdanm	82:6473597d706e	841	*
bogdanm	82:6473597d706e	842	* Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
bogdanm	82:6473597d706e	843	* clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
bogdanm	82:6473597d706e	844	* has no affect and does not enable the PLL Clock to run if it is written to 1.
bogdanm	82:6473597d706e	845	*
bogdanm	82:6473597d706e	846	* Values:
bogdanm	82:6473597d706e	847	* - 0 - MCGPLLCLK is disabled in any of the Stop modes.
bogdanm	82:6473597d706e	848	* - 1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
bogdanm	82:6473597d706e	849	*/
bogdanm	82:6473597d706e	850	//@{
bogdanm	82:6473597d706e	851	#define BP_MCG_C5_PLLSTEN0 (5U) //!< Bit position for MCG_C5_PLLSTEN0.
bogdanm	82:6473597d706e	852	#define BM_MCG_C5_PLLSTEN0 (0x20U) //!< Bit mask for MCG_C5_PLLSTEN0.
bogdanm	82:6473597d706e	853	#define BS_MCG_C5_PLLSTEN0 (1U) //!< Bit field size in bits for MCG_C5_PLLSTEN0.
bogdanm	82:6473597d706e	854
bogdanm	82:6473597d706e	855	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	856	//! @brief Read current value of the MCG_C5_PLLSTEN0 field.
bogdanm	82:6473597d706e	857	#define BR_MCG_C5_PLLSTEN0 (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLSTEN0))
bogdanm	82:6473597d706e	858	#endif
bogdanm	82:6473597d706e	859
bogdanm	82:6473597d706e	860	//! @brief Format value for bitfield MCG_C5_PLLSTEN0.
bogdanm	82:6473597d706e	861	#define BF_MCG_C5_PLLSTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PLLSTEN0), uint8_t) & BM_MCG_C5_PLLSTEN0)
bogdanm	82:6473597d706e	862
bogdanm	82:6473597d706e	863	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	864	//! @brief Set the PLLSTEN0 field to a new value.
bogdanm	82:6473597d706e	865	#define BW_MCG_C5_PLLSTEN0(v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLSTEN0) = (v))
bogdanm	82:6473597d706e	866	#endif
bogdanm	82:6473597d706e	867	//@}
bogdanm	82:6473597d706e	868
bogdanm	82:6473597d706e	869	/*!
bogdanm	82:6473597d706e	870	* @name Register MCG_C5, field PLLCLKEN0[6] (RW)
bogdanm	82:6473597d706e	871	*
bogdanm	82:6473597d706e	872	* Enables the PLL independent of PLLS and enables the PLL clock for use as
bogdanm	82:6473597d706e	873	* MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
bogdanm	82:6473597d706e	874	* PLL reference clock in the range of 2 - 4 MHz range prior to setting the
bogdanm	82:6473597d706e	875	* PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
bogdanm	82:6473597d706e	876	* already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
bogdanm	82:6473597d706e	877	* and the external oscillator is being used as the reference clock, the OSCINIT 0
bogdanm	82:6473597d706e	878	* bit should be checked to make sure it is set.
bogdanm	82:6473597d706e	879	*
bogdanm	82:6473597d706e	880	* Values:
bogdanm	82:6473597d706e	881	* - 0 - MCGPLLCLK is inactive.
bogdanm	82:6473597d706e	882	* - 1 - MCGPLLCLK is active.
bogdanm	82:6473597d706e	883	*/
bogdanm	82:6473597d706e	884	//@{
bogdanm	82:6473597d706e	885	#define BP_MCG_C5_PLLCLKEN0 (6U) //!< Bit position for MCG_C5_PLLCLKEN0.
bogdanm	82:6473597d706e	886	#define BM_MCG_C5_PLLCLKEN0 (0x40U) //!< Bit mask for MCG_C5_PLLCLKEN0.
bogdanm	82:6473597d706e	887	#define BS_MCG_C5_PLLCLKEN0 (1U) //!< Bit field size in bits for MCG_C5_PLLCLKEN0.
bogdanm	82:6473597d706e	888
bogdanm	82:6473597d706e	889	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	890	//! @brief Read current value of the MCG_C5_PLLCLKEN0 field.
bogdanm	82:6473597d706e	891	#define BR_MCG_C5_PLLCLKEN0 (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLCLKEN0))
bogdanm	82:6473597d706e	892	#endif
bogdanm	82:6473597d706e	893
bogdanm	82:6473597d706e	894	//! @brief Format value for bitfield MCG_C5_PLLCLKEN0.
bogdanm	82:6473597d706e	895	#define BF_MCG_C5_PLLCLKEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PLLCLKEN0), uint8_t) & BM_MCG_C5_PLLCLKEN0)
bogdanm	82:6473597d706e	896
bogdanm	82:6473597d706e	897	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	898	//! @brief Set the PLLCLKEN0 field to a new value.
bogdanm	82:6473597d706e	899	#define BW_MCG_C5_PLLCLKEN0(v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLCLKEN0) = (v))
bogdanm	82:6473597d706e	900	#endif
bogdanm	82:6473597d706e	901	//@}
bogdanm	82:6473597d706e	902
bogdanm	82:6473597d706e	903	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	904	// HW_MCG_C6 - MCG Control 6 Register
bogdanm	82:6473597d706e	905	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	906
bogdanm	82:6473597d706e	907	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	908	/*!
bogdanm	82:6473597d706e	909	* @brief HW_MCG_C6 - MCG Control 6 Register (RW)
bogdanm	82:6473597d706e	910	*
bogdanm	82:6473597d706e	911	* Reset value: 0x00U
bogdanm	82:6473597d706e	912	*/
bogdanm	82:6473597d706e	913	typedef union _hw_mcg_c6
bogdanm	82:6473597d706e	914	{
bogdanm	82:6473597d706e	915	uint8_t U;
bogdanm	82:6473597d706e	916	struct _hw_mcg_c6_bitfields
bogdanm	82:6473597d706e	917	{
bogdanm	82:6473597d706e	918	uint8_t VDIV0 : 5; //!< [4:0] VCO 0 Divider
bogdanm	82:6473597d706e	919	uint8_t CME0 : 1; //!< [5] Clock Monitor Enable
bogdanm	82:6473597d706e	920	uint8_t PLLS : 1; //!< [6] PLL Select
bogdanm	82:6473597d706e	921	uint8_t LOLIE0 : 1; //!< [7] Loss of Lock Interrrupt Enable
bogdanm	82:6473597d706e	922	} B;
bogdanm	82:6473597d706e	923	} hw_mcg_c6_t;
bogdanm	82:6473597d706e	924	#endif
bogdanm	82:6473597d706e	925
bogdanm	82:6473597d706e	926	/*!
bogdanm	82:6473597d706e	927	* @name Constants and macros for entire MCG_C6 register
bogdanm	82:6473597d706e	928	*/
bogdanm	82:6473597d706e	929	//@{
bogdanm	82:6473597d706e	930	#define HW_MCG_C6_ADDR (REGS_MCG_BASE + 0x5U)
bogdanm	82:6473597d706e	931
bogdanm	82:6473597d706e	932	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	933	#define HW_MCG_C6 ((__IO hw_mcg_c6_t ) HW_MCG_C6_ADDR)
bogdanm	82:6473597d706e	934	#define HW_MCG_C6_RD() (HW_MCG_C6.U)
bogdanm	82:6473597d706e	935	#define HW_MCG_C6_WR(v) (HW_MCG_C6.U = (v))
bogdanm	82:6473597d706e	936	#define HW_MCG_C6_SET(v) (HW_MCG_C6_WR(HW_MCG_C6_RD() \| (v)))
bogdanm	82:6473597d706e	937	#define HW_MCG_C6_CLR(v) (HW_MCG_C6_WR(HW_MCG_C6_RD() & ~(v)))
bogdanm	82:6473597d706e	938	#define HW_MCG_C6_TOG(v) (HW_MCG_C6_WR(HW_MCG_C6_RD() ^ (v)))
bogdanm	82:6473597d706e	939	#endif
bogdanm	82:6473597d706e	940	//@}
bogdanm	82:6473597d706e	941
bogdanm	82:6473597d706e	942	/*
bogdanm	82:6473597d706e	943	* Constants & macros for individual MCG_C6 bitfields
bogdanm	82:6473597d706e	944	*/
bogdanm	82:6473597d706e	945
bogdanm	82:6473597d706e	946	/*!
bogdanm	82:6473597d706e	947	* @name Register MCG_C6, field VDIV0[4:0] (RW)
bogdanm	82:6473597d706e	948	*
bogdanm	82:6473597d706e	949	* Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
bogdanm	82:6473597d706e	950	* establish the multiplication factor (M) applied to the reference clock frequency.
bogdanm	82:6473597d706e	951	* After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
bogdanm	82:6473597d706e	952	* value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
bogdanm	82:6473597d706e	953	* Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
bogdanm	82:6473597d706e	954	* Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
bogdanm	82:6473597d706e	955	* 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
bogdanm	82:6473597d706e	956	* 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
bogdanm	82:6473597d706e	957	* 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
bogdanm	82:6473597d706e	958	*/
bogdanm	82:6473597d706e	959	//@{
bogdanm	82:6473597d706e	960	#define BP_MCG_C6_VDIV0 (0U) //!< Bit position for MCG_C6_VDIV0.
bogdanm	82:6473597d706e	961	#define BM_MCG_C6_VDIV0 (0x1FU) //!< Bit mask for MCG_C6_VDIV0.
bogdanm	82:6473597d706e	962	#define BS_MCG_C6_VDIV0 (5U) //!< Bit field size in bits for MCG_C6_VDIV0.
bogdanm	82:6473597d706e	963
bogdanm	82:6473597d706e	964	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	965	//! @brief Read current value of the MCG_C6_VDIV0 field.
bogdanm	82:6473597d706e	966	#define BR_MCG_C6_VDIV0 (HW_MCG_C6.B.VDIV0)
bogdanm	82:6473597d706e	967	#endif
bogdanm	82:6473597d706e	968
bogdanm	82:6473597d706e	969	//! @brief Format value for bitfield MCG_C6_VDIV0.
bogdanm	82:6473597d706e	970	#define BF_MCG_C6_VDIV0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_VDIV0), uint8_t) & BM_MCG_C6_VDIV0)
bogdanm	82:6473597d706e	971
bogdanm	82:6473597d706e	972	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	973	//! @brief Set the VDIV0 field to a new value.
bogdanm	82:6473597d706e	974	#define BW_MCG_C6_VDIV0(v) (HW_MCG_C6_WR((HW_MCG_C6_RD() & ~BM_MCG_C6_VDIV0) \| BF_MCG_C6_VDIV0(v)))
bogdanm	82:6473597d706e	975	#endif
bogdanm	82:6473597d706e	976	//@}
bogdanm	82:6473597d706e	977
bogdanm	82:6473597d706e	978	/*!
bogdanm	82:6473597d706e	979	* @name Register MCG_C6, field CME0[5] (RW)
bogdanm	82:6473597d706e	980	*
bogdanm	82:6473597d706e	981	* Enables the loss of clock monitoring circuit for the OSC0 external reference
bogdanm	82:6473597d706e	982	* mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
bogdanm	82:6473597d706e	983	* generated following a loss of OSC0 indication. The CME0 bit must only be set
bogdanm	82:6473597d706e	984	* to a logic 1 when the MCG is in an operational mode that uses the external
bogdanm	82:6473597d706e	985	* clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
bogdanm	82:6473597d706e	986	* the value of the RANGE0 bits in the C2 register should not be changed. CME0
bogdanm	82:6473597d706e	987	* bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
bogdanm	82:6473597d706e	988	* reset request may occur while in Stop mode. CME0 should also be set to a
bogdanm	82:6473597d706e	989	* logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
bogdanm	82:6473597d706e	990	*
bogdanm	82:6473597d706e	991	* Values:
bogdanm	82:6473597d706e	992	* - 0 - External clock monitor is disabled for OSC0.
bogdanm	82:6473597d706e	993	* - 1 - External clock monitor is enabled for OSC0.
bogdanm	82:6473597d706e	994	*/
bogdanm	82:6473597d706e	995	//@{
bogdanm	82:6473597d706e	996	#define BP_MCG_C6_CME0 (5U) //!< Bit position for MCG_C6_CME0.
bogdanm	82:6473597d706e	997	#define BM_MCG_C6_CME0 (0x20U) //!< Bit mask for MCG_C6_CME0.
bogdanm	82:6473597d706e	998	#define BS_MCG_C6_CME0 (1U) //!< Bit field size in bits for MCG_C6_CME0.
bogdanm	82:6473597d706e	999
bogdanm	82:6473597d706e	1000	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1001	//! @brief Read current value of the MCG_C6_CME0 field.
bogdanm	82:6473597d706e	1002	#define BR_MCG_C6_CME0 (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_CME0))
bogdanm	82:6473597d706e	1003	#endif
bogdanm	82:6473597d706e	1004
bogdanm	82:6473597d706e	1005	//! @brief Format value for bitfield MCG_C6_CME0.
bogdanm	82:6473597d706e	1006	#define BF_MCG_C6_CME0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_CME0), uint8_t) & BM_MCG_C6_CME0)
bogdanm	82:6473597d706e	1007
bogdanm	82:6473597d706e	1008	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1009	//! @brief Set the CME0 field to a new value.
bogdanm	82:6473597d706e	1010	#define BW_MCG_C6_CME0(v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_CME0) = (v))
bogdanm	82:6473597d706e	1011	#endif
bogdanm	82:6473597d706e	1012	//@}
bogdanm	82:6473597d706e	1013
bogdanm	82:6473597d706e	1014	/*!
bogdanm	82:6473597d706e	1015	* @name Register MCG_C6, field PLLS[6] (RW)
bogdanm	82:6473597d706e	1016	*
bogdanm	82:6473597d706e	1017	* Controls whether the PLL or FLL output is selected as the MCG source when
bogdanm	82:6473597d706e	1018	* CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
bogdanm	82:6473597d706e	1019	* disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
bogdanm	82:6473597d706e	1020	*
bogdanm	82:6473597d706e	1021	* Values:
bogdanm	82:6473597d706e	1022	* - 0 - FLL is selected.
bogdanm	82:6473597d706e	1023	* - 1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
bogdanm	82:6473597d706e	1024	* to generate a PLL reference clock in the range of 2-4 MHz prior to setting
bogdanm	82:6473597d706e	1025	* the PLLS bit).
bogdanm	82:6473597d706e	1026	*/
bogdanm	82:6473597d706e	1027	//@{
bogdanm	82:6473597d706e	1028	#define BP_MCG_C6_PLLS (6U) //!< Bit position for MCG_C6_PLLS.
bogdanm	82:6473597d706e	1029	#define BM_MCG_C6_PLLS (0x40U) //!< Bit mask for MCG_C6_PLLS.
bogdanm	82:6473597d706e	1030	#define BS_MCG_C6_PLLS (1U) //!< Bit field size in bits for MCG_C6_PLLS.
bogdanm	82:6473597d706e	1031
bogdanm	82:6473597d706e	1032	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1033	//! @brief Read current value of the MCG_C6_PLLS field.
bogdanm	82:6473597d706e	1034	#define BR_MCG_C6_PLLS (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_PLLS))
bogdanm	82:6473597d706e	1035	#endif
bogdanm	82:6473597d706e	1036
bogdanm	82:6473597d706e	1037	//! @brief Format value for bitfield MCG_C6_PLLS.
bogdanm	82:6473597d706e	1038	#define BF_MCG_C6_PLLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_PLLS), uint8_t) & BM_MCG_C6_PLLS)
bogdanm	82:6473597d706e	1039
bogdanm	82:6473597d706e	1040	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1041	//! @brief Set the PLLS field to a new value.
bogdanm	82:6473597d706e	1042	#define BW_MCG_C6_PLLS(v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_PLLS) = (v))
bogdanm	82:6473597d706e	1043	#endif
bogdanm	82:6473597d706e	1044	//@}
bogdanm	82:6473597d706e	1045
bogdanm	82:6473597d706e	1046	/*!
bogdanm	82:6473597d706e	1047	* @name Register MCG_C6, field LOLIE0[7] (RW)
bogdanm	82:6473597d706e	1048	*
bogdanm	82:6473597d706e	1049	* Determines if an interrupt request is made following a loss of lock
bogdanm	82:6473597d706e	1050	* indication. This bit only has an effect when LOLS 0 is set.
bogdanm	82:6473597d706e	1051	*
bogdanm	82:6473597d706e	1052	* Values:
bogdanm	82:6473597d706e	1053	* - 0 - No interrupt request is generated on loss of lock.
bogdanm	82:6473597d706e	1054	* - 1 - Generate an interrupt request on loss of lock.
bogdanm	82:6473597d706e	1055	*/
bogdanm	82:6473597d706e	1056	//@{
bogdanm	82:6473597d706e	1057	#define BP_MCG_C6_LOLIE0 (7U) //!< Bit position for MCG_C6_LOLIE0.
bogdanm	82:6473597d706e	1058	#define BM_MCG_C6_LOLIE0 (0x80U) //!< Bit mask for MCG_C6_LOLIE0.
bogdanm	82:6473597d706e	1059	#define BS_MCG_C6_LOLIE0 (1U) //!< Bit field size in bits for MCG_C6_LOLIE0.
bogdanm	82:6473597d706e	1060
bogdanm	82:6473597d706e	1061	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1062	//! @brief Read current value of the MCG_C6_LOLIE0 field.
bogdanm	82:6473597d706e	1063	#define BR_MCG_C6_LOLIE0 (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_LOLIE0))
bogdanm	82:6473597d706e	1064	#endif
bogdanm	82:6473597d706e	1065
bogdanm	82:6473597d706e	1066	//! @brief Format value for bitfield MCG_C6_LOLIE0.
bogdanm	82:6473597d706e	1067	#define BF_MCG_C6_LOLIE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_LOLIE0), uint8_t) & BM_MCG_C6_LOLIE0)
bogdanm	82:6473597d706e	1068
bogdanm	82:6473597d706e	1069	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1070	//! @brief Set the LOLIE0 field to a new value.
bogdanm	82:6473597d706e	1071	#define BW_MCG_C6_LOLIE0(v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_LOLIE0) = (v))
bogdanm	82:6473597d706e	1072	#endif
bogdanm	82:6473597d706e	1073	//@}
bogdanm	82:6473597d706e	1074
bogdanm	82:6473597d706e	1075	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1076	// HW_MCG_S - MCG Status Register
bogdanm	82:6473597d706e	1077	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1078
bogdanm	82:6473597d706e	1079	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1080	/*!
bogdanm	82:6473597d706e	1081	* @brief HW_MCG_S - MCG Status Register (RW)
bogdanm	82:6473597d706e	1082	*
bogdanm	82:6473597d706e	1083	* Reset value: 0x10U
bogdanm	82:6473597d706e	1084	*/
bogdanm	82:6473597d706e	1085	typedef union _hw_mcg_s
bogdanm	82:6473597d706e	1086	{
bogdanm	82:6473597d706e	1087	uint8_t U;
bogdanm	82:6473597d706e	1088	struct _hw_mcg_s_bitfields
bogdanm	82:6473597d706e	1089	{
bogdanm	82:6473597d706e	1090	uint8_t IRCST : 1; //!< [0] Internal Reference Clock Status
bogdanm	82:6473597d706e	1091	uint8_t OSCINIT0 : 1; //!< [1] OSC Initialization
bogdanm	82:6473597d706e	1092	uint8_t CLKST : 2; //!< [3:2] Clock Mode Status
bogdanm	82:6473597d706e	1093	uint8_t IREFST : 1; //!< [4] Internal Reference Status
bogdanm	82:6473597d706e	1094	uint8_t PLLST : 1; //!< [5] PLL Select Status
bogdanm	82:6473597d706e	1095	uint8_t LOCK0 : 1; //!< [6] Lock Status
bogdanm	82:6473597d706e	1096	uint8_t LOLS0 : 1; //!< [7] Loss of Lock Status
bogdanm	82:6473597d706e	1097	} B;
bogdanm	82:6473597d706e	1098	} hw_mcg_s_t;
bogdanm	82:6473597d706e	1099	#endif
bogdanm	82:6473597d706e	1100
bogdanm	82:6473597d706e	1101	/*!
bogdanm	82:6473597d706e	1102	* @name Constants and macros for entire MCG_S register
bogdanm	82:6473597d706e	1103	*/
bogdanm	82:6473597d706e	1104	//@{
bogdanm	82:6473597d706e	1105	#define HW_MCG_S_ADDR (REGS_MCG_BASE + 0x6U)
bogdanm	82:6473597d706e	1106
bogdanm	82:6473597d706e	1107	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1108	#define HW_MCG_S ((__IO hw_mcg_s_t ) HW_MCG_S_ADDR)
bogdanm	82:6473597d706e	1109	#define HW_MCG_S_RD() (HW_MCG_S.U)
bogdanm	82:6473597d706e	1110	#define HW_MCG_S_WR(v) (HW_MCG_S.U = (v))
bogdanm	82:6473597d706e	1111	#define HW_MCG_S_SET(v) (HW_MCG_S_WR(HW_MCG_S_RD() \| (v)))
bogdanm	82:6473597d706e	1112	#define HW_MCG_S_CLR(v) (HW_MCG_S_WR(HW_MCG_S_RD() & ~(v)))
bogdanm	82:6473597d706e	1113	#define HW_MCG_S_TOG(v) (HW_MCG_S_WR(HW_MCG_S_RD() ^ (v)))
bogdanm	82:6473597d706e	1114	#endif
bogdanm	82:6473597d706e	1115	//@}
bogdanm	82:6473597d706e	1116
bogdanm	82:6473597d706e	1117	/*
bogdanm	82:6473597d706e	1118	* Constants & macros for individual MCG_S bitfields
bogdanm	82:6473597d706e	1119	*/
bogdanm	82:6473597d706e	1120
bogdanm	82:6473597d706e	1121	/*!
bogdanm	82:6473597d706e	1122	* @name Register MCG_S, field IRCST[0] (RO)
bogdanm	82:6473597d706e	1123	*
bogdanm	82:6473597d706e	1124	* The IRCST bit indicates the current source for the internal reference clock
bogdanm	82:6473597d706e	1125	* select clock (IRCSCLK). The IRCST bit does not update immediately after a write
bogdanm	82:6473597d706e	1126	* to the IRCS bit due to internal synchronization between clock domains. The
bogdanm	82:6473597d706e	1127	* IRCST bit will only be updated if the internal reference clock is enabled,
bogdanm	82:6473597d706e	1128	* either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
bogdanm	82:6473597d706e	1129	* bit .
bogdanm	82:6473597d706e	1130	*
bogdanm	82:6473597d706e	1131	* Values:
bogdanm	82:6473597d706e	1132	* - 0 - Source of internal reference clock is the slow clock (32 kHz IRC).
bogdanm	82:6473597d706e	1133	* - 1 - Source of internal reference clock is the fast clock (4 MHz IRC).
bogdanm	82:6473597d706e	1134	*/
bogdanm	82:6473597d706e	1135	//@{
bogdanm	82:6473597d706e	1136	#define BP_MCG_S_IRCST (0U) //!< Bit position for MCG_S_IRCST.
bogdanm	82:6473597d706e	1137	#define BM_MCG_S_IRCST (0x01U) //!< Bit mask for MCG_S_IRCST.
bogdanm	82:6473597d706e	1138	#define BS_MCG_S_IRCST (1U) //!< Bit field size in bits for MCG_S_IRCST.
bogdanm	82:6473597d706e	1139
bogdanm	82:6473597d706e	1140	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1141	//! @brief Read current value of the MCG_S_IRCST field.
bogdanm	82:6473597d706e	1142	#define BR_MCG_S_IRCST (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_IRCST))
bogdanm	82:6473597d706e	1143	#endif
bogdanm	82:6473597d706e	1144	//@}
bogdanm	82:6473597d706e	1145
bogdanm	82:6473597d706e	1146	/*!
bogdanm	82:6473597d706e	1147	* @name Register MCG_S, field OSCINIT0[1] (RO)
bogdanm	82:6473597d706e	1148	*
bogdanm	82:6473597d706e	1149	* This bit, which resets to 0, is set to 1 after the initialization cycles of
bogdanm	82:6473597d706e	1150	* the crystal oscillator clock have completed. After being set, the bit is
bogdanm	82:6473597d706e	1151	* cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
bogdanm	82:6473597d706e	1152	* description for more information.
bogdanm	82:6473597d706e	1153	*/
bogdanm	82:6473597d706e	1154	//@{
bogdanm	82:6473597d706e	1155	#define BP_MCG_S_OSCINIT0 (1U) //!< Bit position for MCG_S_OSCINIT0.
bogdanm	82:6473597d706e	1156	#define BM_MCG_S_OSCINIT0 (0x02U) //!< Bit mask for MCG_S_OSCINIT0.
bogdanm	82:6473597d706e	1157	#define BS_MCG_S_OSCINIT0 (1U) //!< Bit field size in bits for MCG_S_OSCINIT0.
bogdanm	82:6473597d706e	1158
bogdanm	82:6473597d706e	1159	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1160	//! @brief Read current value of the MCG_S_OSCINIT0 field.
bogdanm	82:6473597d706e	1161	#define BR_MCG_S_OSCINIT0 (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_OSCINIT0))
bogdanm	82:6473597d706e	1162	#endif
bogdanm	82:6473597d706e	1163	//@}
bogdanm	82:6473597d706e	1164
bogdanm	82:6473597d706e	1165	/*!
bogdanm	82:6473597d706e	1166	* @name Register MCG_S, field CLKST[3:2] (RO)
bogdanm	82:6473597d706e	1167	*
bogdanm	82:6473597d706e	1168	* These bits indicate the current clock mode. The CLKST bits do not update
bogdanm	82:6473597d706e	1169	* immediately after a write to the CLKS bits due to internal synchronization between
bogdanm	82:6473597d706e	1170	* clock domains.
bogdanm	82:6473597d706e	1171	*
bogdanm	82:6473597d706e	1172	* Values:
bogdanm	82:6473597d706e	1173	* - 00 - Encoding 0 - Output of the FLL is selected (reset default).
bogdanm	82:6473597d706e	1174	* - 01 - Encoding 1 - Internal reference clock is selected.
bogdanm	82:6473597d706e	1175	* - 10 - Encoding 2 - External reference clock is selected.
bogdanm	82:6473597d706e	1176	* - 11 - Encoding 3 - Output of the PLL is selected.
bogdanm	82:6473597d706e	1177	*/
bogdanm	82:6473597d706e	1178	//@{
bogdanm	82:6473597d706e	1179	#define BP_MCG_S_CLKST (2U) //!< Bit position for MCG_S_CLKST.
bogdanm	82:6473597d706e	1180	#define BM_MCG_S_CLKST (0x0CU) //!< Bit mask for MCG_S_CLKST.
bogdanm	82:6473597d706e	1181	#define BS_MCG_S_CLKST (2U) //!< Bit field size in bits for MCG_S_CLKST.
bogdanm	82:6473597d706e	1182
bogdanm	82:6473597d706e	1183	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1184	//! @brief Read current value of the MCG_S_CLKST field.
bogdanm	82:6473597d706e	1185	#define BR_MCG_S_CLKST (HW_MCG_S.B.CLKST)
bogdanm	82:6473597d706e	1186	#endif
bogdanm	82:6473597d706e	1187	//@}
bogdanm	82:6473597d706e	1188
bogdanm	82:6473597d706e	1189	/*!
bogdanm	82:6473597d706e	1190	* @name Register MCG_S, field IREFST[4] (RO)
bogdanm	82:6473597d706e	1191	*
bogdanm	82:6473597d706e	1192	* This bit indicates the current source for the FLL reference clock. The IREFST
bogdanm	82:6473597d706e	1193	* bit does not update immediately after a write to the IREFS bit due to
bogdanm	82:6473597d706e	1194	* internal synchronization between clock domains.
bogdanm	82:6473597d706e	1195	*
bogdanm	82:6473597d706e	1196	* Values:
bogdanm	82:6473597d706e	1197	* - 0 - Source of FLL reference clock is the external reference clock.
bogdanm	82:6473597d706e	1198	* - 1 - Source of FLL reference clock is the internal reference clock.
bogdanm	82:6473597d706e	1199	*/
bogdanm	82:6473597d706e	1200	//@{
bogdanm	82:6473597d706e	1201	#define BP_MCG_S_IREFST (4U) //!< Bit position for MCG_S_IREFST.
bogdanm	82:6473597d706e	1202	#define BM_MCG_S_IREFST (0x10U) //!< Bit mask for MCG_S_IREFST.
bogdanm	82:6473597d706e	1203	#define BS_MCG_S_IREFST (1U) //!< Bit field size in bits for MCG_S_IREFST.
bogdanm	82:6473597d706e	1204
bogdanm	82:6473597d706e	1205	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1206	//! @brief Read current value of the MCG_S_IREFST field.
bogdanm	82:6473597d706e	1207	#define BR_MCG_S_IREFST (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_IREFST))
bogdanm	82:6473597d706e	1208	#endif
bogdanm	82:6473597d706e	1209	//@}
bogdanm	82:6473597d706e	1210
bogdanm	82:6473597d706e	1211	/*!
bogdanm	82:6473597d706e	1212	* @name Register MCG_S, field PLLST[5] (RO)
bogdanm	82:6473597d706e	1213	*
bogdanm	82:6473597d706e	1214	* This bit indicates the clock source selected by PLLS . The PLLST bit does not
bogdanm	82:6473597d706e	1215	* update immediately after a write to the PLLS bit due to internal
bogdanm	82:6473597d706e	1216	* synchronization between clock domains.
bogdanm	82:6473597d706e	1217	*
bogdanm	82:6473597d706e	1218	* Values:
bogdanm	82:6473597d706e	1219	* - 0 - Source of PLLS clock is FLL clock.
bogdanm	82:6473597d706e	1220	* - 1 - Source of PLLS clock is PLL output clock.
bogdanm	82:6473597d706e	1221	*/
bogdanm	82:6473597d706e	1222	//@{
bogdanm	82:6473597d706e	1223	#define BP_MCG_S_PLLST (5U) //!< Bit position for MCG_S_PLLST.
bogdanm	82:6473597d706e	1224	#define BM_MCG_S_PLLST (0x20U) //!< Bit mask for MCG_S_PLLST.
bogdanm	82:6473597d706e	1225	#define BS_MCG_S_PLLST (1U) //!< Bit field size in bits for MCG_S_PLLST.
bogdanm	82:6473597d706e	1226
bogdanm	82:6473597d706e	1227	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1228	//! @brief Read current value of the MCG_S_PLLST field.
bogdanm	82:6473597d706e	1229	#define BR_MCG_S_PLLST (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_PLLST))
bogdanm	82:6473597d706e	1230	#endif
bogdanm	82:6473597d706e	1231	//@}
bogdanm	82:6473597d706e	1232
bogdanm	82:6473597d706e	1233	/*!
bogdanm	82:6473597d706e	1234	* @name Register MCG_S, field LOCK0[6] (RO)
bogdanm	82:6473597d706e	1235	*
bogdanm	82:6473597d706e	1236	* This bit indicates whether the PLL has acquired lock. Lock detection is only
bogdanm	82:6473597d706e	1237	* enabled when the PLL is enabled (either through clock mode selection or
bogdanm	82:6473597d706e	1238	* PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
bogdanm	82:6473597d706e	1239	* MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
bogdanm	82:6473597d706e	1240	* If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
bogdanm	82:6473597d706e	1241	* the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
bogdanm	82:6473597d706e	1242	* status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
bogdanm	82:6473597d706e	1243	* reference clock will also cause the LOCK0 bit to clear until the PLL has
bogdanm	82:6473597d706e	1244	* reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
bogdanm	82:6473597d706e	1245	* the lock status bit to clear and stay cleared until the Stop mode is exited
bogdanm	82:6473597d706e	1246	* and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
bogdanm	82:6473597d706e	1247	* is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
bogdanm	82:6473597d706e	1248	* again.
bogdanm	82:6473597d706e	1249	*
bogdanm	82:6473597d706e	1250	* Values:
bogdanm	82:6473597d706e	1251	* - 0 - PLL is currently unlocked.
bogdanm	82:6473597d706e	1252	* - 1 - PLL is currently locked.
bogdanm	82:6473597d706e	1253	*/
bogdanm	82:6473597d706e	1254	//@{
bogdanm	82:6473597d706e	1255	#define BP_MCG_S_LOCK0 (6U) //!< Bit position for MCG_S_LOCK0.
bogdanm	82:6473597d706e	1256	#define BM_MCG_S_LOCK0 (0x40U) //!< Bit mask for MCG_S_LOCK0.
bogdanm	82:6473597d706e	1257	#define BS_MCG_S_LOCK0 (1U) //!< Bit field size in bits for MCG_S_LOCK0.
bogdanm	82:6473597d706e	1258
bogdanm	82:6473597d706e	1259	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1260	//! @brief Read current value of the MCG_S_LOCK0 field.
bogdanm	82:6473597d706e	1261	#define BR_MCG_S_LOCK0 (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOCK0))
bogdanm	82:6473597d706e	1262	#endif
bogdanm	82:6473597d706e	1263	//@}
bogdanm	82:6473597d706e	1264
bogdanm	82:6473597d706e	1265	/*!
bogdanm	82:6473597d706e	1266	* @name Register MCG_S, field LOLS0[7] (W1C)
bogdanm	82:6473597d706e	1267	*
bogdanm	82:6473597d706e	1268	* This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
bogdanm	82:6473597d706e	1269	* if after acquiring lock, the PLL output frequency has fallen outside the lock
bogdanm	82:6473597d706e	1270	* exit frequency tolerance, D unl . LOLIE determines whether an interrupt
bogdanm	82:6473597d706e	1271	* request is made when LOLS is set. LOLRE determines whether a reset request is made
bogdanm	82:6473597d706e	1272	* when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
bogdanm	82:6473597d706e	1273	* when set. Writing a logic 0 to this bit has no effect.
bogdanm	82:6473597d706e	1274	*
bogdanm	82:6473597d706e	1275	* Values:
bogdanm	82:6473597d706e	1276	* - 0 - PLL has not lost lock since LOLS 0 was last cleared.
bogdanm	82:6473597d706e	1277	* - 1 - PLL has lost lock since LOLS 0 was last cleared.
bogdanm	82:6473597d706e	1278	*/
bogdanm	82:6473597d706e	1279	//@{
bogdanm	82:6473597d706e	1280	#define BP_MCG_S_LOLS0 (7U) //!< Bit position for MCG_S_LOLS0.
bogdanm	82:6473597d706e	1281	#define BM_MCG_S_LOLS0 (0x80U) //!< Bit mask for MCG_S_LOLS0.
bogdanm	82:6473597d706e	1282	#define BS_MCG_S_LOLS0 (1U) //!< Bit field size in bits for MCG_S_LOLS0.
bogdanm	82:6473597d706e	1283
bogdanm	82:6473597d706e	1284	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1285	//! @brief Read current value of the MCG_S_LOLS0 field.
bogdanm	82:6473597d706e	1286	#define BR_MCG_S_LOLS0 (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOLS0))
bogdanm	82:6473597d706e	1287	#endif
bogdanm	82:6473597d706e	1288
bogdanm	82:6473597d706e	1289	//! @brief Format value for bitfield MCG_S_LOLS0.
bogdanm	82:6473597d706e	1290	#define BF_MCG_S_LOLS0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_S_LOLS0), uint8_t) & BM_MCG_S_LOLS0)
bogdanm	82:6473597d706e	1291
bogdanm	82:6473597d706e	1292	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1293	//! @brief Set the LOLS0 field to a new value.
bogdanm	82:6473597d706e	1294	#define BW_MCG_S_LOLS0(v) (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOLS0) = (v))
bogdanm	82:6473597d706e	1295	#endif
bogdanm	82:6473597d706e	1296	//@}
bogdanm	82:6473597d706e	1297
bogdanm	82:6473597d706e	1298	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1299	// HW_MCG_SC - MCG Status and Control Register
bogdanm	82:6473597d706e	1300	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1301
bogdanm	82:6473597d706e	1302	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1303	/*!
bogdanm	82:6473597d706e	1304	* @brief HW_MCG_SC - MCG Status and Control Register (RW)
bogdanm	82:6473597d706e	1305	*
bogdanm	82:6473597d706e	1306	* Reset value: 0x02U
bogdanm	82:6473597d706e	1307	*/
bogdanm	82:6473597d706e	1308	typedef union _hw_mcg_sc
bogdanm	82:6473597d706e	1309	{
bogdanm	82:6473597d706e	1310	uint8_t U;
bogdanm	82:6473597d706e	1311	struct _hw_mcg_sc_bitfields
bogdanm	82:6473597d706e	1312	{
bogdanm	82:6473597d706e	1313	uint8_t LOCS0 : 1; //!< [0] OSC0 Loss of Clock Status
bogdanm	82:6473597d706e	1314	uint8_t FCRDIV : 3; //!< [3:1] Fast Clock Internal Reference Divider
bogdanm	82:6473597d706e	1315	uint8_t FLTPRSRV : 1; //!< [4] FLL Filter Preserve Enable
bogdanm	82:6473597d706e	1316	uint8_t ATMF : 1; //!< [5] Automatic Trim Machine Fail Flag
bogdanm	82:6473597d706e	1317	uint8_t ATMS : 1; //!< [6] Automatic Trim Machine Select
bogdanm	82:6473597d706e	1318	uint8_t ATME : 1; //!< [7] Automatic Trim Machine Enable
bogdanm	82:6473597d706e	1319	} B;
bogdanm	82:6473597d706e	1320	} hw_mcg_sc_t;
bogdanm	82:6473597d706e	1321	#endif
bogdanm	82:6473597d706e	1322
bogdanm	82:6473597d706e	1323	/*!
bogdanm	82:6473597d706e	1324	* @name Constants and macros for entire MCG_SC register
bogdanm	82:6473597d706e	1325	*/
bogdanm	82:6473597d706e	1326	//@{
bogdanm	82:6473597d706e	1327	#define HW_MCG_SC_ADDR (REGS_MCG_BASE + 0x8U)
bogdanm	82:6473597d706e	1328
bogdanm	82:6473597d706e	1329	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1330	#define HW_MCG_SC ((__IO hw_mcg_sc_t ) HW_MCG_SC_ADDR)
bogdanm	82:6473597d706e	1331	#define HW_MCG_SC_RD() (HW_MCG_SC.U)
bogdanm	82:6473597d706e	1332	#define HW_MCG_SC_WR(v) (HW_MCG_SC.U = (v))
bogdanm	82:6473597d706e	1333	#define HW_MCG_SC_SET(v) (HW_MCG_SC_WR(HW_MCG_SC_RD() \| (v)))
bogdanm	82:6473597d706e	1334	#define HW_MCG_SC_CLR(v) (HW_MCG_SC_WR(HW_MCG_SC_RD() & ~(v)))
bogdanm	82:6473597d706e	1335	#define HW_MCG_SC_TOG(v) (HW_MCG_SC_WR(HW_MCG_SC_RD() ^ (v)))
bogdanm	82:6473597d706e	1336	#endif
bogdanm	82:6473597d706e	1337	//@}
bogdanm	82:6473597d706e	1338
bogdanm	82:6473597d706e	1339	/*
bogdanm	82:6473597d706e	1340	* Constants & macros for individual MCG_SC bitfields
bogdanm	82:6473597d706e	1341	*/
bogdanm	82:6473597d706e	1342
bogdanm	82:6473597d706e	1343	/*!
bogdanm	82:6473597d706e	1344	* @name Register MCG_SC, field LOCS0[0] (W1C)
bogdanm	82:6473597d706e	1345	*
bogdanm	82:6473597d706e	1346	* The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
bogdanm	82:6473597d706e	1347	* LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
bogdanm	82:6473597d706e	1348	* logic 1 to it when set.
bogdanm	82:6473597d706e	1349	*
bogdanm	82:6473597d706e	1350	* Values:
bogdanm	82:6473597d706e	1351	* - 0 - Loss of OSC0 has not occurred.
bogdanm	82:6473597d706e	1352	* - 1 - Loss of OSC0 has occurred.
bogdanm	82:6473597d706e	1353	*/
bogdanm	82:6473597d706e	1354	//@{
bogdanm	82:6473597d706e	1355	#define BP_MCG_SC_LOCS0 (0U) //!< Bit position for MCG_SC_LOCS0.
bogdanm	82:6473597d706e	1356	#define BM_MCG_SC_LOCS0 (0x01U) //!< Bit mask for MCG_SC_LOCS0.
bogdanm	82:6473597d706e	1357	#define BS_MCG_SC_LOCS0 (1U) //!< Bit field size in bits for MCG_SC_LOCS0.
bogdanm	82:6473597d706e	1358
bogdanm	82:6473597d706e	1359	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1360	//! @brief Read current value of the MCG_SC_LOCS0 field.
bogdanm	82:6473597d706e	1361	#define BR_MCG_SC_LOCS0 (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_LOCS0))
bogdanm	82:6473597d706e	1362	#endif
bogdanm	82:6473597d706e	1363
bogdanm	82:6473597d706e	1364	//! @brief Format value for bitfield MCG_SC_LOCS0.
bogdanm	82:6473597d706e	1365	#define BF_MCG_SC_LOCS0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_LOCS0), uint8_t) & BM_MCG_SC_LOCS0)
bogdanm	82:6473597d706e	1366
bogdanm	82:6473597d706e	1367	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1368	//! @brief Set the LOCS0 field to a new value.
bogdanm	82:6473597d706e	1369	#define BW_MCG_SC_LOCS0(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_LOCS0) = (v))
bogdanm	82:6473597d706e	1370	#endif
bogdanm	82:6473597d706e	1371	//@}
bogdanm	82:6473597d706e	1372
bogdanm	82:6473597d706e	1373	/*!
bogdanm	82:6473597d706e	1374	* @name Register MCG_SC, field FCRDIV[3:1] (RW)
bogdanm	82:6473597d706e	1375	*
bogdanm	82:6473597d706e	1376	* Selects the amount to divide down the fast internal reference clock. The
bogdanm	82:6473597d706e	1377	* resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
bogdanm	82:6473597d706e	1378	* divider when the Fast IRC is enabled is not supported).
bogdanm	82:6473597d706e	1379	*
bogdanm	82:6473597d706e	1380	* Values:
bogdanm	82:6473597d706e	1381	* - 000 - Divide Factor is 1
bogdanm	82:6473597d706e	1382	* - 001 - Divide Factor is 2.
bogdanm	82:6473597d706e	1383	* - 010 - Divide Factor is 4.
bogdanm	82:6473597d706e	1384	* - 011 - Divide Factor is 8.
bogdanm	82:6473597d706e	1385	* - 100 - Divide Factor is 16
bogdanm	82:6473597d706e	1386	* - 101 - Divide Factor is 32
bogdanm	82:6473597d706e	1387	* - 110 - Divide Factor is 64
bogdanm	82:6473597d706e	1388	* - 111 - Divide Factor is 128.
bogdanm	82:6473597d706e	1389	*/
bogdanm	82:6473597d706e	1390	//@{
bogdanm	82:6473597d706e	1391	#define BP_MCG_SC_FCRDIV (1U) //!< Bit position for MCG_SC_FCRDIV.
bogdanm	82:6473597d706e	1392	#define BM_MCG_SC_FCRDIV (0x0EU) //!< Bit mask for MCG_SC_FCRDIV.
bogdanm	82:6473597d706e	1393	#define BS_MCG_SC_FCRDIV (3U) //!< Bit field size in bits for MCG_SC_FCRDIV.
bogdanm	82:6473597d706e	1394
bogdanm	82:6473597d706e	1395	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1396	//! @brief Read current value of the MCG_SC_FCRDIV field.
bogdanm	82:6473597d706e	1397	#define BR_MCG_SC_FCRDIV (HW_MCG_SC.B.FCRDIV)
bogdanm	82:6473597d706e	1398	#endif
bogdanm	82:6473597d706e	1399
bogdanm	82:6473597d706e	1400	//! @brief Format value for bitfield MCG_SC_FCRDIV.
bogdanm	82:6473597d706e	1401	#define BF_MCG_SC_FCRDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_FCRDIV), uint8_t) & BM_MCG_SC_FCRDIV)
bogdanm	82:6473597d706e	1402
bogdanm	82:6473597d706e	1403	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1404	//! @brief Set the FCRDIV field to a new value.
bogdanm	82:6473597d706e	1405	#define BW_MCG_SC_FCRDIV(v) (HW_MCG_SC_WR((HW_MCG_SC_RD() & ~BM_MCG_SC_FCRDIV) \| BF_MCG_SC_FCRDIV(v)))
bogdanm	82:6473597d706e	1406	#endif
bogdanm	82:6473597d706e	1407	//@}
bogdanm	82:6473597d706e	1408
bogdanm	82:6473597d706e	1409	/*!
bogdanm	82:6473597d706e	1410	* @name Register MCG_SC, field FLTPRSRV[4] (RW)
bogdanm	82:6473597d706e	1411	*
bogdanm	82:6473597d706e	1412	* This bit will prevent the FLL filter values from resetting allowing the FLL
bogdanm	82:6473597d706e	1413	* output frequency to remain the same during clock mode changes where the FLL/DCO
bogdanm	82:6473597d706e	1414	* output is still valid. (Note: This requires that the FLL reference frequency
bogdanm	82:6473597d706e	1415	* to remain the same as what it was prior to the new clock mode switch.
bogdanm	82:6473597d706e	1416	* Otherwise FLL filter and frequency values will change.)
bogdanm	82:6473597d706e	1417	*
bogdanm	82:6473597d706e	1418	* Values:
bogdanm	82:6473597d706e	1419	* - 0 - FLL filter and FLL frequency will reset on changes to currect clock
bogdanm	82:6473597d706e	1420	* mode.
bogdanm	82:6473597d706e	1421	* - 1 - Fll filter and FLL frequency retain their previous values during new
bogdanm	82:6473597d706e	1422	* clock mode change.
bogdanm	82:6473597d706e	1423	*/
bogdanm	82:6473597d706e	1424	//@{
bogdanm	82:6473597d706e	1425	#define BP_MCG_SC_FLTPRSRV (4U) //!< Bit position for MCG_SC_FLTPRSRV.
bogdanm	82:6473597d706e	1426	#define BM_MCG_SC_FLTPRSRV (0x10U) //!< Bit mask for MCG_SC_FLTPRSRV.
bogdanm	82:6473597d706e	1427	#define BS_MCG_SC_FLTPRSRV (1U) //!< Bit field size in bits for MCG_SC_FLTPRSRV.
bogdanm	82:6473597d706e	1428
bogdanm	82:6473597d706e	1429	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1430	//! @brief Read current value of the MCG_SC_FLTPRSRV field.
bogdanm	82:6473597d706e	1431	#define BR_MCG_SC_FLTPRSRV (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_FLTPRSRV))
bogdanm	82:6473597d706e	1432	#endif
bogdanm	82:6473597d706e	1433
bogdanm	82:6473597d706e	1434	//! @brief Format value for bitfield MCG_SC_FLTPRSRV.
bogdanm	82:6473597d706e	1435	#define BF_MCG_SC_FLTPRSRV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_FLTPRSRV), uint8_t) & BM_MCG_SC_FLTPRSRV)
bogdanm	82:6473597d706e	1436
bogdanm	82:6473597d706e	1437	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1438	//! @brief Set the FLTPRSRV field to a new value.
bogdanm	82:6473597d706e	1439	#define BW_MCG_SC_FLTPRSRV(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_FLTPRSRV) = (v))
bogdanm	82:6473597d706e	1440	#endif
bogdanm	82:6473597d706e	1441	//@}
bogdanm	82:6473597d706e	1442
bogdanm	82:6473597d706e	1443	/*!
bogdanm	82:6473597d706e	1444	* @name Register MCG_SC, field ATMF[5] (RW)
bogdanm	82:6473597d706e	1445	*
bogdanm	82:6473597d706e	1446	* Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
bogdanm	82:6473597d706e	1447	* Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
bogdanm	82:6473597d706e	1448	* registers is detected or the MCG enters into any Stop mode. A write to ATMF
bogdanm	82:6473597d706e	1449	* clears the flag.
bogdanm	82:6473597d706e	1450	*
bogdanm	82:6473597d706e	1451	* Values:
bogdanm	82:6473597d706e	1452	* - 0 - Automatic Trim Machine completed normally.
bogdanm	82:6473597d706e	1453	* - 1 - Automatic Trim Machine failed.
bogdanm	82:6473597d706e	1454	*/
bogdanm	82:6473597d706e	1455	//@{
bogdanm	82:6473597d706e	1456	#define BP_MCG_SC_ATMF (5U) //!< Bit position for MCG_SC_ATMF.
bogdanm	82:6473597d706e	1457	#define BM_MCG_SC_ATMF (0x20U) //!< Bit mask for MCG_SC_ATMF.
bogdanm	82:6473597d706e	1458	#define BS_MCG_SC_ATMF (1U) //!< Bit field size in bits for MCG_SC_ATMF.
bogdanm	82:6473597d706e	1459
bogdanm	82:6473597d706e	1460	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1461	//! @brief Read current value of the MCG_SC_ATMF field.
bogdanm	82:6473597d706e	1462	#define BR_MCG_SC_ATMF (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMF))
bogdanm	82:6473597d706e	1463	#endif
bogdanm	82:6473597d706e	1464
bogdanm	82:6473597d706e	1465	//! @brief Format value for bitfield MCG_SC_ATMF.
bogdanm	82:6473597d706e	1466	#define BF_MCG_SC_ATMF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATMF), uint8_t) & BM_MCG_SC_ATMF)
bogdanm	82:6473597d706e	1467
bogdanm	82:6473597d706e	1468	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1469	//! @brief Set the ATMF field to a new value.
bogdanm	82:6473597d706e	1470	#define BW_MCG_SC_ATMF(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMF) = (v))
bogdanm	82:6473597d706e	1471	#endif
bogdanm	82:6473597d706e	1472	//@}
bogdanm	82:6473597d706e	1473
bogdanm	82:6473597d706e	1474	/*!
bogdanm	82:6473597d706e	1475	* @name Register MCG_SC, field ATMS[6] (RW)
bogdanm	82:6473597d706e	1476	*
bogdanm	82:6473597d706e	1477	* Selects the IRCS clock for Auto Trim Test.
bogdanm	82:6473597d706e	1478	*
bogdanm	82:6473597d706e	1479	* Values:
bogdanm	82:6473597d706e	1480	* - 0 - 32 kHz Internal Reference Clock selected.
bogdanm	82:6473597d706e	1481	* - 1 - 4 MHz Internal Reference Clock selected.
bogdanm	82:6473597d706e	1482	*/
bogdanm	82:6473597d706e	1483	//@{
bogdanm	82:6473597d706e	1484	#define BP_MCG_SC_ATMS (6U) //!< Bit position for MCG_SC_ATMS.
bogdanm	82:6473597d706e	1485	#define BM_MCG_SC_ATMS (0x40U) //!< Bit mask for MCG_SC_ATMS.
bogdanm	82:6473597d706e	1486	#define BS_MCG_SC_ATMS (1U) //!< Bit field size in bits for MCG_SC_ATMS.
bogdanm	82:6473597d706e	1487
bogdanm	82:6473597d706e	1488	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1489	//! @brief Read current value of the MCG_SC_ATMS field.
bogdanm	82:6473597d706e	1490	#define BR_MCG_SC_ATMS (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMS))
bogdanm	82:6473597d706e	1491	#endif
bogdanm	82:6473597d706e	1492
bogdanm	82:6473597d706e	1493	//! @brief Format value for bitfield MCG_SC_ATMS.
bogdanm	82:6473597d706e	1494	#define BF_MCG_SC_ATMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATMS), uint8_t) & BM_MCG_SC_ATMS)
bogdanm	82:6473597d706e	1495
bogdanm	82:6473597d706e	1496	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1497	//! @brief Set the ATMS field to a new value.
bogdanm	82:6473597d706e	1498	#define BW_MCG_SC_ATMS(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMS) = (v))
bogdanm	82:6473597d706e	1499	#endif
bogdanm	82:6473597d706e	1500	//@}
bogdanm	82:6473597d706e	1501
bogdanm	82:6473597d706e	1502	/*!
bogdanm	82:6473597d706e	1503	* @name Register MCG_SC, field ATME[7] (RW)
bogdanm	82:6473597d706e	1504	*
bogdanm	82:6473597d706e	1505	* Enables the Auto Trim Machine to start automatically trimming the selected
bogdanm	82:6473597d706e	1506	* Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
bogdanm	82:6473597d706e	1507	* completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
bogdanm	82:6473597d706e	1508	* to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
bogdanm	82:6473597d706e	1509	* operation and clears this bit.
bogdanm	82:6473597d706e	1510	*
bogdanm	82:6473597d706e	1511	* Values:
bogdanm	82:6473597d706e	1512	* - 0 - Auto Trim Machine disabled.
bogdanm	82:6473597d706e	1513	* - 1 - Auto Trim Machine enabled.
bogdanm	82:6473597d706e	1514	*/
bogdanm	82:6473597d706e	1515	//@{
bogdanm	82:6473597d706e	1516	#define BP_MCG_SC_ATME (7U) //!< Bit position for MCG_SC_ATME.
bogdanm	82:6473597d706e	1517	#define BM_MCG_SC_ATME (0x80U) //!< Bit mask for MCG_SC_ATME.
bogdanm	82:6473597d706e	1518	#define BS_MCG_SC_ATME (1U) //!< Bit field size in bits for MCG_SC_ATME.
bogdanm	82:6473597d706e	1519
bogdanm	82:6473597d706e	1520	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1521	//! @brief Read current value of the MCG_SC_ATME field.
bogdanm	82:6473597d706e	1522	#define BR_MCG_SC_ATME (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATME))
bogdanm	82:6473597d706e	1523	#endif
bogdanm	82:6473597d706e	1524
bogdanm	82:6473597d706e	1525	//! @brief Format value for bitfield MCG_SC_ATME.
bogdanm	82:6473597d706e	1526	#define BF_MCG_SC_ATME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATME), uint8_t) & BM_MCG_SC_ATME)
bogdanm	82:6473597d706e	1527
bogdanm	82:6473597d706e	1528	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1529	//! @brief Set the ATME field to a new value.
bogdanm	82:6473597d706e	1530	#define BW_MCG_SC_ATME(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATME) = (v))
bogdanm	82:6473597d706e	1531	#endif
bogdanm	82:6473597d706e	1532	//@}
bogdanm	82:6473597d706e	1533
bogdanm	82:6473597d706e	1534	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1535	// HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
bogdanm	82:6473597d706e	1536	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1537
bogdanm	82:6473597d706e	1538	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1539	/*!
bogdanm	82:6473597d706e	1540	* @brief HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
bogdanm	82:6473597d706e	1541	*
bogdanm	82:6473597d706e	1542	* Reset value: 0x00U
bogdanm	82:6473597d706e	1543	*/
bogdanm	82:6473597d706e	1544	typedef union _hw_mcg_atcvh
bogdanm	82:6473597d706e	1545	{
bogdanm	82:6473597d706e	1546	uint8_t U;
bogdanm	82:6473597d706e	1547	struct _hw_mcg_atcvh_bitfields
bogdanm	82:6473597d706e	1548	{
bogdanm	82:6473597d706e	1549	uint8_t ATCVH : 8; //!< [7:0] ATM Compare Value High
bogdanm	82:6473597d706e	1550	} B;
bogdanm	82:6473597d706e	1551	} hw_mcg_atcvh_t;
bogdanm	82:6473597d706e	1552	#endif
bogdanm	82:6473597d706e	1553
bogdanm	82:6473597d706e	1554	/*!
bogdanm	82:6473597d706e	1555	* @name Constants and macros for entire MCG_ATCVH register
bogdanm	82:6473597d706e	1556	*/
bogdanm	82:6473597d706e	1557	//@{
bogdanm	82:6473597d706e	1558	#define HW_MCG_ATCVH_ADDR (REGS_MCG_BASE + 0xAU)
bogdanm	82:6473597d706e	1559
bogdanm	82:6473597d706e	1560	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1561	#define HW_MCG_ATCVH ((__IO hw_mcg_atcvh_t ) HW_MCG_ATCVH_ADDR)
bogdanm	82:6473597d706e	1562	#define HW_MCG_ATCVH_RD() (HW_MCG_ATCVH.U)
bogdanm	82:6473597d706e	1563	#define HW_MCG_ATCVH_WR(v) (HW_MCG_ATCVH.U = (v))
bogdanm	82:6473597d706e	1564	#define HW_MCG_ATCVH_SET(v) (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() \| (v)))
bogdanm	82:6473597d706e	1565	#define HW_MCG_ATCVH_CLR(v) (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() & ~(v)))
bogdanm	82:6473597d706e	1566	#define HW_MCG_ATCVH_TOG(v) (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() ^ (v)))
bogdanm	82:6473597d706e	1567	#endif
bogdanm	82:6473597d706e	1568	//@}
bogdanm	82:6473597d706e	1569
bogdanm	82:6473597d706e	1570	/*
bogdanm	82:6473597d706e	1571	* Constants & macros for individual MCG_ATCVH bitfields
bogdanm	82:6473597d706e	1572	*/
bogdanm	82:6473597d706e	1573
bogdanm	82:6473597d706e	1574	/*!
bogdanm	82:6473597d706e	1575	* @name Register MCG_ATCVH, field ATCVH[7:0] (RW)
bogdanm	82:6473597d706e	1576	*
bogdanm	82:6473597d706e	1577	* Values are used by Auto Trim Machine to compare and adjust Internal Reference
bogdanm	82:6473597d706e	1578	* trim values during ATM SAR conversion.
bogdanm	82:6473597d706e	1579	*/
bogdanm	82:6473597d706e	1580	//@{
bogdanm	82:6473597d706e	1581	#define BP_MCG_ATCVH_ATCVH (0U) //!< Bit position for MCG_ATCVH_ATCVH.
bogdanm	82:6473597d706e	1582	#define BM_MCG_ATCVH_ATCVH (0xFFU) //!< Bit mask for MCG_ATCVH_ATCVH.
bogdanm	82:6473597d706e	1583	#define BS_MCG_ATCVH_ATCVH (8U) //!< Bit field size in bits for MCG_ATCVH_ATCVH.
bogdanm	82:6473597d706e	1584
bogdanm	82:6473597d706e	1585	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1586	//! @brief Read current value of the MCG_ATCVH_ATCVH field.
bogdanm	82:6473597d706e	1587	#define BR_MCG_ATCVH_ATCVH (HW_MCG_ATCVH.U)
bogdanm	82:6473597d706e	1588	#endif
bogdanm	82:6473597d706e	1589
bogdanm	82:6473597d706e	1590	//! @brief Format value for bitfield MCG_ATCVH_ATCVH.
bogdanm	82:6473597d706e	1591	#define BF_MCG_ATCVH_ATCVH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_ATCVH_ATCVH), uint8_t) & BM_MCG_ATCVH_ATCVH)
bogdanm	82:6473597d706e	1592
bogdanm	82:6473597d706e	1593	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1594	//! @brief Set the ATCVH field to a new value.
bogdanm	82:6473597d706e	1595	#define BW_MCG_ATCVH_ATCVH(v) (HW_MCG_ATCVH_WR(v))
bogdanm	82:6473597d706e	1596	#endif
bogdanm	82:6473597d706e	1597	//@}
bogdanm	82:6473597d706e	1598
bogdanm	82:6473597d706e	1599	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1600	// HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
bogdanm	82:6473597d706e	1601	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1602
bogdanm	82:6473597d706e	1603	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1604	/*!
bogdanm	82:6473597d706e	1605	* @brief HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
bogdanm	82:6473597d706e	1606	*
bogdanm	82:6473597d706e	1607	* Reset value: 0x00U
bogdanm	82:6473597d706e	1608	*/
bogdanm	82:6473597d706e	1609	typedef union _hw_mcg_atcvl
bogdanm	82:6473597d706e	1610	{
bogdanm	82:6473597d706e	1611	uint8_t U;
bogdanm	82:6473597d706e	1612	struct _hw_mcg_atcvl_bitfields
bogdanm	82:6473597d706e	1613	{
bogdanm	82:6473597d706e	1614	uint8_t ATCVL : 8; //!< [7:0] ATM Compare Value Low
bogdanm	82:6473597d706e	1615	} B;
bogdanm	82:6473597d706e	1616	} hw_mcg_atcvl_t;
bogdanm	82:6473597d706e	1617	#endif
bogdanm	82:6473597d706e	1618
bogdanm	82:6473597d706e	1619	/*!
bogdanm	82:6473597d706e	1620	* @name Constants and macros for entire MCG_ATCVL register
bogdanm	82:6473597d706e	1621	*/
bogdanm	82:6473597d706e	1622	//@{
bogdanm	82:6473597d706e	1623	#define HW_MCG_ATCVL_ADDR (REGS_MCG_BASE + 0xBU)
bogdanm	82:6473597d706e	1624
bogdanm	82:6473597d706e	1625	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1626	#define HW_MCG_ATCVL ((__IO hw_mcg_atcvl_t ) HW_MCG_ATCVL_ADDR)
bogdanm	82:6473597d706e	1627	#define HW_MCG_ATCVL_RD() (HW_MCG_ATCVL.U)
bogdanm	82:6473597d706e	1628	#define HW_MCG_ATCVL_WR(v) (HW_MCG_ATCVL.U = (v))
bogdanm	82:6473597d706e	1629	#define HW_MCG_ATCVL_SET(v) (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() \| (v)))
bogdanm	82:6473597d706e	1630	#define HW_MCG_ATCVL_CLR(v) (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() & ~(v)))
bogdanm	82:6473597d706e	1631	#define HW_MCG_ATCVL_TOG(v) (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() ^ (v)))
bogdanm	82:6473597d706e	1632	#endif
bogdanm	82:6473597d706e	1633	//@}
bogdanm	82:6473597d706e	1634
bogdanm	82:6473597d706e	1635	/*
bogdanm	82:6473597d706e	1636	* Constants & macros for individual MCG_ATCVL bitfields
bogdanm	82:6473597d706e	1637	*/
bogdanm	82:6473597d706e	1638
bogdanm	82:6473597d706e	1639	/*!
bogdanm	82:6473597d706e	1640	* @name Register MCG_ATCVL, field ATCVL[7:0] (RW)
bogdanm	82:6473597d706e	1641	*
bogdanm	82:6473597d706e	1642	* Values are used by Auto Trim Machine to compare and adjust Internal Reference
bogdanm	82:6473597d706e	1643	* trim values during ATM SAR conversion.
bogdanm	82:6473597d706e	1644	*/
bogdanm	82:6473597d706e	1645	//@{
bogdanm	82:6473597d706e	1646	#define BP_MCG_ATCVL_ATCVL (0U) //!< Bit position for MCG_ATCVL_ATCVL.
bogdanm	82:6473597d706e	1647	#define BM_MCG_ATCVL_ATCVL (0xFFU) //!< Bit mask for MCG_ATCVL_ATCVL.
bogdanm	82:6473597d706e	1648	#define BS_MCG_ATCVL_ATCVL (8U) //!< Bit field size in bits for MCG_ATCVL_ATCVL.
bogdanm	82:6473597d706e	1649
bogdanm	82:6473597d706e	1650	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1651	//! @brief Read current value of the MCG_ATCVL_ATCVL field.
bogdanm	82:6473597d706e	1652	#define BR_MCG_ATCVL_ATCVL (HW_MCG_ATCVL.U)
bogdanm	82:6473597d706e	1653	#endif
bogdanm	82:6473597d706e	1654
bogdanm	82:6473597d706e	1655	//! @brief Format value for bitfield MCG_ATCVL_ATCVL.
bogdanm	82:6473597d706e	1656	#define BF_MCG_ATCVL_ATCVL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_ATCVL_ATCVL), uint8_t) & BM_MCG_ATCVL_ATCVL)
bogdanm	82:6473597d706e	1657
bogdanm	82:6473597d706e	1658	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1659	//! @brief Set the ATCVL field to a new value.
bogdanm	82:6473597d706e	1660	#define BW_MCG_ATCVL_ATCVL(v) (HW_MCG_ATCVL_WR(v))
bogdanm	82:6473597d706e	1661	#endif
bogdanm	82:6473597d706e	1662	//@}
bogdanm	82:6473597d706e	1663
bogdanm	82:6473597d706e	1664	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1665	// HW_MCG_C7 - MCG Control 7 Register
bogdanm	82:6473597d706e	1666	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1667
bogdanm	82:6473597d706e	1668	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1669	/*!
bogdanm	82:6473597d706e	1670	* @brief HW_MCG_C7 - MCG Control 7 Register (RW)
bogdanm	82:6473597d706e	1671	*
bogdanm	82:6473597d706e	1672	* Reset value: 0x00U
bogdanm	82:6473597d706e	1673	*/
bogdanm	82:6473597d706e	1674	typedef union _hw_mcg_c7
bogdanm	82:6473597d706e	1675	{
bogdanm	82:6473597d706e	1676	uint8_t U;
bogdanm	82:6473597d706e	1677	struct _hw_mcg_c7_bitfields
bogdanm	82:6473597d706e	1678	{
bogdanm	82:6473597d706e	1679	uint8_t OSCSEL : 2; //!< [1:0] MCG OSC Clock Select
bogdanm	82:6473597d706e	1680	uint8_t RESERVED0 : 6; //!< [7:2]
bogdanm	82:6473597d706e	1681	} B;
bogdanm	82:6473597d706e	1682	} hw_mcg_c7_t;
bogdanm	82:6473597d706e	1683	#endif
bogdanm	82:6473597d706e	1684
bogdanm	82:6473597d706e	1685	/*!
bogdanm	82:6473597d706e	1686	* @name Constants and macros for entire MCG_C7 register
bogdanm	82:6473597d706e	1687	*/
bogdanm	82:6473597d706e	1688	//@{
bogdanm	82:6473597d706e	1689	#define HW_MCG_C7_ADDR (REGS_MCG_BASE + 0xCU)
bogdanm	82:6473597d706e	1690
bogdanm	82:6473597d706e	1691	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1692	#define HW_MCG_C7 ((__IO hw_mcg_c7_t ) HW_MCG_C7_ADDR)
bogdanm	82:6473597d706e	1693	#define HW_MCG_C7_RD() (HW_MCG_C7.U)
bogdanm	82:6473597d706e	1694	#define HW_MCG_C7_WR(v) (HW_MCG_C7.U = (v))
bogdanm	82:6473597d706e	1695	#define HW_MCG_C7_SET(v) (HW_MCG_C7_WR(HW_MCG_C7_RD() \| (v)))
bogdanm	82:6473597d706e	1696	#define HW_MCG_C7_CLR(v) (HW_MCG_C7_WR(HW_MCG_C7_RD() & ~(v)))
bogdanm	82:6473597d706e	1697	#define HW_MCG_C7_TOG(v) (HW_MCG_C7_WR(HW_MCG_C7_RD() ^ (v)))
bogdanm	82:6473597d706e	1698	#endif
bogdanm	82:6473597d706e	1699	//@}
bogdanm	82:6473597d706e	1700
bogdanm	82:6473597d706e	1701	/*
bogdanm	82:6473597d706e	1702	* Constants & macros for individual MCG_C7 bitfields
bogdanm	82:6473597d706e	1703	*/
bogdanm	82:6473597d706e	1704
bogdanm	82:6473597d706e	1705	/*!
bogdanm	82:6473597d706e	1706	* @name Register MCG_C7, field OSCSEL[1:0] (RW)
bogdanm	82:6473597d706e	1707	*
bogdanm	82:6473597d706e	1708	* Selects the MCG FLL external reference clock
bogdanm	82:6473597d706e	1709	*
bogdanm	82:6473597d706e	1710	* Values:
bogdanm	82:6473597d706e	1711	* - 00 - Selects Oscillator (OSCCLK0).
bogdanm	82:6473597d706e	1712	* - 01 - Selects 32 kHz RTC Oscillator.
bogdanm	82:6473597d706e	1713	* - 10 - Selects Oscillator (OSCCLK1).
bogdanm	82:6473597d706e	1714	* - 11 - RESERVED
bogdanm	82:6473597d706e	1715	*/
bogdanm	82:6473597d706e	1716	//@{
bogdanm	82:6473597d706e	1717	#define BP_MCG_C7_OSCSEL (0U) //!< Bit position for MCG_C7_OSCSEL.
bogdanm	82:6473597d706e	1718	#define BM_MCG_C7_OSCSEL (0x03U) //!< Bit mask for MCG_C7_OSCSEL.
bogdanm	82:6473597d706e	1719	#define BS_MCG_C7_OSCSEL (2U) //!< Bit field size in bits for MCG_C7_OSCSEL.
bogdanm	82:6473597d706e	1720
bogdanm	82:6473597d706e	1721	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1722	//! @brief Read current value of the MCG_C7_OSCSEL field.
bogdanm	82:6473597d706e	1723	#define BR_MCG_C7_OSCSEL (HW_MCG_C7.B.OSCSEL)
bogdanm	82:6473597d706e	1724	#endif
bogdanm	82:6473597d706e	1725
bogdanm	82:6473597d706e	1726	//! @brief Format value for bitfield MCG_C7_OSCSEL.
bogdanm	82:6473597d706e	1727	#define BF_MCG_C7_OSCSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C7_OSCSEL), uint8_t) & BM_MCG_C7_OSCSEL)
bogdanm	82:6473597d706e	1728
bogdanm	82:6473597d706e	1729	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1730	//! @brief Set the OSCSEL field to a new value.
bogdanm	82:6473597d706e	1731	#define BW_MCG_C7_OSCSEL(v) (HW_MCG_C7_WR((HW_MCG_C7_RD() & ~BM_MCG_C7_OSCSEL) \| BF_MCG_C7_OSCSEL(v)))
bogdanm	82:6473597d706e	1732	#endif
bogdanm	82:6473597d706e	1733	//@}
bogdanm	82:6473597d706e	1734
bogdanm	82:6473597d706e	1735	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1736	// HW_MCG_C8 - MCG Control 8 Register
bogdanm	82:6473597d706e	1737	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1738
bogdanm	82:6473597d706e	1739	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1740	/*!
bogdanm	82:6473597d706e	1741	* @brief HW_MCG_C8 - MCG Control 8 Register (RW)
bogdanm	82:6473597d706e	1742	*
bogdanm	82:6473597d706e	1743	* Reset value: 0x80U
bogdanm	82:6473597d706e	1744	*/
bogdanm	82:6473597d706e	1745	typedef union _hw_mcg_c8
bogdanm	82:6473597d706e	1746	{
bogdanm	82:6473597d706e	1747	uint8_t U;
bogdanm	82:6473597d706e	1748	struct _hw_mcg_c8_bitfields
bogdanm	82:6473597d706e	1749	{
bogdanm	82:6473597d706e	1750	uint8_t LOCS1 : 1; //!< [0] RTC Loss of Clock Status
bogdanm	82:6473597d706e	1751	uint8_t RESERVED0 : 4; //!< [4:1]
bogdanm	82:6473597d706e	1752	uint8_t CME1 : 1; //!< [5] Clock Monitor Enable1
bogdanm	82:6473597d706e	1753	uint8_t LOLRE : 1; //!< [6] PLL Loss of Lock Reset Enable
bogdanm	82:6473597d706e	1754	uint8_t LOCRE1 : 1; //!< [7] Loss of Clock Reset Enable
bogdanm	82:6473597d706e	1755	} B;
bogdanm	82:6473597d706e	1756	} hw_mcg_c8_t;
bogdanm	82:6473597d706e	1757	#endif
bogdanm	82:6473597d706e	1758
bogdanm	82:6473597d706e	1759	/*!
bogdanm	82:6473597d706e	1760	* @name Constants and macros for entire MCG_C8 register
bogdanm	82:6473597d706e	1761	*/
bogdanm	82:6473597d706e	1762	//@{
bogdanm	82:6473597d706e	1763	#define HW_MCG_C8_ADDR (REGS_MCG_BASE + 0xDU)
bogdanm	82:6473597d706e	1764
bogdanm	82:6473597d706e	1765	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1766	#define HW_MCG_C8 ((__IO hw_mcg_c8_t ) HW_MCG_C8_ADDR)
bogdanm	82:6473597d706e	1767	#define HW_MCG_C8_RD() (HW_MCG_C8.U)
bogdanm	82:6473597d706e	1768	#define HW_MCG_C8_WR(v) (HW_MCG_C8.U = (v))
bogdanm	82:6473597d706e	1769	#define HW_MCG_C8_SET(v) (HW_MCG_C8_WR(HW_MCG_C8_RD() \| (v)))
bogdanm	82:6473597d706e	1770	#define HW_MCG_C8_CLR(v) (HW_MCG_C8_WR(HW_MCG_C8_RD() & ~(v)))
bogdanm	82:6473597d706e	1771	#define HW_MCG_C8_TOG(v) (HW_MCG_C8_WR(HW_MCG_C8_RD() ^ (v)))
bogdanm	82:6473597d706e	1772	#endif
bogdanm	82:6473597d706e	1773	//@}
bogdanm	82:6473597d706e	1774
bogdanm	82:6473597d706e	1775	/*
bogdanm	82:6473597d706e	1776	* Constants & macros for individual MCG_C8 bitfields
bogdanm	82:6473597d706e	1777	*/
bogdanm	82:6473597d706e	1778
bogdanm	82:6473597d706e	1779	/*!
bogdanm	82:6473597d706e	1780	* @name Register MCG_C8, field LOCS1[0] (W1C)
bogdanm	82:6473597d706e	1781	*
bogdanm	82:6473597d706e	1782	* This bit indicates when a loss of clock has occurred. This bit is cleared by
bogdanm	82:6473597d706e	1783	* writing a logic 1 to it when set.
bogdanm	82:6473597d706e	1784	*
bogdanm	82:6473597d706e	1785	* Values:
bogdanm	82:6473597d706e	1786	* - 0 - Loss of RTC has not occur.
bogdanm	82:6473597d706e	1787	* - 1 - Loss of RTC has occur
bogdanm	82:6473597d706e	1788	*/
bogdanm	82:6473597d706e	1789	//@{
bogdanm	82:6473597d706e	1790	#define BP_MCG_C8_LOCS1 (0U) //!< Bit position for MCG_C8_LOCS1.
bogdanm	82:6473597d706e	1791	#define BM_MCG_C8_LOCS1 (0x01U) //!< Bit mask for MCG_C8_LOCS1.
bogdanm	82:6473597d706e	1792	#define BS_MCG_C8_LOCS1 (1U) //!< Bit field size in bits for MCG_C8_LOCS1.
bogdanm	82:6473597d706e	1793
bogdanm	82:6473597d706e	1794	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1795	//! @brief Read current value of the MCG_C8_LOCS1 field.
bogdanm	82:6473597d706e	1796	#define BR_MCG_C8_LOCS1 (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCS1))
bogdanm	82:6473597d706e	1797	#endif
bogdanm	82:6473597d706e	1798
bogdanm	82:6473597d706e	1799	//! @brief Format value for bitfield MCG_C8_LOCS1.
bogdanm	82:6473597d706e	1800	#define BF_MCG_C8_LOCS1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOCS1), uint8_t) & BM_MCG_C8_LOCS1)
bogdanm	82:6473597d706e	1801
bogdanm	82:6473597d706e	1802	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1803	//! @brief Set the LOCS1 field to a new value.
bogdanm	82:6473597d706e	1804	#define BW_MCG_C8_LOCS1(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCS1) = (v))
bogdanm	82:6473597d706e	1805	#endif
bogdanm	82:6473597d706e	1806	//@}
bogdanm	82:6473597d706e	1807
bogdanm	82:6473597d706e	1808	/*!
bogdanm	82:6473597d706e	1809	* @name Register MCG_C8, field CME1[5] (RW)
bogdanm	82:6473597d706e	1810	*
bogdanm	82:6473597d706e	1811	* Enables the loss of clock monitoring circuit for the output of the RTC
bogdanm	82:6473597d706e	1812	* external reference clock. The LOCRE1 bit will determine whether an interrupt or a
bogdanm	82:6473597d706e	1813	* reset request is generated following a loss of RTC clock indication. The CME1
bogdanm	82:6473597d706e	1814	* bit should be set to a logic 1 when the MCG is in an operational mode that uses
bogdanm	82:6473597d706e	1815	* the RTC as its external reference clock or if the RTC is operational. CME1 bit
bogdanm	82:6473597d706e	1816	* must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
bogdanm	82:6473597d706e	1817	* reset request may occur when in Stop mode. CME1 should also be set to a logic 0
bogdanm	82:6473597d706e	1818	* before entering VLPR or VLPW power modes.
bogdanm	82:6473597d706e	1819	*
bogdanm	82:6473597d706e	1820	* Values:
bogdanm	82:6473597d706e	1821	* - 0 - External clock monitor is disabled for RTC clock.
bogdanm	82:6473597d706e	1822	* - 1 - External clock monitor is enabled for RTC clock.
bogdanm	82:6473597d706e	1823	*/
bogdanm	82:6473597d706e	1824	//@{
bogdanm	82:6473597d706e	1825	#define BP_MCG_C8_CME1 (5U) //!< Bit position for MCG_C8_CME1.
bogdanm	82:6473597d706e	1826	#define BM_MCG_C8_CME1 (0x20U) //!< Bit mask for MCG_C8_CME1.
bogdanm	82:6473597d706e	1827	#define BS_MCG_C8_CME1 (1U) //!< Bit field size in bits for MCG_C8_CME1.
bogdanm	82:6473597d706e	1828
bogdanm	82:6473597d706e	1829	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1830	//! @brief Read current value of the MCG_C8_CME1 field.
bogdanm	82:6473597d706e	1831	#define BR_MCG_C8_CME1 (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_CME1))
bogdanm	82:6473597d706e	1832	#endif
bogdanm	82:6473597d706e	1833
bogdanm	82:6473597d706e	1834	//! @brief Format value for bitfield MCG_C8_CME1.
bogdanm	82:6473597d706e	1835	#define BF_MCG_C8_CME1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_CME1), uint8_t) & BM_MCG_C8_CME1)
bogdanm	82:6473597d706e	1836
bogdanm	82:6473597d706e	1837	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1838	//! @brief Set the CME1 field to a new value.
bogdanm	82:6473597d706e	1839	#define BW_MCG_C8_CME1(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_CME1) = (v))
bogdanm	82:6473597d706e	1840	#endif
bogdanm	82:6473597d706e	1841	//@}
bogdanm	82:6473597d706e	1842
bogdanm	82:6473597d706e	1843	/*!
bogdanm	82:6473597d706e	1844	* @name Register MCG_C8, field LOLRE[6] (RW)
bogdanm	82:6473597d706e	1845	*
bogdanm	82:6473597d706e	1846	* Determines if an interrupt or a reset request is made following a PLL loss of
bogdanm	82:6473597d706e	1847	* lock.
bogdanm	82:6473597d706e	1848	*
bogdanm	82:6473597d706e	1849	* Values:
bogdanm	82:6473597d706e	1850	* - 0 - Interrupt request is generated on a PLL loss of lock indication. The
bogdanm	82:6473597d706e	1851	* PLL loss of lock interrupt enable bit must also be set to generate the
bogdanm	82:6473597d706e	1852	* interrupt request.
bogdanm	82:6473597d706e	1853	* - 1 - Generate a reset request on a PLL loss of lock indication.
bogdanm	82:6473597d706e	1854	*/
bogdanm	82:6473597d706e	1855	//@{
bogdanm	82:6473597d706e	1856	#define BP_MCG_C8_LOLRE (6U) //!< Bit position for MCG_C8_LOLRE.
bogdanm	82:6473597d706e	1857	#define BM_MCG_C8_LOLRE (0x40U) //!< Bit mask for MCG_C8_LOLRE.
bogdanm	82:6473597d706e	1858	#define BS_MCG_C8_LOLRE (1U) //!< Bit field size in bits for MCG_C8_LOLRE.
bogdanm	82:6473597d706e	1859
bogdanm	82:6473597d706e	1860	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1861	//! @brief Read current value of the MCG_C8_LOLRE field.
bogdanm	82:6473597d706e	1862	#define BR_MCG_C8_LOLRE (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOLRE))
bogdanm	82:6473597d706e	1863	#endif
bogdanm	82:6473597d706e	1864
bogdanm	82:6473597d706e	1865	//! @brief Format value for bitfield MCG_C8_LOLRE.
bogdanm	82:6473597d706e	1866	#define BF_MCG_C8_LOLRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOLRE), uint8_t) & BM_MCG_C8_LOLRE)
bogdanm	82:6473597d706e	1867
bogdanm	82:6473597d706e	1868	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1869	//! @brief Set the LOLRE field to a new value.
bogdanm	82:6473597d706e	1870	#define BW_MCG_C8_LOLRE(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOLRE) = (v))
bogdanm	82:6473597d706e	1871	#endif
bogdanm	82:6473597d706e	1872	//@}
bogdanm	82:6473597d706e	1873
bogdanm	82:6473597d706e	1874	/*!
bogdanm	82:6473597d706e	1875	* @name Register MCG_C8, field LOCRE1[7] (RW)
bogdanm	82:6473597d706e	1876	*
bogdanm	82:6473597d706e	1877	* Determines if a interrupt or a reset request is made following a loss of RTC
bogdanm	82:6473597d706e	1878	* external reference clock. The LOCRE1 only has an affect when CME1 is set.
bogdanm	82:6473597d706e	1879	*
bogdanm	82:6473597d706e	1880	* Values:
bogdanm	82:6473597d706e	1881	* - 0 - Interrupt request is generated on a loss of RTC external reference
bogdanm	82:6473597d706e	1882	* clock.
bogdanm	82:6473597d706e	1883	* - 1 - Generate a reset request on a loss of RTC external reference clock
bogdanm	82:6473597d706e	1884	*/
bogdanm	82:6473597d706e	1885	//@{
bogdanm	82:6473597d706e	1886	#define BP_MCG_C8_LOCRE1 (7U) //!< Bit position for MCG_C8_LOCRE1.
bogdanm	82:6473597d706e	1887	#define BM_MCG_C8_LOCRE1 (0x80U) //!< Bit mask for MCG_C8_LOCRE1.
bogdanm	82:6473597d706e	1888	#define BS_MCG_C8_LOCRE1 (1U) //!< Bit field size in bits for MCG_C8_LOCRE1.
bogdanm	82:6473597d706e	1889
bogdanm	82:6473597d706e	1890	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1891	//! @brief Read current value of the MCG_C8_LOCRE1 field.
bogdanm	82:6473597d706e	1892	#define BR_MCG_C8_LOCRE1 (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCRE1))
bogdanm	82:6473597d706e	1893	#endif
bogdanm	82:6473597d706e	1894
bogdanm	82:6473597d706e	1895	//! @brief Format value for bitfield MCG_C8_LOCRE1.
bogdanm	82:6473597d706e	1896	#define BF_MCG_C8_LOCRE1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOCRE1), uint8_t) & BM_MCG_C8_LOCRE1)
bogdanm	82:6473597d706e	1897
bogdanm	82:6473597d706e	1898	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1899	//! @brief Set the LOCRE1 field to a new value.
bogdanm	82:6473597d706e	1900	#define BW_MCG_C8_LOCRE1(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCRE1) = (v))
bogdanm	82:6473597d706e	1901	#endif
bogdanm	82:6473597d706e	1902	//@}
bogdanm	82:6473597d706e	1903
bogdanm	82:6473597d706e	1904	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1905	// hw_mcg_t - module struct
bogdanm	82:6473597d706e	1906	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1907	/*!
bogdanm	82:6473597d706e	1908	* @brief All MCG module registers.
bogdanm	82:6473597d706e	1909	*/
bogdanm	82:6473597d706e	1910	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1911	#pragma pack(1)
bogdanm	82:6473597d706e	1912	typedef struct _hw_mcg
bogdanm	82:6473597d706e	1913	{
bogdanm	82:6473597d706e	1914	__IO hw_mcg_c1_t C1; //!< [0x0] MCG Control 1 Register
bogdanm	82:6473597d706e	1915	__IO hw_mcg_c2_t C2; //!< [0x1] MCG Control 2 Register
bogdanm	82:6473597d706e	1916	__IO hw_mcg_c3_t C3; //!< [0x2] MCG Control 3 Register
bogdanm	82:6473597d706e	1917	__IO hw_mcg_c4_t C4; //!< [0x3] MCG Control 4 Register
bogdanm	82:6473597d706e	1918	__IO hw_mcg_c5_t C5; //!< [0x4] MCG Control 5 Register
bogdanm	82:6473597d706e	1919	__IO hw_mcg_c6_t C6; //!< [0x5] MCG Control 6 Register
bogdanm	82:6473597d706e	1920	__IO hw_mcg_s_t S; //!< [0x6] MCG Status Register
bogdanm	82:6473597d706e	1921	uint8_t _reserved0[1];
bogdanm	82:6473597d706e	1922	__IO hw_mcg_sc_t SC; //!< [0x8] MCG Status and Control Register
bogdanm	82:6473597d706e	1923	uint8_t _reserved1[1];
bogdanm	82:6473597d706e	1924	__IO hw_mcg_atcvh_t ATCVH; //!< [0xA] MCG Auto Trim Compare Value High Register
bogdanm	82:6473597d706e	1925	__IO hw_mcg_atcvl_t ATCVL; //!< [0xB] MCG Auto Trim Compare Value Low Register
bogdanm	82:6473597d706e	1926	__IO hw_mcg_c7_t C7; //!< [0xC] MCG Control 7 Register
bogdanm	82:6473597d706e	1927	__IO hw_mcg_c8_t C8; //!< [0xD] MCG Control 8 Register
bogdanm	82:6473597d706e	1928	} hw_mcg_t;
bogdanm	82:6473597d706e	1929	#pragma pack()
bogdanm	82:6473597d706e	1930
bogdanm	82:6473597d706e	1931	//! @brief Macro to access all MCG registers.
bogdanm	82:6473597d706e	1932	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	1933	//! use the '&' operator, like <code>&HW_MCG</code>.
bogdanm	82:6473597d706e	1934	#define HW_MCG ((hw_mcg_t ) REGS_MCG_BASE)
bogdanm	82:6473597d706e	1935	#endif
bogdanm	82:6473597d706e	1936
bogdanm	82:6473597d706e	1937	#endif // __HW_MCG_REGISTERS_H__
bogdanm	82:6473597d706e	1938	// v22/130726/0.9
bogdanm	82:6473597d706e	1939	// EOF

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Type:	Library
Created:	25 Jun 2015
Imports:	24
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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_mcg.h@89:552587b429a1, 2014-09-12 (annotated)

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