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mbed library

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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_lptmr.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:
bogdanm
Date:
Fri Sep 12 16:41:52 2014 +0100
Revision:
89:552587b429a1
Parent:
TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_lptmr.h@82:6473597d706e 
Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_LPTMR_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_LPTMR_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 LPTMR
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * Low Power Timer
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_LPTMR_CSR - Low Power Timer Control Status Register
bogdanm 82:6473597d706e 33 * - HW_LPTMR_PSR - Low Power Timer Prescale Register
bogdanm 82:6473597d706e 34 * - HW_LPTMR_CMR - Low Power Timer Compare Register
bogdanm 82:6473597d706e 35 * - HW_LPTMR_CNR - Low Power Timer Counter Register
bogdanm 82:6473597d706e 36 *
bogdanm 82:6473597d706e 37 * - hw_lptmr_t - Struct containing all module registers.
bogdanm 82:6473597d706e 38 */
bogdanm 82:6473597d706e 39
bogdanm 82:6473597d706e 40 //! @name Module base addresses
bogdanm 82:6473597d706e 41 //@{
bogdanm 82:6473597d706e 42 #ifndef REGS_LPTMR_BASE
bogdanm 82:6473597d706e 43 #define HW_LPTMR_INSTANCE_COUNT (1U) //!< Number of instances of the LPTMR module.
bogdanm 82:6473597d706e 44 #define REGS_LPTMR_BASE (0x40040000U) //!< Base address for LPTMR0.
bogdanm 82:6473597d706e 45 #endif
bogdanm 82:6473597d706e 46 //@}
bogdanm 82:6473597d706e 47
bogdanm 82:6473597d706e 48 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 49 // HW_LPTMR_CSR - Low Power Timer Control Status Register
bogdanm 82:6473597d706e 50 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 51
bogdanm 82:6473597d706e 52 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 53 /*!
bogdanm 82:6473597d706e 54 * @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW)
bogdanm 82:6473597d706e 55 *
bogdanm 82:6473597d706e 56 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 57 */
bogdanm 82:6473597d706e 58 typedef union _hw_lptmr_csr
bogdanm 82:6473597d706e 59 {
bogdanm 82:6473597d706e 60 uint32_t U;
bogdanm 82:6473597d706e 61 struct _hw_lptmr_csr_bitfields
bogdanm 82:6473597d706e 62 {
bogdanm 82:6473597d706e 63 uint32_t TEN : 1; //!< [0] Timer Enable
bogdanm 82:6473597d706e 64 uint32_t TMS : 1; //!< [1] Timer Mode Select
bogdanm 82:6473597d706e 65 uint32_t TFC : 1; //!< [2] Timer Free-Running Counter
bogdanm 82:6473597d706e 66 uint32_t TPP : 1; //!< [3] Timer Pin Polarity
bogdanm 82:6473597d706e 67 uint32_t TPS : 2; //!< [5:4] Timer Pin Select
bogdanm 82:6473597d706e 68 uint32_t TIE : 1; //!< [6] Timer Interrupt Enable
bogdanm 82:6473597d706e 69 uint32_t TCF : 1; //!< [7] Timer Compare Flag
bogdanm 82:6473597d706e 70 uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm 82:6473597d706e 71 } B;
bogdanm 82:6473597d706e 72 } hw_lptmr_csr_t;
bogdanm 82:6473597d706e 73 #endif
bogdanm 82:6473597d706e 74
bogdanm 82:6473597d706e 75 /*!
bogdanm 82:6473597d706e 76 * @name Constants and macros for entire LPTMR_CSR register
bogdanm 82:6473597d706e 77 */
bogdanm 82:6473597d706e 78 //@{
bogdanm 82:6473597d706e 79 #define HW_LPTMR_CSR_ADDR (REGS_LPTMR_BASE + 0x0U)
bogdanm 82:6473597d706e 80
bogdanm 82:6473597d706e 81 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 82 #define HW_LPTMR_CSR (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR)
bogdanm 82:6473597d706e 83 #define HW_LPTMR_CSR_RD() (HW_LPTMR_CSR.U)
bogdanm 82:6473597d706e 84 #define HW_LPTMR_CSR_WR(v) (HW_LPTMR_CSR.U = (v))
bogdanm 82:6473597d706e 85 #define HW_LPTMR_CSR_SET(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() | (v)))
bogdanm 82:6473597d706e 86 #define HW_LPTMR_CSR_CLR(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() & ~(v)))
bogdanm 82:6473597d706e 87 #define HW_LPTMR_CSR_TOG(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() ^ (v)))
bogdanm 82:6473597d706e 88 #endif
bogdanm 82:6473597d706e 89 //@}
bogdanm 82:6473597d706e 90
bogdanm 82:6473597d706e 91 /*
bogdanm 82:6473597d706e 92 * Constants & macros for individual LPTMR_CSR bitfields
bogdanm 82:6473597d706e 93 */
bogdanm 82:6473597d706e 94
bogdanm 82:6473597d706e 95 /*!
bogdanm 82:6473597d706e 96 * @name Register LPTMR_CSR, field TEN[0] (RW)
bogdanm 82:6473597d706e 97 *
bogdanm 82:6473597d706e 98 * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
bogdanm 82:6473597d706e 99 * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
bogdanm 82:6473597d706e 100 * CSR[5:1] must not be altered.
bogdanm 82:6473597d706e 101 *
bogdanm 82:6473597d706e 102 * Values:
bogdanm 82:6473597d706e 103 * - 0 - LPTMR is disabled and internal logic is reset.
bogdanm 82:6473597d706e 104 * - 1 - LPTMR is enabled.
bogdanm 82:6473597d706e 105 */
bogdanm 82:6473597d706e 106 //@{
bogdanm 82:6473597d706e 107 #define BP_LPTMR_CSR_TEN (0U) //!< Bit position for LPTMR_CSR_TEN.
bogdanm 82:6473597d706e 108 #define BM_LPTMR_CSR_TEN (0x00000001U) //!< Bit mask for LPTMR_CSR_TEN.
bogdanm 82:6473597d706e 109 #define BS_LPTMR_CSR_TEN (1U) //!< Bit field size in bits for LPTMR_CSR_TEN.
bogdanm 82:6473597d706e 110
bogdanm 82:6473597d706e 111 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 112 //! @brief Read current value of the LPTMR_CSR_TEN field.
bogdanm 82:6473597d706e 113 #define BR_LPTMR_CSR_TEN (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TEN))
bogdanm 82:6473597d706e 114 #endif
bogdanm 82:6473597d706e 115
bogdanm 82:6473597d706e 116 //! @brief Format value for bitfield LPTMR_CSR_TEN.
bogdanm 82:6473597d706e 117 #define BF_LPTMR_CSR_TEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TEN), uint32_t) & BM_LPTMR_CSR_TEN)
bogdanm 82:6473597d706e 118
bogdanm 82:6473597d706e 119 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 120 //! @brief Set the TEN field to a new value.
bogdanm 82:6473597d706e 121 #define BW_LPTMR_CSR_TEN(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TEN) = (v))
bogdanm 82:6473597d706e 122 #endif
bogdanm 82:6473597d706e 123 //@}
bogdanm 82:6473597d706e 124
bogdanm 82:6473597d706e 125 /*!
bogdanm 82:6473597d706e 126 * @name Register LPTMR_CSR, field TMS[1] (RW)
bogdanm 82:6473597d706e 127 *
bogdanm 82:6473597d706e 128 * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
bogdanm 82:6473597d706e 129 * disabled.
bogdanm 82:6473597d706e 130 *
bogdanm 82:6473597d706e 131 * Values:
bogdanm 82:6473597d706e 132 * - 0 - Time Counter mode.
bogdanm 82:6473597d706e 133 * - 1 - Pulse Counter mode.
bogdanm 82:6473597d706e 134 */
bogdanm 82:6473597d706e 135 //@{
bogdanm 82:6473597d706e 136 #define BP_LPTMR_CSR_TMS (1U) //!< Bit position for LPTMR_CSR_TMS.
bogdanm 82:6473597d706e 137 #define BM_LPTMR_CSR_TMS (0x00000002U) //!< Bit mask for LPTMR_CSR_TMS.
bogdanm 82:6473597d706e 138 #define BS_LPTMR_CSR_TMS (1U) //!< Bit field size in bits for LPTMR_CSR_TMS.
bogdanm 82:6473597d706e 139
bogdanm 82:6473597d706e 140 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 141 //! @brief Read current value of the LPTMR_CSR_TMS field.
bogdanm 82:6473597d706e 142 #define BR_LPTMR_CSR_TMS (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TMS))
bogdanm 82:6473597d706e 143 #endif
bogdanm 82:6473597d706e 144
bogdanm 82:6473597d706e 145 //! @brief Format value for bitfield LPTMR_CSR_TMS.
bogdanm 82:6473597d706e 146 #define BF_LPTMR_CSR_TMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TMS), uint32_t) & BM_LPTMR_CSR_TMS)
bogdanm 82:6473597d706e 147
bogdanm 82:6473597d706e 148 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 149 //! @brief Set the TMS field to a new value.
bogdanm 82:6473597d706e 150 #define BW_LPTMR_CSR_TMS(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TMS) = (v))
bogdanm 82:6473597d706e 151 #endif
bogdanm 82:6473597d706e 152 //@}
bogdanm 82:6473597d706e 153
bogdanm 82:6473597d706e 154 /*!
bogdanm 82:6473597d706e 155 * @name Register LPTMR_CSR, field TFC[2] (RW)
bogdanm 82:6473597d706e 156 *
bogdanm 82:6473597d706e 157 * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
bogdanm 82:6473597d706e 158 * TFC configures the CNR to reset on overflow. TFC must be altered only when the
bogdanm 82:6473597d706e 159 * LPTMR is disabled.
bogdanm 82:6473597d706e 160 *
bogdanm 82:6473597d706e 161 * Values:
bogdanm 82:6473597d706e 162 * - 0 - CNR is reset whenever TCF is set.
bogdanm 82:6473597d706e 163 * - 1 - CNR is reset on overflow.
bogdanm 82:6473597d706e 164 */
bogdanm 82:6473597d706e 165 //@{
bogdanm 82:6473597d706e 166 #define BP_LPTMR_CSR_TFC (2U) //!< Bit position for LPTMR_CSR_TFC.
bogdanm 82:6473597d706e 167 #define BM_LPTMR_CSR_TFC (0x00000004U) //!< Bit mask for LPTMR_CSR_TFC.
bogdanm 82:6473597d706e 168 #define BS_LPTMR_CSR_TFC (1U) //!< Bit field size in bits for LPTMR_CSR_TFC.
bogdanm 82:6473597d706e 169
bogdanm 82:6473597d706e 170 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 171 //! @brief Read current value of the LPTMR_CSR_TFC field.
bogdanm 82:6473597d706e 172 #define BR_LPTMR_CSR_TFC (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TFC))
bogdanm 82:6473597d706e 173 #endif
bogdanm 82:6473597d706e 174
bogdanm 82:6473597d706e 175 //! @brief Format value for bitfield LPTMR_CSR_TFC.
bogdanm 82:6473597d706e 176 #define BF_LPTMR_CSR_TFC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TFC), uint32_t) & BM_LPTMR_CSR_TFC)
bogdanm 82:6473597d706e 177
bogdanm 82:6473597d706e 178 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 179 //! @brief Set the TFC field to a new value.
bogdanm 82:6473597d706e 180 #define BW_LPTMR_CSR_TFC(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TFC) = (v))
bogdanm 82:6473597d706e 181 #endif
bogdanm 82:6473597d706e 182 //@}
bogdanm 82:6473597d706e 183
bogdanm 82:6473597d706e 184 /*!
bogdanm 82:6473597d706e 185 * @name Register LPTMR_CSR, field TPP[3] (RW)
bogdanm 82:6473597d706e 186 *
bogdanm 82:6473597d706e 187 * Configures the polarity of the input source in Pulse Counter mode. TPP must
bogdanm 82:6473597d706e 188 * be changed only when the LPTMR is disabled.
bogdanm 82:6473597d706e 189 *
bogdanm 82:6473597d706e 190 * Values:
bogdanm 82:6473597d706e 191 * - 0 - Pulse Counter input source is active-high, and the CNR will increment
bogdanm 82:6473597d706e 192 * on the rising-edge.
bogdanm 82:6473597d706e 193 * - 1 - Pulse Counter input source is active-low, and the CNR will increment on
bogdanm 82:6473597d706e 194 * the falling-edge.
bogdanm 82:6473597d706e 195 */
bogdanm 82:6473597d706e 196 //@{
bogdanm 82:6473597d706e 197 #define BP_LPTMR_CSR_TPP (3U) //!< Bit position for LPTMR_CSR_TPP.
bogdanm 82:6473597d706e 198 #define BM_LPTMR_CSR_TPP (0x00000008U) //!< Bit mask for LPTMR_CSR_TPP.
bogdanm 82:6473597d706e 199 #define BS_LPTMR_CSR_TPP (1U) //!< Bit field size in bits for LPTMR_CSR_TPP.
bogdanm 82:6473597d706e 200
bogdanm 82:6473597d706e 201 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 202 //! @brief Read current value of the LPTMR_CSR_TPP field.
bogdanm 82:6473597d706e 203 #define BR_LPTMR_CSR_TPP (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TPP))
bogdanm 82:6473597d706e 204 #endif
bogdanm 82:6473597d706e 205
bogdanm 82:6473597d706e 206 //! @brief Format value for bitfield LPTMR_CSR_TPP.
bogdanm 82:6473597d706e 207 #define BF_LPTMR_CSR_TPP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TPP), uint32_t) & BM_LPTMR_CSR_TPP)
bogdanm 82:6473597d706e 208
bogdanm 82:6473597d706e 209 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 210 //! @brief Set the TPP field to a new value.
bogdanm 82:6473597d706e 211 #define BW_LPTMR_CSR_TPP(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TPP) = (v))
bogdanm 82:6473597d706e 212 #endif
bogdanm 82:6473597d706e 213 //@}
bogdanm 82:6473597d706e 214
bogdanm 82:6473597d706e 215 /*!
bogdanm 82:6473597d706e 216 * @name Register LPTMR_CSR, field TPS[5:4] (RW)
bogdanm 82:6473597d706e 217 *
bogdanm 82:6473597d706e 218 * Configures the input source to be used in Pulse Counter mode. TPS must be
bogdanm 82:6473597d706e 219 * altered only when the LPTMR is disabled. The input connections vary by device.
bogdanm 82:6473597d706e 220 * See the chip configuration details for information on the connections to these
bogdanm 82:6473597d706e 221 * inputs.
bogdanm 82:6473597d706e 222 *
bogdanm 82:6473597d706e 223 * Values:
bogdanm 82:6473597d706e 224 * - 00 - Pulse counter input 0 is selected.
bogdanm 82:6473597d706e 225 * - 01 - Pulse counter input 1 is selected.
bogdanm 82:6473597d706e 226 * - 10 - Pulse counter input 2 is selected.
bogdanm 82:6473597d706e 227 * - 11 - Pulse counter input 3 is selected.
bogdanm 82:6473597d706e 228 */
bogdanm 82:6473597d706e 229 //@{
bogdanm 82:6473597d706e 230 #define BP_LPTMR_CSR_TPS (4U) //!< Bit position for LPTMR_CSR_TPS.
bogdanm 82:6473597d706e 231 #define BM_LPTMR_CSR_TPS (0x00000030U) //!< Bit mask for LPTMR_CSR_TPS.
bogdanm 82:6473597d706e 232 #define BS_LPTMR_CSR_TPS (2U) //!< Bit field size in bits for LPTMR_CSR_TPS.
bogdanm 82:6473597d706e 233
bogdanm 82:6473597d706e 234 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 235 //! @brief Read current value of the LPTMR_CSR_TPS field.
bogdanm 82:6473597d706e 236 #define BR_LPTMR_CSR_TPS (HW_LPTMR_CSR.B.TPS)
bogdanm 82:6473597d706e 237 #endif
bogdanm 82:6473597d706e 238
bogdanm 82:6473597d706e 239 //! @brief Format value for bitfield LPTMR_CSR_TPS.
bogdanm 82:6473597d706e 240 #define BF_LPTMR_CSR_TPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TPS), uint32_t) & BM_LPTMR_CSR_TPS)
bogdanm 82:6473597d706e 241
bogdanm 82:6473597d706e 242 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 243 //! @brief Set the TPS field to a new value.
bogdanm 82:6473597d706e 244 #define BW_LPTMR_CSR_TPS(v) (HW_LPTMR_CSR_WR((HW_LPTMR_CSR_RD() & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v)))
bogdanm 82:6473597d706e 245 #endif
bogdanm 82:6473597d706e 246 //@}
bogdanm 82:6473597d706e 247
bogdanm 82:6473597d706e 248 /*!
bogdanm 82:6473597d706e 249 * @name Register LPTMR_CSR, field TIE[6] (RW)
bogdanm 82:6473597d706e 250 *
bogdanm 82:6473597d706e 251 * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
bogdanm 82:6473597d706e 252 *
bogdanm 82:6473597d706e 253 * Values:
bogdanm 82:6473597d706e 254 * - 0 - Timer interrupt disabled.
bogdanm 82:6473597d706e 255 * - 1 - Timer interrupt enabled.
bogdanm 82:6473597d706e 256 */
bogdanm 82:6473597d706e 257 //@{
bogdanm 82:6473597d706e 258 #define BP_LPTMR_CSR_TIE (6U) //!< Bit position for LPTMR_CSR_TIE.
bogdanm 82:6473597d706e 259 #define BM_LPTMR_CSR_TIE (0x00000040U) //!< Bit mask for LPTMR_CSR_TIE.
bogdanm 82:6473597d706e 260 #define BS_LPTMR_CSR_TIE (1U) //!< Bit field size in bits for LPTMR_CSR_TIE.
bogdanm 82:6473597d706e 261
bogdanm 82:6473597d706e 262 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 263 //! @brief Read current value of the LPTMR_CSR_TIE field.
bogdanm 82:6473597d706e 264 #define BR_LPTMR_CSR_TIE (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TIE))
bogdanm 82:6473597d706e 265 #endif
bogdanm 82:6473597d706e 266
bogdanm 82:6473597d706e 267 //! @brief Format value for bitfield LPTMR_CSR_TIE.
bogdanm 82:6473597d706e 268 #define BF_LPTMR_CSR_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TIE), uint32_t) & BM_LPTMR_CSR_TIE)
bogdanm 82:6473597d706e 269
bogdanm 82:6473597d706e 270 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 271 //! @brief Set the TIE field to a new value.
bogdanm 82:6473597d706e 272 #define BW_LPTMR_CSR_TIE(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TIE) = (v))
bogdanm 82:6473597d706e 273 #endif
bogdanm 82:6473597d706e 274 //@}
bogdanm 82:6473597d706e 275
bogdanm 82:6473597d706e 276 /*!
bogdanm 82:6473597d706e 277 * @name Register LPTMR_CSR, field TCF[7] (W1C)
bogdanm 82:6473597d706e 278 *
bogdanm 82:6473597d706e 279 * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
bogdanm 82:6473597d706e 280 * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
bogdanm 82:6473597d706e 281 *
bogdanm 82:6473597d706e 282 * Values:
bogdanm 82:6473597d706e 283 * - 0 - The value of CNR is not equal to CMR and increments.
bogdanm 82:6473597d706e 284 * - 1 - The value of CNR is equal to CMR and increments.
bogdanm 82:6473597d706e 285 */
bogdanm 82:6473597d706e 286 //@{
bogdanm 82:6473597d706e 287 #define BP_LPTMR_CSR_TCF (7U) //!< Bit position for LPTMR_CSR_TCF.
bogdanm 82:6473597d706e 288 #define BM_LPTMR_CSR_TCF (0x00000080U) //!< Bit mask for LPTMR_CSR_TCF.
bogdanm 82:6473597d706e 289 #define BS_LPTMR_CSR_TCF (1U) //!< Bit field size in bits for LPTMR_CSR_TCF.
bogdanm 82:6473597d706e 290
bogdanm 82:6473597d706e 291 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 292 //! @brief Read current value of the LPTMR_CSR_TCF field.
bogdanm 82:6473597d706e 293 #define BR_LPTMR_CSR_TCF (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TCF))
bogdanm 82:6473597d706e 294 #endif
bogdanm 82:6473597d706e 295
bogdanm 82:6473597d706e 296 //! @brief Format value for bitfield LPTMR_CSR_TCF.
bogdanm 82:6473597d706e 297 #define BF_LPTMR_CSR_TCF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TCF), uint32_t) & BM_LPTMR_CSR_TCF)
bogdanm 82:6473597d706e 298
bogdanm 82:6473597d706e 299 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 300 //! @brief Set the TCF field to a new value.
bogdanm 82:6473597d706e 301 #define BW_LPTMR_CSR_TCF(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TCF) = (v))
bogdanm 82:6473597d706e 302 #endif
bogdanm 82:6473597d706e 303 //@}
bogdanm 82:6473597d706e 304
bogdanm 82:6473597d706e 305 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 306 // HW_LPTMR_PSR - Low Power Timer Prescale Register
bogdanm 82:6473597d706e 307 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 308
bogdanm 82:6473597d706e 309 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 310 /*!
bogdanm 82:6473597d706e 311 * @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW)
bogdanm 82:6473597d706e 312 *
bogdanm 82:6473597d706e 313 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 314 */
bogdanm 82:6473597d706e 315 typedef union _hw_lptmr_psr
bogdanm 82:6473597d706e 316 {
bogdanm 82:6473597d706e 317 uint32_t U;
bogdanm 82:6473597d706e 318 struct _hw_lptmr_psr_bitfields
bogdanm 82:6473597d706e 319 {
bogdanm 82:6473597d706e 320 uint32_t PCS : 2; //!< [1:0] Prescaler Clock Select
bogdanm 82:6473597d706e 321 uint32_t PBYP : 1; //!< [2] Prescaler Bypass
bogdanm 82:6473597d706e 322 uint32_t PRESCALE : 4; //!< [6:3] Prescale Value
bogdanm 82:6473597d706e 323 uint32_t RESERVED0 : 25; //!< [31:7]
bogdanm 82:6473597d706e 324 } B;
bogdanm 82:6473597d706e 325 } hw_lptmr_psr_t;
bogdanm 82:6473597d706e 326 #endif
bogdanm 82:6473597d706e 327
bogdanm 82:6473597d706e 328 /*!
bogdanm 82:6473597d706e 329 * @name Constants and macros for entire LPTMR_PSR register
bogdanm 82:6473597d706e 330 */
bogdanm 82:6473597d706e 331 //@{
bogdanm 82:6473597d706e 332 #define HW_LPTMR_PSR_ADDR (REGS_LPTMR_BASE + 0x4U)
bogdanm 82:6473597d706e 333
bogdanm 82:6473597d706e 334 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 335 #define HW_LPTMR_PSR (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR)
bogdanm 82:6473597d706e 336 #define HW_LPTMR_PSR_RD() (HW_LPTMR_PSR.U)
bogdanm 82:6473597d706e 337 #define HW_LPTMR_PSR_WR(v) (HW_LPTMR_PSR.U = (v))
bogdanm 82:6473597d706e 338 #define HW_LPTMR_PSR_SET(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() | (v)))
bogdanm 82:6473597d706e 339 #define HW_LPTMR_PSR_CLR(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() & ~(v)))
bogdanm 82:6473597d706e 340 #define HW_LPTMR_PSR_TOG(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() ^ (v)))
bogdanm 82:6473597d706e 341 #endif
bogdanm 82:6473597d706e 342 //@}
bogdanm 82:6473597d706e 343
bogdanm 82:6473597d706e 344 /*
bogdanm 82:6473597d706e 345 * Constants & macros for individual LPTMR_PSR bitfields
bogdanm 82:6473597d706e 346 */
bogdanm 82:6473597d706e 347
bogdanm 82:6473597d706e 348 /*!
bogdanm 82:6473597d706e 349 * @name Register LPTMR_PSR, field PCS[1:0] (RW)
bogdanm 82:6473597d706e 350 *
bogdanm 82:6473597d706e 351 * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
bogdanm 82:6473597d706e 352 * be altered only when the LPTMR is disabled. The clock connections vary by
bogdanm 82:6473597d706e 353 * device. See the chip configuration details for information on the connections to
bogdanm 82:6473597d706e 354 * these inputs.
bogdanm 82:6473597d706e 355 *
bogdanm 82:6473597d706e 356 * Values:
bogdanm 82:6473597d706e 357 * - 00 - Prescaler/glitch filter clock 0 selected.
bogdanm 82:6473597d706e 358 * - 01 - Prescaler/glitch filter clock 1 selected.
bogdanm 82:6473597d706e 359 * - 10 - Prescaler/glitch filter clock 2 selected.
bogdanm 82:6473597d706e 360 * - 11 - Prescaler/glitch filter clock 3 selected.
bogdanm 82:6473597d706e 361 */
bogdanm 82:6473597d706e 362 //@{
bogdanm 82:6473597d706e 363 #define BP_LPTMR_PSR_PCS (0U) //!< Bit position for LPTMR_PSR_PCS.
bogdanm 82:6473597d706e 364 #define BM_LPTMR_PSR_PCS (0x00000003U) //!< Bit mask for LPTMR_PSR_PCS.
bogdanm 82:6473597d706e 365 #define BS_LPTMR_PSR_PCS (2U) //!< Bit field size in bits for LPTMR_PSR_PCS.
bogdanm 82:6473597d706e 366
bogdanm 82:6473597d706e 367 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 368 //! @brief Read current value of the LPTMR_PSR_PCS field.
bogdanm 82:6473597d706e 369 #define BR_LPTMR_PSR_PCS (HW_LPTMR_PSR.B.PCS)
bogdanm 82:6473597d706e 370 #endif
bogdanm 82:6473597d706e 371
bogdanm 82:6473597d706e 372 //! @brief Format value for bitfield LPTMR_PSR_PCS.
bogdanm 82:6473597d706e 373 #define BF_LPTMR_PSR_PCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PCS), uint32_t) & BM_LPTMR_PSR_PCS)
bogdanm 82:6473597d706e 374
bogdanm 82:6473597d706e 375 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 376 //! @brief Set the PCS field to a new value.
bogdanm 82:6473597d706e 377 #define BW_LPTMR_PSR_PCS(v) (HW_LPTMR_PSR_WR((HW_LPTMR_PSR_RD() & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v)))
bogdanm 82:6473597d706e 378 #endif
bogdanm 82:6473597d706e 379 //@}
bogdanm 82:6473597d706e 380
bogdanm 82:6473597d706e 381 /*!
bogdanm 82:6473597d706e 382 * @name Register LPTMR_PSR, field PBYP[2] (RW)
bogdanm 82:6473597d706e 383 *
bogdanm 82:6473597d706e 384 * When PBYP is set, the selected prescaler clock in Time Counter mode or
bogdanm 82:6473597d706e 385 * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
bogdanm 82:6473597d706e 386 * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
bogdanm 82:6473597d706e 387 * must be altered only when the LPTMR is disabled.
bogdanm 82:6473597d706e 388 *
bogdanm 82:6473597d706e 389 * Values:
bogdanm 82:6473597d706e 390 * - 0 - Prescaler/glitch filter is enabled.
bogdanm 82:6473597d706e 391 * - 1 - Prescaler/glitch filter is bypassed.
bogdanm 82:6473597d706e 392 */
bogdanm 82:6473597d706e 393 //@{
bogdanm 82:6473597d706e 394 #define BP_LPTMR_PSR_PBYP (2U) //!< Bit position for LPTMR_PSR_PBYP.
bogdanm 82:6473597d706e 395 #define BM_LPTMR_PSR_PBYP (0x00000004U) //!< Bit mask for LPTMR_PSR_PBYP.
bogdanm 82:6473597d706e 396 #define BS_LPTMR_PSR_PBYP (1U) //!< Bit field size in bits for LPTMR_PSR_PBYP.
bogdanm 82:6473597d706e 397
bogdanm 82:6473597d706e 398 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 399 //! @brief Read current value of the LPTMR_PSR_PBYP field.
bogdanm 82:6473597d706e 400 #define BR_LPTMR_PSR_PBYP (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR, BP_LPTMR_PSR_PBYP))
bogdanm 82:6473597d706e 401 #endif
bogdanm 82:6473597d706e 402
bogdanm 82:6473597d706e 403 //! @brief Format value for bitfield LPTMR_PSR_PBYP.
bogdanm 82:6473597d706e 404 #define BF_LPTMR_PSR_PBYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PBYP), uint32_t) & BM_LPTMR_PSR_PBYP)
bogdanm 82:6473597d706e 405
bogdanm 82:6473597d706e 406 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 407 //! @brief Set the PBYP field to a new value.
bogdanm 82:6473597d706e 408 #define BW_LPTMR_PSR_PBYP(v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR, BP_LPTMR_PSR_PBYP) = (v))
bogdanm 82:6473597d706e 409 #endif
bogdanm 82:6473597d706e 410 //@}
bogdanm 82:6473597d706e 411
bogdanm 82:6473597d706e 412 /*!
bogdanm 82:6473597d706e 413 * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
bogdanm 82:6473597d706e 414 *
bogdanm 82:6473597d706e 415 * Configures the size of the Prescaler in Time Counter mode or width of the
bogdanm 82:6473597d706e 416 * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
bogdanm 82:6473597d706e 417 * is disabled.
bogdanm 82:6473597d706e 418 *
bogdanm 82:6473597d706e 419 * Values:
bogdanm 82:6473597d706e 420 * - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
bogdanm 82:6473597d706e 421 * support this configuration.
bogdanm 82:6473597d706e 422 * - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes
bogdanm 82:6473597d706e 423 * change on input pin after 2 rising clock edges.
bogdanm 82:6473597d706e 424 * - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes
bogdanm 82:6473597d706e 425 * change on input pin after 4 rising clock edges.
bogdanm 82:6473597d706e 426 * - 0011 - Prescaler divides the prescaler clock by 16; glitch filter
bogdanm 82:6473597d706e 427 * recognizes change on input pin after 8 rising clock edges.
bogdanm 82:6473597d706e 428 * - 0100 - Prescaler divides the prescaler clock by 32; glitch filter
bogdanm 82:6473597d706e 429 * recognizes change on input pin after 16 rising clock edges.
bogdanm 82:6473597d706e 430 * - 0101 - Prescaler divides the prescaler clock by 64; glitch filter
bogdanm 82:6473597d706e 431 * recognizes change on input pin after 32 rising clock edges.
bogdanm 82:6473597d706e 432 * - 0110 - Prescaler divides the prescaler clock by 128; glitch filter
bogdanm 82:6473597d706e 433 * recognizes change on input pin after 64 rising clock edges.
bogdanm 82:6473597d706e 434 * - 0111 - Prescaler divides the prescaler clock by 256; glitch filter
bogdanm 82:6473597d706e 435 * recognizes change on input pin after 128 rising clock edges.
bogdanm 82:6473597d706e 436 * - 1000 - Prescaler divides the prescaler clock by 512; glitch filter
bogdanm 82:6473597d706e 437 * recognizes change on input pin after 256 rising clock edges.
bogdanm 82:6473597d706e 438 * - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter
bogdanm 82:6473597d706e 439 * recognizes change on input pin after 512 rising clock edges.
bogdanm 82:6473597d706e 440 * - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter
bogdanm 82:6473597d706e 441 * recognizes change on input pin after 1024 rising clock edges.
bogdanm 82:6473597d706e 442 * - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter
bogdanm 82:6473597d706e 443 * recognizes change on input pin after 2048 rising clock edges.
bogdanm 82:6473597d706e 444 * - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter
bogdanm 82:6473597d706e 445 * recognizes change on input pin after 4096 rising clock edges.
bogdanm 82:6473597d706e 446 * - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
bogdanm 82:6473597d706e 447 * recognizes change on input pin after 8192 rising clock edges.
bogdanm 82:6473597d706e 448 * - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
bogdanm 82:6473597d706e 449 * recognizes change on input pin after 16,384 rising clock edges.
bogdanm 82:6473597d706e 450 * - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
bogdanm 82:6473597d706e 451 * recognizes change on input pin after 32,768 rising clock edges.
bogdanm 82:6473597d706e 452 */
bogdanm 82:6473597d706e 453 //@{
bogdanm 82:6473597d706e 454 #define BP_LPTMR_PSR_PRESCALE (3U) //!< Bit position for LPTMR_PSR_PRESCALE.
bogdanm 82:6473597d706e 455 #define BM_LPTMR_PSR_PRESCALE (0x00000078U) //!< Bit mask for LPTMR_PSR_PRESCALE.
bogdanm 82:6473597d706e 456 #define BS_LPTMR_PSR_PRESCALE (4U) //!< Bit field size in bits for LPTMR_PSR_PRESCALE.
bogdanm 82:6473597d706e 457
bogdanm 82:6473597d706e 458 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 459 //! @brief Read current value of the LPTMR_PSR_PRESCALE field.
bogdanm 82:6473597d706e 460 #define BR_LPTMR_PSR_PRESCALE (HW_LPTMR_PSR.B.PRESCALE)
bogdanm 82:6473597d706e 461 #endif
bogdanm 82:6473597d706e 462
bogdanm 82:6473597d706e 463 //! @brief Format value for bitfield LPTMR_PSR_PRESCALE.
bogdanm 82:6473597d706e 464 #define BF_LPTMR_PSR_PRESCALE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PRESCALE), uint32_t) & BM_LPTMR_PSR_PRESCALE)
bogdanm 82:6473597d706e 465
bogdanm 82:6473597d706e 466 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 467 //! @brief Set the PRESCALE field to a new value.
bogdanm 82:6473597d706e 468 #define BW_LPTMR_PSR_PRESCALE(v) (HW_LPTMR_PSR_WR((HW_LPTMR_PSR_RD() & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v)))
bogdanm 82:6473597d706e 469 #endif
bogdanm 82:6473597d706e 470 //@}
bogdanm 82:6473597d706e 471
bogdanm 82:6473597d706e 472 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 473 // HW_LPTMR_CMR - Low Power Timer Compare Register
bogdanm 82:6473597d706e 474 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 475
bogdanm 82:6473597d706e 476 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 477 /*!
bogdanm 82:6473597d706e 478 * @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW)
bogdanm 82:6473597d706e 479 *
bogdanm 82:6473597d706e 480 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 481 */
bogdanm 82:6473597d706e 482 typedef union _hw_lptmr_cmr
bogdanm 82:6473597d706e 483 {
bogdanm 82:6473597d706e 484 uint32_t U;
bogdanm 82:6473597d706e 485 struct _hw_lptmr_cmr_bitfields
bogdanm 82:6473597d706e 486 {
bogdanm 82:6473597d706e 487 uint32_t COMPARE : 16; //!< [15:0] Compare Value
bogdanm 82:6473597d706e 488 uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm 82:6473597d706e 489 } B;
bogdanm 82:6473597d706e 490 } hw_lptmr_cmr_t;
bogdanm 82:6473597d706e 491 #endif
bogdanm 82:6473597d706e 492
bogdanm 82:6473597d706e 493 /*!
bogdanm 82:6473597d706e 494 * @name Constants and macros for entire LPTMR_CMR register
bogdanm 82:6473597d706e 495 */
bogdanm 82:6473597d706e 496 //@{
bogdanm 82:6473597d706e 497 #define HW_LPTMR_CMR_ADDR (REGS_LPTMR_BASE + 0x8U)
bogdanm 82:6473597d706e 498
bogdanm 82:6473597d706e 499 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 500 #define HW_LPTMR_CMR (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR)
bogdanm 82:6473597d706e 501 #define HW_LPTMR_CMR_RD() (HW_LPTMR_CMR.U)
bogdanm 82:6473597d706e 502 #define HW_LPTMR_CMR_WR(v) (HW_LPTMR_CMR.U = (v))
bogdanm 82:6473597d706e 503 #define HW_LPTMR_CMR_SET(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() | (v)))
bogdanm 82:6473597d706e 504 #define HW_LPTMR_CMR_CLR(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() & ~(v)))
bogdanm 82:6473597d706e 505 #define HW_LPTMR_CMR_TOG(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() ^ (v)))
bogdanm 82:6473597d706e 506 #endif
bogdanm 82:6473597d706e 507 //@}
bogdanm 82:6473597d706e 508
bogdanm 82:6473597d706e 509 /*
bogdanm 82:6473597d706e 510 * Constants & macros for individual LPTMR_CMR bitfields
bogdanm 82:6473597d706e 511 */
bogdanm 82:6473597d706e 512
bogdanm 82:6473597d706e 513 /*!
bogdanm 82:6473597d706e 514 * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
bogdanm 82:6473597d706e 515 *
bogdanm 82:6473597d706e 516 * When the LPTMR is enabled and the CNR equals the value in the CMR and
bogdanm 82:6473597d706e 517 * increments, TCF is set and the hardware trigger asserts until the next time the CNR
bogdanm 82:6473597d706e 518 * increments. If the CMR is 0, the hardware trigger will remain asserted until
bogdanm 82:6473597d706e 519 * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
bogdanm 82:6473597d706e 520 * when TCF is set.
bogdanm 82:6473597d706e 521 */
bogdanm 82:6473597d706e 522 //@{
bogdanm 82:6473597d706e 523 #define BP_LPTMR_CMR_COMPARE (0U) //!< Bit position for LPTMR_CMR_COMPARE.
bogdanm 82:6473597d706e 524 #define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) //!< Bit mask for LPTMR_CMR_COMPARE.
bogdanm 82:6473597d706e 525 #define BS_LPTMR_CMR_COMPARE (16U) //!< Bit field size in bits for LPTMR_CMR_COMPARE.
bogdanm 82:6473597d706e 526
bogdanm 82:6473597d706e 527 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 528 //! @brief Read current value of the LPTMR_CMR_COMPARE field.
bogdanm 82:6473597d706e 529 #define BR_LPTMR_CMR_COMPARE (HW_LPTMR_CMR.B.COMPARE)
bogdanm 82:6473597d706e 530 #endif
bogdanm 82:6473597d706e 531
bogdanm 82:6473597d706e 532 //! @brief Format value for bitfield LPTMR_CMR_COMPARE.
bogdanm 82:6473597d706e 533 #define BF_LPTMR_CMR_COMPARE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CMR_COMPARE), uint32_t) & BM_LPTMR_CMR_COMPARE)
bogdanm 82:6473597d706e 534
bogdanm 82:6473597d706e 535 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 536 //! @brief Set the COMPARE field to a new value.
bogdanm 82:6473597d706e 537 #define BW_LPTMR_CMR_COMPARE(v) (HW_LPTMR_CMR_WR((HW_LPTMR_CMR_RD() & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v)))
bogdanm 82:6473597d706e 538 #endif
bogdanm 82:6473597d706e 539 //@}
bogdanm 82:6473597d706e 540
bogdanm 82:6473597d706e 541 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 542 // HW_LPTMR_CNR - Low Power Timer Counter Register
bogdanm 82:6473597d706e 543 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 544
bogdanm 82:6473597d706e 545 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 546 /*!
bogdanm 82:6473597d706e 547 * @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW)
bogdanm 82:6473597d706e 548 *
bogdanm 82:6473597d706e 549 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 550 */
bogdanm 82:6473597d706e 551 typedef union _hw_lptmr_cnr
bogdanm 82:6473597d706e 552 {
bogdanm 82:6473597d706e 553 uint32_t U;
bogdanm 82:6473597d706e 554 struct _hw_lptmr_cnr_bitfields
bogdanm 82:6473597d706e 555 {
bogdanm 82:6473597d706e 556 uint32_t COUNTER : 16; //!< [15:0] Counter Value
bogdanm 82:6473597d706e 557 uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm 82:6473597d706e 558 } B;
bogdanm 82:6473597d706e 559 } hw_lptmr_cnr_t;
bogdanm 82:6473597d706e 560 #endif
bogdanm 82:6473597d706e 561
bogdanm 82:6473597d706e 562 /*!
bogdanm 82:6473597d706e 563 * @name Constants and macros for entire LPTMR_CNR register
bogdanm 82:6473597d706e 564 */
bogdanm 82:6473597d706e 565 //@{
bogdanm 82:6473597d706e 566 #define HW_LPTMR_CNR_ADDR (REGS_LPTMR_BASE + 0xCU)
bogdanm 82:6473597d706e 567
bogdanm 82:6473597d706e 568 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 569 #define HW_LPTMR_CNR (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR)
bogdanm 82:6473597d706e 570 #define HW_LPTMR_CNR_RD() (HW_LPTMR_CNR.U)
bogdanm 82:6473597d706e 571 #define HW_LPTMR_CNR_WR(v) (HW_LPTMR_CNR.U = (v))
bogdanm 82:6473597d706e 572 #define HW_LPTMR_CNR_SET(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() | (v)))
bogdanm 82:6473597d706e 573 #define HW_LPTMR_CNR_CLR(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() & ~(v)))
bogdanm 82:6473597d706e 574 #define HW_LPTMR_CNR_TOG(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() ^ (v)))
bogdanm 82:6473597d706e 575 #endif
bogdanm 82:6473597d706e 576 //@}
bogdanm 82:6473597d706e 577
bogdanm 82:6473597d706e 578 /*
bogdanm 82:6473597d706e 579 * Constants & macros for individual LPTMR_CNR bitfields
bogdanm 82:6473597d706e 580 */
bogdanm 82:6473597d706e 581
bogdanm 82:6473597d706e 582 /*!
bogdanm 82:6473597d706e 583 * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
bogdanm 82:6473597d706e 584 */
bogdanm 82:6473597d706e 585 //@{
bogdanm 82:6473597d706e 586 #define BP_LPTMR_CNR_COUNTER (0U) //!< Bit position for LPTMR_CNR_COUNTER.
bogdanm 82:6473597d706e 587 #define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) //!< Bit mask for LPTMR_CNR_COUNTER.
bogdanm 82:6473597d706e 588 #define BS_LPTMR_CNR_COUNTER (16U) //!< Bit field size in bits for LPTMR_CNR_COUNTER.
bogdanm 82:6473597d706e 589
bogdanm 82:6473597d706e 590 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 591 //! @brief Read current value of the LPTMR_CNR_COUNTER field.
bogdanm 82:6473597d706e 592 #define BR_LPTMR_CNR_COUNTER (HW_LPTMR_CNR.B.COUNTER)
bogdanm 82:6473597d706e 593 #endif
bogdanm 82:6473597d706e 594
bogdanm 82:6473597d706e 595 //! @brief Format value for bitfield LPTMR_CNR_COUNTER.
bogdanm 82:6473597d706e 596 #define BF_LPTMR_CNR_COUNTER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CNR_COUNTER), uint32_t) & BM_LPTMR_CNR_COUNTER)
bogdanm 82:6473597d706e 597
bogdanm 82:6473597d706e 598 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 599 //! @brief Set the COUNTER field to a new value.
bogdanm 82:6473597d706e 600 #define BW_LPTMR_CNR_COUNTER(v) (HW_LPTMR_CNR_WR((HW_LPTMR_CNR_RD() & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v)))
bogdanm 82:6473597d706e 601 #endif
bogdanm 82:6473597d706e 602 //@}
bogdanm 82:6473597d706e 603
bogdanm 82:6473597d706e 604 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 605 // hw_lptmr_t - module struct
bogdanm 82:6473597d706e 606 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 607 /*!
bogdanm 82:6473597d706e 608 * @brief All LPTMR module registers.
bogdanm 82:6473597d706e 609 */
bogdanm 82:6473597d706e 610 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 611 #pragma pack(1)
bogdanm 82:6473597d706e 612 typedef struct _hw_lptmr
bogdanm 82:6473597d706e 613 {
bogdanm 82:6473597d706e 614 __IO hw_lptmr_csr_t CSR; //!< [0x0] Low Power Timer Control Status Register
bogdanm 82:6473597d706e 615 __IO hw_lptmr_psr_t PSR; //!< [0x4] Low Power Timer Prescale Register
bogdanm 82:6473597d706e 616 __IO hw_lptmr_cmr_t CMR; //!< [0x8] Low Power Timer Compare Register
bogdanm 82:6473597d706e 617 __IO hw_lptmr_cnr_t CNR; //!< [0xC] Low Power Timer Counter Register
bogdanm 82:6473597d706e 618 } hw_lptmr_t;
bogdanm 82:6473597d706e 619 #pragma pack()
bogdanm 82:6473597d706e 620
bogdanm 82:6473597d706e 621 //! @brief Macro to access all LPTMR registers.
bogdanm 82:6473597d706e 622 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 623 //! use the '&' operator, like <code>&HW_LPTMR</code>.
bogdanm 82:6473597d706e 624 #define HW_LPTMR (*(hw_lptmr_t *) REGS_LPTMR_BASE)
bogdanm 82:6473597d706e 625 #endif
bogdanm 82:6473597d706e 626
bogdanm 82:6473597d706e 627 #endif // __HW_LPTMR_REGISTERS_H__
bogdanm 82:6473597d706e 628 // v22/130726/0.9
bogdanm 82:6473597d706e 629 // EOF