mbed - mbed library

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mbed library

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_fmc.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_fmc.h@82:6473597d706e

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_FMC_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_FMC_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 FMC
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Flash Memory Controller
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_FMC_PFAPR - Flash Access Protection Register
bogdanm	82:6473597d706e	33	* - HW_FMC_PFB0CR - Flash Bank 0 Control Register
bogdanm	82:6473597d706e	34	* - HW_FMC_PFB1CR - Flash Bank 1 Control Register
bogdanm	82:6473597d706e	35	* - HW_FMC_TAGVDW0Sn - Cache Tag Storage
bogdanm	82:6473597d706e	36	* - HW_FMC_TAGVDW1Sn - Cache Tag Storage
bogdanm	82:6473597d706e	37	* - HW_FMC_TAGVDW2Sn - Cache Tag Storage
bogdanm	82:6473597d706e	38	* - HW_FMC_TAGVDW3Sn - Cache Tag Storage
bogdanm	82:6473597d706e	39	* - HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
bogdanm	82:6473597d706e	40	* - HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
bogdanm	82:6473597d706e	41	* - HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
bogdanm	82:6473597d706e	42	* - HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
bogdanm	82:6473597d706e	43	* - HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
bogdanm	82:6473597d706e	44	* - HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
bogdanm	82:6473597d706e	45	* - HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
bogdanm	82:6473597d706e	46	* - HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
bogdanm	82:6473597d706e	47	*
bogdanm	82:6473597d706e	48	* - hw_fmc_t - Struct containing all module registers.
bogdanm	82:6473597d706e	49	*/
bogdanm	82:6473597d706e	50
bogdanm	82:6473597d706e	51	//! @name Module base addresses
bogdanm	82:6473597d706e	52	//@{
bogdanm	82:6473597d706e	53	#ifndef REGS_FMC_BASE
bogdanm	82:6473597d706e	54	#define HW_FMC_INSTANCE_COUNT (1U) //!< Number of instances of the FMC module.
bogdanm	82:6473597d706e	55	#define REGS_FMC_BASE (0x4001F000U) //!< Base address for FMC.
bogdanm	82:6473597d706e	56	#endif
bogdanm	82:6473597d706e	57	//@}
bogdanm	82:6473597d706e	58
bogdanm	82:6473597d706e	59	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	60	// HW_FMC_PFAPR - Flash Access Protection Register
bogdanm	82:6473597d706e	61	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	62
bogdanm	82:6473597d706e	63	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	64	/*!
bogdanm	82:6473597d706e	65	* @brief HW_FMC_PFAPR - Flash Access Protection Register (RW)
bogdanm	82:6473597d706e	66	*
bogdanm	82:6473597d706e	67	* Reset value: 0x00F8003FU
bogdanm	82:6473597d706e	68	*/
bogdanm	82:6473597d706e	69	typedef union _hw_fmc_pfapr
bogdanm	82:6473597d706e	70	{
bogdanm	82:6473597d706e	71	uint32_t U;
bogdanm	82:6473597d706e	72	struct _hw_fmc_pfapr_bitfields
bogdanm	82:6473597d706e	73	{
bogdanm	82:6473597d706e	74	uint32_t M0AP : 2; //!< [1:0] Master 0 Access Protection
bogdanm	82:6473597d706e	75	uint32_t M1AP : 2; //!< [3:2] Master 1 Access Protection
bogdanm	82:6473597d706e	76	uint32_t M2AP : 2; //!< [5:4] Master 2 Access Protection
bogdanm	82:6473597d706e	77	uint32_t M3AP : 2; //!< [7:6] Master 3 Access Protection
bogdanm	82:6473597d706e	78	uint32_t M4AP : 2; //!< [9:8] Master 4 Access Protection
bogdanm	82:6473597d706e	79	uint32_t M5AP : 2; //!< [11:10] Master 5 Access Protection
bogdanm	82:6473597d706e	80	uint32_t M6AP : 2; //!< [13:12] Master 6 Access Protection
bogdanm	82:6473597d706e	81	uint32_t M7AP : 2; //!< [15:14] Master 7 Access Protection
bogdanm	82:6473597d706e	82	uint32_t M0PFD : 1; //!< [16] Master 0 Prefetch Disable
bogdanm	82:6473597d706e	83	uint32_t M1PFD : 1; //!< [17] Master 1 Prefetch Disable
bogdanm	82:6473597d706e	84	uint32_t M2PFD : 1; //!< [18] Master 2 Prefetch Disable
bogdanm	82:6473597d706e	85	uint32_t M3PFD : 1; //!< [19] Master 3 Prefetch Disable
bogdanm	82:6473597d706e	86	uint32_t M4PFD : 1; //!< [20] Master 4 Prefetch Disable
bogdanm	82:6473597d706e	87	uint32_t M5PFD : 1; //!< [21] Master 5 Prefetch Disable
bogdanm	82:6473597d706e	88	uint32_t M6PFD : 1; //!< [22] Master 6 Prefetch Disable
bogdanm	82:6473597d706e	89	uint32_t M7PFD : 1; //!< [23] Master 7 Prefetch Disable
bogdanm	82:6473597d706e	90	uint32_t RESERVED0 : 8; //!< [31:24]
bogdanm	82:6473597d706e	91	} B;
bogdanm	82:6473597d706e	92	} hw_fmc_pfapr_t;
bogdanm	82:6473597d706e	93	#endif
bogdanm	82:6473597d706e	94
bogdanm	82:6473597d706e	95	/*!
bogdanm	82:6473597d706e	96	* @name Constants and macros for entire FMC_PFAPR register
bogdanm	82:6473597d706e	97	*/
bogdanm	82:6473597d706e	98	//@{
bogdanm	82:6473597d706e	99	#define HW_FMC_PFAPR_ADDR (REGS_FMC_BASE + 0x0U)
bogdanm	82:6473597d706e	100
bogdanm	82:6473597d706e	101	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	102	#define HW_FMC_PFAPR ((__IO hw_fmc_pfapr_t ) HW_FMC_PFAPR_ADDR)
bogdanm	82:6473597d706e	103	#define HW_FMC_PFAPR_RD() (HW_FMC_PFAPR.U)
bogdanm	82:6473597d706e	104	#define HW_FMC_PFAPR_WR(v) (HW_FMC_PFAPR.U = (v))
bogdanm	82:6473597d706e	105	#define HW_FMC_PFAPR_SET(v) (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() \| (v)))
bogdanm	82:6473597d706e	106	#define HW_FMC_PFAPR_CLR(v) (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() & ~(v)))
bogdanm	82:6473597d706e	107	#define HW_FMC_PFAPR_TOG(v) (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() ^ (v)))
bogdanm	82:6473597d706e	108	#endif
bogdanm	82:6473597d706e	109	//@}
bogdanm	82:6473597d706e	110
bogdanm	82:6473597d706e	111	/*
bogdanm	82:6473597d706e	112	* Constants & macros for individual FMC_PFAPR bitfields
bogdanm	82:6473597d706e	113	*/
bogdanm	82:6473597d706e	114
bogdanm	82:6473597d706e	115	/*!
bogdanm	82:6473597d706e	116	* @name Register FMC_PFAPR, field M0AP[1:0] (RW)
bogdanm	82:6473597d706e	117	*
bogdanm	82:6473597d706e	118	* This field controls whether read and write access to the flash are allowed
bogdanm	82:6473597d706e	119	* based on the logical master number of the requesting crossbar switch master.
bogdanm	82:6473597d706e	120	*
bogdanm	82:6473597d706e	121	* Values:
bogdanm	82:6473597d706e	122	* - 00 - No access may be performed by this master
bogdanm	82:6473597d706e	123	* - 01 - Only read accesses may be performed by this master
bogdanm	82:6473597d706e	124	* - 10 - Only write accesses may be performed by this master
bogdanm	82:6473597d706e	125	* - 11 - Both read and write accesses may be performed by this master
bogdanm	82:6473597d706e	126	*/
bogdanm	82:6473597d706e	127	//@{
bogdanm	82:6473597d706e	128	#define BP_FMC_PFAPR_M0AP (0U) //!< Bit position for FMC_PFAPR_M0AP.
bogdanm	82:6473597d706e	129	#define BM_FMC_PFAPR_M0AP (0x00000003U) //!< Bit mask for FMC_PFAPR_M0AP.
bogdanm	82:6473597d706e	130	#define BS_FMC_PFAPR_M0AP (2U) //!< Bit field size in bits for FMC_PFAPR_M0AP.
bogdanm	82:6473597d706e	131
bogdanm	82:6473597d706e	132	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	133	//! @brief Read current value of the FMC_PFAPR_M0AP field.
bogdanm	82:6473597d706e	134	#define BR_FMC_PFAPR_M0AP (HW_FMC_PFAPR.B.M0AP)
bogdanm	82:6473597d706e	135	#endif
bogdanm	82:6473597d706e	136
bogdanm	82:6473597d706e	137	//! @brief Format value for bitfield FMC_PFAPR_M0AP.
bogdanm	82:6473597d706e	138	#define BF_FMC_PFAPR_M0AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M0AP), uint32_t) & BM_FMC_PFAPR_M0AP)
bogdanm	82:6473597d706e	139
bogdanm	82:6473597d706e	140	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	141	//! @brief Set the M0AP field to a new value.
bogdanm	82:6473597d706e	142	#define BW_FMC_PFAPR_M0AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M0AP) \| BF_FMC_PFAPR_M0AP(v)))
bogdanm	82:6473597d706e	143	#endif
bogdanm	82:6473597d706e	144	//@}
bogdanm	82:6473597d706e	145
bogdanm	82:6473597d706e	146	/*!
bogdanm	82:6473597d706e	147	* @name Register FMC_PFAPR, field M1AP[3:2] (RW)
bogdanm	82:6473597d706e	148	*
bogdanm	82:6473597d706e	149	* This field controls whether read and write access to the flash are allowed
bogdanm	82:6473597d706e	150	* based on the logical master number of the requesting crossbar switch master.
bogdanm	82:6473597d706e	151	*
bogdanm	82:6473597d706e	152	* Values:
bogdanm	82:6473597d706e	153	* - 00 - No access may be performed by this master
bogdanm	82:6473597d706e	154	* - 01 - Only read accesses may be performed by this master
bogdanm	82:6473597d706e	155	* - 10 - Only write accesses may be performed by this master
bogdanm	82:6473597d706e	156	* - 11 - Both read and write accesses may be performed by this master
bogdanm	82:6473597d706e	157	*/
bogdanm	82:6473597d706e	158	//@{
bogdanm	82:6473597d706e	159	#define BP_FMC_PFAPR_M1AP (2U) //!< Bit position for FMC_PFAPR_M1AP.
bogdanm	82:6473597d706e	160	#define BM_FMC_PFAPR_M1AP (0x0000000CU) //!< Bit mask for FMC_PFAPR_M1AP.
bogdanm	82:6473597d706e	161	#define BS_FMC_PFAPR_M1AP (2U) //!< Bit field size in bits for FMC_PFAPR_M1AP.
bogdanm	82:6473597d706e	162
bogdanm	82:6473597d706e	163	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	164	//! @brief Read current value of the FMC_PFAPR_M1AP field.
bogdanm	82:6473597d706e	165	#define BR_FMC_PFAPR_M1AP (HW_FMC_PFAPR.B.M1AP)
bogdanm	82:6473597d706e	166	#endif
bogdanm	82:6473597d706e	167
bogdanm	82:6473597d706e	168	//! @brief Format value for bitfield FMC_PFAPR_M1AP.
bogdanm	82:6473597d706e	169	#define BF_FMC_PFAPR_M1AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M1AP), uint32_t) & BM_FMC_PFAPR_M1AP)
bogdanm	82:6473597d706e	170
bogdanm	82:6473597d706e	171	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	172	//! @brief Set the M1AP field to a new value.
bogdanm	82:6473597d706e	173	#define BW_FMC_PFAPR_M1AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M1AP) \| BF_FMC_PFAPR_M1AP(v)))
bogdanm	82:6473597d706e	174	#endif
bogdanm	82:6473597d706e	175	//@}
bogdanm	82:6473597d706e	176
bogdanm	82:6473597d706e	177	/*!
bogdanm	82:6473597d706e	178	* @name Register FMC_PFAPR, field M2AP[5:4] (RW)
bogdanm	82:6473597d706e	179	*
bogdanm	82:6473597d706e	180	* This field controls whether read and write access to the flash are allowed
bogdanm	82:6473597d706e	181	* based on the logical master number of the requesting crossbar switch master.
bogdanm	82:6473597d706e	182	*
bogdanm	82:6473597d706e	183	* Values:
bogdanm	82:6473597d706e	184	* - 00 - No access may be performed by this master
bogdanm	82:6473597d706e	185	* - 01 - Only read accesses may be performed by this master
bogdanm	82:6473597d706e	186	* - 10 - Only write accesses may be performed by this master
bogdanm	82:6473597d706e	187	* - 11 - Both read and write accesses may be performed by this master
bogdanm	82:6473597d706e	188	*/
bogdanm	82:6473597d706e	189	//@{
bogdanm	82:6473597d706e	190	#define BP_FMC_PFAPR_M2AP (4U) //!< Bit position for FMC_PFAPR_M2AP.
bogdanm	82:6473597d706e	191	#define BM_FMC_PFAPR_M2AP (0x00000030U) //!< Bit mask for FMC_PFAPR_M2AP.
bogdanm	82:6473597d706e	192	#define BS_FMC_PFAPR_M2AP (2U) //!< Bit field size in bits for FMC_PFAPR_M2AP.
bogdanm	82:6473597d706e	193
bogdanm	82:6473597d706e	194	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	195	//! @brief Read current value of the FMC_PFAPR_M2AP field.
bogdanm	82:6473597d706e	196	#define BR_FMC_PFAPR_M2AP (HW_FMC_PFAPR.B.M2AP)
bogdanm	82:6473597d706e	197	#endif
bogdanm	82:6473597d706e	198
bogdanm	82:6473597d706e	199	//! @brief Format value for bitfield FMC_PFAPR_M2AP.
bogdanm	82:6473597d706e	200	#define BF_FMC_PFAPR_M2AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M2AP), uint32_t) & BM_FMC_PFAPR_M2AP)
bogdanm	82:6473597d706e	201
bogdanm	82:6473597d706e	202	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	203	//! @brief Set the M2AP field to a new value.
bogdanm	82:6473597d706e	204	#define BW_FMC_PFAPR_M2AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M2AP) \| BF_FMC_PFAPR_M2AP(v)))
bogdanm	82:6473597d706e	205	#endif
bogdanm	82:6473597d706e	206	//@}
bogdanm	82:6473597d706e	207
bogdanm	82:6473597d706e	208	/*!
bogdanm	82:6473597d706e	209	* @name Register FMC_PFAPR, field M3AP[7:6] (RW)
bogdanm	82:6473597d706e	210	*
bogdanm	82:6473597d706e	211	* This field controls whether read and write access to the flash are allowed
bogdanm	82:6473597d706e	212	* based on the logical master number of the requesting crossbar switch master.
bogdanm	82:6473597d706e	213	*
bogdanm	82:6473597d706e	214	* Values:
bogdanm	82:6473597d706e	215	* - 00 - No access may be performed by this master
bogdanm	82:6473597d706e	216	* - 01 - Only read accesses may be performed by this master
bogdanm	82:6473597d706e	217	* - 10 - Only write accesses may be performed by this master
bogdanm	82:6473597d706e	218	* - 11 - Both read and write accesses may be performed by this master
bogdanm	82:6473597d706e	219	*/
bogdanm	82:6473597d706e	220	//@{
bogdanm	82:6473597d706e	221	#define BP_FMC_PFAPR_M3AP (6U) //!< Bit position for FMC_PFAPR_M3AP.
bogdanm	82:6473597d706e	222	#define BM_FMC_PFAPR_M3AP (0x000000C0U) //!< Bit mask for FMC_PFAPR_M3AP.
bogdanm	82:6473597d706e	223	#define BS_FMC_PFAPR_M3AP (2U) //!< Bit field size in bits for FMC_PFAPR_M3AP.
bogdanm	82:6473597d706e	224
bogdanm	82:6473597d706e	225	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	226	//! @brief Read current value of the FMC_PFAPR_M3AP field.
bogdanm	82:6473597d706e	227	#define BR_FMC_PFAPR_M3AP (HW_FMC_PFAPR.B.M3AP)
bogdanm	82:6473597d706e	228	#endif
bogdanm	82:6473597d706e	229
bogdanm	82:6473597d706e	230	//! @brief Format value for bitfield FMC_PFAPR_M3AP.
bogdanm	82:6473597d706e	231	#define BF_FMC_PFAPR_M3AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M3AP), uint32_t) & BM_FMC_PFAPR_M3AP)
bogdanm	82:6473597d706e	232
bogdanm	82:6473597d706e	233	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	234	//! @brief Set the M3AP field to a new value.
bogdanm	82:6473597d706e	235	#define BW_FMC_PFAPR_M3AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M3AP) \| BF_FMC_PFAPR_M3AP(v)))
bogdanm	82:6473597d706e	236	#endif
bogdanm	82:6473597d706e	237	//@}
bogdanm	82:6473597d706e	238
bogdanm	82:6473597d706e	239	/*!
bogdanm	82:6473597d706e	240	* @name Register FMC_PFAPR, field M4AP[9:8] (RW)
bogdanm	82:6473597d706e	241	*
bogdanm	82:6473597d706e	242	* This field controls whether read and write access to the flash are allowed
bogdanm	82:6473597d706e	243	* based on the logical master number of the requesting crossbar switch master.
bogdanm	82:6473597d706e	244	*
bogdanm	82:6473597d706e	245	* Values:
bogdanm	82:6473597d706e	246	* - 00 - No access may be performed by this master
bogdanm	82:6473597d706e	247	* - 01 - Only read accesses may be performed by this master
bogdanm	82:6473597d706e	248	* - 10 - Only write accesses may be performed by this master
bogdanm	82:6473597d706e	249	* - 11 - Both read and write accesses may be performed by this master
bogdanm	82:6473597d706e	250	*/
bogdanm	82:6473597d706e	251	//@{
bogdanm	82:6473597d706e	252	#define BP_FMC_PFAPR_M4AP (8U) //!< Bit position for FMC_PFAPR_M4AP.
bogdanm	82:6473597d706e	253	#define BM_FMC_PFAPR_M4AP (0x00000300U) //!< Bit mask for FMC_PFAPR_M4AP.
bogdanm	82:6473597d706e	254	#define BS_FMC_PFAPR_M4AP (2U) //!< Bit field size in bits for FMC_PFAPR_M4AP.
bogdanm	82:6473597d706e	255
bogdanm	82:6473597d706e	256	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	257	//! @brief Read current value of the FMC_PFAPR_M4AP field.
bogdanm	82:6473597d706e	258	#define BR_FMC_PFAPR_M4AP (HW_FMC_PFAPR.B.M4AP)
bogdanm	82:6473597d706e	259	#endif
bogdanm	82:6473597d706e	260
bogdanm	82:6473597d706e	261	//! @brief Format value for bitfield FMC_PFAPR_M4AP.
bogdanm	82:6473597d706e	262	#define BF_FMC_PFAPR_M4AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M4AP), uint32_t) & BM_FMC_PFAPR_M4AP)
bogdanm	82:6473597d706e	263
bogdanm	82:6473597d706e	264	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	265	//! @brief Set the M4AP field to a new value.
bogdanm	82:6473597d706e	266	#define BW_FMC_PFAPR_M4AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M4AP) \| BF_FMC_PFAPR_M4AP(v)))
bogdanm	82:6473597d706e	267	#endif
bogdanm	82:6473597d706e	268	//@}
bogdanm	82:6473597d706e	269
bogdanm	82:6473597d706e	270	/*!
bogdanm	82:6473597d706e	271	* @name Register FMC_PFAPR, field M5AP[11:10] (RW)
bogdanm	82:6473597d706e	272	*
bogdanm	82:6473597d706e	273	* This field controls whether read and write access to the flash are allowed
bogdanm	82:6473597d706e	274	* based on the logical master number of the requesting crossbar switch master.
bogdanm	82:6473597d706e	275	*
bogdanm	82:6473597d706e	276	* Values:
bogdanm	82:6473597d706e	277	* - 00 - No access may be performed by this master
bogdanm	82:6473597d706e	278	* - 01 - Only read accesses may be performed by this master
bogdanm	82:6473597d706e	279	* - 10 - Only write accesses may be performed by this master
bogdanm	82:6473597d706e	280	* - 11 - Both read and write accesses may be performed by this master
bogdanm	82:6473597d706e	281	*/
bogdanm	82:6473597d706e	282	//@{
bogdanm	82:6473597d706e	283	#define BP_FMC_PFAPR_M5AP (10U) //!< Bit position for FMC_PFAPR_M5AP.
bogdanm	82:6473597d706e	284	#define BM_FMC_PFAPR_M5AP (0x00000C00U) //!< Bit mask for FMC_PFAPR_M5AP.
bogdanm	82:6473597d706e	285	#define BS_FMC_PFAPR_M5AP (2U) //!< Bit field size in bits for FMC_PFAPR_M5AP.
bogdanm	82:6473597d706e	286
bogdanm	82:6473597d706e	287	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	288	//! @brief Read current value of the FMC_PFAPR_M5AP field.
bogdanm	82:6473597d706e	289	#define BR_FMC_PFAPR_M5AP (HW_FMC_PFAPR.B.M5AP)
bogdanm	82:6473597d706e	290	#endif
bogdanm	82:6473597d706e	291
bogdanm	82:6473597d706e	292	//! @brief Format value for bitfield FMC_PFAPR_M5AP.
bogdanm	82:6473597d706e	293	#define BF_FMC_PFAPR_M5AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M5AP), uint32_t) & BM_FMC_PFAPR_M5AP)
bogdanm	82:6473597d706e	294
bogdanm	82:6473597d706e	295	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	296	//! @brief Set the M5AP field to a new value.
bogdanm	82:6473597d706e	297	#define BW_FMC_PFAPR_M5AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M5AP) \| BF_FMC_PFAPR_M5AP(v)))
bogdanm	82:6473597d706e	298	#endif
bogdanm	82:6473597d706e	299	//@}
bogdanm	82:6473597d706e	300
bogdanm	82:6473597d706e	301	/*!
bogdanm	82:6473597d706e	302	* @name Register FMC_PFAPR, field M6AP[13:12] (RW)
bogdanm	82:6473597d706e	303	*
bogdanm	82:6473597d706e	304	* This field controls whether read and write access to the flash are allowed
bogdanm	82:6473597d706e	305	* based on the logical master number of the requesting crossbar switch master.
bogdanm	82:6473597d706e	306	*
bogdanm	82:6473597d706e	307	* Values:
bogdanm	82:6473597d706e	308	* - 00 - No access may be performed by this master
bogdanm	82:6473597d706e	309	* - 01 - Only read accesses may be performed by this master
bogdanm	82:6473597d706e	310	* - 10 - Only write accesses may be performed by this master
bogdanm	82:6473597d706e	311	* - 11 - Both read and write accesses may be performed by this master
bogdanm	82:6473597d706e	312	*/
bogdanm	82:6473597d706e	313	//@{
bogdanm	82:6473597d706e	314	#define BP_FMC_PFAPR_M6AP (12U) //!< Bit position for FMC_PFAPR_M6AP.
bogdanm	82:6473597d706e	315	#define BM_FMC_PFAPR_M6AP (0x00003000U) //!< Bit mask for FMC_PFAPR_M6AP.
bogdanm	82:6473597d706e	316	#define BS_FMC_PFAPR_M6AP (2U) //!< Bit field size in bits for FMC_PFAPR_M6AP.
bogdanm	82:6473597d706e	317
bogdanm	82:6473597d706e	318	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	319	//! @brief Read current value of the FMC_PFAPR_M6AP field.
bogdanm	82:6473597d706e	320	#define BR_FMC_PFAPR_M6AP (HW_FMC_PFAPR.B.M6AP)
bogdanm	82:6473597d706e	321	#endif
bogdanm	82:6473597d706e	322
bogdanm	82:6473597d706e	323	//! @brief Format value for bitfield FMC_PFAPR_M6AP.
bogdanm	82:6473597d706e	324	#define BF_FMC_PFAPR_M6AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M6AP), uint32_t) & BM_FMC_PFAPR_M6AP)
bogdanm	82:6473597d706e	325
bogdanm	82:6473597d706e	326	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	327	//! @brief Set the M6AP field to a new value.
bogdanm	82:6473597d706e	328	#define BW_FMC_PFAPR_M6AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M6AP) \| BF_FMC_PFAPR_M6AP(v)))
bogdanm	82:6473597d706e	329	#endif
bogdanm	82:6473597d706e	330	//@}
bogdanm	82:6473597d706e	331
bogdanm	82:6473597d706e	332	/*!
bogdanm	82:6473597d706e	333	* @name Register FMC_PFAPR, field M7AP[15:14] (RW)
bogdanm	82:6473597d706e	334	*
bogdanm	82:6473597d706e	335	* This field controls whether read and write access to the flash are allowed
bogdanm	82:6473597d706e	336	* based on the logical master number of the requesting crossbar switch master.
bogdanm	82:6473597d706e	337	*
bogdanm	82:6473597d706e	338	* Values:
bogdanm	82:6473597d706e	339	* - 00 - No access may be performed by this master.
bogdanm	82:6473597d706e	340	* - 01 - Only read accesses may be performed by this master.
bogdanm	82:6473597d706e	341	* - 10 - Only write accesses may be performed by this master.
bogdanm	82:6473597d706e	342	* - 11 - Both read and write accesses may be performed by this master.
bogdanm	82:6473597d706e	343	*/
bogdanm	82:6473597d706e	344	//@{
bogdanm	82:6473597d706e	345	#define BP_FMC_PFAPR_M7AP (14U) //!< Bit position for FMC_PFAPR_M7AP.
bogdanm	82:6473597d706e	346	#define BM_FMC_PFAPR_M7AP (0x0000C000U) //!< Bit mask for FMC_PFAPR_M7AP.
bogdanm	82:6473597d706e	347	#define BS_FMC_PFAPR_M7AP (2U) //!< Bit field size in bits for FMC_PFAPR_M7AP.
bogdanm	82:6473597d706e	348
bogdanm	82:6473597d706e	349	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	350	//! @brief Read current value of the FMC_PFAPR_M7AP field.
bogdanm	82:6473597d706e	351	#define BR_FMC_PFAPR_M7AP (HW_FMC_PFAPR.B.M7AP)
bogdanm	82:6473597d706e	352	#endif
bogdanm	82:6473597d706e	353
bogdanm	82:6473597d706e	354	//! @brief Format value for bitfield FMC_PFAPR_M7AP.
bogdanm	82:6473597d706e	355	#define BF_FMC_PFAPR_M7AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M7AP), uint32_t) & BM_FMC_PFAPR_M7AP)
bogdanm	82:6473597d706e	356
bogdanm	82:6473597d706e	357	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	358	//! @brief Set the M7AP field to a new value.
bogdanm	82:6473597d706e	359	#define BW_FMC_PFAPR_M7AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M7AP) \| BF_FMC_PFAPR_M7AP(v)))
bogdanm	82:6473597d706e	360	#endif
bogdanm	82:6473597d706e	361	//@}
bogdanm	82:6473597d706e	362
bogdanm	82:6473597d706e	363	/*!
bogdanm	82:6473597d706e	364	* @name Register FMC_PFAPR, field M0PFD[16] (RW)
bogdanm	82:6473597d706e	365	*
bogdanm	82:6473597d706e	366	* These bits control whether prefetching is enabled based on the logical number
bogdanm	82:6473597d706e	367	* of the requesting crossbar switch master. This field is further qualified by
bogdanm	82:6473597d706e	368	* the PFBnCR[BxDPE,BxIPE] bits.
bogdanm	82:6473597d706e	369	*
bogdanm	82:6473597d706e	370	* Values:
bogdanm	82:6473597d706e	371	* - 0 - Prefetching for this master is enabled.
bogdanm	82:6473597d706e	372	* - 1 - Prefetching for this master is disabled.
bogdanm	82:6473597d706e	373	*/
bogdanm	82:6473597d706e	374	//@{
bogdanm	82:6473597d706e	375	#define BP_FMC_PFAPR_M0PFD (16U) //!< Bit position for FMC_PFAPR_M0PFD.
bogdanm	82:6473597d706e	376	#define BM_FMC_PFAPR_M0PFD (0x00010000U) //!< Bit mask for FMC_PFAPR_M0PFD.
bogdanm	82:6473597d706e	377	#define BS_FMC_PFAPR_M0PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M0PFD.
bogdanm	82:6473597d706e	378
bogdanm	82:6473597d706e	379	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	380	//! @brief Read current value of the FMC_PFAPR_M0PFD field.
bogdanm	82:6473597d706e	381	#define BR_FMC_PFAPR_M0PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M0PFD))
bogdanm	82:6473597d706e	382	#endif
bogdanm	82:6473597d706e	383
bogdanm	82:6473597d706e	384	//! @brief Format value for bitfield FMC_PFAPR_M0PFD.
bogdanm	82:6473597d706e	385	#define BF_FMC_PFAPR_M0PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M0PFD), uint32_t) & BM_FMC_PFAPR_M0PFD)
bogdanm	82:6473597d706e	386
bogdanm	82:6473597d706e	387	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	388	//! @brief Set the M0PFD field to a new value.
bogdanm	82:6473597d706e	389	#define BW_FMC_PFAPR_M0PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M0PFD) = (v))
bogdanm	82:6473597d706e	390	#endif
bogdanm	82:6473597d706e	391	//@}
bogdanm	82:6473597d706e	392
bogdanm	82:6473597d706e	393	/*!
bogdanm	82:6473597d706e	394	* @name Register FMC_PFAPR, field M1PFD[17] (RW)
bogdanm	82:6473597d706e	395	*
bogdanm	82:6473597d706e	396	* These bits control whether prefetching is enabled based on the logical number
bogdanm	82:6473597d706e	397	* of the requesting crossbar switch master. This field is further qualified by
bogdanm	82:6473597d706e	398	* the PFBnCR[BxDPE,BxIPE] bits.
bogdanm	82:6473597d706e	399	*
bogdanm	82:6473597d706e	400	* Values:
bogdanm	82:6473597d706e	401	* - 0 - Prefetching for this master is enabled.
bogdanm	82:6473597d706e	402	* - 1 - Prefetching for this master is disabled.
bogdanm	82:6473597d706e	403	*/
bogdanm	82:6473597d706e	404	//@{
bogdanm	82:6473597d706e	405	#define BP_FMC_PFAPR_M1PFD (17U) //!< Bit position for FMC_PFAPR_M1PFD.
bogdanm	82:6473597d706e	406	#define BM_FMC_PFAPR_M1PFD (0x00020000U) //!< Bit mask for FMC_PFAPR_M1PFD.
bogdanm	82:6473597d706e	407	#define BS_FMC_PFAPR_M1PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M1PFD.
bogdanm	82:6473597d706e	408
bogdanm	82:6473597d706e	409	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	410	//! @brief Read current value of the FMC_PFAPR_M1PFD field.
bogdanm	82:6473597d706e	411	#define BR_FMC_PFAPR_M1PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M1PFD))
bogdanm	82:6473597d706e	412	#endif
bogdanm	82:6473597d706e	413
bogdanm	82:6473597d706e	414	//! @brief Format value for bitfield FMC_PFAPR_M1PFD.
bogdanm	82:6473597d706e	415	#define BF_FMC_PFAPR_M1PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M1PFD), uint32_t) & BM_FMC_PFAPR_M1PFD)
bogdanm	82:6473597d706e	416
bogdanm	82:6473597d706e	417	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	418	//! @brief Set the M1PFD field to a new value.
bogdanm	82:6473597d706e	419	#define BW_FMC_PFAPR_M1PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M1PFD) = (v))
bogdanm	82:6473597d706e	420	#endif
bogdanm	82:6473597d706e	421	//@}
bogdanm	82:6473597d706e	422
bogdanm	82:6473597d706e	423	/*!
bogdanm	82:6473597d706e	424	* @name Register FMC_PFAPR, field M2PFD[18] (RW)
bogdanm	82:6473597d706e	425	*
bogdanm	82:6473597d706e	426	* These bits control whether prefetching is enabled based on the logical number
bogdanm	82:6473597d706e	427	* of the requesting crossbar switch master. This field is further qualified by
bogdanm	82:6473597d706e	428	* the PFBnCR[BxDPE,BxIPE] bits.
bogdanm	82:6473597d706e	429	*
bogdanm	82:6473597d706e	430	* Values:
bogdanm	82:6473597d706e	431	* - 0 - Prefetching for this master is enabled.
bogdanm	82:6473597d706e	432	* - 1 - Prefetching for this master is disabled.
bogdanm	82:6473597d706e	433	*/
bogdanm	82:6473597d706e	434	//@{
bogdanm	82:6473597d706e	435	#define BP_FMC_PFAPR_M2PFD (18U) //!< Bit position for FMC_PFAPR_M2PFD.
bogdanm	82:6473597d706e	436	#define BM_FMC_PFAPR_M2PFD (0x00040000U) //!< Bit mask for FMC_PFAPR_M2PFD.
bogdanm	82:6473597d706e	437	#define BS_FMC_PFAPR_M2PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M2PFD.
bogdanm	82:6473597d706e	438
bogdanm	82:6473597d706e	439	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	440	//! @brief Read current value of the FMC_PFAPR_M2PFD field.
bogdanm	82:6473597d706e	441	#define BR_FMC_PFAPR_M2PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M2PFD))
bogdanm	82:6473597d706e	442	#endif
bogdanm	82:6473597d706e	443
bogdanm	82:6473597d706e	444	//! @brief Format value for bitfield FMC_PFAPR_M2PFD.
bogdanm	82:6473597d706e	445	#define BF_FMC_PFAPR_M2PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M2PFD), uint32_t) & BM_FMC_PFAPR_M2PFD)
bogdanm	82:6473597d706e	446
bogdanm	82:6473597d706e	447	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	448	//! @brief Set the M2PFD field to a new value.
bogdanm	82:6473597d706e	449	#define BW_FMC_PFAPR_M2PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M2PFD) = (v))
bogdanm	82:6473597d706e	450	#endif
bogdanm	82:6473597d706e	451	//@}
bogdanm	82:6473597d706e	452
bogdanm	82:6473597d706e	453	/*!
bogdanm	82:6473597d706e	454	* @name Register FMC_PFAPR, field M3PFD[19] (RW)
bogdanm	82:6473597d706e	455	*
bogdanm	82:6473597d706e	456	* These bits control whether prefetching is enabled based on the logical number
bogdanm	82:6473597d706e	457	* of the requesting crossbar switch master. This field is further qualified by
bogdanm	82:6473597d706e	458	* the PFBnCR[BxDPE,BxIPE] bits.
bogdanm	82:6473597d706e	459	*
bogdanm	82:6473597d706e	460	* Values:
bogdanm	82:6473597d706e	461	* - 0 - Prefetching for this master is enabled.
bogdanm	82:6473597d706e	462	* - 1 - Prefetching for this master is disabled.
bogdanm	82:6473597d706e	463	*/
bogdanm	82:6473597d706e	464	//@{
bogdanm	82:6473597d706e	465	#define BP_FMC_PFAPR_M3PFD (19U) //!< Bit position for FMC_PFAPR_M3PFD.
bogdanm	82:6473597d706e	466	#define BM_FMC_PFAPR_M3PFD (0x00080000U) //!< Bit mask for FMC_PFAPR_M3PFD.
bogdanm	82:6473597d706e	467	#define BS_FMC_PFAPR_M3PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M3PFD.
bogdanm	82:6473597d706e	468
bogdanm	82:6473597d706e	469	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	470	//! @brief Read current value of the FMC_PFAPR_M3PFD field.
bogdanm	82:6473597d706e	471	#define BR_FMC_PFAPR_M3PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M3PFD))
bogdanm	82:6473597d706e	472	#endif
bogdanm	82:6473597d706e	473
bogdanm	82:6473597d706e	474	//! @brief Format value for bitfield FMC_PFAPR_M3PFD.
bogdanm	82:6473597d706e	475	#define BF_FMC_PFAPR_M3PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M3PFD), uint32_t) & BM_FMC_PFAPR_M3PFD)
bogdanm	82:6473597d706e	476
bogdanm	82:6473597d706e	477	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	478	//! @brief Set the M3PFD field to a new value.
bogdanm	82:6473597d706e	479	#define BW_FMC_PFAPR_M3PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M3PFD) = (v))
bogdanm	82:6473597d706e	480	#endif
bogdanm	82:6473597d706e	481	//@}
bogdanm	82:6473597d706e	482
bogdanm	82:6473597d706e	483	/*!
bogdanm	82:6473597d706e	484	* @name Register FMC_PFAPR, field M4PFD[20] (RW)
bogdanm	82:6473597d706e	485	*
bogdanm	82:6473597d706e	486	* These bits control whether prefetching is enabled based on the logical number
bogdanm	82:6473597d706e	487	* of the requesting crossbar switch master. This field is further qualified by
bogdanm	82:6473597d706e	488	* the PFBnCR[BxDPE,BxIPE] bits.
bogdanm	82:6473597d706e	489	*
bogdanm	82:6473597d706e	490	* Values:
bogdanm	82:6473597d706e	491	* - 0 - Prefetching for this master is enabled.
bogdanm	82:6473597d706e	492	* - 1 - Prefetching for this master is disabled.
bogdanm	82:6473597d706e	493	*/
bogdanm	82:6473597d706e	494	//@{
bogdanm	82:6473597d706e	495	#define BP_FMC_PFAPR_M4PFD (20U) //!< Bit position for FMC_PFAPR_M4PFD.
bogdanm	82:6473597d706e	496	#define BM_FMC_PFAPR_M4PFD (0x00100000U) //!< Bit mask for FMC_PFAPR_M4PFD.
bogdanm	82:6473597d706e	497	#define BS_FMC_PFAPR_M4PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M4PFD.
bogdanm	82:6473597d706e	498
bogdanm	82:6473597d706e	499	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	500	//! @brief Read current value of the FMC_PFAPR_M4PFD field.
bogdanm	82:6473597d706e	501	#define BR_FMC_PFAPR_M4PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M4PFD))
bogdanm	82:6473597d706e	502	#endif
bogdanm	82:6473597d706e	503
bogdanm	82:6473597d706e	504	//! @brief Format value for bitfield FMC_PFAPR_M4PFD.
bogdanm	82:6473597d706e	505	#define BF_FMC_PFAPR_M4PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M4PFD), uint32_t) & BM_FMC_PFAPR_M4PFD)
bogdanm	82:6473597d706e	506
bogdanm	82:6473597d706e	507	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	508	//! @brief Set the M4PFD field to a new value.
bogdanm	82:6473597d706e	509	#define BW_FMC_PFAPR_M4PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M4PFD) = (v))
bogdanm	82:6473597d706e	510	#endif
bogdanm	82:6473597d706e	511	//@}
bogdanm	82:6473597d706e	512
bogdanm	82:6473597d706e	513	/*!
bogdanm	82:6473597d706e	514	* @name Register FMC_PFAPR, field M5PFD[21] (RW)
bogdanm	82:6473597d706e	515	*
bogdanm	82:6473597d706e	516	* These bits control whether prefetching is enabled based on the logical number
bogdanm	82:6473597d706e	517	* of the requesting crossbar switch master. This field is further qualified by
bogdanm	82:6473597d706e	518	* the PFBnCR[BxDPE,BxIPE] bits.
bogdanm	82:6473597d706e	519	*
bogdanm	82:6473597d706e	520	* Values:
bogdanm	82:6473597d706e	521	* - 0 - Prefetching for this master is enabled.
bogdanm	82:6473597d706e	522	* - 1 - Prefetching for this master is disabled.
bogdanm	82:6473597d706e	523	*/
bogdanm	82:6473597d706e	524	//@{
bogdanm	82:6473597d706e	525	#define BP_FMC_PFAPR_M5PFD (21U) //!< Bit position for FMC_PFAPR_M5PFD.
bogdanm	82:6473597d706e	526	#define BM_FMC_PFAPR_M5PFD (0x00200000U) //!< Bit mask for FMC_PFAPR_M5PFD.
bogdanm	82:6473597d706e	527	#define BS_FMC_PFAPR_M5PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M5PFD.
bogdanm	82:6473597d706e	528
bogdanm	82:6473597d706e	529	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	530	//! @brief Read current value of the FMC_PFAPR_M5PFD field.
bogdanm	82:6473597d706e	531	#define BR_FMC_PFAPR_M5PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M5PFD))
bogdanm	82:6473597d706e	532	#endif
bogdanm	82:6473597d706e	533
bogdanm	82:6473597d706e	534	//! @brief Format value for bitfield FMC_PFAPR_M5PFD.
bogdanm	82:6473597d706e	535	#define BF_FMC_PFAPR_M5PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M5PFD), uint32_t) & BM_FMC_PFAPR_M5PFD)
bogdanm	82:6473597d706e	536
bogdanm	82:6473597d706e	537	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	538	//! @brief Set the M5PFD field to a new value.
bogdanm	82:6473597d706e	539	#define BW_FMC_PFAPR_M5PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M5PFD) = (v))
bogdanm	82:6473597d706e	540	#endif
bogdanm	82:6473597d706e	541	//@}
bogdanm	82:6473597d706e	542
bogdanm	82:6473597d706e	543	/*!
bogdanm	82:6473597d706e	544	* @name Register FMC_PFAPR, field M6PFD[22] (RW)
bogdanm	82:6473597d706e	545	*
bogdanm	82:6473597d706e	546	* These bits control whether prefetching is enabled based on the logical number
bogdanm	82:6473597d706e	547	* of the requesting crossbar switch master. This field is further qualified by
bogdanm	82:6473597d706e	548	* the PFBnCR[BxDPE,BxIPE] bits.
bogdanm	82:6473597d706e	549	*
bogdanm	82:6473597d706e	550	* Values:
bogdanm	82:6473597d706e	551	* - 0 - Prefetching for this master is enabled.
bogdanm	82:6473597d706e	552	* - 1 - Prefetching for this master is disabled.
bogdanm	82:6473597d706e	553	*/
bogdanm	82:6473597d706e	554	//@{
bogdanm	82:6473597d706e	555	#define BP_FMC_PFAPR_M6PFD (22U) //!< Bit position for FMC_PFAPR_M6PFD.
bogdanm	82:6473597d706e	556	#define BM_FMC_PFAPR_M6PFD (0x00400000U) //!< Bit mask for FMC_PFAPR_M6PFD.
bogdanm	82:6473597d706e	557	#define BS_FMC_PFAPR_M6PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M6PFD.
bogdanm	82:6473597d706e	558
bogdanm	82:6473597d706e	559	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	560	//! @brief Read current value of the FMC_PFAPR_M6PFD field.
bogdanm	82:6473597d706e	561	#define BR_FMC_PFAPR_M6PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M6PFD))
bogdanm	82:6473597d706e	562	#endif
bogdanm	82:6473597d706e	563
bogdanm	82:6473597d706e	564	//! @brief Format value for bitfield FMC_PFAPR_M6PFD.
bogdanm	82:6473597d706e	565	#define BF_FMC_PFAPR_M6PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M6PFD), uint32_t) & BM_FMC_PFAPR_M6PFD)
bogdanm	82:6473597d706e	566
bogdanm	82:6473597d706e	567	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	568	//! @brief Set the M6PFD field to a new value.
bogdanm	82:6473597d706e	569	#define BW_FMC_PFAPR_M6PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M6PFD) = (v))
bogdanm	82:6473597d706e	570	#endif
bogdanm	82:6473597d706e	571	//@}
bogdanm	82:6473597d706e	572
bogdanm	82:6473597d706e	573	/*!
bogdanm	82:6473597d706e	574	* @name Register FMC_PFAPR, field M7PFD[23] (RW)
bogdanm	82:6473597d706e	575	*
bogdanm	82:6473597d706e	576	* These bits control whether prefetching is enabled based on the logical number
bogdanm	82:6473597d706e	577	* of the requesting crossbar switch master. This field is further qualified by
bogdanm	82:6473597d706e	578	* the PFBnCR[BxDPE,BxIPE] bits.
bogdanm	82:6473597d706e	579	*
bogdanm	82:6473597d706e	580	* Values:
bogdanm	82:6473597d706e	581	* - 0 - Prefetching for this master is enabled.
bogdanm	82:6473597d706e	582	* - 1 - Prefetching for this master is disabled.
bogdanm	82:6473597d706e	583	*/
bogdanm	82:6473597d706e	584	//@{
bogdanm	82:6473597d706e	585	#define BP_FMC_PFAPR_M7PFD (23U) //!< Bit position for FMC_PFAPR_M7PFD.
bogdanm	82:6473597d706e	586	#define BM_FMC_PFAPR_M7PFD (0x00800000U) //!< Bit mask for FMC_PFAPR_M7PFD.
bogdanm	82:6473597d706e	587	#define BS_FMC_PFAPR_M7PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M7PFD.
bogdanm	82:6473597d706e	588
bogdanm	82:6473597d706e	589	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	590	//! @brief Read current value of the FMC_PFAPR_M7PFD field.
bogdanm	82:6473597d706e	591	#define BR_FMC_PFAPR_M7PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M7PFD))
bogdanm	82:6473597d706e	592	#endif
bogdanm	82:6473597d706e	593
bogdanm	82:6473597d706e	594	//! @brief Format value for bitfield FMC_PFAPR_M7PFD.
bogdanm	82:6473597d706e	595	#define BF_FMC_PFAPR_M7PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M7PFD), uint32_t) & BM_FMC_PFAPR_M7PFD)
bogdanm	82:6473597d706e	596
bogdanm	82:6473597d706e	597	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	598	//! @brief Set the M7PFD field to a new value.
bogdanm	82:6473597d706e	599	#define BW_FMC_PFAPR_M7PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M7PFD) = (v))
bogdanm	82:6473597d706e	600	#endif
bogdanm	82:6473597d706e	601	//@}
bogdanm	82:6473597d706e	602
bogdanm	82:6473597d706e	603	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	604	// HW_FMC_PFB0CR - Flash Bank 0 Control Register
bogdanm	82:6473597d706e	605	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	606
bogdanm	82:6473597d706e	607	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	608	/*!
bogdanm	82:6473597d706e	609	* @brief HW_FMC_PFB0CR - Flash Bank 0 Control Register (RW)
bogdanm	82:6473597d706e	610	*
bogdanm	82:6473597d706e	611	* Reset value: 0x3004001FU
bogdanm	82:6473597d706e	612	*/
bogdanm	82:6473597d706e	613	typedef union _hw_fmc_pfb0cr
bogdanm	82:6473597d706e	614	{
bogdanm	82:6473597d706e	615	uint32_t U;
bogdanm	82:6473597d706e	616	struct _hw_fmc_pfb0cr_bitfields
bogdanm	82:6473597d706e	617	{
bogdanm	82:6473597d706e	618	uint32_t B0SEBE : 1; //!< [0] Bank 0 Single Entry Buffer Enable
bogdanm	82:6473597d706e	619	uint32_t B0IPE : 1; //!< [1] Bank 0 Instruction Prefetch Enable
bogdanm	82:6473597d706e	620	uint32_t B0DPE : 1; //!< [2] Bank 0 Data Prefetch Enable
bogdanm	82:6473597d706e	621	uint32_t B0ICE : 1; //!< [3] Bank 0 Instruction Cache Enable
bogdanm	82:6473597d706e	622	uint32_t B0DCE : 1; //!< [4] Bank 0 Data Cache Enable
bogdanm	82:6473597d706e	623	uint32_t CRCb : 3; //!< [7:5] Cache Replacement Control
bogdanm	82:6473597d706e	624	uint32_t RESERVED0 : 9; //!< [16:8]
bogdanm	82:6473597d706e	625	uint32_t B0MW : 2; //!< [18:17] Bank 0 Memory Width
bogdanm	82:6473597d706e	626	uint32_t S_B_INV : 1; //!< [19] Invalidate Prefetch Speculation Buffer
bogdanm	82:6473597d706e	627	uint32_t CINV_WAY : 4; //!< [23:20] Cache Invalidate Way x
bogdanm	82:6473597d706e	628	uint32_t CLCK_WAY : 4; //!< [27:24] Cache Lock Way x
bogdanm	82:6473597d706e	629	uint32_t B0RWSC : 4; //!< [31:28] Bank 0 Read Wait State Control
bogdanm	82:6473597d706e	630	} B;
bogdanm	82:6473597d706e	631	} hw_fmc_pfb0cr_t;
bogdanm	82:6473597d706e	632	#endif
bogdanm	82:6473597d706e	633
bogdanm	82:6473597d706e	634	/*!
bogdanm	82:6473597d706e	635	* @name Constants and macros for entire FMC_PFB0CR register
bogdanm	82:6473597d706e	636	*/
bogdanm	82:6473597d706e	637	//@{
bogdanm	82:6473597d706e	638	#define HW_FMC_PFB0CR_ADDR (REGS_FMC_BASE + 0x4U)
bogdanm	82:6473597d706e	639
bogdanm	82:6473597d706e	640	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	641	#define HW_FMC_PFB0CR ((__IO hw_fmc_pfb0cr_t ) HW_FMC_PFB0CR_ADDR)
bogdanm	82:6473597d706e	642	#define HW_FMC_PFB0CR_RD() (HW_FMC_PFB0CR.U)
bogdanm	82:6473597d706e	643	#define HW_FMC_PFB0CR_WR(v) (HW_FMC_PFB0CR.U = (v))
bogdanm	82:6473597d706e	644	#define HW_FMC_PFB0CR_SET(v) (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() \| (v)))
bogdanm	82:6473597d706e	645	#define HW_FMC_PFB0CR_CLR(v) (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() & ~(v)))
bogdanm	82:6473597d706e	646	#define HW_FMC_PFB0CR_TOG(v) (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() ^ (v)))
bogdanm	82:6473597d706e	647	#endif
bogdanm	82:6473597d706e	648	//@}
bogdanm	82:6473597d706e	649
bogdanm	82:6473597d706e	650	/*
bogdanm	82:6473597d706e	651	* Constants & macros for individual FMC_PFB0CR bitfields
bogdanm	82:6473597d706e	652	*/
bogdanm	82:6473597d706e	653
bogdanm	82:6473597d706e	654	/*!
bogdanm	82:6473597d706e	655	* @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
bogdanm	82:6473597d706e	656	*
bogdanm	82:6473597d706e	657	* This bit controls whether the single entry page buffer is enabled in response
bogdanm	82:6473597d706e	658	* to flash read accesses. Its operation is independent from bank 1's cache. A
bogdanm	82:6473597d706e	659	* high-to-low transition of this enable forces the page buffer to be invalidated.
bogdanm	82:6473597d706e	660	*
bogdanm	82:6473597d706e	661	* Values:
bogdanm	82:6473597d706e	662	* - 0 - Single entry buffer is disabled.
bogdanm	82:6473597d706e	663	* - 1 - Single entry buffer is enabled.
bogdanm	82:6473597d706e	664	*/
bogdanm	82:6473597d706e	665	//@{
bogdanm	82:6473597d706e	666	#define BP_FMC_PFB0CR_B0SEBE (0U) //!< Bit position for FMC_PFB0CR_B0SEBE.
bogdanm	82:6473597d706e	667	#define BM_FMC_PFB0CR_B0SEBE (0x00000001U) //!< Bit mask for FMC_PFB0CR_B0SEBE.
bogdanm	82:6473597d706e	668	#define BS_FMC_PFB0CR_B0SEBE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0SEBE.
bogdanm	82:6473597d706e	669
bogdanm	82:6473597d706e	670	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	671	//! @brief Read current value of the FMC_PFB0CR_B0SEBE field.
bogdanm	82:6473597d706e	672	#define BR_FMC_PFB0CR_B0SEBE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0SEBE))
bogdanm	82:6473597d706e	673	#endif
bogdanm	82:6473597d706e	674
bogdanm	82:6473597d706e	675	//! @brief Format value for bitfield FMC_PFB0CR_B0SEBE.
bogdanm	82:6473597d706e	676	#define BF_FMC_PFB0CR_B0SEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0SEBE), uint32_t) & BM_FMC_PFB0CR_B0SEBE)
bogdanm	82:6473597d706e	677
bogdanm	82:6473597d706e	678	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	679	//! @brief Set the B0SEBE field to a new value.
bogdanm	82:6473597d706e	680	#define BW_FMC_PFB0CR_B0SEBE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0SEBE) = (v))
bogdanm	82:6473597d706e	681	#endif
bogdanm	82:6473597d706e	682	//@}
bogdanm	82:6473597d706e	683
bogdanm	82:6473597d706e	684	/*!
bogdanm	82:6473597d706e	685	* @name Register FMC_PFB0CR, field B0IPE[1] (RW)
bogdanm	82:6473597d706e	686	*
bogdanm	82:6473597d706e	687	* This bit controls whether prefetches (or speculative accesses) are initiated
bogdanm	82:6473597d706e	688	* in response to instruction fetches.
bogdanm	82:6473597d706e	689	*
bogdanm	82:6473597d706e	690	* Values:
bogdanm	82:6473597d706e	691	* - 0 - Do not prefetch in response to instruction fetches.
bogdanm	82:6473597d706e	692	* - 1 - Enable prefetches in response to instruction fetches.
bogdanm	82:6473597d706e	693	*/
bogdanm	82:6473597d706e	694	//@{
bogdanm	82:6473597d706e	695	#define BP_FMC_PFB0CR_B0IPE (1U) //!< Bit position for FMC_PFB0CR_B0IPE.
bogdanm	82:6473597d706e	696	#define BM_FMC_PFB0CR_B0IPE (0x00000002U) //!< Bit mask for FMC_PFB0CR_B0IPE.
bogdanm	82:6473597d706e	697	#define BS_FMC_PFB0CR_B0IPE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0IPE.
bogdanm	82:6473597d706e	698
bogdanm	82:6473597d706e	699	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	700	//! @brief Read current value of the FMC_PFB0CR_B0IPE field.
bogdanm	82:6473597d706e	701	#define BR_FMC_PFB0CR_B0IPE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0IPE))
bogdanm	82:6473597d706e	702	#endif
bogdanm	82:6473597d706e	703
bogdanm	82:6473597d706e	704	//! @brief Format value for bitfield FMC_PFB0CR_B0IPE.
bogdanm	82:6473597d706e	705	#define BF_FMC_PFB0CR_B0IPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0IPE), uint32_t) & BM_FMC_PFB0CR_B0IPE)
bogdanm	82:6473597d706e	706
bogdanm	82:6473597d706e	707	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	708	//! @brief Set the B0IPE field to a new value.
bogdanm	82:6473597d706e	709	#define BW_FMC_PFB0CR_B0IPE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0IPE) = (v))
bogdanm	82:6473597d706e	710	#endif
bogdanm	82:6473597d706e	711	//@}
bogdanm	82:6473597d706e	712
bogdanm	82:6473597d706e	713	/*!
bogdanm	82:6473597d706e	714	* @name Register FMC_PFB0CR, field B0DPE[2] (RW)
bogdanm	82:6473597d706e	715	*
bogdanm	82:6473597d706e	716	* This bit controls whether prefetches (or speculative accesses) are initiated
bogdanm	82:6473597d706e	717	* in response to data references.
bogdanm	82:6473597d706e	718	*
bogdanm	82:6473597d706e	719	* Values:
bogdanm	82:6473597d706e	720	* - 0 - Do not prefetch in response to data references.
bogdanm	82:6473597d706e	721	* - 1 - Enable prefetches in response to data references.
bogdanm	82:6473597d706e	722	*/
bogdanm	82:6473597d706e	723	//@{
bogdanm	82:6473597d706e	724	#define BP_FMC_PFB0CR_B0DPE (2U) //!< Bit position for FMC_PFB0CR_B0DPE.
bogdanm	82:6473597d706e	725	#define BM_FMC_PFB0CR_B0DPE (0x00000004U) //!< Bit mask for FMC_PFB0CR_B0DPE.
bogdanm	82:6473597d706e	726	#define BS_FMC_PFB0CR_B0DPE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0DPE.
bogdanm	82:6473597d706e	727
bogdanm	82:6473597d706e	728	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	729	//! @brief Read current value of the FMC_PFB0CR_B0DPE field.
bogdanm	82:6473597d706e	730	#define BR_FMC_PFB0CR_B0DPE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DPE))
bogdanm	82:6473597d706e	731	#endif
bogdanm	82:6473597d706e	732
bogdanm	82:6473597d706e	733	//! @brief Format value for bitfield FMC_PFB0CR_B0DPE.
bogdanm	82:6473597d706e	734	#define BF_FMC_PFB0CR_B0DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0DPE), uint32_t) & BM_FMC_PFB0CR_B0DPE)
bogdanm	82:6473597d706e	735
bogdanm	82:6473597d706e	736	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	737	//! @brief Set the B0DPE field to a new value.
bogdanm	82:6473597d706e	738	#define BW_FMC_PFB0CR_B0DPE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DPE) = (v))
bogdanm	82:6473597d706e	739	#endif
bogdanm	82:6473597d706e	740	//@}
bogdanm	82:6473597d706e	741
bogdanm	82:6473597d706e	742	/*!
bogdanm	82:6473597d706e	743	* @name Register FMC_PFB0CR, field B0ICE[3] (RW)
bogdanm	82:6473597d706e	744	*
bogdanm	82:6473597d706e	745	* This bit controls whether instruction fetches are loaded into the cache.
bogdanm	82:6473597d706e	746	*
bogdanm	82:6473597d706e	747	* Values:
bogdanm	82:6473597d706e	748	* - 0 - Do not cache instruction fetches.
bogdanm	82:6473597d706e	749	* - 1 - Cache instruction fetches.
bogdanm	82:6473597d706e	750	*/
bogdanm	82:6473597d706e	751	//@{
bogdanm	82:6473597d706e	752	#define BP_FMC_PFB0CR_B0ICE (3U) //!< Bit position for FMC_PFB0CR_B0ICE.
bogdanm	82:6473597d706e	753	#define BM_FMC_PFB0CR_B0ICE (0x00000008U) //!< Bit mask for FMC_PFB0CR_B0ICE.
bogdanm	82:6473597d706e	754	#define BS_FMC_PFB0CR_B0ICE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0ICE.
bogdanm	82:6473597d706e	755
bogdanm	82:6473597d706e	756	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	757	//! @brief Read current value of the FMC_PFB0CR_B0ICE field.
bogdanm	82:6473597d706e	758	#define BR_FMC_PFB0CR_B0ICE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0ICE))
bogdanm	82:6473597d706e	759	#endif
bogdanm	82:6473597d706e	760
bogdanm	82:6473597d706e	761	//! @brief Format value for bitfield FMC_PFB0CR_B0ICE.
bogdanm	82:6473597d706e	762	#define BF_FMC_PFB0CR_B0ICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0ICE), uint32_t) & BM_FMC_PFB0CR_B0ICE)
bogdanm	82:6473597d706e	763
bogdanm	82:6473597d706e	764	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	765	//! @brief Set the B0ICE field to a new value.
bogdanm	82:6473597d706e	766	#define BW_FMC_PFB0CR_B0ICE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0ICE) = (v))
bogdanm	82:6473597d706e	767	#endif
bogdanm	82:6473597d706e	768	//@}
bogdanm	82:6473597d706e	769
bogdanm	82:6473597d706e	770	/*!
bogdanm	82:6473597d706e	771	* @name Register FMC_PFB0CR, field B0DCE[4] (RW)
bogdanm	82:6473597d706e	772	*
bogdanm	82:6473597d706e	773	* This bit controls whether data references are loaded into the cache.
bogdanm	82:6473597d706e	774	*
bogdanm	82:6473597d706e	775	* Values:
bogdanm	82:6473597d706e	776	* - 0 - Do not cache data references.
bogdanm	82:6473597d706e	777	* - 1 - Cache data references.
bogdanm	82:6473597d706e	778	*/
bogdanm	82:6473597d706e	779	//@{
bogdanm	82:6473597d706e	780	#define BP_FMC_PFB0CR_B0DCE (4U) //!< Bit position for FMC_PFB0CR_B0DCE.
bogdanm	82:6473597d706e	781	#define BM_FMC_PFB0CR_B0DCE (0x00000010U) //!< Bit mask for FMC_PFB0CR_B0DCE.
bogdanm	82:6473597d706e	782	#define BS_FMC_PFB0CR_B0DCE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0DCE.
bogdanm	82:6473597d706e	783
bogdanm	82:6473597d706e	784	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	785	//! @brief Read current value of the FMC_PFB0CR_B0DCE field.
bogdanm	82:6473597d706e	786	#define BR_FMC_PFB0CR_B0DCE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DCE))
bogdanm	82:6473597d706e	787	#endif
bogdanm	82:6473597d706e	788
bogdanm	82:6473597d706e	789	//! @brief Format value for bitfield FMC_PFB0CR_B0DCE.
bogdanm	82:6473597d706e	790	#define BF_FMC_PFB0CR_B0DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0DCE), uint32_t) & BM_FMC_PFB0CR_B0DCE)
bogdanm	82:6473597d706e	791
bogdanm	82:6473597d706e	792	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	793	//! @brief Set the B0DCE field to a new value.
bogdanm	82:6473597d706e	794	#define BW_FMC_PFB0CR_B0DCE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DCE) = (v))
bogdanm	82:6473597d706e	795	#endif
bogdanm	82:6473597d706e	796	//@}
bogdanm	82:6473597d706e	797
bogdanm	82:6473597d706e	798	/*!
bogdanm	82:6473597d706e	799	* @name Register FMC_PFB0CR, field CRC[7:5] (RW)
bogdanm	82:6473597d706e	800	*
bogdanm	82:6473597d706e	801	* This 3-bit field defines the replacement algorithm for accesses that are
bogdanm	82:6473597d706e	802	* cached.
bogdanm	82:6473597d706e	803	*
bogdanm	82:6473597d706e	804	* Values:
bogdanm	82:6473597d706e	805	* - 000 - LRU replacement algorithm per set across all four ways
bogdanm	82:6473597d706e	806	* - 001 - Reserved
bogdanm	82:6473597d706e	807	* - 010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
bogdanm	82:6473597d706e	808	* - 011 - Independent LRU with ways [0-2] for ifetches, [3] for data
bogdanm	82:6473597d706e	809	* - 1xx - Reserved
bogdanm	82:6473597d706e	810	*/
bogdanm	82:6473597d706e	811	//@{
bogdanm	82:6473597d706e	812	#define BP_FMC_PFB0CR_CRC (5U) //!< Bit position for FMC_PFB0CR_CRC.
bogdanm	82:6473597d706e	813	#define BM_FMC_PFB0CR_CRC (0x000000E0U) //!< Bit mask for FMC_PFB0CR_CRC.
bogdanm	82:6473597d706e	814	#define BS_FMC_PFB0CR_CRC (3U) //!< Bit field size in bits for FMC_PFB0CR_CRC.
bogdanm	82:6473597d706e	815
bogdanm	82:6473597d706e	816	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	817	//! @brief Read current value of the FMC_PFB0CR_CRC field.
bogdanm	82:6473597d706e	818	#define BR_FMC_PFB0CR_CRC (HW_FMC_PFB0CR.B.CRC)
bogdanm	82:6473597d706e	819	#endif
bogdanm	82:6473597d706e	820
bogdanm	82:6473597d706e	821	//! @brief Format value for bitfield FMC_PFB0CR_CRC.
bogdanm	82:6473597d706e	822	#define BF_FMC_PFB0CR_CRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CRC), uint32_t) & BM_FMC_PFB0CR_CRC)
bogdanm	82:6473597d706e	823
bogdanm	82:6473597d706e	824	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	825	//! @brief Set the CRC field to a new value.
bogdanm	82:6473597d706e	826	#define BW_FMC_PFB0CR_CRC(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CRC) \| BF_FMC_PFB0CR_CRC(v)))
bogdanm	82:6473597d706e	827	#endif
bogdanm	82:6473597d706e	828	//@}
bogdanm	82:6473597d706e	829
bogdanm	82:6473597d706e	830	/*!
bogdanm	82:6473597d706e	831	* @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
bogdanm	82:6473597d706e	832	*
bogdanm	82:6473597d706e	833	* This read-only field defines the width of the bank 0 memory.
bogdanm	82:6473597d706e	834	*
bogdanm	82:6473597d706e	835	* Values:
bogdanm	82:6473597d706e	836	* - 00 - 32 bits
bogdanm	82:6473597d706e	837	* - 01 - 64 bits
bogdanm	82:6473597d706e	838	* - 10 - 128 bits
bogdanm	82:6473597d706e	839	* - 11 - Reserved
bogdanm	82:6473597d706e	840	*/
bogdanm	82:6473597d706e	841	//@{
bogdanm	82:6473597d706e	842	#define BP_FMC_PFB0CR_B0MW (17U) //!< Bit position for FMC_PFB0CR_B0MW.
bogdanm	82:6473597d706e	843	#define BM_FMC_PFB0CR_B0MW (0x00060000U) //!< Bit mask for FMC_PFB0CR_B0MW.
bogdanm	82:6473597d706e	844	#define BS_FMC_PFB0CR_B0MW (2U) //!< Bit field size in bits for FMC_PFB0CR_B0MW.
bogdanm	82:6473597d706e	845
bogdanm	82:6473597d706e	846	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	847	//! @brief Read current value of the FMC_PFB0CR_B0MW field.
bogdanm	82:6473597d706e	848	#define BR_FMC_PFB0CR_B0MW (HW_FMC_PFB0CR.B.B0MW)
bogdanm	82:6473597d706e	849	#endif
bogdanm	82:6473597d706e	850	//@}
bogdanm	82:6473597d706e	851
bogdanm	82:6473597d706e	852	/*!
bogdanm	82:6473597d706e	853	* @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
bogdanm	82:6473597d706e	854	*
bogdanm	82:6473597d706e	855	* This bit determines if the FMC's prefetch speculation buffer and the single
bogdanm	82:6473597d706e	856	* entry page buffer are to be invalidated (cleared). When this bit is written,
bogdanm	82:6473597d706e	857	* the speculation buffer and single entry buffer are immediately cleared. This bit
bogdanm	82:6473597d706e	858	* always reads as zero.
bogdanm	82:6473597d706e	859	*
bogdanm	82:6473597d706e	860	* Values:
bogdanm	82:6473597d706e	861	* - 0 - Speculation buffer and single entry buffer are not affected.
bogdanm	82:6473597d706e	862	* - 1 - Invalidate (clear) speculation buffer and single entry buffer.
bogdanm	82:6473597d706e	863	*/
bogdanm	82:6473597d706e	864	//@{
bogdanm	82:6473597d706e	865	#define BP_FMC_PFB0CR_S_B_INV (19U) //!< Bit position for FMC_PFB0CR_S_B_INV.
bogdanm	82:6473597d706e	866	#define BM_FMC_PFB0CR_S_B_INV (0x00080000U) //!< Bit mask for FMC_PFB0CR_S_B_INV.
bogdanm	82:6473597d706e	867	#define BS_FMC_PFB0CR_S_B_INV (1U) //!< Bit field size in bits for FMC_PFB0CR_S_B_INV.
bogdanm	82:6473597d706e	868
bogdanm	82:6473597d706e	869	//! @brief Format value for bitfield FMC_PFB0CR_S_B_INV.
bogdanm	82:6473597d706e	870	#define BF_FMC_PFB0CR_S_B_INV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_S_B_INV), uint32_t) & BM_FMC_PFB0CR_S_B_INV)
bogdanm	82:6473597d706e	871
bogdanm	82:6473597d706e	872	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	873	//! @brief Set the S_B_INV field to a new value.
bogdanm	82:6473597d706e	874	#define BW_FMC_PFB0CR_S_B_INV(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_S_B_INV) = (v))
bogdanm	82:6473597d706e	875	#endif
bogdanm	82:6473597d706e	876	//@}
bogdanm	82:6473597d706e	877
bogdanm	82:6473597d706e	878	/*!
bogdanm	82:6473597d706e	879	* @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
bogdanm	82:6473597d706e	880	*
bogdanm	82:6473597d706e	881	* These bits determine if the given cache way is to be invalidated (cleared).
bogdanm	82:6473597d706e	882	* When a bit within this field is written, the corresponding cache way is
bogdanm	82:6473597d706e	883	* immediately invalidated: the way's tag, data, and valid contents are cleared. This
bogdanm	82:6473597d706e	884	* field always reads as zero. Cache invalidation takes precedence over locking.
bogdanm	82:6473597d706e	885	* The cache is invalidated by system reset. System software is required to
bogdanm	82:6473597d706e	886	* maintain memory coherency when any segment of the flash memory is programmed or
bogdanm	82:6473597d706e	887	* erased. Accordingly, cache invalidations must occur after a programming or erase
bogdanm	82:6473597d706e	888	* event is completed and before the new memory image is accessed. The bit setting
bogdanm	82:6473597d706e	889	* definitions are for each bit in the field.
bogdanm	82:6473597d706e	890	*
bogdanm	82:6473597d706e	891	* Values:
bogdanm	82:6473597d706e	892	* - 0 - No cache way invalidation for the corresponding cache
bogdanm	82:6473597d706e	893	* - 1 - Invalidate cache way for the corresponding cache: clear the tag, data,
bogdanm	82:6473597d706e	894	* and vld bits of ways selected
bogdanm	82:6473597d706e	895	*/
bogdanm	82:6473597d706e	896	//@{
bogdanm	82:6473597d706e	897	#define BP_FMC_PFB0CR_CINV_WAY (20U) //!< Bit position for FMC_PFB0CR_CINV_WAY.
bogdanm	82:6473597d706e	898	#define BM_FMC_PFB0CR_CINV_WAY (0x00F00000U) //!< Bit mask for FMC_PFB0CR_CINV_WAY.
bogdanm	82:6473597d706e	899	#define BS_FMC_PFB0CR_CINV_WAY (4U) //!< Bit field size in bits for FMC_PFB0CR_CINV_WAY.
bogdanm	82:6473597d706e	900
bogdanm	82:6473597d706e	901	//! @brief Format value for bitfield FMC_PFB0CR_CINV_WAY.
bogdanm	82:6473597d706e	902	#define BF_FMC_PFB0CR_CINV_WAY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CINV_WAY), uint32_t) & BM_FMC_PFB0CR_CINV_WAY)
bogdanm	82:6473597d706e	903
bogdanm	82:6473597d706e	904	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	905	//! @brief Set the CINV_WAY field to a new value.
bogdanm	82:6473597d706e	906	#define BW_FMC_PFB0CR_CINV_WAY(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CINV_WAY) \| BF_FMC_PFB0CR_CINV_WAY(v)))
bogdanm	82:6473597d706e	907	#endif
bogdanm	82:6473597d706e	908	//@}
bogdanm	82:6473597d706e	909
bogdanm	82:6473597d706e	910	/*!
bogdanm	82:6473597d706e	911	* @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
bogdanm	82:6473597d706e	912	*
bogdanm	82:6473597d706e	913	* These bits determine if the given cache way is locked such that its contents
bogdanm	82:6473597d706e	914	* will not be displaced by future misses. The bit setting definitions are for
bogdanm	82:6473597d706e	915	* each bit in the field.
bogdanm	82:6473597d706e	916	*
bogdanm	82:6473597d706e	917	* Values:
bogdanm	82:6473597d706e	918	* - 0 - Cache way is unlocked and may be displaced
bogdanm	82:6473597d706e	919	* - 1 - Cache way is locked and its contents are not displaced
bogdanm	82:6473597d706e	920	*/
bogdanm	82:6473597d706e	921	//@{
bogdanm	82:6473597d706e	922	#define BP_FMC_PFB0CR_CLCK_WAY (24U) //!< Bit position for FMC_PFB0CR_CLCK_WAY.
bogdanm	82:6473597d706e	923	#define BM_FMC_PFB0CR_CLCK_WAY (0x0F000000U) //!< Bit mask for FMC_PFB0CR_CLCK_WAY.
bogdanm	82:6473597d706e	924	#define BS_FMC_PFB0CR_CLCK_WAY (4U) //!< Bit field size in bits for FMC_PFB0CR_CLCK_WAY.
bogdanm	82:6473597d706e	925
bogdanm	82:6473597d706e	926	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	927	//! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field.
bogdanm	82:6473597d706e	928	#define BR_FMC_PFB0CR_CLCK_WAY (HW_FMC_PFB0CR.B.CLCK_WAY)
bogdanm	82:6473597d706e	929	#endif
bogdanm	82:6473597d706e	930
bogdanm	82:6473597d706e	931	//! @brief Format value for bitfield FMC_PFB0CR_CLCK_WAY.
bogdanm	82:6473597d706e	932	#define BF_FMC_PFB0CR_CLCK_WAY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CLCK_WAY), uint32_t) & BM_FMC_PFB0CR_CLCK_WAY)
bogdanm	82:6473597d706e	933
bogdanm	82:6473597d706e	934	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	935	//! @brief Set the CLCK_WAY field to a new value.
bogdanm	82:6473597d706e	936	#define BW_FMC_PFB0CR_CLCK_WAY(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CLCK_WAY) \| BF_FMC_PFB0CR_CLCK_WAY(v)))
bogdanm	82:6473597d706e	937	#endif
bogdanm	82:6473597d706e	938	//@}
bogdanm	82:6473597d706e	939
bogdanm	82:6473597d706e	940	/*!
bogdanm	82:6473597d706e	941	* @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
bogdanm	82:6473597d706e	942	*
bogdanm	82:6473597d706e	943	* This read-only field defines the number of wait states required to access the
bogdanm	82:6473597d706e	944	* bank 0 flash memory. The relationship between the read access time of the
bogdanm	82:6473597d706e	945	* flash array (expressed in system clock cycles) and RWSC is defined as: Access
bogdanm	82:6473597d706e	946	* time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
bogdanm	82:6473597d706e	947	* this value based on the ratio of the system clock speed to the flash clock
bogdanm	82:6473597d706e	948	* speed. For example, when this ratio is 4:1, the field's value is 3h.
bogdanm	82:6473597d706e	949	*/
bogdanm	82:6473597d706e	950	//@{
bogdanm	82:6473597d706e	951	#define BP_FMC_PFB0CR_B0RWSC (28U) //!< Bit position for FMC_PFB0CR_B0RWSC.
bogdanm	82:6473597d706e	952	#define BM_FMC_PFB0CR_B0RWSC (0xF0000000U) //!< Bit mask for FMC_PFB0CR_B0RWSC.
bogdanm	82:6473597d706e	953	#define BS_FMC_PFB0CR_B0RWSC (4U) //!< Bit field size in bits for FMC_PFB0CR_B0RWSC.
bogdanm	82:6473597d706e	954
bogdanm	82:6473597d706e	955	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	956	//! @brief Read current value of the FMC_PFB0CR_B0RWSC field.
bogdanm	82:6473597d706e	957	#define BR_FMC_PFB0CR_B0RWSC (HW_FMC_PFB0CR.B.B0RWSC)
bogdanm	82:6473597d706e	958	#endif
bogdanm	82:6473597d706e	959	//@}
bogdanm	82:6473597d706e	960
bogdanm	82:6473597d706e	961	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	962	// HW_FMC_PFB1CR - Flash Bank 1 Control Register
bogdanm	82:6473597d706e	963	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	964
bogdanm	82:6473597d706e	965	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	966	/*!
bogdanm	82:6473597d706e	967	* @brief HW_FMC_PFB1CR - Flash Bank 1 Control Register (RW)
bogdanm	82:6473597d706e	968	*
bogdanm	82:6473597d706e	969	* Reset value: 0x3004001FU
bogdanm	82:6473597d706e	970	*
bogdanm	82:6473597d706e	971	* This register has a format similar to that for PFB0CR, except it controls the
bogdanm	82:6473597d706e	972	* operation of flash bank 1, and the "global" cache control fields are empty.
bogdanm	82:6473597d706e	973	*/
bogdanm	82:6473597d706e	974	typedef union _hw_fmc_pfb1cr
bogdanm	82:6473597d706e	975	{
bogdanm	82:6473597d706e	976	uint32_t U;
bogdanm	82:6473597d706e	977	struct _hw_fmc_pfb1cr_bitfields
bogdanm	82:6473597d706e	978	{
bogdanm	82:6473597d706e	979	uint32_t B1SEBE : 1; //!< [0] Bank 1 Single Entry Buffer Enable
bogdanm	82:6473597d706e	980	uint32_t B1IPE : 1; //!< [1] Bank 1 Instruction Prefetch Enable
bogdanm	82:6473597d706e	981	uint32_t B1DPE : 1; //!< [2] Bank 1 Data Prefetch Enable
bogdanm	82:6473597d706e	982	uint32_t B1ICE : 1; //!< [3] Bank 1 Instruction Cache Enable
bogdanm	82:6473597d706e	983	uint32_t B1DCE : 1; //!< [4] Bank 1 Data Cache Enable
bogdanm	82:6473597d706e	984	uint32_t RESERVED0 : 12; //!< [16:5]
bogdanm	82:6473597d706e	985	uint32_t B1MW : 2; //!< [18:17] Bank 1 Memory Width
bogdanm	82:6473597d706e	986	uint32_t RESERVED1 : 9; //!< [27:19]
bogdanm	82:6473597d706e	987	uint32_t B1RWSC : 4; //!< [31:28] Bank 1 Read Wait State Control
bogdanm	82:6473597d706e	988	} B;
bogdanm	82:6473597d706e	989	} hw_fmc_pfb1cr_t;
bogdanm	82:6473597d706e	990	#endif
bogdanm	82:6473597d706e	991
bogdanm	82:6473597d706e	992	/*!
bogdanm	82:6473597d706e	993	* @name Constants and macros for entire FMC_PFB1CR register
bogdanm	82:6473597d706e	994	*/
bogdanm	82:6473597d706e	995	//@{
bogdanm	82:6473597d706e	996	#define HW_FMC_PFB1CR_ADDR (REGS_FMC_BASE + 0x8U)
bogdanm	82:6473597d706e	997
bogdanm	82:6473597d706e	998	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	999	#define HW_FMC_PFB1CR ((__IO hw_fmc_pfb1cr_t ) HW_FMC_PFB1CR_ADDR)
bogdanm	82:6473597d706e	1000	#define HW_FMC_PFB1CR_RD() (HW_FMC_PFB1CR.U)
bogdanm	82:6473597d706e	1001	#define HW_FMC_PFB1CR_WR(v) (HW_FMC_PFB1CR.U = (v))
bogdanm	82:6473597d706e	1002	#define HW_FMC_PFB1CR_SET(v) (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() \| (v)))
bogdanm	82:6473597d706e	1003	#define HW_FMC_PFB1CR_CLR(v) (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() & ~(v)))
bogdanm	82:6473597d706e	1004	#define HW_FMC_PFB1CR_TOG(v) (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() ^ (v)))
bogdanm	82:6473597d706e	1005	#endif
bogdanm	82:6473597d706e	1006	//@}
bogdanm	82:6473597d706e	1007
bogdanm	82:6473597d706e	1008	/*
bogdanm	82:6473597d706e	1009	* Constants & macros for individual FMC_PFB1CR bitfields
bogdanm	82:6473597d706e	1010	*/
bogdanm	82:6473597d706e	1011
bogdanm	82:6473597d706e	1012	/*!
bogdanm	82:6473597d706e	1013	* @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
bogdanm	82:6473597d706e	1014	*
bogdanm	82:6473597d706e	1015	* This bit controls whether the single entry buffer is enabled in response to
bogdanm	82:6473597d706e	1016	* flash read accesses. Its operation is independent from bank 0's cache. A
bogdanm	82:6473597d706e	1017	* high-to-low transition of this enable forces the page buffer to be invalidated.
bogdanm	82:6473597d706e	1018	*
bogdanm	82:6473597d706e	1019	* Values:
bogdanm	82:6473597d706e	1020	* - 0 - Single entry buffer is disabled.
bogdanm	82:6473597d706e	1021	* - 1 - Single entry buffer is enabled.
bogdanm	82:6473597d706e	1022	*/
bogdanm	82:6473597d706e	1023	//@{
bogdanm	82:6473597d706e	1024	#define BP_FMC_PFB1CR_B1SEBE (0U) //!< Bit position for FMC_PFB1CR_B1SEBE.
bogdanm	82:6473597d706e	1025	#define BM_FMC_PFB1CR_B1SEBE (0x00000001U) //!< Bit mask for FMC_PFB1CR_B1SEBE.
bogdanm	82:6473597d706e	1026	#define BS_FMC_PFB1CR_B1SEBE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1SEBE.
bogdanm	82:6473597d706e	1027
bogdanm	82:6473597d706e	1028	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1029	//! @brief Read current value of the FMC_PFB1CR_B1SEBE field.
bogdanm	82:6473597d706e	1030	#define BR_FMC_PFB1CR_B1SEBE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1SEBE))
bogdanm	82:6473597d706e	1031	#endif
bogdanm	82:6473597d706e	1032
bogdanm	82:6473597d706e	1033	//! @brief Format value for bitfield FMC_PFB1CR_B1SEBE.
bogdanm	82:6473597d706e	1034	#define BF_FMC_PFB1CR_B1SEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1SEBE), uint32_t) & BM_FMC_PFB1CR_B1SEBE)
bogdanm	82:6473597d706e	1035
bogdanm	82:6473597d706e	1036	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1037	//! @brief Set the B1SEBE field to a new value.
bogdanm	82:6473597d706e	1038	#define BW_FMC_PFB1CR_B1SEBE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1SEBE) = (v))
bogdanm	82:6473597d706e	1039	#endif
bogdanm	82:6473597d706e	1040	//@}
bogdanm	82:6473597d706e	1041
bogdanm	82:6473597d706e	1042	/*!
bogdanm	82:6473597d706e	1043	* @name Register FMC_PFB1CR, field B1IPE[1] (RW)
bogdanm	82:6473597d706e	1044	*
bogdanm	82:6473597d706e	1045	* This bit controls whether prefetches (or speculative accesses) are initiated
bogdanm	82:6473597d706e	1046	* in response to instruction fetches.
bogdanm	82:6473597d706e	1047	*
bogdanm	82:6473597d706e	1048	* Values:
bogdanm	82:6473597d706e	1049	* - 0 - Do not prefetch in response to instruction fetches.
bogdanm	82:6473597d706e	1050	* - 1 - Enable prefetches in response to instruction fetches.
bogdanm	82:6473597d706e	1051	*/
bogdanm	82:6473597d706e	1052	//@{
bogdanm	82:6473597d706e	1053	#define BP_FMC_PFB1CR_B1IPE (1U) //!< Bit position for FMC_PFB1CR_B1IPE.
bogdanm	82:6473597d706e	1054	#define BM_FMC_PFB1CR_B1IPE (0x00000002U) //!< Bit mask for FMC_PFB1CR_B1IPE.
bogdanm	82:6473597d706e	1055	#define BS_FMC_PFB1CR_B1IPE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1IPE.
bogdanm	82:6473597d706e	1056
bogdanm	82:6473597d706e	1057	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1058	//! @brief Read current value of the FMC_PFB1CR_B1IPE field.
bogdanm	82:6473597d706e	1059	#define BR_FMC_PFB1CR_B1IPE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1IPE))
bogdanm	82:6473597d706e	1060	#endif
bogdanm	82:6473597d706e	1061
bogdanm	82:6473597d706e	1062	//! @brief Format value for bitfield FMC_PFB1CR_B1IPE.
bogdanm	82:6473597d706e	1063	#define BF_FMC_PFB1CR_B1IPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1IPE), uint32_t) & BM_FMC_PFB1CR_B1IPE)
bogdanm	82:6473597d706e	1064
bogdanm	82:6473597d706e	1065	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1066	//! @brief Set the B1IPE field to a new value.
bogdanm	82:6473597d706e	1067	#define BW_FMC_PFB1CR_B1IPE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1IPE) = (v))
bogdanm	82:6473597d706e	1068	#endif
bogdanm	82:6473597d706e	1069	//@}
bogdanm	82:6473597d706e	1070
bogdanm	82:6473597d706e	1071	/*!
bogdanm	82:6473597d706e	1072	* @name Register FMC_PFB1CR, field B1DPE[2] (RW)
bogdanm	82:6473597d706e	1073	*
bogdanm	82:6473597d706e	1074	* This bit controls whether prefetches (or speculative accesses) are initiated
bogdanm	82:6473597d706e	1075	* in response to data references.
bogdanm	82:6473597d706e	1076	*
bogdanm	82:6473597d706e	1077	* Values:
bogdanm	82:6473597d706e	1078	* - 0 - Do not prefetch in response to data references.
bogdanm	82:6473597d706e	1079	* - 1 - Enable prefetches in response to data references.
bogdanm	82:6473597d706e	1080	*/
bogdanm	82:6473597d706e	1081	//@{
bogdanm	82:6473597d706e	1082	#define BP_FMC_PFB1CR_B1DPE (2U) //!< Bit position for FMC_PFB1CR_B1DPE.
bogdanm	82:6473597d706e	1083	#define BM_FMC_PFB1CR_B1DPE (0x00000004U) //!< Bit mask for FMC_PFB1CR_B1DPE.
bogdanm	82:6473597d706e	1084	#define BS_FMC_PFB1CR_B1DPE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1DPE.
bogdanm	82:6473597d706e	1085
bogdanm	82:6473597d706e	1086	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1087	//! @brief Read current value of the FMC_PFB1CR_B1DPE field.
bogdanm	82:6473597d706e	1088	#define BR_FMC_PFB1CR_B1DPE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DPE))
bogdanm	82:6473597d706e	1089	#endif
bogdanm	82:6473597d706e	1090
bogdanm	82:6473597d706e	1091	//! @brief Format value for bitfield FMC_PFB1CR_B1DPE.
bogdanm	82:6473597d706e	1092	#define BF_FMC_PFB1CR_B1DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1DPE), uint32_t) & BM_FMC_PFB1CR_B1DPE)
bogdanm	82:6473597d706e	1093
bogdanm	82:6473597d706e	1094	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1095	//! @brief Set the B1DPE field to a new value.
bogdanm	82:6473597d706e	1096	#define BW_FMC_PFB1CR_B1DPE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DPE) = (v))
bogdanm	82:6473597d706e	1097	#endif
bogdanm	82:6473597d706e	1098	//@}
bogdanm	82:6473597d706e	1099
bogdanm	82:6473597d706e	1100	/*!
bogdanm	82:6473597d706e	1101	* @name Register FMC_PFB1CR, field B1ICE[3] (RW)
bogdanm	82:6473597d706e	1102	*
bogdanm	82:6473597d706e	1103	* This bit controls whether instruction fetches are loaded into the cache.
bogdanm	82:6473597d706e	1104	*
bogdanm	82:6473597d706e	1105	* Values:
bogdanm	82:6473597d706e	1106	* - 0 - Do not cache instruction fetches.
bogdanm	82:6473597d706e	1107	* - 1 - Cache instruction fetches.
bogdanm	82:6473597d706e	1108	*/
bogdanm	82:6473597d706e	1109	//@{
bogdanm	82:6473597d706e	1110	#define BP_FMC_PFB1CR_B1ICE (3U) //!< Bit position for FMC_PFB1CR_B1ICE.
bogdanm	82:6473597d706e	1111	#define BM_FMC_PFB1CR_B1ICE (0x00000008U) //!< Bit mask for FMC_PFB1CR_B1ICE.
bogdanm	82:6473597d706e	1112	#define BS_FMC_PFB1CR_B1ICE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1ICE.
bogdanm	82:6473597d706e	1113
bogdanm	82:6473597d706e	1114	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1115	//! @brief Read current value of the FMC_PFB1CR_B1ICE field.
bogdanm	82:6473597d706e	1116	#define BR_FMC_PFB1CR_B1ICE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1ICE))
bogdanm	82:6473597d706e	1117	#endif
bogdanm	82:6473597d706e	1118
bogdanm	82:6473597d706e	1119	//! @brief Format value for bitfield FMC_PFB1CR_B1ICE.
bogdanm	82:6473597d706e	1120	#define BF_FMC_PFB1CR_B1ICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1ICE), uint32_t) & BM_FMC_PFB1CR_B1ICE)
bogdanm	82:6473597d706e	1121
bogdanm	82:6473597d706e	1122	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1123	//! @brief Set the B1ICE field to a new value.
bogdanm	82:6473597d706e	1124	#define BW_FMC_PFB1CR_B1ICE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1ICE) = (v))
bogdanm	82:6473597d706e	1125	#endif
bogdanm	82:6473597d706e	1126	//@}
bogdanm	82:6473597d706e	1127
bogdanm	82:6473597d706e	1128	/*!
bogdanm	82:6473597d706e	1129	* @name Register FMC_PFB1CR, field B1DCE[4] (RW)
bogdanm	82:6473597d706e	1130	*
bogdanm	82:6473597d706e	1131	* This bit controls whether data references are loaded into the cache.
bogdanm	82:6473597d706e	1132	*
bogdanm	82:6473597d706e	1133	* Values:
bogdanm	82:6473597d706e	1134	* - 0 - Do not cache data references.
bogdanm	82:6473597d706e	1135	* - 1 - Cache data references.
bogdanm	82:6473597d706e	1136	*/
bogdanm	82:6473597d706e	1137	//@{
bogdanm	82:6473597d706e	1138	#define BP_FMC_PFB1CR_B1DCE (4U) //!< Bit position for FMC_PFB1CR_B1DCE.
bogdanm	82:6473597d706e	1139	#define BM_FMC_PFB1CR_B1DCE (0x00000010U) //!< Bit mask for FMC_PFB1CR_B1DCE.
bogdanm	82:6473597d706e	1140	#define BS_FMC_PFB1CR_B1DCE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1DCE.
bogdanm	82:6473597d706e	1141
bogdanm	82:6473597d706e	1142	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1143	//! @brief Read current value of the FMC_PFB1CR_B1DCE field.
bogdanm	82:6473597d706e	1144	#define BR_FMC_PFB1CR_B1DCE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DCE))
bogdanm	82:6473597d706e	1145	#endif
bogdanm	82:6473597d706e	1146
bogdanm	82:6473597d706e	1147	//! @brief Format value for bitfield FMC_PFB1CR_B1DCE.
bogdanm	82:6473597d706e	1148	#define BF_FMC_PFB1CR_B1DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1DCE), uint32_t) & BM_FMC_PFB1CR_B1DCE)
bogdanm	82:6473597d706e	1149
bogdanm	82:6473597d706e	1150	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1151	//! @brief Set the B1DCE field to a new value.
bogdanm	82:6473597d706e	1152	#define BW_FMC_PFB1CR_B1DCE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DCE) = (v))
bogdanm	82:6473597d706e	1153	#endif
bogdanm	82:6473597d706e	1154	//@}
bogdanm	82:6473597d706e	1155
bogdanm	82:6473597d706e	1156	/*!
bogdanm	82:6473597d706e	1157	* @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
bogdanm	82:6473597d706e	1158	*
bogdanm	82:6473597d706e	1159	* This read-only field defines the width of the bank 1 memory.
bogdanm	82:6473597d706e	1160	*
bogdanm	82:6473597d706e	1161	* Values:
bogdanm	82:6473597d706e	1162	* - 00 - 32 bits
bogdanm	82:6473597d706e	1163	* - 01 - 64 bits
bogdanm	82:6473597d706e	1164	* - 10 - 128 bits
bogdanm	82:6473597d706e	1165	* - 11 - Reserved
bogdanm	82:6473597d706e	1166	*/
bogdanm	82:6473597d706e	1167	//@{
bogdanm	82:6473597d706e	1168	#define BP_FMC_PFB1CR_B1MW (17U) //!< Bit position for FMC_PFB1CR_B1MW.
bogdanm	82:6473597d706e	1169	#define BM_FMC_PFB1CR_B1MW (0x00060000U) //!< Bit mask for FMC_PFB1CR_B1MW.
bogdanm	82:6473597d706e	1170	#define BS_FMC_PFB1CR_B1MW (2U) //!< Bit field size in bits for FMC_PFB1CR_B1MW.
bogdanm	82:6473597d706e	1171
bogdanm	82:6473597d706e	1172	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1173	//! @brief Read current value of the FMC_PFB1CR_B1MW field.
bogdanm	82:6473597d706e	1174	#define BR_FMC_PFB1CR_B1MW (HW_FMC_PFB1CR.B.B1MW)
bogdanm	82:6473597d706e	1175	#endif
bogdanm	82:6473597d706e	1176	//@}
bogdanm	82:6473597d706e	1177
bogdanm	82:6473597d706e	1178	/*!
bogdanm	82:6473597d706e	1179	* @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
bogdanm	82:6473597d706e	1180	*
bogdanm	82:6473597d706e	1181	* This read-only field defines the number of wait states required to access the
bogdanm	82:6473597d706e	1182	* bank 1 flash memory. The relationship between the read access time of the
bogdanm	82:6473597d706e	1183	* flash array (expressed in system clock cycles) and RWSC is defined as: Access
bogdanm	82:6473597d706e	1184	* time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
bogdanm	82:6473597d706e	1185	* this value based on the ratio of the system clock speed to the flash clock
bogdanm	82:6473597d706e	1186	* speed. For example, when this ratio is 4:1, the field's value is 3h.
bogdanm	82:6473597d706e	1187	*/
bogdanm	82:6473597d706e	1188	//@{
bogdanm	82:6473597d706e	1189	#define BP_FMC_PFB1CR_B1RWSC (28U) //!< Bit position for FMC_PFB1CR_B1RWSC.
bogdanm	82:6473597d706e	1190	#define BM_FMC_PFB1CR_B1RWSC (0xF0000000U) //!< Bit mask for FMC_PFB1CR_B1RWSC.
bogdanm	82:6473597d706e	1191	#define BS_FMC_PFB1CR_B1RWSC (4U) //!< Bit field size in bits for FMC_PFB1CR_B1RWSC.
bogdanm	82:6473597d706e	1192
bogdanm	82:6473597d706e	1193	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1194	//! @brief Read current value of the FMC_PFB1CR_B1RWSC field.
bogdanm	82:6473597d706e	1195	#define BR_FMC_PFB1CR_B1RWSC (HW_FMC_PFB1CR.B.B1RWSC)
bogdanm	82:6473597d706e	1196	#endif
bogdanm	82:6473597d706e	1197	//@}
bogdanm	82:6473597d706e	1198
bogdanm	82:6473597d706e	1199	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1200	// HW_FMC_TAGVDW0Sn - Cache Tag Storage
bogdanm	82:6473597d706e	1201	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1202
bogdanm	82:6473597d706e	1203	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1204	/*!
bogdanm	82:6473597d706e	1205	* @brief HW_FMC_TAGVDW0Sn - Cache Tag Storage (RW)
bogdanm	82:6473597d706e	1206	*
bogdanm	82:6473597d706e	1207	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1208	*
bogdanm	82:6473597d706e	1209	* The cache is a 4-way, set-associative cache with 4 sets. The ways are
bogdanm	82:6473597d706e	1210	* numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
bogdanm	82:6473597d706e	1211	* denotes the set. This section represents tag/vld information for all sets in the
bogdanm	82:6473597d706e	1212	* indicated way.
bogdanm	82:6473597d706e	1213	*/
bogdanm	82:6473597d706e	1214	typedef union _hw_fmc_tagvdw0sn
bogdanm	82:6473597d706e	1215	{
bogdanm	82:6473597d706e	1216	uint32_t U;
bogdanm	82:6473597d706e	1217	struct _hw_fmc_tagvdw0sn_bitfields
bogdanm	82:6473597d706e	1218	{
bogdanm	82:6473597d706e	1219	uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
bogdanm	82:6473597d706e	1220	uint32_t RESERVED0 : 4; //!< [4:1]
bogdanm	82:6473597d706e	1221	uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
bogdanm	82:6473597d706e	1222	uint32_t RESERVED1 : 13; //!< [31:19]
bogdanm	82:6473597d706e	1223	} B;
bogdanm	82:6473597d706e	1224	} hw_fmc_tagvdw0sn_t;
bogdanm	82:6473597d706e	1225	#endif
bogdanm	82:6473597d706e	1226
bogdanm	82:6473597d706e	1227	/*!
bogdanm	82:6473597d706e	1228	* @name Constants and macros for entire FMC_TAGVDW0Sn register
bogdanm	82:6473597d706e	1229	*/
bogdanm	82:6473597d706e	1230	//@{
bogdanm	82:6473597d706e	1231	#define HW_FMC_TAGVDW0Sn_COUNT (4U)
bogdanm	82:6473597d706e	1232
bogdanm	82:6473597d706e	1233	#define HW_FMC_TAGVDW0Sn_ADDR(n) (REGS_FMC_BASE + 0x100U + (0x4U * n))
bogdanm	82:6473597d706e	1234
bogdanm	82:6473597d706e	1235	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1236	#define HW_FMC_TAGVDW0Sn(n) ((__IO hw_fmc_tagvdw0sn_t ) HW_FMC_TAGVDW0Sn_ADDR(n))
bogdanm	82:6473597d706e	1237	#define HW_FMC_TAGVDW0Sn_RD(n) (HW_FMC_TAGVDW0Sn(n).U)
bogdanm	82:6473597d706e	1238	#define HW_FMC_TAGVDW0Sn_WR(n, v) (HW_FMC_TAGVDW0Sn(n).U = (v))
bogdanm	82:6473597d706e	1239	#define HW_FMC_TAGVDW0Sn_SET(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) \| (v)))
bogdanm	82:6473597d706e	1240	#define HW_FMC_TAGVDW0Sn_CLR(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1241	#define HW_FMC_TAGVDW0Sn_TOG(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1242	#endif
bogdanm	82:6473597d706e	1243	//@}
bogdanm	82:6473597d706e	1244
bogdanm	82:6473597d706e	1245	/*
bogdanm	82:6473597d706e	1246	* Constants & macros for individual FMC_TAGVDW0Sn bitfields
bogdanm	82:6473597d706e	1247	*/
bogdanm	82:6473597d706e	1248
bogdanm	82:6473597d706e	1249	/*!
bogdanm	82:6473597d706e	1250	* @name Register FMC_TAGVDW0Sn, field valid[0] (RW)
bogdanm	82:6473597d706e	1251	*/
bogdanm	82:6473597d706e	1252	//@{
bogdanm	82:6473597d706e	1253	#define BP_FMC_TAGVDW0Sn_valid (0U) //!< Bit position for FMC_TAGVDW0Sn_valid.
bogdanm	82:6473597d706e	1254	#define BM_FMC_TAGVDW0Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW0Sn_valid.
bogdanm	82:6473597d706e	1255	#define BS_FMC_TAGVDW0Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW0Sn_valid.
bogdanm	82:6473597d706e	1256
bogdanm	82:6473597d706e	1257	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1258	//! @brief Read current value of the FMC_TAGVDW0Sn_valid field.
bogdanm	82:6473597d706e	1259	#define BR_FMC_TAGVDW0Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(n), BP_FMC_TAGVDW0Sn_valid))
bogdanm	82:6473597d706e	1260	#endif
bogdanm	82:6473597d706e	1261
bogdanm	82:6473597d706e	1262	//! @brief Format value for bitfield FMC_TAGVDW0Sn_valid.
bogdanm	82:6473597d706e	1263	#define BF_FMC_TAGVDW0Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW0Sn_valid), uint32_t) & BM_FMC_TAGVDW0Sn_valid)
bogdanm	82:6473597d706e	1264
bogdanm	82:6473597d706e	1265	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1266	//! @brief Set the valid field to a new value.
bogdanm	82:6473597d706e	1267	#define BW_FMC_TAGVDW0Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(n), BP_FMC_TAGVDW0Sn_valid) = (v))
bogdanm	82:6473597d706e	1268	#endif
bogdanm	82:6473597d706e	1269	//@}
bogdanm	82:6473597d706e	1270
bogdanm	82:6473597d706e	1271	/*!
bogdanm	82:6473597d706e	1272	* @name Register FMC_TAGVDW0Sn, field tag[18:5] (RW)
bogdanm	82:6473597d706e	1273	*/
bogdanm	82:6473597d706e	1274	//@{
bogdanm	82:6473597d706e	1275	#define BP_FMC_TAGVDW0Sn_tag (5U) //!< Bit position for FMC_TAGVDW0Sn_tag.
bogdanm	82:6473597d706e	1276	#define BM_FMC_TAGVDW0Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW0Sn_tag.
bogdanm	82:6473597d706e	1277	#define BS_FMC_TAGVDW0Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW0Sn_tag.
bogdanm	82:6473597d706e	1278
bogdanm	82:6473597d706e	1279	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1280	//! @brief Read current value of the FMC_TAGVDW0Sn_tag field.
bogdanm	82:6473597d706e	1281	#define BR_FMC_TAGVDW0Sn_tag(n) (HW_FMC_TAGVDW0Sn(n).B.tag)
bogdanm	82:6473597d706e	1282	#endif
bogdanm	82:6473597d706e	1283
bogdanm	82:6473597d706e	1284	//! @brief Format value for bitfield FMC_TAGVDW0Sn_tag.
bogdanm	82:6473597d706e	1285	#define BF_FMC_TAGVDW0Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW0Sn_tag), uint32_t) & BM_FMC_TAGVDW0Sn_tag)
bogdanm	82:6473597d706e	1286
bogdanm	82:6473597d706e	1287	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1288	//! @brief Set the tag field to a new value.
bogdanm	82:6473597d706e	1289	#define BW_FMC_TAGVDW0Sn_tag(n, v) (HW_FMC_TAGVDW0Sn_WR(n, (HW_FMC_TAGVDW0Sn_RD(n) & ~BM_FMC_TAGVDW0Sn_tag) \| BF_FMC_TAGVDW0Sn_tag(v)))
bogdanm	82:6473597d706e	1290	#endif
bogdanm	82:6473597d706e	1291	//@}
bogdanm	82:6473597d706e	1292
bogdanm	82:6473597d706e	1293	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1294	// HW_FMC_TAGVDW1Sn - Cache Tag Storage
bogdanm	82:6473597d706e	1295	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1296
bogdanm	82:6473597d706e	1297	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1298	/*!
bogdanm	82:6473597d706e	1299	* @brief HW_FMC_TAGVDW1Sn - Cache Tag Storage (RW)
bogdanm	82:6473597d706e	1300	*
bogdanm	82:6473597d706e	1301	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1302	*
bogdanm	82:6473597d706e	1303	* The cache is a 4-way, set-associative cache with 4 sets. The ways are
bogdanm	82:6473597d706e	1304	* numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
bogdanm	82:6473597d706e	1305	* denotes the set. This section represents tag/vld information for all sets in the
bogdanm	82:6473597d706e	1306	* indicated way.
bogdanm	82:6473597d706e	1307	*/
bogdanm	82:6473597d706e	1308	typedef union _hw_fmc_tagvdw1sn
bogdanm	82:6473597d706e	1309	{
bogdanm	82:6473597d706e	1310	uint32_t U;
bogdanm	82:6473597d706e	1311	struct _hw_fmc_tagvdw1sn_bitfields
bogdanm	82:6473597d706e	1312	{
bogdanm	82:6473597d706e	1313	uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
bogdanm	82:6473597d706e	1314	uint32_t RESERVED0 : 4; //!< [4:1]
bogdanm	82:6473597d706e	1315	uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
bogdanm	82:6473597d706e	1316	uint32_t RESERVED1 : 13; //!< [31:19]
bogdanm	82:6473597d706e	1317	} B;
bogdanm	82:6473597d706e	1318	} hw_fmc_tagvdw1sn_t;
bogdanm	82:6473597d706e	1319	#endif
bogdanm	82:6473597d706e	1320
bogdanm	82:6473597d706e	1321	/*!
bogdanm	82:6473597d706e	1322	* @name Constants and macros for entire FMC_TAGVDW1Sn register
bogdanm	82:6473597d706e	1323	*/
bogdanm	82:6473597d706e	1324	//@{
bogdanm	82:6473597d706e	1325	#define HW_FMC_TAGVDW1Sn_COUNT (4U)
bogdanm	82:6473597d706e	1326
bogdanm	82:6473597d706e	1327	#define HW_FMC_TAGVDW1Sn_ADDR(n) (REGS_FMC_BASE + 0x110U + (0x4U * n))
bogdanm	82:6473597d706e	1328
bogdanm	82:6473597d706e	1329	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1330	#define HW_FMC_TAGVDW1Sn(n) ((__IO hw_fmc_tagvdw1sn_t ) HW_FMC_TAGVDW1Sn_ADDR(n))
bogdanm	82:6473597d706e	1331	#define HW_FMC_TAGVDW1Sn_RD(n) (HW_FMC_TAGVDW1Sn(n).U)
bogdanm	82:6473597d706e	1332	#define HW_FMC_TAGVDW1Sn_WR(n, v) (HW_FMC_TAGVDW1Sn(n).U = (v))
bogdanm	82:6473597d706e	1333	#define HW_FMC_TAGVDW1Sn_SET(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) \| (v)))
bogdanm	82:6473597d706e	1334	#define HW_FMC_TAGVDW1Sn_CLR(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1335	#define HW_FMC_TAGVDW1Sn_TOG(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1336	#endif
bogdanm	82:6473597d706e	1337	//@}
bogdanm	82:6473597d706e	1338
bogdanm	82:6473597d706e	1339	/*
bogdanm	82:6473597d706e	1340	* Constants & macros for individual FMC_TAGVDW1Sn bitfields
bogdanm	82:6473597d706e	1341	*/
bogdanm	82:6473597d706e	1342
bogdanm	82:6473597d706e	1343	/*!
bogdanm	82:6473597d706e	1344	* @name Register FMC_TAGVDW1Sn, field valid[0] (RW)
bogdanm	82:6473597d706e	1345	*/
bogdanm	82:6473597d706e	1346	//@{
bogdanm	82:6473597d706e	1347	#define BP_FMC_TAGVDW1Sn_valid (0U) //!< Bit position for FMC_TAGVDW1Sn_valid.
bogdanm	82:6473597d706e	1348	#define BM_FMC_TAGVDW1Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW1Sn_valid.
bogdanm	82:6473597d706e	1349	#define BS_FMC_TAGVDW1Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW1Sn_valid.
bogdanm	82:6473597d706e	1350
bogdanm	82:6473597d706e	1351	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1352	//! @brief Read current value of the FMC_TAGVDW1Sn_valid field.
bogdanm	82:6473597d706e	1353	#define BR_FMC_TAGVDW1Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(n), BP_FMC_TAGVDW1Sn_valid))
bogdanm	82:6473597d706e	1354	#endif
bogdanm	82:6473597d706e	1355
bogdanm	82:6473597d706e	1356	//! @brief Format value for bitfield FMC_TAGVDW1Sn_valid.
bogdanm	82:6473597d706e	1357	#define BF_FMC_TAGVDW1Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW1Sn_valid), uint32_t) & BM_FMC_TAGVDW1Sn_valid)
bogdanm	82:6473597d706e	1358
bogdanm	82:6473597d706e	1359	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1360	//! @brief Set the valid field to a new value.
bogdanm	82:6473597d706e	1361	#define BW_FMC_TAGVDW1Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(n), BP_FMC_TAGVDW1Sn_valid) = (v))
bogdanm	82:6473597d706e	1362	#endif
bogdanm	82:6473597d706e	1363	//@}
bogdanm	82:6473597d706e	1364
bogdanm	82:6473597d706e	1365	/*!
bogdanm	82:6473597d706e	1366	* @name Register FMC_TAGVDW1Sn, field tag[18:5] (RW)
bogdanm	82:6473597d706e	1367	*/
bogdanm	82:6473597d706e	1368	//@{
bogdanm	82:6473597d706e	1369	#define BP_FMC_TAGVDW1Sn_tag (5U) //!< Bit position for FMC_TAGVDW1Sn_tag.
bogdanm	82:6473597d706e	1370	#define BM_FMC_TAGVDW1Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW1Sn_tag.
bogdanm	82:6473597d706e	1371	#define BS_FMC_TAGVDW1Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW1Sn_tag.
bogdanm	82:6473597d706e	1372
bogdanm	82:6473597d706e	1373	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1374	//! @brief Read current value of the FMC_TAGVDW1Sn_tag field.
bogdanm	82:6473597d706e	1375	#define BR_FMC_TAGVDW1Sn_tag(n) (HW_FMC_TAGVDW1Sn(n).B.tag)
bogdanm	82:6473597d706e	1376	#endif
bogdanm	82:6473597d706e	1377
bogdanm	82:6473597d706e	1378	//! @brief Format value for bitfield FMC_TAGVDW1Sn_tag.
bogdanm	82:6473597d706e	1379	#define BF_FMC_TAGVDW1Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW1Sn_tag), uint32_t) & BM_FMC_TAGVDW1Sn_tag)
bogdanm	82:6473597d706e	1380
bogdanm	82:6473597d706e	1381	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1382	//! @brief Set the tag field to a new value.
bogdanm	82:6473597d706e	1383	#define BW_FMC_TAGVDW1Sn_tag(n, v) (HW_FMC_TAGVDW1Sn_WR(n, (HW_FMC_TAGVDW1Sn_RD(n) & ~BM_FMC_TAGVDW1Sn_tag) \| BF_FMC_TAGVDW1Sn_tag(v)))
bogdanm	82:6473597d706e	1384	#endif
bogdanm	82:6473597d706e	1385	//@}
bogdanm	82:6473597d706e	1386
bogdanm	82:6473597d706e	1387	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1388	// HW_FMC_TAGVDW2Sn - Cache Tag Storage
bogdanm	82:6473597d706e	1389	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1390
bogdanm	82:6473597d706e	1391	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1392	/*!
bogdanm	82:6473597d706e	1393	* @brief HW_FMC_TAGVDW2Sn - Cache Tag Storage (RW)
bogdanm	82:6473597d706e	1394	*
bogdanm	82:6473597d706e	1395	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1396	*
bogdanm	82:6473597d706e	1397	* The cache is a 4-way, set-associative cache with 4 sets. The ways are
bogdanm	82:6473597d706e	1398	* numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
bogdanm	82:6473597d706e	1399	* denotes the set. This section represents tag/vld information for all sets in the
bogdanm	82:6473597d706e	1400	* indicated way.
bogdanm	82:6473597d706e	1401	*/
bogdanm	82:6473597d706e	1402	typedef union _hw_fmc_tagvdw2sn
bogdanm	82:6473597d706e	1403	{
bogdanm	82:6473597d706e	1404	uint32_t U;
bogdanm	82:6473597d706e	1405	struct _hw_fmc_tagvdw2sn_bitfields
bogdanm	82:6473597d706e	1406	{
bogdanm	82:6473597d706e	1407	uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
bogdanm	82:6473597d706e	1408	uint32_t RESERVED0 : 4; //!< [4:1]
bogdanm	82:6473597d706e	1409	uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
bogdanm	82:6473597d706e	1410	uint32_t RESERVED1 : 13; //!< [31:19]
bogdanm	82:6473597d706e	1411	} B;
bogdanm	82:6473597d706e	1412	} hw_fmc_tagvdw2sn_t;
bogdanm	82:6473597d706e	1413	#endif
bogdanm	82:6473597d706e	1414
bogdanm	82:6473597d706e	1415	/*!
bogdanm	82:6473597d706e	1416	* @name Constants and macros for entire FMC_TAGVDW2Sn register
bogdanm	82:6473597d706e	1417	*/
bogdanm	82:6473597d706e	1418	//@{
bogdanm	82:6473597d706e	1419	#define HW_FMC_TAGVDW2Sn_COUNT (4U)
bogdanm	82:6473597d706e	1420
bogdanm	82:6473597d706e	1421	#define HW_FMC_TAGVDW2Sn_ADDR(n) (REGS_FMC_BASE + 0x120U + (0x4U * n))
bogdanm	82:6473597d706e	1422
bogdanm	82:6473597d706e	1423	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1424	#define HW_FMC_TAGVDW2Sn(n) ((__IO hw_fmc_tagvdw2sn_t ) HW_FMC_TAGVDW2Sn_ADDR(n))
bogdanm	82:6473597d706e	1425	#define HW_FMC_TAGVDW2Sn_RD(n) (HW_FMC_TAGVDW2Sn(n).U)
bogdanm	82:6473597d706e	1426	#define HW_FMC_TAGVDW2Sn_WR(n, v) (HW_FMC_TAGVDW2Sn(n).U = (v))
bogdanm	82:6473597d706e	1427	#define HW_FMC_TAGVDW2Sn_SET(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) \| (v)))
bogdanm	82:6473597d706e	1428	#define HW_FMC_TAGVDW2Sn_CLR(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1429	#define HW_FMC_TAGVDW2Sn_TOG(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1430	#endif
bogdanm	82:6473597d706e	1431	//@}
bogdanm	82:6473597d706e	1432
bogdanm	82:6473597d706e	1433	/*
bogdanm	82:6473597d706e	1434	* Constants & macros for individual FMC_TAGVDW2Sn bitfields
bogdanm	82:6473597d706e	1435	*/
bogdanm	82:6473597d706e	1436
bogdanm	82:6473597d706e	1437	/*!
bogdanm	82:6473597d706e	1438	* @name Register FMC_TAGVDW2Sn, field valid[0] (RW)
bogdanm	82:6473597d706e	1439	*/
bogdanm	82:6473597d706e	1440	//@{
bogdanm	82:6473597d706e	1441	#define BP_FMC_TAGVDW2Sn_valid (0U) //!< Bit position for FMC_TAGVDW2Sn_valid.
bogdanm	82:6473597d706e	1442	#define BM_FMC_TAGVDW2Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW2Sn_valid.
bogdanm	82:6473597d706e	1443	#define BS_FMC_TAGVDW2Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW2Sn_valid.
bogdanm	82:6473597d706e	1444
bogdanm	82:6473597d706e	1445	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1446	//! @brief Read current value of the FMC_TAGVDW2Sn_valid field.
bogdanm	82:6473597d706e	1447	#define BR_FMC_TAGVDW2Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(n), BP_FMC_TAGVDW2Sn_valid))
bogdanm	82:6473597d706e	1448	#endif
bogdanm	82:6473597d706e	1449
bogdanm	82:6473597d706e	1450	//! @brief Format value for bitfield FMC_TAGVDW2Sn_valid.
bogdanm	82:6473597d706e	1451	#define BF_FMC_TAGVDW2Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW2Sn_valid), uint32_t) & BM_FMC_TAGVDW2Sn_valid)
bogdanm	82:6473597d706e	1452
bogdanm	82:6473597d706e	1453	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1454	//! @brief Set the valid field to a new value.
bogdanm	82:6473597d706e	1455	#define BW_FMC_TAGVDW2Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(n), BP_FMC_TAGVDW2Sn_valid) = (v))
bogdanm	82:6473597d706e	1456	#endif
bogdanm	82:6473597d706e	1457	//@}
bogdanm	82:6473597d706e	1458
bogdanm	82:6473597d706e	1459	/*!
bogdanm	82:6473597d706e	1460	* @name Register FMC_TAGVDW2Sn, field tag[18:5] (RW)
bogdanm	82:6473597d706e	1461	*/
bogdanm	82:6473597d706e	1462	//@{
bogdanm	82:6473597d706e	1463	#define BP_FMC_TAGVDW2Sn_tag (5U) //!< Bit position for FMC_TAGVDW2Sn_tag.
bogdanm	82:6473597d706e	1464	#define BM_FMC_TAGVDW2Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW2Sn_tag.
bogdanm	82:6473597d706e	1465	#define BS_FMC_TAGVDW2Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW2Sn_tag.
bogdanm	82:6473597d706e	1466
bogdanm	82:6473597d706e	1467	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1468	//! @brief Read current value of the FMC_TAGVDW2Sn_tag field.
bogdanm	82:6473597d706e	1469	#define BR_FMC_TAGVDW2Sn_tag(n) (HW_FMC_TAGVDW2Sn(n).B.tag)
bogdanm	82:6473597d706e	1470	#endif
bogdanm	82:6473597d706e	1471
bogdanm	82:6473597d706e	1472	//! @brief Format value for bitfield FMC_TAGVDW2Sn_tag.
bogdanm	82:6473597d706e	1473	#define BF_FMC_TAGVDW2Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW2Sn_tag), uint32_t) & BM_FMC_TAGVDW2Sn_tag)
bogdanm	82:6473597d706e	1474
bogdanm	82:6473597d706e	1475	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1476	//! @brief Set the tag field to a new value.
bogdanm	82:6473597d706e	1477	#define BW_FMC_TAGVDW2Sn_tag(n, v) (HW_FMC_TAGVDW2Sn_WR(n, (HW_FMC_TAGVDW2Sn_RD(n) & ~BM_FMC_TAGVDW2Sn_tag) \| BF_FMC_TAGVDW2Sn_tag(v)))
bogdanm	82:6473597d706e	1478	#endif
bogdanm	82:6473597d706e	1479	//@}
bogdanm	82:6473597d706e	1480
bogdanm	82:6473597d706e	1481	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1482	// HW_FMC_TAGVDW3Sn - Cache Tag Storage
bogdanm	82:6473597d706e	1483	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1484
bogdanm	82:6473597d706e	1485	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1486	/*!
bogdanm	82:6473597d706e	1487	* @brief HW_FMC_TAGVDW3Sn - Cache Tag Storage (RW)
bogdanm	82:6473597d706e	1488	*
bogdanm	82:6473597d706e	1489	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1490	*
bogdanm	82:6473597d706e	1491	* The cache is a 4-way, set-associative cache with 4 sets. The ways are
bogdanm	82:6473597d706e	1492	* numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
bogdanm	82:6473597d706e	1493	* denotes the set. This section represents tag/vld information for all sets in the
bogdanm	82:6473597d706e	1494	* indicated way.
bogdanm	82:6473597d706e	1495	*/
bogdanm	82:6473597d706e	1496	typedef union _hw_fmc_tagvdw3sn
bogdanm	82:6473597d706e	1497	{
bogdanm	82:6473597d706e	1498	uint32_t U;
bogdanm	82:6473597d706e	1499	struct _hw_fmc_tagvdw3sn_bitfields
bogdanm	82:6473597d706e	1500	{
bogdanm	82:6473597d706e	1501	uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
bogdanm	82:6473597d706e	1502	uint32_t RESERVED0 : 4; //!< [4:1]
bogdanm	82:6473597d706e	1503	uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
bogdanm	82:6473597d706e	1504	uint32_t RESERVED1 : 13; //!< [31:19]
bogdanm	82:6473597d706e	1505	} B;
bogdanm	82:6473597d706e	1506	} hw_fmc_tagvdw3sn_t;
bogdanm	82:6473597d706e	1507	#endif
bogdanm	82:6473597d706e	1508
bogdanm	82:6473597d706e	1509	/*!
bogdanm	82:6473597d706e	1510	* @name Constants and macros for entire FMC_TAGVDW3Sn register
bogdanm	82:6473597d706e	1511	*/
bogdanm	82:6473597d706e	1512	//@{
bogdanm	82:6473597d706e	1513	#define HW_FMC_TAGVDW3Sn_COUNT (4U)
bogdanm	82:6473597d706e	1514
bogdanm	82:6473597d706e	1515	#define HW_FMC_TAGVDW3Sn_ADDR(n) (REGS_FMC_BASE + 0x130U + (0x4U * n))
bogdanm	82:6473597d706e	1516
bogdanm	82:6473597d706e	1517	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1518	#define HW_FMC_TAGVDW3Sn(n) ((__IO hw_fmc_tagvdw3sn_t ) HW_FMC_TAGVDW3Sn_ADDR(n))
bogdanm	82:6473597d706e	1519	#define HW_FMC_TAGVDW3Sn_RD(n) (HW_FMC_TAGVDW3Sn(n).U)
bogdanm	82:6473597d706e	1520	#define HW_FMC_TAGVDW3Sn_WR(n, v) (HW_FMC_TAGVDW3Sn(n).U = (v))
bogdanm	82:6473597d706e	1521	#define HW_FMC_TAGVDW3Sn_SET(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) \| (v)))
bogdanm	82:6473597d706e	1522	#define HW_FMC_TAGVDW3Sn_CLR(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1523	#define HW_FMC_TAGVDW3Sn_TOG(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1524	#endif
bogdanm	82:6473597d706e	1525	//@}
bogdanm	82:6473597d706e	1526
bogdanm	82:6473597d706e	1527	/*
bogdanm	82:6473597d706e	1528	* Constants & macros for individual FMC_TAGVDW3Sn bitfields
bogdanm	82:6473597d706e	1529	*/
bogdanm	82:6473597d706e	1530
bogdanm	82:6473597d706e	1531	/*!
bogdanm	82:6473597d706e	1532	* @name Register FMC_TAGVDW3Sn, field valid[0] (RW)
bogdanm	82:6473597d706e	1533	*/
bogdanm	82:6473597d706e	1534	//@{
bogdanm	82:6473597d706e	1535	#define BP_FMC_TAGVDW3Sn_valid (0U) //!< Bit position for FMC_TAGVDW3Sn_valid.
bogdanm	82:6473597d706e	1536	#define BM_FMC_TAGVDW3Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW3Sn_valid.
bogdanm	82:6473597d706e	1537	#define BS_FMC_TAGVDW3Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW3Sn_valid.
bogdanm	82:6473597d706e	1538
bogdanm	82:6473597d706e	1539	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1540	//! @brief Read current value of the FMC_TAGVDW3Sn_valid field.
bogdanm	82:6473597d706e	1541	#define BR_FMC_TAGVDW3Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(n), BP_FMC_TAGVDW3Sn_valid))
bogdanm	82:6473597d706e	1542	#endif
bogdanm	82:6473597d706e	1543
bogdanm	82:6473597d706e	1544	//! @brief Format value for bitfield FMC_TAGVDW3Sn_valid.
bogdanm	82:6473597d706e	1545	#define BF_FMC_TAGVDW3Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW3Sn_valid), uint32_t) & BM_FMC_TAGVDW3Sn_valid)
bogdanm	82:6473597d706e	1546
bogdanm	82:6473597d706e	1547	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1548	//! @brief Set the valid field to a new value.
bogdanm	82:6473597d706e	1549	#define BW_FMC_TAGVDW3Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(n), BP_FMC_TAGVDW3Sn_valid) = (v))
bogdanm	82:6473597d706e	1550	#endif
bogdanm	82:6473597d706e	1551	//@}
bogdanm	82:6473597d706e	1552
bogdanm	82:6473597d706e	1553	/*!
bogdanm	82:6473597d706e	1554	* @name Register FMC_TAGVDW3Sn, field tag[18:5] (RW)
bogdanm	82:6473597d706e	1555	*/
bogdanm	82:6473597d706e	1556	//@{
bogdanm	82:6473597d706e	1557	#define BP_FMC_TAGVDW3Sn_tag (5U) //!< Bit position for FMC_TAGVDW3Sn_tag.
bogdanm	82:6473597d706e	1558	#define BM_FMC_TAGVDW3Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW3Sn_tag.
bogdanm	82:6473597d706e	1559	#define BS_FMC_TAGVDW3Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW3Sn_tag.
bogdanm	82:6473597d706e	1560
bogdanm	82:6473597d706e	1561	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1562	//! @brief Read current value of the FMC_TAGVDW3Sn_tag field.
bogdanm	82:6473597d706e	1563	#define BR_FMC_TAGVDW3Sn_tag(n) (HW_FMC_TAGVDW3Sn(n).B.tag)
bogdanm	82:6473597d706e	1564	#endif
bogdanm	82:6473597d706e	1565
bogdanm	82:6473597d706e	1566	//! @brief Format value for bitfield FMC_TAGVDW3Sn_tag.
bogdanm	82:6473597d706e	1567	#define BF_FMC_TAGVDW3Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW3Sn_tag), uint32_t) & BM_FMC_TAGVDW3Sn_tag)
bogdanm	82:6473597d706e	1568
bogdanm	82:6473597d706e	1569	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1570	//! @brief Set the tag field to a new value.
bogdanm	82:6473597d706e	1571	#define BW_FMC_TAGVDW3Sn_tag(n, v) (HW_FMC_TAGVDW3Sn_WR(n, (HW_FMC_TAGVDW3Sn_RD(n) & ~BM_FMC_TAGVDW3Sn_tag) \| BF_FMC_TAGVDW3Sn_tag(v)))
bogdanm	82:6473597d706e	1572	#endif
bogdanm	82:6473597d706e	1573	//@}
bogdanm	82:6473597d706e	1574
bogdanm	82:6473597d706e	1575	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1576	// HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
bogdanm	82:6473597d706e	1577	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1578
bogdanm	82:6473597d706e	1579	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1580	/*!
bogdanm	82:6473597d706e	1581	* @brief HW_FMC_DATAW0SnU - Cache Data Storage (upper word) (RW)
bogdanm	82:6473597d706e	1582	*
bogdanm	82:6473597d706e	1583	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1584	*
bogdanm	82:6473597d706e	1585	* The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
bogdanm	82:6473597d706e	1586	* The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
bogdanm	82:6473597d706e	1587	* DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
bogdanm	82:6473597d706e	1588	* lower word, respectively. This section represents data for the upper word (bits
bogdanm	82:6473597d706e	1589	* [63:32]) of all sets in the indicated way.
bogdanm	82:6473597d706e	1590	*/
bogdanm	82:6473597d706e	1591	typedef union _hw_fmc_dataw0snu
bogdanm	82:6473597d706e	1592	{
bogdanm	82:6473597d706e	1593	uint32_t U;
bogdanm	82:6473597d706e	1594	struct _hw_fmc_dataw0snu_bitfields
bogdanm	82:6473597d706e	1595	{
bogdanm	82:6473597d706e	1596	uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
bogdanm	82:6473597d706e	1597	} B;
bogdanm	82:6473597d706e	1598	} hw_fmc_dataw0snu_t;
bogdanm	82:6473597d706e	1599	#endif
bogdanm	82:6473597d706e	1600
bogdanm	82:6473597d706e	1601	/*!
bogdanm	82:6473597d706e	1602	* @name Constants and macros for entire FMC_DATAW0SnU register
bogdanm	82:6473597d706e	1603	*/
bogdanm	82:6473597d706e	1604	//@{
bogdanm	82:6473597d706e	1605	#define HW_FMC_DATAW0SnU_COUNT (4U)
bogdanm	82:6473597d706e	1606
bogdanm	82:6473597d706e	1607	#define HW_FMC_DATAW0SnU_ADDR(n) (REGS_FMC_BASE + 0x200U + (0x8U * n))
bogdanm	82:6473597d706e	1608
bogdanm	82:6473597d706e	1609	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1610	#define HW_FMC_DATAW0SnU(n) ((__IO hw_fmc_dataw0snu_t ) HW_FMC_DATAW0SnU_ADDR(n))
bogdanm	82:6473597d706e	1611	#define HW_FMC_DATAW0SnU_RD(n) (HW_FMC_DATAW0SnU(n).U)
bogdanm	82:6473597d706e	1612	#define HW_FMC_DATAW0SnU_WR(n, v) (HW_FMC_DATAW0SnU(n).U = (v))
bogdanm	82:6473597d706e	1613	#define HW_FMC_DATAW0SnU_SET(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) \| (v)))
bogdanm	82:6473597d706e	1614	#define HW_FMC_DATAW0SnU_CLR(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1615	#define HW_FMC_DATAW0SnU_TOG(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1616	#endif
bogdanm	82:6473597d706e	1617	//@}
bogdanm	82:6473597d706e	1618
bogdanm	82:6473597d706e	1619	/*
bogdanm	82:6473597d706e	1620	* Constants & macros for individual FMC_DATAW0SnU bitfields
bogdanm	82:6473597d706e	1621	*/
bogdanm	82:6473597d706e	1622
bogdanm	82:6473597d706e	1623	/*!
bogdanm	82:6473597d706e	1624	* @name Register FMC_DATAW0SnU, field data[31:0] (RW)
bogdanm	82:6473597d706e	1625	*/
bogdanm	82:6473597d706e	1626	//@{
bogdanm	82:6473597d706e	1627	#define BP_FMC_DATAW0SnU_data (0U) //!< Bit position for FMC_DATAW0SnU_data.
bogdanm	82:6473597d706e	1628	#define BM_FMC_DATAW0SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW0SnU_data.
bogdanm	82:6473597d706e	1629	#define BS_FMC_DATAW0SnU_data (32U) //!< Bit field size in bits for FMC_DATAW0SnU_data.
bogdanm	82:6473597d706e	1630
bogdanm	82:6473597d706e	1631	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1632	//! @brief Read current value of the FMC_DATAW0SnU_data field.
bogdanm	82:6473597d706e	1633	#define BR_FMC_DATAW0SnU_data(n) (HW_FMC_DATAW0SnU(n).U)
bogdanm	82:6473597d706e	1634	#endif
bogdanm	82:6473597d706e	1635
bogdanm	82:6473597d706e	1636	//! @brief Format value for bitfield FMC_DATAW0SnU_data.
bogdanm	82:6473597d706e	1637	#define BF_FMC_DATAW0SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW0SnU_data), uint32_t) & BM_FMC_DATAW0SnU_data)
bogdanm	82:6473597d706e	1638
bogdanm	82:6473597d706e	1639	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1640	//! @brief Set the data field to a new value.
bogdanm	82:6473597d706e	1641	#define BW_FMC_DATAW0SnU_data(n, v) (HW_FMC_DATAW0SnU_WR(n, v))
bogdanm	82:6473597d706e	1642	#endif
bogdanm	82:6473597d706e	1643	//@}
bogdanm	82:6473597d706e	1644	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1645	// HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
bogdanm	82:6473597d706e	1646	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1647
bogdanm	82:6473597d706e	1648	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1649	/*!
bogdanm	82:6473597d706e	1650	* @brief HW_FMC_DATAW0SnL - Cache Data Storage (lower word) (RW)
bogdanm	82:6473597d706e	1651	*
bogdanm	82:6473597d706e	1652	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1653	*
bogdanm	82:6473597d706e	1654	* The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
bogdanm	82:6473597d706e	1655	* The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
bogdanm	82:6473597d706e	1656	* DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
bogdanm	82:6473597d706e	1657	* lower word, respectively. This section represents data for the lower word (bits
bogdanm	82:6473597d706e	1658	* [31:0]) of all sets in the indicated way.
bogdanm	82:6473597d706e	1659	*/
bogdanm	82:6473597d706e	1660	typedef union _hw_fmc_dataw0snl
bogdanm	82:6473597d706e	1661	{
bogdanm	82:6473597d706e	1662	uint32_t U;
bogdanm	82:6473597d706e	1663	struct _hw_fmc_dataw0snl_bitfields
bogdanm	82:6473597d706e	1664	{
bogdanm	82:6473597d706e	1665	uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
bogdanm	82:6473597d706e	1666	} B;
bogdanm	82:6473597d706e	1667	} hw_fmc_dataw0snl_t;
bogdanm	82:6473597d706e	1668	#endif
bogdanm	82:6473597d706e	1669
bogdanm	82:6473597d706e	1670	/*!
bogdanm	82:6473597d706e	1671	* @name Constants and macros for entire FMC_DATAW0SnL register
bogdanm	82:6473597d706e	1672	*/
bogdanm	82:6473597d706e	1673	//@{
bogdanm	82:6473597d706e	1674	#define HW_FMC_DATAW0SnL_COUNT (4U)
bogdanm	82:6473597d706e	1675
bogdanm	82:6473597d706e	1676	#define HW_FMC_DATAW0SnL_ADDR(n) (REGS_FMC_BASE + 0x204U + (0x8U * n))
bogdanm	82:6473597d706e	1677
bogdanm	82:6473597d706e	1678	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1679	#define HW_FMC_DATAW0SnL(n) ((__IO hw_fmc_dataw0snl_t ) HW_FMC_DATAW0SnL_ADDR(n))
bogdanm	82:6473597d706e	1680	#define HW_FMC_DATAW0SnL_RD(n) (HW_FMC_DATAW0SnL(n).U)
bogdanm	82:6473597d706e	1681	#define HW_FMC_DATAW0SnL_WR(n, v) (HW_FMC_DATAW0SnL(n).U = (v))
bogdanm	82:6473597d706e	1682	#define HW_FMC_DATAW0SnL_SET(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) \| (v)))
bogdanm	82:6473597d706e	1683	#define HW_FMC_DATAW0SnL_CLR(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1684	#define HW_FMC_DATAW0SnL_TOG(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1685	#endif
bogdanm	82:6473597d706e	1686	//@}
bogdanm	82:6473597d706e	1687
bogdanm	82:6473597d706e	1688	/*
bogdanm	82:6473597d706e	1689	* Constants & macros for individual FMC_DATAW0SnL bitfields
bogdanm	82:6473597d706e	1690	*/
bogdanm	82:6473597d706e	1691
bogdanm	82:6473597d706e	1692	/*!
bogdanm	82:6473597d706e	1693	* @name Register FMC_DATAW0SnL, field data[31:0] (RW)
bogdanm	82:6473597d706e	1694	*/
bogdanm	82:6473597d706e	1695	//@{
bogdanm	82:6473597d706e	1696	#define BP_FMC_DATAW0SnL_data (0U) //!< Bit position for FMC_DATAW0SnL_data.
bogdanm	82:6473597d706e	1697	#define BM_FMC_DATAW0SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW0SnL_data.
bogdanm	82:6473597d706e	1698	#define BS_FMC_DATAW0SnL_data (32U) //!< Bit field size in bits for FMC_DATAW0SnL_data.
bogdanm	82:6473597d706e	1699
bogdanm	82:6473597d706e	1700	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1701	//! @brief Read current value of the FMC_DATAW0SnL_data field.
bogdanm	82:6473597d706e	1702	#define BR_FMC_DATAW0SnL_data(n) (HW_FMC_DATAW0SnL(n).U)
bogdanm	82:6473597d706e	1703	#endif
bogdanm	82:6473597d706e	1704
bogdanm	82:6473597d706e	1705	//! @brief Format value for bitfield FMC_DATAW0SnL_data.
bogdanm	82:6473597d706e	1706	#define BF_FMC_DATAW0SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW0SnL_data), uint32_t) & BM_FMC_DATAW0SnL_data)
bogdanm	82:6473597d706e	1707
bogdanm	82:6473597d706e	1708	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1709	//! @brief Set the data field to a new value.
bogdanm	82:6473597d706e	1710	#define BW_FMC_DATAW0SnL_data(n, v) (HW_FMC_DATAW0SnL_WR(n, v))
bogdanm	82:6473597d706e	1711	#endif
bogdanm	82:6473597d706e	1712	//@}
bogdanm	82:6473597d706e	1713
bogdanm	82:6473597d706e	1714	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1715	// HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
bogdanm	82:6473597d706e	1716	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1717
bogdanm	82:6473597d706e	1718	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1719	/*!
bogdanm	82:6473597d706e	1720	* @brief HW_FMC_DATAW1SnU - Cache Data Storage (upper word) (RW)
bogdanm	82:6473597d706e	1721	*
bogdanm	82:6473597d706e	1722	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1723	*
bogdanm	82:6473597d706e	1724	* The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
bogdanm	82:6473597d706e	1725	* The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
bogdanm	82:6473597d706e	1726	* DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
bogdanm	82:6473597d706e	1727	* lower word, respectively. This section represents data for the upper word (bits
bogdanm	82:6473597d706e	1728	* [63:32]) of all sets in the indicated way.
bogdanm	82:6473597d706e	1729	*/
bogdanm	82:6473597d706e	1730	typedef union _hw_fmc_dataw1snu
bogdanm	82:6473597d706e	1731	{
bogdanm	82:6473597d706e	1732	uint32_t U;
bogdanm	82:6473597d706e	1733	struct _hw_fmc_dataw1snu_bitfields
bogdanm	82:6473597d706e	1734	{
bogdanm	82:6473597d706e	1735	uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
bogdanm	82:6473597d706e	1736	} B;
bogdanm	82:6473597d706e	1737	} hw_fmc_dataw1snu_t;
bogdanm	82:6473597d706e	1738	#endif
bogdanm	82:6473597d706e	1739
bogdanm	82:6473597d706e	1740	/*!
bogdanm	82:6473597d706e	1741	* @name Constants and macros for entire FMC_DATAW1SnU register
bogdanm	82:6473597d706e	1742	*/
bogdanm	82:6473597d706e	1743	//@{
bogdanm	82:6473597d706e	1744	#define HW_FMC_DATAW1SnU_COUNT (4U)
bogdanm	82:6473597d706e	1745
bogdanm	82:6473597d706e	1746	#define HW_FMC_DATAW1SnU_ADDR(n) (REGS_FMC_BASE + 0x220U + (0x8U * n))
bogdanm	82:6473597d706e	1747
bogdanm	82:6473597d706e	1748	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1749	#define HW_FMC_DATAW1SnU(n) ((__IO hw_fmc_dataw1snu_t ) HW_FMC_DATAW1SnU_ADDR(n))
bogdanm	82:6473597d706e	1750	#define HW_FMC_DATAW1SnU_RD(n) (HW_FMC_DATAW1SnU(n).U)
bogdanm	82:6473597d706e	1751	#define HW_FMC_DATAW1SnU_WR(n, v) (HW_FMC_DATAW1SnU(n).U = (v))
bogdanm	82:6473597d706e	1752	#define HW_FMC_DATAW1SnU_SET(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) \| (v)))
bogdanm	82:6473597d706e	1753	#define HW_FMC_DATAW1SnU_CLR(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1754	#define HW_FMC_DATAW1SnU_TOG(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1755	#endif
bogdanm	82:6473597d706e	1756	//@}
bogdanm	82:6473597d706e	1757
bogdanm	82:6473597d706e	1758	/*
bogdanm	82:6473597d706e	1759	* Constants & macros for individual FMC_DATAW1SnU bitfields
bogdanm	82:6473597d706e	1760	*/
bogdanm	82:6473597d706e	1761
bogdanm	82:6473597d706e	1762	/*!
bogdanm	82:6473597d706e	1763	* @name Register FMC_DATAW1SnU, field data[31:0] (RW)
bogdanm	82:6473597d706e	1764	*/
bogdanm	82:6473597d706e	1765	//@{
bogdanm	82:6473597d706e	1766	#define BP_FMC_DATAW1SnU_data (0U) //!< Bit position for FMC_DATAW1SnU_data.
bogdanm	82:6473597d706e	1767	#define BM_FMC_DATAW1SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW1SnU_data.
bogdanm	82:6473597d706e	1768	#define BS_FMC_DATAW1SnU_data (32U) //!< Bit field size in bits for FMC_DATAW1SnU_data.
bogdanm	82:6473597d706e	1769
bogdanm	82:6473597d706e	1770	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1771	//! @brief Read current value of the FMC_DATAW1SnU_data field.
bogdanm	82:6473597d706e	1772	#define BR_FMC_DATAW1SnU_data(n) (HW_FMC_DATAW1SnU(n).U)
bogdanm	82:6473597d706e	1773	#endif
bogdanm	82:6473597d706e	1774
bogdanm	82:6473597d706e	1775	//! @brief Format value for bitfield FMC_DATAW1SnU_data.
bogdanm	82:6473597d706e	1776	#define BF_FMC_DATAW1SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW1SnU_data), uint32_t) & BM_FMC_DATAW1SnU_data)
bogdanm	82:6473597d706e	1777
bogdanm	82:6473597d706e	1778	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1779	//! @brief Set the data field to a new value.
bogdanm	82:6473597d706e	1780	#define BW_FMC_DATAW1SnU_data(n, v) (HW_FMC_DATAW1SnU_WR(n, v))
bogdanm	82:6473597d706e	1781	#endif
bogdanm	82:6473597d706e	1782	//@}
bogdanm	82:6473597d706e	1783	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1784	// HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
bogdanm	82:6473597d706e	1785	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1786
bogdanm	82:6473597d706e	1787	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1788	/*!
bogdanm	82:6473597d706e	1789	* @brief HW_FMC_DATAW1SnL - Cache Data Storage (lower word) (RW)
bogdanm	82:6473597d706e	1790	*
bogdanm	82:6473597d706e	1791	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1792	*
bogdanm	82:6473597d706e	1793	* The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
bogdanm	82:6473597d706e	1794	* The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
bogdanm	82:6473597d706e	1795	* DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
bogdanm	82:6473597d706e	1796	* lower word, respectively. This section represents data for the lower word (bits
bogdanm	82:6473597d706e	1797	* [31:0]) of all sets in the indicated way.
bogdanm	82:6473597d706e	1798	*/
bogdanm	82:6473597d706e	1799	typedef union _hw_fmc_dataw1snl
bogdanm	82:6473597d706e	1800	{
bogdanm	82:6473597d706e	1801	uint32_t U;
bogdanm	82:6473597d706e	1802	struct _hw_fmc_dataw1snl_bitfields
bogdanm	82:6473597d706e	1803	{
bogdanm	82:6473597d706e	1804	uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
bogdanm	82:6473597d706e	1805	} B;
bogdanm	82:6473597d706e	1806	} hw_fmc_dataw1snl_t;
bogdanm	82:6473597d706e	1807	#endif
bogdanm	82:6473597d706e	1808
bogdanm	82:6473597d706e	1809	/*!
bogdanm	82:6473597d706e	1810	* @name Constants and macros for entire FMC_DATAW1SnL register
bogdanm	82:6473597d706e	1811	*/
bogdanm	82:6473597d706e	1812	//@{
bogdanm	82:6473597d706e	1813	#define HW_FMC_DATAW1SnL_COUNT (4U)
bogdanm	82:6473597d706e	1814
bogdanm	82:6473597d706e	1815	#define HW_FMC_DATAW1SnL_ADDR(n) (REGS_FMC_BASE + 0x224U + (0x8U * n))
bogdanm	82:6473597d706e	1816
bogdanm	82:6473597d706e	1817	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1818	#define HW_FMC_DATAW1SnL(n) ((__IO hw_fmc_dataw1snl_t ) HW_FMC_DATAW1SnL_ADDR(n))
bogdanm	82:6473597d706e	1819	#define HW_FMC_DATAW1SnL_RD(n) (HW_FMC_DATAW1SnL(n).U)
bogdanm	82:6473597d706e	1820	#define HW_FMC_DATAW1SnL_WR(n, v) (HW_FMC_DATAW1SnL(n).U = (v))
bogdanm	82:6473597d706e	1821	#define HW_FMC_DATAW1SnL_SET(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) \| (v)))
bogdanm	82:6473597d706e	1822	#define HW_FMC_DATAW1SnL_CLR(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1823	#define HW_FMC_DATAW1SnL_TOG(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1824	#endif
bogdanm	82:6473597d706e	1825	//@}
bogdanm	82:6473597d706e	1826
bogdanm	82:6473597d706e	1827	/*
bogdanm	82:6473597d706e	1828	* Constants & macros for individual FMC_DATAW1SnL bitfields
bogdanm	82:6473597d706e	1829	*/
bogdanm	82:6473597d706e	1830
bogdanm	82:6473597d706e	1831	/*!
bogdanm	82:6473597d706e	1832	* @name Register FMC_DATAW1SnL, field data[31:0] (RW)
bogdanm	82:6473597d706e	1833	*/
bogdanm	82:6473597d706e	1834	//@{
bogdanm	82:6473597d706e	1835	#define BP_FMC_DATAW1SnL_data (0U) //!< Bit position for FMC_DATAW1SnL_data.
bogdanm	82:6473597d706e	1836	#define BM_FMC_DATAW1SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW1SnL_data.
bogdanm	82:6473597d706e	1837	#define BS_FMC_DATAW1SnL_data (32U) //!< Bit field size in bits for FMC_DATAW1SnL_data.
bogdanm	82:6473597d706e	1838
bogdanm	82:6473597d706e	1839	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1840	//! @brief Read current value of the FMC_DATAW1SnL_data field.
bogdanm	82:6473597d706e	1841	#define BR_FMC_DATAW1SnL_data(n) (HW_FMC_DATAW1SnL(n).U)
bogdanm	82:6473597d706e	1842	#endif
bogdanm	82:6473597d706e	1843
bogdanm	82:6473597d706e	1844	//! @brief Format value for bitfield FMC_DATAW1SnL_data.
bogdanm	82:6473597d706e	1845	#define BF_FMC_DATAW1SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW1SnL_data), uint32_t) & BM_FMC_DATAW1SnL_data)
bogdanm	82:6473597d706e	1846
bogdanm	82:6473597d706e	1847	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1848	//! @brief Set the data field to a new value.
bogdanm	82:6473597d706e	1849	#define BW_FMC_DATAW1SnL_data(n, v) (HW_FMC_DATAW1SnL_WR(n, v))
bogdanm	82:6473597d706e	1850	#endif
bogdanm	82:6473597d706e	1851	//@}
bogdanm	82:6473597d706e	1852
bogdanm	82:6473597d706e	1853	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1854	// HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
bogdanm	82:6473597d706e	1855	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1856
bogdanm	82:6473597d706e	1857	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1858	/*!
bogdanm	82:6473597d706e	1859	* @brief HW_FMC_DATAW2SnU - Cache Data Storage (upper word) (RW)
bogdanm	82:6473597d706e	1860	*
bogdanm	82:6473597d706e	1861	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1862	*
bogdanm	82:6473597d706e	1863	* The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
bogdanm	82:6473597d706e	1864	* The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
bogdanm	82:6473597d706e	1865	* DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
bogdanm	82:6473597d706e	1866	* lower word, respectively. This section represents data for the upper word (bits
bogdanm	82:6473597d706e	1867	* [63:32]) of all sets in the indicated way.
bogdanm	82:6473597d706e	1868	*/
bogdanm	82:6473597d706e	1869	typedef union _hw_fmc_dataw2snu
bogdanm	82:6473597d706e	1870	{
bogdanm	82:6473597d706e	1871	uint32_t U;
bogdanm	82:6473597d706e	1872	struct _hw_fmc_dataw2snu_bitfields
bogdanm	82:6473597d706e	1873	{
bogdanm	82:6473597d706e	1874	uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
bogdanm	82:6473597d706e	1875	} B;
bogdanm	82:6473597d706e	1876	} hw_fmc_dataw2snu_t;
bogdanm	82:6473597d706e	1877	#endif
bogdanm	82:6473597d706e	1878
bogdanm	82:6473597d706e	1879	/*!
bogdanm	82:6473597d706e	1880	* @name Constants and macros for entire FMC_DATAW2SnU register
bogdanm	82:6473597d706e	1881	*/
bogdanm	82:6473597d706e	1882	//@{
bogdanm	82:6473597d706e	1883	#define HW_FMC_DATAW2SnU_COUNT (4U)
bogdanm	82:6473597d706e	1884
bogdanm	82:6473597d706e	1885	#define HW_FMC_DATAW2SnU_ADDR(n) (REGS_FMC_BASE + 0x240U + (0x8U * n))
bogdanm	82:6473597d706e	1886
bogdanm	82:6473597d706e	1887	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1888	#define HW_FMC_DATAW2SnU(n) ((__IO hw_fmc_dataw2snu_t ) HW_FMC_DATAW2SnU_ADDR(n))
bogdanm	82:6473597d706e	1889	#define HW_FMC_DATAW2SnU_RD(n) (HW_FMC_DATAW2SnU(n).U)
bogdanm	82:6473597d706e	1890	#define HW_FMC_DATAW2SnU_WR(n, v) (HW_FMC_DATAW2SnU(n).U = (v))
bogdanm	82:6473597d706e	1891	#define HW_FMC_DATAW2SnU_SET(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) \| (v)))
bogdanm	82:6473597d706e	1892	#define HW_FMC_DATAW2SnU_CLR(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1893	#define HW_FMC_DATAW2SnU_TOG(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1894	#endif
bogdanm	82:6473597d706e	1895	//@}
bogdanm	82:6473597d706e	1896
bogdanm	82:6473597d706e	1897	/*
bogdanm	82:6473597d706e	1898	* Constants & macros for individual FMC_DATAW2SnU bitfields
bogdanm	82:6473597d706e	1899	*/
bogdanm	82:6473597d706e	1900
bogdanm	82:6473597d706e	1901	/*!
bogdanm	82:6473597d706e	1902	* @name Register FMC_DATAW2SnU, field data[31:0] (RW)
bogdanm	82:6473597d706e	1903	*/
bogdanm	82:6473597d706e	1904	//@{
bogdanm	82:6473597d706e	1905	#define BP_FMC_DATAW2SnU_data (0U) //!< Bit position for FMC_DATAW2SnU_data.
bogdanm	82:6473597d706e	1906	#define BM_FMC_DATAW2SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW2SnU_data.
bogdanm	82:6473597d706e	1907	#define BS_FMC_DATAW2SnU_data (32U) //!< Bit field size in bits for FMC_DATAW2SnU_data.
bogdanm	82:6473597d706e	1908
bogdanm	82:6473597d706e	1909	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1910	//! @brief Read current value of the FMC_DATAW2SnU_data field.
bogdanm	82:6473597d706e	1911	#define BR_FMC_DATAW2SnU_data(n) (HW_FMC_DATAW2SnU(n).U)
bogdanm	82:6473597d706e	1912	#endif
bogdanm	82:6473597d706e	1913
bogdanm	82:6473597d706e	1914	//! @brief Format value for bitfield FMC_DATAW2SnU_data.
bogdanm	82:6473597d706e	1915	#define BF_FMC_DATAW2SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW2SnU_data), uint32_t) & BM_FMC_DATAW2SnU_data)
bogdanm	82:6473597d706e	1916
bogdanm	82:6473597d706e	1917	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1918	//! @brief Set the data field to a new value.
bogdanm	82:6473597d706e	1919	#define BW_FMC_DATAW2SnU_data(n, v) (HW_FMC_DATAW2SnU_WR(n, v))
bogdanm	82:6473597d706e	1920	#endif
bogdanm	82:6473597d706e	1921	//@}
bogdanm	82:6473597d706e	1922	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1923	// HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
bogdanm	82:6473597d706e	1924	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1925
bogdanm	82:6473597d706e	1926	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1927	/*!
bogdanm	82:6473597d706e	1928	* @brief HW_FMC_DATAW2SnL - Cache Data Storage (lower word) (RW)
bogdanm	82:6473597d706e	1929	*
bogdanm	82:6473597d706e	1930	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1931	*
bogdanm	82:6473597d706e	1932	* The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
bogdanm	82:6473597d706e	1933	* The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
bogdanm	82:6473597d706e	1934	* DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
bogdanm	82:6473597d706e	1935	* lower word, respectively. This section represents data for the lower word (bits
bogdanm	82:6473597d706e	1936	* [31:0]) of all sets in the indicated way.
bogdanm	82:6473597d706e	1937	*/
bogdanm	82:6473597d706e	1938	typedef union _hw_fmc_dataw2snl
bogdanm	82:6473597d706e	1939	{
bogdanm	82:6473597d706e	1940	uint32_t U;
bogdanm	82:6473597d706e	1941	struct _hw_fmc_dataw2snl_bitfields
bogdanm	82:6473597d706e	1942	{
bogdanm	82:6473597d706e	1943	uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
bogdanm	82:6473597d706e	1944	} B;
bogdanm	82:6473597d706e	1945	} hw_fmc_dataw2snl_t;
bogdanm	82:6473597d706e	1946	#endif
bogdanm	82:6473597d706e	1947
bogdanm	82:6473597d706e	1948	/*!
bogdanm	82:6473597d706e	1949	* @name Constants and macros for entire FMC_DATAW2SnL register
bogdanm	82:6473597d706e	1950	*/
bogdanm	82:6473597d706e	1951	//@{
bogdanm	82:6473597d706e	1952	#define HW_FMC_DATAW2SnL_COUNT (4U)
bogdanm	82:6473597d706e	1953
bogdanm	82:6473597d706e	1954	#define HW_FMC_DATAW2SnL_ADDR(n) (REGS_FMC_BASE + 0x244U + (0x8U * n))
bogdanm	82:6473597d706e	1955
bogdanm	82:6473597d706e	1956	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1957	#define HW_FMC_DATAW2SnL(n) ((__IO hw_fmc_dataw2snl_t ) HW_FMC_DATAW2SnL_ADDR(n))
bogdanm	82:6473597d706e	1958	#define HW_FMC_DATAW2SnL_RD(n) (HW_FMC_DATAW2SnL(n).U)
bogdanm	82:6473597d706e	1959	#define HW_FMC_DATAW2SnL_WR(n, v) (HW_FMC_DATAW2SnL(n).U = (v))
bogdanm	82:6473597d706e	1960	#define HW_FMC_DATAW2SnL_SET(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) \| (v)))
bogdanm	82:6473597d706e	1961	#define HW_FMC_DATAW2SnL_CLR(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) & ~(v)))
bogdanm	82:6473597d706e	1962	#define HW_FMC_DATAW2SnL_TOG(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) ^ (v)))
bogdanm	82:6473597d706e	1963	#endif
bogdanm	82:6473597d706e	1964	//@}
bogdanm	82:6473597d706e	1965
bogdanm	82:6473597d706e	1966	/*
bogdanm	82:6473597d706e	1967	* Constants & macros for individual FMC_DATAW2SnL bitfields
bogdanm	82:6473597d706e	1968	*/
bogdanm	82:6473597d706e	1969
bogdanm	82:6473597d706e	1970	/*!
bogdanm	82:6473597d706e	1971	* @name Register FMC_DATAW2SnL, field data[31:0] (RW)
bogdanm	82:6473597d706e	1972	*/
bogdanm	82:6473597d706e	1973	//@{
bogdanm	82:6473597d706e	1974	#define BP_FMC_DATAW2SnL_data (0U) //!< Bit position for FMC_DATAW2SnL_data.
bogdanm	82:6473597d706e	1975	#define BM_FMC_DATAW2SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW2SnL_data.
bogdanm	82:6473597d706e	1976	#define BS_FMC_DATAW2SnL_data (32U) //!< Bit field size in bits for FMC_DATAW2SnL_data.
bogdanm	82:6473597d706e	1977
bogdanm	82:6473597d706e	1978	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1979	//! @brief Read current value of the FMC_DATAW2SnL_data field.
bogdanm	82:6473597d706e	1980	#define BR_FMC_DATAW2SnL_data(n) (HW_FMC_DATAW2SnL(n).U)
bogdanm	82:6473597d706e	1981	#endif
bogdanm	82:6473597d706e	1982
bogdanm	82:6473597d706e	1983	//! @brief Format value for bitfield FMC_DATAW2SnL_data.
bogdanm	82:6473597d706e	1984	#define BF_FMC_DATAW2SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW2SnL_data), uint32_t) & BM_FMC_DATAW2SnL_data)
bogdanm	82:6473597d706e	1985
bogdanm	82:6473597d706e	1986	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1987	//! @brief Set the data field to a new value.
bogdanm	82:6473597d706e	1988	#define BW_FMC_DATAW2SnL_data(n, v) (HW_FMC_DATAW2SnL_WR(n, v))
bogdanm	82:6473597d706e	1989	#endif
bogdanm	82:6473597d706e	1990	//@}
bogdanm	82:6473597d706e	1991
bogdanm	82:6473597d706e	1992	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1993	// HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
bogdanm	82:6473597d706e	1994	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1995
bogdanm	82:6473597d706e	1996	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1997	/*!
bogdanm	82:6473597d706e	1998	* @brief HW_FMC_DATAW3SnU - Cache Data Storage (upper word) (RW)
bogdanm	82:6473597d706e	1999	*
bogdanm	82:6473597d706e	2000	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2001	*
bogdanm	82:6473597d706e	2002	* The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
bogdanm	82:6473597d706e	2003	* The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
bogdanm	82:6473597d706e	2004	* DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
bogdanm	82:6473597d706e	2005	* lower word, respectively. This section represents data for the upper word (bits
bogdanm	82:6473597d706e	2006	* [63:32]) of all sets in the indicated way.
bogdanm	82:6473597d706e	2007	*/
bogdanm	82:6473597d706e	2008	typedef union _hw_fmc_dataw3snu
bogdanm	82:6473597d706e	2009	{
bogdanm	82:6473597d706e	2010	uint32_t U;
bogdanm	82:6473597d706e	2011	struct _hw_fmc_dataw3snu_bitfields
bogdanm	82:6473597d706e	2012	{
bogdanm	82:6473597d706e	2013	uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
bogdanm	82:6473597d706e	2014	} B;
bogdanm	82:6473597d706e	2015	} hw_fmc_dataw3snu_t;
bogdanm	82:6473597d706e	2016	#endif
bogdanm	82:6473597d706e	2017
bogdanm	82:6473597d706e	2018	/*!
bogdanm	82:6473597d706e	2019	* @name Constants and macros for entire FMC_DATAW3SnU register
bogdanm	82:6473597d706e	2020	*/
bogdanm	82:6473597d706e	2021	//@{
bogdanm	82:6473597d706e	2022	#define HW_FMC_DATAW3SnU_COUNT (4U)
bogdanm	82:6473597d706e	2023
bogdanm	82:6473597d706e	2024	#define HW_FMC_DATAW3SnU_ADDR(n) (REGS_FMC_BASE + 0x260U + (0x8U * n))
bogdanm	82:6473597d706e	2025
bogdanm	82:6473597d706e	2026	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2027	#define HW_FMC_DATAW3SnU(n) ((__IO hw_fmc_dataw3snu_t ) HW_FMC_DATAW3SnU_ADDR(n))
bogdanm	82:6473597d706e	2028	#define HW_FMC_DATAW3SnU_RD(n) (HW_FMC_DATAW3SnU(n).U)
bogdanm	82:6473597d706e	2029	#define HW_FMC_DATAW3SnU_WR(n, v) (HW_FMC_DATAW3SnU(n).U = (v))
bogdanm	82:6473597d706e	2030	#define HW_FMC_DATAW3SnU_SET(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) \| (v)))
bogdanm	82:6473597d706e	2031	#define HW_FMC_DATAW3SnU_CLR(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) & ~(v)))
bogdanm	82:6473597d706e	2032	#define HW_FMC_DATAW3SnU_TOG(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) ^ (v)))
bogdanm	82:6473597d706e	2033	#endif
bogdanm	82:6473597d706e	2034	//@}
bogdanm	82:6473597d706e	2035
bogdanm	82:6473597d706e	2036	/*
bogdanm	82:6473597d706e	2037	* Constants & macros for individual FMC_DATAW3SnU bitfields
bogdanm	82:6473597d706e	2038	*/
bogdanm	82:6473597d706e	2039
bogdanm	82:6473597d706e	2040	/*!
bogdanm	82:6473597d706e	2041	* @name Register FMC_DATAW3SnU, field data[31:0] (RW)
bogdanm	82:6473597d706e	2042	*/
bogdanm	82:6473597d706e	2043	//@{
bogdanm	82:6473597d706e	2044	#define BP_FMC_DATAW3SnU_data (0U) //!< Bit position for FMC_DATAW3SnU_data.
bogdanm	82:6473597d706e	2045	#define BM_FMC_DATAW3SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW3SnU_data.
bogdanm	82:6473597d706e	2046	#define BS_FMC_DATAW3SnU_data (32U) //!< Bit field size in bits for FMC_DATAW3SnU_data.
bogdanm	82:6473597d706e	2047
bogdanm	82:6473597d706e	2048	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2049	//! @brief Read current value of the FMC_DATAW3SnU_data field.
bogdanm	82:6473597d706e	2050	#define BR_FMC_DATAW3SnU_data(n) (HW_FMC_DATAW3SnU(n).U)
bogdanm	82:6473597d706e	2051	#endif
bogdanm	82:6473597d706e	2052
bogdanm	82:6473597d706e	2053	//! @brief Format value for bitfield FMC_DATAW3SnU_data.
bogdanm	82:6473597d706e	2054	#define BF_FMC_DATAW3SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW3SnU_data), uint32_t) & BM_FMC_DATAW3SnU_data)
bogdanm	82:6473597d706e	2055
bogdanm	82:6473597d706e	2056	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2057	//! @brief Set the data field to a new value.
bogdanm	82:6473597d706e	2058	#define BW_FMC_DATAW3SnU_data(n, v) (HW_FMC_DATAW3SnU_WR(n, v))
bogdanm	82:6473597d706e	2059	#endif
bogdanm	82:6473597d706e	2060	//@}
bogdanm	82:6473597d706e	2061	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2062	// HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
bogdanm	82:6473597d706e	2063	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2064
bogdanm	82:6473597d706e	2065	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2066	/*!
bogdanm	82:6473597d706e	2067	* @brief HW_FMC_DATAW3SnL - Cache Data Storage (lower word) (RW)
bogdanm	82:6473597d706e	2068	*
bogdanm	82:6473597d706e	2069	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2070	*
bogdanm	82:6473597d706e	2071	* The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
bogdanm	82:6473597d706e	2072	* The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
bogdanm	82:6473597d706e	2073	* DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
bogdanm	82:6473597d706e	2074	* lower word, respectively. This section represents data for the lower word (bits
bogdanm	82:6473597d706e	2075	* [31:0]) of all sets in the indicated way.
bogdanm	82:6473597d706e	2076	*/
bogdanm	82:6473597d706e	2077	typedef union _hw_fmc_dataw3snl
bogdanm	82:6473597d706e	2078	{
bogdanm	82:6473597d706e	2079	uint32_t U;
bogdanm	82:6473597d706e	2080	struct _hw_fmc_dataw3snl_bitfields
bogdanm	82:6473597d706e	2081	{
bogdanm	82:6473597d706e	2082	uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
bogdanm	82:6473597d706e	2083	} B;
bogdanm	82:6473597d706e	2084	} hw_fmc_dataw3snl_t;
bogdanm	82:6473597d706e	2085	#endif
bogdanm	82:6473597d706e	2086
bogdanm	82:6473597d706e	2087	/*!
bogdanm	82:6473597d706e	2088	* @name Constants and macros for entire FMC_DATAW3SnL register
bogdanm	82:6473597d706e	2089	*/
bogdanm	82:6473597d706e	2090	//@{
bogdanm	82:6473597d706e	2091	#define HW_FMC_DATAW3SnL_COUNT (4U)
bogdanm	82:6473597d706e	2092
bogdanm	82:6473597d706e	2093	#define HW_FMC_DATAW3SnL_ADDR(n) (REGS_FMC_BASE + 0x264U + (0x8U * n))
bogdanm	82:6473597d706e	2094
bogdanm	82:6473597d706e	2095	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2096	#define HW_FMC_DATAW3SnL(n) ((__IO hw_fmc_dataw3snl_t ) HW_FMC_DATAW3SnL_ADDR(n))
bogdanm	82:6473597d706e	2097	#define HW_FMC_DATAW3SnL_RD(n) (HW_FMC_DATAW3SnL(n).U)
bogdanm	82:6473597d706e	2098	#define HW_FMC_DATAW3SnL_WR(n, v) (HW_FMC_DATAW3SnL(n).U = (v))
bogdanm	82:6473597d706e	2099	#define HW_FMC_DATAW3SnL_SET(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) \| (v)))
bogdanm	82:6473597d706e	2100	#define HW_FMC_DATAW3SnL_CLR(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) & ~(v)))
bogdanm	82:6473597d706e	2101	#define HW_FMC_DATAW3SnL_TOG(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) ^ (v)))
bogdanm	82:6473597d706e	2102	#endif
bogdanm	82:6473597d706e	2103	//@}
bogdanm	82:6473597d706e	2104
bogdanm	82:6473597d706e	2105	/*
bogdanm	82:6473597d706e	2106	* Constants & macros for individual FMC_DATAW3SnL bitfields
bogdanm	82:6473597d706e	2107	*/
bogdanm	82:6473597d706e	2108
bogdanm	82:6473597d706e	2109	/*!
bogdanm	82:6473597d706e	2110	* @name Register FMC_DATAW3SnL, field data[31:0] (RW)
bogdanm	82:6473597d706e	2111	*/
bogdanm	82:6473597d706e	2112	//@{
bogdanm	82:6473597d706e	2113	#define BP_FMC_DATAW3SnL_data (0U) //!< Bit position for FMC_DATAW3SnL_data.
bogdanm	82:6473597d706e	2114	#define BM_FMC_DATAW3SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW3SnL_data.
bogdanm	82:6473597d706e	2115	#define BS_FMC_DATAW3SnL_data (32U) //!< Bit field size in bits for FMC_DATAW3SnL_data.
bogdanm	82:6473597d706e	2116
bogdanm	82:6473597d706e	2117	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2118	//! @brief Read current value of the FMC_DATAW3SnL_data field.
bogdanm	82:6473597d706e	2119	#define BR_FMC_DATAW3SnL_data(n) (HW_FMC_DATAW3SnL(n).U)
bogdanm	82:6473597d706e	2120	#endif
bogdanm	82:6473597d706e	2121
bogdanm	82:6473597d706e	2122	//! @brief Format value for bitfield FMC_DATAW3SnL_data.
bogdanm	82:6473597d706e	2123	#define BF_FMC_DATAW3SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW3SnL_data), uint32_t) & BM_FMC_DATAW3SnL_data)
bogdanm	82:6473597d706e	2124
bogdanm	82:6473597d706e	2125	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2126	//! @brief Set the data field to a new value.
bogdanm	82:6473597d706e	2127	#define BW_FMC_DATAW3SnL_data(n, v) (HW_FMC_DATAW3SnL_WR(n, v))
bogdanm	82:6473597d706e	2128	#endif
bogdanm	82:6473597d706e	2129	//@}
bogdanm	82:6473597d706e	2130
bogdanm	82:6473597d706e	2131	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2132	// hw_fmc_t - module struct
bogdanm	82:6473597d706e	2133	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2134	/*!
bogdanm	82:6473597d706e	2135	* @brief All FMC module registers.
bogdanm	82:6473597d706e	2136	*/
bogdanm	82:6473597d706e	2137	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2138	#pragma pack(1)
bogdanm	82:6473597d706e	2139	typedef struct _hw_fmc
bogdanm	82:6473597d706e	2140	{
bogdanm	82:6473597d706e	2141	__IO hw_fmc_pfapr_t PFAPR; //!< [0x0] Flash Access Protection Register
bogdanm	82:6473597d706e	2142	__IO hw_fmc_pfb0cr_t PFB0CR; //!< [0x4] Flash Bank 0 Control Register
bogdanm	82:6473597d706e	2143	__IO hw_fmc_pfb1cr_t PFB1CR; //!< [0x8] Flash Bank 1 Control Register
bogdanm	82:6473597d706e	2144	uint8_t _reserved0[244];
bogdanm	82:6473597d706e	2145	__IO hw_fmc_tagvdw0sn_t TAGVDW0Sn[4]; //!< [0x100] Cache Tag Storage
bogdanm	82:6473597d706e	2146	__IO hw_fmc_tagvdw1sn_t TAGVDW1Sn[4]; //!< [0x110] Cache Tag Storage
bogdanm	82:6473597d706e	2147	__IO hw_fmc_tagvdw2sn_t TAGVDW2Sn[4]; //!< [0x120] Cache Tag Storage
bogdanm	82:6473597d706e	2148	__IO hw_fmc_tagvdw3sn_t TAGVDW3Sn[4]; //!< [0x130] Cache Tag Storage
bogdanm	82:6473597d706e	2149	uint8_t _reserved1[192];
bogdanm	82:6473597d706e	2150	struct {
bogdanm	82:6473597d706e	2151	__IO hw_fmc_dataw0snu_t DATAW0SnU; //!< [0x200] Cache Data Storage (upper word)
bogdanm	82:6473597d706e	2152	__IO hw_fmc_dataw0snl_t DATAW0SnL; //!< [0x204] Cache Data Storage (lower word)
bogdanm	82:6473597d706e	2153	} DATAW0Sn[4];
bogdanm	82:6473597d706e	2154	struct {
bogdanm	82:6473597d706e	2155	__IO hw_fmc_dataw1snu_t DATAW1SnU; //!< [0x220] Cache Data Storage (upper word)
bogdanm	82:6473597d706e	2156	__IO hw_fmc_dataw1snl_t DATAW1SnL; //!< [0x224] Cache Data Storage (lower word)
bogdanm	82:6473597d706e	2157	} DATAW1Sn[4];
bogdanm	82:6473597d706e	2158	struct {
bogdanm	82:6473597d706e	2159	__IO hw_fmc_dataw2snu_t DATAW2SnU; //!< [0x240] Cache Data Storage (upper word)
bogdanm	82:6473597d706e	2160	__IO hw_fmc_dataw2snl_t DATAW2SnL; //!< [0x244] Cache Data Storage (lower word)
bogdanm	82:6473597d706e	2161	} DATAW2Sn[4];
bogdanm	82:6473597d706e	2162	struct {
bogdanm	82:6473597d706e	2163	__IO hw_fmc_dataw3snu_t DATAW3SnU; //!< [0x260] Cache Data Storage (upper word)
bogdanm	82:6473597d706e	2164	__IO hw_fmc_dataw3snl_t DATAW3SnL; //!< [0x264] Cache Data Storage (lower word)
bogdanm	82:6473597d706e	2165	} DATAW3Sn[4];
bogdanm	82:6473597d706e	2166	} hw_fmc_t;
bogdanm	82:6473597d706e	2167	#pragma pack()
bogdanm	82:6473597d706e	2168
bogdanm	82:6473597d706e	2169	//! @brief Macro to access all FMC registers.
bogdanm	82:6473597d706e	2170	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	2171	//! use the '&' operator, like <code>&HW_FMC</code>.
bogdanm	82:6473597d706e	2172	#define HW_FMC ((hw_fmc_t ) REGS_FMC_BASE)
bogdanm	82:6473597d706e	2173	#endif
bogdanm	82:6473597d706e	2174
bogdanm	82:6473597d706e	2175	#endif // __HW_FMC_REGISTERS_H__
bogdanm	82:6473597d706e	2176	// v22/130726/0.9
bogdanm	82:6473597d706e	2177	// EOF

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Type:	Library
Created:	25 Jun 2015
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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_fmc.h@89:552587b429a1, 2014-09-12 (annotated)

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