mbed - mbed library

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mbed library

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_enet.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_enet.h@82:6473597d706e

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_ENET_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_ENET_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 ENET
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Ethernet MAC-NET Core
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_ENET_EIR - Interrupt Event Register
bogdanm	82:6473597d706e	33	* - HW_ENET_EIMR - Interrupt Mask Register
bogdanm	82:6473597d706e	34	* - HW_ENET_RDAR - Receive Descriptor Active Register
bogdanm	82:6473597d706e	35	* - HW_ENET_TDAR - Transmit Descriptor Active Register
bogdanm	82:6473597d706e	36	* - HW_ENET_ECR - Ethernet Control Register
bogdanm	82:6473597d706e	37	* - HW_ENET_MMFR - MII Management Frame Register
bogdanm	82:6473597d706e	38	* - HW_ENET_MSCR - MII Speed Control Register
bogdanm	82:6473597d706e	39	* - HW_ENET_MIBC - MIB Control Register
bogdanm	82:6473597d706e	40	* - HW_ENET_RCR - Receive Control Register
bogdanm	82:6473597d706e	41	* - HW_ENET_TCR - Transmit Control Register
bogdanm	82:6473597d706e	42	* - HW_ENET_PALR - Physical Address Lower Register
bogdanm	82:6473597d706e	43	* - HW_ENET_PAUR - Physical Address Upper Register
bogdanm	82:6473597d706e	44	* - HW_ENET_OPD - Opcode/Pause Duration Register
bogdanm	82:6473597d706e	45	* - HW_ENET_IAUR - Descriptor Individual Upper Address Register
bogdanm	82:6473597d706e	46	* - HW_ENET_IALR - Descriptor Individual Lower Address Register
bogdanm	82:6473597d706e	47	* - HW_ENET_GAUR - Descriptor Group Upper Address Register
bogdanm	82:6473597d706e	48	* - HW_ENET_GALR - Descriptor Group Lower Address Register
bogdanm	82:6473597d706e	49	* - HW_ENET_TFWR - Transmit FIFO Watermark Register
bogdanm	82:6473597d706e	50	* - HW_ENET_RDSR - Receive Descriptor Ring Start Register
bogdanm	82:6473597d706e	51	* - HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
bogdanm	82:6473597d706e	52	* - HW_ENET_MRBR - Maximum Receive Buffer Size Register
bogdanm	82:6473597d706e	53	* - HW_ENET_RSFL - Receive FIFO Section Full Threshold
bogdanm	82:6473597d706e	54	* - HW_ENET_RSEM - Receive FIFO Section Empty Threshold
bogdanm	82:6473597d706e	55	* - HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
bogdanm	82:6473597d706e	56	* - HW_ENET_RAFL - Receive FIFO Almost Full Threshold
bogdanm	82:6473597d706e	57	* - HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
bogdanm	82:6473597d706e	58	* - HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
bogdanm	82:6473597d706e	59	* - HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
bogdanm	82:6473597d706e	60	* - HW_ENET_TIPG - Transmit Inter-Packet Gap
bogdanm	82:6473597d706e	61	* - HW_ENET_FTRL - Frame Truncation Length
bogdanm	82:6473597d706e	62	* - HW_ENET_TACC - Transmit Accelerator Function Configuration
bogdanm	82:6473597d706e	63	* - HW_ENET_RACC - Receive Accelerator Function Configuration
bogdanm	82:6473597d706e	64	* - HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
bogdanm	82:6473597d706e	65	* - HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
bogdanm	82:6473597d706e	66	* - HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
bogdanm	82:6473597d706e	67	* - HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
bogdanm	82:6473597d706e	68	* - HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
bogdanm	82:6473597d706e	69	* - HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
bogdanm	82:6473597d706e	70	* - HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
bogdanm	82:6473597d706e	71	* - HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
bogdanm	82:6473597d706e	72	* - HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
bogdanm	82:6473597d706e	73	* - HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
bogdanm	82:6473597d706e	74	* - HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
bogdanm	82:6473597d706e	75	* - HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
bogdanm	82:6473597d706e	76	* - HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
bogdanm	82:6473597d706e	77	* - HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
bogdanm	82:6473597d706e	78	* - HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
bogdanm	82:6473597d706e	79	* - HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
bogdanm	82:6473597d706e	80	* - HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
bogdanm	82:6473597d706e	81	* - HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
bogdanm	82:6473597d706e	82	* - HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
bogdanm	82:6473597d706e	83	* - HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
bogdanm	82:6473597d706e	84	* - HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
bogdanm	82:6473597d706e	85	* - HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
bogdanm	82:6473597d706e	86	* - HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
bogdanm	82:6473597d706e	87	* - HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
bogdanm	82:6473597d706e	88	* - HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
bogdanm	82:6473597d706e	89	* - HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
bogdanm	82:6473597d706e	90	* - HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
bogdanm	82:6473597d706e	91	* - HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
bogdanm	82:6473597d706e	92	* - HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
bogdanm	82:6473597d706e	93	* - HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
bogdanm	82:6473597d706e	94	* - HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
bogdanm	82:6473597d706e	95	* - HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
bogdanm	82:6473597d706e	96	* - HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
bogdanm	82:6473597d706e	97	* - HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
bogdanm	82:6473597d706e	98	* - HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
bogdanm	82:6473597d706e	99	* - HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
bogdanm	82:6473597d706e	100	* - HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
bogdanm	82:6473597d706e	101	* - HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
bogdanm	82:6473597d706e	102	* - HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
bogdanm	82:6473597d706e	103	* - HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
bogdanm	82:6473597d706e	104	* - HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
bogdanm	82:6473597d706e	105	* - HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
bogdanm	82:6473597d706e	106	* - HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
bogdanm	82:6473597d706e	107	* - HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
bogdanm	82:6473597d706e	108	* - HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
bogdanm	82:6473597d706e	109	* - HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
bogdanm	82:6473597d706e	110	* - HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
bogdanm	82:6473597d706e	111	* - HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
bogdanm	82:6473597d706e	112	* - HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
bogdanm	82:6473597d706e	113	* - HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
bogdanm	82:6473597d706e	114	* - HW_ENET_ATCR - Adjustable Timer Control Register
bogdanm	82:6473597d706e	115	* - HW_ENET_ATVR - Timer Value Register
bogdanm	82:6473597d706e	116	* - HW_ENET_ATOFF - Timer Offset Register
bogdanm	82:6473597d706e	117	* - HW_ENET_ATPER - Timer Period Register
bogdanm	82:6473597d706e	118	* - HW_ENET_ATCOR - Timer Correction Register
bogdanm	82:6473597d706e	119	* - HW_ENET_ATINC - Time-Stamping Clock Period Register
bogdanm	82:6473597d706e	120	* - HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
bogdanm	82:6473597d706e	121	* - HW_ENET_TGSR - Timer Global Status Register
bogdanm	82:6473597d706e	122	* - HW_ENET_TCSRn - Timer Control Status Register
bogdanm	82:6473597d706e	123	* - HW_ENET_TCCRn - Timer Compare Capture Register
bogdanm	82:6473597d706e	124	*
bogdanm	82:6473597d706e	125	* - hw_enet_t - Struct containing all module registers.
bogdanm	82:6473597d706e	126	*/
bogdanm	82:6473597d706e	127
bogdanm	82:6473597d706e	128	//! @name Module base addresses
bogdanm	82:6473597d706e	129	//@{
bogdanm	82:6473597d706e	130	#ifndef REGS_ENET_BASE
bogdanm	82:6473597d706e	131	#define HW_ENET_INSTANCE_COUNT (1U) //!< Number of instances of the ENET module.
bogdanm	82:6473597d706e	132	#define HW_ENET0 (0U) //!< Instance number for ENET.
bogdanm	82:6473597d706e	133	#define REGS_ENET0_BASE (0x400C0000U) //!< Base address for ENET.
bogdanm	82:6473597d706e	134
bogdanm	82:6473597d706e	135	//! @brief Table of base addresses for ENET instances.
bogdanm	82:6473597d706e	136	static const uint32_t __g_regs_ENET_base_addresses[] = {
bogdanm	82:6473597d706e	137	REGS_ENET0_BASE,
bogdanm	82:6473597d706e	138	};
bogdanm	82:6473597d706e	139
bogdanm	82:6473597d706e	140	//! @brief Get the base address of ENET by instance number.
bogdanm	82:6473597d706e	141	//! @param x ENET instance number, from 0 through 0.
bogdanm	82:6473597d706e	142	#define REGS_ENET_BASE(x) (__g_regs_ENET_base_addresses[(x)])
bogdanm	82:6473597d706e	143
bogdanm	82:6473597d706e	144	//! @brief Get the instance number given a base address.
bogdanm	82:6473597d706e	145	//! @param b Base address for an instance of ENET.
bogdanm	82:6473597d706e	146	#define REGS_ENET_INSTANCE(b) ((b) == REGS_ENET0_BASE ? HW_ENET0 : 0)
bogdanm	82:6473597d706e	147	#endif
bogdanm	82:6473597d706e	148	//@}
bogdanm	82:6473597d706e	149
bogdanm	82:6473597d706e	150	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	151	// HW_ENET_EIR - Interrupt Event Register
bogdanm	82:6473597d706e	152	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	153
bogdanm	82:6473597d706e	154	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	155	/*!
bogdanm	82:6473597d706e	156	* @brief HW_ENET_EIR - Interrupt Event Register (RW)
bogdanm	82:6473597d706e	157	*
bogdanm	82:6473597d706e	158	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	159	*
bogdanm	82:6473597d706e	160	* When an event occurs that sets a bit in EIR, an interrupt occurs if the
bogdanm	82:6473597d706e	161	* corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
bogdanm	82:6473597d706e	162	* an EIR bit clears it; writing 0 has no effect. This register is cleared upon
bogdanm	82:6473597d706e	163	* hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
bogdanm	82:6473597d706e	164	* corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
bogdanm	82:6473597d706e	165	* Legacy mode does not require these flags to be enabled.
bogdanm	82:6473597d706e	166	*/
bogdanm	82:6473597d706e	167	typedef union _hw_enet_eir
bogdanm	82:6473597d706e	168	{
bogdanm	82:6473597d706e	169	uint32_t U;
bogdanm	82:6473597d706e	170	struct _hw_enet_eir_bitfields
bogdanm	82:6473597d706e	171	{
bogdanm	82:6473597d706e	172	uint32_t RESERVED0 : 15; //!< [14:0]
bogdanm	82:6473597d706e	173	uint32_t TS_TIMER : 1; //!< [15] Timestamp Timer
bogdanm	82:6473597d706e	174	uint32_t TS_AVAIL : 1; //!< [16] Transmit Timestamp Available
bogdanm	82:6473597d706e	175	uint32_t WAKEUP : 1; //!< [17] Node Wakeup Request Indication
bogdanm	82:6473597d706e	176	uint32_t PLR : 1; //!< [18] Payload Receive Error
bogdanm	82:6473597d706e	177	uint32_t UN : 1; //!< [19] Transmit FIFO Underrun
bogdanm	82:6473597d706e	178	uint32_t RL : 1; //!< [20] Collision Retry Limit
bogdanm	82:6473597d706e	179	uint32_t LC : 1; //!< [21] Late Collision
bogdanm	82:6473597d706e	180	uint32_t EBERR : 1; //!< [22] Ethernet Bus Error
bogdanm	82:6473597d706e	181	uint32_t MII : 1; //!< [23] MII Interrupt.
bogdanm	82:6473597d706e	182	uint32_t RXB : 1; //!< [24] Receive Buffer Interrupt
bogdanm	82:6473597d706e	183	uint32_t RXF : 1; //!< [25] Receive Frame Interrupt
bogdanm	82:6473597d706e	184	uint32_t TXB : 1; //!< [26] Transmit Buffer Interrupt
bogdanm	82:6473597d706e	185	uint32_t TXF : 1; //!< [27] Transmit Frame Interrupt
bogdanm	82:6473597d706e	186	uint32_t GRA : 1; //!< [28] Graceful Stop Complete
bogdanm	82:6473597d706e	187	uint32_t BABT : 1; //!< [29] Babbling Transmit Error
bogdanm	82:6473597d706e	188	uint32_t BABR : 1; //!< [30] Babbling Receive Error
bogdanm	82:6473597d706e	189	uint32_t RESERVED1 : 1; //!< [31]
bogdanm	82:6473597d706e	190	} B;
bogdanm	82:6473597d706e	191	} hw_enet_eir_t;
bogdanm	82:6473597d706e	192	#endif
bogdanm	82:6473597d706e	193
bogdanm	82:6473597d706e	194	/*!
bogdanm	82:6473597d706e	195	* @name Constants and macros for entire ENET_EIR register
bogdanm	82:6473597d706e	196	*/
bogdanm	82:6473597d706e	197	//@{
bogdanm	82:6473597d706e	198	#define HW_ENET_EIR_ADDR(x) (REGS_ENET_BASE(x) + 0x4U)
bogdanm	82:6473597d706e	199
bogdanm	82:6473597d706e	200	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	201	#define HW_ENET_EIR(x) ((__IO hw_enet_eir_t ) HW_ENET_EIR_ADDR(x))
bogdanm	82:6473597d706e	202	#define HW_ENET_EIR_RD(x) (HW_ENET_EIR(x).U)
bogdanm	82:6473597d706e	203	#define HW_ENET_EIR_WR(x, v) (HW_ENET_EIR(x).U = (v))
bogdanm	82:6473597d706e	204	#define HW_ENET_EIR_SET(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) \| (v)))
bogdanm	82:6473597d706e	205	#define HW_ENET_EIR_CLR(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	206	#define HW_ENET_EIR_TOG(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	207	#endif
bogdanm	82:6473597d706e	208	//@}
bogdanm	82:6473597d706e	209
bogdanm	82:6473597d706e	210	/*
bogdanm	82:6473597d706e	211	* Constants & macros for individual ENET_EIR bitfields
bogdanm	82:6473597d706e	212	*/
bogdanm	82:6473597d706e	213
bogdanm	82:6473597d706e	214	/*!
bogdanm	82:6473597d706e	215	* @name Register ENET_EIR, field TS_TIMER[15] (W1C)
bogdanm	82:6473597d706e	216	*
bogdanm	82:6473597d706e	217	* The adjustable timer reached the period event. A period event interrupt can
bogdanm	82:6473597d706e	218	* be generated if ATCR[PEREN] is set and the timer wraps according to the
bogdanm	82:6473597d706e	219	* periodic setting in the ATPER register. Set the timer period value before setting
bogdanm	82:6473597d706e	220	* ATCR[PEREN].
bogdanm	82:6473597d706e	221	*/
bogdanm	82:6473597d706e	222	//@{
bogdanm	82:6473597d706e	223	#define BP_ENET_EIR_TS_TIMER (15U) //!< Bit position for ENET_EIR_TS_TIMER.
bogdanm	82:6473597d706e	224	#define BM_ENET_EIR_TS_TIMER (0x00008000U) //!< Bit mask for ENET_EIR_TS_TIMER.
bogdanm	82:6473597d706e	225	#define BS_ENET_EIR_TS_TIMER (1U) //!< Bit field size in bits for ENET_EIR_TS_TIMER.
bogdanm	82:6473597d706e	226
bogdanm	82:6473597d706e	227	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	228	//! @brief Read current value of the ENET_EIR_TS_TIMER field.
bogdanm	82:6473597d706e	229	#define BR_ENET_EIR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER))
bogdanm	82:6473597d706e	230	#endif
bogdanm	82:6473597d706e	231
bogdanm	82:6473597d706e	232	//! @brief Format value for bitfield ENET_EIR_TS_TIMER.
bogdanm	82:6473597d706e	233	#define BF_ENET_EIR_TS_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TS_TIMER), uint32_t) & BM_ENET_EIR_TS_TIMER)
bogdanm	82:6473597d706e	234
bogdanm	82:6473597d706e	235	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	236	//! @brief Set the TS_TIMER field to a new value.
bogdanm	82:6473597d706e	237	#define BW_ENET_EIR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER) = (v))
bogdanm	82:6473597d706e	238	#endif
bogdanm	82:6473597d706e	239	//@}
bogdanm	82:6473597d706e	240
bogdanm	82:6473597d706e	241	/*!
bogdanm	82:6473597d706e	242	* @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
bogdanm	82:6473597d706e	243	*
bogdanm	82:6473597d706e	244	* Indicates that the timestamp of the last transmitted timing frame is
bogdanm	82:6473597d706e	245	* available in the ATSTMP register.
bogdanm	82:6473597d706e	246	*/
bogdanm	82:6473597d706e	247	//@{
bogdanm	82:6473597d706e	248	#define BP_ENET_EIR_TS_AVAIL (16U) //!< Bit position for ENET_EIR_TS_AVAIL.
bogdanm	82:6473597d706e	249	#define BM_ENET_EIR_TS_AVAIL (0x00010000U) //!< Bit mask for ENET_EIR_TS_AVAIL.
bogdanm	82:6473597d706e	250	#define BS_ENET_EIR_TS_AVAIL (1U) //!< Bit field size in bits for ENET_EIR_TS_AVAIL.
bogdanm	82:6473597d706e	251
bogdanm	82:6473597d706e	252	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	253	//! @brief Read current value of the ENET_EIR_TS_AVAIL field.
bogdanm	82:6473597d706e	254	#define BR_ENET_EIR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL))
bogdanm	82:6473597d706e	255	#endif
bogdanm	82:6473597d706e	256
bogdanm	82:6473597d706e	257	//! @brief Format value for bitfield ENET_EIR_TS_AVAIL.
bogdanm	82:6473597d706e	258	#define BF_ENET_EIR_TS_AVAIL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TS_AVAIL), uint32_t) & BM_ENET_EIR_TS_AVAIL)
bogdanm	82:6473597d706e	259
bogdanm	82:6473597d706e	260	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	261	//! @brief Set the TS_AVAIL field to a new value.
bogdanm	82:6473597d706e	262	#define BW_ENET_EIR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL) = (v))
bogdanm	82:6473597d706e	263	#endif
bogdanm	82:6473597d706e	264	//@}
bogdanm	82:6473597d706e	265
bogdanm	82:6473597d706e	266	/*!
bogdanm	82:6473597d706e	267	* @name Register ENET_EIR, field WAKEUP[17] (W1C)
bogdanm	82:6473597d706e	268	*
bogdanm	82:6473597d706e	269	* Read-only status bit to indicate that a magic packet has been detected. Will
bogdanm	82:6473597d706e	270	* act only if ECR[MAGICEN] is set.
bogdanm	82:6473597d706e	271	*/
bogdanm	82:6473597d706e	272	//@{
bogdanm	82:6473597d706e	273	#define BP_ENET_EIR_WAKEUP (17U) //!< Bit position for ENET_EIR_WAKEUP.
bogdanm	82:6473597d706e	274	#define BM_ENET_EIR_WAKEUP (0x00020000U) //!< Bit mask for ENET_EIR_WAKEUP.
bogdanm	82:6473597d706e	275	#define BS_ENET_EIR_WAKEUP (1U) //!< Bit field size in bits for ENET_EIR_WAKEUP.
bogdanm	82:6473597d706e	276
bogdanm	82:6473597d706e	277	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	278	//! @brief Read current value of the ENET_EIR_WAKEUP field.
bogdanm	82:6473597d706e	279	#define BR_ENET_EIR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP))
bogdanm	82:6473597d706e	280	#endif
bogdanm	82:6473597d706e	281
bogdanm	82:6473597d706e	282	//! @brief Format value for bitfield ENET_EIR_WAKEUP.
bogdanm	82:6473597d706e	283	#define BF_ENET_EIR_WAKEUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_WAKEUP), uint32_t) & BM_ENET_EIR_WAKEUP)
bogdanm	82:6473597d706e	284
bogdanm	82:6473597d706e	285	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	286	//! @brief Set the WAKEUP field to a new value.
bogdanm	82:6473597d706e	287	#define BW_ENET_EIR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP) = (v))
bogdanm	82:6473597d706e	288	#endif
bogdanm	82:6473597d706e	289	//@}
bogdanm	82:6473597d706e	290
bogdanm	82:6473597d706e	291	/*!
bogdanm	82:6473597d706e	292	* @name Register ENET_EIR, field PLR[18] (W1C)
bogdanm	82:6473597d706e	293	*
bogdanm	82:6473597d706e	294	* Indicates a frame was received with a payload length error. See Frame
bogdanm	82:6473597d706e	295	* Length/Type Verification: Payload Length Check for more information.
bogdanm	82:6473597d706e	296	*/
bogdanm	82:6473597d706e	297	//@{
bogdanm	82:6473597d706e	298	#define BP_ENET_EIR_PLR (18U) //!< Bit position for ENET_EIR_PLR.
bogdanm	82:6473597d706e	299	#define BM_ENET_EIR_PLR (0x00040000U) //!< Bit mask for ENET_EIR_PLR.
bogdanm	82:6473597d706e	300	#define BS_ENET_EIR_PLR (1U) //!< Bit field size in bits for ENET_EIR_PLR.
bogdanm	82:6473597d706e	301
bogdanm	82:6473597d706e	302	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	303	//! @brief Read current value of the ENET_EIR_PLR field.
bogdanm	82:6473597d706e	304	#define BR_ENET_EIR_PLR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR))
bogdanm	82:6473597d706e	305	#endif
bogdanm	82:6473597d706e	306
bogdanm	82:6473597d706e	307	//! @brief Format value for bitfield ENET_EIR_PLR.
bogdanm	82:6473597d706e	308	#define BF_ENET_EIR_PLR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_PLR), uint32_t) & BM_ENET_EIR_PLR)
bogdanm	82:6473597d706e	309
bogdanm	82:6473597d706e	310	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	311	//! @brief Set the PLR field to a new value.
bogdanm	82:6473597d706e	312	#define BW_ENET_EIR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR) = (v))
bogdanm	82:6473597d706e	313	#endif
bogdanm	82:6473597d706e	314	//@}
bogdanm	82:6473597d706e	315
bogdanm	82:6473597d706e	316	/*!
bogdanm	82:6473597d706e	317	* @name Register ENET_EIR, field UN[19] (W1C)
bogdanm	82:6473597d706e	318	*
bogdanm	82:6473597d706e	319	* Indicates the transmit FIFO became empty before the complete frame was
bogdanm	82:6473597d706e	320	* transmitted. A bad CRC is appended to the frame fragment and the remainder of the
bogdanm	82:6473597d706e	321	* frame is discarded.
bogdanm	82:6473597d706e	322	*/
bogdanm	82:6473597d706e	323	//@{
bogdanm	82:6473597d706e	324	#define BP_ENET_EIR_UN (19U) //!< Bit position for ENET_EIR_UN.
bogdanm	82:6473597d706e	325	#define BM_ENET_EIR_UN (0x00080000U) //!< Bit mask for ENET_EIR_UN.
bogdanm	82:6473597d706e	326	#define BS_ENET_EIR_UN (1U) //!< Bit field size in bits for ENET_EIR_UN.
bogdanm	82:6473597d706e	327
bogdanm	82:6473597d706e	328	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	329	//! @brief Read current value of the ENET_EIR_UN field.
bogdanm	82:6473597d706e	330	#define BR_ENET_EIR_UN(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN))
bogdanm	82:6473597d706e	331	#endif
bogdanm	82:6473597d706e	332
bogdanm	82:6473597d706e	333	//! @brief Format value for bitfield ENET_EIR_UN.
bogdanm	82:6473597d706e	334	#define BF_ENET_EIR_UN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_UN), uint32_t) & BM_ENET_EIR_UN)
bogdanm	82:6473597d706e	335
bogdanm	82:6473597d706e	336	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	337	//! @brief Set the UN field to a new value.
bogdanm	82:6473597d706e	338	#define BW_ENET_EIR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN) = (v))
bogdanm	82:6473597d706e	339	#endif
bogdanm	82:6473597d706e	340	//@}
bogdanm	82:6473597d706e	341
bogdanm	82:6473597d706e	342	/*!
bogdanm	82:6473597d706e	343	* @name Register ENET_EIR, field RL[20] (W1C)
bogdanm	82:6473597d706e	344	*
bogdanm	82:6473597d706e	345	* Indicates a collision occurred on each of 16 successive attempts to transmit
bogdanm	82:6473597d706e	346	* the frame. The frame is discarded without being transmitted and transmission
bogdanm	82:6473597d706e	347	* of the next frame commences. This error can only occur in half-duplex mode.
bogdanm	82:6473597d706e	348	*/
bogdanm	82:6473597d706e	349	//@{
bogdanm	82:6473597d706e	350	#define BP_ENET_EIR_RL (20U) //!< Bit position for ENET_EIR_RL.
bogdanm	82:6473597d706e	351	#define BM_ENET_EIR_RL (0x00100000U) //!< Bit mask for ENET_EIR_RL.
bogdanm	82:6473597d706e	352	#define BS_ENET_EIR_RL (1U) //!< Bit field size in bits for ENET_EIR_RL.
bogdanm	82:6473597d706e	353
bogdanm	82:6473597d706e	354	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	355	//! @brief Read current value of the ENET_EIR_RL field.
bogdanm	82:6473597d706e	356	#define BR_ENET_EIR_RL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL))
bogdanm	82:6473597d706e	357	#endif
bogdanm	82:6473597d706e	358
bogdanm	82:6473597d706e	359	//! @brief Format value for bitfield ENET_EIR_RL.
bogdanm	82:6473597d706e	360	#define BF_ENET_EIR_RL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RL), uint32_t) & BM_ENET_EIR_RL)
bogdanm	82:6473597d706e	361
bogdanm	82:6473597d706e	362	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	363	//! @brief Set the RL field to a new value.
bogdanm	82:6473597d706e	364	#define BW_ENET_EIR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL) = (v))
bogdanm	82:6473597d706e	365	#endif
bogdanm	82:6473597d706e	366	//@}
bogdanm	82:6473597d706e	367
bogdanm	82:6473597d706e	368	/*!
bogdanm	82:6473597d706e	369	* @name Register ENET_EIR, field LC[21] (W1C)
bogdanm	82:6473597d706e	370	*
bogdanm	82:6473597d706e	371	* Indicates a collision occurred beyond the collision window (slot time) in
bogdanm	82:6473597d706e	372	* half-duplex mode. The frame truncates with a bad CRC and the remainder of the
bogdanm	82:6473597d706e	373	* frame is discarded.
bogdanm	82:6473597d706e	374	*/
bogdanm	82:6473597d706e	375	//@{
bogdanm	82:6473597d706e	376	#define BP_ENET_EIR_LC (21U) //!< Bit position for ENET_EIR_LC.
bogdanm	82:6473597d706e	377	#define BM_ENET_EIR_LC (0x00200000U) //!< Bit mask for ENET_EIR_LC.
bogdanm	82:6473597d706e	378	#define BS_ENET_EIR_LC (1U) //!< Bit field size in bits for ENET_EIR_LC.
bogdanm	82:6473597d706e	379
bogdanm	82:6473597d706e	380	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	381	//! @brief Read current value of the ENET_EIR_LC field.
bogdanm	82:6473597d706e	382	#define BR_ENET_EIR_LC(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC))
bogdanm	82:6473597d706e	383	#endif
bogdanm	82:6473597d706e	384
bogdanm	82:6473597d706e	385	//! @brief Format value for bitfield ENET_EIR_LC.
bogdanm	82:6473597d706e	386	#define BF_ENET_EIR_LC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_LC), uint32_t) & BM_ENET_EIR_LC)
bogdanm	82:6473597d706e	387
bogdanm	82:6473597d706e	388	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	389	//! @brief Set the LC field to a new value.
bogdanm	82:6473597d706e	390	#define BW_ENET_EIR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC) = (v))
bogdanm	82:6473597d706e	391	#endif
bogdanm	82:6473597d706e	392	//@}
bogdanm	82:6473597d706e	393
bogdanm	82:6473597d706e	394	/*!
bogdanm	82:6473597d706e	395	* @name Register ENET_EIR, field EBERR[22] (W1C)
bogdanm	82:6473597d706e	396	*
bogdanm	82:6473597d706e	397	* Indicates a system bus error occurred when a uDMA transaction is underway.
bogdanm	82:6473597d706e	398	* When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
bogdanm	82:6473597d706e	399	* MAC. When this occurs, software must ensure proper actions, possibly resetting
bogdanm	82:6473597d706e	400	* the system, to resume normal operation.
bogdanm	82:6473597d706e	401	*/
bogdanm	82:6473597d706e	402	//@{
bogdanm	82:6473597d706e	403	#define BP_ENET_EIR_EBERR (22U) //!< Bit position for ENET_EIR_EBERR.
bogdanm	82:6473597d706e	404	#define BM_ENET_EIR_EBERR (0x00400000U) //!< Bit mask for ENET_EIR_EBERR.
bogdanm	82:6473597d706e	405	#define BS_ENET_EIR_EBERR (1U) //!< Bit field size in bits for ENET_EIR_EBERR.
bogdanm	82:6473597d706e	406
bogdanm	82:6473597d706e	407	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	408	//! @brief Read current value of the ENET_EIR_EBERR field.
bogdanm	82:6473597d706e	409	#define BR_ENET_EIR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR))
bogdanm	82:6473597d706e	410	#endif
bogdanm	82:6473597d706e	411
bogdanm	82:6473597d706e	412	//! @brief Format value for bitfield ENET_EIR_EBERR.
bogdanm	82:6473597d706e	413	#define BF_ENET_EIR_EBERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_EBERR), uint32_t) & BM_ENET_EIR_EBERR)
bogdanm	82:6473597d706e	414
bogdanm	82:6473597d706e	415	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	416	//! @brief Set the EBERR field to a new value.
bogdanm	82:6473597d706e	417	#define BW_ENET_EIR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR) = (v))
bogdanm	82:6473597d706e	418	#endif
bogdanm	82:6473597d706e	419	//@}
bogdanm	82:6473597d706e	420
bogdanm	82:6473597d706e	421	/*!
bogdanm	82:6473597d706e	422	* @name Register ENET_EIR, field MII[23] (W1C)
bogdanm	82:6473597d706e	423	*
bogdanm	82:6473597d706e	424	* Indicates that the MII has completed the data transfer requested.
bogdanm	82:6473597d706e	425	*/
bogdanm	82:6473597d706e	426	//@{
bogdanm	82:6473597d706e	427	#define BP_ENET_EIR_MII (23U) //!< Bit position for ENET_EIR_MII.
bogdanm	82:6473597d706e	428	#define BM_ENET_EIR_MII (0x00800000U) //!< Bit mask for ENET_EIR_MII.
bogdanm	82:6473597d706e	429	#define BS_ENET_EIR_MII (1U) //!< Bit field size in bits for ENET_EIR_MII.
bogdanm	82:6473597d706e	430
bogdanm	82:6473597d706e	431	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	432	//! @brief Read current value of the ENET_EIR_MII field.
bogdanm	82:6473597d706e	433	#define BR_ENET_EIR_MII(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII))
bogdanm	82:6473597d706e	434	#endif
bogdanm	82:6473597d706e	435
bogdanm	82:6473597d706e	436	//! @brief Format value for bitfield ENET_EIR_MII.
bogdanm	82:6473597d706e	437	#define BF_ENET_EIR_MII(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_MII), uint32_t) & BM_ENET_EIR_MII)
bogdanm	82:6473597d706e	438
bogdanm	82:6473597d706e	439	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	440	//! @brief Set the MII field to a new value.
bogdanm	82:6473597d706e	441	#define BW_ENET_EIR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII) = (v))
bogdanm	82:6473597d706e	442	#endif
bogdanm	82:6473597d706e	443	//@}
bogdanm	82:6473597d706e	444
bogdanm	82:6473597d706e	445	/*!
bogdanm	82:6473597d706e	446	* @name Register ENET_EIR, field RXB[24] (W1C)
bogdanm	82:6473597d706e	447	*
bogdanm	82:6473597d706e	448	* Indicates a receive buffer descriptor is not the last in the frame has been
bogdanm	82:6473597d706e	449	* updated.
bogdanm	82:6473597d706e	450	*/
bogdanm	82:6473597d706e	451	//@{
bogdanm	82:6473597d706e	452	#define BP_ENET_EIR_RXB (24U) //!< Bit position for ENET_EIR_RXB.
bogdanm	82:6473597d706e	453	#define BM_ENET_EIR_RXB (0x01000000U) //!< Bit mask for ENET_EIR_RXB.
bogdanm	82:6473597d706e	454	#define BS_ENET_EIR_RXB (1U) //!< Bit field size in bits for ENET_EIR_RXB.
bogdanm	82:6473597d706e	455
bogdanm	82:6473597d706e	456	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	457	//! @brief Read current value of the ENET_EIR_RXB field.
bogdanm	82:6473597d706e	458	#define BR_ENET_EIR_RXB(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB))
bogdanm	82:6473597d706e	459	#endif
bogdanm	82:6473597d706e	460
bogdanm	82:6473597d706e	461	//! @brief Format value for bitfield ENET_EIR_RXB.
bogdanm	82:6473597d706e	462	#define BF_ENET_EIR_RXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RXB), uint32_t) & BM_ENET_EIR_RXB)
bogdanm	82:6473597d706e	463
bogdanm	82:6473597d706e	464	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	465	//! @brief Set the RXB field to a new value.
bogdanm	82:6473597d706e	466	#define BW_ENET_EIR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB) = (v))
bogdanm	82:6473597d706e	467	#endif
bogdanm	82:6473597d706e	468	//@}
bogdanm	82:6473597d706e	469
bogdanm	82:6473597d706e	470	/*!
bogdanm	82:6473597d706e	471	* @name Register ENET_EIR, field RXF[25] (W1C)
bogdanm	82:6473597d706e	472	*
bogdanm	82:6473597d706e	473	* Indicates a frame has been received and the last corresponding buffer
bogdanm	82:6473597d706e	474	* descriptor has been updated.
bogdanm	82:6473597d706e	475	*/
bogdanm	82:6473597d706e	476	//@{
bogdanm	82:6473597d706e	477	#define BP_ENET_EIR_RXF (25U) //!< Bit position for ENET_EIR_RXF.
bogdanm	82:6473597d706e	478	#define BM_ENET_EIR_RXF (0x02000000U) //!< Bit mask for ENET_EIR_RXF.
bogdanm	82:6473597d706e	479	#define BS_ENET_EIR_RXF (1U) //!< Bit field size in bits for ENET_EIR_RXF.
bogdanm	82:6473597d706e	480
bogdanm	82:6473597d706e	481	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	482	//! @brief Read current value of the ENET_EIR_RXF field.
bogdanm	82:6473597d706e	483	#define BR_ENET_EIR_RXF(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF))
bogdanm	82:6473597d706e	484	#endif
bogdanm	82:6473597d706e	485
bogdanm	82:6473597d706e	486	//! @brief Format value for bitfield ENET_EIR_RXF.
bogdanm	82:6473597d706e	487	#define BF_ENET_EIR_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RXF), uint32_t) & BM_ENET_EIR_RXF)
bogdanm	82:6473597d706e	488
bogdanm	82:6473597d706e	489	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	490	//! @brief Set the RXF field to a new value.
bogdanm	82:6473597d706e	491	#define BW_ENET_EIR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF) = (v))
bogdanm	82:6473597d706e	492	#endif
bogdanm	82:6473597d706e	493	//@}
bogdanm	82:6473597d706e	494
bogdanm	82:6473597d706e	495	/*!
bogdanm	82:6473597d706e	496	* @name Register ENET_EIR, field TXB[26] (W1C)
bogdanm	82:6473597d706e	497	*
bogdanm	82:6473597d706e	498	* Indicates a transmit buffer descriptor has been updated.
bogdanm	82:6473597d706e	499	*/
bogdanm	82:6473597d706e	500	//@{
bogdanm	82:6473597d706e	501	#define BP_ENET_EIR_TXB (26U) //!< Bit position for ENET_EIR_TXB.
bogdanm	82:6473597d706e	502	#define BM_ENET_EIR_TXB (0x04000000U) //!< Bit mask for ENET_EIR_TXB.
bogdanm	82:6473597d706e	503	#define BS_ENET_EIR_TXB (1U) //!< Bit field size in bits for ENET_EIR_TXB.
bogdanm	82:6473597d706e	504
bogdanm	82:6473597d706e	505	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	506	//! @brief Read current value of the ENET_EIR_TXB field.
bogdanm	82:6473597d706e	507	#define BR_ENET_EIR_TXB(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB))
bogdanm	82:6473597d706e	508	#endif
bogdanm	82:6473597d706e	509
bogdanm	82:6473597d706e	510	//! @brief Format value for bitfield ENET_EIR_TXB.
bogdanm	82:6473597d706e	511	#define BF_ENET_EIR_TXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TXB), uint32_t) & BM_ENET_EIR_TXB)
bogdanm	82:6473597d706e	512
bogdanm	82:6473597d706e	513	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	514	//! @brief Set the TXB field to a new value.
bogdanm	82:6473597d706e	515	#define BW_ENET_EIR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB) = (v))
bogdanm	82:6473597d706e	516	#endif
bogdanm	82:6473597d706e	517	//@}
bogdanm	82:6473597d706e	518
bogdanm	82:6473597d706e	519	/*!
bogdanm	82:6473597d706e	520	* @name Register ENET_EIR, field TXF[27] (W1C)
bogdanm	82:6473597d706e	521	*
bogdanm	82:6473597d706e	522	* Indicates a frame has been transmitted and the last corresponding buffer
bogdanm	82:6473597d706e	523	* descriptor has been updated.
bogdanm	82:6473597d706e	524	*/
bogdanm	82:6473597d706e	525	//@{
bogdanm	82:6473597d706e	526	#define BP_ENET_EIR_TXF (27U) //!< Bit position for ENET_EIR_TXF.
bogdanm	82:6473597d706e	527	#define BM_ENET_EIR_TXF (0x08000000U) //!< Bit mask for ENET_EIR_TXF.
bogdanm	82:6473597d706e	528	#define BS_ENET_EIR_TXF (1U) //!< Bit field size in bits for ENET_EIR_TXF.
bogdanm	82:6473597d706e	529
bogdanm	82:6473597d706e	530	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	531	//! @brief Read current value of the ENET_EIR_TXF field.
bogdanm	82:6473597d706e	532	#define BR_ENET_EIR_TXF(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF))
bogdanm	82:6473597d706e	533	#endif
bogdanm	82:6473597d706e	534
bogdanm	82:6473597d706e	535	//! @brief Format value for bitfield ENET_EIR_TXF.
bogdanm	82:6473597d706e	536	#define BF_ENET_EIR_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TXF), uint32_t) & BM_ENET_EIR_TXF)
bogdanm	82:6473597d706e	537
bogdanm	82:6473597d706e	538	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	539	//! @brief Set the TXF field to a new value.
bogdanm	82:6473597d706e	540	#define BW_ENET_EIR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF) = (v))
bogdanm	82:6473597d706e	541	#endif
bogdanm	82:6473597d706e	542	//@}
bogdanm	82:6473597d706e	543
bogdanm	82:6473597d706e	544	/*!
bogdanm	82:6473597d706e	545	* @name Register ENET_EIR, field GRA[28] (W1C)
bogdanm	82:6473597d706e	546	*
bogdanm	82:6473597d706e	547	* This interrupt is asserted after the transmitter is put into a pause state
bogdanm	82:6473597d706e	548	* after completion of the frame currently being transmitted. See Graceful Transmit
bogdanm	82:6473597d706e	549	* Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
bogdanm	82:6473597d706e	550	* asserted only when the TX transitions into the stopped state. If this bit is
bogdanm	82:6473597d706e	551	* cleared by writing 1 and the TX is still stopped, the bit is not set again.
bogdanm	82:6473597d706e	552	*/
bogdanm	82:6473597d706e	553	//@{
bogdanm	82:6473597d706e	554	#define BP_ENET_EIR_GRA (28U) //!< Bit position for ENET_EIR_GRA.
bogdanm	82:6473597d706e	555	#define BM_ENET_EIR_GRA (0x10000000U) //!< Bit mask for ENET_EIR_GRA.
bogdanm	82:6473597d706e	556	#define BS_ENET_EIR_GRA (1U) //!< Bit field size in bits for ENET_EIR_GRA.
bogdanm	82:6473597d706e	557
bogdanm	82:6473597d706e	558	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	559	//! @brief Read current value of the ENET_EIR_GRA field.
bogdanm	82:6473597d706e	560	#define BR_ENET_EIR_GRA(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA))
bogdanm	82:6473597d706e	561	#endif
bogdanm	82:6473597d706e	562
bogdanm	82:6473597d706e	563	//! @brief Format value for bitfield ENET_EIR_GRA.
bogdanm	82:6473597d706e	564	#define BF_ENET_EIR_GRA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_GRA), uint32_t) & BM_ENET_EIR_GRA)
bogdanm	82:6473597d706e	565
bogdanm	82:6473597d706e	566	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	567	//! @brief Set the GRA field to a new value.
bogdanm	82:6473597d706e	568	#define BW_ENET_EIR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA) = (v))
bogdanm	82:6473597d706e	569	#endif
bogdanm	82:6473597d706e	570	//@}
bogdanm	82:6473597d706e	571
bogdanm	82:6473597d706e	572	/*!
bogdanm	82:6473597d706e	573	* @name Register ENET_EIR, field BABT[29] (W1C)
bogdanm	82:6473597d706e	574	*
bogdanm	82:6473597d706e	575	* Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
bogdanm	82:6473597d706e	576	* this condition is caused when a frame that is too long is placed into the
bogdanm	82:6473597d706e	577	* transmit data buffer(s). Truncation does not occur.
bogdanm	82:6473597d706e	578	*/
bogdanm	82:6473597d706e	579	//@{
bogdanm	82:6473597d706e	580	#define BP_ENET_EIR_BABT (29U) //!< Bit position for ENET_EIR_BABT.
bogdanm	82:6473597d706e	581	#define BM_ENET_EIR_BABT (0x20000000U) //!< Bit mask for ENET_EIR_BABT.
bogdanm	82:6473597d706e	582	#define BS_ENET_EIR_BABT (1U) //!< Bit field size in bits for ENET_EIR_BABT.
bogdanm	82:6473597d706e	583
bogdanm	82:6473597d706e	584	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	585	//! @brief Read current value of the ENET_EIR_BABT field.
bogdanm	82:6473597d706e	586	#define BR_ENET_EIR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT))
bogdanm	82:6473597d706e	587	#endif
bogdanm	82:6473597d706e	588
bogdanm	82:6473597d706e	589	//! @brief Format value for bitfield ENET_EIR_BABT.
bogdanm	82:6473597d706e	590	#define BF_ENET_EIR_BABT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_BABT), uint32_t) & BM_ENET_EIR_BABT)
bogdanm	82:6473597d706e	591
bogdanm	82:6473597d706e	592	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	593	//! @brief Set the BABT field to a new value.
bogdanm	82:6473597d706e	594	#define BW_ENET_EIR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT) = (v))
bogdanm	82:6473597d706e	595	#endif
bogdanm	82:6473597d706e	596	//@}
bogdanm	82:6473597d706e	597
bogdanm	82:6473597d706e	598	/*!
bogdanm	82:6473597d706e	599	* @name Register ENET_EIR, field BABR[30] (W1C)
bogdanm	82:6473597d706e	600	*
bogdanm	82:6473597d706e	601	* Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
bogdanm	82:6473597d706e	602	*/
bogdanm	82:6473597d706e	603	//@{
bogdanm	82:6473597d706e	604	#define BP_ENET_EIR_BABR (30U) //!< Bit position for ENET_EIR_BABR.
bogdanm	82:6473597d706e	605	#define BM_ENET_EIR_BABR (0x40000000U) //!< Bit mask for ENET_EIR_BABR.
bogdanm	82:6473597d706e	606	#define BS_ENET_EIR_BABR (1U) //!< Bit field size in bits for ENET_EIR_BABR.
bogdanm	82:6473597d706e	607
bogdanm	82:6473597d706e	608	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	609	//! @brief Read current value of the ENET_EIR_BABR field.
bogdanm	82:6473597d706e	610	#define BR_ENET_EIR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR))
bogdanm	82:6473597d706e	611	#endif
bogdanm	82:6473597d706e	612
bogdanm	82:6473597d706e	613	//! @brief Format value for bitfield ENET_EIR_BABR.
bogdanm	82:6473597d706e	614	#define BF_ENET_EIR_BABR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_BABR), uint32_t) & BM_ENET_EIR_BABR)
bogdanm	82:6473597d706e	615
bogdanm	82:6473597d706e	616	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	617	//! @brief Set the BABR field to a new value.
bogdanm	82:6473597d706e	618	#define BW_ENET_EIR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR) = (v))
bogdanm	82:6473597d706e	619	#endif
bogdanm	82:6473597d706e	620	//@}
bogdanm	82:6473597d706e	621
bogdanm	82:6473597d706e	622	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	623	// HW_ENET_EIMR - Interrupt Mask Register
bogdanm	82:6473597d706e	624	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	625
bogdanm	82:6473597d706e	626	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	627	/*!
bogdanm	82:6473597d706e	628	* @brief HW_ENET_EIMR - Interrupt Mask Register (RW)
bogdanm	82:6473597d706e	629	*
bogdanm	82:6473597d706e	630	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	631	*
bogdanm	82:6473597d706e	632	* EIMR controls which interrupt events are allowed to generate actual
bogdanm	82:6473597d706e	633	* interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
bogdanm	82:6473597d706e	634	* and EIMR registers are set, an interrupt is generated. The interrupt signal
bogdanm	82:6473597d706e	635	* remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
bogdanm	82:6473597d706e	636	* 0 is written to the EIMR field.
bogdanm	82:6473597d706e	637	*/
bogdanm	82:6473597d706e	638	typedef union _hw_enet_eimr
bogdanm	82:6473597d706e	639	{
bogdanm	82:6473597d706e	640	uint32_t U;
bogdanm	82:6473597d706e	641	struct _hw_enet_eimr_bitfields
bogdanm	82:6473597d706e	642	{
bogdanm	82:6473597d706e	643	uint32_t RESERVED0 : 15; //!< [14:0]
bogdanm	82:6473597d706e	644	uint32_t TS_TIMER : 1; //!< [15] TS_TIMER Interrupt Mask
bogdanm	82:6473597d706e	645	uint32_t TS_AVAIL : 1; //!< [16] TS_AVAIL Interrupt Mask
bogdanm	82:6473597d706e	646	uint32_t WAKEUP : 1; //!< [17] WAKEUP Interrupt Mask
bogdanm	82:6473597d706e	647	uint32_t PLR : 1; //!< [18] PLR Interrupt Mask
bogdanm	82:6473597d706e	648	uint32_t UN : 1; //!< [19] UN Interrupt Mask
bogdanm	82:6473597d706e	649	uint32_t RL : 1; //!< [20] RL Interrupt Mask
bogdanm	82:6473597d706e	650	uint32_t LC : 1; //!< [21] LC Interrupt Mask
bogdanm	82:6473597d706e	651	uint32_t EBERR : 1; //!< [22] EBERR Interrupt Mask
bogdanm	82:6473597d706e	652	uint32_t MII : 1; //!< [23] MII Interrupt Mask
bogdanm	82:6473597d706e	653	uint32_t RXB : 1; //!< [24] RXB Interrupt Mask
bogdanm	82:6473597d706e	654	uint32_t RXF : 1; //!< [25] RXF Interrupt Mask
bogdanm	82:6473597d706e	655	uint32_t TXB : 1; //!< [26] TXB Interrupt Mask
bogdanm	82:6473597d706e	656	uint32_t TXF : 1; //!< [27] TXF Interrupt Mask
bogdanm	82:6473597d706e	657	uint32_t GRA : 1; //!< [28] GRA Interrupt Mask
bogdanm	82:6473597d706e	658	uint32_t BABT : 1; //!< [29] BABT Interrupt Mask
bogdanm	82:6473597d706e	659	uint32_t BABR : 1; //!< [30] BABR Interrupt Mask
bogdanm	82:6473597d706e	660	uint32_t RESERVED1 : 1; //!< [31]
bogdanm	82:6473597d706e	661	} B;
bogdanm	82:6473597d706e	662	} hw_enet_eimr_t;
bogdanm	82:6473597d706e	663	#endif
bogdanm	82:6473597d706e	664
bogdanm	82:6473597d706e	665	/*!
bogdanm	82:6473597d706e	666	* @name Constants and macros for entire ENET_EIMR register
bogdanm	82:6473597d706e	667	*/
bogdanm	82:6473597d706e	668	//@{
bogdanm	82:6473597d706e	669	#define HW_ENET_EIMR_ADDR(x) (REGS_ENET_BASE(x) + 0x8U)
bogdanm	82:6473597d706e	670
bogdanm	82:6473597d706e	671	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	672	#define HW_ENET_EIMR(x) ((__IO hw_enet_eimr_t ) HW_ENET_EIMR_ADDR(x))
bogdanm	82:6473597d706e	673	#define HW_ENET_EIMR_RD(x) (HW_ENET_EIMR(x).U)
bogdanm	82:6473597d706e	674	#define HW_ENET_EIMR_WR(x, v) (HW_ENET_EIMR(x).U = (v))
bogdanm	82:6473597d706e	675	#define HW_ENET_EIMR_SET(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) \| (v)))
bogdanm	82:6473597d706e	676	#define HW_ENET_EIMR_CLR(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	677	#define HW_ENET_EIMR_TOG(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	678	#endif
bogdanm	82:6473597d706e	679	//@}
bogdanm	82:6473597d706e	680
bogdanm	82:6473597d706e	681	/*
bogdanm	82:6473597d706e	682	* Constants & macros for individual ENET_EIMR bitfields
bogdanm	82:6473597d706e	683	*/
bogdanm	82:6473597d706e	684
bogdanm	82:6473597d706e	685	/*!
bogdanm	82:6473597d706e	686	* @name Register ENET_EIMR, field TS_TIMER[15] (RW)
bogdanm	82:6473597d706e	687	*
bogdanm	82:6473597d706e	688	* Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
bogdanm	82:6473597d706e	689	* an interrupt condition can generate an interrupt. At every module clock, the
bogdanm	82:6473597d706e	690	* EIR samples the signal generated by the interrupting source. The corresponding
bogdanm	82:6473597d706e	691	* EIR TS_TIMER field reflects the state of the interrupt signal even if the
bogdanm	82:6473597d706e	692	* corresponding EIMR field is cleared.
bogdanm	82:6473597d706e	693	*/
bogdanm	82:6473597d706e	694	//@{
bogdanm	82:6473597d706e	695	#define BP_ENET_EIMR_TS_TIMER (15U) //!< Bit position for ENET_EIMR_TS_TIMER.
bogdanm	82:6473597d706e	696	#define BM_ENET_EIMR_TS_TIMER (0x00008000U) //!< Bit mask for ENET_EIMR_TS_TIMER.
bogdanm	82:6473597d706e	697	#define BS_ENET_EIMR_TS_TIMER (1U) //!< Bit field size in bits for ENET_EIMR_TS_TIMER.
bogdanm	82:6473597d706e	698
bogdanm	82:6473597d706e	699	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	700	//! @brief Read current value of the ENET_EIMR_TS_TIMER field.
bogdanm	82:6473597d706e	701	#define BR_ENET_EIMR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER))
bogdanm	82:6473597d706e	702	#endif
bogdanm	82:6473597d706e	703
bogdanm	82:6473597d706e	704	//! @brief Format value for bitfield ENET_EIMR_TS_TIMER.
bogdanm	82:6473597d706e	705	#define BF_ENET_EIMR_TS_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TS_TIMER), uint32_t) & BM_ENET_EIMR_TS_TIMER)
bogdanm	82:6473597d706e	706
bogdanm	82:6473597d706e	707	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	708	//! @brief Set the TS_TIMER field to a new value.
bogdanm	82:6473597d706e	709	#define BW_ENET_EIMR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER) = (v))
bogdanm	82:6473597d706e	710	#endif
bogdanm	82:6473597d706e	711	//@}
bogdanm	82:6473597d706e	712
bogdanm	82:6473597d706e	713	/*!
bogdanm	82:6473597d706e	714	* @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
bogdanm	82:6473597d706e	715	*
bogdanm	82:6473597d706e	716	* Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
bogdanm	82:6473597d706e	717	* an interrupt condition can generate an interrupt. At every module clock, the
bogdanm	82:6473597d706e	718	* EIR samples the signal generated by the interrupting source. The corresponding
bogdanm	82:6473597d706e	719	* EIR TS_AVAIL field reflects the state of the interrupt signal even if the
bogdanm	82:6473597d706e	720	* corresponding EIMR field is cleared.
bogdanm	82:6473597d706e	721	*/
bogdanm	82:6473597d706e	722	//@{
bogdanm	82:6473597d706e	723	#define BP_ENET_EIMR_TS_AVAIL (16U) //!< Bit position for ENET_EIMR_TS_AVAIL.
bogdanm	82:6473597d706e	724	#define BM_ENET_EIMR_TS_AVAIL (0x00010000U) //!< Bit mask for ENET_EIMR_TS_AVAIL.
bogdanm	82:6473597d706e	725	#define BS_ENET_EIMR_TS_AVAIL (1U) //!< Bit field size in bits for ENET_EIMR_TS_AVAIL.
bogdanm	82:6473597d706e	726
bogdanm	82:6473597d706e	727	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	728	//! @brief Read current value of the ENET_EIMR_TS_AVAIL field.
bogdanm	82:6473597d706e	729	#define BR_ENET_EIMR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL))
bogdanm	82:6473597d706e	730	#endif
bogdanm	82:6473597d706e	731
bogdanm	82:6473597d706e	732	//! @brief Format value for bitfield ENET_EIMR_TS_AVAIL.
bogdanm	82:6473597d706e	733	#define BF_ENET_EIMR_TS_AVAIL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TS_AVAIL), uint32_t) & BM_ENET_EIMR_TS_AVAIL)
bogdanm	82:6473597d706e	734
bogdanm	82:6473597d706e	735	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	736	//! @brief Set the TS_AVAIL field to a new value.
bogdanm	82:6473597d706e	737	#define BW_ENET_EIMR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL) = (v))
bogdanm	82:6473597d706e	738	#endif
bogdanm	82:6473597d706e	739	//@}
bogdanm	82:6473597d706e	740
bogdanm	82:6473597d706e	741	/*!
bogdanm	82:6473597d706e	742	* @name Register ENET_EIMR, field WAKEUP[17] (RW)
bogdanm	82:6473597d706e	743	*
bogdanm	82:6473597d706e	744	* Corresponds to interrupt source EIR[WAKEUP] register and determines whether
bogdanm	82:6473597d706e	745	* an interrupt condition can generate an interrupt. At every module clock, the
bogdanm	82:6473597d706e	746	* EIR samples the signal generated by the interrupting source. The corresponding
bogdanm	82:6473597d706e	747	* EIR WAKEUP field reflects the state of the interrupt signal even if the
bogdanm	82:6473597d706e	748	* corresponding EIMR field is cleared.
bogdanm	82:6473597d706e	749	*/
bogdanm	82:6473597d706e	750	//@{
bogdanm	82:6473597d706e	751	#define BP_ENET_EIMR_WAKEUP (17U) //!< Bit position for ENET_EIMR_WAKEUP.
bogdanm	82:6473597d706e	752	#define BM_ENET_EIMR_WAKEUP (0x00020000U) //!< Bit mask for ENET_EIMR_WAKEUP.
bogdanm	82:6473597d706e	753	#define BS_ENET_EIMR_WAKEUP (1U) //!< Bit field size in bits for ENET_EIMR_WAKEUP.
bogdanm	82:6473597d706e	754
bogdanm	82:6473597d706e	755	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	756	//! @brief Read current value of the ENET_EIMR_WAKEUP field.
bogdanm	82:6473597d706e	757	#define BR_ENET_EIMR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP))
bogdanm	82:6473597d706e	758	#endif
bogdanm	82:6473597d706e	759
bogdanm	82:6473597d706e	760	//! @brief Format value for bitfield ENET_EIMR_WAKEUP.
bogdanm	82:6473597d706e	761	#define BF_ENET_EIMR_WAKEUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_WAKEUP), uint32_t) & BM_ENET_EIMR_WAKEUP)
bogdanm	82:6473597d706e	762
bogdanm	82:6473597d706e	763	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	764	//! @brief Set the WAKEUP field to a new value.
bogdanm	82:6473597d706e	765	#define BW_ENET_EIMR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP) = (v))
bogdanm	82:6473597d706e	766	#endif
bogdanm	82:6473597d706e	767	//@}
bogdanm	82:6473597d706e	768
bogdanm	82:6473597d706e	769	/*!
bogdanm	82:6473597d706e	770	* @name Register ENET_EIMR, field PLR[18] (RW)
bogdanm	82:6473597d706e	771	*
bogdanm	82:6473597d706e	772	* Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
bogdanm	82:6473597d706e	773	* condition can generate an interrupt. At every module clock, the EIR samples
bogdanm	82:6473597d706e	774	* the signal generated by the interrupting source. The corresponding EIR PLR field
bogdanm	82:6473597d706e	775	* reflects the state of the interrupt signal even if the corresponding EIMR
bogdanm	82:6473597d706e	776	* field is cleared.
bogdanm	82:6473597d706e	777	*/
bogdanm	82:6473597d706e	778	//@{
bogdanm	82:6473597d706e	779	#define BP_ENET_EIMR_PLR (18U) //!< Bit position for ENET_EIMR_PLR.
bogdanm	82:6473597d706e	780	#define BM_ENET_EIMR_PLR (0x00040000U) //!< Bit mask for ENET_EIMR_PLR.
bogdanm	82:6473597d706e	781	#define BS_ENET_EIMR_PLR (1U) //!< Bit field size in bits for ENET_EIMR_PLR.
bogdanm	82:6473597d706e	782
bogdanm	82:6473597d706e	783	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	784	//! @brief Read current value of the ENET_EIMR_PLR field.
bogdanm	82:6473597d706e	785	#define BR_ENET_EIMR_PLR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR))
bogdanm	82:6473597d706e	786	#endif
bogdanm	82:6473597d706e	787
bogdanm	82:6473597d706e	788	//! @brief Format value for bitfield ENET_EIMR_PLR.
bogdanm	82:6473597d706e	789	#define BF_ENET_EIMR_PLR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_PLR), uint32_t) & BM_ENET_EIMR_PLR)
bogdanm	82:6473597d706e	790
bogdanm	82:6473597d706e	791	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	792	//! @brief Set the PLR field to a new value.
bogdanm	82:6473597d706e	793	#define BW_ENET_EIMR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR) = (v))
bogdanm	82:6473597d706e	794	#endif
bogdanm	82:6473597d706e	795	//@}
bogdanm	82:6473597d706e	796
bogdanm	82:6473597d706e	797	/*!
bogdanm	82:6473597d706e	798	* @name Register ENET_EIMR, field UN[19] (RW)
bogdanm	82:6473597d706e	799	*
bogdanm	82:6473597d706e	800	* Corresponds to interrupt source EIR[UN] and determines whether an interrupt
bogdanm	82:6473597d706e	801	* condition can generate an interrupt. At every module clock, the EIR samples the
bogdanm	82:6473597d706e	802	* signal generated by the interrupting source. The corresponding EIR UN field
bogdanm	82:6473597d706e	803	* reflects the state of the interrupt signal even if the corresponding EIMR field
bogdanm	82:6473597d706e	804	* is cleared.
bogdanm	82:6473597d706e	805	*/
bogdanm	82:6473597d706e	806	//@{
bogdanm	82:6473597d706e	807	#define BP_ENET_EIMR_UN (19U) //!< Bit position for ENET_EIMR_UN.
bogdanm	82:6473597d706e	808	#define BM_ENET_EIMR_UN (0x00080000U) //!< Bit mask for ENET_EIMR_UN.
bogdanm	82:6473597d706e	809	#define BS_ENET_EIMR_UN (1U) //!< Bit field size in bits for ENET_EIMR_UN.
bogdanm	82:6473597d706e	810
bogdanm	82:6473597d706e	811	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	812	//! @brief Read current value of the ENET_EIMR_UN field.
bogdanm	82:6473597d706e	813	#define BR_ENET_EIMR_UN(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN))
bogdanm	82:6473597d706e	814	#endif
bogdanm	82:6473597d706e	815
bogdanm	82:6473597d706e	816	//! @brief Format value for bitfield ENET_EIMR_UN.
bogdanm	82:6473597d706e	817	#define BF_ENET_EIMR_UN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_UN), uint32_t) & BM_ENET_EIMR_UN)
bogdanm	82:6473597d706e	818
bogdanm	82:6473597d706e	819	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	820	//! @brief Set the UN field to a new value.
bogdanm	82:6473597d706e	821	#define BW_ENET_EIMR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN) = (v))
bogdanm	82:6473597d706e	822	#endif
bogdanm	82:6473597d706e	823	//@}
bogdanm	82:6473597d706e	824
bogdanm	82:6473597d706e	825	/*!
bogdanm	82:6473597d706e	826	* @name Register ENET_EIMR, field RL[20] (RW)
bogdanm	82:6473597d706e	827	*
bogdanm	82:6473597d706e	828	* Corresponds to interrupt source EIR[RL] and determines whether an interrupt
bogdanm	82:6473597d706e	829	* condition can generate an interrupt. At every module clock, the EIR samples the
bogdanm	82:6473597d706e	830	* signal generated by the interrupting source. The corresponding EIR RL field
bogdanm	82:6473597d706e	831	* reflects the state of the interrupt signal even if the corresponding EIMR field
bogdanm	82:6473597d706e	832	* is cleared.
bogdanm	82:6473597d706e	833	*/
bogdanm	82:6473597d706e	834	//@{
bogdanm	82:6473597d706e	835	#define BP_ENET_EIMR_RL (20U) //!< Bit position for ENET_EIMR_RL.
bogdanm	82:6473597d706e	836	#define BM_ENET_EIMR_RL (0x00100000U) //!< Bit mask for ENET_EIMR_RL.
bogdanm	82:6473597d706e	837	#define BS_ENET_EIMR_RL (1U) //!< Bit field size in bits for ENET_EIMR_RL.
bogdanm	82:6473597d706e	838
bogdanm	82:6473597d706e	839	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	840	//! @brief Read current value of the ENET_EIMR_RL field.
bogdanm	82:6473597d706e	841	#define BR_ENET_EIMR_RL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL))
bogdanm	82:6473597d706e	842	#endif
bogdanm	82:6473597d706e	843
bogdanm	82:6473597d706e	844	//! @brief Format value for bitfield ENET_EIMR_RL.
bogdanm	82:6473597d706e	845	#define BF_ENET_EIMR_RL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RL), uint32_t) & BM_ENET_EIMR_RL)
bogdanm	82:6473597d706e	846
bogdanm	82:6473597d706e	847	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	848	//! @brief Set the RL field to a new value.
bogdanm	82:6473597d706e	849	#define BW_ENET_EIMR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL) = (v))
bogdanm	82:6473597d706e	850	#endif
bogdanm	82:6473597d706e	851	//@}
bogdanm	82:6473597d706e	852
bogdanm	82:6473597d706e	853	/*!
bogdanm	82:6473597d706e	854	* @name Register ENET_EIMR, field LC[21] (RW)
bogdanm	82:6473597d706e	855	*
bogdanm	82:6473597d706e	856	* Corresponds to interrupt source EIR[LC] and determines whether an interrupt
bogdanm	82:6473597d706e	857	* condition can generate an interrupt. At every module clock, the EIR samples the
bogdanm	82:6473597d706e	858	* signal generated by the interrupting source. The corresponding EIR LC field
bogdanm	82:6473597d706e	859	* reflects the state of the interrupt signal even if the corresponding EIMR field
bogdanm	82:6473597d706e	860	* is cleared.
bogdanm	82:6473597d706e	861	*/
bogdanm	82:6473597d706e	862	//@{
bogdanm	82:6473597d706e	863	#define BP_ENET_EIMR_LC (21U) //!< Bit position for ENET_EIMR_LC.
bogdanm	82:6473597d706e	864	#define BM_ENET_EIMR_LC (0x00200000U) //!< Bit mask for ENET_EIMR_LC.
bogdanm	82:6473597d706e	865	#define BS_ENET_EIMR_LC (1U) //!< Bit field size in bits for ENET_EIMR_LC.
bogdanm	82:6473597d706e	866
bogdanm	82:6473597d706e	867	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	868	//! @brief Read current value of the ENET_EIMR_LC field.
bogdanm	82:6473597d706e	869	#define BR_ENET_EIMR_LC(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC))
bogdanm	82:6473597d706e	870	#endif
bogdanm	82:6473597d706e	871
bogdanm	82:6473597d706e	872	//! @brief Format value for bitfield ENET_EIMR_LC.
bogdanm	82:6473597d706e	873	#define BF_ENET_EIMR_LC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_LC), uint32_t) & BM_ENET_EIMR_LC)
bogdanm	82:6473597d706e	874
bogdanm	82:6473597d706e	875	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	876	//! @brief Set the LC field to a new value.
bogdanm	82:6473597d706e	877	#define BW_ENET_EIMR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC) = (v))
bogdanm	82:6473597d706e	878	#endif
bogdanm	82:6473597d706e	879	//@}
bogdanm	82:6473597d706e	880
bogdanm	82:6473597d706e	881	/*!
bogdanm	82:6473597d706e	882	* @name Register ENET_EIMR, field EBERR[22] (RW)
bogdanm	82:6473597d706e	883	*
bogdanm	82:6473597d706e	884	* Corresponds to interrupt source EIR[EBERR] and determines whether an
bogdanm	82:6473597d706e	885	* interrupt condition can generate an interrupt. At every module clock, the EIR samples
bogdanm	82:6473597d706e	886	* the signal generated by the interrupting source. The corresponding EIR EBERR
bogdanm	82:6473597d706e	887	* field reflects the state of the interrupt signal even if the corresponding EIMR
bogdanm	82:6473597d706e	888	* field is cleared.
bogdanm	82:6473597d706e	889	*/
bogdanm	82:6473597d706e	890	//@{
bogdanm	82:6473597d706e	891	#define BP_ENET_EIMR_EBERR (22U) //!< Bit position for ENET_EIMR_EBERR.
bogdanm	82:6473597d706e	892	#define BM_ENET_EIMR_EBERR (0x00400000U) //!< Bit mask for ENET_EIMR_EBERR.
bogdanm	82:6473597d706e	893	#define BS_ENET_EIMR_EBERR (1U) //!< Bit field size in bits for ENET_EIMR_EBERR.
bogdanm	82:6473597d706e	894
bogdanm	82:6473597d706e	895	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	896	//! @brief Read current value of the ENET_EIMR_EBERR field.
bogdanm	82:6473597d706e	897	#define BR_ENET_EIMR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR))
bogdanm	82:6473597d706e	898	#endif
bogdanm	82:6473597d706e	899
bogdanm	82:6473597d706e	900	//! @brief Format value for bitfield ENET_EIMR_EBERR.
bogdanm	82:6473597d706e	901	#define BF_ENET_EIMR_EBERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_EBERR), uint32_t) & BM_ENET_EIMR_EBERR)
bogdanm	82:6473597d706e	902
bogdanm	82:6473597d706e	903	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	904	//! @brief Set the EBERR field to a new value.
bogdanm	82:6473597d706e	905	#define BW_ENET_EIMR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR) = (v))
bogdanm	82:6473597d706e	906	#endif
bogdanm	82:6473597d706e	907	//@}
bogdanm	82:6473597d706e	908
bogdanm	82:6473597d706e	909	/*!
bogdanm	82:6473597d706e	910	* @name Register ENET_EIMR, field MII[23] (RW)
bogdanm	82:6473597d706e	911	*
bogdanm	82:6473597d706e	912	* Corresponds to interrupt source EIR[MII] and determines whether an interrupt
bogdanm	82:6473597d706e	913	* condition can generate an interrupt. At every module clock, the EIR samples
bogdanm	82:6473597d706e	914	* the signal generated by the interrupting source. The corresponding EIR MII field
bogdanm	82:6473597d706e	915	* reflects the state of the interrupt signal even if the corresponding EIMR
bogdanm	82:6473597d706e	916	* field is cleared.
bogdanm	82:6473597d706e	917	*/
bogdanm	82:6473597d706e	918	//@{
bogdanm	82:6473597d706e	919	#define BP_ENET_EIMR_MII (23U) //!< Bit position for ENET_EIMR_MII.
bogdanm	82:6473597d706e	920	#define BM_ENET_EIMR_MII (0x00800000U) //!< Bit mask for ENET_EIMR_MII.
bogdanm	82:6473597d706e	921	#define BS_ENET_EIMR_MII (1U) //!< Bit field size in bits for ENET_EIMR_MII.
bogdanm	82:6473597d706e	922
bogdanm	82:6473597d706e	923	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	924	//! @brief Read current value of the ENET_EIMR_MII field.
bogdanm	82:6473597d706e	925	#define BR_ENET_EIMR_MII(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII))
bogdanm	82:6473597d706e	926	#endif
bogdanm	82:6473597d706e	927
bogdanm	82:6473597d706e	928	//! @brief Format value for bitfield ENET_EIMR_MII.
bogdanm	82:6473597d706e	929	#define BF_ENET_EIMR_MII(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_MII), uint32_t) & BM_ENET_EIMR_MII)
bogdanm	82:6473597d706e	930
bogdanm	82:6473597d706e	931	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	932	//! @brief Set the MII field to a new value.
bogdanm	82:6473597d706e	933	#define BW_ENET_EIMR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII) = (v))
bogdanm	82:6473597d706e	934	#endif
bogdanm	82:6473597d706e	935	//@}
bogdanm	82:6473597d706e	936
bogdanm	82:6473597d706e	937	/*!
bogdanm	82:6473597d706e	938	* @name Register ENET_EIMR, field RXB[24] (RW)
bogdanm	82:6473597d706e	939	*
bogdanm	82:6473597d706e	940	* Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
bogdanm	82:6473597d706e	941	* condition can generate an interrupt. At every module clock, the EIR samples
bogdanm	82:6473597d706e	942	* the signal generated by the interrupting source. The corresponding EIR RXB field
bogdanm	82:6473597d706e	943	* reflects the state of the interrupt signal even if the corresponding EIMR
bogdanm	82:6473597d706e	944	* field is cleared.
bogdanm	82:6473597d706e	945	*/
bogdanm	82:6473597d706e	946	//@{
bogdanm	82:6473597d706e	947	#define BP_ENET_EIMR_RXB (24U) //!< Bit position for ENET_EIMR_RXB.
bogdanm	82:6473597d706e	948	#define BM_ENET_EIMR_RXB (0x01000000U) //!< Bit mask for ENET_EIMR_RXB.
bogdanm	82:6473597d706e	949	#define BS_ENET_EIMR_RXB (1U) //!< Bit field size in bits for ENET_EIMR_RXB.
bogdanm	82:6473597d706e	950
bogdanm	82:6473597d706e	951	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	952	//! @brief Read current value of the ENET_EIMR_RXB field.
bogdanm	82:6473597d706e	953	#define BR_ENET_EIMR_RXB(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB))
bogdanm	82:6473597d706e	954	#endif
bogdanm	82:6473597d706e	955
bogdanm	82:6473597d706e	956	//! @brief Format value for bitfield ENET_EIMR_RXB.
bogdanm	82:6473597d706e	957	#define BF_ENET_EIMR_RXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RXB), uint32_t) & BM_ENET_EIMR_RXB)
bogdanm	82:6473597d706e	958
bogdanm	82:6473597d706e	959	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	960	//! @brief Set the RXB field to a new value.
bogdanm	82:6473597d706e	961	#define BW_ENET_EIMR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB) = (v))
bogdanm	82:6473597d706e	962	#endif
bogdanm	82:6473597d706e	963	//@}
bogdanm	82:6473597d706e	964
bogdanm	82:6473597d706e	965	/*!
bogdanm	82:6473597d706e	966	* @name Register ENET_EIMR, field RXF[25] (RW)
bogdanm	82:6473597d706e	967	*
bogdanm	82:6473597d706e	968	* Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
bogdanm	82:6473597d706e	969	* condition can generate an interrupt. At every module clock, the EIR samples
bogdanm	82:6473597d706e	970	* the signal generated by the interrupting source. The corresponding EIR RXF field
bogdanm	82:6473597d706e	971	* reflects the state of the interrupt signal even if the corresponding EIMR
bogdanm	82:6473597d706e	972	* field is cleared.
bogdanm	82:6473597d706e	973	*/
bogdanm	82:6473597d706e	974	//@{
bogdanm	82:6473597d706e	975	#define BP_ENET_EIMR_RXF (25U) //!< Bit position for ENET_EIMR_RXF.
bogdanm	82:6473597d706e	976	#define BM_ENET_EIMR_RXF (0x02000000U) //!< Bit mask for ENET_EIMR_RXF.
bogdanm	82:6473597d706e	977	#define BS_ENET_EIMR_RXF (1U) //!< Bit field size in bits for ENET_EIMR_RXF.
bogdanm	82:6473597d706e	978
bogdanm	82:6473597d706e	979	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	980	//! @brief Read current value of the ENET_EIMR_RXF field.
bogdanm	82:6473597d706e	981	#define BR_ENET_EIMR_RXF(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF))
bogdanm	82:6473597d706e	982	#endif
bogdanm	82:6473597d706e	983
bogdanm	82:6473597d706e	984	//! @brief Format value for bitfield ENET_EIMR_RXF.
bogdanm	82:6473597d706e	985	#define BF_ENET_EIMR_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RXF), uint32_t) & BM_ENET_EIMR_RXF)
bogdanm	82:6473597d706e	986
bogdanm	82:6473597d706e	987	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	988	//! @brief Set the RXF field to a new value.
bogdanm	82:6473597d706e	989	#define BW_ENET_EIMR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF) = (v))
bogdanm	82:6473597d706e	990	#endif
bogdanm	82:6473597d706e	991	//@}
bogdanm	82:6473597d706e	992
bogdanm	82:6473597d706e	993	/*!
bogdanm	82:6473597d706e	994	* @name Register ENET_EIMR, field TXB[26] (RW)
bogdanm	82:6473597d706e	995	*
bogdanm	82:6473597d706e	996	* Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
bogdanm	82:6473597d706e	997	* condition can generate an interrupt. At every module clock, the EIR samples
bogdanm	82:6473597d706e	998	* the signal generated by the interrupting source. The corresponding EIR TXF field
bogdanm	82:6473597d706e	999	* reflects the state of the interrupt signal even if the corresponding EIMR
bogdanm	82:6473597d706e	1000	* field is cleared.
bogdanm	82:6473597d706e	1001	*
bogdanm	82:6473597d706e	1002	* Values:
bogdanm	82:6473597d706e	1003	* - 0 - The corresponding interrupt source is masked.
bogdanm	82:6473597d706e	1004	* - 1 - The corresponding interrupt source is not masked.
bogdanm	82:6473597d706e	1005	*/
bogdanm	82:6473597d706e	1006	//@{
bogdanm	82:6473597d706e	1007	#define BP_ENET_EIMR_TXB (26U) //!< Bit position for ENET_EIMR_TXB.
bogdanm	82:6473597d706e	1008	#define BM_ENET_EIMR_TXB (0x04000000U) //!< Bit mask for ENET_EIMR_TXB.
bogdanm	82:6473597d706e	1009	#define BS_ENET_EIMR_TXB (1U) //!< Bit field size in bits for ENET_EIMR_TXB.
bogdanm	82:6473597d706e	1010
bogdanm	82:6473597d706e	1011	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1012	//! @brief Read current value of the ENET_EIMR_TXB field.
bogdanm	82:6473597d706e	1013	#define BR_ENET_EIMR_TXB(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB))
bogdanm	82:6473597d706e	1014	#endif
bogdanm	82:6473597d706e	1015
bogdanm	82:6473597d706e	1016	//! @brief Format value for bitfield ENET_EIMR_TXB.
bogdanm	82:6473597d706e	1017	#define BF_ENET_EIMR_TXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TXB), uint32_t) & BM_ENET_EIMR_TXB)
bogdanm	82:6473597d706e	1018
bogdanm	82:6473597d706e	1019	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1020	//! @brief Set the TXB field to a new value.
bogdanm	82:6473597d706e	1021	#define BW_ENET_EIMR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB) = (v))
bogdanm	82:6473597d706e	1022	#endif
bogdanm	82:6473597d706e	1023	//@}
bogdanm	82:6473597d706e	1024
bogdanm	82:6473597d706e	1025	/*!
bogdanm	82:6473597d706e	1026	* @name Register ENET_EIMR, field TXF[27] (RW)
bogdanm	82:6473597d706e	1027	*
bogdanm	82:6473597d706e	1028	* Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
bogdanm	82:6473597d706e	1029	* condition can generate an interrupt. At every module clock, the EIR samples
bogdanm	82:6473597d706e	1030	* the signal generated by the interrupting source. The corresponding EIR TXF field
bogdanm	82:6473597d706e	1031	* reflects the state of the interrupt signal even if the corresponding EIMR
bogdanm	82:6473597d706e	1032	* field is cleared.
bogdanm	82:6473597d706e	1033	*
bogdanm	82:6473597d706e	1034	* Values:
bogdanm	82:6473597d706e	1035	* - 0 - The corresponding interrupt source is masked.
bogdanm	82:6473597d706e	1036	* - 1 - The corresponding interrupt source is not masked.
bogdanm	82:6473597d706e	1037	*/
bogdanm	82:6473597d706e	1038	//@{
bogdanm	82:6473597d706e	1039	#define BP_ENET_EIMR_TXF (27U) //!< Bit position for ENET_EIMR_TXF.
bogdanm	82:6473597d706e	1040	#define BM_ENET_EIMR_TXF (0x08000000U) //!< Bit mask for ENET_EIMR_TXF.
bogdanm	82:6473597d706e	1041	#define BS_ENET_EIMR_TXF (1U) //!< Bit field size in bits for ENET_EIMR_TXF.
bogdanm	82:6473597d706e	1042
bogdanm	82:6473597d706e	1043	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1044	//! @brief Read current value of the ENET_EIMR_TXF field.
bogdanm	82:6473597d706e	1045	#define BR_ENET_EIMR_TXF(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF))
bogdanm	82:6473597d706e	1046	#endif
bogdanm	82:6473597d706e	1047
bogdanm	82:6473597d706e	1048	//! @brief Format value for bitfield ENET_EIMR_TXF.
bogdanm	82:6473597d706e	1049	#define BF_ENET_EIMR_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TXF), uint32_t) & BM_ENET_EIMR_TXF)
bogdanm	82:6473597d706e	1050
bogdanm	82:6473597d706e	1051	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1052	//! @brief Set the TXF field to a new value.
bogdanm	82:6473597d706e	1053	#define BW_ENET_EIMR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF) = (v))
bogdanm	82:6473597d706e	1054	#endif
bogdanm	82:6473597d706e	1055	//@}
bogdanm	82:6473597d706e	1056
bogdanm	82:6473597d706e	1057	/*!
bogdanm	82:6473597d706e	1058	* @name Register ENET_EIMR, field GRA[28] (RW)
bogdanm	82:6473597d706e	1059	*
bogdanm	82:6473597d706e	1060	* Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
bogdanm	82:6473597d706e	1061	* condition can generate an interrupt. At every module clock, the EIR samples
bogdanm	82:6473597d706e	1062	* the signal generated by the interrupting source. The corresponding EIR GRA field
bogdanm	82:6473597d706e	1063	* reflects the state of the interrupt signal even if the corresponding EIMR
bogdanm	82:6473597d706e	1064	* field is cleared.
bogdanm	82:6473597d706e	1065	*
bogdanm	82:6473597d706e	1066	* Values:
bogdanm	82:6473597d706e	1067	* - 0 - The corresponding interrupt source is masked.
bogdanm	82:6473597d706e	1068	* - 1 - The corresponding interrupt source is not masked.
bogdanm	82:6473597d706e	1069	*/
bogdanm	82:6473597d706e	1070	//@{
bogdanm	82:6473597d706e	1071	#define BP_ENET_EIMR_GRA (28U) //!< Bit position for ENET_EIMR_GRA.
bogdanm	82:6473597d706e	1072	#define BM_ENET_EIMR_GRA (0x10000000U) //!< Bit mask for ENET_EIMR_GRA.
bogdanm	82:6473597d706e	1073	#define BS_ENET_EIMR_GRA (1U) //!< Bit field size in bits for ENET_EIMR_GRA.
bogdanm	82:6473597d706e	1074
bogdanm	82:6473597d706e	1075	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1076	//! @brief Read current value of the ENET_EIMR_GRA field.
bogdanm	82:6473597d706e	1077	#define BR_ENET_EIMR_GRA(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA))
bogdanm	82:6473597d706e	1078	#endif
bogdanm	82:6473597d706e	1079
bogdanm	82:6473597d706e	1080	//! @brief Format value for bitfield ENET_EIMR_GRA.
bogdanm	82:6473597d706e	1081	#define BF_ENET_EIMR_GRA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_GRA), uint32_t) & BM_ENET_EIMR_GRA)
bogdanm	82:6473597d706e	1082
bogdanm	82:6473597d706e	1083	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1084	//! @brief Set the GRA field to a new value.
bogdanm	82:6473597d706e	1085	#define BW_ENET_EIMR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA) = (v))
bogdanm	82:6473597d706e	1086	#endif
bogdanm	82:6473597d706e	1087	//@}
bogdanm	82:6473597d706e	1088
bogdanm	82:6473597d706e	1089	/*!
bogdanm	82:6473597d706e	1090	* @name Register ENET_EIMR, field BABT[29] (RW)
bogdanm	82:6473597d706e	1091	*
bogdanm	82:6473597d706e	1092	* Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
bogdanm	82:6473597d706e	1093	* condition can generate an interrupt. At every module clock, the EIR samples
bogdanm	82:6473597d706e	1094	* the signal generated by the interrupting source. The corresponding EIR BABT
bogdanm	82:6473597d706e	1095	* field reflects the state of the interrupt signal even if the corresponding EIMR
bogdanm	82:6473597d706e	1096	* field is cleared.
bogdanm	82:6473597d706e	1097	*
bogdanm	82:6473597d706e	1098	* Values:
bogdanm	82:6473597d706e	1099	* - 0 - The corresponding interrupt source is masked.
bogdanm	82:6473597d706e	1100	* - 1 - The corresponding interrupt source is not masked.
bogdanm	82:6473597d706e	1101	*/
bogdanm	82:6473597d706e	1102	//@{
bogdanm	82:6473597d706e	1103	#define BP_ENET_EIMR_BABT (29U) //!< Bit position for ENET_EIMR_BABT.
bogdanm	82:6473597d706e	1104	#define BM_ENET_EIMR_BABT (0x20000000U) //!< Bit mask for ENET_EIMR_BABT.
bogdanm	82:6473597d706e	1105	#define BS_ENET_EIMR_BABT (1U) //!< Bit field size in bits for ENET_EIMR_BABT.
bogdanm	82:6473597d706e	1106
bogdanm	82:6473597d706e	1107	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1108	//! @brief Read current value of the ENET_EIMR_BABT field.
bogdanm	82:6473597d706e	1109	#define BR_ENET_EIMR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT))
bogdanm	82:6473597d706e	1110	#endif
bogdanm	82:6473597d706e	1111
bogdanm	82:6473597d706e	1112	//! @brief Format value for bitfield ENET_EIMR_BABT.
bogdanm	82:6473597d706e	1113	#define BF_ENET_EIMR_BABT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_BABT), uint32_t) & BM_ENET_EIMR_BABT)
bogdanm	82:6473597d706e	1114
bogdanm	82:6473597d706e	1115	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1116	//! @brief Set the BABT field to a new value.
bogdanm	82:6473597d706e	1117	#define BW_ENET_EIMR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT) = (v))
bogdanm	82:6473597d706e	1118	#endif
bogdanm	82:6473597d706e	1119	//@}
bogdanm	82:6473597d706e	1120
bogdanm	82:6473597d706e	1121	/*!
bogdanm	82:6473597d706e	1122	* @name Register ENET_EIMR, field BABR[30] (RW)
bogdanm	82:6473597d706e	1123	*
bogdanm	82:6473597d706e	1124	* Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
bogdanm	82:6473597d706e	1125	* condition can generate an interrupt. At every module clock, the EIR samples
bogdanm	82:6473597d706e	1126	* the signal generated by the interrupting source. The corresponding EIR BABR
bogdanm	82:6473597d706e	1127	* field reflects the state of the interrupt signal even if the corresponding EIMR
bogdanm	82:6473597d706e	1128	* field is cleared.
bogdanm	82:6473597d706e	1129	*
bogdanm	82:6473597d706e	1130	* Values:
bogdanm	82:6473597d706e	1131	* - 0 - The corresponding interrupt source is masked.
bogdanm	82:6473597d706e	1132	* - 1 - The corresponding interrupt source is not masked.
bogdanm	82:6473597d706e	1133	*/
bogdanm	82:6473597d706e	1134	//@{
bogdanm	82:6473597d706e	1135	#define BP_ENET_EIMR_BABR (30U) //!< Bit position for ENET_EIMR_BABR.
bogdanm	82:6473597d706e	1136	#define BM_ENET_EIMR_BABR (0x40000000U) //!< Bit mask for ENET_EIMR_BABR.
bogdanm	82:6473597d706e	1137	#define BS_ENET_EIMR_BABR (1U) //!< Bit field size in bits for ENET_EIMR_BABR.
bogdanm	82:6473597d706e	1138
bogdanm	82:6473597d706e	1139	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1140	//! @brief Read current value of the ENET_EIMR_BABR field.
bogdanm	82:6473597d706e	1141	#define BR_ENET_EIMR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR))
bogdanm	82:6473597d706e	1142	#endif
bogdanm	82:6473597d706e	1143
bogdanm	82:6473597d706e	1144	//! @brief Format value for bitfield ENET_EIMR_BABR.
bogdanm	82:6473597d706e	1145	#define BF_ENET_EIMR_BABR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_BABR), uint32_t) & BM_ENET_EIMR_BABR)
bogdanm	82:6473597d706e	1146
bogdanm	82:6473597d706e	1147	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1148	//! @brief Set the BABR field to a new value.
bogdanm	82:6473597d706e	1149	#define BW_ENET_EIMR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR) = (v))
bogdanm	82:6473597d706e	1150	#endif
bogdanm	82:6473597d706e	1151	//@}
bogdanm	82:6473597d706e	1152
bogdanm	82:6473597d706e	1153	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1154	// HW_ENET_RDAR - Receive Descriptor Active Register
bogdanm	82:6473597d706e	1155	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1156
bogdanm	82:6473597d706e	1157	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1158	/*!
bogdanm	82:6473597d706e	1159	* @brief HW_ENET_RDAR - Receive Descriptor Active Register (RW)
bogdanm	82:6473597d706e	1160	*
bogdanm	82:6473597d706e	1161	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1162	*
bogdanm	82:6473597d706e	1163	* RDAR is a command register, written by the user, to indicate that the receive
bogdanm	82:6473597d706e	1164	* descriptor ring has been updated, that is, that the driver produced empty
bogdanm	82:6473597d706e	1165	* receive buffers with the empty bit set.
bogdanm	82:6473597d706e	1166	*/
bogdanm	82:6473597d706e	1167	typedef union _hw_enet_rdar
bogdanm	82:6473597d706e	1168	{
bogdanm	82:6473597d706e	1169	uint32_t U;
bogdanm	82:6473597d706e	1170	struct _hw_enet_rdar_bitfields
bogdanm	82:6473597d706e	1171	{
bogdanm	82:6473597d706e	1172	uint32_t RESERVED0 : 24; //!< [23:0]
bogdanm	82:6473597d706e	1173	uint32_t RDAR : 1; //!< [24] Receive Descriptor Active
bogdanm	82:6473597d706e	1174	uint32_t RESERVED1 : 7; //!< [31:25]
bogdanm	82:6473597d706e	1175	} B;
bogdanm	82:6473597d706e	1176	} hw_enet_rdar_t;
bogdanm	82:6473597d706e	1177	#endif
bogdanm	82:6473597d706e	1178
bogdanm	82:6473597d706e	1179	/*!
bogdanm	82:6473597d706e	1180	* @name Constants and macros for entire ENET_RDAR register
bogdanm	82:6473597d706e	1181	*/
bogdanm	82:6473597d706e	1182	//@{
bogdanm	82:6473597d706e	1183	#define HW_ENET_RDAR_ADDR(x) (REGS_ENET_BASE(x) + 0x10U)
bogdanm	82:6473597d706e	1184
bogdanm	82:6473597d706e	1185	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1186	#define HW_ENET_RDAR(x) ((__IO hw_enet_rdar_t ) HW_ENET_RDAR_ADDR(x))
bogdanm	82:6473597d706e	1187	#define HW_ENET_RDAR_RD(x) (HW_ENET_RDAR(x).U)
bogdanm	82:6473597d706e	1188	#define HW_ENET_RDAR_WR(x, v) (HW_ENET_RDAR(x).U = (v))
bogdanm	82:6473597d706e	1189	#define HW_ENET_RDAR_SET(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) \| (v)))
bogdanm	82:6473597d706e	1190	#define HW_ENET_RDAR_CLR(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1191	#define HW_ENET_RDAR_TOG(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1192	#endif
bogdanm	82:6473597d706e	1193	//@}
bogdanm	82:6473597d706e	1194
bogdanm	82:6473597d706e	1195	/*
bogdanm	82:6473597d706e	1196	* Constants & macros for individual ENET_RDAR bitfields
bogdanm	82:6473597d706e	1197	*/
bogdanm	82:6473597d706e	1198
bogdanm	82:6473597d706e	1199	/*!
bogdanm	82:6473597d706e	1200	* @name Register ENET_RDAR, field RDAR[24] (RW)
bogdanm	82:6473597d706e	1201	*
bogdanm	82:6473597d706e	1202	* Always set to 1 when this register is written, regardless of the value
bogdanm	82:6473597d706e	1203	* written. This field is cleared by the MAC device when no additional empty
bogdanm	82:6473597d706e	1204	* descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
bogdanm	82:6473597d706e	1205	* from set to cleared or when ECR[RESET] is set.
bogdanm	82:6473597d706e	1206	*/
bogdanm	82:6473597d706e	1207	//@{
bogdanm	82:6473597d706e	1208	#define BP_ENET_RDAR_RDAR (24U) //!< Bit position for ENET_RDAR_RDAR.
bogdanm	82:6473597d706e	1209	#define BM_ENET_RDAR_RDAR (0x01000000U) //!< Bit mask for ENET_RDAR_RDAR.
bogdanm	82:6473597d706e	1210	#define BS_ENET_RDAR_RDAR (1U) //!< Bit field size in bits for ENET_RDAR_RDAR.
bogdanm	82:6473597d706e	1211
bogdanm	82:6473597d706e	1212	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1213	//! @brief Read current value of the ENET_RDAR_RDAR field.
bogdanm	82:6473597d706e	1214	#define BR_ENET_RDAR_RDAR(x) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR))
bogdanm	82:6473597d706e	1215	#endif
bogdanm	82:6473597d706e	1216
bogdanm	82:6473597d706e	1217	//! @brief Format value for bitfield ENET_RDAR_RDAR.
bogdanm	82:6473597d706e	1218	#define BF_ENET_RDAR_RDAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RDAR_RDAR), uint32_t) & BM_ENET_RDAR_RDAR)
bogdanm	82:6473597d706e	1219
bogdanm	82:6473597d706e	1220	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1221	//! @brief Set the RDAR field to a new value.
bogdanm	82:6473597d706e	1222	#define BW_ENET_RDAR_RDAR(x, v) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR) = (v))
bogdanm	82:6473597d706e	1223	#endif
bogdanm	82:6473597d706e	1224	//@}
bogdanm	82:6473597d706e	1225
bogdanm	82:6473597d706e	1226	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1227	// HW_ENET_TDAR - Transmit Descriptor Active Register
bogdanm	82:6473597d706e	1228	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1229
bogdanm	82:6473597d706e	1230	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1231	/*!
bogdanm	82:6473597d706e	1232	* @brief HW_ENET_TDAR - Transmit Descriptor Active Register (RW)
bogdanm	82:6473597d706e	1233	*
bogdanm	82:6473597d706e	1234	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1235	*
bogdanm	82:6473597d706e	1236	* The TDAR is a command register that the user writes to indicate that the
bogdanm	82:6473597d706e	1237	* transmit descriptor ring has been updated, that is, that transmit buffers have
bogdanm	82:6473597d706e	1238	* been produced by the driver with the ready bit set in the buffer descriptor. The
bogdanm	82:6473597d706e	1239	* TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
bogdanm	82:6473597d706e	1240	* cleared, or when ECR[RESET] is set.
bogdanm	82:6473597d706e	1241	*/
bogdanm	82:6473597d706e	1242	typedef union _hw_enet_tdar
bogdanm	82:6473597d706e	1243	{
bogdanm	82:6473597d706e	1244	uint32_t U;
bogdanm	82:6473597d706e	1245	struct _hw_enet_tdar_bitfields
bogdanm	82:6473597d706e	1246	{
bogdanm	82:6473597d706e	1247	uint32_t RESERVED0 : 24; //!< [23:0]
bogdanm	82:6473597d706e	1248	uint32_t TDAR : 1; //!< [24] Transmit Descriptor Active
bogdanm	82:6473597d706e	1249	uint32_t RESERVED1 : 7; //!< [31:25]
bogdanm	82:6473597d706e	1250	} B;
bogdanm	82:6473597d706e	1251	} hw_enet_tdar_t;
bogdanm	82:6473597d706e	1252	#endif
bogdanm	82:6473597d706e	1253
bogdanm	82:6473597d706e	1254	/*!
bogdanm	82:6473597d706e	1255	* @name Constants and macros for entire ENET_TDAR register
bogdanm	82:6473597d706e	1256	*/
bogdanm	82:6473597d706e	1257	//@{
bogdanm	82:6473597d706e	1258	#define HW_ENET_TDAR_ADDR(x) (REGS_ENET_BASE(x) + 0x14U)
bogdanm	82:6473597d706e	1259
bogdanm	82:6473597d706e	1260	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1261	#define HW_ENET_TDAR(x) ((__IO hw_enet_tdar_t ) HW_ENET_TDAR_ADDR(x))
bogdanm	82:6473597d706e	1262	#define HW_ENET_TDAR_RD(x) (HW_ENET_TDAR(x).U)
bogdanm	82:6473597d706e	1263	#define HW_ENET_TDAR_WR(x, v) (HW_ENET_TDAR(x).U = (v))
bogdanm	82:6473597d706e	1264	#define HW_ENET_TDAR_SET(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) \| (v)))
bogdanm	82:6473597d706e	1265	#define HW_ENET_TDAR_CLR(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1266	#define HW_ENET_TDAR_TOG(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1267	#endif
bogdanm	82:6473597d706e	1268	//@}
bogdanm	82:6473597d706e	1269
bogdanm	82:6473597d706e	1270	/*
bogdanm	82:6473597d706e	1271	* Constants & macros for individual ENET_TDAR bitfields
bogdanm	82:6473597d706e	1272	*/
bogdanm	82:6473597d706e	1273
bogdanm	82:6473597d706e	1274	/*!
bogdanm	82:6473597d706e	1275	* @name Register ENET_TDAR, field TDAR[24] (RW)
bogdanm	82:6473597d706e	1276	*
bogdanm	82:6473597d706e	1277	* Always set to 1 when this register is written, regardless of the value
bogdanm	82:6473597d706e	1278	* written. This bit is cleared by the MAC device when no additional ready descriptors
bogdanm	82:6473597d706e	1279	* remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
bogdanm	82:6473597d706e	1280	* set to cleared or when ECR[RESET] is set.
bogdanm	82:6473597d706e	1281	*/
bogdanm	82:6473597d706e	1282	//@{
bogdanm	82:6473597d706e	1283	#define BP_ENET_TDAR_TDAR (24U) //!< Bit position for ENET_TDAR_TDAR.
bogdanm	82:6473597d706e	1284	#define BM_ENET_TDAR_TDAR (0x01000000U) //!< Bit mask for ENET_TDAR_TDAR.
bogdanm	82:6473597d706e	1285	#define BS_ENET_TDAR_TDAR (1U) //!< Bit field size in bits for ENET_TDAR_TDAR.
bogdanm	82:6473597d706e	1286
bogdanm	82:6473597d706e	1287	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1288	//! @brief Read current value of the ENET_TDAR_TDAR field.
bogdanm	82:6473597d706e	1289	#define BR_ENET_TDAR_TDAR(x) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR))
bogdanm	82:6473597d706e	1290	#endif
bogdanm	82:6473597d706e	1291
bogdanm	82:6473597d706e	1292	//! @brief Format value for bitfield ENET_TDAR_TDAR.
bogdanm	82:6473597d706e	1293	#define BF_ENET_TDAR_TDAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TDAR_TDAR), uint32_t) & BM_ENET_TDAR_TDAR)
bogdanm	82:6473597d706e	1294
bogdanm	82:6473597d706e	1295	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1296	//! @brief Set the TDAR field to a new value.
bogdanm	82:6473597d706e	1297	#define BW_ENET_TDAR_TDAR(x, v) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR) = (v))
bogdanm	82:6473597d706e	1298	#endif
bogdanm	82:6473597d706e	1299	//@}
bogdanm	82:6473597d706e	1300
bogdanm	82:6473597d706e	1301	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1302	// HW_ENET_ECR - Ethernet Control Register
bogdanm	82:6473597d706e	1303	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1304
bogdanm	82:6473597d706e	1305	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1306	/*!
bogdanm	82:6473597d706e	1307	* @brief HW_ENET_ECR - Ethernet Control Register (RW)
bogdanm	82:6473597d706e	1308	*
bogdanm	82:6473597d706e	1309	* Reset value: 0xF0000000U
bogdanm	82:6473597d706e	1310	*
bogdanm	82:6473597d706e	1311	* ECR is a read/write user register, though hardware may also alter fields in
bogdanm	82:6473597d706e	1312	* this register. It controls many of the high level features of the Ethernet MAC,
bogdanm	82:6473597d706e	1313	* including legacy FEC support through the EN1588 field.
bogdanm	82:6473597d706e	1314	*/
bogdanm	82:6473597d706e	1315	typedef union _hw_enet_ecr
bogdanm	82:6473597d706e	1316	{
bogdanm	82:6473597d706e	1317	uint32_t U;
bogdanm	82:6473597d706e	1318	struct _hw_enet_ecr_bitfields
bogdanm	82:6473597d706e	1319	{
bogdanm	82:6473597d706e	1320	uint32_t RESET : 1; //!< [0] Ethernet MAC Reset
bogdanm	82:6473597d706e	1321	uint32_t ETHEREN : 1; //!< [1] Ethernet Enable
bogdanm	82:6473597d706e	1322	uint32_t MAGICEN : 1; //!< [2] Magic Packet Detection Enable
bogdanm	82:6473597d706e	1323	uint32_t SLEEP : 1; //!< [3] Sleep Mode Enable
bogdanm	82:6473597d706e	1324	uint32_t EN1588 : 1; //!< [4] EN1588 Enable
bogdanm	82:6473597d706e	1325	uint32_t RESERVED0 : 1; //!< [5]
bogdanm	82:6473597d706e	1326	uint32_t DBGEN : 1; //!< [6] Debug Enable
bogdanm	82:6473597d706e	1327	uint32_t STOPEN : 1; //!< [7] STOPEN Signal Control
bogdanm	82:6473597d706e	1328	uint32_t DBSWP : 1; //!< [8] Descriptor Byte Swapping Enable
bogdanm	82:6473597d706e	1329	uint32_t RESERVED1 : 23; //!< [31:9]
bogdanm	82:6473597d706e	1330	} B;
bogdanm	82:6473597d706e	1331	} hw_enet_ecr_t;
bogdanm	82:6473597d706e	1332	#endif
bogdanm	82:6473597d706e	1333
bogdanm	82:6473597d706e	1334	/*!
bogdanm	82:6473597d706e	1335	* @name Constants and macros for entire ENET_ECR register
bogdanm	82:6473597d706e	1336	*/
bogdanm	82:6473597d706e	1337	//@{
bogdanm	82:6473597d706e	1338	#define HW_ENET_ECR_ADDR(x) (REGS_ENET_BASE(x) + 0x24U)
bogdanm	82:6473597d706e	1339
bogdanm	82:6473597d706e	1340	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1341	#define HW_ENET_ECR(x) ((__IO hw_enet_ecr_t ) HW_ENET_ECR_ADDR(x))
bogdanm	82:6473597d706e	1342	#define HW_ENET_ECR_RD(x) (HW_ENET_ECR(x).U)
bogdanm	82:6473597d706e	1343	#define HW_ENET_ECR_WR(x, v) (HW_ENET_ECR(x).U = (v))
bogdanm	82:6473597d706e	1344	#define HW_ENET_ECR_SET(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) \| (v)))
bogdanm	82:6473597d706e	1345	#define HW_ENET_ECR_CLR(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1346	#define HW_ENET_ECR_TOG(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1347	#endif
bogdanm	82:6473597d706e	1348	//@}
bogdanm	82:6473597d706e	1349
bogdanm	82:6473597d706e	1350	/*
bogdanm	82:6473597d706e	1351	* Constants & macros for individual ENET_ECR bitfields
bogdanm	82:6473597d706e	1352	*/
bogdanm	82:6473597d706e	1353
bogdanm	82:6473597d706e	1354	/*!
bogdanm	82:6473597d706e	1355	* @name Register ENET_ECR, field RESET[0] (RW)
bogdanm	82:6473597d706e	1356	*
bogdanm	82:6473597d706e	1357	* When this field is set, it clears the ETHEREN field.
bogdanm	82:6473597d706e	1358	*/
bogdanm	82:6473597d706e	1359	//@{
bogdanm	82:6473597d706e	1360	#define BP_ENET_ECR_RESET (0U) //!< Bit position for ENET_ECR_RESET.
bogdanm	82:6473597d706e	1361	#define BM_ENET_ECR_RESET (0x00000001U) //!< Bit mask for ENET_ECR_RESET.
bogdanm	82:6473597d706e	1362	#define BS_ENET_ECR_RESET (1U) //!< Bit field size in bits for ENET_ECR_RESET.
bogdanm	82:6473597d706e	1363
bogdanm	82:6473597d706e	1364	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1365	//! @brief Read current value of the ENET_ECR_RESET field.
bogdanm	82:6473597d706e	1366	#define BR_ENET_ECR_RESET(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET))
bogdanm	82:6473597d706e	1367	#endif
bogdanm	82:6473597d706e	1368
bogdanm	82:6473597d706e	1369	//! @brief Format value for bitfield ENET_ECR_RESET.
bogdanm	82:6473597d706e	1370	#define BF_ENET_ECR_RESET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_RESET), uint32_t) & BM_ENET_ECR_RESET)
bogdanm	82:6473597d706e	1371
bogdanm	82:6473597d706e	1372	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1373	//! @brief Set the RESET field to a new value.
bogdanm	82:6473597d706e	1374	#define BW_ENET_ECR_RESET(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET) = (v))
bogdanm	82:6473597d706e	1375	#endif
bogdanm	82:6473597d706e	1376	//@}
bogdanm	82:6473597d706e	1377
bogdanm	82:6473597d706e	1378	/*!
bogdanm	82:6473597d706e	1379	* @name Register ENET_ECR, field ETHEREN[1] (RW)
bogdanm	82:6473597d706e	1380	*
bogdanm	82:6473597d706e	1381	* Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
bogdanm	82:6473597d706e	1382	* descriptors for an aborted transmit frame are not updated. The uDMA, buffer
bogdanm	82:6473597d706e	1383	* descriptor, and FIFO control logic are reset, including the buffer descriptor and
bogdanm	82:6473597d706e	1384	* FIFO pointers. Hardware clears this field under the following conditions: RESET
bogdanm	82:6473597d706e	1385	* is set by software An error condition causes the EBERR field to set. ETHEREN
bogdanm	82:6473597d706e	1386	* must be set at the very last step during ENET
bogdanm	82:6473597d706e	1387	* configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
bogdanm	82:6473597d706e	1388	* is cleared to 0 by software then then next time ETHEREN is set, the EIR
bogdanm	82:6473597d706e	1389	* interrupts must cleared to 0 due to previous pending interrupts.
bogdanm	82:6473597d706e	1390	*
bogdanm	82:6473597d706e	1391	* Values:
bogdanm	82:6473597d706e	1392	* - 0 - Reception immediately stops and transmission stops after a bad CRC is
bogdanm	82:6473597d706e	1393	* appended to any currently transmitted frame.
bogdanm	82:6473597d706e	1394	* - 1 - MAC is enabled, and reception and transmission are possible.
bogdanm	82:6473597d706e	1395	*/
bogdanm	82:6473597d706e	1396	//@{
bogdanm	82:6473597d706e	1397	#define BP_ENET_ECR_ETHEREN (1U) //!< Bit position for ENET_ECR_ETHEREN.
bogdanm	82:6473597d706e	1398	#define BM_ENET_ECR_ETHEREN (0x00000002U) //!< Bit mask for ENET_ECR_ETHEREN.
bogdanm	82:6473597d706e	1399	#define BS_ENET_ECR_ETHEREN (1U) //!< Bit field size in bits for ENET_ECR_ETHEREN.
bogdanm	82:6473597d706e	1400
bogdanm	82:6473597d706e	1401	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1402	//! @brief Read current value of the ENET_ECR_ETHEREN field.
bogdanm	82:6473597d706e	1403	#define BR_ENET_ECR_ETHEREN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN))
bogdanm	82:6473597d706e	1404	#endif
bogdanm	82:6473597d706e	1405
bogdanm	82:6473597d706e	1406	//! @brief Format value for bitfield ENET_ECR_ETHEREN.
bogdanm	82:6473597d706e	1407	#define BF_ENET_ECR_ETHEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_ETHEREN), uint32_t) & BM_ENET_ECR_ETHEREN)
bogdanm	82:6473597d706e	1408
bogdanm	82:6473597d706e	1409	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1410	//! @brief Set the ETHEREN field to a new value.
bogdanm	82:6473597d706e	1411	#define BW_ENET_ECR_ETHEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN) = (v))
bogdanm	82:6473597d706e	1412	#endif
bogdanm	82:6473597d706e	1413	//@}
bogdanm	82:6473597d706e	1414
bogdanm	82:6473597d706e	1415	/*!
bogdanm	82:6473597d706e	1416	* @name Register ENET_ECR, field MAGICEN[2] (RW)
bogdanm	82:6473597d706e	1417	*
bogdanm	82:6473597d706e	1418	* Enables/disables magic packet detection. MAGICEN is relevant only if the
bogdanm	82:6473597d706e	1419	* SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
bogdanm	82:6473597d706e	1420	* sleep mode and magic packet detection.
bogdanm	82:6473597d706e	1421	*
bogdanm	82:6473597d706e	1422	* Values:
bogdanm	82:6473597d706e	1423	* - 0 - Magic detection logic disabled.
bogdanm	82:6473597d706e	1424	* - 1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame
bogdanm	82:6473597d706e	1425	* is detected.
bogdanm	82:6473597d706e	1426	*/
bogdanm	82:6473597d706e	1427	//@{
bogdanm	82:6473597d706e	1428	#define BP_ENET_ECR_MAGICEN (2U) //!< Bit position for ENET_ECR_MAGICEN.
bogdanm	82:6473597d706e	1429	#define BM_ENET_ECR_MAGICEN (0x00000004U) //!< Bit mask for ENET_ECR_MAGICEN.
bogdanm	82:6473597d706e	1430	#define BS_ENET_ECR_MAGICEN (1U) //!< Bit field size in bits for ENET_ECR_MAGICEN.
bogdanm	82:6473597d706e	1431
bogdanm	82:6473597d706e	1432	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1433	//! @brief Read current value of the ENET_ECR_MAGICEN field.
bogdanm	82:6473597d706e	1434	#define BR_ENET_ECR_MAGICEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN))
bogdanm	82:6473597d706e	1435	#endif
bogdanm	82:6473597d706e	1436
bogdanm	82:6473597d706e	1437	//! @brief Format value for bitfield ENET_ECR_MAGICEN.
bogdanm	82:6473597d706e	1438	#define BF_ENET_ECR_MAGICEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_MAGICEN), uint32_t) & BM_ENET_ECR_MAGICEN)
bogdanm	82:6473597d706e	1439
bogdanm	82:6473597d706e	1440	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1441	//! @brief Set the MAGICEN field to a new value.
bogdanm	82:6473597d706e	1442	#define BW_ENET_ECR_MAGICEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN) = (v))
bogdanm	82:6473597d706e	1443	#endif
bogdanm	82:6473597d706e	1444	//@}
bogdanm	82:6473597d706e	1445
bogdanm	82:6473597d706e	1446	/*!
bogdanm	82:6473597d706e	1447	* @name Register ENET_ECR, field SLEEP[3] (RW)
bogdanm	82:6473597d706e	1448	*
bogdanm	82:6473597d706e	1449	* Values:
bogdanm	82:6473597d706e	1450	* - 0 - Normal operating mode.
bogdanm	82:6473597d706e	1451	* - 1 - Sleep mode.
bogdanm	82:6473597d706e	1452	*/
bogdanm	82:6473597d706e	1453	//@{
bogdanm	82:6473597d706e	1454	#define BP_ENET_ECR_SLEEP (3U) //!< Bit position for ENET_ECR_SLEEP.
bogdanm	82:6473597d706e	1455	#define BM_ENET_ECR_SLEEP (0x00000008U) //!< Bit mask for ENET_ECR_SLEEP.
bogdanm	82:6473597d706e	1456	#define BS_ENET_ECR_SLEEP (1U) //!< Bit field size in bits for ENET_ECR_SLEEP.
bogdanm	82:6473597d706e	1457
bogdanm	82:6473597d706e	1458	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1459	//! @brief Read current value of the ENET_ECR_SLEEP field.
bogdanm	82:6473597d706e	1460	#define BR_ENET_ECR_SLEEP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP))
bogdanm	82:6473597d706e	1461	#endif
bogdanm	82:6473597d706e	1462
bogdanm	82:6473597d706e	1463	//! @brief Format value for bitfield ENET_ECR_SLEEP.
bogdanm	82:6473597d706e	1464	#define BF_ENET_ECR_SLEEP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_SLEEP), uint32_t) & BM_ENET_ECR_SLEEP)
bogdanm	82:6473597d706e	1465
bogdanm	82:6473597d706e	1466	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1467	//! @brief Set the SLEEP field to a new value.
bogdanm	82:6473597d706e	1468	#define BW_ENET_ECR_SLEEP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP) = (v))
bogdanm	82:6473597d706e	1469	#endif
bogdanm	82:6473597d706e	1470	//@}
bogdanm	82:6473597d706e	1471
bogdanm	82:6473597d706e	1472	/*!
bogdanm	82:6473597d706e	1473	* @name Register ENET_ECR, field EN1588[4] (RW)
bogdanm	82:6473597d706e	1474	*
bogdanm	82:6473597d706e	1475	* Enables enhanced functionality of the MAC.
bogdanm	82:6473597d706e	1476	*
bogdanm	82:6473597d706e	1477	* Values:
bogdanm	82:6473597d706e	1478	* - 0 - Legacy FEC buffer descriptors and functions enabled.
bogdanm	82:6473597d706e	1479	* - 1 - Enhanced frame time-stamping functions enabled.
bogdanm	82:6473597d706e	1480	*/
bogdanm	82:6473597d706e	1481	//@{
bogdanm	82:6473597d706e	1482	#define BP_ENET_ECR_EN1588 (4U) //!< Bit position for ENET_ECR_EN1588.
bogdanm	82:6473597d706e	1483	#define BM_ENET_ECR_EN1588 (0x00000010U) //!< Bit mask for ENET_ECR_EN1588.
bogdanm	82:6473597d706e	1484	#define BS_ENET_ECR_EN1588 (1U) //!< Bit field size in bits for ENET_ECR_EN1588.
bogdanm	82:6473597d706e	1485
bogdanm	82:6473597d706e	1486	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1487	//! @brief Read current value of the ENET_ECR_EN1588 field.
bogdanm	82:6473597d706e	1488	#define BR_ENET_ECR_EN1588(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588))
bogdanm	82:6473597d706e	1489	#endif
bogdanm	82:6473597d706e	1490
bogdanm	82:6473597d706e	1491	//! @brief Format value for bitfield ENET_ECR_EN1588.
bogdanm	82:6473597d706e	1492	#define BF_ENET_ECR_EN1588(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_EN1588), uint32_t) & BM_ENET_ECR_EN1588)
bogdanm	82:6473597d706e	1493
bogdanm	82:6473597d706e	1494	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1495	//! @brief Set the EN1588 field to a new value.
bogdanm	82:6473597d706e	1496	#define BW_ENET_ECR_EN1588(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588) = (v))
bogdanm	82:6473597d706e	1497	#endif
bogdanm	82:6473597d706e	1498	//@}
bogdanm	82:6473597d706e	1499
bogdanm	82:6473597d706e	1500	/*!
bogdanm	82:6473597d706e	1501	* @name Register ENET_ECR, field DBGEN[6] (RW)
bogdanm	82:6473597d706e	1502	*
bogdanm	82:6473597d706e	1503	* Enables the MAC to enter hardware freeze mode when the device enters debug
bogdanm	82:6473597d706e	1504	* mode.
bogdanm	82:6473597d706e	1505	*
bogdanm	82:6473597d706e	1506	* Values:
bogdanm	82:6473597d706e	1507	* - 0 - MAC continues operation in debug mode.
bogdanm	82:6473597d706e	1508	* - 1 - MAC enters hardware freeze mode when the processor is in debug mode.
bogdanm	82:6473597d706e	1509	*/
bogdanm	82:6473597d706e	1510	//@{
bogdanm	82:6473597d706e	1511	#define BP_ENET_ECR_DBGEN (6U) //!< Bit position for ENET_ECR_DBGEN.
bogdanm	82:6473597d706e	1512	#define BM_ENET_ECR_DBGEN (0x00000040U) //!< Bit mask for ENET_ECR_DBGEN.
bogdanm	82:6473597d706e	1513	#define BS_ENET_ECR_DBGEN (1U) //!< Bit field size in bits for ENET_ECR_DBGEN.
bogdanm	82:6473597d706e	1514
bogdanm	82:6473597d706e	1515	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1516	//! @brief Read current value of the ENET_ECR_DBGEN field.
bogdanm	82:6473597d706e	1517	#define BR_ENET_ECR_DBGEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN))
bogdanm	82:6473597d706e	1518	#endif
bogdanm	82:6473597d706e	1519
bogdanm	82:6473597d706e	1520	//! @brief Format value for bitfield ENET_ECR_DBGEN.
bogdanm	82:6473597d706e	1521	#define BF_ENET_ECR_DBGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_DBGEN), uint32_t) & BM_ENET_ECR_DBGEN)
bogdanm	82:6473597d706e	1522
bogdanm	82:6473597d706e	1523	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1524	//! @brief Set the DBGEN field to a new value.
bogdanm	82:6473597d706e	1525	#define BW_ENET_ECR_DBGEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN) = (v))
bogdanm	82:6473597d706e	1526	#endif
bogdanm	82:6473597d706e	1527	//@}
bogdanm	82:6473597d706e	1528
bogdanm	82:6473597d706e	1529	/*!
bogdanm	82:6473597d706e	1530	* @name Register ENET_ECR, field STOPEN[7] (RW)
bogdanm	82:6473597d706e	1531	*
bogdanm	82:6473597d706e	1532	* Controls device behavior in doze mode. In doze mode, if this field is set
bogdanm	82:6473597d706e	1533	* then all the clocks of the ENET assembly are disabled, except the RMII /MII
bogdanm	82:6473597d706e	1534	* clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
bogdanm	82:6473597d706e	1535	* depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
bogdanm	82:6473597d706e	1536	* can still wake the system after receiving a magic packet in stop mode. MAGICEN
bogdanm	82:6473597d706e	1537	* must be set prior to entering sleep/stop mode.
bogdanm	82:6473597d706e	1538	*/
bogdanm	82:6473597d706e	1539	//@{
bogdanm	82:6473597d706e	1540	#define BP_ENET_ECR_STOPEN (7U) //!< Bit position for ENET_ECR_STOPEN.
bogdanm	82:6473597d706e	1541	#define BM_ENET_ECR_STOPEN (0x00000080U) //!< Bit mask for ENET_ECR_STOPEN.
bogdanm	82:6473597d706e	1542	#define BS_ENET_ECR_STOPEN (1U) //!< Bit field size in bits for ENET_ECR_STOPEN.
bogdanm	82:6473597d706e	1543
bogdanm	82:6473597d706e	1544	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1545	//! @brief Read current value of the ENET_ECR_STOPEN field.
bogdanm	82:6473597d706e	1546	#define BR_ENET_ECR_STOPEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN))
bogdanm	82:6473597d706e	1547	#endif
bogdanm	82:6473597d706e	1548
bogdanm	82:6473597d706e	1549	//! @brief Format value for bitfield ENET_ECR_STOPEN.
bogdanm	82:6473597d706e	1550	#define BF_ENET_ECR_STOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_STOPEN), uint32_t) & BM_ENET_ECR_STOPEN)
bogdanm	82:6473597d706e	1551
bogdanm	82:6473597d706e	1552	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1553	//! @brief Set the STOPEN field to a new value.
bogdanm	82:6473597d706e	1554	#define BW_ENET_ECR_STOPEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN) = (v))
bogdanm	82:6473597d706e	1555	#endif
bogdanm	82:6473597d706e	1556	//@}
bogdanm	82:6473597d706e	1557
bogdanm	82:6473597d706e	1558	/*!
bogdanm	82:6473597d706e	1559	* @name Register ENET_ECR, field DBSWP[8] (RW)
bogdanm	82:6473597d706e	1560	*
bogdanm	82:6473597d706e	1561	* Swaps the byte locations of the buffer descriptors. This field must be
bogdanm	82:6473597d706e	1562	* written to 1 after reset.
bogdanm	82:6473597d706e	1563	*
bogdanm	82:6473597d706e	1564	* Values:
bogdanm	82:6473597d706e	1565	* - 0 - The buffer descriptor bytes are not swapped to support big-endian
bogdanm	82:6473597d706e	1566	* devices.
bogdanm	82:6473597d706e	1567	* - 1 - The buffer descriptor bytes are swapped to support little-endian
bogdanm	82:6473597d706e	1568	* devices.
bogdanm	82:6473597d706e	1569	*/
bogdanm	82:6473597d706e	1570	//@{
bogdanm	82:6473597d706e	1571	#define BP_ENET_ECR_DBSWP (8U) //!< Bit position for ENET_ECR_DBSWP.
bogdanm	82:6473597d706e	1572	#define BM_ENET_ECR_DBSWP (0x00000100U) //!< Bit mask for ENET_ECR_DBSWP.
bogdanm	82:6473597d706e	1573	#define BS_ENET_ECR_DBSWP (1U) //!< Bit field size in bits for ENET_ECR_DBSWP.
bogdanm	82:6473597d706e	1574
bogdanm	82:6473597d706e	1575	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1576	//! @brief Read current value of the ENET_ECR_DBSWP field.
bogdanm	82:6473597d706e	1577	#define BR_ENET_ECR_DBSWP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP))
bogdanm	82:6473597d706e	1578	#endif
bogdanm	82:6473597d706e	1579
bogdanm	82:6473597d706e	1580	//! @brief Format value for bitfield ENET_ECR_DBSWP.
bogdanm	82:6473597d706e	1581	#define BF_ENET_ECR_DBSWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_DBSWP), uint32_t) & BM_ENET_ECR_DBSWP)
bogdanm	82:6473597d706e	1582
bogdanm	82:6473597d706e	1583	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1584	//! @brief Set the DBSWP field to a new value.
bogdanm	82:6473597d706e	1585	#define BW_ENET_ECR_DBSWP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP) = (v))
bogdanm	82:6473597d706e	1586	#endif
bogdanm	82:6473597d706e	1587	//@}
bogdanm	82:6473597d706e	1588
bogdanm	82:6473597d706e	1589	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1590	// HW_ENET_MMFR - MII Management Frame Register
bogdanm	82:6473597d706e	1591	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1592
bogdanm	82:6473597d706e	1593	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1594	/*!
bogdanm	82:6473597d706e	1595	* @brief HW_ENET_MMFR - MII Management Frame Register (RW)
bogdanm	82:6473597d706e	1596	*
bogdanm	82:6473597d706e	1597	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1598	*
bogdanm	82:6473597d706e	1599	* Writing to MMFR triggers a management frame transaction to the PHY device
bogdanm	82:6473597d706e	1600	* unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
bogdanm	82:6473597d706e	1601	* during a write to MMFR, an MII frame is generated with the data previously written
bogdanm	82:6473597d706e	1602	* to the MMFR. This allows MMFR and MSCR to be programmed in either order if
bogdanm	82:6473597d706e	1603	* MSCR is currently zero. If the MMFR register is written while frame generation is
bogdanm	82:6473597d706e	1604	* in progress, the frame contents are altered. Software must use the EIR[MII]
bogdanm	82:6473597d706e	1605	* interrupt indication to avoid writing to the MMFR register while frame
bogdanm	82:6473597d706e	1606	* generation is in progress.
bogdanm	82:6473597d706e	1607	*/
bogdanm	82:6473597d706e	1608	typedef union _hw_enet_mmfr
bogdanm	82:6473597d706e	1609	{
bogdanm	82:6473597d706e	1610	uint32_t U;
bogdanm	82:6473597d706e	1611	struct _hw_enet_mmfr_bitfields
bogdanm	82:6473597d706e	1612	{
bogdanm	82:6473597d706e	1613	uint32_t DATA : 16; //!< [15:0] Management Frame Data
bogdanm	82:6473597d706e	1614	uint32_t TA : 2; //!< [17:16] Turn Around
bogdanm	82:6473597d706e	1615	uint32_t RA : 5; //!< [22:18] Register Address
bogdanm	82:6473597d706e	1616	uint32_t PA : 5; //!< [27:23] PHY Address
bogdanm	82:6473597d706e	1617	uint32_t OP : 2; //!< [29:28] Operation Code
bogdanm	82:6473597d706e	1618	uint32_t ST : 2; //!< [31:30] Start Of Frame Delimiter
bogdanm	82:6473597d706e	1619	} B;
bogdanm	82:6473597d706e	1620	} hw_enet_mmfr_t;
bogdanm	82:6473597d706e	1621	#endif
bogdanm	82:6473597d706e	1622
bogdanm	82:6473597d706e	1623	/*!
bogdanm	82:6473597d706e	1624	* @name Constants and macros for entire ENET_MMFR register
bogdanm	82:6473597d706e	1625	*/
bogdanm	82:6473597d706e	1626	//@{
bogdanm	82:6473597d706e	1627	#define HW_ENET_MMFR_ADDR(x) (REGS_ENET_BASE(x) + 0x40U)
bogdanm	82:6473597d706e	1628
bogdanm	82:6473597d706e	1629	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1630	#define HW_ENET_MMFR(x) ((__IO hw_enet_mmfr_t ) HW_ENET_MMFR_ADDR(x))
bogdanm	82:6473597d706e	1631	#define HW_ENET_MMFR_RD(x) (HW_ENET_MMFR(x).U)
bogdanm	82:6473597d706e	1632	#define HW_ENET_MMFR_WR(x, v) (HW_ENET_MMFR(x).U = (v))
bogdanm	82:6473597d706e	1633	#define HW_ENET_MMFR_SET(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) \| (v)))
bogdanm	82:6473597d706e	1634	#define HW_ENET_MMFR_CLR(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1635	#define HW_ENET_MMFR_TOG(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1636	#endif
bogdanm	82:6473597d706e	1637	//@}
bogdanm	82:6473597d706e	1638
bogdanm	82:6473597d706e	1639	/*
bogdanm	82:6473597d706e	1640	* Constants & macros for individual ENET_MMFR bitfields
bogdanm	82:6473597d706e	1641	*/
bogdanm	82:6473597d706e	1642
bogdanm	82:6473597d706e	1643	/*!
bogdanm	82:6473597d706e	1644	* @name Register ENET_MMFR, field DATA[15:0] (RW)
bogdanm	82:6473597d706e	1645	*
bogdanm	82:6473597d706e	1646	* This is the field for data to be written to or read from the PHY register.
bogdanm	82:6473597d706e	1647	*/
bogdanm	82:6473597d706e	1648	//@{
bogdanm	82:6473597d706e	1649	#define BP_ENET_MMFR_DATA (0U) //!< Bit position for ENET_MMFR_DATA.
bogdanm	82:6473597d706e	1650	#define BM_ENET_MMFR_DATA (0x0000FFFFU) //!< Bit mask for ENET_MMFR_DATA.
bogdanm	82:6473597d706e	1651	#define BS_ENET_MMFR_DATA (16U) //!< Bit field size in bits for ENET_MMFR_DATA.
bogdanm	82:6473597d706e	1652
bogdanm	82:6473597d706e	1653	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1654	//! @brief Read current value of the ENET_MMFR_DATA field.
bogdanm	82:6473597d706e	1655	#define BR_ENET_MMFR_DATA(x) (HW_ENET_MMFR(x).B.DATA)
bogdanm	82:6473597d706e	1656	#endif
bogdanm	82:6473597d706e	1657
bogdanm	82:6473597d706e	1658	//! @brief Format value for bitfield ENET_MMFR_DATA.
bogdanm	82:6473597d706e	1659	#define BF_ENET_MMFR_DATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_DATA), uint32_t) & BM_ENET_MMFR_DATA)
bogdanm	82:6473597d706e	1660
bogdanm	82:6473597d706e	1661	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1662	//! @brief Set the DATA field to a new value.
bogdanm	82:6473597d706e	1663	#define BW_ENET_MMFR_DATA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_DATA) \| BF_ENET_MMFR_DATA(v)))
bogdanm	82:6473597d706e	1664	#endif
bogdanm	82:6473597d706e	1665	//@}
bogdanm	82:6473597d706e	1666
bogdanm	82:6473597d706e	1667	/*!
bogdanm	82:6473597d706e	1668	* @name Register ENET_MMFR, field TA[17:16] (RW)
bogdanm	82:6473597d706e	1669	*
bogdanm	82:6473597d706e	1670	* This field must be programmed to 10 to generate a valid MII management frame.
bogdanm	82:6473597d706e	1671	*/
bogdanm	82:6473597d706e	1672	//@{
bogdanm	82:6473597d706e	1673	#define BP_ENET_MMFR_TA (16U) //!< Bit position for ENET_MMFR_TA.
bogdanm	82:6473597d706e	1674	#define BM_ENET_MMFR_TA (0x00030000U) //!< Bit mask for ENET_MMFR_TA.
bogdanm	82:6473597d706e	1675	#define BS_ENET_MMFR_TA (2U) //!< Bit field size in bits for ENET_MMFR_TA.
bogdanm	82:6473597d706e	1676
bogdanm	82:6473597d706e	1677	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1678	//! @brief Read current value of the ENET_MMFR_TA field.
bogdanm	82:6473597d706e	1679	#define BR_ENET_MMFR_TA(x) (HW_ENET_MMFR(x).B.TA)
bogdanm	82:6473597d706e	1680	#endif
bogdanm	82:6473597d706e	1681
bogdanm	82:6473597d706e	1682	//! @brief Format value for bitfield ENET_MMFR_TA.
bogdanm	82:6473597d706e	1683	#define BF_ENET_MMFR_TA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_TA), uint32_t) & BM_ENET_MMFR_TA)
bogdanm	82:6473597d706e	1684
bogdanm	82:6473597d706e	1685	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1686	//! @brief Set the TA field to a new value.
bogdanm	82:6473597d706e	1687	#define BW_ENET_MMFR_TA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_TA) \| BF_ENET_MMFR_TA(v)))
bogdanm	82:6473597d706e	1688	#endif
bogdanm	82:6473597d706e	1689	//@}
bogdanm	82:6473597d706e	1690
bogdanm	82:6473597d706e	1691	/*!
bogdanm	82:6473597d706e	1692	* @name Register ENET_MMFR, field RA[22:18] (RW)
bogdanm	82:6473597d706e	1693	*
bogdanm	82:6473597d706e	1694	* Specifies one of up to 32 registers within the specified PHY device.
bogdanm	82:6473597d706e	1695	*/
bogdanm	82:6473597d706e	1696	//@{
bogdanm	82:6473597d706e	1697	#define BP_ENET_MMFR_RA (18U) //!< Bit position for ENET_MMFR_RA.
bogdanm	82:6473597d706e	1698	#define BM_ENET_MMFR_RA (0x007C0000U) //!< Bit mask for ENET_MMFR_RA.
bogdanm	82:6473597d706e	1699	#define BS_ENET_MMFR_RA (5U) //!< Bit field size in bits for ENET_MMFR_RA.
bogdanm	82:6473597d706e	1700
bogdanm	82:6473597d706e	1701	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1702	//! @brief Read current value of the ENET_MMFR_RA field.
bogdanm	82:6473597d706e	1703	#define BR_ENET_MMFR_RA(x) (HW_ENET_MMFR(x).B.RA)
bogdanm	82:6473597d706e	1704	#endif
bogdanm	82:6473597d706e	1705
bogdanm	82:6473597d706e	1706	//! @brief Format value for bitfield ENET_MMFR_RA.
bogdanm	82:6473597d706e	1707	#define BF_ENET_MMFR_RA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_RA), uint32_t) & BM_ENET_MMFR_RA)
bogdanm	82:6473597d706e	1708
bogdanm	82:6473597d706e	1709	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1710	//! @brief Set the RA field to a new value.
bogdanm	82:6473597d706e	1711	#define BW_ENET_MMFR_RA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_RA) \| BF_ENET_MMFR_RA(v)))
bogdanm	82:6473597d706e	1712	#endif
bogdanm	82:6473597d706e	1713	//@}
bogdanm	82:6473597d706e	1714
bogdanm	82:6473597d706e	1715	/*!
bogdanm	82:6473597d706e	1716	* @name Register ENET_MMFR, field PA[27:23] (RW)
bogdanm	82:6473597d706e	1717	*
bogdanm	82:6473597d706e	1718	* Specifies one of up to 32 attached PHY devices.
bogdanm	82:6473597d706e	1719	*/
bogdanm	82:6473597d706e	1720	//@{
bogdanm	82:6473597d706e	1721	#define BP_ENET_MMFR_PA (23U) //!< Bit position for ENET_MMFR_PA.
bogdanm	82:6473597d706e	1722	#define BM_ENET_MMFR_PA (0x0F800000U) //!< Bit mask for ENET_MMFR_PA.
bogdanm	82:6473597d706e	1723	#define BS_ENET_MMFR_PA (5U) //!< Bit field size in bits for ENET_MMFR_PA.
bogdanm	82:6473597d706e	1724
bogdanm	82:6473597d706e	1725	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1726	//! @brief Read current value of the ENET_MMFR_PA field.
bogdanm	82:6473597d706e	1727	#define BR_ENET_MMFR_PA(x) (HW_ENET_MMFR(x).B.PA)
bogdanm	82:6473597d706e	1728	#endif
bogdanm	82:6473597d706e	1729
bogdanm	82:6473597d706e	1730	//! @brief Format value for bitfield ENET_MMFR_PA.
bogdanm	82:6473597d706e	1731	#define BF_ENET_MMFR_PA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_PA), uint32_t) & BM_ENET_MMFR_PA)
bogdanm	82:6473597d706e	1732
bogdanm	82:6473597d706e	1733	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1734	//! @brief Set the PA field to a new value.
bogdanm	82:6473597d706e	1735	#define BW_ENET_MMFR_PA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_PA) \| BF_ENET_MMFR_PA(v)))
bogdanm	82:6473597d706e	1736	#endif
bogdanm	82:6473597d706e	1737	//@}
bogdanm	82:6473597d706e	1738
bogdanm	82:6473597d706e	1739	/*!
bogdanm	82:6473597d706e	1740	* @name Register ENET_MMFR, field OP[29:28] (RW)
bogdanm	82:6473597d706e	1741	*
bogdanm	82:6473597d706e	1742	* Determines the frame operation.
bogdanm	82:6473597d706e	1743	*
bogdanm	82:6473597d706e	1744	* Values:
bogdanm	82:6473597d706e	1745	* - 00 - Write frame operation, but not MII compliant.
bogdanm	82:6473597d706e	1746	* - 01 - Write frame operation for a valid MII management frame.
bogdanm	82:6473597d706e	1747	* - 10 - Read frame operation for a valid MII management frame.
bogdanm	82:6473597d706e	1748	* - 11 - Read frame operation, but not MII compliant.
bogdanm	82:6473597d706e	1749	*/
bogdanm	82:6473597d706e	1750	//@{
bogdanm	82:6473597d706e	1751	#define BP_ENET_MMFR_OP (28U) //!< Bit position for ENET_MMFR_OP.
bogdanm	82:6473597d706e	1752	#define BM_ENET_MMFR_OP (0x30000000U) //!< Bit mask for ENET_MMFR_OP.
bogdanm	82:6473597d706e	1753	#define BS_ENET_MMFR_OP (2U) //!< Bit field size in bits for ENET_MMFR_OP.
bogdanm	82:6473597d706e	1754
bogdanm	82:6473597d706e	1755	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1756	//! @brief Read current value of the ENET_MMFR_OP field.
bogdanm	82:6473597d706e	1757	#define BR_ENET_MMFR_OP(x) (HW_ENET_MMFR(x).B.OP)
bogdanm	82:6473597d706e	1758	#endif
bogdanm	82:6473597d706e	1759
bogdanm	82:6473597d706e	1760	//! @brief Format value for bitfield ENET_MMFR_OP.
bogdanm	82:6473597d706e	1761	#define BF_ENET_MMFR_OP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_OP), uint32_t) & BM_ENET_MMFR_OP)
bogdanm	82:6473597d706e	1762
bogdanm	82:6473597d706e	1763	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1764	//! @brief Set the OP field to a new value.
bogdanm	82:6473597d706e	1765	#define BW_ENET_MMFR_OP(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_OP) \| BF_ENET_MMFR_OP(v)))
bogdanm	82:6473597d706e	1766	#endif
bogdanm	82:6473597d706e	1767	//@}
bogdanm	82:6473597d706e	1768
bogdanm	82:6473597d706e	1769	/*!
bogdanm	82:6473597d706e	1770	* @name Register ENET_MMFR, field ST[31:30] (RW)
bogdanm	82:6473597d706e	1771	*
bogdanm	82:6473597d706e	1772	* These fields must be programmed to 01 for a valid MII management frame.
bogdanm	82:6473597d706e	1773	*/
bogdanm	82:6473597d706e	1774	//@{
bogdanm	82:6473597d706e	1775	#define BP_ENET_MMFR_ST (30U) //!< Bit position for ENET_MMFR_ST.
bogdanm	82:6473597d706e	1776	#define BM_ENET_MMFR_ST (0xC0000000U) //!< Bit mask for ENET_MMFR_ST.
bogdanm	82:6473597d706e	1777	#define BS_ENET_MMFR_ST (2U) //!< Bit field size in bits for ENET_MMFR_ST.
bogdanm	82:6473597d706e	1778
bogdanm	82:6473597d706e	1779	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1780	//! @brief Read current value of the ENET_MMFR_ST field.
bogdanm	82:6473597d706e	1781	#define BR_ENET_MMFR_ST(x) (HW_ENET_MMFR(x).B.ST)
bogdanm	82:6473597d706e	1782	#endif
bogdanm	82:6473597d706e	1783
bogdanm	82:6473597d706e	1784	//! @brief Format value for bitfield ENET_MMFR_ST.
bogdanm	82:6473597d706e	1785	#define BF_ENET_MMFR_ST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_ST), uint32_t) & BM_ENET_MMFR_ST)
bogdanm	82:6473597d706e	1786
bogdanm	82:6473597d706e	1787	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1788	//! @brief Set the ST field to a new value.
bogdanm	82:6473597d706e	1789	#define BW_ENET_MMFR_ST(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_ST) \| BF_ENET_MMFR_ST(v)))
bogdanm	82:6473597d706e	1790	#endif
bogdanm	82:6473597d706e	1791	//@}
bogdanm	82:6473597d706e	1792
bogdanm	82:6473597d706e	1793	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1794	// HW_ENET_MSCR - MII Speed Control Register
bogdanm	82:6473597d706e	1795	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1796
bogdanm	82:6473597d706e	1797	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1798	/*!
bogdanm	82:6473597d706e	1799	* @brief HW_ENET_MSCR - MII Speed Control Register (RW)
bogdanm	82:6473597d706e	1800	*
bogdanm	82:6473597d706e	1801	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1802	*
bogdanm	82:6473597d706e	1803	* MSCR provides control of the MII clock (MDC pin) frequency and allows a
bogdanm	82:6473597d706e	1804	* preamble drop on the MII management frame. The MII_SPEED field must be programmed
bogdanm	82:6473597d706e	1805	* with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
bogdanm	82:6473597d706e	1806	* compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
bogdanm	82:6473597d706e	1807	* a non-zero value to source a read or write management frame. After the
bogdanm	82:6473597d706e	1808	* management frame is complete, the MSCR register may optionally be cleared to turn
bogdanm	82:6473597d706e	1809	* off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
bogdanm	82:6473597d706e	1810	* changes during operation. This change takes effect following a rising or falling
bogdanm	82:6473597d706e	1811	* edge of MDC. If the internal module clock is 25 MHz, programming this register
bogdanm	82:6473597d706e	1812	* to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
bogdanm	82:6473597d706e	1813	* / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
bogdanm	82:6473597d706e	1814	* MII_SPEED as a function of internal module clock frequency. Programming Examples
bogdanm	82:6473597d706e	1815	* for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
bogdanm	82:6473597d706e	1816	* 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
bogdanm	82:6473597d706e	1817	* 0xD 2.36 MHz
bogdanm	82:6473597d706e	1818	*/
bogdanm	82:6473597d706e	1819	typedef union _hw_enet_mscr
bogdanm	82:6473597d706e	1820	{
bogdanm	82:6473597d706e	1821	uint32_t U;
bogdanm	82:6473597d706e	1822	struct _hw_enet_mscr_bitfields
bogdanm	82:6473597d706e	1823	{
bogdanm	82:6473597d706e	1824	uint32_t RESERVED0 : 1; //!< [0]
bogdanm	82:6473597d706e	1825	uint32_t MII_SPEED : 6; //!< [6:1] MII Speed
bogdanm	82:6473597d706e	1826	uint32_t DIS_PRE : 1; //!< [7] Disable Preamble
bogdanm	82:6473597d706e	1827	uint32_t HOLDTIME : 3; //!< [10:8] Hold time On MDIO Output
bogdanm	82:6473597d706e	1828	uint32_t RESERVED1 : 21; //!< [31:11]
bogdanm	82:6473597d706e	1829	} B;
bogdanm	82:6473597d706e	1830	} hw_enet_mscr_t;
bogdanm	82:6473597d706e	1831	#endif
bogdanm	82:6473597d706e	1832
bogdanm	82:6473597d706e	1833	/*!
bogdanm	82:6473597d706e	1834	* @name Constants and macros for entire ENET_MSCR register
bogdanm	82:6473597d706e	1835	*/
bogdanm	82:6473597d706e	1836	//@{
bogdanm	82:6473597d706e	1837	#define HW_ENET_MSCR_ADDR(x) (REGS_ENET_BASE(x) + 0x44U)
bogdanm	82:6473597d706e	1838
bogdanm	82:6473597d706e	1839	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1840	#define HW_ENET_MSCR(x) ((__IO hw_enet_mscr_t ) HW_ENET_MSCR_ADDR(x))
bogdanm	82:6473597d706e	1841	#define HW_ENET_MSCR_RD(x) (HW_ENET_MSCR(x).U)
bogdanm	82:6473597d706e	1842	#define HW_ENET_MSCR_WR(x, v) (HW_ENET_MSCR(x).U = (v))
bogdanm	82:6473597d706e	1843	#define HW_ENET_MSCR_SET(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) \| (v)))
bogdanm	82:6473597d706e	1844	#define HW_ENET_MSCR_CLR(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1845	#define HW_ENET_MSCR_TOG(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1846	#endif
bogdanm	82:6473597d706e	1847	//@}
bogdanm	82:6473597d706e	1848
bogdanm	82:6473597d706e	1849	/*
bogdanm	82:6473597d706e	1850	* Constants & macros for individual ENET_MSCR bitfields
bogdanm	82:6473597d706e	1851	*/
bogdanm	82:6473597d706e	1852
bogdanm	82:6473597d706e	1853	/*!
bogdanm	82:6473597d706e	1854	* @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
bogdanm	82:6473597d706e	1855	*
bogdanm	82:6473597d706e	1856	* Controls the frequency of the MII management interface clock (MDC) relative
bogdanm	82:6473597d706e	1857	* to the internal module clock. A value of 0 in this field turns off MDC and
bogdanm	82:6473597d706e	1858	* leaves it in low voltage state. Any non-zero value results in the MDC frequency
bogdanm	82:6473597d706e	1859	* of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
bogdanm	82:6473597d706e	1860	*/
bogdanm	82:6473597d706e	1861	//@{
bogdanm	82:6473597d706e	1862	#define BP_ENET_MSCR_MII_SPEED (1U) //!< Bit position for ENET_MSCR_MII_SPEED.
bogdanm	82:6473597d706e	1863	#define BM_ENET_MSCR_MII_SPEED (0x0000007EU) //!< Bit mask for ENET_MSCR_MII_SPEED.
bogdanm	82:6473597d706e	1864	#define BS_ENET_MSCR_MII_SPEED (6U) //!< Bit field size in bits for ENET_MSCR_MII_SPEED.
bogdanm	82:6473597d706e	1865
bogdanm	82:6473597d706e	1866	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1867	//! @brief Read current value of the ENET_MSCR_MII_SPEED field.
bogdanm	82:6473597d706e	1868	#define BR_ENET_MSCR_MII_SPEED(x) (HW_ENET_MSCR(x).B.MII_SPEED)
bogdanm	82:6473597d706e	1869	#endif
bogdanm	82:6473597d706e	1870
bogdanm	82:6473597d706e	1871	//! @brief Format value for bitfield ENET_MSCR_MII_SPEED.
bogdanm	82:6473597d706e	1872	#define BF_ENET_MSCR_MII_SPEED(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_MII_SPEED), uint32_t) & BM_ENET_MSCR_MII_SPEED)
bogdanm	82:6473597d706e	1873
bogdanm	82:6473597d706e	1874	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1875	//! @brief Set the MII_SPEED field to a new value.
bogdanm	82:6473597d706e	1876	#define BW_ENET_MSCR_MII_SPEED(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_MII_SPEED) \| BF_ENET_MSCR_MII_SPEED(v)))
bogdanm	82:6473597d706e	1877	#endif
bogdanm	82:6473597d706e	1878	//@}
bogdanm	82:6473597d706e	1879
bogdanm	82:6473597d706e	1880	/*!
bogdanm	82:6473597d706e	1881	* @name Register ENET_MSCR, field DIS_PRE[7] (RW)
bogdanm	82:6473597d706e	1882	*
bogdanm	82:6473597d706e	1883	* Enables/disables prepending a preamble to the MII management frame. The MII
bogdanm	82:6473597d706e	1884	* standard allows the preamble to be dropped if the attached PHY devices do not
bogdanm	82:6473597d706e	1885	* require it.
bogdanm	82:6473597d706e	1886	*
bogdanm	82:6473597d706e	1887	* Values:
bogdanm	82:6473597d706e	1888	* - 0 - Preamble enabled.
bogdanm	82:6473597d706e	1889	* - 1 - Preamble (32 ones) is not prepended to the MII management frame.
bogdanm	82:6473597d706e	1890	*/
bogdanm	82:6473597d706e	1891	//@{
bogdanm	82:6473597d706e	1892	#define BP_ENET_MSCR_DIS_PRE (7U) //!< Bit position for ENET_MSCR_DIS_PRE.
bogdanm	82:6473597d706e	1893	#define BM_ENET_MSCR_DIS_PRE (0x00000080U) //!< Bit mask for ENET_MSCR_DIS_PRE.
bogdanm	82:6473597d706e	1894	#define BS_ENET_MSCR_DIS_PRE (1U) //!< Bit field size in bits for ENET_MSCR_DIS_PRE.
bogdanm	82:6473597d706e	1895
bogdanm	82:6473597d706e	1896	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1897	//! @brief Read current value of the ENET_MSCR_DIS_PRE field.
bogdanm	82:6473597d706e	1898	#define BR_ENET_MSCR_DIS_PRE(x) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE))
bogdanm	82:6473597d706e	1899	#endif
bogdanm	82:6473597d706e	1900
bogdanm	82:6473597d706e	1901	//! @brief Format value for bitfield ENET_MSCR_DIS_PRE.
bogdanm	82:6473597d706e	1902	#define BF_ENET_MSCR_DIS_PRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_DIS_PRE), uint32_t) & BM_ENET_MSCR_DIS_PRE)
bogdanm	82:6473597d706e	1903
bogdanm	82:6473597d706e	1904	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1905	//! @brief Set the DIS_PRE field to a new value.
bogdanm	82:6473597d706e	1906	#define BW_ENET_MSCR_DIS_PRE(x, v) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE) = (v))
bogdanm	82:6473597d706e	1907	#endif
bogdanm	82:6473597d706e	1908	//@}
bogdanm	82:6473597d706e	1909
bogdanm	82:6473597d706e	1910	/*!
bogdanm	82:6473597d706e	1911	* @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
bogdanm	82:6473597d706e	1912	*
bogdanm	82:6473597d706e	1913	* IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
bogdanm	82:6473597d706e	1914	* output. Depending on the host bus frequency, the setting may need to be
bogdanm	82:6473597d706e	1915	* increased.
bogdanm	82:6473597d706e	1916	*
bogdanm	82:6473597d706e	1917	* Values:
bogdanm	82:6473597d706e	1918	* - 000 - 1 internal module clock cycle
bogdanm	82:6473597d706e	1919	* - 001 - 2 internal module clock cycles
bogdanm	82:6473597d706e	1920	* - 010 - 3 internal module clock cycles
bogdanm	82:6473597d706e	1921	* - 111 - 8 internal module clock cycles
bogdanm	82:6473597d706e	1922	*/
bogdanm	82:6473597d706e	1923	//@{
bogdanm	82:6473597d706e	1924	#define BP_ENET_MSCR_HOLDTIME (8U) //!< Bit position for ENET_MSCR_HOLDTIME.
bogdanm	82:6473597d706e	1925	#define BM_ENET_MSCR_HOLDTIME (0x00000700U) //!< Bit mask for ENET_MSCR_HOLDTIME.
bogdanm	82:6473597d706e	1926	#define BS_ENET_MSCR_HOLDTIME (3U) //!< Bit field size in bits for ENET_MSCR_HOLDTIME.
bogdanm	82:6473597d706e	1927
bogdanm	82:6473597d706e	1928	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1929	//! @brief Read current value of the ENET_MSCR_HOLDTIME field.
bogdanm	82:6473597d706e	1930	#define BR_ENET_MSCR_HOLDTIME(x) (HW_ENET_MSCR(x).B.HOLDTIME)
bogdanm	82:6473597d706e	1931	#endif
bogdanm	82:6473597d706e	1932
bogdanm	82:6473597d706e	1933	//! @brief Format value for bitfield ENET_MSCR_HOLDTIME.
bogdanm	82:6473597d706e	1934	#define BF_ENET_MSCR_HOLDTIME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_HOLDTIME), uint32_t) & BM_ENET_MSCR_HOLDTIME)
bogdanm	82:6473597d706e	1935
bogdanm	82:6473597d706e	1936	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1937	//! @brief Set the HOLDTIME field to a new value.
bogdanm	82:6473597d706e	1938	#define BW_ENET_MSCR_HOLDTIME(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_HOLDTIME) \| BF_ENET_MSCR_HOLDTIME(v)))
bogdanm	82:6473597d706e	1939	#endif
bogdanm	82:6473597d706e	1940	//@}
bogdanm	82:6473597d706e	1941
bogdanm	82:6473597d706e	1942	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1943	// HW_ENET_MIBC - MIB Control Register
bogdanm	82:6473597d706e	1944	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1945
bogdanm	82:6473597d706e	1946	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1947	/*!
bogdanm	82:6473597d706e	1948	* @brief HW_ENET_MIBC - MIB Control Register (RW)
bogdanm	82:6473597d706e	1949	*
bogdanm	82:6473597d706e	1950	* Reset value: 0xC0000000U
bogdanm	82:6473597d706e	1951	*
bogdanm	82:6473597d706e	1952	* MIBC is a read/write register controlling and observing the state of the MIB
bogdanm	82:6473597d706e	1953	* block. Access this register to disable the MIB block operation or clear the
bogdanm	82:6473597d706e	1954	* MIB counters. The MIB_DIS field resets to 1.
bogdanm	82:6473597d706e	1955	*/
bogdanm	82:6473597d706e	1956	typedef union _hw_enet_mibc
bogdanm	82:6473597d706e	1957	{
bogdanm	82:6473597d706e	1958	uint32_t U;
bogdanm	82:6473597d706e	1959	struct _hw_enet_mibc_bitfields
bogdanm	82:6473597d706e	1960	{
bogdanm	82:6473597d706e	1961	uint32_t RESERVED0 : 29; //!< [28:0]
bogdanm	82:6473597d706e	1962	uint32_t MIB_CLEAR : 1; //!< [29] MIB Clear
bogdanm	82:6473597d706e	1963	uint32_t MIB_IDLE : 1; //!< [30] MIB Idle
bogdanm	82:6473597d706e	1964	uint32_t MIB_DIS : 1; //!< [31] Disable MIB Logic
bogdanm	82:6473597d706e	1965	} B;
bogdanm	82:6473597d706e	1966	} hw_enet_mibc_t;
bogdanm	82:6473597d706e	1967	#endif
bogdanm	82:6473597d706e	1968
bogdanm	82:6473597d706e	1969	/*!
bogdanm	82:6473597d706e	1970	* @name Constants and macros for entire ENET_MIBC register
bogdanm	82:6473597d706e	1971	*/
bogdanm	82:6473597d706e	1972	//@{
bogdanm	82:6473597d706e	1973	#define HW_ENET_MIBC_ADDR(x) (REGS_ENET_BASE(x) + 0x64U)
bogdanm	82:6473597d706e	1974
bogdanm	82:6473597d706e	1975	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1976	#define HW_ENET_MIBC(x) ((__IO hw_enet_mibc_t ) HW_ENET_MIBC_ADDR(x))
bogdanm	82:6473597d706e	1977	#define HW_ENET_MIBC_RD(x) (HW_ENET_MIBC(x).U)
bogdanm	82:6473597d706e	1978	#define HW_ENET_MIBC_WR(x, v) (HW_ENET_MIBC(x).U = (v))
bogdanm	82:6473597d706e	1979	#define HW_ENET_MIBC_SET(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) \| (v)))
bogdanm	82:6473597d706e	1980	#define HW_ENET_MIBC_CLR(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1981	#define HW_ENET_MIBC_TOG(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1982	#endif
bogdanm	82:6473597d706e	1983	//@}
bogdanm	82:6473597d706e	1984
bogdanm	82:6473597d706e	1985	/*
bogdanm	82:6473597d706e	1986	* Constants & macros for individual ENET_MIBC bitfields
bogdanm	82:6473597d706e	1987	*/
bogdanm	82:6473597d706e	1988
bogdanm	82:6473597d706e	1989	/*!
bogdanm	82:6473597d706e	1990	* @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
bogdanm	82:6473597d706e	1991	*
bogdanm	82:6473597d706e	1992	* If set, all statistics counters are reset to 0. This field is not
bogdanm	82:6473597d706e	1993	* self-clearing. To clear the MIB counters set and then clear the field.
bogdanm	82:6473597d706e	1994	*/
bogdanm	82:6473597d706e	1995	//@{
bogdanm	82:6473597d706e	1996	#define BP_ENET_MIBC_MIB_CLEAR (29U) //!< Bit position for ENET_MIBC_MIB_CLEAR.
bogdanm	82:6473597d706e	1997	#define BM_ENET_MIBC_MIB_CLEAR (0x20000000U) //!< Bit mask for ENET_MIBC_MIB_CLEAR.
bogdanm	82:6473597d706e	1998	#define BS_ENET_MIBC_MIB_CLEAR (1U) //!< Bit field size in bits for ENET_MIBC_MIB_CLEAR.
bogdanm	82:6473597d706e	1999
bogdanm	82:6473597d706e	2000	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2001	//! @brief Read current value of the ENET_MIBC_MIB_CLEAR field.
bogdanm	82:6473597d706e	2002	#define BR_ENET_MIBC_MIB_CLEAR(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR))
bogdanm	82:6473597d706e	2003	#endif
bogdanm	82:6473597d706e	2004
bogdanm	82:6473597d706e	2005	//! @brief Format value for bitfield ENET_MIBC_MIB_CLEAR.
bogdanm	82:6473597d706e	2006	#define BF_ENET_MIBC_MIB_CLEAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MIBC_MIB_CLEAR), uint32_t) & BM_ENET_MIBC_MIB_CLEAR)
bogdanm	82:6473597d706e	2007
bogdanm	82:6473597d706e	2008	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2009	//! @brief Set the MIB_CLEAR field to a new value.
bogdanm	82:6473597d706e	2010	#define BW_ENET_MIBC_MIB_CLEAR(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR) = (v))
bogdanm	82:6473597d706e	2011	#endif
bogdanm	82:6473597d706e	2012	//@}
bogdanm	82:6473597d706e	2013
bogdanm	82:6473597d706e	2014	/*!
bogdanm	82:6473597d706e	2015	* @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
bogdanm	82:6473597d706e	2016	*
bogdanm	82:6473597d706e	2017	* If this status field is set, the MIB block is not currently updating any MIB
bogdanm	82:6473597d706e	2018	* counters.
bogdanm	82:6473597d706e	2019	*/
bogdanm	82:6473597d706e	2020	//@{
bogdanm	82:6473597d706e	2021	#define BP_ENET_MIBC_MIB_IDLE (30U) //!< Bit position for ENET_MIBC_MIB_IDLE.
bogdanm	82:6473597d706e	2022	#define BM_ENET_MIBC_MIB_IDLE (0x40000000U) //!< Bit mask for ENET_MIBC_MIB_IDLE.
bogdanm	82:6473597d706e	2023	#define BS_ENET_MIBC_MIB_IDLE (1U) //!< Bit field size in bits for ENET_MIBC_MIB_IDLE.
bogdanm	82:6473597d706e	2024
bogdanm	82:6473597d706e	2025	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2026	//! @brief Read current value of the ENET_MIBC_MIB_IDLE field.
bogdanm	82:6473597d706e	2027	#define BR_ENET_MIBC_MIB_IDLE(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_IDLE))
bogdanm	82:6473597d706e	2028	#endif
bogdanm	82:6473597d706e	2029	//@}
bogdanm	82:6473597d706e	2030
bogdanm	82:6473597d706e	2031	/*!
bogdanm	82:6473597d706e	2032	* @name Register ENET_MIBC, field MIB_DIS[31] (RW)
bogdanm	82:6473597d706e	2033	*
bogdanm	82:6473597d706e	2034	* If this control field is set, the MIB logic halts and does not update any MIB
bogdanm	82:6473597d706e	2035	* counters.
bogdanm	82:6473597d706e	2036	*/
bogdanm	82:6473597d706e	2037	//@{
bogdanm	82:6473597d706e	2038	#define BP_ENET_MIBC_MIB_DIS (31U) //!< Bit position for ENET_MIBC_MIB_DIS.
bogdanm	82:6473597d706e	2039	#define BM_ENET_MIBC_MIB_DIS (0x80000000U) //!< Bit mask for ENET_MIBC_MIB_DIS.
bogdanm	82:6473597d706e	2040	#define BS_ENET_MIBC_MIB_DIS (1U) //!< Bit field size in bits for ENET_MIBC_MIB_DIS.
bogdanm	82:6473597d706e	2041
bogdanm	82:6473597d706e	2042	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2043	//! @brief Read current value of the ENET_MIBC_MIB_DIS field.
bogdanm	82:6473597d706e	2044	#define BR_ENET_MIBC_MIB_DIS(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS))
bogdanm	82:6473597d706e	2045	#endif
bogdanm	82:6473597d706e	2046
bogdanm	82:6473597d706e	2047	//! @brief Format value for bitfield ENET_MIBC_MIB_DIS.
bogdanm	82:6473597d706e	2048	#define BF_ENET_MIBC_MIB_DIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MIBC_MIB_DIS), uint32_t) & BM_ENET_MIBC_MIB_DIS)
bogdanm	82:6473597d706e	2049
bogdanm	82:6473597d706e	2050	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2051	//! @brief Set the MIB_DIS field to a new value.
bogdanm	82:6473597d706e	2052	#define BW_ENET_MIBC_MIB_DIS(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS) = (v))
bogdanm	82:6473597d706e	2053	#endif
bogdanm	82:6473597d706e	2054	//@}
bogdanm	82:6473597d706e	2055
bogdanm	82:6473597d706e	2056	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2057	// HW_ENET_RCR - Receive Control Register
bogdanm	82:6473597d706e	2058	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2059
bogdanm	82:6473597d706e	2060	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2061	/*!
bogdanm	82:6473597d706e	2062	* @brief HW_ENET_RCR - Receive Control Register (RW)
bogdanm	82:6473597d706e	2063	*
bogdanm	82:6473597d706e	2064	* Reset value: 0x05EE0001U
bogdanm	82:6473597d706e	2065	*/
bogdanm	82:6473597d706e	2066	typedef union _hw_enet_rcr
bogdanm	82:6473597d706e	2067	{
bogdanm	82:6473597d706e	2068	uint32_t U;
bogdanm	82:6473597d706e	2069	struct _hw_enet_rcr_bitfields
bogdanm	82:6473597d706e	2070	{
bogdanm	82:6473597d706e	2071	uint32_t LOOP : 1; //!< [0] Internal Loopback
bogdanm	82:6473597d706e	2072	uint32_t DRT : 1; //!< [1] Disable Receive On Transmit
bogdanm	82:6473597d706e	2073	uint32_t MII_MODE : 1; //!< [2] Media Independent Interface Mode
bogdanm	82:6473597d706e	2074	uint32_t PROM : 1; //!< [3] Promiscuous Mode
bogdanm	82:6473597d706e	2075	uint32_t BC_REJ : 1; //!< [4] Broadcast Frame Reject
bogdanm	82:6473597d706e	2076	uint32_t FCE : 1; //!< [5] Flow Control Enable
bogdanm	82:6473597d706e	2077	uint32_t RESERVED0 : 2; //!< [7:6]
bogdanm	82:6473597d706e	2078	uint32_t RMII_MODE : 1; //!< [8] RMII Mode Enable
bogdanm	82:6473597d706e	2079	uint32_t RMII_10T : 1; //!< [9]
bogdanm	82:6473597d706e	2080	uint32_t RESERVED1 : 2; //!< [11:10]
bogdanm	82:6473597d706e	2081	uint32_t PADEN : 1; //!< [12] Enable Frame Padding Remove On Receive
bogdanm	82:6473597d706e	2082	uint32_t PAUFWD : 1; //!< [13] Terminate/Forward Pause Frames
bogdanm	82:6473597d706e	2083	uint32_t CRCFWD : 1; //!< [14] Terminate/Forward Received CRC
bogdanm	82:6473597d706e	2084	uint32_t CFEN : 1; //!< [15] MAC Control Frame Enable
bogdanm	82:6473597d706e	2085	uint32_t MAX_FL : 14; //!< [29:16] Maximum Frame Length
bogdanm	82:6473597d706e	2086	uint32_t NLC : 1; //!< [30] Payload Length Check Disable
bogdanm	82:6473597d706e	2087	uint32_t GRS : 1; //!< [31] Graceful Receive Stopped
bogdanm	82:6473597d706e	2088	} B;
bogdanm	82:6473597d706e	2089	} hw_enet_rcr_t;
bogdanm	82:6473597d706e	2090	#endif
bogdanm	82:6473597d706e	2091
bogdanm	82:6473597d706e	2092	/*!
bogdanm	82:6473597d706e	2093	* @name Constants and macros for entire ENET_RCR register
bogdanm	82:6473597d706e	2094	*/
bogdanm	82:6473597d706e	2095	//@{
bogdanm	82:6473597d706e	2096	#define HW_ENET_RCR_ADDR(x) (REGS_ENET_BASE(x) + 0x84U)
bogdanm	82:6473597d706e	2097
bogdanm	82:6473597d706e	2098	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2099	#define HW_ENET_RCR(x) ((__IO hw_enet_rcr_t ) HW_ENET_RCR_ADDR(x))
bogdanm	82:6473597d706e	2100	#define HW_ENET_RCR_RD(x) (HW_ENET_RCR(x).U)
bogdanm	82:6473597d706e	2101	#define HW_ENET_RCR_WR(x, v) (HW_ENET_RCR(x).U = (v))
bogdanm	82:6473597d706e	2102	#define HW_ENET_RCR_SET(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) \| (v)))
bogdanm	82:6473597d706e	2103	#define HW_ENET_RCR_CLR(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2104	#define HW_ENET_RCR_TOG(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2105	#endif
bogdanm	82:6473597d706e	2106	//@}
bogdanm	82:6473597d706e	2107
bogdanm	82:6473597d706e	2108	/*
bogdanm	82:6473597d706e	2109	* Constants & macros for individual ENET_RCR bitfields
bogdanm	82:6473597d706e	2110	*/
bogdanm	82:6473597d706e	2111
bogdanm	82:6473597d706e	2112	/*!
bogdanm	82:6473597d706e	2113	* @name Register ENET_RCR, field LOOP[0] (RW)
bogdanm	82:6473597d706e	2114	*
bogdanm	82:6473597d706e	2115	* This is an MII internal loopback, therefore MII_MODE must be written to 1 and
bogdanm	82:6473597d706e	2116	* RMII_MODE must be written to 0.
bogdanm	82:6473597d706e	2117	*
bogdanm	82:6473597d706e	2118	* Values:
bogdanm	82:6473597d706e	2119	* - 0 - Loopback disabled.
bogdanm	82:6473597d706e	2120	* - 1 - Transmitted frames are looped back internal to the device and transmit
bogdanm	82:6473597d706e	2121	* MII output signals are not asserted. DRT must be cleared.
bogdanm	82:6473597d706e	2122	*/
bogdanm	82:6473597d706e	2123	//@{
bogdanm	82:6473597d706e	2124	#define BP_ENET_RCR_LOOP (0U) //!< Bit position for ENET_RCR_LOOP.
bogdanm	82:6473597d706e	2125	#define BM_ENET_RCR_LOOP (0x00000001U) //!< Bit mask for ENET_RCR_LOOP.
bogdanm	82:6473597d706e	2126	#define BS_ENET_RCR_LOOP (1U) //!< Bit field size in bits for ENET_RCR_LOOP.
bogdanm	82:6473597d706e	2127
bogdanm	82:6473597d706e	2128	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2129	//! @brief Read current value of the ENET_RCR_LOOP field.
bogdanm	82:6473597d706e	2130	#define BR_ENET_RCR_LOOP(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP))
bogdanm	82:6473597d706e	2131	#endif
bogdanm	82:6473597d706e	2132
bogdanm	82:6473597d706e	2133	//! @brief Format value for bitfield ENET_RCR_LOOP.
bogdanm	82:6473597d706e	2134	#define BF_ENET_RCR_LOOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_LOOP), uint32_t) & BM_ENET_RCR_LOOP)
bogdanm	82:6473597d706e	2135
bogdanm	82:6473597d706e	2136	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2137	//! @brief Set the LOOP field to a new value.
bogdanm	82:6473597d706e	2138	#define BW_ENET_RCR_LOOP(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP) = (v))
bogdanm	82:6473597d706e	2139	#endif
bogdanm	82:6473597d706e	2140	//@}
bogdanm	82:6473597d706e	2141
bogdanm	82:6473597d706e	2142	/*!
bogdanm	82:6473597d706e	2143	* @name Register ENET_RCR, field DRT[1] (RW)
bogdanm	82:6473597d706e	2144	*
bogdanm	82:6473597d706e	2145	* Values:
bogdanm	82:6473597d706e	2146	* - 0 - Receive path operates independently of transmit. Used for full-duplex
bogdanm	82:6473597d706e	2147	* or to monitor transmit activity in half-duplex mode.
bogdanm	82:6473597d706e	2148	* - 1 - Disable reception of frames while transmitting. Normally used for
bogdanm	82:6473597d706e	2149	* half-duplex mode.
bogdanm	82:6473597d706e	2150	*/
bogdanm	82:6473597d706e	2151	//@{
bogdanm	82:6473597d706e	2152	#define BP_ENET_RCR_DRT (1U) //!< Bit position for ENET_RCR_DRT.
bogdanm	82:6473597d706e	2153	#define BM_ENET_RCR_DRT (0x00000002U) //!< Bit mask for ENET_RCR_DRT.
bogdanm	82:6473597d706e	2154	#define BS_ENET_RCR_DRT (1U) //!< Bit field size in bits for ENET_RCR_DRT.
bogdanm	82:6473597d706e	2155
bogdanm	82:6473597d706e	2156	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2157	//! @brief Read current value of the ENET_RCR_DRT field.
bogdanm	82:6473597d706e	2158	#define BR_ENET_RCR_DRT(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT))
bogdanm	82:6473597d706e	2159	#endif
bogdanm	82:6473597d706e	2160
bogdanm	82:6473597d706e	2161	//! @brief Format value for bitfield ENET_RCR_DRT.
bogdanm	82:6473597d706e	2162	#define BF_ENET_RCR_DRT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_DRT), uint32_t) & BM_ENET_RCR_DRT)
bogdanm	82:6473597d706e	2163
bogdanm	82:6473597d706e	2164	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2165	//! @brief Set the DRT field to a new value.
bogdanm	82:6473597d706e	2166	#define BW_ENET_RCR_DRT(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT) = (v))
bogdanm	82:6473597d706e	2167	#endif
bogdanm	82:6473597d706e	2168	//@}
bogdanm	82:6473597d706e	2169
bogdanm	82:6473597d706e	2170	/*!
bogdanm	82:6473597d706e	2171	* @name Register ENET_RCR, field MII_MODE[2] (RW)
bogdanm	82:6473597d706e	2172	*
bogdanm	82:6473597d706e	2173	* This field must always be set.
bogdanm	82:6473597d706e	2174	*
bogdanm	82:6473597d706e	2175	* Values:
bogdanm	82:6473597d706e	2176	* - 0 - Reserved.
bogdanm	82:6473597d706e	2177	* - 1 - MII or RMII mode, as indicated by the RMII_MODE field.
bogdanm	82:6473597d706e	2178	*/
bogdanm	82:6473597d706e	2179	//@{
bogdanm	82:6473597d706e	2180	#define BP_ENET_RCR_MII_MODE (2U) //!< Bit position for ENET_RCR_MII_MODE.
bogdanm	82:6473597d706e	2181	#define BM_ENET_RCR_MII_MODE (0x00000004U) //!< Bit mask for ENET_RCR_MII_MODE.
bogdanm	82:6473597d706e	2182	#define BS_ENET_RCR_MII_MODE (1U) //!< Bit field size in bits for ENET_RCR_MII_MODE.
bogdanm	82:6473597d706e	2183
bogdanm	82:6473597d706e	2184	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2185	//! @brief Read current value of the ENET_RCR_MII_MODE field.
bogdanm	82:6473597d706e	2186	#define BR_ENET_RCR_MII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE))
bogdanm	82:6473597d706e	2187	#endif
bogdanm	82:6473597d706e	2188
bogdanm	82:6473597d706e	2189	//! @brief Format value for bitfield ENET_RCR_MII_MODE.
bogdanm	82:6473597d706e	2190	#define BF_ENET_RCR_MII_MODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_MII_MODE), uint32_t) & BM_ENET_RCR_MII_MODE)
bogdanm	82:6473597d706e	2191
bogdanm	82:6473597d706e	2192	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2193	//! @brief Set the MII_MODE field to a new value.
bogdanm	82:6473597d706e	2194	#define BW_ENET_RCR_MII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE) = (v))
bogdanm	82:6473597d706e	2195	#endif
bogdanm	82:6473597d706e	2196	//@}
bogdanm	82:6473597d706e	2197
bogdanm	82:6473597d706e	2198	/*!
bogdanm	82:6473597d706e	2199	* @name Register ENET_RCR, field PROM[3] (RW)
bogdanm	82:6473597d706e	2200	*
bogdanm	82:6473597d706e	2201	* All frames are accepted regardless of address matching.
bogdanm	82:6473597d706e	2202	*
bogdanm	82:6473597d706e	2203	* Values:
bogdanm	82:6473597d706e	2204	* - 0 - Disabled.
bogdanm	82:6473597d706e	2205	* - 1 - Enabled.
bogdanm	82:6473597d706e	2206	*/
bogdanm	82:6473597d706e	2207	//@{
bogdanm	82:6473597d706e	2208	#define BP_ENET_RCR_PROM (3U) //!< Bit position for ENET_RCR_PROM.
bogdanm	82:6473597d706e	2209	#define BM_ENET_RCR_PROM (0x00000008U) //!< Bit mask for ENET_RCR_PROM.
bogdanm	82:6473597d706e	2210	#define BS_ENET_RCR_PROM (1U) //!< Bit field size in bits for ENET_RCR_PROM.
bogdanm	82:6473597d706e	2211
bogdanm	82:6473597d706e	2212	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2213	//! @brief Read current value of the ENET_RCR_PROM field.
bogdanm	82:6473597d706e	2214	#define BR_ENET_RCR_PROM(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM))
bogdanm	82:6473597d706e	2215	#endif
bogdanm	82:6473597d706e	2216
bogdanm	82:6473597d706e	2217	//! @brief Format value for bitfield ENET_RCR_PROM.
bogdanm	82:6473597d706e	2218	#define BF_ENET_RCR_PROM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PROM), uint32_t) & BM_ENET_RCR_PROM)
bogdanm	82:6473597d706e	2219
bogdanm	82:6473597d706e	2220	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2221	//! @brief Set the PROM field to a new value.
bogdanm	82:6473597d706e	2222	#define BW_ENET_RCR_PROM(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM) = (v))
bogdanm	82:6473597d706e	2223	#endif
bogdanm	82:6473597d706e	2224	//@}
bogdanm	82:6473597d706e	2225
bogdanm	82:6473597d706e	2226	/*!
bogdanm	82:6473597d706e	2227	* @name Register ENET_RCR, field BC_REJ[4] (RW)
bogdanm	82:6473597d706e	2228	*
bogdanm	82:6473597d706e	2229	* If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
bogdanm	82:6473597d706e	2230	* rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
bogdanm	82:6473597d706e	2231	* broadcast DA are accepted and the MISS (M) is set in the receive buffer
bogdanm	82:6473597d706e	2232	* descriptor.
bogdanm	82:6473597d706e	2233	*/
bogdanm	82:6473597d706e	2234	//@{
bogdanm	82:6473597d706e	2235	#define BP_ENET_RCR_BC_REJ (4U) //!< Bit position for ENET_RCR_BC_REJ.
bogdanm	82:6473597d706e	2236	#define BM_ENET_RCR_BC_REJ (0x00000010U) //!< Bit mask for ENET_RCR_BC_REJ.
bogdanm	82:6473597d706e	2237	#define BS_ENET_RCR_BC_REJ (1U) //!< Bit field size in bits for ENET_RCR_BC_REJ.
bogdanm	82:6473597d706e	2238
bogdanm	82:6473597d706e	2239	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2240	//! @brief Read current value of the ENET_RCR_BC_REJ field.
bogdanm	82:6473597d706e	2241	#define BR_ENET_RCR_BC_REJ(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ))
bogdanm	82:6473597d706e	2242	#endif
bogdanm	82:6473597d706e	2243
bogdanm	82:6473597d706e	2244	//! @brief Format value for bitfield ENET_RCR_BC_REJ.
bogdanm	82:6473597d706e	2245	#define BF_ENET_RCR_BC_REJ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_BC_REJ), uint32_t) & BM_ENET_RCR_BC_REJ)
bogdanm	82:6473597d706e	2246
bogdanm	82:6473597d706e	2247	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2248	//! @brief Set the BC_REJ field to a new value.
bogdanm	82:6473597d706e	2249	#define BW_ENET_RCR_BC_REJ(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ) = (v))
bogdanm	82:6473597d706e	2250	#endif
bogdanm	82:6473597d706e	2251	//@}
bogdanm	82:6473597d706e	2252
bogdanm	82:6473597d706e	2253	/*!
bogdanm	82:6473597d706e	2254	* @name Register ENET_RCR, field FCE[5] (RW)
bogdanm	82:6473597d706e	2255	*
bogdanm	82:6473597d706e	2256	* If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
bogdanm	82:6473597d706e	2257	* transmitter stops transmitting data frames for a given duration.
bogdanm	82:6473597d706e	2258	*/
bogdanm	82:6473597d706e	2259	//@{
bogdanm	82:6473597d706e	2260	#define BP_ENET_RCR_FCE (5U) //!< Bit position for ENET_RCR_FCE.
bogdanm	82:6473597d706e	2261	#define BM_ENET_RCR_FCE (0x00000020U) //!< Bit mask for ENET_RCR_FCE.
bogdanm	82:6473597d706e	2262	#define BS_ENET_RCR_FCE (1U) //!< Bit field size in bits for ENET_RCR_FCE.
bogdanm	82:6473597d706e	2263
bogdanm	82:6473597d706e	2264	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2265	//! @brief Read current value of the ENET_RCR_FCE field.
bogdanm	82:6473597d706e	2266	#define BR_ENET_RCR_FCE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE))
bogdanm	82:6473597d706e	2267	#endif
bogdanm	82:6473597d706e	2268
bogdanm	82:6473597d706e	2269	//! @brief Format value for bitfield ENET_RCR_FCE.
bogdanm	82:6473597d706e	2270	#define BF_ENET_RCR_FCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_FCE), uint32_t) & BM_ENET_RCR_FCE)
bogdanm	82:6473597d706e	2271
bogdanm	82:6473597d706e	2272	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2273	//! @brief Set the FCE field to a new value.
bogdanm	82:6473597d706e	2274	#define BW_ENET_RCR_FCE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE) = (v))
bogdanm	82:6473597d706e	2275	#endif
bogdanm	82:6473597d706e	2276	//@}
bogdanm	82:6473597d706e	2277
bogdanm	82:6473597d706e	2278	/*!
bogdanm	82:6473597d706e	2279	* @name Register ENET_RCR, field RMII_MODE[8] (RW)
bogdanm	82:6473597d706e	2280	*
bogdanm	82:6473597d706e	2281	* Specifies whether the MAC is configured for MII mode or RMII operation .
bogdanm	82:6473597d706e	2282	*
bogdanm	82:6473597d706e	2283	* Values:
bogdanm	82:6473597d706e	2284	* - 0 - MAC configured for MII mode.
bogdanm	82:6473597d706e	2285	* - 1 - MAC configured for RMII operation.
bogdanm	82:6473597d706e	2286	*/
bogdanm	82:6473597d706e	2287	//@{
bogdanm	82:6473597d706e	2288	#define BP_ENET_RCR_RMII_MODE (8U) //!< Bit position for ENET_RCR_RMII_MODE.
bogdanm	82:6473597d706e	2289	#define BM_ENET_RCR_RMII_MODE (0x00000100U) //!< Bit mask for ENET_RCR_RMII_MODE.
bogdanm	82:6473597d706e	2290	#define BS_ENET_RCR_RMII_MODE (1U) //!< Bit field size in bits for ENET_RCR_RMII_MODE.
bogdanm	82:6473597d706e	2291
bogdanm	82:6473597d706e	2292	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2293	//! @brief Read current value of the ENET_RCR_RMII_MODE field.
bogdanm	82:6473597d706e	2294	#define BR_ENET_RCR_RMII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE))
bogdanm	82:6473597d706e	2295	#endif
bogdanm	82:6473597d706e	2296
bogdanm	82:6473597d706e	2297	//! @brief Format value for bitfield ENET_RCR_RMII_MODE.
bogdanm	82:6473597d706e	2298	#define BF_ENET_RCR_RMII_MODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_RMII_MODE), uint32_t) & BM_ENET_RCR_RMII_MODE)
bogdanm	82:6473597d706e	2299
bogdanm	82:6473597d706e	2300	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2301	//! @brief Set the RMII_MODE field to a new value.
bogdanm	82:6473597d706e	2302	#define BW_ENET_RCR_RMII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE) = (v))
bogdanm	82:6473597d706e	2303	#endif
bogdanm	82:6473597d706e	2304	//@}
bogdanm	82:6473597d706e	2305
bogdanm	82:6473597d706e	2306	/*!
bogdanm	82:6473597d706e	2307	* @name Register ENET_RCR, field RMII_10T[9] (RW)
bogdanm	82:6473597d706e	2308	*
bogdanm	82:6473597d706e	2309	* Enables 10-Mbps mode of the RMII .
bogdanm	82:6473597d706e	2310	*
bogdanm	82:6473597d706e	2311	* Values:
bogdanm	82:6473597d706e	2312	* - 0 - 100 Mbps operation.
bogdanm	82:6473597d706e	2313	* - 1 - 10 Mbps operation.
bogdanm	82:6473597d706e	2314	*/
bogdanm	82:6473597d706e	2315	//@{
bogdanm	82:6473597d706e	2316	#define BP_ENET_RCR_RMII_10T (9U) //!< Bit position for ENET_RCR_RMII_10T.
bogdanm	82:6473597d706e	2317	#define BM_ENET_RCR_RMII_10T (0x00000200U) //!< Bit mask for ENET_RCR_RMII_10T.
bogdanm	82:6473597d706e	2318	#define BS_ENET_RCR_RMII_10T (1U) //!< Bit field size in bits for ENET_RCR_RMII_10T.
bogdanm	82:6473597d706e	2319
bogdanm	82:6473597d706e	2320	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2321	//! @brief Read current value of the ENET_RCR_RMII_10T field.
bogdanm	82:6473597d706e	2322	#define BR_ENET_RCR_RMII_10T(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T))
bogdanm	82:6473597d706e	2323	#endif
bogdanm	82:6473597d706e	2324
bogdanm	82:6473597d706e	2325	//! @brief Format value for bitfield ENET_RCR_RMII_10T.
bogdanm	82:6473597d706e	2326	#define BF_ENET_RCR_RMII_10T(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_RMII_10T), uint32_t) & BM_ENET_RCR_RMII_10T)
bogdanm	82:6473597d706e	2327
bogdanm	82:6473597d706e	2328	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2329	//! @brief Set the RMII_10T field to a new value.
bogdanm	82:6473597d706e	2330	#define BW_ENET_RCR_RMII_10T(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T) = (v))
bogdanm	82:6473597d706e	2331	#endif
bogdanm	82:6473597d706e	2332	//@}
bogdanm	82:6473597d706e	2333
bogdanm	82:6473597d706e	2334	/*!
bogdanm	82:6473597d706e	2335	* @name Register ENET_RCR, field PADEN[12] (RW)
bogdanm	82:6473597d706e	2336	*
bogdanm	82:6473597d706e	2337	* Specifies whether the MAC removes padding from received frames.
bogdanm	82:6473597d706e	2338	*
bogdanm	82:6473597d706e	2339	* Values:
bogdanm	82:6473597d706e	2340	* - 0 - No padding is removed on receive by the MAC.
bogdanm	82:6473597d706e	2341	* - 1 - Padding is removed from received frames.
bogdanm	82:6473597d706e	2342	*/
bogdanm	82:6473597d706e	2343	//@{
bogdanm	82:6473597d706e	2344	#define BP_ENET_RCR_PADEN (12U) //!< Bit position for ENET_RCR_PADEN.
bogdanm	82:6473597d706e	2345	#define BM_ENET_RCR_PADEN (0x00001000U) //!< Bit mask for ENET_RCR_PADEN.
bogdanm	82:6473597d706e	2346	#define BS_ENET_RCR_PADEN (1U) //!< Bit field size in bits for ENET_RCR_PADEN.
bogdanm	82:6473597d706e	2347
bogdanm	82:6473597d706e	2348	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2349	//! @brief Read current value of the ENET_RCR_PADEN field.
bogdanm	82:6473597d706e	2350	#define BR_ENET_RCR_PADEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN))
bogdanm	82:6473597d706e	2351	#endif
bogdanm	82:6473597d706e	2352
bogdanm	82:6473597d706e	2353	//! @brief Format value for bitfield ENET_RCR_PADEN.
bogdanm	82:6473597d706e	2354	#define BF_ENET_RCR_PADEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PADEN), uint32_t) & BM_ENET_RCR_PADEN)
bogdanm	82:6473597d706e	2355
bogdanm	82:6473597d706e	2356	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2357	//! @brief Set the PADEN field to a new value.
bogdanm	82:6473597d706e	2358	#define BW_ENET_RCR_PADEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN) = (v))
bogdanm	82:6473597d706e	2359	#endif
bogdanm	82:6473597d706e	2360	//@}
bogdanm	82:6473597d706e	2361
bogdanm	82:6473597d706e	2362	/*!
bogdanm	82:6473597d706e	2363	* @name Register ENET_RCR, field PAUFWD[13] (RW)
bogdanm	82:6473597d706e	2364	*
bogdanm	82:6473597d706e	2365	* Specifies whether pause frames are terminated or forwarded.
bogdanm	82:6473597d706e	2366	*
bogdanm	82:6473597d706e	2367	* Values:
bogdanm	82:6473597d706e	2368	* - 0 - Pause frames are terminated and discarded in the MAC.
bogdanm	82:6473597d706e	2369	* - 1 - Pause frames are forwarded to the user application.
bogdanm	82:6473597d706e	2370	*/
bogdanm	82:6473597d706e	2371	//@{
bogdanm	82:6473597d706e	2372	#define BP_ENET_RCR_PAUFWD (13U) //!< Bit position for ENET_RCR_PAUFWD.
bogdanm	82:6473597d706e	2373	#define BM_ENET_RCR_PAUFWD (0x00002000U) //!< Bit mask for ENET_RCR_PAUFWD.
bogdanm	82:6473597d706e	2374	#define BS_ENET_RCR_PAUFWD (1U) //!< Bit field size in bits for ENET_RCR_PAUFWD.
bogdanm	82:6473597d706e	2375
bogdanm	82:6473597d706e	2376	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2377	//! @brief Read current value of the ENET_RCR_PAUFWD field.
bogdanm	82:6473597d706e	2378	#define BR_ENET_RCR_PAUFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD))
bogdanm	82:6473597d706e	2379	#endif
bogdanm	82:6473597d706e	2380
bogdanm	82:6473597d706e	2381	//! @brief Format value for bitfield ENET_RCR_PAUFWD.
bogdanm	82:6473597d706e	2382	#define BF_ENET_RCR_PAUFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PAUFWD), uint32_t) & BM_ENET_RCR_PAUFWD)
bogdanm	82:6473597d706e	2383
bogdanm	82:6473597d706e	2384	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2385	//! @brief Set the PAUFWD field to a new value.
bogdanm	82:6473597d706e	2386	#define BW_ENET_RCR_PAUFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD) = (v))
bogdanm	82:6473597d706e	2387	#endif
bogdanm	82:6473597d706e	2388	//@}
bogdanm	82:6473597d706e	2389
bogdanm	82:6473597d706e	2390	/*!
bogdanm	82:6473597d706e	2391	* @name Register ENET_RCR, field CRCFWD[14] (RW)
bogdanm	82:6473597d706e	2392	*
bogdanm	82:6473597d706e	2393	* Specifies whether the CRC field of received frames is transmitted or
bogdanm	82:6473597d706e	2394	* stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
bogdanm	82:6473597d706e	2395	* field is checked and always terminated and removed.
bogdanm	82:6473597d706e	2396	*
bogdanm	82:6473597d706e	2397	* Values:
bogdanm	82:6473597d706e	2398	* - 0 - The CRC field of received frames is transmitted to the user application.
bogdanm	82:6473597d706e	2399	* - 1 - The CRC field is stripped from the frame.
bogdanm	82:6473597d706e	2400	*/
bogdanm	82:6473597d706e	2401	//@{
bogdanm	82:6473597d706e	2402	#define BP_ENET_RCR_CRCFWD (14U) //!< Bit position for ENET_RCR_CRCFWD.
bogdanm	82:6473597d706e	2403	#define BM_ENET_RCR_CRCFWD (0x00004000U) //!< Bit mask for ENET_RCR_CRCFWD.
bogdanm	82:6473597d706e	2404	#define BS_ENET_RCR_CRCFWD (1U) //!< Bit field size in bits for ENET_RCR_CRCFWD.
bogdanm	82:6473597d706e	2405
bogdanm	82:6473597d706e	2406	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2407	//! @brief Read current value of the ENET_RCR_CRCFWD field.
bogdanm	82:6473597d706e	2408	#define BR_ENET_RCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD))
bogdanm	82:6473597d706e	2409	#endif
bogdanm	82:6473597d706e	2410
bogdanm	82:6473597d706e	2411	//! @brief Format value for bitfield ENET_RCR_CRCFWD.
bogdanm	82:6473597d706e	2412	#define BF_ENET_RCR_CRCFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_CRCFWD), uint32_t) & BM_ENET_RCR_CRCFWD)
bogdanm	82:6473597d706e	2413
bogdanm	82:6473597d706e	2414	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2415	//! @brief Set the CRCFWD field to a new value.
bogdanm	82:6473597d706e	2416	#define BW_ENET_RCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD) = (v))
bogdanm	82:6473597d706e	2417	#endif
bogdanm	82:6473597d706e	2418	//@}
bogdanm	82:6473597d706e	2419
bogdanm	82:6473597d706e	2420	/*!
bogdanm	82:6473597d706e	2421	* @name Register ENET_RCR, field CFEN[15] (RW)
bogdanm	82:6473597d706e	2422	*
bogdanm	82:6473597d706e	2423	* Enables/disables the MAC control frame.
bogdanm	82:6473597d706e	2424	*
bogdanm	82:6473597d706e	2425	* Values:
bogdanm	82:6473597d706e	2426	* - 0 - MAC control frames with any opcode other than 0x0001 (pause frame) are
bogdanm	82:6473597d706e	2427	* accepted and forwarded to the client interface.
bogdanm	82:6473597d706e	2428	* - 1 - MAC control frames with any opcode other than 0x0001 (pause frame) are
bogdanm	82:6473597d706e	2429	* silently discarded.
bogdanm	82:6473597d706e	2430	*/
bogdanm	82:6473597d706e	2431	//@{
bogdanm	82:6473597d706e	2432	#define BP_ENET_RCR_CFEN (15U) //!< Bit position for ENET_RCR_CFEN.
bogdanm	82:6473597d706e	2433	#define BM_ENET_RCR_CFEN (0x00008000U) //!< Bit mask for ENET_RCR_CFEN.
bogdanm	82:6473597d706e	2434	#define BS_ENET_RCR_CFEN (1U) //!< Bit field size in bits for ENET_RCR_CFEN.
bogdanm	82:6473597d706e	2435
bogdanm	82:6473597d706e	2436	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2437	//! @brief Read current value of the ENET_RCR_CFEN field.
bogdanm	82:6473597d706e	2438	#define BR_ENET_RCR_CFEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN))
bogdanm	82:6473597d706e	2439	#endif
bogdanm	82:6473597d706e	2440
bogdanm	82:6473597d706e	2441	//! @brief Format value for bitfield ENET_RCR_CFEN.
bogdanm	82:6473597d706e	2442	#define BF_ENET_RCR_CFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_CFEN), uint32_t) & BM_ENET_RCR_CFEN)
bogdanm	82:6473597d706e	2443
bogdanm	82:6473597d706e	2444	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2445	//! @brief Set the CFEN field to a new value.
bogdanm	82:6473597d706e	2446	#define BW_ENET_RCR_CFEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN) = (v))
bogdanm	82:6473597d706e	2447	#endif
bogdanm	82:6473597d706e	2448	//@}
bogdanm	82:6473597d706e	2449
bogdanm	82:6473597d706e	2450	/*!
bogdanm	82:6473597d706e	2451	* @name Register ENET_RCR, field MAX_FL[29:16] (RW)
bogdanm	82:6473597d706e	2452	*
bogdanm	82:6473597d706e	2453	* Resets to decimal 1518. Length is measured starting at DA and includes the
bogdanm	82:6473597d706e	2454	* CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
bogdanm	82:6473597d706e	2455	* interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
bogdanm	82:6473597d706e	2456	* to occur and set the LG field in the end of frame receive buffer descriptor.
bogdanm	82:6473597d706e	2457	* The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
bogdanm	82:6473597d706e	2458	* supported.
bogdanm	82:6473597d706e	2459	*/
bogdanm	82:6473597d706e	2460	//@{
bogdanm	82:6473597d706e	2461	#define BP_ENET_RCR_MAX_FL (16U) //!< Bit position for ENET_RCR_MAX_FL.
bogdanm	82:6473597d706e	2462	#define BM_ENET_RCR_MAX_FL (0x3FFF0000U) //!< Bit mask for ENET_RCR_MAX_FL.
bogdanm	82:6473597d706e	2463	#define BS_ENET_RCR_MAX_FL (14U) //!< Bit field size in bits for ENET_RCR_MAX_FL.
bogdanm	82:6473597d706e	2464
bogdanm	82:6473597d706e	2465	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2466	//! @brief Read current value of the ENET_RCR_MAX_FL field.
bogdanm	82:6473597d706e	2467	#define BR_ENET_RCR_MAX_FL(x) (HW_ENET_RCR(x).B.MAX_FL)
bogdanm	82:6473597d706e	2468	#endif
bogdanm	82:6473597d706e	2469
bogdanm	82:6473597d706e	2470	//! @brief Format value for bitfield ENET_RCR_MAX_FL.
bogdanm	82:6473597d706e	2471	#define BF_ENET_RCR_MAX_FL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_MAX_FL), uint32_t) & BM_ENET_RCR_MAX_FL)
bogdanm	82:6473597d706e	2472
bogdanm	82:6473597d706e	2473	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2474	//! @brief Set the MAX_FL field to a new value.
bogdanm	82:6473597d706e	2475	#define BW_ENET_RCR_MAX_FL(x, v) (HW_ENET_RCR_WR(x, (HW_ENET_RCR_RD(x) & ~BM_ENET_RCR_MAX_FL) \| BF_ENET_RCR_MAX_FL(v)))
bogdanm	82:6473597d706e	2476	#endif
bogdanm	82:6473597d706e	2477	//@}
bogdanm	82:6473597d706e	2478
bogdanm	82:6473597d706e	2479	/*!
bogdanm	82:6473597d706e	2480	* @name Register ENET_RCR, field NLC[30] (RW)
bogdanm	82:6473597d706e	2481	*
bogdanm	82:6473597d706e	2482	* Enables/disables a payload length check.
bogdanm	82:6473597d706e	2483	*
bogdanm	82:6473597d706e	2484	* Values:
bogdanm	82:6473597d706e	2485	* - 0 - The payload length check is disabled.
bogdanm	82:6473597d706e	2486	* - 1 - The core checks the frame's payload length with the frame length/type
bogdanm	82:6473597d706e	2487	* field. Errors are indicated in the EIR[PLC] field.
bogdanm	82:6473597d706e	2488	*/
bogdanm	82:6473597d706e	2489	//@{
bogdanm	82:6473597d706e	2490	#define BP_ENET_RCR_NLC (30U) //!< Bit position for ENET_RCR_NLC.
bogdanm	82:6473597d706e	2491	#define BM_ENET_RCR_NLC (0x40000000U) //!< Bit mask for ENET_RCR_NLC.
bogdanm	82:6473597d706e	2492	#define BS_ENET_RCR_NLC (1U) //!< Bit field size in bits for ENET_RCR_NLC.
bogdanm	82:6473597d706e	2493
bogdanm	82:6473597d706e	2494	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2495	//! @brief Read current value of the ENET_RCR_NLC field.
bogdanm	82:6473597d706e	2496	#define BR_ENET_RCR_NLC(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC))
bogdanm	82:6473597d706e	2497	#endif
bogdanm	82:6473597d706e	2498
bogdanm	82:6473597d706e	2499	//! @brief Format value for bitfield ENET_RCR_NLC.
bogdanm	82:6473597d706e	2500	#define BF_ENET_RCR_NLC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_NLC), uint32_t) & BM_ENET_RCR_NLC)
bogdanm	82:6473597d706e	2501
bogdanm	82:6473597d706e	2502	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2503	//! @brief Set the NLC field to a new value.
bogdanm	82:6473597d706e	2504	#define BW_ENET_RCR_NLC(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC) = (v))
bogdanm	82:6473597d706e	2505	#endif
bogdanm	82:6473597d706e	2506	//@}
bogdanm	82:6473597d706e	2507
bogdanm	82:6473597d706e	2508	/*!
bogdanm	82:6473597d706e	2509	* @name Register ENET_RCR, field GRS[31] (RO)
bogdanm	82:6473597d706e	2510	*
bogdanm	82:6473597d706e	2511	* Read-only status indicating that the MAC receive datapath is stopped.
bogdanm	82:6473597d706e	2512	*/
bogdanm	82:6473597d706e	2513	//@{
bogdanm	82:6473597d706e	2514	#define BP_ENET_RCR_GRS (31U) //!< Bit position for ENET_RCR_GRS.
bogdanm	82:6473597d706e	2515	#define BM_ENET_RCR_GRS (0x80000000U) //!< Bit mask for ENET_RCR_GRS.
bogdanm	82:6473597d706e	2516	#define BS_ENET_RCR_GRS (1U) //!< Bit field size in bits for ENET_RCR_GRS.
bogdanm	82:6473597d706e	2517
bogdanm	82:6473597d706e	2518	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2519	//! @brief Read current value of the ENET_RCR_GRS field.
bogdanm	82:6473597d706e	2520	#define BR_ENET_RCR_GRS(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_GRS))
bogdanm	82:6473597d706e	2521	#endif
bogdanm	82:6473597d706e	2522	//@}
bogdanm	82:6473597d706e	2523
bogdanm	82:6473597d706e	2524	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2525	// HW_ENET_TCR - Transmit Control Register
bogdanm	82:6473597d706e	2526	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2527
bogdanm	82:6473597d706e	2528	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2529	/*!
bogdanm	82:6473597d706e	2530	* @brief HW_ENET_TCR - Transmit Control Register (RW)
bogdanm	82:6473597d706e	2531	*
bogdanm	82:6473597d706e	2532	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2533	*
bogdanm	82:6473597d706e	2534	* TCR is read/write and configures the transmit block. This register is cleared
bogdanm	82:6473597d706e	2535	* at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
bogdanm	82:6473597d706e	2536	*/
bogdanm	82:6473597d706e	2537	typedef union _hw_enet_tcr
bogdanm	82:6473597d706e	2538	{
bogdanm	82:6473597d706e	2539	uint32_t U;
bogdanm	82:6473597d706e	2540	struct _hw_enet_tcr_bitfields
bogdanm	82:6473597d706e	2541	{
bogdanm	82:6473597d706e	2542	uint32_t GTS : 1; //!< [0] Graceful Transmit Stop
bogdanm	82:6473597d706e	2543	uint32_t RESERVED0 : 1; //!< [1]
bogdanm	82:6473597d706e	2544	uint32_t FDEN : 1; //!< [2] Full-Duplex Enable
bogdanm	82:6473597d706e	2545	uint32_t TFC_PAUSE : 1; //!< [3] Transmit Frame Control Pause
bogdanm	82:6473597d706e	2546	uint32_t RFC_PAUSE : 1; //!< [4] Receive Frame Control Pause
bogdanm	82:6473597d706e	2547	uint32_t ADDSEL : 3; //!< [7:5] Source MAC Address Select On Transmit
bogdanm	82:6473597d706e	2548	uint32_t ADDINS : 1; //!< [8] Set MAC Address On Transmit
bogdanm	82:6473597d706e	2549	uint32_t CRCFWD : 1; //!< [9] Forward Frame From Application With CRC
bogdanm	82:6473597d706e	2550	uint32_t RESERVED1 : 22; //!< [31:10]
bogdanm	82:6473597d706e	2551	} B;
bogdanm	82:6473597d706e	2552	} hw_enet_tcr_t;
bogdanm	82:6473597d706e	2553	#endif
bogdanm	82:6473597d706e	2554
bogdanm	82:6473597d706e	2555	/*!
bogdanm	82:6473597d706e	2556	* @name Constants and macros for entire ENET_TCR register
bogdanm	82:6473597d706e	2557	*/
bogdanm	82:6473597d706e	2558	//@{
bogdanm	82:6473597d706e	2559	#define HW_ENET_TCR_ADDR(x) (REGS_ENET_BASE(x) + 0xC4U)
bogdanm	82:6473597d706e	2560
bogdanm	82:6473597d706e	2561	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2562	#define HW_ENET_TCR(x) ((__IO hw_enet_tcr_t ) HW_ENET_TCR_ADDR(x))
bogdanm	82:6473597d706e	2563	#define HW_ENET_TCR_RD(x) (HW_ENET_TCR(x).U)
bogdanm	82:6473597d706e	2564	#define HW_ENET_TCR_WR(x, v) (HW_ENET_TCR(x).U = (v))
bogdanm	82:6473597d706e	2565	#define HW_ENET_TCR_SET(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) \| (v)))
bogdanm	82:6473597d706e	2566	#define HW_ENET_TCR_CLR(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2567	#define HW_ENET_TCR_TOG(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2568	#endif
bogdanm	82:6473597d706e	2569	//@}
bogdanm	82:6473597d706e	2570
bogdanm	82:6473597d706e	2571	/*
bogdanm	82:6473597d706e	2572	* Constants & macros for individual ENET_TCR bitfields
bogdanm	82:6473597d706e	2573	*/
bogdanm	82:6473597d706e	2574
bogdanm	82:6473597d706e	2575	/*!
bogdanm	82:6473597d706e	2576	* @name Register ENET_TCR, field GTS[0] (RW)
bogdanm	82:6473597d706e	2577	*
bogdanm	82:6473597d706e	2578	* When this field is set, MAC stops transmission after any frame currently
bogdanm	82:6473597d706e	2579	* transmitted is complete and EIR[GRA] is set. If frame transmission is not
bogdanm	82:6473597d706e	2580	* currently underway, the GRA interrupt is asserted immediately. After transmission
bogdanm	82:6473597d706e	2581	* finishes, clear GTS to restart. The next frame in the transmit FIFO is then
bogdanm	82:6473597d706e	2582	* transmitted. If an early collision occurs during transmission when GTS is set,
bogdanm	82:6473597d706e	2583	* transmission stops after the collision. The frame is transmitted again after GTS is
bogdanm	82:6473597d706e	2584	* cleared. There may be old frames in the transmit FIFO that transmit when GTS
bogdanm	82:6473597d706e	2585	* is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
bogdanm	82:6473597d706e	2586	*/
bogdanm	82:6473597d706e	2587	//@{
bogdanm	82:6473597d706e	2588	#define BP_ENET_TCR_GTS (0U) //!< Bit position for ENET_TCR_GTS.
bogdanm	82:6473597d706e	2589	#define BM_ENET_TCR_GTS (0x00000001U) //!< Bit mask for ENET_TCR_GTS.
bogdanm	82:6473597d706e	2590	#define BS_ENET_TCR_GTS (1U) //!< Bit field size in bits for ENET_TCR_GTS.
bogdanm	82:6473597d706e	2591
bogdanm	82:6473597d706e	2592	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2593	//! @brief Read current value of the ENET_TCR_GTS field.
bogdanm	82:6473597d706e	2594	#define BR_ENET_TCR_GTS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS))
bogdanm	82:6473597d706e	2595	#endif
bogdanm	82:6473597d706e	2596
bogdanm	82:6473597d706e	2597	//! @brief Format value for bitfield ENET_TCR_GTS.
bogdanm	82:6473597d706e	2598	#define BF_ENET_TCR_GTS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_GTS), uint32_t) & BM_ENET_TCR_GTS)
bogdanm	82:6473597d706e	2599
bogdanm	82:6473597d706e	2600	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2601	//! @brief Set the GTS field to a new value.
bogdanm	82:6473597d706e	2602	#define BW_ENET_TCR_GTS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS) = (v))
bogdanm	82:6473597d706e	2603	#endif
bogdanm	82:6473597d706e	2604	//@}
bogdanm	82:6473597d706e	2605
bogdanm	82:6473597d706e	2606	/*!
bogdanm	82:6473597d706e	2607	* @name Register ENET_TCR, field FDEN[2] (RW)
bogdanm	82:6473597d706e	2608	*
bogdanm	82:6473597d706e	2609	* If this field is set, frames transmit independent of carrier sense and
bogdanm	82:6473597d706e	2610	* collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
bogdanm	82:6473597d706e	2611	*/
bogdanm	82:6473597d706e	2612	//@{
bogdanm	82:6473597d706e	2613	#define BP_ENET_TCR_FDEN (2U) //!< Bit position for ENET_TCR_FDEN.
bogdanm	82:6473597d706e	2614	#define BM_ENET_TCR_FDEN (0x00000004U) //!< Bit mask for ENET_TCR_FDEN.
bogdanm	82:6473597d706e	2615	#define BS_ENET_TCR_FDEN (1U) //!< Bit field size in bits for ENET_TCR_FDEN.
bogdanm	82:6473597d706e	2616
bogdanm	82:6473597d706e	2617	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2618	//! @brief Read current value of the ENET_TCR_FDEN field.
bogdanm	82:6473597d706e	2619	#define BR_ENET_TCR_FDEN(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN))
bogdanm	82:6473597d706e	2620	#endif
bogdanm	82:6473597d706e	2621
bogdanm	82:6473597d706e	2622	//! @brief Format value for bitfield ENET_TCR_FDEN.
bogdanm	82:6473597d706e	2623	#define BF_ENET_TCR_FDEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_FDEN), uint32_t) & BM_ENET_TCR_FDEN)
bogdanm	82:6473597d706e	2624
bogdanm	82:6473597d706e	2625	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2626	//! @brief Set the FDEN field to a new value.
bogdanm	82:6473597d706e	2627	#define BW_ENET_TCR_FDEN(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN) = (v))
bogdanm	82:6473597d706e	2628	#endif
bogdanm	82:6473597d706e	2629	//@}
bogdanm	82:6473597d706e	2630
bogdanm	82:6473597d706e	2631	/*!
bogdanm	82:6473597d706e	2632	* @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
bogdanm	82:6473597d706e	2633	*
bogdanm	82:6473597d706e	2634	* Pauses frame transmission. When this field is set, EIR[GRA] is set. With
bogdanm	82:6473597d706e	2635	* transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
bogdanm	82:6473597d706e	2636	* Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
bogdanm	82:6473597d706e	2637	* transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
bogdanm	82:6473597d706e	2638	* the MAC may continue transmitting a MAC control PAUSE frame.
bogdanm	82:6473597d706e	2639	*
bogdanm	82:6473597d706e	2640	* Values:
bogdanm	82:6473597d706e	2641	* - 0 - No PAUSE frame transmitted.
bogdanm	82:6473597d706e	2642	* - 1 - The MAC stops transmission of data frames after the current
bogdanm	82:6473597d706e	2643	* transmission is complete.
bogdanm	82:6473597d706e	2644	*/
bogdanm	82:6473597d706e	2645	//@{
bogdanm	82:6473597d706e	2646	#define BP_ENET_TCR_TFC_PAUSE (3U) //!< Bit position for ENET_TCR_TFC_PAUSE.
bogdanm	82:6473597d706e	2647	#define BM_ENET_TCR_TFC_PAUSE (0x00000008U) //!< Bit mask for ENET_TCR_TFC_PAUSE.
bogdanm	82:6473597d706e	2648	#define BS_ENET_TCR_TFC_PAUSE (1U) //!< Bit field size in bits for ENET_TCR_TFC_PAUSE.
bogdanm	82:6473597d706e	2649
bogdanm	82:6473597d706e	2650	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2651	//! @brief Read current value of the ENET_TCR_TFC_PAUSE field.
bogdanm	82:6473597d706e	2652	#define BR_ENET_TCR_TFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE))
bogdanm	82:6473597d706e	2653	#endif
bogdanm	82:6473597d706e	2654
bogdanm	82:6473597d706e	2655	//! @brief Format value for bitfield ENET_TCR_TFC_PAUSE.
bogdanm	82:6473597d706e	2656	#define BF_ENET_TCR_TFC_PAUSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_TFC_PAUSE), uint32_t) & BM_ENET_TCR_TFC_PAUSE)
bogdanm	82:6473597d706e	2657
bogdanm	82:6473597d706e	2658	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2659	//! @brief Set the TFC_PAUSE field to a new value.
bogdanm	82:6473597d706e	2660	#define BW_ENET_TCR_TFC_PAUSE(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE) = (v))
bogdanm	82:6473597d706e	2661	#endif
bogdanm	82:6473597d706e	2662	//@}
bogdanm	82:6473597d706e	2663
bogdanm	82:6473597d706e	2664	/*!
bogdanm	82:6473597d706e	2665	* @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
bogdanm	82:6473597d706e	2666	*
bogdanm	82:6473597d706e	2667	* This status field is set when a full-duplex flow control pause frame is
bogdanm	82:6473597d706e	2668	* received and the transmitter pauses for the duration defined in this pause frame.
bogdanm	82:6473597d706e	2669	* This field automatically clears when the pause duration is complete.
bogdanm	82:6473597d706e	2670	*/
bogdanm	82:6473597d706e	2671	//@{
bogdanm	82:6473597d706e	2672	#define BP_ENET_TCR_RFC_PAUSE (4U) //!< Bit position for ENET_TCR_RFC_PAUSE.
bogdanm	82:6473597d706e	2673	#define BM_ENET_TCR_RFC_PAUSE (0x00000010U) //!< Bit mask for ENET_TCR_RFC_PAUSE.
bogdanm	82:6473597d706e	2674	#define BS_ENET_TCR_RFC_PAUSE (1U) //!< Bit field size in bits for ENET_TCR_RFC_PAUSE.
bogdanm	82:6473597d706e	2675
bogdanm	82:6473597d706e	2676	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2677	//! @brief Read current value of the ENET_TCR_RFC_PAUSE field.
bogdanm	82:6473597d706e	2678	#define BR_ENET_TCR_RFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_RFC_PAUSE))
bogdanm	82:6473597d706e	2679	#endif
bogdanm	82:6473597d706e	2680	//@}
bogdanm	82:6473597d706e	2681
bogdanm	82:6473597d706e	2682	/*!
bogdanm	82:6473597d706e	2683	* @name Register ENET_TCR, field ADDSEL[7:5] (RW)
bogdanm	82:6473597d706e	2684	*
bogdanm	82:6473597d706e	2685	* If ADDINS is set, indicates the MAC address that overwrites the source MAC
bogdanm	82:6473597d706e	2686	* address.
bogdanm	82:6473597d706e	2687	*
bogdanm	82:6473597d706e	2688	* Values:
bogdanm	82:6473597d706e	2689	* - 000 - Node MAC address programmed on PADDR1/2 registers.
bogdanm	82:6473597d706e	2690	* - 100 - Reserved.
bogdanm	82:6473597d706e	2691	* - 101 - Reserved.
bogdanm	82:6473597d706e	2692	* - 110 - Reserved.
bogdanm	82:6473597d706e	2693	*/
bogdanm	82:6473597d706e	2694	//@{
bogdanm	82:6473597d706e	2695	#define BP_ENET_TCR_ADDSEL (5U) //!< Bit position for ENET_TCR_ADDSEL.
bogdanm	82:6473597d706e	2696	#define BM_ENET_TCR_ADDSEL (0x000000E0U) //!< Bit mask for ENET_TCR_ADDSEL.
bogdanm	82:6473597d706e	2697	#define BS_ENET_TCR_ADDSEL (3U) //!< Bit field size in bits for ENET_TCR_ADDSEL.
bogdanm	82:6473597d706e	2698
bogdanm	82:6473597d706e	2699	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2700	//! @brief Read current value of the ENET_TCR_ADDSEL field.
bogdanm	82:6473597d706e	2701	#define BR_ENET_TCR_ADDSEL(x) (HW_ENET_TCR(x).B.ADDSEL)
bogdanm	82:6473597d706e	2702	#endif
bogdanm	82:6473597d706e	2703
bogdanm	82:6473597d706e	2704	//! @brief Format value for bitfield ENET_TCR_ADDSEL.
bogdanm	82:6473597d706e	2705	#define BF_ENET_TCR_ADDSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_ADDSEL), uint32_t) & BM_ENET_TCR_ADDSEL)
bogdanm	82:6473597d706e	2706
bogdanm	82:6473597d706e	2707	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2708	//! @brief Set the ADDSEL field to a new value.
bogdanm	82:6473597d706e	2709	#define BW_ENET_TCR_ADDSEL(x, v) (HW_ENET_TCR_WR(x, (HW_ENET_TCR_RD(x) & ~BM_ENET_TCR_ADDSEL) \| BF_ENET_TCR_ADDSEL(v)))
bogdanm	82:6473597d706e	2710	#endif
bogdanm	82:6473597d706e	2711	//@}
bogdanm	82:6473597d706e	2712
bogdanm	82:6473597d706e	2713	/*!
bogdanm	82:6473597d706e	2714	* @name Register ENET_TCR, field ADDINS[8] (RW)
bogdanm	82:6473597d706e	2715	*
bogdanm	82:6473597d706e	2716	* Values:
bogdanm	82:6473597d706e	2717	* - 0 - The source MAC address is not modified by the MAC.
bogdanm	82:6473597d706e	2718	* - 1 - The MAC overwrites the source MAC address with the programmed MAC
bogdanm	82:6473597d706e	2719	* address according to ADDSEL.
bogdanm	82:6473597d706e	2720	*/
bogdanm	82:6473597d706e	2721	//@{
bogdanm	82:6473597d706e	2722	#define BP_ENET_TCR_ADDINS (8U) //!< Bit position for ENET_TCR_ADDINS.
bogdanm	82:6473597d706e	2723	#define BM_ENET_TCR_ADDINS (0x00000100U) //!< Bit mask for ENET_TCR_ADDINS.
bogdanm	82:6473597d706e	2724	#define BS_ENET_TCR_ADDINS (1U) //!< Bit field size in bits for ENET_TCR_ADDINS.
bogdanm	82:6473597d706e	2725
bogdanm	82:6473597d706e	2726	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2727	//! @brief Read current value of the ENET_TCR_ADDINS field.
bogdanm	82:6473597d706e	2728	#define BR_ENET_TCR_ADDINS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS))
bogdanm	82:6473597d706e	2729	#endif
bogdanm	82:6473597d706e	2730
bogdanm	82:6473597d706e	2731	//! @brief Format value for bitfield ENET_TCR_ADDINS.
bogdanm	82:6473597d706e	2732	#define BF_ENET_TCR_ADDINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_ADDINS), uint32_t) & BM_ENET_TCR_ADDINS)
bogdanm	82:6473597d706e	2733
bogdanm	82:6473597d706e	2734	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2735	//! @brief Set the ADDINS field to a new value.
bogdanm	82:6473597d706e	2736	#define BW_ENET_TCR_ADDINS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS) = (v))
bogdanm	82:6473597d706e	2737	#endif
bogdanm	82:6473597d706e	2738	//@}
bogdanm	82:6473597d706e	2739
bogdanm	82:6473597d706e	2740	/*!
bogdanm	82:6473597d706e	2741	* @name Register ENET_TCR, field CRCFWD[9] (RW)
bogdanm	82:6473597d706e	2742	*
bogdanm	82:6473597d706e	2743	* Values:
bogdanm	82:6473597d706e	2744	* - 0 - TxBD[TC] controls whether the frame has a CRC from the application.
bogdanm	82:6473597d706e	2745	* - 1 - The transmitter does not append any CRC to transmitted frames, as it is
bogdanm	82:6473597d706e	2746	* expecting a frame with CRC from the application.
bogdanm	82:6473597d706e	2747	*/
bogdanm	82:6473597d706e	2748	//@{
bogdanm	82:6473597d706e	2749	#define BP_ENET_TCR_CRCFWD (9U) //!< Bit position for ENET_TCR_CRCFWD.
bogdanm	82:6473597d706e	2750	#define BM_ENET_TCR_CRCFWD (0x00000200U) //!< Bit mask for ENET_TCR_CRCFWD.
bogdanm	82:6473597d706e	2751	#define BS_ENET_TCR_CRCFWD (1U) //!< Bit field size in bits for ENET_TCR_CRCFWD.
bogdanm	82:6473597d706e	2752
bogdanm	82:6473597d706e	2753	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2754	//! @brief Read current value of the ENET_TCR_CRCFWD field.
bogdanm	82:6473597d706e	2755	#define BR_ENET_TCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD))
bogdanm	82:6473597d706e	2756	#endif
bogdanm	82:6473597d706e	2757
bogdanm	82:6473597d706e	2758	//! @brief Format value for bitfield ENET_TCR_CRCFWD.
bogdanm	82:6473597d706e	2759	#define BF_ENET_TCR_CRCFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_CRCFWD), uint32_t) & BM_ENET_TCR_CRCFWD)
bogdanm	82:6473597d706e	2760
bogdanm	82:6473597d706e	2761	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2762	//! @brief Set the CRCFWD field to a new value.
bogdanm	82:6473597d706e	2763	#define BW_ENET_TCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD) = (v))
bogdanm	82:6473597d706e	2764	#endif
bogdanm	82:6473597d706e	2765	//@}
bogdanm	82:6473597d706e	2766
bogdanm	82:6473597d706e	2767	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2768	// HW_ENET_PALR - Physical Address Lower Register
bogdanm	82:6473597d706e	2769	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2770
bogdanm	82:6473597d706e	2771	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2772	/*!
bogdanm	82:6473597d706e	2773	* @brief HW_ENET_PALR - Physical Address Lower Register (RW)
bogdanm	82:6473597d706e	2774	*
bogdanm	82:6473597d706e	2775	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2776	*
bogdanm	82:6473597d706e	2777	* PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
bogdanm	82:6473597d706e	2778	* in the address recognition process to compare with the destination address
bogdanm	82:6473597d706e	2779	* (DA) field of receive frames with an individual DA. In addition, this register
bogdanm	82:6473597d706e	2780	* is used in bytes 0 through 3 of the six-byte source address field when
bogdanm	82:6473597d706e	2781	* transmitting PAUSE frames. This register is not reset and you must initialize it.
bogdanm	82:6473597d706e	2782	*/
bogdanm	82:6473597d706e	2783	typedef union _hw_enet_palr
bogdanm	82:6473597d706e	2784	{
bogdanm	82:6473597d706e	2785	uint32_t U;
bogdanm	82:6473597d706e	2786	struct _hw_enet_palr_bitfields
bogdanm	82:6473597d706e	2787	{
bogdanm	82:6473597d706e	2788	uint32_t PADDR1 : 32; //!< [31:0] Pause Address
bogdanm	82:6473597d706e	2789	} B;
bogdanm	82:6473597d706e	2790	} hw_enet_palr_t;
bogdanm	82:6473597d706e	2791	#endif
bogdanm	82:6473597d706e	2792
bogdanm	82:6473597d706e	2793	/*!
bogdanm	82:6473597d706e	2794	* @name Constants and macros for entire ENET_PALR register
bogdanm	82:6473597d706e	2795	*/
bogdanm	82:6473597d706e	2796	//@{
bogdanm	82:6473597d706e	2797	#define HW_ENET_PALR_ADDR(x) (REGS_ENET_BASE(x) + 0xE4U)
bogdanm	82:6473597d706e	2798
bogdanm	82:6473597d706e	2799	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2800	#define HW_ENET_PALR(x) ((__IO hw_enet_palr_t ) HW_ENET_PALR_ADDR(x))
bogdanm	82:6473597d706e	2801	#define HW_ENET_PALR_RD(x) (HW_ENET_PALR(x).U)
bogdanm	82:6473597d706e	2802	#define HW_ENET_PALR_WR(x, v) (HW_ENET_PALR(x).U = (v))
bogdanm	82:6473597d706e	2803	#define HW_ENET_PALR_SET(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) \| (v)))
bogdanm	82:6473597d706e	2804	#define HW_ENET_PALR_CLR(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2805	#define HW_ENET_PALR_TOG(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2806	#endif
bogdanm	82:6473597d706e	2807	//@}
bogdanm	82:6473597d706e	2808
bogdanm	82:6473597d706e	2809	/*
bogdanm	82:6473597d706e	2810	* Constants & macros for individual ENET_PALR bitfields
bogdanm	82:6473597d706e	2811	*/
bogdanm	82:6473597d706e	2812
bogdanm	82:6473597d706e	2813	/*!
bogdanm	82:6473597d706e	2814	* @name Register ENET_PALR, field PADDR1[31:0] (RW)
bogdanm	82:6473597d706e	2815	*
bogdanm	82:6473597d706e	2816	* Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the
bogdanm	82:6473597d706e	2817	* 6-byte individual address are used for exact match and the source address
bogdanm	82:6473597d706e	2818	* field in PAUSE frames.
bogdanm	82:6473597d706e	2819	*/
bogdanm	82:6473597d706e	2820	//@{
bogdanm	82:6473597d706e	2821	#define BP_ENET_PALR_PADDR1 (0U) //!< Bit position for ENET_PALR_PADDR1.
bogdanm	82:6473597d706e	2822	#define BM_ENET_PALR_PADDR1 (0xFFFFFFFFU) //!< Bit mask for ENET_PALR_PADDR1.
bogdanm	82:6473597d706e	2823	#define BS_ENET_PALR_PADDR1 (32U) //!< Bit field size in bits for ENET_PALR_PADDR1.
bogdanm	82:6473597d706e	2824
bogdanm	82:6473597d706e	2825	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2826	//! @brief Read current value of the ENET_PALR_PADDR1 field.
bogdanm	82:6473597d706e	2827	#define BR_ENET_PALR_PADDR1(x) (HW_ENET_PALR(x).U)
bogdanm	82:6473597d706e	2828	#endif
bogdanm	82:6473597d706e	2829
bogdanm	82:6473597d706e	2830	//! @brief Format value for bitfield ENET_PALR_PADDR1.
bogdanm	82:6473597d706e	2831	#define BF_ENET_PALR_PADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_PALR_PADDR1), uint32_t) & BM_ENET_PALR_PADDR1)
bogdanm	82:6473597d706e	2832
bogdanm	82:6473597d706e	2833	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2834	//! @brief Set the PADDR1 field to a new value.
bogdanm	82:6473597d706e	2835	#define BW_ENET_PALR_PADDR1(x, v) (HW_ENET_PALR_WR(x, v))
bogdanm	82:6473597d706e	2836	#endif
bogdanm	82:6473597d706e	2837	//@}
bogdanm	82:6473597d706e	2838
bogdanm	82:6473597d706e	2839	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2840	// HW_ENET_PAUR - Physical Address Upper Register
bogdanm	82:6473597d706e	2841	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2842
bogdanm	82:6473597d706e	2843	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2844	/*!
bogdanm	82:6473597d706e	2845	* @brief HW_ENET_PAUR - Physical Address Upper Register (RW)
bogdanm	82:6473597d706e	2846	*
bogdanm	82:6473597d706e	2847	* Reset value: 0x00008808U
bogdanm	82:6473597d706e	2848	*
bogdanm	82:6473597d706e	2849	* PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
bogdanm	82:6473597d706e	2850	* the address recognition process to compare with the destination address (DA)
bogdanm	82:6473597d706e	2851	* field of receive frames with an individual DA. In addition, this register is
bogdanm	82:6473597d706e	2852	* used in bytes 4 and 5 of the six-byte source address field when transmitting
bogdanm	82:6473597d706e	2853	* PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
bogdanm	82:6473597d706e	2854	* transmission of PAUSE frames. The upper 16 bits of this register are not reset and
bogdanm	82:6473597d706e	2855	* you must initialize it.
bogdanm	82:6473597d706e	2856	*/
bogdanm	82:6473597d706e	2857	typedef union _hw_enet_paur
bogdanm	82:6473597d706e	2858	{
bogdanm	82:6473597d706e	2859	uint32_t U;
bogdanm	82:6473597d706e	2860	struct _hw_enet_paur_bitfields
bogdanm	82:6473597d706e	2861	{
bogdanm	82:6473597d706e	2862	uint32_t TYPE : 16; //!< [15:0] Type Field In PAUSE Frames
bogdanm	82:6473597d706e	2863	uint32_t PADDR2 : 16; //!< [31:16]
bogdanm	82:6473597d706e	2864	} B;
bogdanm	82:6473597d706e	2865	} hw_enet_paur_t;
bogdanm	82:6473597d706e	2866	#endif
bogdanm	82:6473597d706e	2867
bogdanm	82:6473597d706e	2868	/*!
bogdanm	82:6473597d706e	2869	* @name Constants and macros for entire ENET_PAUR register
bogdanm	82:6473597d706e	2870	*/
bogdanm	82:6473597d706e	2871	//@{
bogdanm	82:6473597d706e	2872	#define HW_ENET_PAUR_ADDR(x) (REGS_ENET_BASE(x) + 0xE8U)
bogdanm	82:6473597d706e	2873
bogdanm	82:6473597d706e	2874	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2875	#define HW_ENET_PAUR(x) ((__IO hw_enet_paur_t ) HW_ENET_PAUR_ADDR(x))
bogdanm	82:6473597d706e	2876	#define HW_ENET_PAUR_RD(x) (HW_ENET_PAUR(x).U)
bogdanm	82:6473597d706e	2877	#define HW_ENET_PAUR_WR(x, v) (HW_ENET_PAUR(x).U = (v))
bogdanm	82:6473597d706e	2878	#define HW_ENET_PAUR_SET(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) \| (v)))
bogdanm	82:6473597d706e	2879	#define HW_ENET_PAUR_CLR(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2880	#define HW_ENET_PAUR_TOG(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2881	#endif
bogdanm	82:6473597d706e	2882	//@}
bogdanm	82:6473597d706e	2883
bogdanm	82:6473597d706e	2884	/*
bogdanm	82:6473597d706e	2885	* Constants & macros for individual ENET_PAUR bitfields
bogdanm	82:6473597d706e	2886	*/
bogdanm	82:6473597d706e	2887
bogdanm	82:6473597d706e	2888	/*!
bogdanm	82:6473597d706e	2889	* @name Register ENET_PAUR, field TYPE[15:0] (RO)
bogdanm	82:6473597d706e	2890	*
bogdanm	82:6473597d706e	2891	* These fields have a constant value of 0x8808.
bogdanm	82:6473597d706e	2892	*/
bogdanm	82:6473597d706e	2893	//@{
bogdanm	82:6473597d706e	2894	#define BP_ENET_PAUR_TYPE (0U) //!< Bit position for ENET_PAUR_TYPE.
bogdanm	82:6473597d706e	2895	#define BM_ENET_PAUR_TYPE (0x0000FFFFU) //!< Bit mask for ENET_PAUR_TYPE.
bogdanm	82:6473597d706e	2896	#define BS_ENET_PAUR_TYPE (16U) //!< Bit field size in bits for ENET_PAUR_TYPE.
bogdanm	82:6473597d706e	2897
bogdanm	82:6473597d706e	2898	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2899	//! @brief Read current value of the ENET_PAUR_TYPE field.
bogdanm	82:6473597d706e	2900	#define BR_ENET_PAUR_TYPE(x) (HW_ENET_PAUR(x).B.TYPE)
bogdanm	82:6473597d706e	2901	#endif
bogdanm	82:6473597d706e	2902	//@}
bogdanm	82:6473597d706e	2903
bogdanm	82:6473597d706e	2904	/*!
bogdanm	82:6473597d706e	2905	* @name Register ENET_PAUR, field PADDR2[31:16] (RW)
bogdanm	82:6473597d706e	2906	*
bogdanm	82:6473597d706e	2907	* Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
bogdanm	82:6473597d706e	2908	* for exact match, and the source address field in PAUSE frames.
bogdanm	82:6473597d706e	2909	*/
bogdanm	82:6473597d706e	2910	//@{
bogdanm	82:6473597d706e	2911	#define BP_ENET_PAUR_PADDR2 (16U) //!< Bit position for ENET_PAUR_PADDR2.
bogdanm	82:6473597d706e	2912	#define BM_ENET_PAUR_PADDR2 (0xFFFF0000U) //!< Bit mask for ENET_PAUR_PADDR2.
bogdanm	82:6473597d706e	2913	#define BS_ENET_PAUR_PADDR2 (16U) //!< Bit field size in bits for ENET_PAUR_PADDR2.
bogdanm	82:6473597d706e	2914
bogdanm	82:6473597d706e	2915	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2916	//! @brief Read current value of the ENET_PAUR_PADDR2 field.
bogdanm	82:6473597d706e	2917	#define BR_ENET_PAUR_PADDR2(x) (HW_ENET_PAUR(x).B.PADDR2)
bogdanm	82:6473597d706e	2918	#endif
bogdanm	82:6473597d706e	2919
bogdanm	82:6473597d706e	2920	//! @brief Format value for bitfield ENET_PAUR_PADDR2.
bogdanm	82:6473597d706e	2921	#define BF_ENET_PAUR_PADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_PAUR_PADDR2), uint32_t) & BM_ENET_PAUR_PADDR2)
bogdanm	82:6473597d706e	2922
bogdanm	82:6473597d706e	2923	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2924	//! @brief Set the PADDR2 field to a new value.
bogdanm	82:6473597d706e	2925	#define BW_ENET_PAUR_PADDR2(x, v) (HW_ENET_PAUR_WR(x, (HW_ENET_PAUR_RD(x) & ~BM_ENET_PAUR_PADDR2) \| BF_ENET_PAUR_PADDR2(v)))
bogdanm	82:6473597d706e	2926	#endif
bogdanm	82:6473597d706e	2927	//@}
bogdanm	82:6473597d706e	2928
bogdanm	82:6473597d706e	2929	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2930	// HW_ENET_OPD - Opcode/Pause Duration Register
bogdanm	82:6473597d706e	2931	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2932
bogdanm	82:6473597d706e	2933	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2934	/*!
bogdanm	82:6473597d706e	2935	* @brief HW_ENET_OPD - Opcode/Pause Duration Register (RW)
bogdanm	82:6473597d706e	2936	*
bogdanm	82:6473597d706e	2937	* Reset value: 0x00010000U
bogdanm	82:6473597d706e	2938	*
bogdanm	82:6473597d706e	2939	* OPD is read/write accessible. This register contains the 16-bit opcode and
bogdanm	82:6473597d706e	2940	* 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
bogdanm	82:6473597d706e	2941	* field is a constant value, 0x0001. When another node detects a PAUSE frame,
bogdanm	82:6473597d706e	2942	* that node pauses transmission for the duration specified in the pause duration
bogdanm	82:6473597d706e	2943	* field. The lower 16 bits of this register are not reset and you must initialize
bogdanm	82:6473597d706e	2944	* it.
bogdanm	82:6473597d706e	2945	*/
bogdanm	82:6473597d706e	2946	typedef union _hw_enet_opd
bogdanm	82:6473597d706e	2947	{
bogdanm	82:6473597d706e	2948	uint32_t U;
bogdanm	82:6473597d706e	2949	struct _hw_enet_opd_bitfields
bogdanm	82:6473597d706e	2950	{
bogdanm	82:6473597d706e	2951	uint32_t PAUSE_DUR : 16; //!< [15:0] Pause Duration
bogdanm	82:6473597d706e	2952	uint32_t OPCODE : 16; //!< [31:16] Opcode Field In PAUSE Frames
bogdanm	82:6473597d706e	2953	} B;
bogdanm	82:6473597d706e	2954	} hw_enet_opd_t;
bogdanm	82:6473597d706e	2955	#endif
bogdanm	82:6473597d706e	2956
bogdanm	82:6473597d706e	2957	/*!
bogdanm	82:6473597d706e	2958	* @name Constants and macros for entire ENET_OPD register
bogdanm	82:6473597d706e	2959	*/
bogdanm	82:6473597d706e	2960	//@{
bogdanm	82:6473597d706e	2961	#define HW_ENET_OPD_ADDR(x) (REGS_ENET_BASE(x) + 0xECU)
bogdanm	82:6473597d706e	2962
bogdanm	82:6473597d706e	2963	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2964	#define HW_ENET_OPD(x) ((__IO hw_enet_opd_t ) HW_ENET_OPD_ADDR(x))
bogdanm	82:6473597d706e	2965	#define HW_ENET_OPD_RD(x) (HW_ENET_OPD(x).U)
bogdanm	82:6473597d706e	2966	#define HW_ENET_OPD_WR(x, v) (HW_ENET_OPD(x).U = (v))
bogdanm	82:6473597d706e	2967	#define HW_ENET_OPD_SET(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) \| (v)))
bogdanm	82:6473597d706e	2968	#define HW_ENET_OPD_CLR(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2969	#define HW_ENET_OPD_TOG(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2970	#endif
bogdanm	82:6473597d706e	2971	//@}
bogdanm	82:6473597d706e	2972
bogdanm	82:6473597d706e	2973	/*
bogdanm	82:6473597d706e	2974	* Constants & macros for individual ENET_OPD bitfields
bogdanm	82:6473597d706e	2975	*/
bogdanm	82:6473597d706e	2976
bogdanm	82:6473597d706e	2977	/*!
bogdanm	82:6473597d706e	2978	* @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
bogdanm	82:6473597d706e	2979	*
bogdanm	82:6473597d706e	2980	* Pause duration field used in PAUSE frames.
bogdanm	82:6473597d706e	2981	*/
bogdanm	82:6473597d706e	2982	//@{
bogdanm	82:6473597d706e	2983	#define BP_ENET_OPD_PAUSE_DUR (0U) //!< Bit position for ENET_OPD_PAUSE_DUR.
bogdanm	82:6473597d706e	2984	#define BM_ENET_OPD_PAUSE_DUR (0x0000FFFFU) //!< Bit mask for ENET_OPD_PAUSE_DUR.
bogdanm	82:6473597d706e	2985	#define BS_ENET_OPD_PAUSE_DUR (16U) //!< Bit field size in bits for ENET_OPD_PAUSE_DUR.
bogdanm	82:6473597d706e	2986
bogdanm	82:6473597d706e	2987	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2988	//! @brief Read current value of the ENET_OPD_PAUSE_DUR field.
bogdanm	82:6473597d706e	2989	#define BR_ENET_OPD_PAUSE_DUR(x) (HW_ENET_OPD(x).B.PAUSE_DUR)
bogdanm	82:6473597d706e	2990	#endif
bogdanm	82:6473597d706e	2991
bogdanm	82:6473597d706e	2992	//! @brief Format value for bitfield ENET_OPD_PAUSE_DUR.
bogdanm	82:6473597d706e	2993	#define BF_ENET_OPD_PAUSE_DUR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_OPD_PAUSE_DUR), uint32_t) & BM_ENET_OPD_PAUSE_DUR)
bogdanm	82:6473597d706e	2994
bogdanm	82:6473597d706e	2995	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2996	//! @brief Set the PAUSE_DUR field to a new value.
bogdanm	82:6473597d706e	2997	#define BW_ENET_OPD_PAUSE_DUR(x, v) (HW_ENET_OPD_WR(x, (HW_ENET_OPD_RD(x) & ~BM_ENET_OPD_PAUSE_DUR) \| BF_ENET_OPD_PAUSE_DUR(v)))
bogdanm	82:6473597d706e	2998	#endif
bogdanm	82:6473597d706e	2999	//@}
bogdanm	82:6473597d706e	3000
bogdanm	82:6473597d706e	3001	/*!
bogdanm	82:6473597d706e	3002	* @name Register ENET_OPD, field OPCODE[31:16] (RO)
bogdanm	82:6473597d706e	3003	*
bogdanm	82:6473597d706e	3004	* These fields have a constant value of 0x0001.
bogdanm	82:6473597d706e	3005	*/
bogdanm	82:6473597d706e	3006	//@{
bogdanm	82:6473597d706e	3007	#define BP_ENET_OPD_OPCODE (16U) //!< Bit position for ENET_OPD_OPCODE.
bogdanm	82:6473597d706e	3008	#define BM_ENET_OPD_OPCODE (0xFFFF0000U) //!< Bit mask for ENET_OPD_OPCODE.
bogdanm	82:6473597d706e	3009	#define BS_ENET_OPD_OPCODE (16U) //!< Bit field size in bits for ENET_OPD_OPCODE.
bogdanm	82:6473597d706e	3010
bogdanm	82:6473597d706e	3011	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3012	//! @brief Read current value of the ENET_OPD_OPCODE field.
bogdanm	82:6473597d706e	3013	#define BR_ENET_OPD_OPCODE(x) (HW_ENET_OPD(x).B.OPCODE)
bogdanm	82:6473597d706e	3014	#endif
bogdanm	82:6473597d706e	3015	//@}
bogdanm	82:6473597d706e	3016
bogdanm	82:6473597d706e	3017	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3018	// HW_ENET_IAUR - Descriptor Individual Upper Address Register
bogdanm	82:6473597d706e	3019	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3020
bogdanm	82:6473597d706e	3021	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3022	/*!
bogdanm	82:6473597d706e	3023	* @brief HW_ENET_IAUR - Descriptor Individual Upper Address Register (RW)
bogdanm	82:6473597d706e	3024	*
bogdanm	82:6473597d706e	3025	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3026	*
bogdanm	82:6473597d706e	3027	* IAUR contains the upper 32 bits of the 64-bit individual address hash table.
bogdanm	82:6473597d706e	3028	* The address recognition process uses this table to check for a possible match
bogdanm	82:6473597d706e	3029	* with the destination address (DA) field of receive frames with an individual
bogdanm	82:6473597d706e	3030	* DA. This register is not reset and you must initialize it.
bogdanm	82:6473597d706e	3031	*/
bogdanm	82:6473597d706e	3032	typedef union _hw_enet_iaur
bogdanm	82:6473597d706e	3033	{
bogdanm	82:6473597d706e	3034	uint32_t U;
bogdanm	82:6473597d706e	3035	struct _hw_enet_iaur_bitfields
bogdanm	82:6473597d706e	3036	{
bogdanm	82:6473597d706e	3037	uint32_t IADDR1 : 32; //!< [31:0]
bogdanm	82:6473597d706e	3038	} B;
bogdanm	82:6473597d706e	3039	} hw_enet_iaur_t;
bogdanm	82:6473597d706e	3040	#endif
bogdanm	82:6473597d706e	3041
bogdanm	82:6473597d706e	3042	/*!
bogdanm	82:6473597d706e	3043	* @name Constants and macros for entire ENET_IAUR register
bogdanm	82:6473597d706e	3044	*/
bogdanm	82:6473597d706e	3045	//@{
bogdanm	82:6473597d706e	3046	#define HW_ENET_IAUR_ADDR(x) (REGS_ENET_BASE(x) + 0x118U)
bogdanm	82:6473597d706e	3047
bogdanm	82:6473597d706e	3048	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3049	#define HW_ENET_IAUR(x) ((__IO hw_enet_iaur_t ) HW_ENET_IAUR_ADDR(x))
bogdanm	82:6473597d706e	3050	#define HW_ENET_IAUR_RD(x) (HW_ENET_IAUR(x).U)
bogdanm	82:6473597d706e	3051	#define HW_ENET_IAUR_WR(x, v) (HW_ENET_IAUR(x).U = (v))
bogdanm	82:6473597d706e	3052	#define HW_ENET_IAUR_SET(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) \| (v)))
bogdanm	82:6473597d706e	3053	#define HW_ENET_IAUR_CLR(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3054	#define HW_ENET_IAUR_TOG(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3055	#endif
bogdanm	82:6473597d706e	3056	//@}
bogdanm	82:6473597d706e	3057
bogdanm	82:6473597d706e	3058	/*
bogdanm	82:6473597d706e	3059	* Constants & macros for individual ENET_IAUR bitfields
bogdanm	82:6473597d706e	3060	*/
bogdanm	82:6473597d706e	3061
bogdanm	82:6473597d706e	3062	/*!
bogdanm	82:6473597d706e	3063	* @name Register ENET_IAUR, field IADDR1[31:0] (RW)
bogdanm	82:6473597d706e	3064	*
bogdanm	82:6473597d706e	3065	* Contains the upper 32 bits of the 64-bit hash table used in the address
bogdanm	82:6473597d706e	3066	* recognition process for receive frames with a unicast address. Bit 31 of IADDR1
bogdanm	82:6473597d706e	3067	* contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
bogdanm	82:6473597d706e	3068	*/
bogdanm	82:6473597d706e	3069	//@{
bogdanm	82:6473597d706e	3070	#define BP_ENET_IAUR_IADDR1 (0U) //!< Bit position for ENET_IAUR_IADDR1.
bogdanm	82:6473597d706e	3071	#define BM_ENET_IAUR_IADDR1 (0xFFFFFFFFU) //!< Bit mask for ENET_IAUR_IADDR1.
bogdanm	82:6473597d706e	3072	#define BS_ENET_IAUR_IADDR1 (32U) //!< Bit field size in bits for ENET_IAUR_IADDR1.
bogdanm	82:6473597d706e	3073
bogdanm	82:6473597d706e	3074	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3075	//! @brief Read current value of the ENET_IAUR_IADDR1 field.
bogdanm	82:6473597d706e	3076	#define BR_ENET_IAUR_IADDR1(x) (HW_ENET_IAUR(x).U)
bogdanm	82:6473597d706e	3077	#endif
bogdanm	82:6473597d706e	3078
bogdanm	82:6473597d706e	3079	//! @brief Format value for bitfield ENET_IAUR_IADDR1.
bogdanm	82:6473597d706e	3080	#define BF_ENET_IAUR_IADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_IAUR_IADDR1), uint32_t) & BM_ENET_IAUR_IADDR1)
bogdanm	82:6473597d706e	3081
bogdanm	82:6473597d706e	3082	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3083	//! @brief Set the IADDR1 field to a new value.
bogdanm	82:6473597d706e	3084	#define BW_ENET_IAUR_IADDR1(x, v) (HW_ENET_IAUR_WR(x, v))
bogdanm	82:6473597d706e	3085	#endif
bogdanm	82:6473597d706e	3086	//@}
bogdanm	82:6473597d706e	3087
bogdanm	82:6473597d706e	3088	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3089	// HW_ENET_IALR - Descriptor Individual Lower Address Register
bogdanm	82:6473597d706e	3090	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3091
bogdanm	82:6473597d706e	3092	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3093	/*!
bogdanm	82:6473597d706e	3094	* @brief HW_ENET_IALR - Descriptor Individual Lower Address Register (RW)
bogdanm	82:6473597d706e	3095	*
bogdanm	82:6473597d706e	3096	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3097	*
bogdanm	82:6473597d706e	3098	* IALR contains the lower 32 bits of the 64-bit individual address hash table.
bogdanm	82:6473597d706e	3099	* The address recognition process uses this table to check for a possible match
bogdanm	82:6473597d706e	3100	* with the DA field of receive frames with an individual DA. This register is
bogdanm	82:6473597d706e	3101	* not reset and you must initialize it.
bogdanm	82:6473597d706e	3102	*/
bogdanm	82:6473597d706e	3103	typedef union _hw_enet_ialr
bogdanm	82:6473597d706e	3104	{
bogdanm	82:6473597d706e	3105	uint32_t U;
bogdanm	82:6473597d706e	3106	struct _hw_enet_ialr_bitfields
bogdanm	82:6473597d706e	3107	{
bogdanm	82:6473597d706e	3108	uint32_t IADDR2 : 32; //!< [31:0]
bogdanm	82:6473597d706e	3109	} B;
bogdanm	82:6473597d706e	3110	} hw_enet_ialr_t;
bogdanm	82:6473597d706e	3111	#endif
bogdanm	82:6473597d706e	3112
bogdanm	82:6473597d706e	3113	/*!
bogdanm	82:6473597d706e	3114	* @name Constants and macros for entire ENET_IALR register
bogdanm	82:6473597d706e	3115	*/
bogdanm	82:6473597d706e	3116	//@{
bogdanm	82:6473597d706e	3117	#define HW_ENET_IALR_ADDR(x) (REGS_ENET_BASE(x) + 0x11CU)
bogdanm	82:6473597d706e	3118
bogdanm	82:6473597d706e	3119	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3120	#define HW_ENET_IALR(x) ((__IO hw_enet_ialr_t ) HW_ENET_IALR_ADDR(x))
bogdanm	82:6473597d706e	3121	#define HW_ENET_IALR_RD(x) (HW_ENET_IALR(x).U)
bogdanm	82:6473597d706e	3122	#define HW_ENET_IALR_WR(x, v) (HW_ENET_IALR(x).U = (v))
bogdanm	82:6473597d706e	3123	#define HW_ENET_IALR_SET(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) \| (v)))
bogdanm	82:6473597d706e	3124	#define HW_ENET_IALR_CLR(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3125	#define HW_ENET_IALR_TOG(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3126	#endif
bogdanm	82:6473597d706e	3127	//@}
bogdanm	82:6473597d706e	3128
bogdanm	82:6473597d706e	3129	/*
bogdanm	82:6473597d706e	3130	* Constants & macros for individual ENET_IALR bitfields
bogdanm	82:6473597d706e	3131	*/
bogdanm	82:6473597d706e	3132
bogdanm	82:6473597d706e	3133	/*!
bogdanm	82:6473597d706e	3134	* @name Register ENET_IALR, field IADDR2[31:0] (RW)
bogdanm	82:6473597d706e	3135	*
bogdanm	82:6473597d706e	3136	* Contains the lower 32 bits of the 64-bit hash table used in the address
bogdanm	82:6473597d706e	3137	* recognition process for receive frames with a unicast address. Bit 31 of IADDR2
bogdanm	82:6473597d706e	3138	* contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
bogdanm	82:6473597d706e	3139	*/
bogdanm	82:6473597d706e	3140	//@{
bogdanm	82:6473597d706e	3141	#define BP_ENET_IALR_IADDR2 (0U) //!< Bit position for ENET_IALR_IADDR2.
bogdanm	82:6473597d706e	3142	#define BM_ENET_IALR_IADDR2 (0xFFFFFFFFU) //!< Bit mask for ENET_IALR_IADDR2.
bogdanm	82:6473597d706e	3143	#define BS_ENET_IALR_IADDR2 (32U) //!< Bit field size in bits for ENET_IALR_IADDR2.
bogdanm	82:6473597d706e	3144
bogdanm	82:6473597d706e	3145	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3146	//! @brief Read current value of the ENET_IALR_IADDR2 field.
bogdanm	82:6473597d706e	3147	#define BR_ENET_IALR_IADDR2(x) (HW_ENET_IALR(x).U)
bogdanm	82:6473597d706e	3148	#endif
bogdanm	82:6473597d706e	3149
bogdanm	82:6473597d706e	3150	//! @brief Format value for bitfield ENET_IALR_IADDR2.
bogdanm	82:6473597d706e	3151	#define BF_ENET_IALR_IADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_IALR_IADDR2), uint32_t) & BM_ENET_IALR_IADDR2)
bogdanm	82:6473597d706e	3152
bogdanm	82:6473597d706e	3153	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3154	//! @brief Set the IADDR2 field to a new value.
bogdanm	82:6473597d706e	3155	#define BW_ENET_IALR_IADDR2(x, v) (HW_ENET_IALR_WR(x, v))
bogdanm	82:6473597d706e	3156	#endif
bogdanm	82:6473597d706e	3157	//@}
bogdanm	82:6473597d706e	3158
bogdanm	82:6473597d706e	3159	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3160	// HW_ENET_GAUR - Descriptor Group Upper Address Register
bogdanm	82:6473597d706e	3161	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3162
bogdanm	82:6473597d706e	3163	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3164	/*!
bogdanm	82:6473597d706e	3165	* @brief HW_ENET_GAUR - Descriptor Group Upper Address Register (RW)
bogdanm	82:6473597d706e	3166	*
bogdanm	82:6473597d706e	3167	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3168	*
bogdanm	82:6473597d706e	3169	* GAUR contains the upper 32 bits of the 64-bit hash table used in the address
bogdanm	82:6473597d706e	3170	* recognition process for receive frames with a multicast address. You must
bogdanm	82:6473597d706e	3171	* initialize this register.
bogdanm	82:6473597d706e	3172	*/
bogdanm	82:6473597d706e	3173	typedef union _hw_enet_gaur
bogdanm	82:6473597d706e	3174	{
bogdanm	82:6473597d706e	3175	uint32_t U;
bogdanm	82:6473597d706e	3176	struct _hw_enet_gaur_bitfields
bogdanm	82:6473597d706e	3177	{
bogdanm	82:6473597d706e	3178	uint32_t GADDR1 : 32; //!< [31:0]
bogdanm	82:6473597d706e	3179	} B;
bogdanm	82:6473597d706e	3180	} hw_enet_gaur_t;
bogdanm	82:6473597d706e	3181	#endif
bogdanm	82:6473597d706e	3182
bogdanm	82:6473597d706e	3183	/*!
bogdanm	82:6473597d706e	3184	* @name Constants and macros for entire ENET_GAUR register
bogdanm	82:6473597d706e	3185	*/
bogdanm	82:6473597d706e	3186	//@{
bogdanm	82:6473597d706e	3187	#define HW_ENET_GAUR_ADDR(x) (REGS_ENET_BASE(x) + 0x120U)
bogdanm	82:6473597d706e	3188
bogdanm	82:6473597d706e	3189	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3190	#define HW_ENET_GAUR(x) ((__IO hw_enet_gaur_t ) HW_ENET_GAUR_ADDR(x))
bogdanm	82:6473597d706e	3191	#define HW_ENET_GAUR_RD(x) (HW_ENET_GAUR(x).U)
bogdanm	82:6473597d706e	3192	#define HW_ENET_GAUR_WR(x, v) (HW_ENET_GAUR(x).U = (v))
bogdanm	82:6473597d706e	3193	#define HW_ENET_GAUR_SET(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) \| (v)))
bogdanm	82:6473597d706e	3194	#define HW_ENET_GAUR_CLR(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3195	#define HW_ENET_GAUR_TOG(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3196	#endif
bogdanm	82:6473597d706e	3197	//@}
bogdanm	82:6473597d706e	3198
bogdanm	82:6473597d706e	3199	/*
bogdanm	82:6473597d706e	3200	* Constants & macros for individual ENET_GAUR bitfields
bogdanm	82:6473597d706e	3201	*/
bogdanm	82:6473597d706e	3202
bogdanm	82:6473597d706e	3203	/*!
bogdanm	82:6473597d706e	3204	* @name Register ENET_GAUR, field GADDR1[31:0] (RW)
bogdanm	82:6473597d706e	3205	*
bogdanm	82:6473597d706e	3206	* Contains the upper 32 bits of the 64-bit hash table used in the address
bogdanm	82:6473597d706e	3207	* recognition process for receive frames with a multicast address. Bit 31 of GADDR1
bogdanm	82:6473597d706e	3208	* contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
bogdanm	82:6473597d706e	3209	*/
bogdanm	82:6473597d706e	3210	//@{
bogdanm	82:6473597d706e	3211	#define BP_ENET_GAUR_GADDR1 (0U) //!< Bit position for ENET_GAUR_GADDR1.
bogdanm	82:6473597d706e	3212	#define BM_ENET_GAUR_GADDR1 (0xFFFFFFFFU) //!< Bit mask for ENET_GAUR_GADDR1.
bogdanm	82:6473597d706e	3213	#define BS_ENET_GAUR_GADDR1 (32U) //!< Bit field size in bits for ENET_GAUR_GADDR1.
bogdanm	82:6473597d706e	3214
bogdanm	82:6473597d706e	3215	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3216	//! @brief Read current value of the ENET_GAUR_GADDR1 field.
bogdanm	82:6473597d706e	3217	#define BR_ENET_GAUR_GADDR1(x) (HW_ENET_GAUR(x).U)
bogdanm	82:6473597d706e	3218	#endif
bogdanm	82:6473597d706e	3219
bogdanm	82:6473597d706e	3220	//! @brief Format value for bitfield ENET_GAUR_GADDR1.
bogdanm	82:6473597d706e	3221	#define BF_ENET_GAUR_GADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_GAUR_GADDR1), uint32_t) & BM_ENET_GAUR_GADDR1)
bogdanm	82:6473597d706e	3222
bogdanm	82:6473597d706e	3223	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3224	//! @brief Set the GADDR1 field to a new value.
bogdanm	82:6473597d706e	3225	#define BW_ENET_GAUR_GADDR1(x, v) (HW_ENET_GAUR_WR(x, v))
bogdanm	82:6473597d706e	3226	#endif
bogdanm	82:6473597d706e	3227	//@}
bogdanm	82:6473597d706e	3228
bogdanm	82:6473597d706e	3229	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3230	// HW_ENET_GALR - Descriptor Group Lower Address Register
bogdanm	82:6473597d706e	3231	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3232
bogdanm	82:6473597d706e	3233	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3234	/*!
bogdanm	82:6473597d706e	3235	* @brief HW_ENET_GALR - Descriptor Group Lower Address Register (RW)
bogdanm	82:6473597d706e	3236	*
bogdanm	82:6473597d706e	3237	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3238	*
bogdanm	82:6473597d706e	3239	* GALR contains the lower 32 bits of the 64-bit hash table used in the address
bogdanm	82:6473597d706e	3240	* recognition process for receive frames with a multicast address. You must
bogdanm	82:6473597d706e	3241	* initialize this register.
bogdanm	82:6473597d706e	3242	*/
bogdanm	82:6473597d706e	3243	typedef union _hw_enet_galr
bogdanm	82:6473597d706e	3244	{
bogdanm	82:6473597d706e	3245	uint32_t U;
bogdanm	82:6473597d706e	3246	struct _hw_enet_galr_bitfields
bogdanm	82:6473597d706e	3247	{
bogdanm	82:6473597d706e	3248	uint32_t GADDR2 : 32; //!< [31:0]
bogdanm	82:6473597d706e	3249	} B;
bogdanm	82:6473597d706e	3250	} hw_enet_galr_t;
bogdanm	82:6473597d706e	3251	#endif
bogdanm	82:6473597d706e	3252
bogdanm	82:6473597d706e	3253	/*!
bogdanm	82:6473597d706e	3254	* @name Constants and macros for entire ENET_GALR register
bogdanm	82:6473597d706e	3255	*/
bogdanm	82:6473597d706e	3256	//@{
bogdanm	82:6473597d706e	3257	#define HW_ENET_GALR_ADDR(x) (REGS_ENET_BASE(x) + 0x124U)
bogdanm	82:6473597d706e	3258
bogdanm	82:6473597d706e	3259	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3260	#define HW_ENET_GALR(x) ((__IO hw_enet_galr_t ) HW_ENET_GALR_ADDR(x))
bogdanm	82:6473597d706e	3261	#define HW_ENET_GALR_RD(x) (HW_ENET_GALR(x).U)
bogdanm	82:6473597d706e	3262	#define HW_ENET_GALR_WR(x, v) (HW_ENET_GALR(x).U = (v))
bogdanm	82:6473597d706e	3263	#define HW_ENET_GALR_SET(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) \| (v)))
bogdanm	82:6473597d706e	3264	#define HW_ENET_GALR_CLR(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3265	#define HW_ENET_GALR_TOG(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3266	#endif
bogdanm	82:6473597d706e	3267	//@}
bogdanm	82:6473597d706e	3268
bogdanm	82:6473597d706e	3269	/*
bogdanm	82:6473597d706e	3270	* Constants & macros for individual ENET_GALR bitfields
bogdanm	82:6473597d706e	3271	*/
bogdanm	82:6473597d706e	3272
bogdanm	82:6473597d706e	3273	/*!
bogdanm	82:6473597d706e	3274	* @name Register ENET_GALR, field GADDR2[31:0] (RW)
bogdanm	82:6473597d706e	3275	*
bogdanm	82:6473597d706e	3276	* Contains the lower 32 bits of the 64-bit hash table used in the address
bogdanm	82:6473597d706e	3277	* recognition process for receive frames with a multicast address. Bit 31 of GADDR2
bogdanm	82:6473597d706e	3278	* contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
bogdanm	82:6473597d706e	3279	*/
bogdanm	82:6473597d706e	3280	//@{
bogdanm	82:6473597d706e	3281	#define BP_ENET_GALR_GADDR2 (0U) //!< Bit position for ENET_GALR_GADDR2.
bogdanm	82:6473597d706e	3282	#define BM_ENET_GALR_GADDR2 (0xFFFFFFFFU) //!< Bit mask for ENET_GALR_GADDR2.
bogdanm	82:6473597d706e	3283	#define BS_ENET_GALR_GADDR2 (32U) //!< Bit field size in bits for ENET_GALR_GADDR2.
bogdanm	82:6473597d706e	3284
bogdanm	82:6473597d706e	3285	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3286	//! @brief Read current value of the ENET_GALR_GADDR2 field.
bogdanm	82:6473597d706e	3287	#define BR_ENET_GALR_GADDR2(x) (HW_ENET_GALR(x).U)
bogdanm	82:6473597d706e	3288	#endif
bogdanm	82:6473597d706e	3289
bogdanm	82:6473597d706e	3290	//! @brief Format value for bitfield ENET_GALR_GADDR2.
bogdanm	82:6473597d706e	3291	#define BF_ENET_GALR_GADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_GALR_GADDR2), uint32_t) & BM_ENET_GALR_GADDR2)
bogdanm	82:6473597d706e	3292
bogdanm	82:6473597d706e	3293	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3294	//! @brief Set the GADDR2 field to a new value.
bogdanm	82:6473597d706e	3295	#define BW_ENET_GALR_GADDR2(x, v) (HW_ENET_GALR_WR(x, v))
bogdanm	82:6473597d706e	3296	#endif
bogdanm	82:6473597d706e	3297	//@}
bogdanm	82:6473597d706e	3298
bogdanm	82:6473597d706e	3299	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3300	// HW_ENET_TFWR - Transmit FIFO Watermark Register
bogdanm	82:6473597d706e	3301	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3302
bogdanm	82:6473597d706e	3303	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3304	/*!
bogdanm	82:6473597d706e	3305	* @brief HW_ENET_TFWR - Transmit FIFO Watermark Register (RW)
bogdanm	82:6473597d706e	3306	*
bogdanm	82:6473597d706e	3307	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3308	*
bogdanm	82:6473597d706e	3309	* If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
bogdanm	82:6473597d706e	3310	* in the transmit FIFO before transmission of a frame can begin. This allows you
bogdanm	82:6473597d706e	3311	* to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
bogdanm	82:6473597d706e	3312	* latency (TFWR = 11) due to contention for the system bus. Setting the
bogdanm	82:6473597d706e	3313	* watermark to a high value minimizes the risk of transmit FIFO underrun due to
bogdanm	82:6473597d706e	3314	* contention for the system bus. The byte counts associated with the TFWR field may need
bogdanm	82:6473597d706e	3315	* to be modified to match a given system requirement. For example, worst case
bogdanm	82:6473597d706e	3316	* bus access latency by the transmit data DMA channel. When the FIFO level
bogdanm	82:6473597d706e	3317	* reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
bogdanm	82:6473597d706e	3318	* transmit control logic starts frame transmission even before the end-of-frame is
bogdanm	82:6473597d706e	3319	* available in the FIFO (cut-through operation). If a complete frame has a size
bogdanm	82:6473597d706e	3320	* smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
bogdanm	82:6473597d706e	3321	* to the line. To enable store and forward on the Transmit path, set STR_FWD to
bogdanm	82:6473597d706e	3322	* '1'. In this case, the MAC starts to transmit data only when a complete frame
bogdanm	82:6473597d706e	3323	* is stored in the Transmit FIFO.
bogdanm	82:6473597d706e	3324	*/
bogdanm	82:6473597d706e	3325	typedef union _hw_enet_tfwr
bogdanm	82:6473597d706e	3326	{
bogdanm	82:6473597d706e	3327	uint32_t U;
bogdanm	82:6473597d706e	3328	struct _hw_enet_tfwr_bitfields
bogdanm	82:6473597d706e	3329	{
bogdanm	82:6473597d706e	3330	uint32_t TFWR : 6; //!< [5:0] Transmit FIFO Write
bogdanm	82:6473597d706e	3331	uint32_t RESERVED0 : 2; //!< [7:6]
bogdanm	82:6473597d706e	3332	uint32_t STRFWD : 1; //!< [8] Store And Forward Enable
bogdanm	82:6473597d706e	3333	uint32_t RESERVED1 : 23; //!< [31:9]
bogdanm	82:6473597d706e	3334	} B;
bogdanm	82:6473597d706e	3335	} hw_enet_tfwr_t;
bogdanm	82:6473597d706e	3336	#endif
bogdanm	82:6473597d706e	3337
bogdanm	82:6473597d706e	3338	/*!
bogdanm	82:6473597d706e	3339	* @name Constants and macros for entire ENET_TFWR register
bogdanm	82:6473597d706e	3340	*/
bogdanm	82:6473597d706e	3341	//@{
bogdanm	82:6473597d706e	3342	#define HW_ENET_TFWR_ADDR(x) (REGS_ENET_BASE(x) + 0x144U)
bogdanm	82:6473597d706e	3343
bogdanm	82:6473597d706e	3344	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3345	#define HW_ENET_TFWR(x) ((__IO hw_enet_tfwr_t ) HW_ENET_TFWR_ADDR(x))
bogdanm	82:6473597d706e	3346	#define HW_ENET_TFWR_RD(x) (HW_ENET_TFWR(x).U)
bogdanm	82:6473597d706e	3347	#define HW_ENET_TFWR_WR(x, v) (HW_ENET_TFWR(x).U = (v))
bogdanm	82:6473597d706e	3348	#define HW_ENET_TFWR_SET(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) \| (v)))
bogdanm	82:6473597d706e	3349	#define HW_ENET_TFWR_CLR(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3350	#define HW_ENET_TFWR_TOG(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3351	#endif
bogdanm	82:6473597d706e	3352	//@}
bogdanm	82:6473597d706e	3353
bogdanm	82:6473597d706e	3354	/*
bogdanm	82:6473597d706e	3355	* Constants & macros for individual ENET_TFWR bitfields
bogdanm	82:6473597d706e	3356	*/
bogdanm	82:6473597d706e	3357
bogdanm	82:6473597d706e	3358	/*!
bogdanm	82:6473597d706e	3359	* @name Register ENET_TFWR, field TFWR[5:0] (RW)
bogdanm	82:6473597d706e	3360	*
bogdanm	82:6473597d706e	3361	* If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
bogdanm	82:6473597d706e	3362	* steps of 64 bytes, written to the transmit FIFO before transmission of a frame
bogdanm	82:6473597d706e	3363	* begins. If a frame with less than the threshold is written, it is still sent
bogdanm	82:6473597d706e	3364	* independently of this threshold setting. The threshold is relevant only if the
bogdanm	82:6473597d706e	3365	* frame is larger than the threshold given. This chip may not support the maximum
bogdanm	82:6473597d706e	3366	* number of bytes written shown below. See the chip-specific information for the
bogdanm	82:6473597d706e	3367	* ENET module for this value.
bogdanm	82:6473597d706e	3368	*
bogdanm	82:6473597d706e	3369	* Values:
bogdanm	82:6473597d706e	3370	* - 000000 - 64 bytes written.
bogdanm	82:6473597d706e	3371	* - 000001 - 64 bytes written.
bogdanm	82:6473597d706e	3372	* - 000010 - 128 bytes written.
bogdanm	82:6473597d706e	3373	* - 000011 - 192 bytes written.
bogdanm	82:6473597d706e	3374	* - 111110 - 3968 bytes written.
bogdanm	82:6473597d706e	3375	* - 111111 - 4032 bytes written.
bogdanm	82:6473597d706e	3376	*/
bogdanm	82:6473597d706e	3377	//@{
bogdanm	82:6473597d706e	3378	#define BP_ENET_TFWR_TFWR (0U) //!< Bit position for ENET_TFWR_TFWR.
bogdanm	82:6473597d706e	3379	#define BM_ENET_TFWR_TFWR (0x0000003FU) //!< Bit mask for ENET_TFWR_TFWR.
bogdanm	82:6473597d706e	3380	#define BS_ENET_TFWR_TFWR (6U) //!< Bit field size in bits for ENET_TFWR_TFWR.
bogdanm	82:6473597d706e	3381
bogdanm	82:6473597d706e	3382	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3383	//! @brief Read current value of the ENET_TFWR_TFWR field.
bogdanm	82:6473597d706e	3384	#define BR_ENET_TFWR_TFWR(x) (HW_ENET_TFWR(x).B.TFWR)
bogdanm	82:6473597d706e	3385	#endif
bogdanm	82:6473597d706e	3386
bogdanm	82:6473597d706e	3387	//! @brief Format value for bitfield ENET_TFWR_TFWR.
bogdanm	82:6473597d706e	3388	#define BF_ENET_TFWR_TFWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TFWR_TFWR), uint32_t) & BM_ENET_TFWR_TFWR)
bogdanm	82:6473597d706e	3389
bogdanm	82:6473597d706e	3390	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3391	//! @brief Set the TFWR field to a new value.
bogdanm	82:6473597d706e	3392	#define BW_ENET_TFWR_TFWR(x, v) (HW_ENET_TFWR_WR(x, (HW_ENET_TFWR_RD(x) & ~BM_ENET_TFWR_TFWR) \| BF_ENET_TFWR_TFWR(v)))
bogdanm	82:6473597d706e	3393	#endif
bogdanm	82:6473597d706e	3394	//@}
bogdanm	82:6473597d706e	3395
bogdanm	82:6473597d706e	3396	/*!
bogdanm	82:6473597d706e	3397	* @name Register ENET_TFWR, field STRFWD[8] (RW)
bogdanm	82:6473597d706e	3398	*
bogdanm	82:6473597d706e	3399	* Values:
bogdanm	82:6473597d706e	3400	* - 0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
bogdanm	82:6473597d706e	3401	* - 1 - Enabled.
bogdanm	82:6473597d706e	3402	*/
bogdanm	82:6473597d706e	3403	//@{
bogdanm	82:6473597d706e	3404	#define BP_ENET_TFWR_STRFWD (8U) //!< Bit position for ENET_TFWR_STRFWD.
bogdanm	82:6473597d706e	3405	#define BM_ENET_TFWR_STRFWD (0x00000100U) //!< Bit mask for ENET_TFWR_STRFWD.
bogdanm	82:6473597d706e	3406	#define BS_ENET_TFWR_STRFWD (1U) //!< Bit field size in bits for ENET_TFWR_STRFWD.
bogdanm	82:6473597d706e	3407
bogdanm	82:6473597d706e	3408	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3409	//! @brief Read current value of the ENET_TFWR_STRFWD field.
bogdanm	82:6473597d706e	3410	#define BR_ENET_TFWR_STRFWD(x) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD))
bogdanm	82:6473597d706e	3411	#endif
bogdanm	82:6473597d706e	3412
bogdanm	82:6473597d706e	3413	//! @brief Format value for bitfield ENET_TFWR_STRFWD.
bogdanm	82:6473597d706e	3414	#define BF_ENET_TFWR_STRFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TFWR_STRFWD), uint32_t) & BM_ENET_TFWR_STRFWD)
bogdanm	82:6473597d706e	3415
bogdanm	82:6473597d706e	3416	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3417	//! @brief Set the STRFWD field to a new value.
bogdanm	82:6473597d706e	3418	#define BW_ENET_TFWR_STRFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD) = (v))
bogdanm	82:6473597d706e	3419	#endif
bogdanm	82:6473597d706e	3420	//@}
bogdanm	82:6473597d706e	3421
bogdanm	82:6473597d706e	3422	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3423	// HW_ENET_RDSR - Receive Descriptor Ring Start Register
bogdanm	82:6473597d706e	3424	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3425
bogdanm	82:6473597d706e	3426	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3427	/*!
bogdanm	82:6473597d706e	3428	* @brief HW_ENET_RDSR - Receive Descriptor Ring Start Register (RW)
bogdanm	82:6473597d706e	3429	*
bogdanm	82:6473597d706e	3430	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3431	*
bogdanm	82:6473597d706e	3432	* RDSR points to the beginning of the circular receive buffer descriptor queue
bogdanm	82:6473597d706e	3433	* in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
bogdanm	82:6473597d706e	3434	* zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
bogdanm	82:6473597d706e	3435	* by 16. This register must be initialized prior to operation
bogdanm	82:6473597d706e	3436	*/
bogdanm	82:6473597d706e	3437	typedef union _hw_enet_rdsr
bogdanm	82:6473597d706e	3438	{
bogdanm	82:6473597d706e	3439	uint32_t U;
bogdanm	82:6473597d706e	3440	struct _hw_enet_rdsr_bitfields
bogdanm	82:6473597d706e	3441	{
bogdanm	82:6473597d706e	3442	uint32_t RESERVED0 : 3; //!< [2:0]
bogdanm	82:6473597d706e	3443	uint32_t R_DES_START : 29; //!< [31:3]
bogdanm	82:6473597d706e	3444	} B;
bogdanm	82:6473597d706e	3445	} hw_enet_rdsr_t;
bogdanm	82:6473597d706e	3446	#endif
bogdanm	82:6473597d706e	3447
bogdanm	82:6473597d706e	3448	/*!
bogdanm	82:6473597d706e	3449	* @name Constants and macros for entire ENET_RDSR register
bogdanm	82:6473597d706e	3450	*/
bogdanm	82:6473597d706e	3451	//@{
bogdanm	82:6473597d706e	3452	#define HW_ENET_RDSR_ADDR(x) (REGS_ENET_BASE(x) + 0x180U)
bogdanm	82:6473597d706e	3453
bogdanm	82:6473597d706e	3454	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3455	#define HW_ENET_RDSR(x) ((__IO hw_enet_rdsr_t ) HW_ENET_RDSR_ADDR(x))
bogdanm	82:6473597d706e	3456	#define HW_ENET_RDSR_RD(x) (HW_ENET_RDSR(x).U)
bogdanm	82:6473597d706e	3457	#define HW_ENET_RDSR_WR(x, v) (HW_ENET_RDSR(x).U = (v))
bogdanm	82:6473597d706e	3458	#define HW_ENET_RDSR_SET(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) \| (v)))
bogdanm	82:6473597d706e	3459	#define HW_ENET_RDSR_CLR(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3460	#define HW_ENET_RDSR_TOG(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3461	#endif
bogdanm	82:6473597d706e	3462	//@}
bogdanm	82:6473597d706e	3463
bogdanm	82:6473597d706e	3464	/*
bogdanm	82:6473597d706e	3465	* Constants & macros for individual ENET_RDSR bitfields
bogdanm	82:6473597d706e	3466	*/
bogdanm	82:6473597d706e	3467
bogdanm	82:6473597d706e	3468	/*!
bogdanm	82:6473597d706e	3469	* @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
bogdanm	82:6473597d706e	3470	*
bogdanm	82:6473597d706e	3471	* Pointer to the beginning of the receive buffer descriptor queue.
bogdanm	82:6473597d706e	3472	*/
bogdanm	82:6473597d706e	3473	//@{
bogdanm	82:6473597d706e	3474	#define BP_ENET_RDSR_R_DES_START (3U) //!< Bit position for ENET_RDSR_R_DES_START.
bogdanm	82:6473597d706e	3475	#define BM_ENET_RDSR_R_DES_START (0xFFFFFFF8U) //!< Bit mask for ENET_RDSR_R_DES_START.
bogdanm	82:6473597d706e	3476	#define BS_ENET_RDSR_R_DES_START (29U) //!< Bit field size in bits for ENET_RDSR_R_DES_START.
bogdanm	82:6473597d706e	3477
bogdanm	82:6473597d706e	3478	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3479	//! @brief Read current value of the ENET_RDSR_R_DES_START field.
bogdanm	82:6473597d706e	3480	#define BR_ENET_RDSR_R_DES_START(x) (HW_ENET_RDSR(x).B.R_DES_START)
bogdanm	82:6473597d706e	3481	#endif
bogdanm	82:6473597d706e	3482
bogdanm	82:6473597d706e	3483	//! @brief Format value for bitfield ENET_RDSR_R_DES_START.
bogdanm	82:6473597d706e	3484	#define BF_ENET_RDSR_R_DES_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RDSR_R_DES_START), uint32_t) & BM_ENET_RDSR_R_DES_START)
bogdanm	82:6473597d706e	3485
bogdanm	82:6473597d706e	3486	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3487	//! @brief Set the R_DES_START field to a new value.
bogdanm	82:6473597d706e	3488	#define BW_ENET_RDSR_R_DES_START(x, v) (HW_ENET_RDSR_WR(x, (HW_ENET_RDSR_RD(x) & ~BM_ENET_RDSR_R_DES_START) \| BF_ENET_RDSR_R_DES_START(v)))
bogdanm	82:6473597d706e	3489	#endif
bogdanm	82:6473597d706e	3490	//@}
bogdanm	82:6473597d706e	3491
bogdanm	82:6473597d706e	3492	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3493	// HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
bogdanm	82:6473597d706e	3494	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3495
bogdanm	82:6473597d706e	3496	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3497	/*!
bogdanm	82:6473597d706e	3498	* @brief HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
bogdanm	82:6473597d706e	3499	*
bogdanm	82:6473597d706e	3500	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3501	*
bogdanm	82:6473597d706e	3502	* TDSR provides a pointer to the beginning of the circular transmit buffer
bogdanm	82:6473597d706e	3503	* descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
bogdanm	82:6473597d706e	3504	* must be zero); however, it is recommended to be 128-bit aligned, that is,
bogdanm	82:6473597d706e	3505	* evenly divisible by 16. This register must be initialized prior to operation.
bogdanm	82:6473597d706e	3506	*/
bogdanm	82:6473597d706e	3507	typedef union _hw_enet_tdsr
bogdanm	82:6473597d706e	3508	{
bogdanm	82:6473597d706e	3509	uint32_t U;
bogdanm	82:6473597d706e	3510	struct _hw_enet_tdsr_bitfields
bogdanm	82:6473597d706e	3511	{
bogdanm	82:6473597d706e	3512	uint32_t RESERVED0 : 3; //!< [2:0]
bogdanm	82:6473597d706e	3513	uint32_t X_DES_START : 29; //!< [31:3]
bogdanm	82:6473597d706e	3514	} B;
bogdanm	82:6473597d706e	3515	} hw_enet_tdsr_t;
bogdanm	82:6473597d706e	3516	#endif
bogdanm	82:6473597d706e	3517
bogdanm	82:6473597d706e	3518	/*!
bogdanm	82:6473597d706e	3519	* @name Constants and macros for entire ENET_TDSR register
bogdanm	82:6473597d706e	3520	*/
bogdanm	82:6473597d706e	3521	//@{
bogdanm	82:6473597d706e	3522	#define HW_ENET_TDSR_ADDR(x) (REGS_ENET_BASE(x) + 0x184U)
bogdanm	82:6473597d706e	3523
bogdanm	82:6473597d706e	3524	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3525	#define HW_ENET_TDSR(x) ((__IO hw_enet_tdsr_t ) HW_ENET_TDSR_ADDR(x))
bogdanm	82:6473597d706e	3526	#define HW_ENET_TDSR_RD(x) (HW_ENET_TDSR(x).U)
bogdanm	82:6473597d706e	3527	#define HW_ENET_TDSR_WR(x, v) (HW_ENET_TDSR(x).U = (v))
bogdanm	82:6473597d706e	3528	#define HW_ENET_TDSR_SET(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) \| (v)))
bogdanm	82:6473597d706e	3529	#define HW_ENET_TDSR_CLR(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3530	#define HW_ENET_TDSR_TOG(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3531	#endif
bogdanm	82:6473597d706e	3532	//@}
bogdanm	82:6473597d706e	3533
bogdanm	82:6473597d706e	3534	/*
bogdanm	82:6473597d706e	3535	* Constants & macros for individual ENET_TDSR bitfields
bogdanm	82:6473597d706e	3536	*/
bogdanm	82:6473597d706e	3537
bogdanm	82:6473597d706e	3538	/*!
bogdanm	82:6473597d706e	3539	* @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
bogdanm	82:6473597d706e	3540	*
bogdanm	82:6473597d706e	3541	* Pointer to the beginning of the transmit buffer descriptor queue.
bogdanm	82:6473597d706e	3542	*/
bogdanm	82:6473597d706e	3543	//@{
bogdanm	82:6473597d706e	3544	#define BP_ENET_TDSR_X_DES_START (3U) //!< Bit position for ENET_TDSR_X_DES_START.
bogdanm	82:6473597d706e	3545	#define BM_ENET_TDSR_X_DES_START (0xFFFFFFF8U) //!< Bit mask for ENET_TDSR_X_DES_START.
bogdanm	82:6473597d706e	3546	#define BS_ENET_TDSR_X_DES_START (29U) //!< Bit field size in bits for ENET_TDSR_X_DES_START.
bogdanm	82:6473597d706e	3547
bogdanm	82:6473597d706e	3548	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3549	//! @brief Read current value of the ENET_TDSR_X_DES_START field.
bogdanm	82:6473597d706e	3550	#define BR_ENET_TDSR_X_DES_START(x) (HW_ENET_TDSR(x).B.X_DES_START)
bogdanm	82:6473597d706e	3551	#endif
bogdanm	82:6473597d706e	3552
bogdanm	82:6473597d706e	3553	//! @brief Format value for bitfield ENET_TDSR_X_DES_START.
bogdanm	82:6473597d706e	3554	#define BF_ENET_TDSR_X_DES_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TDSR_X_DES_START), uint32_t) & BM_ENET_TDSR_X_DES_START)
bogdanm	82:6473597d706e	3555
bogdanm	82:6473597d706e	3556	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3557	//! @brief Set the X_DES_START field to a new value.
bogdanm	82:6473597d706e	3558	#define BW_ENET_TDSR_X_DES_START(x, v) (HW_ENET_TDSR_WR(x, (HW_ENET_TDSR_RD(x) & ~BM_ENET_TDSR_X_DES_START) \| BF_ENET_TDSR_X_DES_START(v)))
bogdanm	82:6473597d706e	3559	#endif
bogdanm	82:6473597d706e	3560	//@}
bogdanm	82:6473597d706e	3561
bogdanm	82:6473597d706e	3562	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3563	// HW_ENET_MRBR - Maximum Receive Buffer Size Register
bogdanm	82:6473597d706e	3564	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3565
bogdanm	82:6473597d706e	3566	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3567	/*!
bogdanm	82:6473597d706e	3568	* @brief HW_ENET_MRBR - Maximum Receive Buffer Size Register (RW)
bogdanm	82:6473597d706e	3569	*
bogdanm	82:6473597d706e	3570	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3571	*
bogdanm	82:6473597d706e	3572	* The MRBR is a user-programmable register that dictates the maximum size of
bogdanm	82:6473597d706e	3573	* all receive buffers. This value should take into consideration that the receive
bogdanm	82:6473597d706e	3574	* CRC is always written into the last receive buffer. To allow one maximum size
bogdanm	82:6473597d706e	3575	* frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
bogdanm	82:6473597d706e	3576	* the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
bogdanm	82:6473597d706e	3577	* set to zero by the device. To minimize bus usage (descriptor fetches), set
bogdanm	82:6473597d706e	3578	* MRBR greater than or equal to 256 bytes. This register must be initialized
bogdanm	82:6473597d706e	3579	* before operation.
bogdanm	82:6473597d706e	3580	*/
bogdanm	82:6473597d706e	3581	typedef union _hw_enet_mrbr
bogdanm	82:6473597d706e	3582	{
bogdanm	82:6473597d706e	3583	uint32_t U;
bogdanm	82:6473597d706e	3584	struct _hw_enet_mrbr_bitfields
bogdanm	82:6473597d706e	3585	{
bogdanm	82:6473597d706e	3586	uint32_t RESERVED0 : 4; //!< [3:0]
bogdanm	82:6473597d706e	3587	uint32_t R_BUF_SIZE : 10; //!< [13:4]
bogdanm	82:6473597d706e	3588	uint32_t RESERVED1 : 18; //!< [31:14]
bogdanm	82:6473597d706e	3589	} B;
bogdanm	82:6473597d706e	3590	} hw_enet_mrbr_t;
bogdanm	82:6473597d706e	3591	#endif
bogdanm	82:6473597d706e	3592
bogdanm	82:6473597d706e	3593	/*!
bogdanm	82:6473597d706e	3594	* @name Constants and macros for entire ENET_MRBR register
bogdanm	82:6473597d706e	3595	*/
bogdanm	82:6473597d706e	3596	//@{
bogdanm	82:6473597d706e	3597	#define HW_ENET_MRBR_ADDR(x) (REGS_ENET_BASE(x) + 0x188U)
bogdanm	82:6473597d706e	3598
bogdanm	82:6473597d706e	3599	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3600	#define HW_ENET_MRBR(x) ((__IO hw_enet_mrbr_t ) HW_ENET_MRBR_ADDR(x))
bogdanm	82:6473597d706e	3601	#define HW_ENET_MRBR_RD(x) (HW_ENET_MRBR(x).U)
bogdanm	82:6473597d706e	3602	#define HW_ENET_MRBR_WR(x, v) (HW_ENET_MRBR(x).U = (v))
bogdanm	82:6473597d706e	3603	#define HW_ENET_MRBR_SET(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) \| (v)))
bogdanm	82:6473597d706e	3604	#define HW_ENET_MRBR_CLR(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3605	#define HW_ENET_MRBR_TOG(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3606	#endif
bogdanm	82:6473597d706e	3607	//@}
bogdanm	82:6473597d706e	3608
bogdanm	82:6473597d706e	3609	/*
bogdanm	82:6473597d706e	3610	* Constants & macros for individual ENET_MRBR bitfields
bogdanm	82:6473597d706e	3611	*/
bogdanm	82:6473597d706e	3612
bogdanm	82:6473597d706e	3613	/*!
bogdanm	82:6473597d706e	3614	* @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
bogdanm	82:6473597d706e	3615	*
bogdanm	82:6473597d706e	3616	* Receive buffer size in bytes.
bogdanm	82:6473597d706e	3617	*/
bogdanm	82:6473597d706e	3618	//@{
bogdanm	82:6473597d706e	3619	#define BP_ENET_MRBR_R_BUF_SIZE (4U) //!< Bit position for ENET_MRBR_R_BUF_SIZE.
bogdanm	82:6473597d706e	3620	#define BM_ENET_MRBR_R_BUF_SIZE (0x00003FF0U) //!< Bit mask for ENET_MRBR_R_BUF_SIZE.
bogdanm	82:6473597d706e	3621	#define BS_ENET_MRBR_R_BUF_SIZE (10U) //!< Bit field size in bits for ENET_MRBR_R_BUF_SIZE.
bogdanm	82:6473597d706e	3622
bogdanm	82:6473597d706e	3623	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3624	//! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field.
bogdanm	82:6473597d706e	3625	#define BR_ENET_MRBR_R_BUF_SIZE(x) (HW_ENET_MRBR(x).B.R_BUF_SIZE)
bogdanm	82:6473597d706e	3626	#endif
bogdanm	82:6473597d706e	3627
bogdanm	82:6473597d706e	3628	//! @brief Format value for bitfield ENET_MRBR_R_BUF_SIZE.
bogdanm	82:6473597d706e	3629	#define BF_ENET_MRBR_R_BUF_SIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MRBR_R_BUF_SIZE), uint32_t) & BM_ENET_MRBR_R_BUF_SIZE)
bogdanm	82:6473597d706e	3630
bogdanm	82:6473597d706e	3631	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3632	//! @brief Set the R_BUF_SIZE field to a new value.
bogdanm	82:6473597d706e	3633	#define BW_ENET_MRBR_R_BUF_SIZE(x, v) (HW_ENET_MRBR_WR(x, (HW_ENET_MRBR_RD(x) & ~BM_ENET_MRBR_R_BUF_SIZE) \| BF_ENET_MRBR_R_BUF_SIZE(v)))
bogdanm	82:6473597d706e	3634	#endif
bogdanm	82:6473597d706e	3635	//@}
bogdanm	82:6473597d706e	3636
bogdanm	82:6473597d706e	3637	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3638	// HW_ENET_RSFL - Receive FIFO Section Full Threshold
bogdanm	82:6473597d706e	3639	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3640
bogdanm	82:6473597d706e	3641	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3642	/*!
bogdanm	82:6473597d706e	3643	* @brief HW_ENET_RSFL - Receive FIFO Section Full Threshold (RW)
bogdanm	82:6473597d706e	3644	*
bogdanm	82:6473597d706e	3645	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3646	*/
bogdanm	82:6473597d706e	3647	typedef union _hw_enet_rsfl
bogdanm	82:6473597d706e	3648	{
bogdanm	82:6473597d706e	3649	uint32_t U;
bogdanm	82:6473597d706e	3650	struct _hw_enet_rsfl_bitfields
bogdanm	82:6473597d706e	3651	{
bogdanm	82:6473597d706e	3652	uint32_t RX_SECTION_FULL : 8; //!< [7:0] Value Of Receive FIFO
bogdanm	82:6473597d706e	3653	//! Section Full Threshold
bogdanm	82:6473597d706e	3654	uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm	82:6473597d706e	3655	} B;
bogdanm	82:6473597d706e	3656	} hw_enet_rsfl_t;
bogdanm	82:6473597d706e	3657	#endif
bogdanm	82:6473597d706e	3658
bogdanm	82:6473597d706e	3659	/*!
bogdanm	82:6473597d706e	3660	* @name Constants and macros for entire ENET_RSFL register
bogdanm	82:6473597d706e	3661	*/
bogdanm	82:6473597d706e	3662	//@{
bogdanm	82:6473597d706e	3663	#define HW_ENET_RSFL_ADDR(x) (REGS_ENET_BASE(x) + 0x190U)
bogdanm	82:6473597d706e	3664
bogdanm	82:6473597d706e	3665	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3666	#define HW_ENET_RSFL(x) ((__IO hw_enet_rsfl_t ) HW_ENET_RSFL_ADDR(x))
bogdanm	82:6473597d706e	3667	#define HW_ENET_RSFL_RD(x) (HW_ENET_RSFL(x).U)
bogdanm	82:6473597d706e	3668	#define HW_ENET_RSFL_WR(x, v) (HW_ENET_RSFL(x).U = (v))
bogdanm	82:6473597d706e	3669	#define HW_ENET_RSFL_SET(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) \| (v)))
bogdanm	82:6473597d706e	3670	#define HW_ENET_RSFL_CLR(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3671	#define HW_ENET_RSFL_TOG(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3672	#endif
bogdanm	82:6473597d706e	3673	//@}
bogdanm	82:6473597d706e	3674
bogdanm	82:6473597d706e	3675	/*
bogdanm	82:6473597d706e	3676	* Constants & macros for individual ENET_RSFL bitfields
bogdanm	82:6473597d706e	3677	*/
bogdanm	82:6473597d706e	3678
bogdanm	82:6473597d706e	3679	/*!
bogdanm	82:6473597d706e	3680	* @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
bogdanm	82:6473597d706e	3681	*
bogdanm	82:6473597d706e	3682	* Value, in 64-bit words, of the receive FIFO section full threshold. Clear
bogdanm	82:6473597d706e	3683	* this field to enable store and forward on the RX FIFO. When programming a value
bogdanm	82:6473597d706e	3684	* greater than 0 (cut-through operation), it must be greater than
bogdanm	82:6473597d706e	3685	* RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
bogdanm	82:6473597d706e	3686	* in the Receive FIFO (cut-through operation).
bogdanm	82:6473597d706e	3687	*/
bogdanm	82:6473597d706e	3688	//@{
bogdanm	82:6473597d706e	3689	#define BP_ENET_RSFL_RX_SECTION_FULL (0U) //!< Bit position for ENET_RSFL_RX_SECTION_FULL.
bogdanm	82:6473597d706e	3690	#define BM_ENET_RSFL_RX_SECTION_FULL (0x000000FFU) //!< Bit mask for ENET_RSFL_RX_SECTION_FULL.
bogdanm	82:6473597d706e	3691	#define BS_ENET_RSFL_RX_SECTION_FULL (8U) //!< Bit field size in bits for ENET_RSFL_RX_SECTION_FULL.
bogdanm	82:6473597d706e	3692
bogdanm	82:6473597d706e	3693	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3694	//! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field.
bogdanm	82:6473597d706e	3695	#define BR_ENET_RSFL_RX_SECTION_FULL(x) (HW_ENET_RSFL(x).B.RX_SECTION_FULL)
bogdanm	82:6473597d706e	3696	#endif
bogdanm	82:6473597d706e	3697
bogdanm	82:6473597d706e	3698	//! @brief Format value for bitfield ENET_RSFL_RX_SECTION_FULL.
bogdanm	82:6473597d706e	3699	#define BF_ENET_RSFL_RX_SECTION_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSFL_RX_SECTION_FULL), uint32_t) & BM_ENET_RSFL_RX_SECTION_FULL)
bogdanm	82:6473597d706e	3700
bogdanm	82:6473597d706e	3701	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3702	//! @brief Set the RX_SECTION_FULL field to a new value.
bogdanm	82:6473597d706e	3703	#define BW_ENET_RSFL_RX_SECTION_FULL(x, v) (HW_ENET_RSFL_WR(x, (HW_ENET_RSFL_RD(x) & ~BM_ENET_RSFL_RX_SECTION_FULL) \| BF_ENET_RSFL_RX_SECTION_FULL(v)))
bogdanm	82:6473597d706e	3704	#endif
bogdanm	82:6473597d706e	3705	//@}
bogdanm	82:6473597d706e	3706
bogdanm	82:6473597d706e	3707	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3708	// HW_ENET_RSEM - Receive FIFO Section Empty Threshold
bogdanm	82:6473597d706e	3709	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3710
bogdanm	82:6473597d706e	3711	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3712	/*!
bogdanm	82:6473597d706e	3713	* @brief HW_ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
bogdanm	82:6473597d706e	3714	*
bogdanm	82:6473597d706e	3715	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3716	*/
bogdanm	82:6473597d706e	3717	typedef union _hw_enet_rsem
bogdanm	82:6473597d706e	3718	{
bogdanm	82:6473597d706e	3719	uint32_t U;
bogdanm	82:6473597d706e	3720	struct _hw_enet_rsem_bitfields
bogdanm	82:6473597d706e	3721	{
bogdanm	82:6473597d706e	3722	uint32_t RX_SECTION_EMPTY : 8; //!< [7:0] Value Of The Receive FIFO
bogdanm	82:6473597d706e	3723	//! Section Empty Threshold
bogdanm	82:6473597d706e	3724	uint32_t RESERVED0 : 8; //!< [15:8]
bogdanm	82:6473597d706e	3725	uint32_t STAT_SECTION_EMPTY : 5; //!< [20:16] RX Status FIFO Section
bogdanm	82:6473597d706e	3726	//! Empty Threshold
bogdanm	82:6473597d706e	3727	uint32_t RESERVED1 : 11; //!< [31:21]
bogdanm	82:6473597d706e	3728	} B;
bogdanm	82:6473597d706e	3729	} hw_enet_rsem_t;
bogdanm	82:6473597d706e	3730	#endif
bogdanm	82:6473597d706e	3731
bogdanm	82:6473597d706e	3732	/*!
bogdanm	82:6473597d706e	3733	* @name Constants and macros for entire ENET_RSEM register
bogdanm	82:6473597d706e	3734	*/
bogdanm	82:6473597d706e	3735	//@{
bogdanm	82:6473597d706e	3736	#define HW_ENET_RSEM_ADDR(x) (REGS_ENET_BASE(x) + 0x194U)
bogdanm	82:6473597d706e	3737
bogdanm	82:6473597d706e	3738	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3739	#define HW_ENET_RSEM(x) ((__IO hw_enet_rsem_t ) HW_ENET_RSEM_ADDR(x))
bogdanm	82:6473597d706e	3740	#define HW_ENET_RSEM_RD(x) (HW_ENET_RSEM(x).U)
bogdanm	82:6473597d706e	3741	#define HW_ENET_RSEM_WR(x, v) (HW_ENET_RSEM(x).U = (v))
bogdanm	82:6473597d706e	3742	#define HW_ENET_RSEM_SET(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) \| (v)))
bogdanm	82:6473597d706e	3743	#define HW_ENET_RSEM_CLR(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3744	#define HW_ENET_RSEM_TOG(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3745	#endif
bogdanm	82:6473597d706e	3746	//@}
bogdanm	82:6473597d706e	3747
bogdanm	82:6473597d706e	3748	/*
bogdanm	82:6473597d706e	3749	* Constants & macros for individual ENET_RSEM bitfields
bogdanm	82:6473597d706e	3750	*/
bogdanm	82:6473597d706e	3751
bogdanm	82:6473597d706e	3752	/*!
bogdanm	82:6473597d706e	3753	* @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
bogdanm	82:6473597d706e	3754	*
bogdanm	82:6473597d706e	3755	* Value, in 64-bit words, of the receive FIFO section empty threshold. When the
bogdanm	82:6473597d706e	3756	* FIFO has reached this level, a pause frame will be issued. A value of 0
bogdanm	82:6473597d706e	3757	* disables automatic pause frame generation. When the FIFO level goes below the value
bogdanm	82:6473597d706e	3758	* programmed in this field, an XON pause frame is issued to indicate the FIFO
bogdanm	82:6473597d706e	3759	* congestion is cleared to the remote Ethernet client. The section-empty
bogdanm	82:6473597d706e	3760	* threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
bogdanm	82:6473597d706e	3761	*/
bogdanm	82:6473597d706e	3762	//@{
bogdanm	82:6473597d706e	3763	#define BP_ENET_RSEM_RX_SECTION_EMPTY (0U) //!< Bit position for ENET_RSEM_RX_SECTION_EMPTY.
bogdanm	82:6473597d706e	3764	#define BM_ENET_RSEM_RX_SECTION_EMPTY (0x000000FFU) //!< Bit mask for ENET_RSEM_RX_SECTION_EMPTY.
bogdanm	82:6473597d706e	3765	#define BS_ENET_RSEM_RX_SECTION_EMPTY (8U) //!< Bit field size in bits for ENET_RSEM_RX_SECTION_EMPTY.
bogdanm	82:6473597d706e	3766
bogdanm	82:6473597d706e	3767	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3768	//! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field.
bogdanm	82:6473597d706e	3769	#define BR_ENET_RSEM_RX_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.RX_SECTION_EMPTY)
bogdanm	82:6473597d706e	3770	#endif
bogdanm	82:6473597d706e	3771
bogdanm	82:6473597d706e	3772	//! @brief Format value for bitfield ENET_RSEM_RX_SECTION_EMPTY.
bogdanm	82:6473597d706e	3773	#define BF_ENET_RSEM_RX_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSEM_RX_SECTION_EMPTY), uint32_t) & BM_ENET_RSEM_RX_SECTION_EMPTY)
bogdanm	82:6473597d706e	3774
bogdanm	82:6473597d706e	3775	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3776	//! @brief Set the RX_SECTION_EMPTY field to a new value.
bogdanm	82:6473597d706e	3777	#define BW_ENET_RSEM_RX_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_RX_SECTION_EMPTY) \| BF_ENET_RSEM_RX_SECTION_EMPTY(v)))
bogdanm	82:6473597d706e	3778	#endif
bogdanm	82:6473597d706e	3779	//@}
bogdanm	82:6473597d706e	3780
bogdanm	82:6473597d706e	3781	/*!
bogdanm	82:6473597d706e	3782	* @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
bogdanm	82:6473597d706e	3783	*
bogdanm	82:6473597d706e	3784	* Defines number of frames in the receive FIFO, independent of its size, that
bogdanm	82:6473597d706e	3785	* can be accepted. If the limit is reached, reception will continue normally,
bogdanm	82:6473597d706e	3786	* however a pause frame will be triggered to indicate a possible congestion to the
bogdanm	82:6473597d706e	3787	* remote device to avoid FIFO overflow. A value of 0 disables automatic pause
bogdanm	82:6473597d706e	3788	* frame generation
bogdanm	82:6473597d706e	3789	*/
bogdanm	82:6473597d706e	3790	//@{
bogdanm	82:6473597d706e	3791	#define BP_ENET_RSEM_STAT_SECTION_EMPTY (16U) //!< Bit position for ENET_RSEM_STAT_SECTION_EMPTY.
bogdanm	82:6473597d706e	3792	#define BM_ENET_RSEM_STAT_SECTION_EMPTY (0x001F0000U) //!< Bit mask for ENET_RSEM_STAT_SECTION_EMPTY.
bogdanm	82:6473597d706e	3793	#define BS_ENET_RSEM_STAT_SECTION_EMPTY (5U) //!< Bit field size in bits for ENET_RSEM_STAT_SECTION_EMPTY.
bogdanm	82:6473597d706e	3794
bogdanm	82:6473597d706e	3795	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3796	//! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field.
bogdanm	82:6473597d706e	3797	#define BR_ENET_RSEM_STAT_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.STAT_SECTION_EMPTY)
bogdanm	82:6473597d706e	3798	#endif
bogdanm	82:6473597d706e	3799
bogdanm	82:6473597d706e	3800	//! @brief Format value for bitfield ENET_RSEM_STAT_SECTION_EMPTY.
bogdanm	82:6473597d706e	3801	#define BF_ENET_RSEM_STAT_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSEM_STAT_SECTION_EMPTY), uint32_t) & BM_ENET_RSEM_STAT_SECTION_EMPTY)
bogdanm	82:6473597d706e	3802
bogdanm	82:6473597d706e	3803	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3804	//! @brief Set the STAT_SECTION_EMPTY field to a new value.
bogdanm	82:6473597d706e	3805	#define BW_ENET_RSEM_STAT_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_STAT_SECTION_EMPTY) \| BF_ENET_RSEM_STAT_SECTION_EMPTY(v)))
bogdanm	82:6473597d706e	3806	#endif
bogdanm	82:6473597d706e	3807	//@}
bogdanm	82:6473597d706e	3808
bogdanm	82:6473597d706e	3809	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3810	// HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
bogdanm	82:6473597d706e	3811	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3812
bogdanm	82:6473597d706e	3813	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3814	/*!
bogdanm	82:6473597d706e	3815	* @brief HW_ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
bogdanm	82:6473597d706e	3816	*
bogdanm	82:6473597d706e	3817	* Reset value: 0x00000004U
bogdanm	82:6473597d706e	3818	*/
bogdanm	82:6473597d706e	3819	typedef union _hw_enet_raem
bogdanm	82:6473597d706e	3820	{
bogdanm	82:6473597d706e	3821	uint32_t U;
bogdanm	82:6473597d706e	3822	struct _hw_enet_raem_bitfields
bogdanm	82:6473597d706e	3823	{
bogdanm	82:6473597d706e	3824	uint32_t RX_ALMOST_EMPTY : 8; //!< [7:0] Value Of The Receive FIFO
bogdanm	82:6473597d706e	3825	//! Almost Empty Threshold
bogdanm	82:6473597d706e	3826	uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm	82:6473597d706e	3827	} B;
bogdanm	82:6473597d706e	3828	} hw_enet_raem_t;
bogdanm	82:6473597d706e	3829	#endif
bogdanm	82:6473597d706e	3830
bogdanm	82:6473597d706e	3831	/*!
bogdanm	82:6473597d706e	3832	* @name Constants and macros for entire ENET_RAEM register
bogdanm	82:6473597d706e	3833	*/
bogdanm	82:6473597d706e	3834	//@{
bogdanm	82:6473597d706e	3835	#define HW_ENET_RAEM_ADDR(x) (REGS_ENET_BASE(x) + 0x198U)
bogdanm	82:6473597d706e	3836
bogdanm	82:6473597d706e	3837	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3838	#define HW_ENET_RAEM(x) ((__IO hw_enet_raem_t ) HW_ENET_RAEM_ADDR(x))
bogdanm	82:6473597d706e	3839	#define HW_ENET_RAEM_RD(x) (HW_ENET_RAEM(x).U)
bogdanm	82:6473597d706e	3840	#define HW_ENET_RAEM_WR(x, v) (HW_ENET_RAEM(x).U = (v))
bogdanm	82:6473597d706e	3841	#define HW_ENET_RAEM_SET(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) \| (v)))
bogdanm	82:6473597d706e	3842	#define HW_ENET_RAEM_CLR(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3843	#define HW_ENET_RAEM_TOG(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3844	#endif
bogdanm	82:6473597d706e	3845	//@}
bogdanm	82:6473597d706e	3846
bogdanm	82:6473597d706e	3847	/*
bogdanm	82:6473597d706e	3848	* Constants & macros for individual ENET_RAEM bitfields
bogdanm	82:6473597d706e	3849	*/
bogdanm	82:6473597d706e	3850
bogdanm	82:6473597d706e	3851	/*!
bogdanm	82:6473597d706e	3852	* @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
bogdanm	82:6473597d706e	3853	*
bogdanm	82:6473597d706e	3854	* Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
bogdanm	82:6473597d706e	3855	* FIFO level reaches the value programmed in this field and the end-of-frame has
bogdanm	82:6473597d706e	3856	* not been received for the frame yet, the core receive read control stops FIFO
bogdanm	82:6473597d706e	3857	* read (and subsequently stops transferring data to the MAC client
bogdanm	82:6473597d706e	3858	* application). It continues to deliver the frame, if again more data than the threshold or
bogdanm	82:6473597d706e	3859	* the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
bogdanm	82:6473597d706e	3860	*/
bogdanm	82:6473597d706e	3861	//@{
bogdanm	82:6473597d706e	3862	#define BP_ENET_RAEM_RX_ALMOST_EMPTY (0U) //!< Bit position for ENET_RAEM_RX_ALMOST_EMPTY.
bogdanm	82:6473597d706e	3863	#define BM_ENET_RAEM_RX_ALMOST_EMPTY (0x000000FFU) //!< Bit mask for ENET_RAEM_RX_ALMOST_EMPTY.
bogdanm	82:6473597d706e	3864	#define BS_ENET_RAEM_RX_ALMOST_EMPTY (8U) //!< Bit field size in bits for ENET_RAEM_RX_ALMOST_EMPTY.
bogdanm	82:6473597d706e	3865
bogdanm	82:6473597d706e	3866	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3867	//! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field.
bogdanm	82:6473597d706e	3868	#define BR_ENET_RAEM_RX_ALMOST_EMPTY(x) (HW_ENET_RAEM(x).B.RX_ALMOST_EMPTY)
bogdanm	82:6473597d706e	3869	#endif
bogdanm	82:6473597d706e	3870
bogdanm	82:6473597d706e	3871	//! @brief Format value for bitfield ENET_RAEM_RX_ALMOST_EMPTY.
bogdanm	82:6473597d706e	3872	#define BF_ENET_RAEM_RX_ALMOST_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RAEM_RX_ALMOST_EMPTY), uint32_t) & BM_ENET_RAEM_RX_ALMOST_EMPTY)
bogdanm	82:6473597d706e	3873
bogdanm	82:6473597d706e	3874	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3875	//! @brief Set the RX_ALMOST_EMPTY field to a new value.
bogdanm	82:6473597d706e	3876	#define BW_ENET_RAEM_RX_ALMOST_EMPTY(x, v) (HW_ENET_RAEM_WR(x, (HW_ENET_RAEM_RD(x) & ~BM_ENET_RAEM_RX_ALMOST_EMPTY) \| BF_ENET_RAEM_RX_ALMOST_EMPTY(v)))
bogdanm	82:6473597d706e	3877	#endif
bogdanm	82:6473597d706e	3878	//@}
bogdanm	82:6473597d706e	3879
bogdanm	82:6473597d706e	3880	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3881	// HW_ENET_RAFL - Receive FIFO Almost Full Threshold
bogdanm	82:6473597d706e	3882	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3883
bogdanm	82:6473597d706e	3884	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3885	/*!
bogdanm	82:6473597d706e	3886	* @brief HW_ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
bogdanm	82:6473597d706e	3887	*
bogdanm	82:6473597d706e	3888	* Reset value: 0x00000004U
bogdanm	82:6473597d706e	3889	*/
bogdanm	82:6473597d706e	3890	typedef union _hw_enet_rafl
bogdanm	82:6473597d706e	3891	{
bogdanm	82:6473597d706e	3892	uint32_t U;
bogdanm	82:6473597d706e	3893	struct _hw_enet_rafl_bitfields
bogdanm	82:6473597d706e	3894	{
bogdanm	82:6473597d706e	3895	uint32_t RX_ALMOST_FULL : 8; //!< [7:0] Value Of The Receive FIFO
bogdanm	82:6473597d706e	3896	//! Almost Full Threshold
bogdanm	82:6473597d706e	3897	uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm	82:6473597d706e	3898	} B;
bogdanm	82:6473597d706e	3899	} hw_enet_rafl_t;
bogdanm	82:6473597d706e	3900	#endif
bogdanm	82:6473597d706e	3901
bogdanm	82:6473597d706e	3902	/*!
bogdanm	82:6473597d706e	3903	* @name Constants and macros for entire ENET_RAFL register
bogdanm	82:6473597d706e	3904	*/
bogdanm	82:6473597d706e	3905	//@{
bogdanm	82:6473597d706e	3906	#define HW_ENET_RAFL_ADDR(x) (REGS_ENET_BASE(x) + 0x19CU)
bogdanm	82:6473597d706e	3907
bogdanm	82:6473597d706e	3908	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3909	#define HW_ENET_RAFL(x) ((__IO hw_enet_rafl_t ) HW_ENET_RAFL_ADDR(x))
bogdanm	82:6473597d706e	3910	#define HW_ENET_RAFL_RD(x) (HW_ENET_RAFL(x).U)
bogdanm	82:6473597d706e	3911	#define HW_ENET_RAFL_WR(x, v) (HW_ENET_RAFL(x).U = (v))
bogdanm	82:6473597d706e	3912	#define HW_ENET_RAFL_SET(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) \| (v)))
bogdanm	82:6473597d706e	3913	#define HW_ENET_RAFL_CLR(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3914	#define HW_ENET_RAFL_TOG(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3915	#endif
bogdanm	82:6473597d706e	3916	//@}
bogdanm	82:6473597d706e	3917
bogdanm	82:6473597d706e	3918	/*
bogdanm	82:6473597d706e	3919	* Constants & macros for individual ENET_RAFL bitfields
bogdanm	82:6473597d706e	3920	*/
bogdanm	82:6473597d706e	3921
bogdanm	82:6473597d706e	3922	/*!
bogdanm	82:6473597d706e	3923	* @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
bogdanm	82:6473597d706e	3924	*
bogdanm	82:6473597d706e	3925	* Value, in 64-bit words, of the receive FIFO almost full threshold. When the
bogdanm	82:6473597d706e	3926	* FIFO level comes close to the maximum, so that there is no more space for at
bogdanm	82:6473597d706e	3927	* least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
bogdanm	82:6473597d706e	3928	* truncates the received frame to avoid FIFO overflow. The corresponding error
bogdanm	82:6473597d706e	3929	* status will be set when the frame is delivered to the application. A minimum
bogdanm	82:6473597d706e	3930	* value of 4 should be set.
bogdanm	82:6473597d706e	3931	*/
bogdanm	82:6473597d706e	3932	//@{
bogdanm	82:6473597d706e	3933	#define BP_ENET_RAFL_RX_ALMOST_FULL (0U) //!< Bit position for ENET_RAFL_RX_ALMOST_FULL.
bogdanm	82:6473597d706e	3934	#define BM_ENET_RAFL_RX_ALMOST_FULL (0x000000FFU) //!< Bit mask for ENET_RAFL_RX_ALMOST_FULL.
bogdanm	82:6473597d706e	3935	#define BS_ENET_RAFL_RX_ALMOST_FULL (8U) //!< Bit field size in bits for ENET_RAFL_RX_ALMOST_FULL.
bogdanm	82:6473597d706e	3936
bogdanm	82:6473597d706e	3937	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3938	//! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field.
bogdanm	82:6473597d706e	3939	#define BR_ENET_RAFL_RX_ALMOST_FULL(x) (HW_ENET_RAFL(x).B.RX_ALMOST_FULL)
bogdanm	82:6473597d706e	3940	#endif
bogdanm	82:6473597d706e	3941
bogdanm	82:6473597d706e	3942	//! @brief Format value for bitfield ENET_RAFL_RX_ALMOST_FULL.
bogdanm	82:6473597d706e	3943	#define BF_ENET_RAFL_RX_ALMOST_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RAFL_RX_ALMOST_FULL), uint32_t) & BM_ENET_RAFL_RX_ALMOST_FULL)
bogdanm	82:6473597d706e	3944
bogdanm	82:6473597d706e	3945	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3946	//! @brief Set the RX_ALMOST_FULL field to a new value.
bogdanm	82:6473597d706e	3947	#define BW_ENET_RAFL_RX_ALMOST_FULL(x, v) (HW_ENET_RAFL_WR(x, (HW_ENET_RAFL_RD(x) & ~BM_ENET_RAFL_RX_ALMOST_FULL) \| BF_ENET_RAFL_RX_ALMOST_FULL(v)))
bogdanm	82:6473597d706e	3948	#endif
bogdanm	82:6473597d706e	3949	//@}
bogdanm	82:6473597d706e	3950
bogdanm	82:6473597d706e	3951	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3952	// HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
bogdanm	82:6473597d706e	3953	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3954
bogdanm	82:6473597d706e	3955	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3956	/*!
bogdanm	82:6473597d706e	3957	* @brief HW_ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
bogdanm	82:6473597d706e	3958	*
bogdanm	82:6473597d706e	3959	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3960	*/
bogdanm	82:6473597d706e	3961	typedef union _hw_enet_tsem
bogdanm	82:6473597d706e	3962	{
bogdanm	82:6473597d706e	3963	uint32_t U;
bogdanm	82:6473597d706e	3964	struct _hw_enet_tsem_bitfields
bogdanm	82:6473597d706e	3965	{
bogdanm	82:6473597d706e	3966	uint32_t TX_SECTION_EMPTY : 8; //!< [7:0] Value Of The Transmit FIFO
bogdanm	82:6473597d706e	3967	//! Section Empty Threshold
bogdanm	82:6473597d706e	3968	uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm	82:6473597d706e	3969	} B;
bogdanm	82:6473597d706e	3970	} hw_enet_tsem_t;
bogdanm	82:6473597d706e	3971	#endif
bogdanm	82:6473597d706e	3972
bogdanm	82:6473597d706e	3973	/*!
bogdanm	82:6473597d706e	3974	* @name Constants and macros for entire ENET_TSEM register
bogdanm	82:6473597d706e	3975	*/
bogdanm	82:6473597d706e	3976	//@{
bogdanm	82:6473597d706e	3977	#define HW_ENET_TSEM_ADDR(x) (REGS_ENET_BASE(x) + 0x1A0U)
bogdanm	82:6473597d706e	3978
bogdanm	82:6473597d706e	3979	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3980	#define HW_ENET_TSEM(x) ((__IO hw_enet_tsem_t ) HW_ENET_TSEM_ADDR(x))
bogdanm	82:6473597d706e	3981	#define HW_ENET_TSEM_RD(x) (HW_ENET_TSEM(x).U)
bogdanm	82:6473597d706e	3982	#define HW_ENET_TSEM_WR(x, v) (HW_ENET_TSEM(x).U = (v))
bogdanm	82:6473597d706e	3983	#define HW_ENET_TSEM_SET(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) \| (v)))
bogdanm	82:6473597d706e	3984	#define HW_ENET_TSEM_CLR(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3985	#define HW_ENET_TSEM_TOG(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3986	#endif
bogdanm	82:6473597d706e	3987	//@}
bogdanm	82:6473597d706e	3988
bogdanm	82:6473597d706e	3989	/*
bogdanm	82:6473597d706e	3990	* Constants & macros for individual ENET_TSEM bitfields
bogdanm	82:6473597d706e	3991	*/
bogdanm	82:6473597d706e	3992
bogdanm	82:6473597d706e	3993	/*!
bogdanm	82:6473597d706e	3994	* @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
bogdanm	82:6473597d706e	3995	*
bogdanm	82:6473597d706e	3996	* Value, in 64-bit words, of the transmit FIFO section empty threshold. See
bogdanm	82:6473597d706e	3997	* Transmit FIFOFour programmable thresholds are available which control the core
bogdanm	82:6473597d706e	3998	* operation. for more information.
bogdanm	82:6473597d706e	3999	*/
bogdanm	82:6473597d706e	4000	//@{
bogdanm	82:6473597d706e	4001	#define BP_ENET_TSEM_TX_SECTION_EMPTY (0U) //!< Bit position for ENET_TSEM_TX_SECTION_EMPTY.
bogdanm	82:6473597d706e	4002	#define BM_ENET_TSEM_TX_SECTION_EMPTY (0x000000FFU) //!< Bit mask for ENET_TSEM_TX_SECTION_EMPTY.
bogdanm	82:6473597d706e	4003	#define BS_ENET_TSEM_TX_SECTION_EMPTY (8U) //!< Bit field size in bits for ENET_TSEM_TX_SECTION_EMPTY.
bogdanm	82:6473597d706e	4004
bogdanm	82:6473597d706e	4005	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4006	//! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field.
bogdanm	82:6473597d706e	4007	#define BR_ENET_TSEM_TX_SECTION_EMPTY(x) (HW_ENET_TSEM(x).B.TX_SECTION_EMPTY)
bogdanm	82:6473597d706e	4008	#endif
bogdanm	82:6473597d706e	4009
bogdanm	82:6473597d706e	4010	//! @brief Format value for bitfield ENET_TSEM_TX_SECTION_EMPTY.
bogdanm	82:6473597d706e	4011	#define BF_ENET_TSEM_TX_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TSEM_TX_SECTION_EMPTY), uint32_t) & BM_ENET_TSEM_TX_SECTION_EMPTY)
bogdanm	82:6473597d706e	4012
bogdanm	82:6473597d706e	4013	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4014	//! @brief Set the TX_SECTION_EMPTY field to a new value.
bogdanm	82:6473597d706e	4015	#define BW_ENET_TSEM_TX_SECTION_EMPTY(x, v) (HW_ENET_TSEM_WR(x, (HW_ENET_TSEM_RD(x) & ~BM_ENET_TSEM_TX_SECTION_EMPTY) \| BF_ENET_TSEM_TX_SECTION_EMPTY(v)))
bogdanm	82:6473597d706e	4016	#endif
bogdanm	82:6473597d706e	4017	//@}
bogdanm	82:6473597d706e	4018
bogdanm	82:6473597d706e	4019	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4020	// HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
bogdanm	82:6473597d706e	4021	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4022
bogdanm	82:6473597d706e	4023	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4024	/*!
bogdanm	82:6473597d706e	4025	* @brief HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
bogdanm	82:6473597d706e	4026	*
bogdanm	82:6473597d706e	4027	* Reset value: 0x00000004U
bogdanm	82:6473597d706e	4028	*/
bogdanm	82:6473597d706e	4029	typedef union _hw_enet_taem
bogdanm	82:6473597d706e	4030	{
bogdanm	82:6473597d706e	4031	uint32_t U;
bogdanm	82:6473597d706e	4032	struct _hw_enet_taem_bitfields
bogdanm	82:6473597d706e	4033	{
bogdanm	82:6473597d706e	4034	uint32_t TX_ALMOST_EMPTY : 8; //!< [7:0] Value of Transmit FIFO
bogdanm	82:6473597d706e	4035	//! Almost Empty Threshold
bogdanm	82:6473597d706e	4036	uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm	82:6473597d706e	4037	} B;
bogdanm	82:6473597d706e	4038	} hw_enet_taem_t;
bogdanm	82:6473597d706e	4039	#endif
bogdanm	82:6473597d706e	4040
bogdanm	82:6473597d706e	4041	/*!
bogdanm	82:6473597d706e	4042	* @name Constants and macros for entire ENET_TAEM register
bogdanm	82:6473597d706e	4043	*/
bogdanm	82:6473597d706e	4044	//@{
bogdanm	82:6473597d706e	4045	#define HW_ENET_TAEM_ADDR(x) (REGS_ENET_BASE(x) + 0x1A4U)
bogdanm	82:6473597d706e	4046
bogdanm	82:6473597d706e	4047	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4048	#define HW_ENET_TAEM(x) ((__IO hw_enet_taem_t ) HW_ENET_TAEM_ADDR(x))
bogdanm	82:6473597d706e	4049	#define HW_ENET_TAEM_RD(x) (HW_ENET_TAEM(x).U)
bogdanm	82:6473597d706e	4050	#define HW_ENET_TAEM_WR(x, v) (HW_ENET_TAEM(x).U = (v))
bogdanm	82:6473597d706e	4051	#define HW_ENET_TAEM_SET(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) \| (v)))
bogdanm	82:6473597d706e	4052	#define HW_ENET_TAEM_CLR(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) & ~(v)))
bogdanm	82:6473597d706e	4053	#define HW_ENET_TAEM_TOG(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) ^ (v)))
bogdanm	82:6473597d706e	4054	#endif
bogdanm	82:6473597d706e	4055	//@}
bogdanm	82:6473597d706e	4056
bogdanm	82:6473597d706e	4057	/*
bogdanm	82:6473597d706e	4058	* Constants & macros for individual ENET_TAEM bitfields
bogdanm	82:6473597d706e	4059	*/
bogdanm	82:6473597d706e	4060
bogdanm	82:6473597d706e	4061	/*!
bogdanm	82:6473597d706e	4062	* @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
bogdanm	82:6473597d706e	4063	*
bogdanm	82:6473597d706e	4064	* Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
bogdanm	82:6473597d706e	4065	* FIFO level reaches the value programmed in this field, and no end-of-frame is
bogdanm	82:6473597d706e	4066	* available for the frame, the MAC transmit logic, to avoid FIFO underflow,
bogdanm	82:6473597d706e	4067	* stops reading the FIFO and transmits a frame with an MII error indication. See
bogdanm	82:6473597d706e	4068	* Transmit FIFOFour programmable thresholds are available which control the core
bogdanm	82:6473597d706e	4069	* operation. for more information. A minimum value of 4 should be set.
bogdanm	82:6473597d706e	4070	*/
bogdanm	82:6473597d706e	4071	//@{
bogdanm	82:6473597d706e	4072	#define BP_ENET_TAEM_TX_ALMOST_EMPTY (0U) //!< Bit position for ENET_TAEM_TX_ALMOST_EMPTY.
bogdanm	82:6473597d706e	4073	#define BM_ENET_TAEM_TX_ALMOST_EMPTY (0x000000FFU) //!< Bit mask for ENET_TAEM_TX_ALMOST_EMPTY.
bogdanm	82:6473597d706e	4074	#define BS_ENET_TAEM_TX_ALMOST_EMPTY (8U) //!< Bit field size in bits for ENET_TAEM_TX_ALMOST_EMPTY.
bogdanm	82:6473597d706e	4075
bogdanm	82:6473597d706e	4076	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4077	//! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field.
bogdanm	82:6473597d706e	4078	#define BR_ENET_TAEM_TX_ALMOST_EMPTY(x) (HW_ENET_TAEM(x).B.TX_ALMOST_EMPTY)
bogdanm	82:6473597d706e	4079	#endif
bogdanm	82:6473597d706e	4080
bogdanm	82:6473597d706e	4081	//! @brief Format value for bitfield ENET_TAEM_TX_ALMOST_EMPTY.
bogdanm	82:6473597d706e	4082	#define BF_ENET_TAEM_TX_ALMOST_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TAEM_TX_ALMOST_EMPTY), uint32_t) & BM_ENET_TAEM_TX_ALMOST_EMPTY)
bogdanm	82:6473597d706e	4083
bogdanm	82:6473597d706e	4084	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4085	//! @brief Set the TX_ALMOST_EMPTY field to a new value.
bogdanm	82:6473597d706e	4086	#define BW_ENET_TAEM_TX_ALMOST_EMPTY(x, v) (HW_ENET_TAEM_WR(x, (HW_ENET_TAEM_RD(x) & ~BM_ENET_TAEM_TX_ALMOST_EMPTY) \| BF_ENET_TAEM_TX_ALMOST_EMPTY(v)))
bogdanm	82:6473597d706e	4087	#endif
bogdanm	82:6473597d706e	4088	//@}
bogdanm	82:6473597d706e	4089
bogdanm	82:6473597d706e	4090	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4091	// HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
bogdanm	82:6473597d706e	4092	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4093
bogdanm	82:6473597d706e	4094	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4095	/*!
bogdanm	82:6473597d706e	4096	* @brief HW_ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
bogdanm	82:6473597d706e	4097	*
bogdanm	82:6473597d706e	4098	* Reset value: 0x00000008U
bogdanm	82:6473597d706e	4099	*/
bogdanm	82:6473597d706e	4100	typedef union _hw_enet_tafl
bogdanm	82:6473597d706e	4101	{
bogdanm	82:6473597d706e	4102	uint32_t U;
bogdanm	82:6473597d706e	4103	struct _hw_enet_tafl_bitfields
bogdanm	82:6473597d706e	4104	{
bogdanm	82:6473597d706e	4105	uint32_t TX_ALMOST_FULL : 8; //!< [7:0] Value Of The Transmit FIFO
bogdanm	82:6473597d706e	4106	//! Almost Full Threshold
bogdanm	82:6473597d706e	4107	uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm	82:6473597d706e	4108	} B;
bogdanm	82:6473597d706e	4109	} hw_enet_tafl_t;
bogdanm	82:6473597d706e	4110	#endif
bogdanm	82:6473597d706e	4111
bogdanm	82:6473597d706e	4112	/*!
bogdanm	82:6473597d706e	4113	* @name Constants and macros for entire ENET_TAFL register
bogdanm	82:6473597d706e	4114	*/
bogdanm	82:6473597d706e	4115	//@{
bogdanm	82:6473597d706e	4116	#define HW_ENET_TAFL_ADDR(x) (REGS_ENET_BASE(x) + 0x1A8U)
bogdanm	82:6473597d706e	4117
bogdanm	82:6473597d706e	4118	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4119	#define HW_ENET_TAFL(x) ((__IO hw_enet_tafl_t ) HW_ENET_TAFL_ADDR(x))
bogdanm	82:6473597d706e	4120	#define HW_ENET_TAFL_RD(x) (HW_ENET_TAFL(x).U)
bogdanm	82:6473597d706e	4121	#define HW_ENET_TAFL_WR(x, v) (HW_ENET_TAFL(x).U = (v))
bogdanm	82:6473597d706e	4122	#define HW_ENET_TAFL_SET(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) \| (v)))
bogdanm	82:6473597d706e	4123	#define HW_ENET_TAFL_CLR(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) & ~(v)))
bogdanm	82:6473597d706e	4124	#define HW_ENET_TAFL_TOG(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) ^ (v)))
bogdanm	82:6473597d706e	4125	#endif
bogdanm	82:6473597d706e	4126	//@}
bogdanm	82:6473597d706e	4127
bogdanm	82:6473597d706e	4128	/*
bogdanm	82:6473597d706e	4129	* Constants & macros for individual ENET_TAFL bitfields
bogdanm	82:6473597d706e	4130	*/
bogdanm	82:6473597d706e	4131
bogdanm	82:6473597d706e	4132	/*!
bogdanm	82:6473597d706e	4133	* @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
bogdanm	82:6473597d706e	4134	*
bogdanm	82:6473597d706e	4135	* Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
bogdanm	82:6473597d706e	4136	* value of six is required . A recommended value of at least 8 should be set
bogdanm	82:6473597d706e	4137	* allowing a latency of two clock cycles to the application. If more latency is
bogdanm	82:6473597d706e	4138	* required the value can be increased as necessary (latency = TAFL - 5). When the
bogdanm	82:6473597d706e	4139	* FIFO level comes close to the maximum, so that there is no more space for at
bogdanm	82:6473597d706e	4140	* least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
bogdanm	82:6473597d706e	4141	* application does not react on this signal, the FIFO write control logic, to
bogdanm	82:6473597d706e	4142	* avoid FIFO overflow, truncates the current frame and sets the error status. As a
bogdanm	82:6473597d706e	4143	* result, the frame will be transmitted with an GMII/MII error indication. See
bogdanm	82:6473597d706e	4144	* Transmit FIFOFour programmable thresholds are available which control the core
bogdanm	82:6473597d706e	4145	* operation. for more information. A FIFO overflow is a fatal error and requires
bogdanm	82:6473597d706e	4146	* a global reset on the transmit datapath or at least deassertion of ETHEREN.
bogdanm	82:6473597d706e	4147	*/
bogdanm	82:6473597d706e	4148	//@{
bogdanm	82:6473597d706e	4149	#define BP_ENET_TAFL_TX_ALMOST_FULL (0U) //!< Bit position for ENET_TAFL_TX_ALMOST_FULL.
bogdanm	82:6473597d706e	4150	#define BM_ENET_TAFL_TX_ALMOST_FULL (0x000000FFU) //!< Bit mask for ENET_TAFL_TX_ALMOST_FULL.
bogdanm	82:6473597d706e	4151	#define BS_ENET_TAFL_TX_ALMOST_FULL (8U) //!< Bit field size in bits for ENET_TAFL_TX_ALMOST_FULL.
bogdanm	82:6473597d706e	4152
bogdanm	82:6473597d706e	4153	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4154	//! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field.
bogdanm	82:6473597d706e	4155	#define BR_ENET_TAFL_TX_ALMOST_FULL(x) (HW_ENET_TAFL(x).B.TX_ALMOST_FULL)
bogdanm	82:6473597d706e	4156	#endif
bogdanm	82:6473597d706e	4157
bogdanm	82:6473597d706e	4158	//! @brief Format value for bitfield ENET_TAFL_TX_ALMOST_FULL.
bogdanm	82:6473597d706e	4159	#define BF_ENET_TAFL_TX_ALMOST_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TAFL_TX_ALMOST_FULL), uint32_t) & BM_ENET_TAFL_TX_ALMOST_FULL)
bogdanm	82:6473597d706e	4160
bogdanm	82:6473597d706e	4161	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4162	//! @brief Set the TX_ALMOST_FULL field to a new value.
bogdanm	82:6473597d706e	4163	#define BW_ENET_TAFL_TX_ALMOST_FULL(x, v) (HW_ENET_TAFL_WR(x, (HW_ENET_TAFL_RD(x) & ~BM_ENET_TAFL_TX_ALMOST_FULL) \| BF_ENET_TAFL_TX_ALMOST_FULL(v)))
bogdanm	82:6473597d706e	4164	#endif
bogdanm	82:6473597d706e	4165	//@}
bogdanm	82:6473597d706e	4166
bogdanm	82:6473597d706e	4167	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4168	// HW_ENET_TIPG - Transmit Inter-Packet Gap
bogdanm	82:6473597d706e	4169	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4170
bogdanm	82:6473597d706e	4171	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4172	/*!
bogdanm	82:6473597d706e	4173	* @brief HW_ENET_TIPG - Transmit Inter-Packet Gap (RW)
bogdanm	82:6473597d706e	4174	*
bogdanm	82:6473597d706e	4175	* Reset value: 0x0000000CU
bogdanm	82:6473597d706e	4176	*/
bogdanm	82:6473597d706e	4177	typedef union _hw_enet_tipg
bogdanm	82:6473597d706e	4178	{
bogdanm	82:6473597d706e	4179	uint32_t U;
bogdanm	82:6473597d706e	4180	struct _hw_enet_tipg_bitfields
bogdanm	82:6473597d706e	4181	{
bogdanm	82:6473597d706e	4182	uint32_t IPG : 5; //!< [4:0] Transmit Inter-Packet Gap
bogdanm	82:6473597d706e	4183	uint32_t RESERVED0 : 27; //!< [31:5]
bogdanm	82:6473597d706e	4184	} B;
bogdanm	82:6473597d706e	4185	} hw_enet_tipg_t;
bogdanm	82:6473597d706e	4186	#endif
bogdanm	82:6473597d706e	4187
bogdanm	82:6473597d706e	4188	/*!
bogdanm	82:6473597d706e	4189	* @name Constants and macros for entire ENET_TIPG register
bogdanm	82:6473597d706e	4190	*/
bogdanm	82:6473597d706e	4191	//@{
bogdanm	82:6473597d706e	4192	#define HW_ENET_TIPG_ADDR(x) (REGS_ENET_BASE(x) + 0x1ACU)
bogdanm	82:6473597d706e	4193
bogdanm	82:6473597d706e	4194	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4195	#define HW_ENET_TIPG(x) ((__IO hw_enet_tipg_t ) HW_ENET_TIPG_ADDR(x))
bogdanm	82:6473597d706e	4196	#define HW_ENET_TIPG_RD(x) (HW_ENET_TIPG(x).U)
bogdanm	82:6473597d706e	4197	#define HW_ENET_TIPG_WR(x, v) (HW_ENET_TIPG(x).U = (v))
bogdanm	82:6473597d706e	4198	#define HW_ENET_TIPG_SET(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) \| (v)))
bogdanm	82:6473597d706e	4199	#define HW_ENET_TIPG_CLR(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) & ~(v)))
bogdanm	82:6473597d706e	4200	#define HW_ENET_TIPG_TOG(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) ^ (v)))
bogdanm	82:6473597d706e	4201	#endif
bogdanm	82:6473597d706e	4202	//@}
bogdanm	82:6473597d706e	4203
bogdanm	82:6473597d706e	4204	/*
bogdanm	82:6473597d706e	4205	* Constants & macros for individual ENET_TIPG bitfields
bogdanm	82:6473597d706e	4206	*/
bogdanm	82:6473597d706e	4207
bogdanm	82:6473597d706e	4208	/*!
bogdanm	82:6473597d706e	4209	* @name Register ENET_TIPG, field IPG[4:0] (RW)
bogdanm	82:6473597d706e	4210	*
bogdanm	82:6473597d706e	4211	* Indicates the IPG, in bytes, between transmitted frames. Valid values range
bogdanm	82:6473597d706e	4212	* from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
bogdanm	82:6473597d706e	4213	* 27, the IPG is 27.
bogdanm	82:6473597d706e	4214	*/
bogdanm	82:6473597d706e	4215	//@{
bogdanm	82:6473597d706e	4216	#define BP_ENET_TIPG_IPG (0U) //!< Bit position for ENET_TIPG_IPG.
bogdanm	82:6473597d706e	4217	#define BM_ENET_TIPG_IPG (0x0000001FU) //!< Bit mask for ENET_TIPG_IPG.
bogdanm	82:6473597d706e	4218	#define BS_ENET_TIPG_IPG (5U) //!< Bit field size in bits for ENET_TIPG_IPG.
bogdanm	82:6473597d706e	4219
bogdanm	82:6473597d706e	4220	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4221	//! @brief Read current value of the ENET_TIPG_IPG field.
bogdanm	82:6473597d706e	4222	#define BR_ENET_TIPG_IPG(x) (HW_ENET_TIPG(x).B.IPG)
bogdanm	82:6473597d706e	4223	#endif
bogdanm	82:6473597d706e	4224
bogdanm	82:6473597d706e	4225	//! @brief Format value for bitfield ENET_TIPG_IPG.
bogdanm	82:6473597d706e	4226	#define BF_ENET_TIPG_IPG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TIPG_IPG), uint32_t) & BM_ENET_TIPG_IPG)
bogdanm	82:6473597d706e	4227
bogdanm	82:6473597d706e	4228	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4229	//! @brief Set the IPG field to a new value.
bogdanm	82:6473597d706e	4230	#define BW_ENET_TIPG_IPG(x, v) (HW_ENET_TIPG_WR(x, (HW_ENET_TIPG_RD(x) & ~BM_ENET_TIPG_IPG) \| BF_ENET_TIPG_IPG(v)))
bogdanm	82:6473597d706e	4231	#endif
bogdanm	82:6473597d706e	4232	//@}
bogdanm	82:6473597d706e	4233
bogdanm	82:6473597d706e	4234	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4235	// HW_ENET_FTRL - Frame Truncation Length
bogdanm	82:6473597d706e	4236	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4237
bogdanm	82:6473597d706e	4238	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4239	/*!
bogdanm	82:6473597d706e	4240	* @brief HW_ENET_FTRL - Frame Truncation Length (RW)
bogdanm	82:6473597d706e	4241	*
bogdanm	82:6473597d706e	4242	* Reset value: 0x000007FFU
bogdanm	82:6473597d706e	4243	*/
bogdanm	82:6473597d706e	4244	typedef union _hw_enet_ftrl
bogdanm	82:6473597d706e	4245	{
bogdanm	82:6473597d706e	4246	uint32_t U;
bogdanm	82:6473597d706e	4247	struct _hw_enet_ftrl_bitfields
bogdanm	82:6473597d706e	4248	{
bogdanm	82:6473597d706e	4249	uint32_t TRUNC_FL : 14; //!< [13:0] Frame Truncation Length
bogdanm	82:6473597d706e	4250	uint32_t RESERVED0 : 18; //!< [31:14]
bogdanm	82:6473597d706e	4251	} B;
bogdanm	82:6473597d706e	4252	} hw_enet_ftrl_t;
bogdanm	82:6473597d706e	4253	#endif
bogdanm	82:6473597d706e	4254
bogdanm	82:6473597d706e	4255	/*!
bogdanm	82:6473597d706e	4256	* @name Constants and macros for entire ENET_FTRL register
bogdanm	82:6473597d706e	4257	*/
bogdanm	82:6473597d706e	4258	//@{
bogdanm	82:6473597d706e	4259	#define HW_ENET_FTRL_ADDR(x) (REGS_ENET_BASE(x) + 0x1B0U)
bogdanm	82:6473597d706e	4260
bogdanm	82:6473597d706e	4261	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4262	#define HW_ENET_FTRL(x) ((__IO hw_enet_ftrl_t ) HW_ENET_FTRL_ADDR(x))
bogdanm	82:6473597d706e	4263	#define HW_ENET_FTRL_RD(x) (HW_ENET_FTRL(x).U)
bogdanm	82:6473597d706e	4264	#define HW_ENET_FTRL_WR(x, v) (HW_ENET_FTRL(x).U = (v))
bogdanm	82:6473597d706e	4265	#define HW_ENET_FTRL_SET(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) \| (v)))
bogdanm	82:6473597d706e	4266	#define HW_ENET_FTRL_CLR(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) & ~(v)))
bogdanm	82:6473597d706e	4267	#define HW_ENET_FTRL_TOG(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) ^ (v)))
bogdanm	82:6473597d706e	4268	#endif
bogdanm	82:6473597d706e	4269	//@}
bogdanm	82:6473597d706e	4270
bogdanm	82:6473597d706e	4271	/*
bogdanm	82:6473597d706e	4272	* Constants & macros for individual ENET_FTRL bitfields
bogdanm	82:6473597d706e	4273	*/
bogdanm	82:6473597d706e	4274
bogdanm	82:6473597d706e	4275	/*!
bogdanm	82:6473597d706e	4276	* @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
bogdanm	82:6473597d706e	4277	*
bogdanm	82:6473597d706e	4278	* Indicates the value a receive frame is truncated, if it is greater than this
bogdanm	82:6473597d706e	4279	* value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
bogdanm	82:6473597d706e	4280	* TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
bogdanm	82:6473597d706e	4281	* less data, guaranteeing that it never receives more than the set limit.
bogdanm	82:6473597d706e	4282	*/
bogdanm	82:6473597d706e	4283	//@{
bogdanm	82:6473597d706e	4284	#define BP_ENET_FTRL_TRUNC_FL (0U) //!< Bit position for ENET_FTRL_TRUNC_FL.
bogdanm	82:6473597d706e	4285	#define BM_ENET_FTRL_TRUNC_FL (0x00003FFFU) //!< Bit mask for ENET_FTRL_TRUNC_FL.
bogdanm	82:6473597d706e	4286	#define BS_ENET_FTRL_TRUNC_FL (14U) //!< Bit field size in bits for ENET_FTRL_TRUNC_FL.
bogdanm	82:6473597d706e	4287
bogdanm	82:6473597d706e	4288	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4289	//! @brief Read current value of the ENET_FTRL_TRUNC_FL field.
bogdanm	82:6473597d706e	4290	#define BR_ENET_FTRL_TRUNC_FL(x) (HW_ENET_FTRL(x).B.TRUNC_FL)
bogdanm	82:6473597d706e	4291	#endif
bogdanm	82:6473597d706e	4292
bogdanm	82:6473597d706e	4293	//! @brief Format value for bitfield ENET_FTRL_TRUNC_FL.
bogdanm	82:6473597d706e	4294	#define BF_ENET_FTRL_TRUNC_FL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_FTRL_TRUNC_FL), uint32_t) & BM_ENET_FTRL_TRUNC_FL)
bogdanm	82:6473597d706e	4295
bogdanm	82:6473597d706e	4296	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4297	//! @brief Set the TRUNC_FL field to a new value.
bogdanm	82:6473597d706e	4298	#define BW_ENET_FTRL_TRUNC_FL(x, v) (HW_ENET_FTRL_WR(x, (HW_ENET_FTRL_RD(x) & ~BM_ENET_FTRL_TRUNC_FL) \| BF_ENET_FTRL_TRUNC_FL(v)))
bogdanm	82:6473597d706e	4299	#endif
bogdanm	82:6473597d706e	4300	//@}
bogdanm	82:6473597d706e	4301
bogdanm	82:6473597d706e	4302	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4303	// HW_ENET_TACC - Transmit Accelerator Function Configuration
bogdanm	82:6473597d706e	4304	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4305
bogdanm	82:6473597d706e	4306	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4307	/*!
bogdanm	82:6473597d706e	4308	* @brief HW_ENET_TACC - Transmit Accelerator Function Configuration (RW)
bogdanm	82:6473597d706e	4309	*
bogdanm	82:6473597d706e	4310	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4311	*
bogdanm	82:6473597d706e	4312	* TACC controls accelerator actions when sending frames. The register can be
bogdanm	82:6473597d706e	4313	* changed before or after each frame, but it must remain unmodified during frame
bogdanm	82:6473597d706e	4314	* writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
bogdanm	82:6473597d706e	4315	* checksum feature.
bogdanm	82:6473597d706e	4316	*/
bogdanm	82:6473597d706e	4317	typedef union _hw_enet_tacc
bogdanm	82:6473597d706e	4318	{
bogdanm	82:6473597d706e	4319	uint32_t U;
bogdanm	82:6473597d706e	4320	struct _hw_enet_tacc_bitfields
bogdanm	82:6473597d706e	4321	{
bogdanm	82:6473597d706e	4322	uint32_t SHIFT16 : 1; //!< [0] TX FIFO Shift-16
bogdanm	82:6473597d706e	4323	uint32_t RESERVED0 : 2; //!< [2:1]
bogdanm	82:6473597d706e	4324	uint32_t IPCHK : 1; //!< [3]
bogdanm	82:6473597d706e	4325	uint32_t PROCHK : 1; //!< [4]
bogdanm	82:6473597d706e	4326	uint32_t RESERVED1 : 27; //!< [31:5]
bogdanm	82:6473597d706e	4327	} B;
bogdanm	82:6473597d706e	4328	} hw_enet_tacc_t;
bogdanm	82:6473597d706e	4329	#endif
bogdanm	82:6473597d706e	4330
bogdanm	82:6473597d706e	4331	/*!
bogdanm	82:6473597d706e	4332	* @name Constants and macros for entire ENET_TACC register
bogdanm	82:6473597d706e	4333	*/
bogdanm	82:6473597d706e	4334	//@{
bogdanm	82:6473597d706e	4335	#define HW_ENET_TACC_ADDR(x) (REGS_ENET_BASE(x) + 0x1C0U)
bogdanm	82:6473597d706e	4336
bogdanm	82:6473597d706e	4337	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4338	#define HW_ENET_TACC(x) ((__IO hw_enet_tacc_t ) HW_ENET_TACC_ADDR(x))
bogdanm	82:6473597d706e	4339	#define HW_ENET_TACC_RD(x) (HW_ENET_TACC(x).U)
bogdanm	82:6473597d706e	4340	#define HW_ENET_TACC_WR(x, v) (HW_ENET_TACC(x).U = (v))
bogdanm	82:6473597d706e	4341	#define HW_ENET_TACC_SET(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) \| (v)))
bogdanm	82:6473597d706e	4342	#define HW_ENET_TACC_CLR(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) & ~(v)))
bogdanm	82:6473597d706e	4343	#define HW_ENET_TACC_TOG(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) ^ (v)))
bogdanm	82:6473597d706e	4344	#endif
bogdanm	82:6473597d706e	4345	//@}
bogdanm	82:6473597d706e	4346
bogdanm	82:6473597d706e	4347	/*
bogdanm	82:6473597d706e	4348	* Constants & macros for individual ENET_TACC bitfields
bogdanm	82:6473597d706e	4349	*/
bogdanm	82:6473597d706e	4350
bogdanm	82:6473597d706e	4351	/*!
bogdanm	82:6473597d706e	4352	* @name Register ENET_TACC, field SHIFT16[0] (RW)
bogdanm	82:6473597d706e	4353	*
bogdanm	82:6473597d706e	4354	* Values:
bogdanm	82:6473597d706e	4355	* - 0 - Disabled.
bogdanm	82:6473597d706e	4356	* - 1 - Indicates to the transmit data FIFO that the written frames contain two
bogdanm	82:6473597d706e	4357	* additional octets before the frame data. This means the actual frame
bogdanm	82:6473597d706e	4358	* begins at bit 16 of the first word written into the FIFO. This function allows
bogdanm	82:6473597d706e	4359	* putting the frame payload on a 32-bit boundary in memory, as the 14-byte
bogdanm	82:6473597d706e	4360	* Ethernet header is extended to a 16-byte header.
bogdanm	82:6473597d706e	4361	*/
bogdanm	82:6473597d706e	4362	//@{
bogdanm	82:6473597d706e	4363	#define BP_ENET_TACC_SHIFT16 (0U) //!< Bit position for ENET_TACC_SHIFT16.
bogdanm	82:6473597d706e	4364	#define BM_ENET_TACC_SHIFT16 (0x00000001U) //!< Bit mask for ENET_TACC_SHIFT16.
bogdanm	82:6473597d706e	4365	#define BS_ENET_TACC_SHIFT16 (1U) //!< Bit field size in bits for ENET_TACC_SHIFT16.
bogdanm	82:6473597d706e	4366
bogdanm	82:6473597d706e	4367	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4368	//! @brief Read current value of the ENET_TACC_SHIFT16 field.
bogdanm	82:6473597d706e	4369	#define BR_ENET_TACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16))
bogdanm	82:6473597d706e	4370	#endif
bogdanm	82:6473597d706e	4371
bogdanm	82:6473597d706e	4372	//! @brief Format value for bitfield ENET_TACC_SHIFT16.
bogdanm	82:6473597d706e	4373	#define BF_ENET_TACC_SHIFT16(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_SHIFT16), uint32_t) & BM_ENET_TACC_SHIFT16)
bogdanm	82:6473597d706e	4374
bogdanm	82:6473597d706e	4375	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4376	//! @brief Set the SHIFT16 field to a new value.
bogdanm	82:6473597d706e	4377	#define BW_ENET_TACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16) = (v))
bogdanm	82:6473597d706e	4378	#endif
bogdanm	82:6473597d706e	4379	//@}
bogdanm	82:6473597d706e	4380
bogdanm	82:6473597d706e	4381	/*!
bogdanm	82:6473597d706e	4382	* @name Register ENET_TACC, field IPCHK[3] (RW)
bogdanm	82:6473597d706e	4383	*
bogdanm	82:6473597d706e	4384	* Enables insertion of IP header checksum.
bogdanm	82:6473597d706e	4385	*
bogdanm	82:6473597d706e	4386	* Values:
bogdanm	82:6473597d706e	4387	* - 0 - Checksum is not inserted.
bogdanm	82:6473597d706e	4388	* - 1 - If an IP frame is transmitted, the checksum is inserted automatically.
bogdanm	82:6473597d706e	4389	* The IP header checksum field must be cleared. If a non-IP frame is
bogdanm	82:6473597d706e	4390	* transmitted the frame is not modified.
bogdanm	82:6473597d706e	4391	*/
bogdanm	82:6473597d706e	4392	//@{
bogdanm	82:6473597d706e	4393	#define BP_ENET_TACC_IPCHK (3U) //!< Bit position for ENET_TACC_IPCHK.
bogdanm	82:6473597d706e	4394	#define BM_ENET_TACC_IPCHK (0x00000008U) //!< Bit mask for ENET_TACC_IPCHK.
bogdanm	82:6473597d706e	4395	#define BS_ENET_TACC_IPCHK (1U) //!< Bit field size in bits for ENET_TACC_IPCHK.
bogdanm	82:6473597d706e	4396
bogdanm	82:6473597d706e	4397	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4398	//! @brief Read current value of the ENET_TACC_IPCHK field.
bogdanm	82:6473597d706e	4399	#define BR_ENET_TACC_IPCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK))
bogdanm	82:6473597d706e	4400	#endif
bogdanm	82:6473597d706e	4401
bogdanm	82:6473597d706e	4402	//! @brief Format value for bitfield ENET_TACC_IPCHK.
bogdanm	82:6473597d706e	4403	#define BF_ENET_TACC_IPCHK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_IPCHK), uint32_t) & BM_ENET_TACC_IPCHK)
bogdanm	82:6473597d706e	4404
bogdanm	82:6473597d706e	4405	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4406	//! @brief Set the IPCHK field to a new value.
bogdanm	82:6473597d706e	4407	#define BW_ENET_TACC_IPCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK) = (v))
bogdanm	82:6473597d706e	4408	#endif
bogdanm	82:6473597d706e	4409	//@}
bogdanm	82:6473597d706e	4410
bogdanm	82:6473597d706e	4411	/*!
bogdanm	82:6473597d706e	4412	* @name Register ENET_TACC, field PROCHK[4] (RW)
bogdanm	82:6473597d706e	4413	*
bogdanm	82:6473597d706e	4414	* Enables insertion of protocol checksum.
bogdanm	82:6473597d706e	4415	*
bogdanm	82:6473597d706e	4416	* Values:
bogdanm	82:6473597d706e	4417	* - 0 - Checksum not inserted.
bogdanm	82:6473597d706e	4418	* - 1 - If an IP frame with a known protocol is transmitted, the checksum is
bogdanm	82:6473597d706e	4419	* inserted automatically into the frame. The checksum field must be cleared.
bogdanm	82:6473597d706e	4420	* The other frames are not modified.
bogdanm	82:6473597d706e	4421	*/
bogdanm	82:6473597d706e	4422	//@{
bogdanm	82:6473597d706e	4423	#define BP_ENET_TACC_PROCHK (4U) //!< Bit position for ENET_TACC_PROCHK.
bogdanm	82:6473597d706e	4424	#define BM_ENET_TACC_PROCHK (0x00000010U) //!< Bit mask for ENET_TACC_PROCHK.
bogdanm	82:6473597d706e	4425	#define BS_ENET_TACC_PROCHK (1U) //!< Bit field size in bits for ENET_TACC_PROCHK.
bogdanm	82:6473597d706e	4426
bogdanm	82:6473597d706e	4427	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4428	//! @brief Read current value of the ENET_TACC_PROCHK field.
bogdanm	82:6473597d706e	4429	#define BR_ENET_TACC_PROCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK))
bogdanm	82:6473597d706e	4430	#endif
bogdanm	82:6473597d706e	4431
bogdanm	82:6473597d706e	4432	//! @brief Format value for bitfield ENET_TACC_PROCHK.
bogdanm	82:6473597d706e	4433	#define BF_ENET_TACC_PROCHK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_PROCHK), uint32_t) & BM_ENET_TACC_PROCHK)
bogdanm	82:6473597d706e	4434
bogdanm	82:6473597d706e	4435	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4436	//! @brief Set the PROCHK field to a new value.
bogdanm	82:6473597d706e	4437	#define BW_ENET_TACC_PROCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK) = (v))
bogdanm	82:6473597d706e	4438	#endif
bogdanm	82:6473597d706e	4439	//@}
bogdanm	82:6473597d706e	4440
bogdanm	82:6473597d706e	4441	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4442	// HW_ENET_RACC - Receive Accelerator Function Configuration
bogdanm	82:6473597d706e	4443	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4444
bogdanm	82:6473597d706e	4445	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4446	/*!
bogdanm	82:6473597d706e	4447	* @brief HW_ENET_RACC - Receive Accelerator Function Configuration (RW)
bogdanm	82:6473597d706e	4448	*
bogdanm	82:6473597d706e	4449	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4450	*/
bogdanm	82:6473597d706e	4451	typedef union _hw_enet_racc
bogdanm	82:6473597d706e	4452	{
bogdanm	82:6473597d706e	4453	uint32_t U;
bogdanm	82:6473597d706e	4454	struct _hw_enet_racc_bitfields
bogdanm	82:6473597d706e	4455	{
bogdanm	82:6473597d706e	4456	uint32_t PADREM : 1; //!< [0] Enable Padding Removal For Short IP
bogdanm	82:6473597d706e	4457	//! Frames
bogdanm	82:6473597d706e	4458	uint32_t IPDIS : 1; //!< [1] Enable Discard Of Frames With Wrong IPv4
bogdanm	82:6473597d706e	4459	//! Header Checksum
bogdanm	82:6473597d706e	4460	uint32_t PRODIS : 1; //!< [2] Enable Discard Of Frames With Wrong
bogdanm	82:6473597d706e	4461	//! Protocol Checksum
bogdanm	82:6473597d706e	4462	uint32_t RESERVED0 : 3; //!< [5:3]
bogdanm	82:6473597d706e	4463	uint32_t LINEDIS : 1; //!< [6] Enable Discard Of Frames With MAC
bogdanm	82:6473597d706e	4464	//! Layer Errors
bogdanm	82:6473597d706e	4465	uint32_t SHIFT16 : 1; //!< [7] RX FIFO Shift-16
bogdanm	82:6473597d706e	4466	uint32_t RESERVED1 : 24; //!< [31:8]
bogdanm	82:6473597d706e	4467	} B;
bogdanm	82:6473597d706e	4468	} hw_enet_racc_t;
bogdanm	82:6473597d706e	4469	#endif
bogdanm	82:6473597d706e	4470
bogdanm	82:6473597d706e	4471	/*!
bogdanm	82:6473597d706e	4472	* @name Constants and macros for entire ENET_RACC register
bogdanm	82:6473597d706e	4473	*/
bogdanm	82:6473597d706e	4474	//@{
bogdanm	82:6473597d706e	4475	#define HW_ENET_RACC_ADDR(x) (REGS_ENET_BASE(x) + 0x1C4U)
bogdanm	82:6473597d706e	4476
bogdanm	82:6473597d706e	4477	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4478	#define HW_ENET_RACC(x) ((__IO hw_enet_racc_t ) HW_ENET_RACC_ADDR(x))
bogdanm	82:6473597d706e	4479	#define HW_ENET_RACC_RD(x) (HW_ENET_RACC(x).U)
bogdanm	82:6473597d706e	4480	#define HW_ENET_RACC_WR(x, v) (HW_ENET_RACC(x).U = (v))
bogdanm	82:6473597d706e	4481	#define HW_ENET_RACC_SET(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) \| (v)))
bogdanm	82:6473597d706e	4482	#define HW_ENET_RACC_CLR(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) & ~(v)))
bogdanm	82:6473597d706e	4483	#define HW_ENET_RACC_TOG(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) ^ (v)))
bogdanm	82:6473597d706e	4484	#endif
bogdanm	82:6473597d706e	4485	//@}
bogdanm	82:6473597d706e	4486
bogdanm	82:6473597d706e	4487	/*
bogdanm	82:6473597d706e	4488	* Constants & macros for individual ENET_RACC bitfields
bogdanm	82:6473597d706e	4489	*/
bogdanm	82:6473597d706e	4490
bogdanm	82:6473597d706e	4491	/*!
bogdanm	82:6473597d706e	4492	* @name Register ENET_RACC, field PADREM[0] (RW)
bogdanm	82:6473597d706e	4493	*
bogdanm	82:6473597d706e	4494	* Values:
bogdanm	82:6473597d706e	4495	* - 0 - Padding not removed.
bogdanm	82:6473597d706e	4496	* - 1 - Any bytes following the IP payload section of the frame are removed
bogdanm	82:6473597d706e	4497	* from the frame.
bogdanm	82:6473597d706e	4498	*/
bogdanm	82:6473597d706e	4499	//@{
bogdanm	82:6473597d706e	4500	#define BP_ENET_RACC_PADREM (0U) //!< Bit position for ENET_RACC_PADREM.
bogdanm	82:6473597d706e	4501	#define BM_ENET_RACC_PADREM (0x00000001U) //!< Bit mask for ENET_RACC_PADREM.
bogdanm	82:6473597d706e	4502	#define BS_ENET_RACC_PADREM (1U) //!< Bit field size in bits for ENET_RACC_PADREM.
bogdanm	82:6473597d706e	4503
bogdanm	82:6473597d706e	4504	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4505	//! @brief Read current value of the ENET_RACC_PADREM field.
bogdanm	82:6473597d706e	4506	#define BR_ENET_RACC_PADREM(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM))
bogdanm	82:6473597d706e	4507	#endif
bogdanm	82:6473597d706e	4508
bogdanm	82:6473597d706e	4509	//! @brief Format value for bitfield ENET_RACC_PADREM.
bogdanm	82:6473597d706e	4510	#define BF_ENET_RACC_PADREM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_PADREM), uint32_t) & BM_ENET_RACC_PADREM)
bogdanm	82:6473597d706e	4511
bogdanm	82:6473597d706e	4512	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4513	//! @brief Set the PADREM field to a new value.
bogdanm	82:6473597d706e	4514	#define BW_ENET_RACC_PADREM(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM) = (v))
bogdanm	82:6473597d706e	4515	#endif
bogdanm	82:6473597d706e	4516	//@}
bogdanm	82:6473597d706e	4517
bogdanm	82:6473597d706e	4518	/*!
bogdanm	82:6473597d706e	4519	* @name Register ENET_RACC, field IPDIS[1] (RW)
bogdanm	82:6473597d706e	4520	*
bogdanm	82:6473597d706e	4521	* Values:
bogdanm	82:6473597d706e	4522	* - 0 - Frames with wrong IPv4 header checksum are not discarded.
bogdanm	82:6473597d706e	4523	* - 1 - If an IPv4 frame is received with a mismatching header checksum, the
bogdanm	82:6473597d706e	4524	* frame is discarded. IPv6 has no header checksum and is not affected by this
bogdanm	82:6473597d706e	4525	* setting. Discarding is only available when the RX FIFO operates in store
bogdanm	82:6473597d706e	4526	* and forward mode (RSFL cleared).
bogdanm	82:6473597d706e	4527	*/
bogdanm	82:6473597d706e	4528	//@{
bogdanm	82:6473597d706e	4529	#define BP_ENET_RACC_IPDIS (1U) //!< Bit position for ENET_RACC_IPDIS.
bogdanm	82:6473597d706e	4530	#define BM_ENET_RACC_IPDIS (0x00000002U) //!< Bit mask for ENET_RACC_IPDIS.
bogdanm	82:6473597d706e	4531	#define BS_ENET_RACC_IPDIS (1U) //!< Bit field size in bits for ENET_RACC_IPDIS.
bogdanm	82:6473597d706e	4532
bogdanm	82:6473597d706e	4533	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4534	//! @brief Read current value of the ENET_RACC_IPDIS field.
bogdanm	82:6473597d706e	4535	#define BR_ENET_RACC_IPDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS))
bogdanm	82:6473597d706e	4536	#endif
bogdanm	82:6473597d706e	4537
bogdanm	82:6473597d706e	4538	//! @brief Format value for bitfield ENET_RACC_IPDIS.
bogdanm	82:6473597d706e	4539	#define BF_ENET_RACC_IPDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_IPDIS), uint32_t) & BM_ENET_RACC_IPDIS)
bogdanm	82:6473597d706e	4540
bogdanm	82:6473597d706e	4541	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4542	//! @brief Set the IPDIS field to a new value.
bogdanm	82:6473597d706e	4543	#define BW_ENET_RACC_IPDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS) = (v))
bogdanm	82:6473597d706e	4544	#endif
bogdanm	82:6473597d706e	4545	//@}
bogdanm	82:6473597d706e	4546
bogdanm	82:6473597d706e	4547	/*!
bogdanm	82:6473597d706e	4548	* @name Register ENET_RACC, field PRODIS[2] (RW)
bogdanm	82:6473597d706e	4549	*
bogdanm	82:6473597d706e	4550	* Values:
bogdanm	82:6473597d706e	4551	* - 0 - Frames with wrong checksum are not discarded.
bogdanm	82:6473597d706e	4552	* - 1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP,
bogdanm	82:6473597d706e	4553	* UDP, or ICMP checksum, the frame is discarded. Discarding is only
bogdanm	82:6473597d706e	4554	* available when the RX FIFO operates in store and forward mode (RSFL cleared).
bogdanm	82:6473597d706e	4555	*/
bogdanm	82:6473597d706e	4556	//@{
bogdanm	82:6473597d706e	4557	#define BP_ENET_RACC_PRODIS (2U) //!< Bit position for ENET_RACC_PRODIS.
bogdanm	82:6473597d706e	4558	#define BM_ENET_RACC_PRODIS (0x00000004U) //!< Bit mask for ENET_RACC_PRODIS.
bogdanm	82:6473597d706e	4559	#define BS_ENET_RACC_PRODIS (1U) //!< Bit field size in bits for ENET_RACC_PRODIS.
bogdanm	82:6473597d706e	4560
bogdanm	82:6473597d706e	4561	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4562	//! @brief Read current value of the ENET_RACC_PRODIS field.
bogdanm	82:6473597d706e	4563	#define BR_ENET_RACC_PRODIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS))
bogdanm	82:6473597d706e	4564	#endif
bogdanm	82:6473597d706e	4565
bogdanm	82:6473597d706e	4566	//! @brief Format value for bitfield ENET_RACC_PRODIS.
bogdanm	82:6473597d706e	4567	#define BF_ENET_RACC_PRODIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_PRODIS), uint32_t) & BM_ENET_RACC_PRODIS)
bogdanm	82:6473597d706e	4568
bogdanm	82:6473597d706e	4569	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4570	//! @brief Set the PRODIS field to a new value.
bogdanm	82:6473597d706e	4571	#define BW_ENET_RACC_PRODIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS) = (v))
bogdanm	82:6473597d706e	4572	#endif
bogdanm	82:6473597d706e	4573	//@}
bogdanm	82:6473597d706e	4574
bogdanm	82:6473597d706e	4575	/*!
bogdanm	82:6473597d706e	4576	* @name Register ENET_RACC, field LINEDIS[6] (RW)
bogdanm	82:6473597d706e	4577	*
bogdanm	82:6473597d706e	4578	* Values:
bogdanm	82:6473597d706e	4579	* - 0 - Frames with errors are not discarded.
bogdanm	82:6473597d706e	4580	* - 1 - Any frame received with a CRC, length, or PHY error is automatically
bogdanm	82:6473597d706e	4581	* discarded and not forwarded to the user application interface.
bogdanm	82:6473597d706e	4582	*/
bogdanm	82:6473597d706e	4583	//@{
bogdanm	82:6473597d706e	4584	#define BP_ENET_RACC_LINEDIS (6U) //!< Bit position for ENET_RACC_LINEDIS.
bogdanm	82:6473597d706e	4585	#define BM_ENET_RACC_LINEDIS (0x00000040U) //!< Bit mask for ENET_RACC_LINEDIS.
bogdanm	82:6473597d706e	4586	#define BS_ENET_RACC_LINEDIS (1U) //!< Bit field size in bits for ENET_RACC_LINEDIS.
bogdanm	82:6473597d706e	4587
bogdanm	82:6473597d706e	4588	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4589	//! @brief Read current value of the ENET_RACC_LINEDIS field.
bogdanm	82:6473597d706e	4590	#define BR_ENET_RACC_LINEDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS))
bogdanm	82:6473597d706e	4591	#endif
bogdanm	82:6473597d706e	4592
bogdanm	82:6473597d706e	4593	//! @brief Format value for bitfield ENET_RACC_LINEDIS.
bogdanm	82:6473597d706e	4594	#define BF_ENET_RACC_LINEDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_LINEDIS), uint32_t) & BM_ENET_RACC_LINEDIS)
bogdanm	82:6473597d706e	4595
bogdanm	82:6473597d706e	4596	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4597	//! @brief Set the LINEDIS field to a new value.
bogdanm	82:6473597d706e	4598	#define BW_ENET_RACC_LINEDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS) = (v))
bogdanm	82:6473597d706e	4599	#endif
bogdanm	82:6473597d706e	4600	//@}
bogdanm	82:6473597d706e	4601
bogdanm	82:6473597d706e	4602	/*!
bogdanm	82:6473597d706e	4603	* @name Register ENET_RACC, field SHIFT16[7] (RW)
bogdanm	82:6473597d706e	4604	*
bogdanm	82:6473597d706e	4605	* When this field is set, the actual frame data starts at bit 16 of the first
bogdanm	82:6473597d706e	4606	* word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
bogdanm	82:6473597d706e	4607	* This function only affects the FIFO storage and has no influence on the
bogdanm	82:6473597d706e	4608	* statistics, which use the actual length of the frame received.
bogdanm	82:6473597d706e	4609	*
bogdanm	82:6473597d706e	4610	* Values:
bogdanm	82:6473597d706e	4611	* - 0 - Disabled.
bogdanm	82:6473597d706e	4612	* - 1 - Instructs the MAC to write two additional bytes in front of each frame
bogdanm	82:6473597d706e	4613	* received into the RX FIFO.
bogdanm	82:6473597d706e	4614	*/
bogdanm	82:6473597d706e	4615	//@{
bogdanm	82:6473597d706e	4616	#define BP_ENET_RACC_SHIFT16 (7U) //!< Bit position for ENET_RACC_SHIFT16.
bogdanm	82:6473597d706e	4617	#define BM_ENET_RACC_SHIFT16 (0x00000080U) //!< Bit mask for ENET_RACC_SHIFT16.
bogdanm	82:6473597d706e	4618	#define BS_ENET_RACC_SHIFT16 (1U) //!< Bit field size in bits for ENET_RACC_SHIFT16.
bogdanm	82:6473597d706e	4619
bogdanm	82:6473597d706e	4620	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4621	//! @brief Read current value of the ENET_RACC_SHIFT16 field.
bogdanm	82:6473597d706e	4622	#define BR_ENET_RACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16))
bogdanm	82:6473597d706e	4623	#endif
bogdanm	82:6473597d706e	4624
bogdanm	82:6473597d706e	4625	//! @brief Format value for bitfield ENET_RACC_SHIFT16.
bogdanm	82:6473597d706e	4626	#define BF_ENET_RACC_SHIFT16(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_SHIFT16), uint32_t) & BM_ENET_RACC_SHIFT16)
bogdanm	82:6473597d706e	4627
bogdanm	82:6473597d706e	4628	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4629	//! @brief Set the SHIFT16 field to a new value.
bogdanm	82:6473597d706e	4630	#define BW_ENET_RACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16) = (v))
bogdanm	82:6473597d706e	4631	#endif
bogdanm	82:6473597d706e	4632	//@}
bogdanm	82:6473597d706e	4633
bogdanm	82:6473597d706e	4634	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4635	// HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
bogdanm	82:6473597d706e	4636	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4637
bogdanm	82:6473597d706e	4638	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4639	/*!
bogdanm	82:6473597d706e	4640	* @brief HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
bogdanm	82:6473597d706e	4641	*
bogdanm	82:6473597d706e	4642	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4643	*/
bogdanm	82:6473597d706e	4644	typedef union _hw_enet_rmon_t_packets
bogdanm	82:6473597d706e	4645	{
bogdanm	82:6473597d706e	4646	uint32_t U;
bogdanm	82:6473597d706e	4647	struct _hw_enet_rmon_t_packets_bitfields
bogdanm	82:6473597d706e	4648	{
bogdanm	82:6473597d706e	4649	uint32_t TXPKTS : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	4650	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	4651	} B;
bogdanm	82:6473597d706e	4652	} hw_enet_rmon_t_packets_t;
bogdanm	82:6473597d706e	4653	#endif
bogdanm	82:6473597d706e	4654
bogdanm	82:6473597d706e	4655	/*!
bogdanm	82:6473597d706e	4656	* @name Constants and macros for entire ENET_RMON_T_PACKETS register
bogdanm	82:6473597d706e	4657	*/
bogdanm	82:6473597d706e	4658	//@{
bogdanm	82:6473597d706e	4659	#define HW_ENET_RMON_T_PACKETS_ADDR(x) (REGS_ENET_BASE(x) + 0x204U)
bogdanm	82:6473597d706e	4660
bogdanm	82:6473597d706e	4661	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4662	#define HW_ENET_RMON_T_PACKETS(x) ((__I hw_enet_rmon_t_packets_t ) HW_ENET_RMON_T_PACKETS_ADDR(x))
bogdanm	82:6473597d706e	4663	#define HW_ENET_RMON_T_PACKETS_RD(x) (HW_ENET_RMON_T_PACKETS(x).U)
bogdanm	82:6473597d706e	4664	#endif
bogdanm	82:6473597d706e	4665	//@}
bogdanm	82:6473597d706e	4666
bogdanm	82:6473597d706e	4667	/*
bogdanm	82:6473597d706e	4668	* Constants & macros for individual ENET_RMON_T_PACKETS bitfields
bogdanm	82:6473597d706e	4669	*/
bogdanm	82:6473597d706e	4670
bogdanm	82:6473597d706e	4671	/*!
bogdanm	82:6473597d706e	4672	* @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	4673	*/
bogdanm	82:6473597d706e	4674	//@{
bogdanm	82:6473597d706e	4675	#define BP_ENET_RMON_T_PACKETS_TXPKTS (0U) //!< Bit position for ENET_RMON_T_PACKETS_TXPKTS.
bogdanm	82:6473597d706e	4676	#define BM_ENET_RMON_T_PACKETS_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_PACKETS_TXPKTS.
bogdanm	82:6473597d706e	4677	#define BS_ENET_RMON_T_PACKETS_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_PACKETS_TXPKTS.
bogdanm	82:6473597d706e	4678
bogdanm	82:6473597d706e	4679	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4680	//! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field.
bogdanm	82:6473597d706e	4681	#define BR_ENET_RMON_T_PACKETS_TXPKTS(x) (HW_ENET_RMON_T_PACKETS(x).B.TXPKTS)
bogdanm	82:6473597d706e	4682	#endif
bogdanm	82:6473597d706e	4683	//@}
bogdanm	82:6473597d706e	4684
bogdanm	82:6473597d706e	4685	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4686	// HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
bogdanm	82:6473597d706e	4687	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4688
bogdanm	82:6473597d706e	4689	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4690	/*!
bogdanm	82:6473597d706e	4691	* @brief HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
bogdanm	82:6473597d706e	4692	*
bogdanm	82:6473597d706e	4693	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4694	*
bogdanm	82:6473597d706e	4695	* RMON Tx Broadcast Packets
bogdanm	82:6473597d706e	4696	*/
bogdanm	82:6473597d706e	4697	typedef union _hw_enet_rmon_t_bc_pkt
bogdanm	82:6473597d706e	4698	{
bogdanm	82:6473597d706e	4699	uint32_t U;
bogdanm	82:6473597d706e	4700	struct _hw_enet_rmon_t_bc_pkt_bitfields
bogdanm	82:6473597d706e	4701	{
bogdanm	82:6473597d706e	4702	uint32_t TXPKTS : 16; //!< [15:0] Broadcast packets
bogdanm	82:6473597d706e	4703	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	4704	} B;
bogdanm	82:6473597d706e	4705	} hw_enet_rmon_t_bc_pkt_t;
bogdanm	82:6473597d706e	4706	#endif
bogdanm	82:6473597d706e	4707
bogdanm	82:6473597d706e	4708	/*!
bogdanm	82:6473597d706e	4709	* @name Constants and macros for entire ENET_RMON_T_BC_PKT register
bogdanm	82:6473597d706e	4710	*/
bogdanm	82:6473597d706e	4711	//@{
bogdanm	82:6473597d706e	4712	#define HW_ENET_RMON_T_BC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x208U)
bogdanm	82:6473597d706e	4713
bogdanm	82:6473597d706e	4714	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4715	#define HW_ENET_RMON_T_BC_PKT(x) ((__I hw_enet_rmon_t_bc_pkt_t ) HW_ENET_RMON_T_BC_PKT_ADDR(x))
bogdanm	82:6473597d706e	4716	#define HW_ENET_RMON_T_BC_PKT_RD(x) (HW_ENET_RMON_T_BC_PKT(x).U)
bogdanm	82:6473597d706e	4717	#endif
bogdanm	82:6473597d706e	4718	//@}
bogdanm	82:6473597d706e	4719
bogdanm	82:6473597d706e	4720	/*
bogdanm	82:6473597d706e	4721	* Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
bogdanm	82:6473597d706e	4722	*/
bogdanm	82:6473597d706e	4723
bogdanm	82:6473597d706e	4724	/*!
bogdanm	82:6473597d706e	4725	* @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	4726	*/
bogdanm	82:6473597d706e	4727	//@{
bogdanm	82:6473597d706e	4728	#define BP_ENET_RMON_T_BC_PKT_TXPKTS (0U) //!< Bit position for ENET_RMON_T_BC_PKT_TXPKTS.
bogdanm	82:6473597d706e	4729	#define BM_ENET_RMON_T_BC_PKT_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_BC_PKT_TXPKTS.
bogdanm	82:6473597d706e	4730	#define BS_ENET_RMON_T_BC_PKT_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_BC_PKT_TXPKTS.
bogdanm	82:6473597d706e	4731
bogdanm	82:6473597d706e	4732	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4733	//! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field.
bogdanm	82:6473597d706e	4734	#define BR_ENET_RMON_T_BC_PKT_TXPKTS(x) (HW_ENET_RMON_T_BC_PKT(x).B.TXPKTS)
bogdanm	82:6473597d706e	4735	#endif
bogdanm	82:6473597d706e	4736	//@}
bogdanm	82:6473597d706e	4737
bogdanm	82:6473597d706e	4738	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4739	// HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
bogdanm	82:6473597d706e	4740	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4741
bogdanm	82:6473597d706e	4742	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4743	/*!
bogdanm	82:6473597d706e	4744	* @brief HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
bogdanm	82:6473597d706e	4745	*
bogdanm	82:6473597d706e	4746	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4747	*/
bogdanm	82:6473597d706e	4748	typedef union _hw_enet_rmon_t_mc_pkt
bogdanm	82:6473597d706e	4749	{
bogdanm	82:6473597d706e	4750	uint32_t U;
bogdanm	82:6473597d706e	4751	struct _hw_enet_rmon_t_mc_pkt_bitfields
bogdanm	82:6473597d706e	4752	{
bogdanm	82:6473597d706e	4753	uint32_t TXPKTS : 16; //!< [15:0] Multicast packets
bogdanm	82:6473597d706e	4754	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	4755	} B;
bogdanm	82:6473597d706e	4756	} hw_enet_rmon_t_mc_pkt_t;
bogdanm	82:6473597d706e	4757	#endif
bogdanm	82:6473597d706e	4758
bogdanm	82:6473597d706e	4759	/*!
bogdanm	82:6473597d706e	4760	* @name Constants and macros for entire ENET_RMON_T_MC_PKT register
bogdanm	82:6473597d706e	4761	*/
bogdanm	82:6473597d706e	4762	//@{
bogdanm	82:6473597d706e	4763	#define HW_ENET_RMON_T_MC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x20CU)
bogdanm	82:6473597d706e	4764
bogdanm	82:6473597d706e	4765	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4766	#define HW_ENET_RMON_T_MC_PKT(x) ((__I hw_enet_rmon_t_mc_pkt_t ) HW_ENET_RMON_T_MC_PKT_ADDR(x))
bogdanm	82:6473597d706e	4767	#define HW_ENET_RMON_T_MC_PKT_RD(x) (HW_ENET_RMON_T_MC_PKT(x).U)
bogdanm	82:6473597d706e	4768	#endif
bogdanm	82:6473597d706e	4769	//@}
bogdanm	82:6473597d706e	4770
bogdanm	82:6473597d706e	4771	/*
bogdanm	82:6473597d706e	4772	* Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
bogdanm	82:6473597d706e	4773	*/
bogdanm	82:6473597d706e	4774
bogdanm	82:6473597d706e	4775	/*!
bogdanm	82:6473597d706e	4776	* @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	4777	*/
bogdanm	82:6473597d706e	4778	//@{
bogdanm	82:6473597d706e	4779	#define BP_ENET_RMON_T_MC_PKT_TXPKTS (0U) //!< Bit position for ENET_RMON_T_MC_PKT_TXPKTS.
bogdanm	82:6473597d706e	4780	#define BM_ENET_RMON_T_MC_PKT_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_MC_PKT_TXPKTS.
bogdanm	82:6473597d706e	4781	#define BS_ENET_RMON_T_MC_PKT_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_MC_PKT_TXPKTS.
bogdanm	82:6473597d706e	4782
bogdanm	82:6473597d706e	4783	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4784	//! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field.
bogdanm	82:6473597d706e	4785	#define BR_ENET_RMON_T_MC_PKT_TXPKTS(x) (HW_ENET_RMON_T_MC_PKT(x).B.TXPKTS)
bogdanm	82:6473597d706e	4786	#endif
bogdanm	82:6473597d706e	4787	//@}
bogdanm	82:6473597d706e	4788
bogdanm	82:6473597d706e	4789	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4790	// HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
bogdanm	82:6473597d706e	4791	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4792
bogdanm	82:6473597d706e	4793	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4794	/*!
bogdanm	82:6473597d706e	4795	* @brief HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
bogdanm	82:6473597d706e	4796	*
bogdanm	82:6473597d706e	4797	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4798	*/
bogdanm	82:6473597d706e	4799	typedef union _hw_enet_rmon_t_crc_align
bogdanm	82:6473597d706e	4800	{
bogdanm	82:6473597d706e	4801	uint32_t U;
bogdanm	82:6473597d706e	4802	struct _hw_enet_rmon_t_crc_align_bitfields
bogdanm	82:6473597d706e	4803	{
bogdanm	82:6473597d706e	4804	uint32_t TXPKTS : 16; //!< [15:0] Packets with CRC/align error
bogdanm	82:6473597d706e	4805	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	4806	} B;
bogdanm	82:6473597d706e	4807	} hw_enet_rmon_t_crc_align_t;
bogdanm	82:6473597d706e	4808	#endif
bogdanm	82:6473597d706e	4809
bogdanm	82:6473597d706e	4810	/*!
bogdanm	82:6473597d706e	4811	* @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
bogdanm	82:6473597d706e	4812	*/
bogdanm	82:6473597d706e	4813	//@{
bogdanm	82:6473597d706e	4814	#define HW_ENET_RMON_T_CRC_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x210U)
bogdanm	82:6473597d706e	4815
bogdanm	82:6473597d706e	4816	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4817	#define HW_ENET_RMON_T_CRC_ALIGN(x) ((__I hw_enet_rmon_t_crc_align_t ) HW_ENET_RMON_T_CRC_ALIGN_ADDR(x))
bogdanm	82:6473597d706e	4818	#define HW_ENET_RMON_T_CRC_ALIGN_RD(x) (HW_ENET_RMON_T_CRC_ALIGN(x).U)
bogdanm	82:6473597d706e	4819	#endif
bogdanm	82:6473597d706e	4820	//@}
bogdanm	82:6473597d706e	4821
bogdanm	82:6473597d706e	4822	/*
bogdanm	82:6473597d706e	4823	* Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
bogdanm	82:6473597d706e	4824	*/
bogdanm	82:6473597d706e	4825
bogdanm	82:6473597d706e	4826	/*!
bogdanm	82:6473597d706e	4827	* @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	4828	*/
bogdanm	82:6473597d706e	4829	//@{
bogdanm	82:6473597d706e	4830	#define BP_ENET_RMON_T_CRC_ALIGN_TXPKTS (0U) //!< Bit position for ENET_RMON_T_CRC_ALIGN_TXPKTS.
bogdanm	82:6473597d706e	4831	#define BM_ENET_RMON_T_CRC_ALIGN_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_CRC_ALIGN_TXPKTS.
bogdanm	82:6473597d706e	4832	#define BS_ENET_RMON_T_CRC_ALIGN_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_CRC_ALIGN_TXPKTS.
bogdanm	82:6473597d706e	4833
bogdanm	82:6473597d706e	4834	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4835	//! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field.
bogdanm	82:6473597d706e	4836	#define BR_ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (HW_ENET_RMON_T_CRC_ALIGN(x).B.TXPKTS)
bogdanm	82:6473597d706e	4837	#endif
bogdanm	82:6473597d706e	4838	//@}
bogdanm	82:6473597d706e	4839
bogdanm	82:6473597d706e	4840	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4841	// HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
bogdanm	82:6473597d706e	4842	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4843
bogdanm	82:6473597d706e	4844	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4845	/*!
bogdanm	82:6473597d706e	4846	* @brief HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
bogdanm	82:6473597d706e	4847	*
bogdanm	82:6473597d706e	4848	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4849	*/
bogdanm	82:6473597d706e	4850	typedef union _hw_enet_rmon_t_undersize
bogdanm	82:6473597d706e	4851	{
bogdanm	82:6473597d706e	4852	uint32_t U;
bogdanm	82:6473597d706e	4853	struct _hw_enet_rmon_t_undersize_bitfields
bogdanm	82:6473597d706e	4854	{
bogdanm	82:6473597d706e	4855	uint32_t TXPKTS : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	4856	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	4857	} B;
bogdanm	82:6473597d706e	4858	} hw_enet_rmon_t_undersize_t;
bogdanm	82:6473597d706e	4859	#endif
bogdanm	82:6473597d706e	4860
bogdanm	82:6473597d706e	4861	/*!
bogdanm	82:6473597d706e	4862	* @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
bogdanm	82:6473597d706e	4863	*/
bogdanm	82:6473597d706e	4864	//@{
bogdanm	82:6473597d706e	4865	#define HW_ENET_RMON_T_UNDERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x214U)
bogdanm	82:6473597d706e	4866
bogdanm	82:6473597d706e	4867	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4868	#define HW_ENET_RMON_T_UNDERSIZE(x) ((__I hw_enet_rmon_t_undersize_t ) HW_ENET_RMON_T_UNDERSIZE_ADDR(x))
bogdanm	82:6473597d706e	4869	#define HW_ENET_RMON_T_UNDERSIZE_RD(x) (HW_ENET_RMON_T_UNDERSIZE(x).U)
bogdanm	82:6473597d706e	4870	#endif
bogdanm	82:6473597d706e	4871	//@}
bogdanm	82:6473597d706e	4872
bogdanm	82:6473597d706e	4873	/*
bogdanm	82:6473597d706e	4874	* Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
bogdanm	82:6473597d706e	4875	*/
bogdanm	82:6473597d706e	4876
bogdanm	82:6473597d706e	4877	/*!
bogdanm	82:6473597d706e	4878	* @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	4879	*/
bogdanm	82:6473597d706e	4880	//@{
bogdanm	82:6473597d706e	4881	#define BP_ENET_RMON_T_UNDERSIZE_TXPKTS (0U) //!< Bit position for ENET_RMON_T_UNDERSIZE_TXPKTS.
bogdanm	82:6473597d706e	4882	#define BM_ENET_RMON_T_UNDERSIZE_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_UNDERSIZE_TXPKTS.
bogdanm	82:6473597d706e	4883	#define BS_ENET_RMON_T_UNDERSIZE_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_UNDERSIZE_TXPKTS.
bogdanm	82:6473597d706e	4884
bogdanm	82:6473597d706e	4885	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4886	//! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field.
bogdanm	82:6473597d706e	4887	#define BR_ENET_RMON_T_UNDERSIZE_TXPKTS(x) (HW_ENET_RMON_T_UNDERSIZE(x).B.TXPKTS)
bogdanm	82:6473597d706e	4888	#endif
bogdanm	82:6473597d706e	4889	//@}
bogdanm	82:6473597d706e	4890
bogdanm	82:6473597d706e	4891	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4892	// HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
bogdanm	82:6473597d706e	4893	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4894
bogdanm	82:6473597d706e	4895	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4896	/*!
bogdanm	82:6473597d706e	4897	* @brief HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
bogdanm	82:6473597d706e	4898	*
bogdanm	82:6473597d706e	4899	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4900	*/
bogdanm	82:6473597d706e	4901	typedef union _hw_enet_rmon_t_oversize
bogdanm	82:6473597d706e	4902	{
bogdanm	82:6473597d706e	4903	uint32_t U;
bogdanm	82:6473597d706e	4904	struct _hw_enet_rmon_t_oversize_bitfields
bogdanm	82:6473597d706e	4905	{
bogdanm	82:6473597d706e	4906	uint32_t TXPKTS : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	4907	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	4908	} B;
bogdanm	82:6473597d706e	4909	} hw_enet_rmon_t_oversize_t;
bogdanm	82:6473597d706e	4910	#endif
bogdanm	82:6473597d706e	4911
bogdanm	82:6473597d706e	4912	/*!
bogdanm	82:6473597d706e	4913	* @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
bogdanm	82:6473597d706e	4914	*/
bogdanm	82:6473597d706e	4915	//@{
bogdanm	82:6473597d706e	4916	#define HW_ENET_RMON_T_OVERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x218U)
bogdanm	82:6473597d706e	4917
bogdanm	82:6473597d706e	4918	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4919	#define HW_ENET_RMON_T_OVERSIZE(x) ((__I hw_enet_rmon_t_oversize_t ) HW_ENET_RMON_T_OVERSIZE_ADDR(x))
bogdanm	82:6473597d706e	4920	#define HW_ENET_RMON_T_OVERSIZE_RD(x) (HW_ENET_RMON_T_OVERSIZE(x).U)
bogdanm	82:6473597d706e	4921	#endif
bogdanm	82:6473597d706e	4922	//@}
bogdanm	82:6473597d706e	4923
bogdanm	82:6473597d706e	4924	/*
bogdanm	82:6473597d706e	4925	* Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
bogdanm	82:6473597d706e	4926	*/
bogdanm	82:6473597d706e	4927
bogdanm	82:6473597d706e	4928	/*!
bogdanm	82:6473597d706e	4929	* @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	4930	*/
bogdanm	82:6473597d706e	4931	//@{
bogdanm	82:6473597d706e	4932	#define BP_ENET_RMON_T_OVERSIZE_TXPKTS (0U) //!< Bit position for ENET_RMON_T_OVERSIZE_TXPKTS.
bogdanm	82:6473597d706e	4933	#define BM_ENET_RMON_T_OVERSIZE_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_OVERSIZE_TXPKTS.
bogdanm	82:6473597d706e	4934	#define BS_ENET_RMON_T_OVERSIZE_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_OVERSIZE_TXPKTS.
bogdanm	82:6473597d706e	4935
bogdanm	82:6473597d706e	4936	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4937	//! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field.
bogdanm	82:6473597d706e	4938	#define BR_ENET_RMON_T_OVERSIZE_TXPKTS(x) (HW_ENET_RMON_T_OVERSIZE(x).B.TXPKTS)
bogdanm	82:6473597d706e	4939	#endif
bogdanm	82:6473597d706e	4940	//@}
bogdanm	82:6473597d706e	4941
bogdanm	82:6473597d706e	4942	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4943	// HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
bogdanm	82:6473597d706e	4944	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4945
bogdanm	82:6473597d706e	4946	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4947	/*!
bogdanm	82:6473597d706e	4948	* @brief HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
bogdanm	82:6473597d706e	4949	*
bogdanm	82:6473597d706e	4950	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4951	*
bogdanm	82:6473597d706e	4952	* .
bogdanm	82:6473597d706e	4953	*/
bogdanm	82:6473597d706e	4954	typedef union _hw_enet_rmon_t_frag
bogdanm	82:6473597d706e	4955	{
bogdanm	82:6473597d706e	4956	uint32_t U;
bogdanm	82:6473597d706e	4957	struct _hw_enet_rmon_t_frag_bitfields
bogdanm	82:6473597d706e	4958	{
bogdanm	82:6473597d706e	4959	uint32_t TXPKTS : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	4960	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	4961	} B;
bogdanm	82:6473597d706e	4962	} hw_enet_rmon_t_frag_t;
bogdanm	82:6473597d706e	4963	#endif
bogdanm	82:6473597d706e	4964
bogdanm	82:6473597d706e	4965	/*!
bogdanm	82:6473597d706e	4966	* @name Constants and macros for entire ENET_RMON_T_FRAG register
bogdanm	82:6473597d706e	4967	*/
bogdanm	82:6473597d706e	4968	//@{
bogdanm	82:6473597d706e	4969	#define HW_ENET_RMON_T_FRAG_ADDR(x) (REGS_ENET_BASE(x) + 0x21CU)
bogdanm	82:6473597d706e	4970
bogdanm	82:6473597d706e	4971	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4972	#define HW_ENET_RMON_T_FRAG(x) ((__I hw_enet_rmon_t_frag_t ) HW_ENET_RMON_T_FRAG_ADDR(x))
bogdanm	82:6473597d706e	4973	#define HW_ENET_RMON_T_FRAG_RD(x) (HW_ENET_RMON_T_FRAG(x).U)
bogdanm	82:6473597d706e	4974	#endif
bogdanm	82:6473597d706e	4975	//@}
bogdanm	82:6473597d706e	4976
bogdanm	82:6473597d706e	4977	/*
bogdanm	82:6473597d706e	4978	* Constants & macros for individual ENET_RMON_T_FRAG bitfields
bogdanm	82:6473597d706e	4979	*/
bogdanm	82:6473597d706e	4980
bogdanm	82:6473597d706e	4981	/*!
bogdanm	82:6473597d706e	4982	* @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	4983	*/
bogdanm	82:6473597d706e	4984	//@{
bogdanm	82:6473597d706e	4985	#define BP_ENET_RMON_T_FRAG_TXPKTS (0U) //!< Bit position for ENET_RMON_T_FRAG_TXPKTS.
bogdanm	82:6473597d706e	4986	#define BM_ENET_RMON_T_FRAG_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_FRAG_TXPKTS.
bogdanm	82:6473597d706e	4987	#define BS_ENET_RMON_T_FRAG_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_FRAG_TXPKTS.
bogdanm	82:6473597d706e	4988
bogdanm	82:6473597d706e	4989	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4990	//! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field.
bogdanm	82:6473597d706e	4991	#define BR_ENET_RMON_T_FRAG_TXPKTS(x) (HW_ENET_RMON_T_FRAG(x).B.TXPKTS)
bogdanm	82:6473597d706e	4992	#endif
bogdanm	82:6473597d706e	4993	//@}
bogdanm	82:6473597d706e	4994
bogdanm	82:6473597d706e	4995	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4996	// HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
bogdanm	82:6473597d706e	4997	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4998
bogdanm	82:6473597d706e	4999	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5000	/*!
bogdanm	82:6473597d706e	5001	* @brief HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
bogdanm	82:6473597d706e	5002	*
bogdanm	82:6473597d706e	5003	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5004	*/
bogdanm	82:6473597d706e	5005	typedef union _hw_enet_rmon_t_jab
bogdanm	82:6473597d706e	5006	{
bogdanm	82:6473597d706e	5007	uint32_t U;
bogdanm	82:6473597d706e	5008	struct _hw_enet_rmon_t_jab_bitfields
bogdanm	82:6473597d706e	5009	{
bogdanm	82:6473597d706e	5010	uint32_t TXPKTS : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	5011	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5012	} B;
bogdanm	82:6473597d706e	5013	} hw_enet_rmon_t_jab_t;
bogdanm	82:6473597d706e	5014	#endif
bogdanm	82:6473597d706e	5015
bogdanm	82:6473597d706e	5016	/*!
bogdanm	82:6473597d706e	5017	* @name Constants and macros for entire ENET_RMON_T_JAB register
bogdanm	82:6473597d706e	5018	*/
bogdanm	82:6473597d706e	5019	//@{
bogdanm	82:6473597d706e	5020	#define HW_ENET_RMON_T_JAB_ADDR(x) (REGS_ENET_BASE(x) + 0x220U)
bogdanm	82:6473597d706e	5021
bogdanm	82:6473597d706e	5022	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5023	#define HW_ENET_RMON_T_JAB(x) ((__I hw_enet_rmon_t_jab_t ) HW_ENET_RMON_T_JAB_ADDR(x))
bogdanm	82:6473597d706e	5024	#define HW_ENET_RMON_T_JAB_RD(x) (HW_ENET_RMON_T_JAB(x).U)
bogdanm	82:6473597d706e	5025	#endif
bogdanm	82:6473597d706e	5026	//@}
bogdanm	82:6473597d706e	5027
bogdanm	82:6473597d706e	5028	/*
bogdanm	82:6473597d706e	5029	* Constants & macros for individual ENET_RMON_T_JAB bitfields
bogdanm	82:6473597d706e	5030	*/
bogdanm	82:6473597d706e	5031
bogdanm	82:6473597d706e	5032	/*!
bogdanm	82:6473597d706e	5033	* @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	5034	*/
bogdanm	82:6473597d706e	5035	//@{
bogdanm	82:6473597d706e	5036	#define BP_ENET_RMON_T_JAB_TXPKTS (0U) //!< Bit position for ENET_RMON_T_JAB_TXPKTS.
bogdanm	82:6473597d706e	5037	#define BM_ENET_RMON_T_JAB_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_JAB_TXPKTS.
bogdanm	82:6473597d706e	5038	#define BS_ENET_RMON_T_JAB_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_JAB_TXPKTS.
bogdanm	82:6473597d706e	5039
bogdanm	82:6473597d706e	5040	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5041	//! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field.
bogdanm	82:6473597d706e	5042	#define BR_ENET_RMON_T_JAB_TXPKTS(x) (HW_ENET_RMON_T_JAB(x).B.TXPKTS)
bogdanm	82:6473597d706e	5043	#endif
bogdanm	82:6473597d706e	5044	//@}
bogdanm	82:6473597d706e	5045
bogdanm	82:6473597d706e	5046	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5047	// HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
bogdanm	82:6473597d706e	5048	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5049
bogdanm	82:6473597d706e	5050	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5051	/*!
bogdanm	82:6473597d706e	5052	* @brief HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
bogdanm	82:6473597d706e	5053	*
bogdanm	82:6473597d706e	5054	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5055	*/
bogdanm	82:6473597d706e	5056	typedef union _hw_enet_rmon_t_col
bogdanm	82:6473597d706e	5057	{
bogdanm	82:6473597d706e	5058	uint32_t U;
bogdanm	82:6473597d706e	5059	struct _hw_enet_rmon_t_col_bitfields
bogdanm	82:6473597d706e	5060	{
bogdanm	82:6473597d706e	5061	uint32_t TXPKTS : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	5062	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5063	} B;
bogdanm	82:6473597d706e	5064	} hw_enet_rmon_t_col_t;
bogdanm	82:6473597d706e	5065	#endif
bogdanm	82:6473597d706e	5066
bogdanm	82:6473597d706e	5067	/*!
bogdanm	82:6473597d706e	5068	* @name Constants and macros for entire ENET_RMON_T_COL register
bogdanm	82:6473597d706e	5069	*/
bogdanm	82:6473597d706e	5070	//@{
bogdanm	82:6473597d706e	5071	#define HW_ENET_RMON_T_COL_ADDR(x) (REGS_ENET_BASE(x) + 0x224U)
bogdanm	82:6473597d706e	5072
bogdanm	82:6473597d706e	5073	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5074	#define HW_ENET_RMON_T_COL(x) ((__I hw_enet_rmon_t_col_t ) HW_ENET_RMON_T_COL_ADDR(x))
bogdanm	82:6473597d706e	5075	#define HW_ENET_RMON_T_COL_RD(x) (HW_ENET_RMON_T_COL(x).U)
bogdanm	82:6473597d706e	5076	#endif
bogdanm	82:6473597d706e	5077	//@}
bogdanm	82:6473597d706e	5078
bogdanm	82:6473597d706e	5079	/*
bogdanm	82:6473597d706e	5080	* Constants & macros for individual ENET_RMON_T_COL bitfields
bogdanm	82:6473597d706e	5081	*/
bogdanm	82:6473597d706e	5082
bogdanm	82:6473597d706e	5083	/*!
bogdanm	82:6473597d706e	5084	* @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	5085	*/
bogdanm	82:6473597d706e	5086	//@{
bogdanm	82:6473597d706e	5087	#define BP_ENET_RMON_T_COL_TXPKTS (0U) //!< Bit position for ENET_RMON_T_COL_TXPKTS.
bogdanm	82:6473597d706e	5088	#define BM_ENET_RMON_T_COL_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_COL_TXPKTS.
bogdanm	82:6473597d706e	5089	#define BS_ENET_RMON_T_COL_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_COL_TXPKTS.
bogdanm	82:6473597d706e	5090
bogdanm	82:6473597d706e	5091	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5092	//! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field.
bogdanm	82:6473597d706e	5093	#define BR_ENET_RMON_T_COL_TXPKTS(x) (HW_ENET_RMON_T_COL(x).B.TXPKTS)
bogdanm	82:6473597d706e	5094	#endif
bogdanm	82:6473597d706e	5095	//@}
bogdanm	82:6473597d706e	5096
bogdanm	82:6473597d706e	5097	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5098	// HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
bogdanm	82:6473597d706e	5099	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5100
bogdanm	82:6473597d706e	5101	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5102	/*!
bogdanm	82:6473597d706e	5103	* @brief HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
bogdanm	82:6473597d706e	5104	*
bogdanm	82:6473597d706e	5105	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5106	*
bogdanm	82:6473597d706e	5107	* .
bogdanm	82:6473597d706e	5108	*/
bogdanm	82:6473597d706e	5109	typedef union _hw_enet_rmon_t_p64
bogdanm	82:6473597d706e	5110	{
bogdanm	82:6473597d706e	5111	uint32_t U;
bogdanm	82:6473597d706e	5112	struct _hw_enet_rmon_t_p64_bitfields
bogdanm	82:6473597d706e	5113	{
bogdanm	82:6473597d706e	5114	uint32_t TXPKTS : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	5115	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5116	} B;
bogdanm	82:6473597d706e	5117	} hw_enet_rmon_t_p64_t;
bogdanm	82:6473597d706e	5118	#endif
bogdanm	82:6473597d706e	5119
bogdanm	82:6473597d706e	5120	/*!
bogdanm	82:6473597d706e	5121	* @name Constants and macros for entire ENET_RMON_T_P64 register
bogdanm	82:6473597d706e	5122	*/
bogdanm	82:6473597d706e	5123	//@{
bogdanm	82:6473597d706e	5124	#define HW_ENET_RMON_T_P64_ADDR(x) (REGS_ENET_BASE(x) + 0x228U)
bogdanm	82:6473597d706e	5125
bogdanm	82:6473597d706e	5126	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5127	#define HW_ENET_RMON_T_P64(x) ((__I hw_enet_rmon_t_p64_t ) HW_ENET_RMON_T_P64_ADDR(x))
bogdanm	82:6473597d706e	5128	#define HW_ENET_RMON_T_P64_RD(x) (HW_ENET_RMON_T_P64(x).U)
bogdanm	82:6473597d706e	5129	#endif
bogdanm	82:6473597d706e	5130	//@}
bogdanm	82:6473597d706e	5131
bogdanm	82:6473597d706e	5132	/*
bogdanm	82:6473597d706e	5133	* Constants & macros for individual ENET_RMON_T_P64 bitfields
bogdanm	82:6473597d706e	5134	*/
bogdanm	82:6473597d706e	5135
bogdanm	82:6473597d706e	5136	/*!
bogdanm	82:6473597d706e	5137	* @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	5138	*/
bogdanm	82:6473597d706e	5139	//@{
bogdanm	82:6473597d706e	5140	#define BP_ENET_RMON_T_P64_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P64_TXPKTS.
bogdanm	82:6473597d706e	5141	#define BM_ENET_RMON_T_P64_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P64_TXPKTS.
bogdanm	82:6473597d706e	5142	#define BS_ENET_RMON_T_P64_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P64_TXPKTS.
bogdanm	82:6473597d706e	5143
bogdanm	82:6473597d706e	5144	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5145	//! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field.
bogdanm	82:6473597d706e	5146	#define BR_ENET_RMON_T_P64_TXPKTS(x) (HW_ENET_RMON_T_P64(x).B.TXPKTS)
bogdanm	82:6473597d706e	5147	#endif
bogdanm	82:6473597d706e	5148	//@}
bogdanm	82:6473597d706e	5149
bogdanm	82:6473597d706e	5150	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5151	// HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
bogdanm	82:6473597d706e	5152	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5153
bogdanm	82:6473597d706e	5154	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5155	/*!
bogdanm	82:6473597d706e	5156	* @brief HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
bogdanm	82:6473597d706e	5157	*
bogdanm	82:6473597d706e	5158	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5159	*/
bogdanm	82:6473597d706e	5160	typedef union _hw_enet_rmon_t_p65to127
bogdanm	82:6473597d706e	5161	{
bogdanm	82:6473597d706e	5162	uint32_t U;
bogdanm	82:6473597d706e	5163	struct _hw_enet_rmon_t_p65to127_bitfields
bogdanm	82:6473597d706e	5164	{
bogdanm	82:6473597d706e	5165	uint32_t TXPKTS : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	5166	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5167	} B;
bogdanm	82:6473597d706e	5168	} hw_enet_rmon_t_p65to127_t;
bogdanm	82:6473597d706e	5169	#endif
bogdanm	82:6473597d706e	5170
bogdanm	82:6473597d706e	5171	/*!
bogdanm	82:6473597d706e	5172	* @name Constants and macros for entire ENET_RMON_T_P65TO127 register
bogdanm	82:6473597d706e	5173	*/
bogdanm	82:6473597d706e	5174	//@{
bogdanm	82:6473597d706e	5175	#define HW_ENET_RMON_T_P65TO127_ADDR(x) (REGS_ENET_BASE(x) + 0x22CU)
bogdanm	82:6473597d706e	5176
bogdanm	82:6473597d706e	5177	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5178	#define HW_ENET_RMON_T_P65TO127(x) ((__I hw_enet_rmon_t_p65to127_t ) HW_ENET_RMON_T_P65TO127_ADDR(x))
bogdanm	82:6473597d706e	5179	#define HW_ENET_RMON_T_P65TO127_RD(x) (HW_ENET_RMON_T_P65TO127(x).U)
bogdanm	82:6473597d706e	5180	#endif
bogdanm	82:6473597d706e	5181	//@}
bogdanm	82:6473597d706e	5182
bogdanm	82:6473597d706e	5183	/*
bogdanm	82:6473597d706e	5184	* Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
bogdanm	82:6473597d706e	5185	*/
bogdanm	82:6473597d706e	5186
bogdanm	82:6473597d706e	5187	/*!
bogdanm	82:6473597d706e	5188	* @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	5189	*/
bogdanm	82:6473597d706e	5190	//@{
bogdanm	82:6473597d706e	5191	#define BP_ENET_RMON_T_P65TO127_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P65TO127_TXPKTS.
bogdanm	82:6473597d706e	5192	#define BM_ENET_RMON_T_P65TO127_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P65TO127_TXPKTS.
bogdanm	82:6473597d706e	5193	#define BS_ENET_RMON_T_P65TO127_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P65TO127_TXPKTS.
bogdanm	82:6473597d706e	5194
bogdanm	82:6473597d706e	5195	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5196	//! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field.
bogdanm	82:6473597d706e	5197	#define BR_ENET_RMON_T_P65TO127_TXPKTS(x) (HW_ENET_RMON_T_P65TO127(x).B.TXPKTS)
bogdanm	82:6473597d706e	5198	#endif
bogdanm	82:6473597d706e	5199	//@}
bogdanm	82:6473597d706e	5200
bogdanm	82:6473597d706e	5201	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5202	// HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
bogdanm	82:6473597d706e	5203	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5204
bogdanm	82:6473597d706e	5205	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5206	/*!
bogdanm	82:6473597d706e	5207	* @brief HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
bogdanm	82:6473597d706e	5208	*
bogdanm	82:6473597d706e	5209	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5210	*/
bogdanm	82:6473597d706e	5211	typedef union _hw_enet_rmon_t_p128to255
bogdanm	82:6473597d706e	5212	{
bogdanm	82:6473597d706e	5213	uint32_t U;
bogdanm	82:6473597d706e	5214	struct _hw_enet_rmon_t_p128to255_bitfields
bogdanm	82:6473597d706e	5215	{
bogdanm	82:6473597d706e	5216	uint32_t TXPKTS : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	5217	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5218	} B;
bogdanm	82:6473597d706e	5219	} hw_enet_rmon_t_p128to255_t;
bogdanm	82:6473597d706e	5220	#endif
bogdanm	82:6473597d706e	5221
bogdanm	82:6473597d706e	5222	/*!
bogdanm	82:6473597d706e	5223	* @name Constants and macros for entire ENET_RMON_T_P128TO255 register
bogdanm	82:6473597d706e	5224	*/
bogdanm	82:6473597d706e	5225	//@{
bogdanm	82:6473597d706e	5226	#define HW_ENET_RMON_T_P128TO255_ADDR(x) (REGS_ENET_BASE(x) + 0x230U)
bogdanm	82:6473597d706e	5227
bogdanm	82:6473597d706e	5228	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5229	#define HW_ENET_RMON_T_P128TO255(x) ((__I hw_enet_rmon_t_p128to255_t ) HW_ENET_RMON_T_P128TO255_ADDR(x))
bogdanm	82:6473597d706e	5230	#define HW_ENET_RMON_T_P128TO255_RD(x) (HW_ENET_RMON_T_P128TO255(x).U)
bogdanm	82:6473597d706e	5231	#endif
bogdanm	82:6473597d706e	5232	//@}
bogdanm	82:6473597d706e	5233
bogdanm	82:6473597d706e	5234	/*
bogdanm	82:6473597d706e	5235	* Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
bogdanm	82:6473597d706e	5236	*/
bogdanm	82:6473597d706e	5237
bogdanm	82:6473597d706e	5238	/*!
bogdanm	82:6473597d706e	5239	* @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	5240	*/
bogdanm	82:6473597d706e	5241	//@{
bogdanm	82:6473597d706e	5242	#define BP_ENET_RMON_T_P128TO255_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P128TO255_TXPKTS.
bogdanm	82:6473597d706e	5243	#define BM_ENET_RMON_T_P128TO255_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P128TO255_TXPKTS.
bogdanm	82:6473597d706e	5244	#define BS_ENET_RMON_T_P128TO255_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P128TO255_TXPKTS.
bogdanm	82:6473597d706e	5245
bogdanm	82:6473597d706e	5246	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5247	//! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field.
bogdanm	82:6473597d706e	5248	#define BR_ENET_RMON_T_P128TO255_TXPKTS(x) (HW_ENET_RMON_T_P128TO255(x).B.TXPKTS)
bogdanm	82:6473597d706e	5249	#endif
bogdanm	82:6473597d706e	5250	//@}
bogdanm	82:6473597d706e	5251
bogdanm	82:6473597d706e	5252	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5253	// HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
bogdanm	82:6473597d706e	5254	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5255
bogdanm	82:6473597d706e	5256	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5257	/*!
bogdanm	82:6473597d706e	5258	* @brief HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
bogdanm	82:6473597d706e	5259	*
bogdanm	82:6473597d706e	5260	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5261	*/
bogdanm	82:6473597d706e	5262	typedef union _hw_enet_rmon_t_p256to511
bogdanm	82:6473597d706e	5263	{
bogdanm	82:6473597d706e	5264	uint32_t U;
bogdanm	82:6473597d706e	5265	struct _hw_enet_rmon_t_p256to511_bitfields
bogdanm	82:6473597d706e	5266	{
bogdanm	82:6473597d706e	5267	uint32_t TXPKTS : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	5268	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5269	} B;
bogdanm	82:6473597d706e	5270	} hw_enet_rmon_t_p256to511_t;
bogdanm	82:6473597d706e	5271	#endif
bogdanm	82:6473597d706e	5272
bogdanm	82:6473597d706e	5273	/*!
bogdanm	82:6473597d706e	5274	* @name Constants and macros for entire ENET_RMON_T_P256TO511 register
bogdanm	82:6473597d706e	5275	*/
bogdanm	82:6473597d706e	5276	//@{
bogdanm	82:6473597d706e	5277	#define HW_ENET_RMON_T_P256TO511_ADDR(x) (REGS_ENET_BASE(x) + 0x234U)
bogdanm	82:6473597d706e	5278
bogdanm	82:6473597d706e	5279	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5280	#define HW_ENET_RMON_T_P256TO511(x) ((__I hw_enet_rmon_t_p256to511_t ) HW_ENET_RMON_T_P256TO511_ADDR(x))
bogdanm	82:6473597d706e	5281	#define HW_ENET_RMON_T_P256TO511_RD(x) (HW_ENET_RMON_T_P256TO511(x).U)
bogdanm	82:6473597d706e	5282	#endif
bogdanm	82:6473597d706e	5283	//@}
bogdanm	82:6473597d706e	5284
bogdanm	82:6473597d706e	5285	/*
bogdanm	82:6473597d706e	5286	* Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
bogdanm	82:6473597d706e	5287	*/
bogdanm	82:6473597d706e	5288
bogdanm	82:6473597d706e	5289	/*!
bogdanm	82:6473597d706e	5290	* @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	5291	*/
bogdanm	82:6473597d706e	5292	//@{
bogdanm	82:6473597d706e	5293	#define BP_ENET_RMON_T_P256TO511_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P256TO511_TXPKTS.
bogdanm	82:6473597d706e	5294	#define BM_ENET_RMON_T_P256TO511_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P256TO511_TXPKTS.
bogdanm	82:6473597d706e	5295	#define BS_ENET_RMON_T_P256TO511_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P256TO511_TXPKTS.
bogdanm	82:6473597d706e	5296
bogdanm	82:6473597d706e	5297	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5298	//! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field.
bogdanm	82:6473597d706e	5299	#define BR_ENET_RMON_T_P256TO511_TXPKTS(x) (HW_ENET_RMON_T_P256TO511(x).B.TXPKTS)
bogdanm	82:6473597d706e	5300	#endif
bogdanm	82:6473597d706e	5301	//@}
bogdanm	82:6473597d706e	5302
bogdanm	82:6473597d706e	5303	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5304	// HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
bogdanm	82:6473597d706e	5305	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5306
bogdanm	82:6473597d706e	5307	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5308	/*!
bogdanm	82:6473597d706e	5309	* @brief HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
bogdanm	82:6473597d706e	5310	*
bogdanm	82:6473597d706e	5311	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5312	*
bogdanm	82:6473597d706e	5313	* .
bogdanm	82:6473597d706e	5314	*/
bogdanm	82:6473597d706e	5315	typedef union _hw_enet_rmon_t_p512to1023
bogdanm	82:6473597d706e	5316	{
bogdanm	82:6473597d706e	5317	uint32_t U;
bogdanm	82:6473597d706e	5318	struct _hw_enet_rmon_t_p512to1023_bitfields
bogdanm	82:6473597d706e	5319	{
bogdanm	82:6473597d706e	5320	uint32_t TXPKTS : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	5321	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5322	} B;
bogdanm	82:6473597d706e	5323	} hw_enet_rmon_t_p512to1023_t;
bogdanm	82:6473597d706e	5324	#endif
bogdanm	82:6473597d706e	5325
bogdanm	82:6473597d706e	5326	/*!
bogdanm	82:6473597d706e	5327	* @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
bogdanm	82:6473597d706e	5328	*/
bogdanm	82:6473597d706e	5329	//@{
bogdanm	82:6473597d706e	5330	#define HW_ENET_RMON_T_P512TO1023_ADDR(x) (REGS_ENET_BASE(x) + 0x238U)
bogdanm	82:6473597d706e	5331
bogdanm	82:6473597d706e	5332	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5333	#define HW_ENET_RMON_T_P512TO1023(x) ((__I hw_enet_rmon_t_p512to1023_t ) HW_ENET_RMON_T_P512TO1023_ADDR(x))
bogdanm	82:6473597d706e	5334	#define HW_ENET_RMON_T_P512TO1023_RD(x) (HW_ENET_RMON_T_P512TO1023(x).U)
bogdanm	82:6473597d706e	5335	#endif
bogdanm	82:6473597d706e	5336	//@}
bogdanm	82:6473597d706e	5337
bogdanm	82:6473597d706e	5338	/*
bogdanm	82:6473597d706e	5339	* Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
bogdanm	82:6473597d706e	5340	*/
bogdanm	82:6473597d706e	5341
bogdanm	82:6473597d706e	5342	/*!
bogdanm	82:6473597d706e	5343	* @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	5344	*/
bogdanm	82:6473597d706e	5345	//@{
bogdanm	82:6473597d706e	5346	#define BP_ENET_RMON_T_P512TO1023_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P512TO1023_TXPKTS.
bogdanm	82:6473597d706e	5347	#define BM_ENET_RMON_T_P512TO1023_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P512TO1023_TXPKTS.
bogdanm	82:6473597d706e	5348	#define BS_ENET_RMON_T_P512TO1023_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P512TO1023_TXPKTS.
bogdanm	82:6473597d706e	5349
bogdanm	82:6473597d706e	5350	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5351	//! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field.
bogdanm	82:6473597d706e	5352	#define BR_ENET_RMON_T_P512TO1023_TXPKTS(x) (HW_ENET_RMON_T_P512TO1023(x).B.TXPKTS)
bogdanm	82:6473597d706e	5353	#endif
bogdanm	82:6473597d706e	5354	//@}
bogdanm	82:6473597d706e	5355
bogdanm	82:6473597d706e	5356	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5357	// HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
bogdanm	82:6473597d706e	5358	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5359
bogdanm	82:6473597d706e	5360	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5361	/*!
bogdanm	82:6473597d706e	5362	* @brief HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
bogdanm	82:6473597d706e	5363	*
bogdanm	82:6473597d706e	5364	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5365	*/
bogdanm	82:6473597d706e	5366	typedef union _hw_enet_rmon_t_p1024to2047
bogdanm	82:6473597d706e	5367	{
bogdanm	82:6473597d706e	5368	uint32_t U;
bogdanm	82:6473597d706e	5369	struct _hw_enet_rmon_t_p1024to2047_bitfields
bogdanm	82:6473597d706e	5370	{
bogdanm	82:6473597d706e	5371	uint32_t TXPKTS : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	5372	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5373	} B;
bogdanm	82:6473597d706e	5374	} hw_enet_rmon_t_p1024to2047_t;
bogdanm	82:6473597d706e	5375	#endif
bogdanm	82:6473597d706e	5376
bogdanm	82:6473597d706e	5377	/*!
bogdanm	82:6473597d706e	5378	* @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
bogdanm	82:6473597d706e	5379	*/
bogdanm	82:6473597d706e	5380	//@{
bogdanm	82:6473597d706e	5381	#define HW_ENET_RMON_T_P1024TO2047_ADDR(x) (REGS_ENET_BASE(x) + 0x23CU)
bogdanm	82:6473597d706e	5382
bogdanm	82:6473597d706e	5383	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5384	#define HW_ENET_RMON_T_P1024TO2047(x) ((__I hw_enet_rmon_t_p1024to2047_t ) HW_ENET_RMON_T_P1024TO2047_ADDR(x))
bogdanm	82:6473597d706e	5385	#define HW_ENET_RMON_T_P1024TO2047_RD(x) (HW_ENET_RMON_T_P1024TO2047(x).U)
bogdanm	82:6473597d706e	5386	#endif
bogdanm	82:6473597d706e	5387	//@}
bogdanm	82:6473597d706e	5388
bogdanm	82:6473597d706e	5389	/*
bogdanm	82:6473597d706e	5390	* Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
bogdanm	82:6473597d706e	5391	*/
bogdanm	82:6473597d706e	5392
bogdanm	82:6473597d706e	5393	/*!
bogdanm	82:6473597d706e	5394	* @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	5395	*/
bogdanm	82:6473597d706e	5396	//@{
bogdanm	82:6473597d706e	5397	#define BP_ENET_RMON_T_P1024TO2047_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P1024TO2047_TXPKTS.
bogdanm	82:6473597d706e	5398	#define BM_ENET_RMON_T_P1024TO2047_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P1024TO2047_TXPKTS.
bogdanm	82:6473597d706e	5399	#define BS_ENET_RMON_T_P1024TO2047_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P1024TO2047_TXPKTS.
bogdanm	82:6473597d706e	5400
bogdanm	82:6473597d706e	5401	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5402	//! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field.
bogdanm	82:6473597d706e	5403	#define BR_ENET_RMON_T_P1024TO2047_TXPKTS(x) (HW_ENET_RMON_T_P1024TO2047(x).B.TXPKTS)
bogdanm	82:6473597d706e	5404	#endif
bogdanm	82:6473597d706e	5405	//@}
bogdanm	82:6473597d706e	5406
bogdanm	82:6473597d706e	5407	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5408	// HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
bogdanm	82:6473597d706e	5409	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5410
bogdanm	82:6473597d706e	5411	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5412	/*!
bogdanm	82:6473597d706e	5413	* @brief HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
bogdanm	82:6473597d706e	5414	*
bogdanm	82:6473597d706e	5415	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5416	*/
bogdanm	82:6473597d706e	5417	typedef union _hw_enet_rmon_t_p_gte2048
bogdanm	82:6473597d706e	5418	{
bogdanm	82:6473597d706e	5419	uint32_t U;
bogdanm	82:6473597d706e	5420	struct _hw_enet_rmon_t_p_gte2048_bitfields
bogdanm	82:6473597d706e	5421	{
bogdanm	82:6473597d706e	5422	uint32_t TXPKTS : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	5423	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5424	} B;
bogdanm	82:6473597d706e	5425	} hw_enet_rmon_t_p_gte2048_t;
bogdanm	82:6473597d706e	5426	#endif
bogdanm	82:6473597d706e	5427
bogdanm	82:6473597d706e	5428	/*!
bogdanm	82:6473597d706e	5429	* @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
bogdanm	82:6473597d706e	5430	*/
bogdanm	82:6473597d706e	5431	//@{
bogdanm	82:6473597d706e	5432	#define HW_ENET_RMON_T_P_GTE2048_ADDR(x) (REGS_ENET_BASE(x) + 0x240U)
bogdanm	82:6473597d706e	5433
bogdanm	82:6473597d706e	5434	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5435	#define HW_ENET_RMON_T_P_GTE2048(x) ((__I hw_enet_rmon_t_p_gte2048_t ) HW_ENET_RMON_T_P_GTE2048_ADDR(x))
bogdanm	82:6473597d706e	5436	#define HW_ENET_RMON_T_P_GTE2048_RD(x) (HW_ENET_RMON_T_P_GTE2048(x).U)
bogdanm	82:6473597d706e	5437	#endif
bogdanm	82:6473597d706e	5438	//@}
bogdanm	82:6473597d706e	5439
bogdanm	82:6473597d706e	5440	/*
bogdanm	82:6473597d706e	5441	* Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
bogdanm	82:6473597d706e	5442	*/
bogdanm	82:6473597d706e	5443
bogdanm	82:6473597d706e	5444	/*!
bogdanm	82:6473597d706e	5445	* @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
bogdanm	82:6473597d706e	5446	*/
bogdanm	82:6473597d706e	5447	//@{
bogdanm	82:6473597d706e	5448	#define BP_ENET_RMON_T_P_GTE2048_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P_GTE2048_TXPKTS.
bogdanm	82:6473597d706e	5449	#define BM_ENET_RMON_T_P_GTE2048_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P_GTE2048_TXPKTS.
bogdanm	82:6473597d706e	5450	#define BS_ENET_RMON_T_P_GTE2048_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P_GTE2048_TXPKTS.
bogdanm	82:6473597d706e	5451
bogdanm	82:6473597d706e	5452	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5453	//! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field.
bogdanm	82:6473597d706e	5454	#define BR_ENET_RMON_T_P_GTE2048_TXPKTS(x) (HW_ENET_RMON_T_P_GTE2048(x).B.TXPKTS)
bogdanm	82:6473597d706e	5455	#endif
bogdanm	82:6473597d706e	5456	//@}
bogdanm	82:6473597d706e	5457
bogdanm	82:6473597d706e	5458	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5459	// HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
bogdanm	82:6473597d706e	5460	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5461
bogdanm	82:6473597d706e	5462	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5463	/*!
bogdanm	82:6473597d706e	5464	* @brief HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
bogdanm	82:6473597d706e	5465	*
bogdanm	82:6473597d706e	5466	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5467	*/
bogdanm	82:6473597d706e	5468	typedef union _hw_enet_rmon_t_octets
bogdanm	82:6473597d706e	5469	{
bogdanm	82:6473597d706e	5470	uint32_t U;
bogdanm	82:6473597d706e	5471	struct _hw_enet_rmon_t_octets_bitfields
bogdanm	82:6473597d706e	5472	{
bogdanm	82:6473597d706e	5473	uint32_t TXOCTS : 32; //!< [31:0] Octet count
bogdanm	82:6473597d706e	5474	} B;
bogdanm	82:6473597d706e	5475	} hw_enet_rmon_t_octets_t;
bogdanm	82:6473597d706e	5476	#endif
bogdanm	82:6473597d706e	5477
bogdanm	82:6473597d706e	5478	/*!
bogdanm	82:6473597d706e	5479	* @name Constants and macros for entire ENET_RMON_T_OCTETS register
bogdanm	82:6473597d706e	5480	*/
bogdanm	82:6473597d706e	5481	//@{
bogdanm	82:6473597d706e	5482	#define HW_ENET_RMON_T_OCTETS_ADDR(x) (REGS_ENET_BASE(x) + 0x244U)
bogdanm	82:6473597d706e	5483
bogdanm	82:6473597d706e	5484	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5485	#define HW_ENET_RMON_T_OCTETS(x) ((__I hw_enet_rmon_t_octets_t ) HW_ENET_RMON_T_OCTETS_ADDR(x))
bogdanm	82:6473597d706e	5486	#define HW_ENET_RMON_T_OCTETS_RD(x) (HW_ENET_RMON_T_OCTETS(x).U)
bogdanm	82:6473597d706e	5487	#endif
bogdanm	82:6473597d706e	5488	//@}
bogdanm	82:6473597d706e	5489
bogdanm	82:6473597d706e	5490	/*
bogdanm	82:6473597d706e	5491	* Constants & macros for individual ENET_RMON_T_OCTETS bitfields
bogdanm	82:6473597d706e	5492	*/
bogdanm	82:6473597d706e	5493
bogdanm	82:6473597d706e	5494	/*!
bogdanm	82:6473597d706e	5495	* @name Register ENET_RMON_T_OCTETS, field TXOCTS[31:0] (RO)
bogdanm	82:6473597d706e	5496	*/
bogdanm	82:6473597d706e	5497	//@{
bogdanm	82:6473597d706e	5498	#define BP_ENET_RMON_T_OCTETS_TXOCTS (0U) //!< Bit position for ENET_RMON_T_OCTETS_TXOCTS.
bogdanm	82:6473597d706e	5499	#define BM_ENET_RMON_T_OCTETS_TXOCTS (0xFFFFFFFFU) //!< Bit mask for ENET_RMON_T_OCTETS_TXOCTS.
bogdanm	82:6473597d706e	5500	#define BS_ENET_RMON_T_OCTETS_TXOCTS (32U) //!< Bit field size in bits for ENET_RMON_T_OCTETS_TXOCTS.
bogdanm	82:6473597d706e	5501
bogdanm	82:6473597d706e	5502	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5503	//! @brief Read current value of the ENET_RMON_T_OCTETS_TXOCTS field.
bogdanm	82:6473597d706e	5504	#define BR_ENET_RMON_T_OCTETS_TXOCTS(x) (HW_ENET_RMON_T_OCTETS(x).U)
bogdanm	82:6473597d706e	5505	#endif
bogdanm	82:6473597d706e	5506	//@}
bogdanm	82:6473597d706e	5507
bogdanm	82:6473597d706e	5508	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5509	// HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
bogdanm	82:6473597d706e	5510	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5511
bogdanm	82:6473597d706e	5512	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5513	/*!
bogdanm	82:6473597d706e	5514	* @brief HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
bogdanm	82:6473597d706e	5515	*
bogdanm	82:6473597d706e	5516	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5517	*/
bogdanm	82:6473597d706e	5518	typedef union _hw_enet_ieee_t_frame_ok
bogdanm	82:6473597d706e	5519	{
bogdanm	82:6473597d706e	5520	uint32_t U;
bogdanm	82:6473597d706e	5521	struct _hw_enet_ieee_t_frame_ok_bitfields
bogdanm	82:6473597d706e	5522	{
bogdanm	82:6473597d706e	5523	uint32_t COUNT : 16; //!< [15:0] Frame count
bogdanm	82:6473597d706e	5524	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5525	} B;
bogdanm	82:6473597d706e	5526	} hw_enet_ieee_t_frame_ok_t;
bogdanm	82:6473597d706e	5527	#endif
bogdanm	82:6473597d706e	5528
bogdanm	82:6473597d706e	5529	/*!
bogdanm	82:6473597d706e	5530	* @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
bogdanm	82:6473597d706e	5531	*/
bogdanm	82:6473597d706e	5532	//@{
bogdanm	82:6473597d706e	5533	#define HW_ENET_IEEE_T_FRAME_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x24CU)
bogdanm	82:6473597d706e	5534
bogdanm	82:6473597d706e	5535	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5536	#define HW_ENET_IEEE_T_FRAME_OK(x) ((__I hw_enet_ieee_t_frame_ok_t ) HW_ENET_IEEE_T_FRAME_OK_ADDR(x))
bogdanm	82:6473597d706e	5537	#define HW_ENET_IEEE_T_FRAME_OK_RD(x) (HW_ENET_IEEE_T_FRAME_OK(x).U)
bogdanm	82:6473597d706e	5538	#endif
bogdanm	82:6473597d706e	5539	//@}
bogdanm	82:6473597d706e	5540
bogdanm	82:6473597d706e	5541	/*
bogdanm	82:6473597d706e	5542	* Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
bogdanm	82:6473597d706e	5543	*/
bogdanm	82:6473597d706e	5544
bogdanm	82:6473597d706e	5545	/*!
bogdanm	82:6473597d706e	5546	* @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	5547	*/
bogdanm	82:6473597d706e	5548	//@{
bogdanm	82:6473597d706e	5549	#define BP_ENET_IEEE_T_FRAME_OK_COUNT (0U) //!< Bit position for ENET_IEEE_T_FRAME_OK_COUNT.
bogdanm	82:6473597d706e	5550	#define BM_ENET_IEEE_T_FRAME_OK_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_FRAME_OK_COUNT.
bogdanm	82:6473597d706e	5551	#define BS_ENET_IEEE_T_FRAME_OK_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_FRAME_OK_COUNT.
bogdanm	82:6473597d706e	5552
bogdanm	82:6473597d706e	5553	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5554	//! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field.
bogdanm	82:6473597d706e	5555	#define BR_ENET_IEEE_T_FRAME_OK_COUNT(x) (HW_ENET_IEEE_T_FRAME_OK(x).B.COUNT)
bogdanm	82:6473597d706e	5556	#endif
bogdanm	82:6473597d706e	5557	//@}
bogdanm	82:6473597d706e	5558
bogdanm	82:6473597d706e	5559	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5560	// HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
bogdanm	82:6473597d706e	5561	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5562
bogdanm	82:6473597d706e	5563	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5564	/*!
bogdanm	82:6473597d706e	5565	* @brief HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
bogdanm	82:6473597d706e	5566	*
bogdanm	82:6473597d706e	5567	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5568	*/
bogdanm	82:6473597d706e	5569	typedef union _hw_enet_ieee_t_1col
bogdanm	82:6473597d706e	5570	{
bogdanm	82:6473597d706e	5571	uint32_t U;
bogdanm	82:6473597d706e	5572	struct _hw_enet_ieee_t_1col_bitfields
bogdanm	82:6473597d706e	5573	{
bogdanm	82:6473597d706e	5574	uint32_t COUNT : 16; //!< [15:0] Frame count
bogdanm	82:6473597d706e	5575	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5576	} B;
bogdanm	82:6473597d706e	5577	} hw_enet_ieee_t_1col_t;
bogdanm	82:6473597d706e	5578	#endif
bogdanm	82:6473597d706e	5579
bogdanm	82:6473597d706e	5580	/*!
bogdanm	82:6473597d706e	5581	* @name Constants and macros for entire ENET_IEEE_T_1COL register
bogdanm	82:6473597d706e	5582	*/
bogdanm	82:6473597d706e	5583	//@{
bogdanm	82:6473597d706e	5584	#define HW_ENET_IEEE_T_1COL_ADDR(x) (REGS_ENET_BASE(x) + 0x250U)
bogdanm	82:6473597d706e	5585
bogdanm	82:6473597d706e	5586	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5587	#define HW_ENET_IEEE_T_1COL(x) ((__I hw_enet_ieee_t_1col_t ) HW_ENET_IEEE_T_1COL_ADDR(x))
bogdanm	82:6473597d706e	5588	#define HW_ENET_IEEE_T_1COL_RD(x) (HW_ENET_IEEE_T_1COL(x).U)
bogdanm	82:6473597d706e	5589	#endif
bogdanm	82:6473597d706e	5590	//@}
bogdanm	82:6473597d706e	5591
bogdanm	82:6473597d706e	5592	/*
bogdanm	82:6473597d706e	5593	* Constants & macros for individual ENET_IEEE_T_1COL bitfields
bogdanm	82:6473597d706e	5594	*/
bogdanm	82:6473597d706e	5595
bogdanm	82:6473597d706e	5596	/*!
bogdanm	82:6473597d706e	5597	* @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	5598	*/
bogdanm	82:6473597d706e	5599	//@{
bogdanm	82:6473597d706e	5600	#define BP_ENET_IEEE_T_1COL_COUNT (0U) //!< Bit position for ENET_IEEE_T_1COL_COUNT.
bogdanm	82:6473597d706e	5601	#define BM_ENET_IEEE_T_1COL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_1COL_COUNT.
bogdanm	82:6473597d706e	5602	#define BS_ENET_IEEE_T_1COL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_1COL_COUNT.
bogdanm	82:6473597d706e	5603
bogdanm	82:6473597d706e	5604	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5605	//! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field.
bogdanm	82:6473597d706e	5606	#define BR_ENET_IEEE_T_1COL_COUNT(x) (HW_ENET_IEEE_T_1COL(x).B.COUNT)
bogdanm	82:6473597d706e	5607	#endif
bogdanm	82:6473597d706e	5608	//@}
bogdanm	82:6473597d706e	5609
bogdanm	82:6473597d706e	5610	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5611	// HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
bogdanm	82:6473597d706e	5612	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5613
bogdanm	82:6473597d706e	5614	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5615	/*!
bogdanm	82:6473597d706e	5616	* @brief HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
bogdanm	82:6473597d706e	5617	*
bogdanm	82:6473597d706e	5618	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5619	*/
bogdanm	82:6473597d706e	5620	typedef union _hw_enet_ieee_t_mcol
bogdanm	82:6473597d706e	5621	{
bogdanm	82:6473597d706e	5622	uint32_t U;
bogdanm	82:6473597d706e	5623	struct _hw_enet_ieee_t_mcol_bitfields
bogdanm	82:6473597d706e	5624	{
bogdanm	82:6473597d706e	5625	uint32_t COUNT : 16; //!< [15:0] Frame count
bogdanm	82:6473597d706e	5626	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5627	} B;
bogdanm	82:6473597d706e	5628	} hw_enet_ieee_t_mcol_t;
bogdanm	82:6473597d706e	5629	#endif
bogdanm	82:6473597d706e	5630
bogdanm	82:6473597d706e	5631	/*!
bogdanm	82:6473597d706e	5632	* @name Constants and macros for entire ENET_IEEE_T_MCOL register
bogdanm	82:6473597d706e	5633	*/
bogdanm	82:6473597d706e	5634	//@{
bogdanm	82:6473597d706e	5635	#define HW_ENET_IEEE_T_MCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x254U)
bogdanm	82:6473597d706e	5636
bogdanm	82:6473597d706e	5637	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5638	#define HW_ENET_IEEE_T_MCOL(x) ((__I hw_enet_ieee_t_mcol_t ) HW_ENET_IEEE_T_MCOL_ADDR(x))
bogdanm	82:6473597d706e	5639	#define HW_ENET_IEEE_T_MCOL_RD(x) (HW_ENET_IEEE_T_MCOL(x).U)
bogdanm	82:6473597d706e	5640	#endif
bogdanm	82:6473597d706e	5641	//@}
bogdanm	82:6473597d706e	5642
bogdanm	82:6473597d706e	5643	/*
bogdanm	82:6473597d706e	5644	* Constants & macros for individual ENET_IEEE_T_MCOL bitfields
bogdanm	82:6473597d706e	5645	*/
bogdanm	82:6473597d706e	5646
bogdanm	82:6473597d706e	5647	/*!
bogdanm	82:6473597d706e	5648	* @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	5649	*/
bogdanm	82:6473597d706e	5650	//@{
bogdanm	82:6473597d706e	5651	#define BP_ENET_IEEE_T_MCOL_COUNT (0U) //!< Bit position for ENET_IEEE_T_MCOL_COUNT.
bogdanm	82:6473597d706e	5652	#define BM_ENET_IEEE_T_MCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_MCOL_COUNT.
bogdanm	82:6473597d706e	5653	#define BS_ENET_IEEE_T_MCOL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_MCOL_COUNT.
bogdanm	82:6473597d706e	5654
bogdanm	82:6473597d706e	5655	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5656	//! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field.
bogdanm	82:6473597d706e	5657	#define BR_ENET_IEEE_T_MCOL_COUNT(x) (HW_ENET_IEEE_T_MCOL(x).B.COUNT)
bogdanm	82:6473597d706e	5658	#endif
bogdanm	82:6473597d706e	5659	//@}
bogdanm	82:6473597d706e	5660
bogdanm	82:6473597d706e	5661	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5662	// HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
bogdanm	82:6473597d706e	5663	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5664
bogdanm	82:6473597d706e	5665	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5666	/*!
bogdanm	82:6473597d706e	5667	* @brief HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
bogdanm	82:6473597d706e	5668	*
bogdanm	82:6473597d706e	5669	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5670	*/
bogdanm	82:6473597d706e	5671	typedef union _hw_enet_ieee_t_def
bogdanm	82:6473597d706e	5672	{
bogdanm	82:6473597d706e	5673	uint32_t U;
bogdanm	82:6473597d706e	5674	struct _hw_enet_ieee_t_def_bitfields
bogdanm	82:6473597d706e	5675	{
bogdanm	82:6473597d706e	5676	uint32_t COUNT : 16; //!< [15:0] Frame count
bogdanm	82:6473597d706e	5677	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5678	} B;
bogdanm	82:6473597d706e	5679	} hw_enet_ieee_t_def_t;
bogdanm	82:6473597d706e	5680	#endif
bogdanm	82:6473597d706e	5681
bogdanm	82:6473597d706e	5682	/*!
bogdanm	82:6473597d706e	5683	* @name Constants and macros for entire ENET_IEEE_T_DEF register
bogdanm	82:6473597d706e	5684	*/
bogdanm	82:6473597d706e	5685	//@{
bogdanm	82:6473597d706e	5686	#define HW_ENET_IEEE_T_DEF_ADDR(x) (REGS_ENET_BASE(x) + 0x258U)
bogdanm	82:6473597d706e	5687
bogdanm	82:6473597d706e	5688	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5689	#define HW_ENET_IEEE_T_DEF(x) ((__I hw_enet_ieee_t_def_t ) HW_ENET_IEEE_T_DEF_ADDR(x))
bogdanm	82:6473597d706e	5690	#define HW_ENET_IEEE_T_DEF_RD(x) (HW_ENET_IEEE_T_DEF(x).U)
bogdanm	82:6473597d706e	5691	#endif
bogdanm	82:6473597d706e	5692	//@}
bogdanm	82:6473597d706e	5693
bogdanm	82:6473597d706e	5694	/*
bogdanm	82:6473597d706e	5695	* Constants & macros for individual ENET_IEEE_T_DEF bitfields
bogdanm	82:6473597d706e	5696	*/
bogdanm	82:6473597d706e	5697
bogdanm	82:6473597d706e	5698	/*!
bogdanm	82:6473597d706e	5699	* @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	5700	*/
bogdanm	82:6473597d706e	5701	//@{
bogdanm	82:6473597d706e	5702	#define BP_ENET_IEEE_T_DEF_COUNT (0U) //!< Bit position for ENET_IEEE_T_DEF_COUNT.
bogdanm	82:6473597d706e	5703	#define BM_ENET_IEEE_T_DEF_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_DEF_COUNT.
bogdanm	82:6473597d706e	5704	#define BS_ENET_IEEE_T_DEF_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_DEF_COUNT.
bogdanm	82:6473597d706e	5705
bogdanm	82:6473597d706e	5706	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5707	//! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field.
bogdanm	82:6473597d706e	5708	#define BR_ENET_IEEE_T_DEF_COUNT(x) (HW_ENET_IEEE_T_DEF(x).B.COUNT)
bogdanm	82:6473597d706e	5709	#endif
bogdanm	82:6473597d706e	5710	//@}
bogdanm	82:6473597d706e	5711
bogdanm	82:6473597d706e	5712	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5713	// HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
bogdanm	82:6473597d706e	5714	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5715
bogdanm	82:6473597d706e	5716	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5717	/*!
bogdanm	82:6473597d706e	5718	* @brief HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
bogdanm	82:6473597d706e	5719	*
bogdanm	82:6473597d706e	5720	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5721	*/
bogdanm	82:6473597d706e	5722	typedef union _hw_enet_ieee_t_lcol
bogdanm	82:6473597d706e	5723	{
bogdanm	82:6473597d706e	5724	uint32_t U;
bogdanm	82:6473597d706e	5725	struct _hw_enet_ieee_t_lcol_bitfields
bogdanm	82:6473597d706e	5726	{
bogdanm	82:6473597d706e	5727	uint32_t COUNT : 16; //!< [15:0] Frame count
bogdanm	82:6473597d706e	5728	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5729	} B;
bogdanm	82:6473597d706e	5730	} hw_enet_ieee_t_lcol_t;
bogdanm	82:6473597d706e	5731	#endif
bogdanm	82:6473597d706e	5732
bogdanm	82:6473597d706e	5733	/*!
bogdanm	82:6473597d706e	5734	* @name Constants and macros for entire ENET_IEEE_T_LCOL register
bogdanm	82:6473597d706e	5735	*/
bogdanm	82:6473597d706e	5736	//@{
bogdanm	82:6473597d706e	5737	#define HW_ENET_IEEE_T_LCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x25CU)
bogdanm	82:6473597d706e	5738
bogdanm	82:6473597d706e	5739	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5740	#define HW_ENET_IEEE_T_LCOL(x) ((__I hw_enet_ieee_t_lcol_t ) HW_ENET_IEEE_T_LCOL_ADDR(x))
bogdanm	82:6473597d706e	5741	#define HW_ENET_IEEE_T_LCOL_RD(x) (HW_ENET_IEEE_T_LCOL(x).U)
bogdanm	82:6473597d706e	5742	#endif
bogdanm	82:6473597d706e	5743	//@}
bogdanm	82:6473597d706e	5744
bogdanm	82:6473597d706e	5745	/*
bogdanm	82:6473597d706e	5746	* Constants & macros for individual ENET_IEEE_T_LCOL bitfields
bogdanm	82:6473597d706e	5747	*/
bogdanm	82:6473597d706e	5748
bogdanm	82:6473597d706e	5749	/*!
bogdanm	82:6473597d706e	5750	* @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	5751	*/
bogdanm	82:6473597d706e	5752	//@{
bogdanm	82:6473597d706e	5753	#define BP_ENET_IEEE_T_LCOL_COUNT (0U) //!< Bit position for ENET_IEEE_T_LCOL_COUNT.
bogdanm	82:6473597d706e	5754	#define BM_ENET_IEEE_T_LCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_LCOL_COUNT.
bogdanm	82:6473597d706e	5755	#define BS_ENET_IEEE_T_LCOL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_LCOL_COUNT.
bogdanm	82:6473597d706e	5756
bogdanm	82:6473597d706e	5757	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5758	//! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field.
bogdanm	82:6473597d706e	5759	#define BR_ENET_IEEE_T_LCOL_COUNT(x) (HW_ENET_IEEE_T_LCOL(x).B.COUNT)
bogdanm	82:6473597d706e	5760	#endif
bogdanm	82:6473597d706e	5761	//@}
bogdanm	82:6473597d706e	5762
bogdanm	82:6473597d706e	5763	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5764	// HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
bogdanm	82:6473597d706e	5765	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5766
bogdanm	82:6473597d706e	5767	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5768	/*!
bogdanm	82:6473597d706e	5769	* @brief HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
bogdanm	82:6473597d706e	5770	*
bogdanm	82:6473597d706e	5771	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5772	*/
bogdanm	82:6473597d706e	5773	typedef union _hw_enet_ieee_t_excol
bogdanm	82:6473597d706e	5774	{
bogdanm	82:6473597d706e	5775	uint32_t U;
bogdanm	82:6473597d706e	5776	struct _hw_enet_ieee_t_excol_bitfields
bogdanm	82:6473597d706e	5777	{
bogdanm	82:6473597d706e	5778	uint32_t COUNT : 16; //!< [15:0] Frame count
bogdanm	82:6473597d706e	5779	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5780	} B;
bogdanm	82:6473597d706e	5781	} hw_enet_ieee_t_excol_t;
bogdanm	82:6473597d706e	5782	#endif
bogdanm	82:6473597d706e	5783
bogdanm	82:6473597d706e	5784	/*!
bogdanm	82:6473597d706e	5785	* @name Constants and macros for entire ENET_IEEE_T_EXCOL register
bogdanm	82:6473597d706e	5786	*/
bogdanm	82:6473597d706e	5787	//@{
bogdanm	82:6473597d706e	5788	#define HW_ENET_IEEE_T_EXCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x260U)
bogdanm	82:6473597d706e	5789
bogdanm	82:6473597d706e	5790	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5791	#define HW_ENET_IEEE_T_EXCOL(x) ((__I hw_enet_ieee_t_excol_t ) HW_ENET_IEEE_T_EXCOL_ADDR(x))
bogdanm	82:6473597d706e	5792	#define HW_ENET_IEEE_T_EXCOL_RD(x) (HW_ENET_IEEE_T_EXCOL(x).U)
bogdanm	82:6473597d706e	5793	#endif
bogdanm	82:6473597d706e	5794	//@}
bogdanm	82:6473597d706e	5795
bogdanm	82:6473597d706e	5796	/*
bogdanm	82:6473597d706e	5797	* Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
bogdanm	82:6473597d706e	5798	*/
bogdanm	82:6473597d706e	5799
bogdanm	82:6473597d706e	5800	/*!
bogdanm	82:6473597d706e	5801	* @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	5802	*/
bogdanm	82:6473597d706e	5803	//@{
bogdanm	82:6473597d706e	5804	#define BP_ENET_IEEE_T_EXCOL_COUNT (0U) //!< Bit position for ENET_IEEE_T_EXCOL_COUNT.
bogdanm	82:6473597d706e	5805	#define BM_ENET_IEEE_T_EXCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_EXCOL_COUNT.
bogdanm	82:6473597d706e	5806	#define BS_ENET_IEEE_T_EXCOL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_EXCOL_COUNT.
bogdanm	82:6473597d706e	5807
bogdanm	82:6473597d706e	5808	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5809	//! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field.
bogdanm	82:6473597d706e	5810	#define BR_ENET_IEEE_T_EXCOL_COUNT(x) (HW_ENET_IEEE_T_EXCOL(x).B.COUNT)
bogdanm	82:6473597d706e	5811	#endif
bogdanm	82:6473597d706e	5812	//@}
bogdanm	82:6473597d706e	5813
bogdanm	82:6473597d706e	5814	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5815	// HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
bogdanm	82:6473597d706e	5816	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5817
bogdanm	82:6473597d706e	5818	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5819	/*!
bogdanm	82:6473597d706e	5820	* @brief HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
bogdanm	82:6473597d706e	5821	*
bogdanm	82:6473597d706e	5822	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5823	*/
bogdanm	82:6473597d706e	5824	typedef union _hw_enet_ieee_t_macerr
bogdanm	82:6473597d706e	5825	{
bogdanm	82:6473597d706e	5826	uint32_t U;
bogdanm	82:6473597d706e	5827	struct _hw_enet_ieee_t_macerr_bitfields
bogdanm	82:6473597d706e	5828	{
bogdanm	82:6473597d706e	5829	uint32_t COUNT : 16; //!< [15:0] Frame count
bogdanm	82:6473597d706e	5830	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5831	} B;
bogdanm	82:6473597d706e	5832	} hw_enet_ieee_t_macerr_t;
bogdanm	82:6473597d706e	5833	#endif
bogdanm	82:6473597d706e	5834
bogdanm	82:6473597d706e	5835	/*!
bogdanm	82:6473597d706e	5836	* @name Constants and macros for entire ENET_IEEE_T_MACERR register
bogdanm	82:6473597d706e	5837	*/
bogdanm	82:6473597d706e	5838	//@{
bogdanm	82:6473597d706e	5839	#define HW_ENET_IEEE_T_MACERR_ADDR(x) (REGS_ENET_BASE(x) + 0x264U)
bogdanm	82:6473597d706e	5840
bogdanm	82:6473597d706e	5841	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5842	#define HW_ENET_IEEE_T_MACERR(x) ((__I hw_enet_ieee_t_macerr_t ) HW_ENET_IEEE_T_MACERR_ADDR(x))
bogdanm	82:6473597d706e	5843	#define HW_ENET_IEEE_T_MACERR_RD(x) (HW_ENET_IEEE_T_MACERR(x).U)
bogdanm	82:6473597d706e	5844	#endif
bogdanm	82:6473597d706e	5845	//@}
bogdanm	82:6473597d706e	5846
bogdanm	82:6473597d706e	5847	/*
bogdanm	82:6473597d706e	5848	* Constants & macros for individual ENET_IEEE_T_MACERR bitfields
bogdanm	82:6473597d706e	5849	*/
bogdanm	82:6473597d706e	5850
bogdanm	82:6473597d706e	5851	/*!
bogdanm	82:6473597d706e	5852	* @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	5853	*/
bogdanm	82:6473597d706e	5854	//@{
bogdanm	82:6473597d706e	5855	#define BP_ENET_IEEE_T_MACERR_COUNT (0U) //!< Bit position for ENET_IEEE_T_MACERR_COUNT.
bogdanm	82:6473597d706e	5856	#define BM_ENET_IEEE_T_MACERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_MACERR_COUNT.
bogdanm	82:6473597d706e	5857	#define BS_ENET_IEEE_T_MACERR_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_MACERR_COUNT.
bogdanm	82:6473597d706e	5858
bogdanm	82:6473597d706e	5859	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5860	//! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field.
bogdanm	82:6473597d706e	5861	#define BR_ENET_IEEE_T_MACERR_COUNT(x) (HW_ENET_IEEE_T_MACERR(x).B.COUNT)
bogdanm	82:6473597d706e	5862	#endif
bogdanm	82:6473597d706e	5863	//@}
bogdanm	82:6473597d706e	5864
bogdanm	82:6473597d706e	5865	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5866	// HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
bogdanm	82:6473597d706e	5867	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5868
bogdanm	82:6473597d706e	5869	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5870	/*!
bogdanm	82:6473597d706e	5871	* @brief HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
bogdanm	82:6473597d706e	5872	*
bogdanm	82:6473597d706e	5873	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5874	*/
bogdanm	82:6473597d706e	5875	typedef union _hw_enet_ieee_t_cserr
bogdanm	82:6473597d706e	5876	{
bogdanm	82:6473597d706e	5877	uint32_t U;
bogdanm	82:6473597d706e	5878	struct _hw_enet_ieee_t_cserr_bitfields
bogdanm	82:6473597d706e	5879	{
bogdanm	82:6473597d706e	5880	uint32_t COUNT : 16; //!< [15:0] Frame count
bogdanm	82:6473597d706e	5881	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5882	} B;
bogdanm	82:6473597d706e	5883	} hw_enet_ieee_t_cserr_t;
bogdanm	82:6473597d706e	5884	#endif
bogdanm	82:6473597d706e	5885
bogdanm	82:6473597d706e	5886	/*!
bogdanm	82:6473597d706e	5887	* @name Constants and macros for entire ENET_IEEE_T_CSERR register
bogdanm	82:6473597d706e	5888	*/
bogdanm	82:6473597d706e	5889	//@{
bogdanm	82:6473597d706e	5890	#define HW_ENET_IEEE_T_CSERR_ADDR(x) (REGS_ENET_BASE(x) + 0x268U)
bogdanm	82:6473597d706e	5891
bogdanm	82:6473597d706e	5892	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5893	#define HW_ENET_IEEE_T_CSERR(x) ((__I hw_enet_ieee_t_cserr_t ) HW_ENET_IEEE_T_CSERR_ADDR(x))
bogdanm	82:6473597d706e	5894	#define HW_ENET_IEEE_T_CSERR_RD(x) (HW_ENET_IEEE_T_CSERR(x).U)
bogdanm	82:6473597d706e	5895	#endif
bogdanm	82:6473597d706e	5896	//@}
bogdanm	82:6473597d706e	5897
bogdanm	82:6473597d706e	5898	/*
bogdanm	82:6473597d706e	5899	* Constants & macros for individual ENET_IEEE_T_CSERR bitfields
bogdanm	82:6473597d706e	5900	*/
bogdanm	82:6473597d706e	5901
bogdanm	82:6473597d706e	5902	/*!
bogdanm	82:6473597d706e	5903	* @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	5904	*/
bogdanm	82:6473597d706e	5905	//@{
bogdanm	82:6473597d706e	5906	#define BP_ENET_IEEE_T_CSERR_COUNT (0U) //!< Bit position for ENET_IEEE_T_CSERR_COUNT.
bogdanm	82:6473597d706e	5907	#define BM_ENET_IEEE_T_CSERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_CSERR_COUNT.
bogdanm	82:6473597d706e	5908	#define BS_ENET_IEEE_T_CSERR_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_CSERR_COUNT.
bogdanm	82:6473597d706e	5909
bogdanm	82:6473597d706e	5910	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5911	//! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field.
bogdanm	82:6473597d706e	5912	#define BR_ENET_IEEE_T_CSERR_COUNT(x) (HW_ENET_IEEE_T_CSERR(x).B.COUNT)
bogdanm	82:6473597d706e	5913	#endif
bogdanm	82:6473597d706e	5914	//@}
bogdanm	82:6473597d706e	5915
bogdanm	82:6473597d706e	5916	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5917	// HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
bogdanm	82:6473597d706e	5918	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5919
bogdanm	82:6473597d706e	5920	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5921	/*!
bogdanm	82:6473597d706e	5922	* @brief HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
bogdanm	82:6473597d706e	5923	*
bogdanm	82:6473597d706e	5924	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5925	*/
bogdanm	82:6473597d706e	5926	typedef union _hw_enet_ieee_t_fdxfc
bogdanm	82:6473597d706e	5927	{
bogdanm	82:6473597d706e	5928	uint32_t U;
bogdanm	82:6473597d706e	5929	struct _hw_enet_ieee_t_fdxfc_bitfields
bogdanm	82:6473597d706e	5930	{
bogdanm	82:6473597d706e	5931	uint32_t COUNT : 16; //!< [15:0] Frame count
bogdanm	82:6473597d706e	5932	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	5933	} B;
bogdanm	82:6473597d706e	5934	} hw_enet_ieee_t_fdxfc_t;
bogdanm	82:6473597d706e	5935	#endif
bogdanm	82:6473597d706e	5936
bogdanm	82:6473597d706e	5937	/*!
bogdanm	82:6473597d706e	5938	* @name Constants and macros for entire ENET_IEEE_T_FDXFC register
bogdanm	82:6473597d706e	5939	*/
bogdanm	82:6473597d706e	5940	//@{
bogdanm	82:6473597d706e	5941	#define HW_ENET_IEEE_T_FDXFC_ADDR(x) (REGS_ENET_BASE(x) + 0x270U)
bogdanm	82:6473597d706e	5942
bogdanm	82:6473597d706e	5943	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5944	#define HW_ENET_IEEE_T_FDXFC(x) ((__I hw_enet_ieee_t_fdxfc_t ) HW_ENET_IEEE_T_FDXFC_ADDR(x))
bogdanm	82:6473597d706e	5945	#define HW_ENET_IEEE_T_FDXFC_RD(x) (HW_ENET_IEEE_T_FDXFC(x).U)
bogdanm	82:6473597d706e	5946	#endif
bogdanm	82:6473597d706e	5947	//@}
bogdanm	82:6473597d706e	5948
bogdanm	82:6473597d706e	5949	/*
bogdanm	82:6473597d706e	5950	* Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
bogdanm	82:6473597d706e	5951	*/
bogdanm	82:6473597d706e	5952
bogdanm	82:6473597d706e	5953	/*!
bogdanm	82:6473597d706e	5954	* @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	5955	*/
bogdanm	82:6473597d706e	5956	//@{
bogdanm	82:6473597d706e	5957	#define BP_ENET_IEEE_T_FDXFC_COUNT (0U) //!< Bit position for ENET_IEEE_T_FDXFC_COUNT.
bogdanm	82:6473597d706e	5958	#define BM_ENET_IEEE_T_FDXFC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_FDXFC_COUNT.
bogdanm	82:6473597d706e	5959	#define BS_ENET_IEEE_T_FDXFC_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_FDXFC_COUNT.
bogdanm	82:6473597d706e	5960
bogdanm	82:6473597d706e	5961	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5962	//! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field.
bogdanm	82:6473597d706e	5963	#define BR_ENET_IEEE_T_FDXFC_COUNT(x) (HW_ENET_IEEE_T_FDXFC(x).B.COUNT)
bogdanm	82:6473597d706e	5964	#endif
bogdanm	82:6473597d706e	5965	//@}
bogdanm	82:6473597d706e	5966
bogdanm	82:6473597d706e	5967	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5968	// HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
bogdanm	82:6473597d706e	5969	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5970
bogdanm	82:6473597d706e	5971	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5972	/*!
bogdanm	82:6473597d706e	5973	* @brief HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
bogdanm	82:6473597d706e	5974	*
bogdanm	82:6473597d706e	5975	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5976	*
bogdanm	82:6473597d706e	5977	* Counts total octets (includes header and FCS fields).
bogdanm	82:6473597d706e	5978	*/
bogdanm	82:6473597d706e	5979	typedef union _hw_enet_ieee_t_octets_ok
bogdanm	82:6473597d706e	5980	{
bogdanm	82:6473597d706e	5981	uint32_t U;
bogdanm	82:6473597d706e	5982	struct _hw_enet_ieee_t_octets_ok_bitfields
bogdanm	82:6473597d706e	5983	{
bogdanm	82:6473597d706e	5984	uint32_t COUNT : 32; //!< [31:0] Octet count
bogdanm	82:6473597d706e	5985	} B;
bogdanm	82:6473597d706e	5986	} hw_enet_ieee_t_octets_ok_t;
bogdanm	82:6473597d706e	5987	#endif
bogdanm	82:6473597d706e	5988
bogdanm	82:6473597d706e	5989	/*!
bogdanm	82:6473597d706e	5990	* @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
bogdanm	82:6473597d706e	5991	*/
bogdanm	82:6473597d706e	5992	//@{
bogdanm	82:6473597d706e	5993	#define HW_ENET_IEEE_T_OCTETS_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x274U)
bogdanm	82:6473597d706e	5994
bogdanm	82:6473597d706e	5995	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5996	#define HW_ENET_IEEE_T_OCTETS_OK(x) ((__I hw_enet_ieee_t_octets_ok_t ) HW_ENET_IEEE_T_OCTETS_OK_ADDR(x))
bogdanm	82:6473597d706e	5997	#define HW_ENET_IEEE_T_OCTETS_OK_RD(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
bogdanm	82:6473597d706e	5998	#endif
bogdanm	82:6473597d706e	5999	//@}
bogdanm	82:6473597d706e	6000
bogdanm	82:6473597d706e	6001	/*
bogdanm	82:6473597d706e	6002	* Constants & macros for individual ENET_IEEE_T_OCTETS_OK bitfields
bogdanm	82:6473597d706e	6003	*/
bogdanm	82:6473597d706e	6004
bogdanm	82:6473597d706e	6005	/*!
bogdanm	82:6473597d706e	6006	* @name Register ENET_IEEE_T_OCTETS_OK, field COUNT[31:0] (RO)
bogdanm	82:6473597d706e	6007	*/
bogdanm	82:6473597d706e	6008	//@{
bogdanm	82:6473597d706e	6009	#define BP_ENET_IEEE_T_OCTETS_OK_COUNT (0U) //!< Bit position for ENET_IEEE_T_OCTETS_OK_COUNT.
bogdanm	82:6473597d706e	6010	#define BM_ENET_IEEE_T_OCTETS_OK_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_IEEE_T_OCTETS_OK_COUNT.
bogdanm	82:6473597d706e	6011	#define BS_ENET_IEEE_T_OCTETS_OK_COUNT (32U) //!< Bit field size in bits for ENET_IEEE_T_OCTETS_OK_COUNT.
bogdanm	82:6473597d706e	6012
bogdanm	82:6473597d706e	6013	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6014	//! @brief Read current value of the ENET_IEEE_T_OCTETS_OK_COUNT field.
bogdanm	82:6473597d706e	6015	#define BR_ENET_IEEE_T_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
bogdanm	82:6473597d706e	6016	#endif
bogdanm	82:6473597d706e	6017	//@}
bogdanm	82:6473597d706e	6018
bogdanm	82:6473597d706e	6019	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6020	// HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
bogdanm	82:6473597d706e	6021	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6022
bogdanm	82:6473597d706e	6023	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6024	/*!
bogdanm	82:6473597d706e	6025	* @brief HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
bogdanm	82:6473597d706e	6026	*
bogdanm	82:6473597d706e	6027	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6028	*/
bogdanm	82:6473597d706e	6029	typedef union _hw_enet_rmon_r_packets
bogdanm	82:6473597d706e	6030	{
bogdanm	82:6473597d706e	6031	uint32_t U;
bogdanm	82:6473597d706e	6032	struct _hw_enet_rmon_r_packets_bitfields
bogdanm	82:6473597d706e	6033	{
bogdanm	82:6473597d706e	6034	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6035	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6036	} B;
bogdanm	82:6473597d706e	6037	} hw_enet_rmon_r_packets_t;
bogdanm	82:6473597d706e	6038	#endif
bogdanm	82:6473597d706e	6039
bogdanm	82:6473597d706e	6040	/*!
bogdanm	82:6473597d706e	6041	* @name Constants and macros for entire ENET_RMON_R_PACKETS register
bogdanm	82:6473597d706e	6042	*/
bogdanm	82:6473597d706e	6043	//@{
bogdanm	82:6473597d706e	6044	#define HW_ENET_RMON_R_PACKETS_ADDR(x) (REGS_ENET_BASE(x) + 0x284U)
bogdanm	82:6473597d706e	6045
bogdanm	82:6473597d706e	6046	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6047	#define HW_ENET_RMON_R_PACKETS(x) ((__I hw_enet_rmon_r_packets_t ) HW_ENET_RMON_R_PACKETS_ADDR(x))
bogdanm	82:6473597d706e	6048	#define HW_ENET_RMON_R_PACKETS_RD(x) (HW_ENET_RMON_R_PACKETS(x).U)
bogdanm	82:6473597d706e	6049	#endif
bogdanm	82:6473597d706e	6050	//@}
bogdanm	82:6473597d706e	6051
bogdanm	82:6473597d706e	6052	/*
bogdanm	82:6473597d706e	6053	* Constants & macros for individual ENET_RMON_R_PACKETS bitfields
bogdanm	82:6473597d706e	6054	*/
bogdanm	82:6473597d706e	6055
bogdanm	82:6473597d706e	6056	/*!
bogdanm	82:6473597d706e	6057	* @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6058	*/
bogdanm	82:6473597d706e	6059	//@{
bogdanm	82:6473597d706e	6060	#define BP_ENET_RMON_R_PACKETS_COUNT (0U) //!< Bit position for ENET_RMON_R_PACKETS_COUNT.
bogdanm	82:6473597d706e	6061	#define BM_ENET_RMON_R_PACKETS_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_PACKETS_COUNT.
bogdanm	82:6473597d706e	6062	#define BS_ENET_RMON_R_PACKETS_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_PACKETS_COUNT.
bogdanm	82:6473597d706e	6063
bogdanm	82:6473597d706e	6064	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6065	//! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field.
bogdanm	82:6473597d706e	6066	#define BR_ENET_RMON_R_PACKETS_COUNT(x) (HW_ENET_RMON_R_PACKETS(x).B.COUNT)
bogdanm	82:6473597d706e	6067	#endif
bogdanm	82:6473597d706e	6068	//@}
bogdanm	82:6473597d706e	6069
bogdanm	82:6473597d706e	6070	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6071	// HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
bogdanm	82:6473597d706e	6072	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6073
bogdanm	82:6473597d706e	6074	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6075	/*!
bogdanm	82:6473597d706e	6076	* @brief HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
bogdanm	82:6473597d706e	6077	*
bogdanm	82:6473597d706e	6078	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6079	*/
bogdanm	82:6473597d706e	6080	typedef union _hw_enet_rmon_r_bc_pkt
bogdanm	82:6473597d706e	6081	{
bogdanm	82:6473597d706e	6082	uint32_t U;
bogdanm	82:6473597d706e	6083	struct _hw_enet_rmon_r_bc_pkt_bitfields
bogdanm	82:6473597d706e	6084	{
bogdanm	82:6473597d706e	6085	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6086	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6087	} B;
bogdanm	82:6473597d706e	6088	} hw_enet_rmon_r_bc_pkt_t;
bogdanm	82:6473597d706e	6089	#endif
bogdanm	82:6473597d706e	6090
bogdanm	82:6473597d706e	6091	/*!
bogdanm	82:6473597d706e	6092	* @name Constants and macros for entire ENET_RMON_R_BC_PKT register
bogdanm	82:6473597d706e	6093	*/
bogdanm	82:6473597d706e	6094	//@{
bogdanm	82:6473597d706e	6095	#define HW_ENET_RMON_R_BC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x288U)
bogdanm	82:6473597d706e	6096
bogdanm	82:6473597d706e	6097	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6098	#define HW_ENET_RMON_R_BC_PKT(x) ((__I hw_enet_rmon_r_bc_pkt_t ) HW_ENET_RMON_R_BC_PKT_ADDR(x))
bogdanm	82:6473597d706e	6099	#define HW_ENET_RMON_R_BC_PKT_RD(x) (HW_ENET_RMON_R_BC_PKT(x).U)
bogdanm	82:6473597d706e	6100	#endif
bogdanm	82:6473597d706e	6101	//@}
bogdanm	82:6473597d706e	6102
bogdanm	82:6473597d706e	6103	/*
bogdanm	82:6473597d706e	6104	* Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
bogdanm	82:6473597d706e	6105	*/
bogdanm	82:6473597d706e	6106
bogdanm	82:6473597d706e	6107	/*!
bogdanm	82:6473597d706e	6108	* @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6109	*/
bogdanm	82:6473597d706e	6110	//@{
bogdanm	82:6473597d706e	6111	#define BP_ENET_RMON_R_BC_PKT_COUNT (0U) //!< Bit position for ENET_RMON_R_BC_PKT_COUNT.
bogdanm	82:6473597d706e	6112	#define BM_ENET_RMON_R_BC_PKT_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_BC_PKT_COUNT.
bogdanm	82:6473597d706e	6113	#define BS_ENET_RMON_R_BC_PKT_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_BC_PKT_COUNT.
bogdanm	82:6473597d706e	6114
bogdanm	82:6473597d706e	6115	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6116	//! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field.
bogdanm	82:6473597d706e	6117	#define BR_ENET_RMON_R_BC_PKT_COUNT(x) (HW_ENET_RMON_R_BC_PKT(x).B.COUNT)
bogdanm	82:6473597d706e	6118	#endif
bogdanm	82:6473597d706e	6119	//@}
bogdanm	82:6473597d706e	6120
bogdanm	82:6473597d706e	6121	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6122	// HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
bogdanm	82:6473597d706e	6123	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6124
bogdanm	82:6473597d706e	6125	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6126	/*!
bogdanm	82:6473597d706e	6127	* @brief HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
bogdanm	82:6473597d706e	6128	*
bogdanm	82:6473597d706e	6129	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6130	*/
bogdanm	82:6473597d706e	6131	typedef union _hw_enet_rmon_r_mc_pkt
bogdanm	82:6473597d706e	6132	{
bogdanm	82:6473597d706e	6133	uint32_t U;
bogdanm	82:6473597d706e	6134	struct _hw_enet_rmon_r_mc_pkt_bitfields
bogdanm	82:6473597d706e	6135	{
bogdanm	82:6473597d706e	6136	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6137	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6138	} B;
bogdanm	82:6473597d706e	6139	} hw_enet_rmon_r_mc_pkt_t;
bogdanm	82:6473597d706e	6140	#endif
bogdanm	82:6473597d706e	6141
bogdanm	82:6473597d706e	6142	/*!
bogdanm	82:6473597d706e	6143	* @name Constants and macros for entire ENET_RMON_R_MC_PKT register
bogdanm	82:6473597d706e	6144	*/
bogdanm	82:6473597d706e	6145	//@{
bogdanm	82:6473597d706e	6146	#define HW_ENET_RMON_R_MC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x28CU)
bogdanm	82:6473597d706e	6147
bogdanm	82:6473597d706e	6148	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6149	#define HW_ENET_RMON_R_MC_PKT(x) ((__I hw_enet_rmon_r_mc_pkt_t ) HW_ENET_RMON_R_MC_PKT_ADDR(x))
bogdanm	82:6473597d706e	6150	#define HW_ENET_RMON_R_MC_PKT_RD(x) (HW_ENET_RMON_R_MC_PKT(x).U)
bogdanm	82:6473597d706e	6151	#endif
bogdanm	82:6473597d706e	6152	//@}
bogdanm	82:6473597d706e	6153
bogdanm	82:6473597d706e	6154	/*
bogdanm	82:6473597d706e	6155	* Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
bogdanm	82:6473597d706e	6156	*/
bogdanm	82:6473597d706e	6157
bogdanm	82:6473597d706e	6158	/*!
bogdanm	82:6473597d706e	6159	* @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6160	*/
bogdanm	82:6473597d706e	6161	//@{
bogdanm	82:6473597d706e	6162	#define BP_ENET_RMON_R_MC_PKT_COUNT (0U) //!< Bit position for ENET_RMON_R_MC_PKT_COUNT.
bogdanm	82:6473597d706e	6163	#define BM_ENET_RMON_R_MC_PKT_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_MC_PKT_COUNT.
bogdanm	82:6473597d706e	6164	#define BS_ENET_RMON_R_MC_PKT_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_MC_PKT_COUNT.
bogdanm	82:6473597d706e	6165
bogdanm	82:6473597d706e	6166	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6167	//! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field.
bogdanm	82:6473597d706e	6168	#define BR_ENET_RMON_R_MC_PKT_COUNT(x) (HW_ENET_RMON_R_MC_PKT(x).B.COUNT)
bogdanm	82:6473597d706e	6169	#endif
bogdanm	82:6473597d706e	6170	//@}
bogdanm	82:6473597d706e	6171
bogdanm	82:6473597d706e	6172	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6173	// HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
bogdanm	82:6473597d706e	6174	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6175
bogdanm	82:6473597d706e	6176	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6177	/*!
bogdanm	82:6473597d706e	6178	* @brief HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
bogdanm	82:6473597d706e	6179	*
bogdanm	82:6473597d706e	6180	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6181	*/
bogdanm	82:6473597d706e	6182	typedef union _hw_enet_rmon_r_crc_align
bogdanm	82:6473597d706e	6183	{
bogdanm	82:6473597d706e	6184	uint32_t U;
bogdanm	82:6473597d706e	6185	struct _hw_enet_rmon_r_crc_align_bitfields
bogdanm	82:6473597d706e	6186	{
bogdanm	82:6473597d706e	6187	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6188	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6189	} B;
bogdanm	82:6473597d706e	6190	} hw_enet_rmon_r_crc_align_t;
bogdanm	82:6473597d706e	6191	#endif
bogdanm	82:6473597d706e	6192
bogdanm	82:6473597d706e	6193	/*!
bogdanm	82:6473597d706e	6194	* @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
bogdanm	82:6473597d706e	6195	*/
bogdanm	82:6473597d706e	6196	//@{
bogdanm	82:6473597d706e	6197	#define HW_ENET_RMON_R_CRC_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x290U)
bogdanm	82:6473597d706e	6198
bogdanm	82:6473597d706e	6199	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6200	#define HW_ENET_RMON_R_CRC_ALIGN(x) ((__I hw_enet_rmon_r_crc_align_t ) HW_ENET_RMON_R_CRC_ALIGN_ADDR(x))
bogdanm	82:6473597d706e	6201	#define HW_ENET_RMON_R_CRC_ALIGN_RD(x) (HW_ENET_RMON_R_CRC_ALIGN(x).U)
bogdanm	82:6473597d706e	6202	#endif
bogdanm	82:6473597d706e	6203	//@}
bogdanm	82:6473597d706e	6204
bogdanm	82:6473597d706e	6205	/*
bogdanm	82:6473597d706e	6206	* Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
bogdanm	82:6473597d706e	6207	*/
bogdanm	82:6473597d706e	6208
bogdanm	82:6473597d706e	6209	/*!
bogdanm	82:6473597d706e	6210	* @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6211	*/
bogdanm	82:6473597d706e	6212	//@{
bogdanm	82:6473597d706e	6213	#define BP_ENET_RMON_R_CRC_ALIGN_COUNT (0U) //!< Bit position for ENET_RMON_R_CRC_ALIGN_COUNT.
bogdanm	82:6473597d706e	6214	#define BM_ENET_RMON_R_CRC_ALIGN_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_CRC_ALIGN_COUNT.
bogdanm	82:6473597d706e	6215	#define BS_ENET_RMON_R_CRC_ALIGN_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_CRC_ALIGN_COUNT.
bogdanm	82:6473597d706e	6216
bogdanm	82:6473597d706e	6217	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6218	//! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field.
bogdanm	82:6473597d706e	6219	#define BR_ENET_RMON_R_CRC_ALIGN_COUNT(x) (HW_ENET_RMON_R_CRC_ALIGN(x).B.COUNT)
bogdanm	82:6473597d706e	6220	#endif
bogdanm	82:6473597d706e	6221	//@}
bogdanm	82:6473597d706e	6222
bogdanm	82:6473597d706e	6223	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6224	// HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
bogdanm	82:6473597d706e	6225	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6226
bogdanm	82:6473597d706e	6227	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6228	/*!
bogdanm	82:6473597d706e	6229	* @brief HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
bogdanm	82:6473597d706e	6230	*
bogdanm	82:6473597d706e	6231	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6232	*/
bogdanm	82:6473597d706e	6233	typedef union _hw_enet_rmon_r_undersize
bogdanm	82:6473597d706e	6234	{
bogdanm	82:6473597d706e	6235	uint32_t U;
bogdanm	82:6473597d706e	6236	struct _hw_enet_rmon_r_undersize_bitfields
bogdanm	82:6473597d706e	6237	{
bogdanm	82:6473597d706e	6238	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6239	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6240	} B;
bogdanm	82:6473597d706e	6241	} hw_enet_rmon_r_undersize_t;
bogdanm	82:6473597d706e	6242	#endif
bogdanm	82:6473597d706e	6243
bogdanm	82:6473597d706e	6244	/*!
bogdanm	82:6473597d706e	6245	* @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
bogdanm	82:6473597d706e	6246	*/
bogdanm	82:6473597d706e	6247	//@{
bogdanm	82:6473597d706e	6248	#define HW_ENET_RMON_R_UNDERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x294U)
bogdanm	82:6473597d706e	6249
bogdanm	82:6473597d706e	6250	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6251	#define HW_ENET_RMON_R_UNDERSIZE(x) ((__I hw_enet_rmon_r_undersize_t ) HW_ENET_RMON_R_UNDERSIZE_ADDR(x))
bogdanm	82:6473597d706e	6252	#define HW_ENET_RMON_R_UNDERSIZE_RD(x) (HW_ENET_RMON_R_UNDERSIZE(x).U)
bogdanm	82:6473597d706e	6253	#endif
bogdanm	82:6473597d706e	6254	//@}
bogdanm	82:6473597d706e	6255
bogdanm	82:6473597d706e	6256	/*
bogdanm	82:6473597d706e	6257	* Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
bogdanm	82:6473597d706e	6258	*/
bogdanm	82:6473597d706e	6259
bogdanm	82:6473597d706e	6260	/*!
bogdanm	82:6473597d706e	6261	* @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6262	*/
bogdanm	82:6473597d706e	6263	//@{
bogdanm	82:6473597d706e	6264	#define BP_ENET_RMON_R_UNDERSIZE_COUNT (0U) //!< Bit position for ENET_RMON_R_UNDERSIZE_COUNT.
bogdanm	82:6473597d706e	6265	#define BM_ENET_RMON_R_UNDERSIZE_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_UNDERSIZE_COUNT.
bogdanm	82:6473597d706e	6266	#define BS_ENET_RMON_R_UNDERSIZE_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_UNDERSIZE_COUNT.
bogdanm	82:6473597d706e	6267
bogdanm	82:6473597d706e	6268	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6269	//! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field.
bogdanm	82:6473597d706e	6270	#define BR_ENET_RMON_R_UNDERSIZE_COUNT(x) (HW_ENET_RMON_R_UNDERSIZE(x).B.COUNT)
bogdanm	82:6473597d706e	6271	#endif
bogdanm	82:6473597d706e	6272	//@}
bogdanm	82:6473597d706e	6273
bogdanm	82:6473597d706e	6274	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6275	// HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
bogdanm	82:6473597d706e	6276	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6277
bogdanm	82:6473597d706e	6278	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6279	/*!
bogdanm	82:6473597d706e	6280	* @brief HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
bogdanm	82:6473597d706e	6281	*
bogdanm	82:6473597d706e	6282	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6283	*/
bogdanm	82:6473597d706e	6284	typedef union _hw_enet_rmon_r_oversize
bogdanm	82:6473597d706e	6285	{
bogdanm	82:6473597d706e	6286	uint32_t U;
bogdanm	82:6473597d706e	6287	struct _hw_enet_rmon_r_oversize_bitfields
bogdanm	82:6473597d706e	6288	{
bogdanm	82:6473597d706e	6289	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6290	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6291	} B;
bogdanm	82:6473597d706e	6292	} hw_enet_rmon_r_oversize_t;
bogdanm	82:6473597d706e	6293	#endif
bogdanm	82:6473597d706e	6294
bogdanm	82:6473597d706e	6295	/*!
bogdanm	82:6473597d706e	6296	* @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
bogdanm	82:6473597d706e	6297	*/
bogdanm	82:6473597d706e	6298	//@{
bogdanm	82:6473597d706e	6299	#define HW_ENET_RMON_R_OVERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x298U)
bogdanm	82:6473597d706e	6300
bogdanm	82:6473597d706e	6301	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6302	#define HW_ENET_RMON_R_OVERSIZE(x) ((__I hw_enet_rmon_r_oversize_t ) HW_ENET_RMON_R_OVERSIZE_ADDR(x))
bogdanm	82:6473597d706e	6303	#define HW_ENET_RMON_R_OVERSIZE_RD(x) (HW_ENET_RMON_R_OVERSIZE(x).U)
bogdanm	82:6473597d706e	6304	#endif
bogdanm	82:6473597d706e	6305	//@}
bogdanm	82:6473597d706e	6306
bogdanm	82:6473597d706e	6307	/*
bogdanm	82:6473597d706e	6308	* Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
bogdanm	82:6473597d706e	6309	*/
bogdanm	82:6473597d706e	6310
bogdanm	82:6473597d706e	6311	/*!
bogdanm	82:6473597d706e	6312	* @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6313	*/
bogdanm	82:6473597d706e	6314	//@{
bogdanm	82:6473597d706e	6315	#define BP_ENET_RMON_R_OVERSIZE_COUNT (0U) //!< Bit position for ENET_RMON_R_OVERSIZE_COUNT.
bogdanm	82:6473597d706e	6316	#define BM_ENET_RMON_R_OVERSIZE_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_OVERSIZE_COUNT.
bogdanm	82:6473597d706e	6317	#define BS_ENET_RMON_R_OVERSIZE_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_OVERSIZE_COUNT.
bogdanm	82:6473597d706e	6318
bogdanm	82:6473597d706e	6319	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6320	//! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field.
bogdanm	82:6473597d706e	6321	#define BR_ENET_RMON_R_OVERSIZE_COUNT(x) (HW_ENET_RMON_R_OVERSIZE(x).B.COUNT)
bogdanm	82:6473597d706e	6322	#endif
bogdanm	82:6473597d706e	6323	//@}
bogdanm	82:6473597d706e	6324
bogdanm	82:6473597d706e	6325	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6326	// HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
bogdanm	82:6473597d706e	6327	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6328
bogdanm	82:6473597d706e	6329	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6330	/*!
bogdanm	82:6473597d706e	6331	* @brief HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
bogdanm	82:6473597d706e	6332	*
bogdanm	82:6473597d706e	6333	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6334	*/
bogdanm	82:6473597d706e	6335	typedef union _hw_enet_rmon_r_frag
bogdanm	82:6473597d706e	6336	{
bogdanm	82:6473597d706e	6337	uint32_t U;
bogdanm	82:6473597d706e	6338	struct _hw_enet_rmon_r_frag_bitfields
bogdanm	82:6473597d706e	6339	{
bogdanm	82:6473597d706e	6340	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6341	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6342	} B;
bogdanm	82:6473597d706e	6343	} hw_enet_rmon_r_frag_t;
bogdanm	82:6473597d706e	6344	#endif
bogdanm	82:6473597d706e	6345
bogdanm	82:6473597d706e	6346	/*!
bogdanm	82:6473597d706e	6347	* @name Constants and macros for entire ENET_RMON_R_FRAG register
bogdanm	82:6473597d706e	6348	*/
bogdanm	82:6473597d706e	6349	//@{
bogdanm	82:6473597d706e	6350	#define HW_ENET_RMON_R_FRAG_ADDR(x) (REGS_ENET_BASE(x) + 0x29CU)
bogdanm	82:6473597d706e	6351
bogdanm	82:6473597d706e	6352	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6353	#define HW_ENET_RMON_R_FRAG(x) ((__I hw_enet_rmon_r_frag_t ) HW_ENET_RMON_R_FRAG_ADDR(x))
bogdanm	82:6473597d706e	6354	#define HW_ENET_RMON_R_FRAG_RD(x) (HW_ENET_RMON_R_FRAG(x).U)
bogdanm	82:6473597d706e	6355	#endif
bogdanm	82:6473597d706e	6356	//@}
bogdanm	82:6473597d706e	6357
bogdanm	82:6473597d706e	6358	/*
bogdanm	82:6473597d706e	6359	* Constants & macros for individual ENET_RMON_R_FRAG bitfields
bogdanm	82:6473597d706e	6360	*/
bogdanm	82:6473597d706e	6361
bogdanm	82:6473597d706e	6362	/*!
bogdanm	82:6473597d706e	6363	* @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6364	*/
bogdanm	82:6473597d706e	6365	//@{
bogdanm	82:6473597d706e	6366	#define BP_ENET_RMON_R_FRAG_COUNT (0U) //!< Bit position for ENET_RMON_R_FRAG_COUNT.
bogdanm	82:6473597d706e	6367	#define BM_ENET_RMON_R_FRAG_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_FRAG_COUNT.
bogdanm	82:6473597d706e	6368	#define BS_ENET_RMON_R_FRAG_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_FRAG_COUNT.
bogdanm	82:6473597d706e	6369
bogdanm	82:6473597d706e	6370	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6371	//! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field.
bogdanm	82:6473597d706e	6372	#define BR_ENET_RMON_R_FRAG_COUNT(x) (HW_ENET_RMON_R_FRAG(x).B.COUNT)
bogdanm	82:6473597d706e	6373	#endif
bogdanm	82:6473597d706e	6374	//@}
bogdanm	82:6473597d706e	6375
bogdanm	82:6473597d706e	6376	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6377	// HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
bogdanm	82:6473597d706e	6378	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6379
bogdanm	82:6473597d706e	6380	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6381	/*!
bogdanm	82:6473597d706e	6382	* @brief HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
bogdanm	82:6473597d706e	6383	*
bogdanm	82:6473597d706e	6384	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6385	*/
bogdanm	82:6473597d706e	6386	typedef union _hw_enet_rmon_r_jab
bogdanm	82:6473597d706e	6387	{
bogdanm	82:6473597d706e	6388	uint32_t U;
bogdanm	82:6473597d706e	6389	struct _hw_enet_rmon_r_jab_bitfields
bogdanm	82:6473597d706e	6390	{
bogdanm	82:6473597d706e	6391	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6392	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6393	} B;
bogdanm	82:6473597d706e	6394	} hw_enet_rmon_r_jab_t;
bogdanm	82:6473597d706e	6395	#endif
bogdanm	82:6473597d706e	6396
bogdanm	82:6473597d706e	6397	/*!
bogdanm	82:6473597d706e	6398	* @name Constants and macros for entire ENET_RMON_R_JAB register
bogdanm	82:6473597d706e	6399	*/
bogdanm	82:6473597d706e	6400	//@{
bogdanm	82:6473597d706e	6401	#define HW_ENET_RMON_R_JAB_ADDR(x) (REGS_ENET_BASE(x) + 0x2A0U)
bogdanm	82:6473597d706e	6402
bogdanm	82:6473597d706e	6403	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6404	#define HW_ENET_RMON_R_JAB(x) ((__I hw_enet_rmon_r_jab_t ) HW_ENET_RMON_R_JAB_ADDR(x))
bogdanm	82:6473597d706e	6405	#define HW_ENET_RMON_R_JAB_RD(x) (HW_ENET_RMON_R_JAB(x).U)
bogdanm	82:6473597d706e	6406	#endif
bogdanm	82:6473597d706e	6407	//@}
bogdanm	82:6473597d706e	6408
bogdanm	82:6473597d706e	6409	/*
bogdanm	82:6473597d706e	6410	* Constants & macros for individual ENET_RMON_R_JAB bitfields
bogdanm	82:6473597d706e	6411	*/
bogdanm	82:6473597d706e	6412
bogdanm	82:6473597d706e	6413	/*!
bogdanm	82:6473597d706e	6414	* @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6415	*/
bogdanm	82:6473597d706e	6416	//@{
bogdanm	82:6473597d706e	6417	#define BP_ENET_RMON_R_JAB_COUNT (0U) //!< Bit position for ENET_RMON_R_JAB_COUNT.
bogdanm	82:6473597d706e	6418	#define BM_ENET_RMON_R_JAB_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_JAB_COUNT.
bogdanm	82:6473597d706e	6419	#define BS_ENET_RMON_R_JAB_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_JAB_COUNT.
bogdanm	82:6473597d706e	6420
bogdanm	82:6473597d706e	6421	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6422	//! @brief Read current value of the ENET_RMON_R_JAB_COUNT field.
bogdanm	82:6473597d706e	6423	#define BR_ENET_RMON_R_JAB_COUNT(x) (HW_ENET_RMON_R_JAB(x).B.COUNT)
bogdanm	82:6473597d706e	6424	#endif
bogdanm	82:6473597d706e	6425	//@}
bogdanm	82:6473597d706e	6426
bogdanm	82:6473597d706e	6427	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6428	// HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
bogdanm	82:6473597d706e	6429	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6430
bogdanm	82:6473597d706e	6431	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6432	/*!
bogdanm	82:6473597d706e	6433	* @brief HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
bogdanm	82:6473597d706e	6434	*
bogdanm	82:6473597d706e	6435	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6436	*/
bogdanm	82:6473597d706e	6437	typedef union _hw_enet_rmon_r_p64
bogdanm	82:6473597d706e	6438	{
bogdanm	82:6473597d706e	6439	uint32_t U;
bogdanm	82:6473597d706e	6440	struct _hw_enet_rmon_r_p64_bitfields
bogdanm	82:6473597d706e	6441	{
bogdanm	82:6473597d706e	6442	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6443	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6444	} B;
bogdanm	82:6473597d706e	6445	} hw_enet_rmon_r_p64_t;
bogdanm	82:6473597d706e	6446	#endif
bogdanm	82:6473597d706e	6447
bogdanm	82:6473597d706e	6448	/*!
bogdanm	82:6473597d706e	6449	* @name Constants and macros for entire ENET_RMON_R_P64 register
bogdanm	82:6473597d706e	6450	*/
bogdanm	82:6473597d706e	6451	//@{
bogdanm	82:6473597d706e	6452	#define HW_ENET_RMON_R_P64_ADDR(x) (REGS_ENET_BASE(x) + 0x2A8U)
bogdanm	82:6473597d706e	6453
bogdanm	82:6473597d706e	6454	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6455	#define HW_ENET_RMON_R_P64(x) ((__I hw_enet_rmon_r_p64_t ) HW_ENET_RMON_R_P64_ADDR(x))
bogdanm	82:6473597d706e	6456	#define HW_ENET_RMON_R_P64_RD(x) (HW_ENET_RMON_R_P64(x).U)
bogdanm	82:6473597d706e	6457	#endif
bogdanm	82:6473597d706e	6458	//@}
bogdanm	82:6473597d706e	6459
bogdanm	82:6473597d706e	6460	/*
bogdanm	82:6473597d706e	6461	* Constants & macros for individual ENET_RMON_R_P64 bitfields
bogdanm	82:6473597d706e	6462	*/
bogdanm	82:6473597d706e	6463
bogdanm	82:6473597d706e	6464	/*!
bogdanm	82:6473597d706e	6465	* @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6466	*/
bogdanm	82:6473597d706e	6467	//@{
bogdanm	82:6473597d706e	6468	#define BP_ENET_RMON_R_P64_COUNT (0U) //!< Bit position for ENET_RMON_R_P64_COUNT.
bogdanm	82:6473597d706e	6469	#define BM_ENET_RMON_R_P64_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P64_COUNT.
bogdanm	82:6473597d706e	6470	#define BS_ENET_RMON_R_P64_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P64_COUNT.
bogdanm	82:6473597d706e	6471
bogdanm	82:6473597d706e	6472	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6473	//! @brief Read current value of the ENET_RMON_R_P64_COUNT field.
bogdanm	82:6473597d706e	6474	#define BR_ENET_RMON_R_P64_COUNT(x) (HW_ENET_RMON_R_P64(x).B.COUNT)
bogdanm	82:6473597d706e	6475	#endif
bogdanm	82:6473597d706e	6476	//@}
bogdanm	82:6473597d706e	6477
bogdanm	82:6473597d706e	6478	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6479	// HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
bogdanm	82:6473597d706e	6480	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6481
bogdanm	82:6473597d706e	6482	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6483	/*!
bogdanm	82:6473597d706e	6484	* @brief HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
bogdanm	82:6473597d706e	6485	*
bogdanm	82:6473597d706e	6486	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6487	*/
bogdanm	82:6473597d706e	6488	typedef union _hw_enet_rmon_r_p65to127
bogdanm	82:6473597d706e	6489	{
bogdanm	82:6473597d706e	6490	uint32_t U;
bogdanm	82:6473597d706e	6491	struct _hw_enet_rmon_r_p65to127_bitfields
bogdanm	82:6473597d706e	6492	{
bogdanm	82:6473597d706e	6493	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6494	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6495	} B;
bogdanm	82:6473597d706e	6496	} hw_enet_rmon_r_p65to127_t;
bogdanm	82:6473597d706e	6497	#endif
bogdanm	82:6473597d706e	6498
bogdanm	82:6473597d706e	6499	/*!
bogdanm	82:6473597d706e	6500	* @name Constants and macros for entire ENET_RMON_R_P65TO127 register
bogdanm	82:6473597d706e	6501	*/
bogdanm	82:6473597d706e	6502	//@{
bogdanm	82:6473597d706e	6503	#define HW_ENET_RMON_R_P65TO127_ADDR(x) (REGS_ENET_BASE(x) + 0x2ACU)
bogdanm	82:6473597d706e	6504
bogdanm	82:6473597d706e	6505	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6506	#define HW_ENET_RMON_R_P65TO127(x) ((__I hw_enet_rmon_r_p65to127_t ) HW_ENET_RMON_R_P65TO127_ADDR(x))
bogdanm	82:6473597d706e	6507	#define HW_ENET_RMON_R_P65TO127_RD(x) (HW_ENET_RMON_R_P65TO127(x).U)
bogdanm	82:6473597d706e	6508	#endif
bogdanm	82:6473597d706e	6509	//@}
bogdanm	82:6473597d706e	6510
bogdanm	82:6473597d706e	6511	/*
bogdanm	82:6473597d706e	6512	* Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
bogdanm	82:6473597d706e	6513	*/
bogdanm	82:6473597d706e	6514
bogdanm	82:6473597d706e	6515	/*!
bogdanm	82:6473597d706e	6516	* @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6517	*/
bogdanm	82:6473597d706e	6518	//@{
bogdanm	82:6473597d706e	6519	#define BP_ENET_RMON_R_P65TO127_COUNT (0U) //!< Bit position for ENET_RMON_R_P65TO127_COUNT.
bogdanm	82:6473597d706e	6520	#define BM_ENET_RMON_R_P65TO127_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P65TO127_COUNT.
bogdanm	82:6473597d706e	6521	#define BS_ENET_RMON_R_P65TO127_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P65TO127_COUNT.
bogdanm	82:6473597d706e	6522
bogdanm	82:6473597d706e	6523	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6524	//! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field.
bogdanm	82:6473597d706e	6525	#define BR_ENET_RMON_R_P65TO127_COUNT(x) (HW_ENET_RMON_R_P65TO127(x).B.COUNT)
bogdanm	82:6473597d706e	6526	#endif
bogdanm	82:6473597d706e	6527	//@}
bogdanm	82:6473597d706e	6528
bogdanm	82:6473597d706e	6529	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6530	// HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
bogdanm	82:6473597d706e	6531	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6532
bogdanm	82:6473597d706e	6533	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6534	/*!
bogdanm	82:6473597d706e	6535	* @brief HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
bogdanm	82:6473597d706e	6536	*
bogdanm	82:6473597d706e	6537	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6538	*/
bogdanm	82:6473597d706e	6539	typedef union _hw_enet_rmon_r_p128to255
bogdanm	82:6473597d706e	6540	{
bogdanm	82:6473597d706e	6541	uint32_t U;
bogdanm	82:6473597d706e	6542	struct _hw_enet_rmon_r_p128to255_bitfields
bogdanm	82:6473597d706e	6543	{
bogdanm	82:6473597d706e	6544	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6545	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6546	} B;
bogdanm	82:6473597d706e	6547	} hw_enet_rmon_r_p128to255_t;
bogdanm	82:6473597d706e	6548	#endif
bogdanm	82:6473597d706e	6549
bogdanm	82:6473597d706e	6550	/*!
bogdanm	82:6473597d706e	6551	* @name Constants and macros for entire ENET_RMON_R_P128TO255 register
bogdanm	82:6473597d706e	6552	*/
bogdanm	82:6473597d706e	6553	//@{
bogdanm	82:6473597d706e	6554	#define HW_ENET_RMON_R_P128TO255_ADDR(x) (REGS_ENET_BASE(x) + 0x2B0U)
bogdanm	82:6473597d706e	6555
bogdanm	82:6473597d706e	6556	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6557	#define HW_ENET_RMON_R_P128TO255(x) ((__I hw_enet_rmon_r_p128to255_t ) HW_ENET_RMON_R_P128TO255_ADDR(x))
bogdanm	82:6473597d706e	6558	#define HW_ENET_RMON_R_P128TO255_RD(x) (HW_ENET_RMON_R_P128TO255(x).U)
bogdanm	82:6473597d706e	6559	#endif
bogdanm	82:6473597d706e	6560	//@}
bogdanm	82:6473597d706e	6561
bogdanm	82:6473597d706e	6562	/*
bogdanm	82:6473597d706e	6563	* Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
bogdanm	82:6473597d706e	6564	*/
bogdanm	82:6473597d706e	6565
bogdanm	82:6473597d706e	6566	/*!
bogdanm	82:6473597d706e	6567	* @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6568	*/
bogdanm	82:6473597d706e	6569	//@{
bogdanm	82:6473597d706e	6570	#define BP_ENET_RMON_R_P128TO255_COUNT (0U) //!< Bit position for ENET_RMON_R_P128TO255_COUNT.
bogdanm	82:6473597d706e	6571	#define BM_ENET_RMON_R_P128TO255_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P128TO255_COUNT.
bogdanm	82:6473597d706e	6572	#define BS_ENET_RMON_R_P128TO255_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P128TO255_COUNT.
bogdanm	82:6473597d706e	6573
bogdanm	82:6473597d706e	6574	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6575	//! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field.
bogdanm	82:6473597d706e	6576	#define BR_ENET_RMON_R_P128TO255_COUNT(x) (HW_ENET_RMON_R_P128TO255(x).B.COUNT)
bogdanm	82:6473597d706e	6577	#endif
bogdanm	82:6473597d706e	6578	//@}
bogdanm	82:6473597d706e	6579
bogdanm	82:6473597d706e	6580	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6581	// HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
bogdanm	82:6473597d706e	6582	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6583
bogdanm	82:6473597d706e	6584	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6585	/*!
bogdanm	82:6473597d706e	6586	* @brief HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
bogdanm	82:6473597d706e	6587	*
bogdanm	82:6473597d706e	6588	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6589	*/
bogdanm	82:6473597d706e	6590	typedef union _hw_enet_rmon_r_p256to511
bogdanm	82:6473597d706e	6591	{
bogdanm	82:6473597d706e	6592	uint32_t U;
bogdanm	82:6473597d706e	6593	struct _hw_enet_rmon_r_p256to511_bitfields
bogdanm	82:6473597d706e	6594	{
bogdanm	82:6473597d706e	6595	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6596	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6597	} B;
bogdanm	82:6473597d706e	6598	} hw_enet_rmon_r_p256to511_t;
bogdanm	82:6473597d706e	6599	#endif
bogdanm	82:6473597d706e	6600
bogdanm	82:6473597d706e	6601	/*!
bogdanm	82:6473597d706e	6602	* @name Constants and macros for entire ENET_RMON_R_P256TO511 register
bogdanm	82:6473597d706e	6603	*/
bogdanm	82:6473597d706e	6604	//@{
bogdanm	82:6473597d706e	6605	#define HW_ENET_RMON_R_P256TO511_ADDR(x) (REGS_ENET_BASE(x) + 0x2B4U)
bogdanm	82:6473597d706e	6606
bogdanm	82:6473597d706e	6607	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6608	#define HW_ENET_RMON_R_P256TO511(x) ((__I hw_enet_rmon_r_p256to511_t ) HW_ENET_RMON_R_P256TO511_ADDR(x))
bogdanm	82:6473597d706e	6609	#define HW_ENET_RMON_R_P256TO511_RD(x) (HW_ENET_RMON_R_P256TO511(x).U)
bogdanm	82:6473597d706e	6610	#endif
bogdanm	82:6473597d706e	6611	//@}
bogdanm	82:6473597d706e	6612
bogdanm	82:6473597d706e	6613	/*
bogdanm	82:6473597d706e	6614	* Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
bogdanm	82:6473597d706e	6615	*/
bogdanm	82:6473597d706e	6616
bogdanm	82:6473597d706e	6617	/*!
bogdanm	82:6473597d706e	6618	* @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6619	*/
bogdanm	82:6473597d706e	6620	//@{
bogdanm	82:6473597d706e	6621	#define BP_ENET_RMON_R_P256TO511_COUNT (0U) //!< Bit position for ENET_RMON_R_P256TO511_COUNT.
bogdanm	82:6473597d706e	6622	#define BM_ENET_RMON_R_P256TO511_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P256TO511_COUNT.
bogdanm	82:6473597d706e	6623	#define BS_ENET_RMON_R_P256TO511_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P256TO511_COUNT.
bogdanm	82:6473597d706e	6624
bogdanm	82:6473597d706e	6625	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6626	//! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field.
bogdanm	82:6473597d706e	6627	#define BR_ENET_RMON_R_P256TO511_COUNT(x) (HW_ENET_RMON_R_P256TO511(x).B.COUNT)
bogdanm	82:6473597d706e	6628	#endif
bogdanm	82:6473597d706e	6629	//@}
bogdanm	82:6473597d706e	6630
bogdanm	82:6473597d706e	6631	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6632	// HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
bogdanm	82:6473597d706e	6633	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6634
bogdanm	82:6473597d706e	6635	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6636	/*!
bogdanm	82:6473597d706e	6637	* @brief HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
bogdanm	82:6473597d706e	6638	*
bogdanm	82:6473597d706e	6639	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6640	*/
bogdanm	82:6473597d706e	6641	typedef union _hw_enet_rmon_r_p512to1023
bogdanm	82:6473597d706e	6642	{
bogdanm	82:6473597d706e	6643	uint32_t U;
bogdanm	82:6473597d706e	6644	struct _hw_enet_rmon_r_p512to1023_bitfields
bogdanm	82:6473597d706e	6645	{
bogdanm	82:6473597d706e	6646	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6647	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6648	} B;
bogdanm	82:6473597d706e	6649	} hw_enet_rmon_r_p512to1023_t;
bogdanm	82:6473597d706e	6650	#endif
bogdanm	82:6473597d706e	6651
bogdanm	82:6473597d706e	6652	/*!
bogdanm	82:6473597d706e	6653	* @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
bogdanm	82:6473597d706e	6654	*/
bogdanm	82:6473597d706e	6655	//@{
bogdanm	82:6473597d706e	6656	#define HW_ENET_RMON_R_P512TO1023_ADDR(x) (REGS_ENET_BASE(x) + 0x2B8U)
bogdanm	82:6473597d706e	6657
bogdanm	82:6473597d706e	6658	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6659	#define HW_ENET_RMON_R_P512TO1023(x) ((__I hw_enet_rmon_r_p512to1023_t ) HW_ENET_RMON_R_P512TO1023_ADDR(x))
bogdanm	82:6473597d706e	6660	#define HW_ENET_RMON_R_P512TO1023_RD(x) (HW_ENET_RMON_R_P512TO1023(x).U)
bogdanm	82:6473597d706e	6661	#endif
bogdanm	82:6473597d706e	6662	//@}
bogdanm	82:6473597d706e	6663
bogdanm	82:6473597d706e	6664	/*
bogdanm	82:6473597d706e	6665	* Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
bogdanm	82:6473597d706e	6666	*/
bogdanm	82:6473597d706e	6667
bogdanm	82:6473597d706e	6668	/*!
bogdanm	82:6473597d706e	6669	* @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6670	*/
bogdanm	82:6473597d706e	6671	//@{
bogdanm	82:6473597d706e	6672	#define BP_ENET_RMON_R_P512TO1023_COUNT (0U) //!< Bit position for ENET_RMON_R_P512TO1023_COUNT.
bogdanm	82:6473597d706e	6673	#define BM_ENET_RMON_R_P512TO1023_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P512TO1023_COUNT.
bogdanm	82:6473597d706e	6674	#define BS_ENET_RMON_R_P512TO1023_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P512TO1023_COUNT.
bogdanm	82:6473597d706e	6675
bogdanm	82:6473597d706e	6676	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6677	//! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field.
bogdanm	82:6473597d706e	6678	#define BR_ENET_RMON_R_P512TO1023_COUNT(x) (HW_ENET_RMON_R_P512TO1023(x).B.COUNT)
bogdanm	82:6473597d706e	6679	#endif
bogdanm	82:6473597d706e	6680	//@}
bogdanm	82:6473597d706e	6681
bogdanm	82:6473597d706e	6682	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6683	// HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
bogdanm	82:6473597d706e	6684	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6685
bogdanm	82:6473597d706e	6686	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6687	/*!
bogdanm	82:6473597d706e	6688	* @brief HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
bogdanm	82:6473597d706e	6689	*
bogdanm	82:6473597d706e	6690	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6691	*/
bogdanm	82:6473597d706e	6692	typedef union _hw_enet_rmon_r_p1024to2047
bogdanm	82:6473597d706e	6693	{
bogdanm	82:6473597d706e	6694	uint32_t U;
bogdanm	82:6473597d706e	6695	struct _hw_enet_rmon_r_p1024to2047_bitfields
bogdanm	82:6473597d706e	6696	{
bogdanm	82:6473597d706e	6697	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6698	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6699	} B;
bogdanm	82:6473597d706e	6700	} hw_enet_rmon_r_p1024to2047_t;
bogdanm	82:6473597d706e	6701	#endif
bogdanm	82:6473597d706e	6702
bogdanm	82:6473597d706e	6703	/*!
bogdanm	82:6473597d706e	6704	* @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
bogdanm	82:6473597d706e	6705	*/
bogdanm	82:6473597d706e	6706	//@{
bogdanm	82:6473597d706e	6707	#define HW_ENET_RMON_R_P1024TO2047_ADDR(x) (REGS_ENET_BASE(x) + 0x2BCU)
bogdanm	82:6473597d706e	6708
bogdanm	82:6473597d706e	6709	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6710	#define HW_ENET_RMON_R_P1024TO2047(x) ((__I hw_enet_rmon_r_p1024to2047_t ) HW_ENET_RMON_R_P1024TO2047_ADDR(x))
bogdanm	82:6473597d706e	6711	#define HW_ENET_RMON_R_P1024TO2047_RD(x) (HW_ENET_RMON_R_P1024TO2047(x).U)
bogdanm	82:6473597d706e	6712	#endif
bogdanm	82:6473597d706e	6713	//@}
bogdanm	82:6473597d706e	6714
bogdanm	82:6473597d706e	6715	/*
bogdanm	82:6473597d706e	6716	* Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
bogdanm	82:6473597d706e	6717	*/
bogdanm	82:6473597d706e	6718
bogdanm	82:6473597d706e	6719	/*!
bogdanm	82:6473597d706e	6720	* @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6721	*/
bogdanm	82:6473597d706e	6722	//@{
bogdanm	82:6473597d706e	6723	#define BP_ENET_RMON_R_P1024TO2047_COUNT (0U) //!< Bit position for ENET_RMON_R_P1024TO2047_COUNT.
bogdanm	82:6473597d706e	6724	#define BM_ENET_RMON_R_P1024TO2047_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P1024TO2047_COUNT.
bogdanm	82:6473597d706e	6725	#define BS_ENET_RMON_R_P1024TO2047_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P1024TO2047_COUNT.
bogdanm	82:6473597d706e	6726
bogdanm	82:6473597d706e	6727	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6728	//! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field.
bogdanm	82:6473597d706e	6729	#define BR_ENET_RMON_R_P1024TO2047_COUNT(x) (HW_ENET_RMON_R_P1024TO2047(x).B.COUNT)
bogdanm	82:6473597d706e	6730	#endif
bogdanm	82:6473597d706e	6731	//@}
bogdanm	82:6473597d706e	6732
bogdanm	82:6473597d706e	6733	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6734	// HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
bogdanm	82:6473597d706e	6735	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6736
bogdanm	82:6473597d706e	6737	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6738	/*!
bogdanm	82:6473597d706e	6739	* @brief HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
bogdanm	82:6473597d706e	6740	*
bogdanm	82:6473597d706e	6741	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6742	*/
bogdanm	82:6473597d706e	6743	typedef union _hw_enet_rmon_r_gte2048
bogdanm	82:6473597d706e	6744	{
bogdanm	82:6473597d706e	6745	uint32_t U;
bogdanm	82:6473597d706e	6746	struct _hw_enet_rmon_r_gte2048_bitfields
bogdanm	82:6473597d706e	6747	{
bogdanm	82:6473597d706e	6748	uint32_t COUNT : 16; //!< [15:0] Packet count
bogdanm	82:6473597d706e	6749	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6750	} B;
bogdanm	82:6473597d706e	6751	} hw_enet_rmon_r_gte2048_t;
bogdanm	82:6473597d706e	6752	#endif
bogdanm	82:6473597d706e	6753
bogdanm	82:6473597d706e	6754	/*!
bogdanm	82:6473597d706e	6755	* @name Constants and macros for entire ENET_RMON_R_GTE2048 register
bogdanm	82:6473597d706e	6756	*/
bogdanm	82:6473597d706e	6757	//@{
bogdanm	82:6473597d706e	6758	#define HW_ENET_RMON_R_GTE2048_ADDR(x) (REGS_ENET_BASE(x) + 0x2C0U)
bogdanm	82:6473597d706e	6759
bogdanm	82:6473597d706e	6760	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6761	#define HW_ENET_RMON_R_GTE2048(x) ((__I hw_enet_rmon_r_gte2048_t ) HW_ENET_RMON_R_GTE2048_ADDR(x))
bogdanm	82:6473597d706e	6762	#define HW_ENET_RMON_R_GTE2048_RD(x) (HW_ENET_RMON_R_GTE2048(x).U)
bogdanm	82:6473597d706e	6763	#endif
bogdanm	82:6473597d706e	6764	//@}
bogdanm	82:6473597d706e	6765
bogdanm	82:6473597d706e	6766	/*
bogdanm	82:6473597d706e	6767	* Constants & macros for individual ENET_RMON_R_GTE2048 bitfields
bogdanm	82:6473597d706e	6768	*/
bogdanm	82:6473597d706e	6769
bogdanm	82:6473597d706e	6770	/*!
bogdanm	82:6473597d706e	6771	* @name Register ENET_RMON_R_GTE2048, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6772	*/
bogdanm	82:6473597d706e	6773	//@{
bogdanm	82:6473597d706e	6774	#define BP_ENET_RMON_R_GTE2048_COUNT (0U) //!< Bit position for ENET_RMON_R_GTE2048_COUNT.
bogdanm	82:6473597d706e	6775	#define BM_ENET_RMON_R_GTE2048_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_GTE2048_COUNT.
bogdanm	82:6473597d706e	6776	#define BS_ENET_RMON_R_GTE2048_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_GTE2048_COUNT.
bogdanm	82:6473597d706e	6777
bogdanm	82:6473597d706e	6778	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6779	//! @brief Read current value of the ENET_RMON_R_GTE2048_COUNT field.
bogdanm	82:6473597d706e	6780	#define BR_ENET_RMON_R_GTE2048_COUNT(x) (HW_ENET_RMON_R_GTE2048(x).B.COUNT)
bogdanm	82:6473597d706e	6781	#endif
bogdanm	82:6473597d706e	6782	//@}
bogdanm	82:6473597d706e	6783
bogdanm	82:6473597d706e	6784	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6785	// HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
bogdanm	82:6473597d706e	6786	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6787
bogdanm	82:6473597d706e	6788	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6789	/*!
bogdanm	82:6473597d706e	6790	* @brief HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
bogdanm	82:6473597d706e	6791	*
bogdanm	82:6473597d706e	6792	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6793	*/
bogdanm	82:6473597d706e	6794	typedef union _hw_enet_rmon_r_octets
bogdanm	82:6473597d706e	6795	{
bogdanm	82:6473597d706e	6796	uint32_t U;
bogdanm	82:6473597d706e	6797	struct _hw_enet_rmon_r_octets_bitfields
bogdanm	82:6473597d706e	6798	{
bogdanm	82:6473597d706e	6799	uint32_t COUNT : 32; //!< [31:0] Octet count
bogdanm	82:6473597d706e	6800	} B;
bogdanm	82:6473597d706e	6801	} hw_enet_rmon_r_octets_t;
bogdanm	82:6473597d706e	6802	#endif
bogdanm	82:6473597d706e	6803
bogdanm	82:6473597d706e	6804	/*!
bogdanm	82:6473597d706e	6805	* @name Constants and macros for entire ENET_RMON_R_OCTETS register
bogdanm	82:6473597d706e	6806	*/
bogdanm	82:6473597d706e	6807	//@{
bogdanm	82:6473597d706e	6808	#define HW_ENET_RMON_R_OCTETS_ADDR(x) (REGS_ENET_BASE(x) + 0x2C4U)
bogdanm	82:6473597d706e	6809
bogdanm	82:6473597d706e	6810	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6811	#define HW_ENET_RMON_R_OCTETS(x) ((__I hw_enet_rmon_r_octets_t ) HW_ENET_RMON_R_OCTETS_ADDR(x))
bogdanm	82:6473597d706e	6812	#define HW_ENET_RMON_R_OCTETS_RD(x) (HW_ENET_RMON_R_OCTETS(x).U)
bogdanm	82:6473597d706e	6813	#endif
bogdanm	82:6473597d706e	6814	//@}
bogdanm	82:6473597d706e	6815
bogdanm	82:6473597d706e	6816	/*
bogdanm	82:6473597d706e	6817	* Constants & macros for individual ENET_RMON_R_OCTETS bitfields
bogdanm	82:6473597d706e	6818	*/
bogdanm	82:6473597d706e	6819
bogdanm	82:6473597d706e	6820	/*!
bogdanm	82:6473597d706e	6821	* @name Register ENET_RMON_R_OCTETS, field COUNT[31:0] (RO)
bogdanm	82:6473597d706e	6822	*/
bogdanm	82:6473597d706e	6823	//@{
bogdanm	82:6473597d706e	6824	#define BP_ENET_RMON_R_OCTETS_COUNT (0U) //!< Bit position for ENET_RMON_R_OCTETS_COUNT.
bogdanm	82:6473597d706e	6825	#define BM_ENET_RMON_R_OCTETS_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_RMON_R_OCTETS_COUNT.
bogdanm	82:6473597d706e	6826	#define BS_ENET_RMON_R_OCTETS_COUNT (32U) //!< Bit field size in bits for ENET_RMON_R_OCTETS_COUNT.
bogdanm	82:6473597d706e	6827
bogdanm	82:6473597d706e	6828	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6829	//! @brief Read current value of the ENET_RMON_R_OCTETS_COUNT field.
bogdanm	82:6473597d706e	6830	#define BR_ENET_RMON_R_OCTETS_COUNT(x) (HW_ENET_RMON_R_OCTETS(x).U)
bogdanm	82:6473597d706e	6831	#endif
bogdanm	82:6473597d706e	6832	//@}
bogdanm	82:6473597d706e	6833
bogdanm	82:6473597d706e	6834	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6835	// HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
bogdanm	82:6473597d706e	6836	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6837
bogdanm	82:6473597d706e	6838	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6839	/*!
bogdanm	82:6473597d706e	6840	* @brief HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
bogdanm	82:6473597d706e	6841	*
bogdanm	82:6473597d706e	6842	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6843	*
bogdanm	82:6473597d706e	6844	* Counter increments if a frame with invalid or missing SFD character is
bogdanm	82:6473597d706e	6845	* detected and has been dropped. None of the other counters increments if this counter
bogdanm	82:6473597d706e	6846	* increments.
bogdanm	82:6473597d706e	6847	*/
bogdanm	82:6473597d706e	6848	typedef union _hw_enet_ieee_r_drop
bogdanm	82:6473597d706e	6849	{
bogdanm	82:6473597d706e	6850	uint32_t U;
bogdanm	82:6473597d706e	6851	struct _hw_enet_ieee_r_drop_bitfields
bogdanm	82:6473597d706e	6852	{
bogdanm	82:6473597d706e	6853	uint32_t COUNT : 16; //!< [15:0] Frame count
bogdanm	82:6473597d706e	6854	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6855	} B;
bogdanm	82:6473597d706e	6856	} hw_enet_ieee_r_drop_t;
bogdanm	82:6473597d706e	6857	#endif
bogdanm	82:6473597d706e	6858
bogdanm	82:6473597d706e	6859	/*!
bogdanm	82:6473597d706e	6860	* @name Constants and macros for entire ENET_IEEE_R_DROP register
bogdanm	82:6473597d706e	6861	*/
bogdanm	82:6473597d706e	6862	//@{
bogdanm	82:6473597d706e	6863	#define HW_ENET_IEEE_R_DROP_ADDR(x) (REGS_ENET_BASE(x) + 0x2C8U)
bogdanm	82:6473597d706e	6864
bogdanm	82:6473597d706e	6865	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6866	#define HW_ENET_IEEE_R_DROP(x) ((__I hw_enet_ieee_r_drop_t ) HW_ENET_IEEE_R_DROP_ADDR(x))
bogdanm	82:6473597d706e	6867	#define HW_ENET_IEEE_R_DROP_RD(x) (HW_ENET_IEEE_R_DROP(x).U)
bogdanm	82:6473597d706e	6868	#endif
bogdanm	82:6473597d706e	6869	//@}
bogdanm	82:6473597d706e	6870
bogdanm	82:6473597d706e	6871	/*
bogdanm	82:6473597d706e	6872	* Constants & macros for individual ENET_IEEE_R_DROP bitfields
bogdanm	82:6473597d706e	6873	*/
bogdanm	82:6473597d706e	6874
bogdanm	82:6473597d706e	6875	/*!
bogdanm	82:6473597d706e	6876	* @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6877	*/
bogdanm	82:6473597d706e	6878	//@{
bogdanm	82:6473597d706e	6879	#define BP_ENET_IEEE_R_DROP_COUNT (0U) //!< Bit position for ENET_IEEE_R_DROP_COUNT.
bogdanm	82:6473597d706e	6880	#define BM_ENET_IEEE_R_DROP_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_DROP_COUNT.
bogdanm	82:6473597d706e	6881	#define BS_ENET_IEEE_R_DROP_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_DROP_COUNT.
bogdanm	82:6473597d706e	6882
bogdanm	82:6473597d706e	6883	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6884	//! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field.
bogdanm	82:6473597d706e	6885	#define BR_ENET_IEEE_R_DROP_COUNT(x) (HW_ENET_IEEE_R_DROP(x).B.COUNT)
bogdanm	82:6473597d706e	6886	#endif
bogdanm	82:6473597d706e	6887	//@}
bogdanm	82:6473597d706e	6888
bogdanm	82:6473597d706e	6889	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6890	// HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
bogdanm	82:6473597d706e	6891	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6892
bogdanm	82:6473597d706e	6893	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6894	/*!
bogdanm	82:6473597d706e	6895	* @brief HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
bogdanm	82:6473597d706e	6896	*
bogdanm	82:6473597d706e	6897	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6898	*/
bogdanm	82:6473597d706e	6899	typedef union _hw_enet_ieee_r_frame_ok
bogdanm	82:6473597d706e	6900	{
bogdanm	82:6473597d706e	6901	uint32_t U;
bogdanm	82:6473597d706e	6902	struct _hw_enet_ieee_r_frame_ok_bitfields
bogdanm	82:6473597d706e	6903	{
bogdanm	82:6473597d706e	6904	uint32_t COUNT : 16; //!< [15:0] Frame count
bogdanm	82:6473597d706e	6905	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6906	} B;
bogdanm	82:6473597d706e	6907	} hw_enet_ieee_r_frame_ok_t;
bogdanm	82:6473597d706e	6908	#endif
bogdanm	82:6473597d706e	6909
bogdanm	82:6473597d706e	6910	/*!
bogdanm	82:6473597d706e	6911	* @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
bogdanm	82:6473597d706e	6912	*/
bogdanm	82:6473597d706e	6913	//@{
bogdanm	82:6473597d706e	6914	#define HW_ENET_IEEE_R_FRAME_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x2CCU)
bogdanm	82:6473597d706e	6915
bogdanm	82:6473597d706e	6916	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6917	#define HW_ENET_IEEE_R_FRAME_OK(x) ((__I hw_enet_ieee_r_frame_ok_t ) HW_ENET_IEEE_R_FRAME_OK_ADDR(x))
bogdanm	82:6473597d706e	6918	#define HW_ENET_IEEE_R_FRAME_OK_RD(x) (HW_ENET_IEEE_R_FRAME_OK(x).U)
bogdanm	82:6473597d706e	6919	#endif
bogdanm	82:6473597d706e	6920	//@}
bogdanm	82:6473597d706e	6921
bogdanm	82:6473597d706e	6922	/*
bogdanm	82:6473597d706e	6923	* Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
bogdanm	82:6473597d706e	6924	*/
bogdanm	82:6473597d706e	6925
bogdanm	82:6473597d706e	6926	/*!
bogdanm	82:6473597d706e	6927	* @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6928	*/
bogdanm	82:6473597d706e	6929	//@{
bogdanm	82:6473597d706e	6930	#define BP_ENET_IEEE_R_FRAME_OK_COUNT (0U) //!< Bit position for ENET_IEEE_R_FRAME_OK_COUNT.
bogdanm	82:6473597d706e	6931	#define BM_ENET_IEEE_R_FRAME_OK_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_FRAME_OK_COUNT.
bogdanm	82:6473597d706e	6932	#define BS_ENET_IEEE_R_FRAME_OK_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_FRAME_OK_COUNT.
bogdanm	82:6473597d706e	6933
bogdanm	82:6473597d706e	6934	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6935	//! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field.
bogdanm	82:6473597d706e	6936	#define BR_ENET_IEEE_R_FRAME_OK_COUNT(x) (HW_ENET_IEEE_R_FRAME_OK(x).B.COUNT)
bogdanm	82:6473597d706e	6937	#endif
bogdanm	82:6473597d706e	6938	//@}
bogdanm	82:6473597d706e	6939
bogdanm	82:6473597d706e	6940	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6941	// HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
bogdanm	82:6473597d706e	6942	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6943
bogdanm	82:6473597d706e	6944	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6945	/*!
bogdanm	82:6473597d706e	6946	* @brief HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
bogdanm	82:6473597d706e	6947	*
bogdanm	82:6473597d706e	6948	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	6949	*/
bogdanm	82:6473597d706e	6950	typedef union _hw_enet_ieee_r_crc
bogdanm	82:6473597d706e	6951	{
bogdanm	82:6473597d706e	6952	uint32_t U;
bogdanm	82:6473597d706e	6953	struct _hw_enet_ieee_r_crc_bitfields
bogdanm	82:6473597d706e	6954	{
bogdanm	82:6473597d706e	6955	uint32_t COUNT : 16; //!< [15:0] Frame count
bogdanm	82:6473597d706e	6956	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	6957	} B;
bogdanm	82:6473597d706e	6958	} hw_enet_ieee_r_crc_t;
bogdanm	82:6473597d706e	6959	#endif
bogdanm	82:6473597d706e	6960
bogdanm	82:6473597d706e	6961	/*!
bogdanm	82:6473597d706e	6962	* @name Constants and macros for entire ENET_IEEE_R_CRC register
bogdanm	82:6473597d706e	6963	*/
bogdanm	82:6473597d706e	6964	//@{
bogdanm	82:6473597d706e	6965	#define HW_ENET_IEEE_R_CRC_ADDR(x) (REGS_ENET_BASE(x) + 0x2D0U)
bogdanm	82:6473597d706e	6966
bogdanm	82:6473597d706e	6967	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6968	#define HW_ENET_IEEE_R_CRC(x) ((__I hw_enet_ieee_r_crc_t ) HW_ENET_IEEE_R_CRC_ADDR(x))
bogdanm	82:6473597d706e	6969	#define HW_ENET_IEEE_R_CRC_RD(x) (HW_ENET_IEEE_R_CRC(x).U)
bogdanm	82:6473597d706e	6970	#endif
bogdanm	82:6473597d706e	6971	//@}
bogdanm	82:6473597d706e	6972
bogdanm	82:6473597d706e	6973	/*
bogdanm	82:6473597d706e	6974	* Constants & macros for individual ENET_IEEE_R_CRC bitfields
bogdanm	82:6473597d706e	6975	*/
bogdanm	82:6473597d706e	6976
bogdanm	82:6473597d706e	6977	/*!
bogdanm	82:6473597d706e	6978	* @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	6979	*/
bogdanm	82:6473597d706e	6980	//@{
bogdanm	82:6473597d706e	6981	#define BP_ENET_IEEE_R_CRC_COUNT (0U) //!< Bit position for ENET_IEEE_R_CRC_COUNT.
bogdanm	82:6473597d706e	6982	#define BM_ENET_IEEE_R_CRC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_CRC_COUNT.
bogdanm	82:6473597d706e	6983	#define BS_ENET_IEEE_R_CRC_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_CRC_COUNT.
bogdanm	82:6473597d706e	6984
bogdanm	82:6473597d706e	6985	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6986	//! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field.
bogdanm	82:6473597d706e	6987	#define BR_ENET_IEEE_R_CRC_COUNT(x) (HW_ENET_IEEE_R_CRC(x).B.COUNT)
bogdanm	82:6473597d706e	6988	#endif
bogdanm	82:6473597d706e	6989	//@}
bogdanm	82:6473597d706e	6990
bogdanm	82:6473597d706e	6991	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6992	// HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
bogdanm	82:6473597d706e	6993	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	6994
bogdanm	82:6473597d706e	6995	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	6996	/*!
bogdanm	82:6473597d706e	6997	* @brief HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
bogdanm	82:6473597d706e	6998	*
bogdanm	82:6473597d706e	6999	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	7000	*/
bogdanm	82:6473597d706e	7001	typedef union _hw_enet_ieee_r_align
bogdanm	82:6473597d706e	7002	{
bogdanm	82:6473597d706e	7003	uint32_t U;
bogdanm	82:6473597d706e	7004	struct _hw_enet_ieee_r_align_bitfields
bogdanm	82:6473597d706e	7005	{
bogdanm	82:6473597d706e	7006	uint32_t COUNT : 16; //!< [15:0] Frame count
bogdanm	82:6473597d706e	7007	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	7008	} B;
bogdanm	82:6473597d706e	7009	} hw_enet_ieee_r_align_t;
bogdanm	82:6473597d706e	7010	#endif
bogdanm	82:6473597d706e	7011
bogdanm	82:6473597d706e	7012	/*!
bogdanm	82:6473597d706e	7013	* @name Constants and macros for entire ENET_IEEE_R_ALIGN register
bogdanm	82:6473597d706e	7014	*/
bogdanm	82:6473597d706e	7015	//@{
bogdanm	82:6473597d706e	7016	#define HW_ENET_IEEE_R_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x2D4U)
bogdanm	82:6473597d706e	7017
bogdanm	82:6473597d706e	7018	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7019	#define HW_ENET_IEEE_R_ALIGN(x) ((__I hw_enet_ieee_r_align_t ) HW_ENET_IEEE_R_ALIGN_ADDR(x))
bogdanm	82:6473597d706e	7020	#define HW_ENET_IEEE_R_ALIGN_RD(x) (HW_ENET_IEEE_R_ALIGN(x).U)
bogdanm	82:6473597d706e	7021	#endif
bogdanm	82:6473597d706e	7022	//@}
bogdanm	82:6473597d706e	7023
bogdanm	82:6473597d706e	7024	/*
bogdanm	82:6473597d706e	7025	* Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
bogdanm	82:6473597d706e	7026	*/
bogdanm	82:6473597d706e	7027
bogdanm	82:6473597d706e	7028	/*!
bogdanm	82:6473597d706e	7029	* @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	7030	*/
bogdanm	82:6473597d706e	7031	//@{
bogdanm	82:6473597d706e	7032	#define BP_ENET_IEEE_R_ALIGN_COUNT (0U) //!< Bit position for ENET_IEEE_R_ALIGN_COUNT.
bogdanm	82:6473597d706e	7033	#define BM_ENET_IEEE_R_ALIGN_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_ALIGN_COUNT.
bogdanm	82:6473597d706e	7034	#define BS_ENET_IEEE_R_ALIGN_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_ALIGN_COUNT.
bogdanm	82:6473597d706e	7035
bogdanm	82:6473597d706e	7036	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7037	//! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field.
bogdanm	82:6473597d706e	7038	#define BR_ENET_IEEE_R_ALIGN_COUNT(x) (HW_ENET_IEEE_R_ALIGN(x).B.COUNT)
bogdanm	82:6473597d706e	7039	#endif
bogdanm	82:6473597d706e	7040	//@}
bogdanm	82:6473597d706e	7041
bogdanm	82:6473597d706e	7042	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7043	// HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
bogdanm	82:6473597d706e	7044	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7045
bogdanm	82:6473597d706e	7046	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7047	/*!
bogdanm	82:6473597d706e	7048	* @brief HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
bogdanm	82:6473597d706e	7049	*
bogdanm	82:6473597d706e	7050	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	7051	*/
bogdanm	82:6473597d706e	7052	typedef union _hw_enet_ieee_r_macerr
bogdanm	82:6473597d706e	7053	{
bogdanm	82:6473597d706e	7054	uint32_t U;
bogdanm	82:6473597d706e	7055	struct _hw_enet_ieee_r_macerr_bitfields
bogdanm	82:6473597d706e	7056	{
bogdanm	82:6473597d706e	7057	uint32_t COUNT : 16; //!< [15:0] Count
bogdanm	82:6473597d706e	7058	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	7059	} B;
bogdanm	82:6473597d706e	7060	} hw_enet_ieee_r_macerr_t;
bogdanm	82:6473597d706e	7061	#endif
bogdanm	82:6473597d706e	7062
bogdanm	82:6473597d706e	7063	/*!
bogdanm	82:6473597d706e	7064	* @name Constants and macros for entire ENET_IEEE_R_MACERR register
bogdanm	82:6473597d706e	7065	*/
bogdanm	82:6473597d706e	7066	//@{
bogdanm	82:6473597d706e	7067	#define HW_ENET_IEEE_R_MACERR_ADDR(x) (REGS_ENET_BASE(x) + 0x2D8U)
bogdanm	82:6473597d706e	7068
bogdanm	82:6473597d706e	7069	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7070	#define HW_ENET_IEEE_R_MACERR(x) ((__I hw_enet_ieee_r_macerr_t ) HW_ENET_IEEE_R_MACERR_ADDR(x))
bogdanm	82:6473597d706e	7071	#define HW_ENET_IEEE_R_MACERR_RD(x) (HW_ENET_IEEE_R_MACERR(x).U)
bogdanm	82:6473597d706e	7072	#endif
bogdanm	82:6473597d706e	7073	//@}
bogdanm	82:6473597d706e	7074
bogdanm	82:6473597d706e	7075	/*
bogdanm	82:6473597d706e	7076	* Constants & macros for individual ENET_IEEE_R_MACERR bitfields
bogdanm	82:6473597d706e	7077	*/
bogdanm	82:6473597d706e	7078
bogdanm	82:6473597d706e	7079	/*!
bogdanm	82:6473597d706e	7080	* @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	7081	*/
bogdanm	82:6473597d706e	7082	//@{
bogdanm	82:6473597d706e	7083	#define BP_ENET_IEEE_R_MACERR_COUNT (0U) //!< Bit position for ENET_IEEE_R_MACERR_COUNT.
bogdanm	82:6473597d706e	7084	#define BM_ENET_IEEE_R_MACERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_MACERR_COUNT.
bogdanm	82:6473597d706e	7085	#define BS_ENET_IEEE_R_MACERR_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_MACERR_COUNT.
bogdanm	82:6473597d706e	7086
bogdanm	82:6473597d706e	7087	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7088	//! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field.
bogdanm	82:6473597d706e	7089	#define BR_ENET_IEEE_R_MACERR_COUNT(x) (HW_ENET_IEEE_R_MACERR(x).B.COUNT)
bogdanm	82:6473597d706e	7090	#endif
bogdanm	82:6473597d706e	7091	//@}
bogdanm	82:6473597d706e	7092
bogdanm	82:6473597d706e	7093	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7094	// HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
bogdanm	82:6473597d706e	7095	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7096
bogdanm	82:6473597d706e	7097	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7098	/*!
bogdanm	82:6473597d706e	7099	* @brief HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
bogdanm	82:6473597d706e	7100	*
bogdanm	82:6473597d706e	7101	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	7102	*/
bogdanm	82:6473597d706e	7103	typedef union _hw_enet_ieee_r_fdxfc
bogdanm	82:6473597d706e	7104	{
bogdanm	82:6473597d706e	7105	uint32_t U;
bogdanm	82:6473597d706e	7106	struct _hw_enet_ieee_r_fdxfc_bitfields
bogdanm	82:6473597d706e	7107	{
bogdanm	82:6473597d706e	7108	uint32_t COUNT : 16; //!< [15:0] Pause frame count
bogdanm	82:6473597d706e	7109	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	7110	} B;
bogdanm	82:6473597d706e	7111	} hw_enet_ieee_r_fdxfc_t;
bogdanm	82:6473597d706e	7112	#endif
bogdanm	82:6473597d706e	7113
bogdanm	82:6473597d706e	7114	/*!
bogdanm	82:6473597d706e	7115	* @name Constants and macros for entire ENET_IEEE_R_FDXFC register
bogdanm	82:6473597d706e	7116	*/
bogdanm	82:6473597d706e	7117	//@{
bogdanm	82:6473597d706e	7118	#define HW_ENET_IEEE_R_FDXFC_ADDR(x) (REGS_ENET_BASE(x) + 0x2DCU)
bogdanm	82:6473597d706e	7119
bogdanm	82:6473597d706e	7120	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7121	#define HW_ENET_IEEE_R_FDXFC(x) ((__I hw_enet_ieee_r_fdxfc_t ) HW_ENET_IEEE_R_FDXFC_ADDR(x))
bogdanm	82:6473597d706e	7122	#define HW_ENET_IEEE_R_FDXFC_RD(x) (HW_ENET_IEEE_R_FDXFC(x).U)
bogdanm	82:6473597d706e	7123	#endif
bogdanm	82:6473597d706e	7124	//@}
bogdanm	82:6473597d706e	7125
bogdanm	82:6473597d706e	7126	/*
bogdanm	82:6473597d706e	7127	* Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
bogdanm	82:6473597d706e	7128	*/
bogdanm	82:6473597d706e	7129
bogdanm	82:6473597d706e	7130	/*!
bogdanm	82:6473597d706e	7131	* @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
bogdanm	82:6473597d706e	7132	*/
bogdanm	82:6473597d706e	7133	//@{
bogdanm	82:6473597d706e	7134	#define BP_ENET_IEEE_R_FDXFC_COUNT (0U) //!< Bit position for ENET_IEEE_R_FDXFC_COUNT.
bogdanm	82:6473597d706e	7135	#define BM_ENET_IEEE_R_FDXFC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_FDXFC_COUNT.
bogdanm	82:6473597d706e	7136	#define BS_ENET_IEEE_R_FDXFC_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_FDXFC_COUNT.
bogdanm	82:6473597d706e	7137
bogdanm	82:6473597d706e	7138	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7139	//! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field.
bogdanm	82:6473597d706e	7140	#define BR_ENET_IEEE_R_FDXFC_COUNT(x) (HW_ENET_IEEE_R_FDXFC(x).B.COUNT)
bogdanm	82:6473597d706e	7141	#endif
bogdanm	82:6473597d706e	7142	//@}
bogdanm	82:6473597d706e	7143
bogdanm	82:6473597d706e	7144	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7145	// HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
bogdanm	82:6473597d706e	7146	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7147
bogdanm	82:6473597d706e	7148	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7149	/*!
bogdanm	82:6473597d706e	7150	* @brief HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
bogdanm	82:6473597d706e	7151	*
bogdanm	82:6473597d706e	7152	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	7153	*/
bogdanm	82:6473597d706e	7154	typedef union _hw_enet_ieee_r_octets_ok
bogdanm	82:6473597d706e	7155	{
bogdanm	82:6473597d706e	7156	uint32_t U;
bogdanm	82:6473597d706e	7157	struct _hw_enet_ieee_r_octets_ok_bitfields
bogdanm	82:6473597d706e	7158	{
bogdanm	82:6473597d706e	7159	uint32_t COUNT : 32; //!< [31:0] Octet count
bogdanm	82:6473597d706e	7160	} B;
bogdanm	82:6473597d706e	7161	} hw_enet_ieee_r_octets_ok_t;
bogdanm	82:6473597d706e	7162	#endif
bogdanm	82:6473597d706e	7163
bogdanm	82:6473597d706e	7164	/*!
bogdanm	82:6473597d706e	7165	* @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
bogdanm	82:6473597d706e	7166	*/
bogdanm	82:6473597d706e	7167	//@{
bogdanm	82:6473597d706e	7168	#define HW_ENET_IEEE_R_OCTETS_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x2E0U)
bogdanm	82:6473597d706e	7169
bogdanm	82:6473597d706e	7170	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7171	#define HW_ENET_IEEE_R_OCTETS_OK(x) ((__I hw_enet_ieee_r_octets_ok_t ) HW_ENET_IEEE_R_OCTETS_OK_ADDR(x))
bogdanm	82:6473597d706e	7172	#define HW_ENET_IEEE_R_OCTETS_OK_RD(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
bogdanm	82:6473597d706e	7173	#endif
bogdanm	82:6473597d706e	7174	//@}
bogdanm	82:6473597d706e	7175
bogdanm	82:6473597d706e	7176	/*
bogdanm	82:6473597d706e	7177	* Constants & macros for individual ENET_IEEE_R_OCTETS_OK bitfields
bogdanm	82:6473597d706e	7178	*/
bogdanm	82:6473597d706e	7179
bogdanm	82:6473597d706e	7180	/*!
bogdanm	82:6473597d706e	7181	* @name Register ENET_IEEE_R_OCTETS_OK, field COUNT[31:0] (RO)
bogdanm	82:6473597d706e	7182	*/
bogdanm	82:6473597d706e	7183	//@{
bogdanm	82:6473597d706e	7184	#define BP_ENET_IEEE_R_OCTETS_OK_COUNT (0U) //!< Bit position for ENET_IEEE_R_OCTETS_OK_COUNT.
bogdanm	82:6473597d706e	7185	#define BM_ENET_IEEE_R_OCTETS_OK_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_IEEE_R_OCTETS_OK_COUNT.
bogdanm	82:6473597d706e	7186	#define BS_ENET_IEEE_R_OCTETS_OK_COUNT (32U) //!< Bit field size in bits for ENET_IEEE_R_OCTETS_OK_COUNT.
bogdanm	82:6473597d706e	7187
bogdanm	82:6473597d706e	7188	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7189	//! @brief Read current value of the ENET_IEEE_R_OCTETS_OK_COUNT field.
bogdanm	82:6473597d706e	7190	#define BR_ENET_IEEE_R_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
bogdanm	82:6473597d706e	7191	#endif
bogdanm	82:6473597d706e	7192	//@}
bogdanm	82:6473597d706e	7193
bogdanm	82:6473597d706e	7194	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7195	// HW_ENET_ATCR - Adjustable Timer Control Register
bogdanm	82:6473597d706e	7196	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7197
bogdanm	82:6473597d706e	7198	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7199	/*!
bogdanm	82:6473597d706e	7200	* @brief HW_ENET_ATCR - Adjustable Timer Control Register (RW)
bogdanm	82:6473597d706e	7201	*
bogdanm	82:6473597d706e	7202	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	7203	*
bogdanm	82:6473597d706e	7204	* ATCR command fields can trigger the corresponding events directly. It is not
bogdanm	82:6473597d706e	7205	* necessary to preserve any of the configuration fields when a command field is
bogdanm	82:6473597d706e	7206	* set in the register, that is, no read-modify-write is required. The fields are
bogdanm	82:6473597d706e	7207	* automatically cleared after the command completes.
bogdanm	82:6473597d706e	7208	*/
bogdanm	82:6473597d706e	7209	typedef union _hw_enet_atcr
bogdanm	82:6473597d706e	7210	{
bogdanm	82:6473597d706e	7211	uint32_t U;
bogdanm	82:6473597d706e	7212	struct _hw_enet_atcr_bitfields
bogdanm	82:6473597d706e	7213	{
bogdanm	82:6473597d706e	7214	uint32_t EN : 1; //!< [0] Enable Timer
bogdanm	82:6473597d706e	7215	uint32_t RESERVED0 : 1; //!< [1]
bogdanm	82:6473597d706e	7216	uint32_t OFFEN : 1; //!< [2] Enable One-Shot Offset Event
bogdanm	82:6473597d706e	7217	uint32_t OFFRST : 1; //!< [3] Reset Timer On Offset Event
bogdanm	82:6473597d706e	7218	uint32_t PEREN : 1; //!< [4] Enable Periodical Event
bogdanm	82:6473597d706e	7219	uint32_t RESERVED1 : 2; //!< [6:5]
bogdanm	82:6473597d706e	7220	uint32_t PINPER : 1; //!< [7]
bogdanm	82:6473597d706e	7221	uint32_t RESERVED2 : 1; //!< [8]
bogdanm	82:6473597d706e	7222	uint32_t RESTART : 1; //!< [9] Reset Timer
bogdanm	82:6473597d706e	7223	uint32_t RESERVED3 : 1; //!< [10]
bogdanm	82:6473597d706e	7224	uint32_t CAPTURE : 1; //!< [11] Capture Timer Value
bogdanm	82:6473597d706e	7225	uint32_t RESERVED4 : 1; //!< [12]
bogdanm	82:6473597d706e	7226	uint32_t SLAVE : 1; //!< [13] Enable Timer Slave Mode
bogdanm	82:6473597d706e	7227	uint32_t RESERVED5 : 18; //!< [31:14]
bogdanm	82:6473597d706e	7228	} B;
bogdanm	82:6473597d706e	7229	} hw_enet_atcr_t;
bogdanm	82:6473597d706e	7230	#endif
bogdanm	82:6473597d706e	7231
bogdanm	82:6473597d706e	7232	/*!
bogdanm	82:6473597d706e	7233	* @name Constants and macros for entire ENET_ATCR register
bogdanm	82:6473597d706e	7234	*/
bogdanm	82:6473597d706e	7235	//@{
bogdanm	82:6473597d706e	7236	#define HW_ENET_ATCR_ADDR(x) (REGS_ENET_BASE(x) + 0x400U)
bogdanm	82:6473597d706e	7237
bogdanm	82:6473597d706e	7238	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7239	#define HW_ENET_ATCR(x) ((__IO hw_enet_atcr_t ) HW_ENET_ATCR_ADDR(x))
bogdanm	82:6473597d706e	7240	#define HW_ENET_ATCR_RD(x) (HW_ENET_ATCR(x).U)
bogdanm	82:6473597d706e	7241	#define HW_ENET_ATCR_WR(x, v) (HW_ENET_ATCR(x).U = (v))
bogdanm	82:6473597d706e	7242	#define HW_ENET_ATCR_SET(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) \| (v)))
bogdanm	82:6473597d706e	7243	#define HW_ENET_ATCR_CLR(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	7244	#define HW_ENET_ATCR_TOG(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	7245	#endif
bogdanm	82:6473597d706e	7246	//@}
bogdanm	82:6473597d706e	7247
bogdanm	82:6473597d706e	7248	/*
bogdanm	82:6473597d706e	7249	* Constants & macros for individual ENET_ATCR bitfields
bogdanm	82:6473597d706e	7250	*/
bogdanm	82:6473597d706e	7251
bogdanm	82:6473597d706e	7252	/*!
bogdanm	82:6473597d706e	7253	* @name Register ENET_ATCR, field EN[0] (RW)
bogdanm	82:6473597d706e	7254	*
bogdanm	82:6473597d706e	7255	* Values:
bogdanm	82:6473597d706e	7256	* - 0 - The timer stops at the current value.
bogdanm	82:6473597d706e	7257	* - 1 - The timer starts incrementing.
bogdanm	82:6473597d706e	7258	*/
bogdanm	82:6473597d706e	7259	//@{
bogdanm	82:6473597d706e	7260	#define BP_ENET_ATCR_EN (0U) //!< Bit position for ENET_ATCR_EN.
bogdanm	82:6473597d706e	7261	#define BM_ENET_ATCR_EN (0x00000001U) //!< Bit mask for ENET_ATCR_EN.
bogdanm	82:6473597d706e	7262	#define BS_ENET_ATCR_EN (1U) //!< Bit field size in bits for ENET_ATCR_EN.
bogdanm	82:6473597d706e	7263
bogdanm	82:6473597d706e	7264	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7265	//! @brief Read current value of the ENET_ATCR_EN field.
bogdanm	82:6473597d706e	7266	#define BR_ENET_ATCR_EN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN))
bogdanm	82:6473597d706e	7267	#endif
bogdanm	82:6473597d706e	7268
bogdanm	82:6473597d706e	7269	//! @brief Format value for bitfield ENET_ATCR_EN.
bogdanm	82:6473597d706e	7270	#define BF_ENET_ATCR_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_EN), uint32_t) & BM_ENET_ATCR_EN)
bogdanm	82:6473597d706e	7271
bogdanm	82:6473597d706e	7272	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7273	//! @brief Set the EN field to a new value.
bogdanm	82:6473597d706e	7274	#define BW_ENET_ATCR_EN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN) = (v))
bogdanm	82:6473597d706e	7275	#endif
bogdanm	82:6473597d706e	7276	//@}
bogdanm	82:6473597d706e	7277
bogdanm	82:6473597d706e	7278	/*!
bogdanm	82:6473597d706e	7279	* @name Register ENET_ATCR, field OFFEN[2] (RW)
bogdanm	82:6473597d706e	7280	*
bogdanm	82:6473597d706e	7281	* Values:
bogdanm	82:6473597d706e	7282	* - 0 - Disable.
bogdanm	82:6473597d706e	7283	* - 1 - The timer can be reset to zero when the given offset time is reached
bogdanm	82:6473597d706e	7284	* (offset event). The field is cleared when the offset event is reached, so no
bogdanm	82:6473597d706e	7285	* further event occurs until the field is set again. The timer offset value
bogdanm	82:6473597d706e	7286	* must be set before setting this field.
bogdanm	82:6473597d706e	7287	*/
bogdanm	82:6473597d706e	7288	//@{
bogdanm	82:6473597d706e	7289	#define BP_ENET_ATCR_OFFEN (2U) //!< Bit position for ENET_ATCR_OFFEN.
bogdanm	82:6473597d706e	7290	#define BM_ENET_ATCR_OFFEN (0x00000004U) //!< Bit mask for ENET_ATCR_OFFEN.
bogdanm	82:6473597d706e	7291	#define BS_ENET_ATCR_OFFEN (1U) //!< Bit field size in bits for ENET_ATCR_OFFEN.
bogdanm	82:6473597d706e	7292
bogdanm	82:6473597d706e	7293	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7294	//! @brief Read current value of the ENET_ATCR_OFFEN field.
bogdanm	82:6473597d706e	7295	#define BR_ENET_ATCR_OFFEN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN))
bogdanm	82:6473597d706e	7296	#endif
bogdanm	82:6473597d706e	7297
bogdanm	82:6473597d706e	7298	//! @brief Format value for bitfield ENET_ATCR_OFFEN.
bogdanm	82:6473597d706e	7299	#define BF_ENET_ATCR_OFFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_OFFEN), uint32_t) & BM_ENET_ATCR_OFFEN)
bogdanm	82:6473597d706e	7300
bogdanm	82:6473597d706e	7301	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7302	//! @brief Set the OFFEN field to a new value.
bogdanm	82:6473597d706e	7303	#define BW_ENET_ATCR_OFFEN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN) = (v))
bogdanm	82:6473597d706e	7304	#endif
bogdanm	82:6473597d706e	7305	//@}
bogdanm	82:6473597d706e	7306
bogdanm	82:6473597d706e	7307	/*!
bogdanm	82:6473597d706e	7308	* @name Register ENET_ATCR, field OFFRST[3] (RW)
bogdanm	82:6473597d706e	7309	*
bogdanm	82:6473597d706e	7310	* Values:
bogdanm	82:6473597d706e	7311	* - 0 - The timer is not affected and no action occurs, besides clearing OFFEN,
bogdanm	82:6473597d706e	7312	* when the offset is reached.
bogdanm	82:6473597d706e	7313	* - 1 - If OFFEN is set, the timer resets to zero when the offset setting is
bogdanm	82:6473597d706e	7314	* reached. The offset event does not cause a timer interrupt.
bogdanm	82:6473597d706e	7315	*/
bogdanm	82:6473597d706e	7316	//@{
bogdanm	82:6473597d706e	7317	#define BP_ENET_ATCR_OFFRST (3U) //!< Bit position for ENET_ATCR_OFFRST.
bogdanm	82:6473597d706e	7318	#define BM_ENET_ATCR_OFFRST (0x00000008U) //!< Bit mask for ENET_ATCR_OFFRST.
bogdanm	82:6473597d706e	7319	#define BS_ENET_ATCR_OFFRST (1U) //!< Bit field size in bits for ENET_ATCR_OFFRST.
bogdanm	82:6473597d706e	7320
bogdanm	82:6473597d706e	7321	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7322	//! @brief Read current value of the ENET_ATCR_OFFRST field.
bogdanm	82:6473597d706e	7323	#define BR_ENET_ATCR_OFFRST(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST))
bogdanm	82:6473597d706e	7324	#endif
bogdanm	82:6473597d706e	7325
bogdanm	82:6473597d706e	7326	//! @brief Format value for bitfield ENET_ATCR_OFFRST.
bogdanm	82:6473597d706e	7327	#define BF_ENET_ATCR_OFFRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_OFFRST), uint32_t) & BM_ENET_ATCR_OFFRST)
bogdanm	82:6473597d706e	7328
bogdanm	82:6473597d706e	7329	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7330	//! @brief Set the OFFRST field to a new value.
bogdanm	82:6473597d706e	7331	#define BW_ENET_ATCR_OFFRST(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST) = (v))
bogdanm	82:6473597d706e	7332	#endif
bogdanm	82:6473597d706e	7333	//@}
bogdanm	82:6473597d706e	7334
bogdanm	82:6473597d706e	7335	/*!
bogdanm	82:6473597d706e	7336	* @name Register ENET_ATCR, field PEREN[4] (RW)
bogdanm	82:6473597d706e	7337	*
bogdanm	82:6473597d706e	7338	* Values:
bogdanm	82:6473597d706e	7339	* - 0 - Disable.
bogdanm	82:6473597d706e	7340	* - 1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the event
bogdanm	82:6473597d706e	7341	* signal output is asserted when the timer wraps around according to the
bogdanm	82:6473597d706e	7342	* periodic setting ATPER. The timer period value must be set before setting
bogdanm	82:6473597d706e	7343	* this bit. Not all devices contain the event signal output. See the chip
bogdanm	82:6473597d706e	7344	* configuration details.
bogdanm	82:6473597d706e	7345	*/
bogdanm	82:6473597d706e	7346	//@{
bogdanm	82:6473597d706e	7347	#define BP_ENET_ATCR_PEREN (4U) //!< Bit position for ENET_ATCR_PEREN.
bogdanm	82:6473597d706e	7348	#define BM_ENET_ATCR_PEREN (0x00000010U) //!< Bit mask for ENET_ATCR_PEREN.
bogdanm	82:6473597d706e	7349	#define BS_ENET_ATCR_PEREN (1U) //!< Bit field size in bits for ENET_ATCR_PEREN.
bogdanm	82:6473597d706e	7350
bogdanm	82:6473597d706e	7351	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7352	//! @brief Read current value of the ENET_ATCR_PEREN field.
bogdanm	82:6473597d706e	7353	#define BR_ENET_ATCR_PEREN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN))
bogdanm	82:6473597d706e	7354	#endif
bogdanm	82:6473597d706e	7355
bogdanm	82:6473597d706e	7356	//! @brief Format value for bitfield ENET_ATCR_PEREN.
bogdanm	82:6473597d706e	7357	#define BF_ENET_ATCR_PEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_PEREN), uint32_t) & BM_ENET_ATCR_PEREN)
bogdanm	82:6473597d706e	7358
bogdanm	82:6473597d706e	7359	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7360	//! @brief Set the PEREN field to a new value.
bogdanm	82:6473597d706e	7361	#define BW_ENET_ATCR_PEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN) = (v))
bogdanm	82:6473597d706e	7362	#endif
bogdanm	82:6473597d706e	7363	//@}
bogdanm	82:6473597d706e	7364
bogdanm	82:6473597d706e	7365	/*!
bogdanm	82:6473597d706e	7366	* @name Register ENET_ATCR, field PINPER[7] (RW)
bogdanm	82:6473597d706e	7367	*
bogdanm	82:6473597d706e	7368	* Enables event signal output assertion on period event. Not all devices
bogdanm	82:6473597d706e	7369	* contain the event signal output. See the chip configuration details.
bogdanm	82:6473597d706e	7370	*
bogdanm	82:6473597d706e	7371	* Values:
bogdanm	82:6473597d706e	7372	* - 0 - Disable.
bogdanm	82:6473597d706e	7373	* - 1 - Enable.
bogdanm	82:6473597d706e	7374	*/
bogdanm	82:6473597d706e	7375	//@{
bogdanm	82:6473597d706e	7376	#define BP_ENET_ATCR_PINPER (7U) //!< Bit position for ENET_ATCR_PINPER.
bogdanm	82:6473597d706e	7377	#define BM_ENET_ATCR_PINPER (0x00000080U) //!< Bit mask for ENET_ATCR_PINPER.
bogdanm	82:6473597d706e	7378	#define BS_ENET_ATCR_PINPER (1U) //!< Bit field size in bits for ENET_ATCR_PINPER.
bogdanm	82:6473597d706e	7379
bogdanm	82:6473597d706e	7380	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7381	//! @brief Read current value of the ENET_ATCR_PINPER field.
bogdanm	82:6473597d706e	7382	#define BR_ENET_ATCR_PINPER(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER))
bogdanm	82:6473597d706e	7383	#endif
bogdanm	82:6473597d706e	7384
bogdanm	82:6473597d706e	7385	//! @brief Format value for bitfield ENET_ATCR_PINPER.
bogdanm	82:6473597d706e	7386	#define BF_ENET_ATCR_PINPER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_PINPER), uint32_t) & BM_ENET_ATCR_PINPER)
bogdanm	82:6473597d706e	7387
bogdanm	82:6473597d706e	7388	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7389	//! @brief Set the PINPER field to a new value.
bogdanm	82:6473597d706e	7390	#define BW_ENET_ATCR_PINPER(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER) = (v))
bogdanm	82:6473597d706e	7391	#endif
bogdanm	82:6473597d706e	7392	//@}
bogdanm	82:6473597d706e	7393
bogdanm	82:6473597d706e	7394	/*!
bogdanm	82:6473597d706e	7395	* @name Register ENET_ATCR, field RESTART[9] (RW)
bogdanm	82:6473597d706e	7396	*
bogdanm	82:6473597d706e	7397	* Resets the timer to zero. This has no effect on the counter enable. If the
bogdanm	82:6473597d706e	7398	* counter is enabled when this field is set, the timer is reset to zero and starts
bogdanm	82:6473597d706e	7399	* counting from there. When set, all other fields are ignored during a write.
bogdanm	82:6473597d706e	7400	*/
bogdanm	82:6473597d706e	7401	//@{
bogdanm	82:6473597d706e	7402	#define BP_ENET_ATCR_RESTART (9U) //!< Bit position for ENET_ATCR_RESTART.
bogdanm	82:6473597d706e	7403	#define BM_ENET_ATCR_RESTART (0x00000200U) //!< Bit mask for ENET_ATCR_RESTART.
bogdanm	82:6473597d706e	7404	#define BS_ENET_ATCR_RESTART (1U) //!< Bit field size in bits for ENET_ATCR_RESTART.
bogdanm	82:6473597d706e	7405
bogdanm	82:6473597d706e	7406	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7407	//! @brief Read current value of the ENET_ATCR_RESTART field.
bogdanm	82:6473597d706e	7408	#define BR_ENET_ATCR_RESTART(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART))
bogdanm	82:6473597d706e	7409	#endif
bogdanm	82:6473597d706e	7410
bogdanm	82:6473597d706e	7411	//! @brief Format value for bitfield ENET_ATCR_RESTART.
bogdanm	82:6473597d706e	7412	#define BF_ENET_ATCR_RESTART(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_RESTART), uint32_t) & BM_ENET_ATCR_RESTART)
bogdanm	82:6473597d706e	7413
bogdanm	82:6473597d706e	7414	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7415	//! @brief Set the RESTART field to a new value.
bogdanm	82:6473597d706e	7416	#define BW_ENET_ATCR_RESTART(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART) = (v))
bogdanm	82:6473597d706e	7417	#endif
bogdanm	82:6473597d706e	7418	//@}
bogdanm	82:6473597d706e	7419
bogdanm	82:6473597d706e	7420	/*!
bogdanm	82:6473597d706e	7421	* @name Register ENET_ATCR, field CAPTURE[11] (RW)
bogdanm	82:6473597d706e	7422	*
bogdanm	82:6473597d706e	7423	* Values:
bogdanm	82:6473597d706e	7424	* - 0 - No effect.
bogdanm	82:6473597d706e	7425	* - 1 - The current time is captured and can be read from the ATVR register.
bogdanm	82:6473597d706e	7426	*/
bogdanm	82:6473597d706e	7427	//@{
bogdanm	82:6473597d706e	7428	#define BP_ENET_ATCR_CAPTURE (11U) //!< Bit position for ENET_ATCR_CAPTURE.
bogdanm	82:6473597d706e	7429	#define BM_ENET_ATCR_CAPTURE (0x00000800U) //!< Bit mask for ENET_ATCR_CAPTURE.
bogdanm	82:6473597d706e	7430	#define BS_ENET_ATCR_CAPTURE (1U) //!< Bit field size in bits for ENET_ATCR_CAPTURE.
bogdanm	82:6473597d706e	7431
bogdanm	82:6473597d706e	7432	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7433	//! @brief Read current value of the ENET_ATCR_CAPTURE field.
bogdanm	82:6473597d706e	7434	#define BR_ENET_ATCR_CAPTURE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE))
bogdanm	82:6473597d706e	7435	#endif
bogdanm	82:6473597d706e	7436
bogdanm	82:6473597d706e	7437	//! @brief Format value for bitfield ENET_ATCR_CAPTURE.
bogdanm	82:6473597d706e	7438	#define BF_ENET_ATCR_CAPTURE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_CAPTURE), uint32_t) & BM_ENET_ATCR_CAPTURE)
bogdanm	82:6473597d706e	7439
bogdanm	82:6473597d706e	7440	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7441	//! @brief Set the CAPTURE field to a new value.
bogdanm	82:6473597d706e	7442	#define BW_ENET_ATCR_CAPTURE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE) = (v))
bogdanm	82:6473597d706e	7443	#endif
bogdanm	82:6473597d706e	7444	//@}
bogdanm	82:6473597d706e	7445
bogdanm	82:6473597d706e	7446	/*!
bogdanm	82:6473597d706e	7447	* @name Register ENET_ATCR, field SLAVE[13] (RW)
bogdanm	82:6473597d706e	7448	*
bogdanm	82:6473597d706e	7449	* Values:
bogdanm	82:6473597d706e	7450	* - 0 - The timer is active and all configuration fields in this register are
bogdanm	82:6473597d706e	7451	* relevant.
bogdanm	82:6473597d706e	7452	* - 1 - The internal timer is disabled and the externally provided timer value
bogdanm	82:6473597d706e	7453	* is used. All other fields, except CAPTURE, in this register have no
bogdanm	82:6473597d706e	7454	* effect. CAPTURE can still be used to capture the current timer value.
bogdanm	82:6473597d706e	7455	*/
bogdanm	82:6473597d706e	7456	//@{
bogdanm	82:6473597d706e	7457	#define BP_ENET_ATCR_SLAVE (13U) //!< Bit position for ENET_ATCR_SLAVE.
bogdanm	82:6473597d706e	7458	#define BM_ENET_ATCR_SLAVE (0x00002000U) //!< Bit mask for ENET_ATCR_SLAVE.
bogdanm	82:6473597d706e	7459	#define BS_ENET_ATCR_SLAVE (1U) //!< Bit field size in bits for ENET_ATCR_SLAVE.
bogdanm	82:6473597d706e	7460
bogdanm	82:6473597d706e	7461	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7462	//! @brief Read current value of the ENET_ATCR_SLAVE field.
bogdanm	82:6473597d706e	7463	#define BR_ENET_ATCR_SLAVE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE))
bogdanm	82:6473597d706e	7464	#endif
bogdanm	82:6473597d706e	7465
bogdanm	82:6473597d706e	7466	//! @brief Format value for bitfield ENET_ATCR_SLAVE.
bogdanm	82:6473597d706e	7467	#define BF_ENET_ATCR_SLAVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_SLAVE), uint32_t) & BM_ENET_ATCR_SLAVE)
bogdanm	82:6473597d706e	7468
bogdanm	82:6473597d706e	7469	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7470	//! @brief Set the SLAVE field to a new value.
bogdanm	82:6473597d706e	7471	#define BW_ENET_ATCR_SLAVE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE) = (v))
bogdanm	82:6473597d706e	7472	#endif
bogdanm	82:6473597d706e	7473	//@}
bogdanm	82:6473597d706e	7474
bogdanm	82:6473597d706e	7475	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7476	// HW_ENET_ATVR - Timer Value Register
bogdanm	82:6473597d706e	7477	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7478
bogdanm	82:6473597d706e	7479	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7480	/*!
bogdanm	82:6473597d706e	7481	* @brief HW_ENET_ATVR - Timer Value Register (RW)
bogdanm	82:6473597d706e	7482	*
bogdanm	82:6473597d706e	7483	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	7484	*/
bogdanm	82:6473597d706e	7485	typedef union _hw_enet_atvr
bogdanm	82:6473597d706e	7486	{
bogdanm	82:6473597d706e	7487	uint32_t U;
bogdanm	82:6473597d706e	7488	struct _hw_enet_atvr_bitfields
bogdanm	82:6473597d706e	7489	{
bogdanm	82:6473597d706e	7490	uint32_t ATIME : 32; //!< [31:0]
bogdanm	82:6473597d706e	7491	} B;
bogdanm	82:6473597d706e	7492	} hw_enet_atvr_t;
bogdanm	82:6473597d706e	7493	#endif
bogdanm	82:6473597d706e	7494
bogdanm	82:6473597d706e	7495	/*!
bogdanm	82:6473597d706e	7496	* @name Constants and macros for entire ENET_ATVR register
bogdanm	82:6473597d706e	7497	*/
bogdanm	82:6473597d706e	7498	//@{
bogdanm	82:6473597d706e	7499	#define HW_ENET_ATVR_ADDR(x) (REGS_ENET_BASE(x) + 0x404U)
bogdanm	82:6473597d706e	7500
bogdanm	82:6473597d706e	7501	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7502	#define HW_ENET_ATVR(x) ((__IO hw_enet_atvr_t ) HW_ENET_ATVR_ADDR(x))
bogdanm	82:6473597d706e	7503	#define HW_ENET_ATVR_RD(x) (HW_ENET_ATVR(x).U)
bogdanm	82:6473597d706e	7504	#define HW_ENET_ATVR_WR(x, v) (HW_ENET_ATVR(x).U = (v))
bogdanm	82:6473597d706e	7505	#define HW_ENET_ATVR_SET(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) \| (v)))
bogdanm	82:6473597d706e	7506	#define HW_ENET_ATVR_CLR(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	7507	#define HW_ENET_ATVR_TOG(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	7508	#endif
bogdanm	82:6473597d706e	7509	//@}
bogdanm	82:6473597d706e	7510
bogdanm	82:6473597d706e	7511	/*
bogdanm	82:6473597d706e	7512	* Constants & macros for individual ENET_ATVR bitfields
bogdanm	82:6473597d706e	7513	*/
bogdanm	82:6473597d706e	7514
bogdanm	82:6473597d706e	7515	/*!
bogdanm	82:6473597d706e	7516	* @name Register ENET_ATVR, field ATIME[31:0] (RW)
bogdanm	82:6473597d706e	7517	*
bogdanm	82:6473597d706e	7518	* A write sets the timer. A read returns the last captured value. To read the
bogdanm	82:6473597d706e	7519	* current value, issue a capture command (set ATCR[CAPTURE]) prior to reading
bogdanm	82:6473597d706e	7520	* this register.
bogdanm	82:6473597d706e	7521	*/
bogdanm	82:6473597d706e	7522	//@{
bogdanm	82:6473597d706e	7523	#define BP_ENET_ATVR_ATIME (0U) //!< Bit position for ENET_ATVR_ATIME.
bogdanm	82:6473597d706e	7524	#define BM_ENET_ATVR_ATIME (0xFFFFFFFFU) //!< Bit mask for ENET_ATVR_ATIME.
bogdanm	82:6473597d706e	7525	#define BS_ENET_ATVR_ATIME (32U) //!< Bit field size in bits for ENET_ATVR_ATIME.
bogdanm	82:6473597d706e	7526
bogdanm	82:6473597d706e	7527	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7528	//! @brief Read current value of the ENET_ATVR_ATIME field.
bogdanm	82:6473597d706e	7529	#define BR_ENET_ATVR_ATIME(x) (HW_ENET_ATVR(x).U)
bogdanm	82:6473597d706e	7530	#endif
bogdanm	82:6473597d706e	7531
bogdanm	82:6473597d706e	7532	//! @brief Format value for bitfield ENET_ATVR_ATIME.
bogdanm	82:6473597d706e	7533	#define BF_ENET_ATVR_ATIME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATVR_ATIME), uint32_t) & BM_ENET_ATVR_ATIME)
bogdanm	82:6473597d706e	7534
bogdanm	82:6473597d706e	7535	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7536	//! @brief Set the ATIME field to a new value.
bogdanm	82:6473597d706e	7537	#define BW_ENET_ATVR_ATIME(x, v) (HW_ENET_ATVR_WR(x, v))
bogdanm	82:6473597d706e	7538	#endif
bogdanm	82:6473597d706e	7539	//@}
bogdanm	82:6473597d706e	7540
bogdanm	82:6473597d706e	7541	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7542	// HW_ENET_ATOFF - Timer Offset Register
bogdanm	82:6473597d706e	7543	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7544
bogdanm	82:6473597d706e	7545	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7546	/*!
bogdanm	82:6473597d706e	7547	* @brief HW_ENET_ATOFF - Timer Offset Register (RW)
bogdanm	82:6473597d706e	7548	*
bogdanm	82:6473597d706e	7549	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	7550	*/
bogdanm	82:6473597d706e	7551	typedef union _hw_enet_atoff
bogdanm	82:6473597d706e	7552	{
bogdanm	82:6473597d706e	7553	uint32_t U;
bogdanm	82:6473597d706e	7554	struct _hw_enet_atoff_bitfields
bogdanm	82:6473597d706e	7555	{
bogdanm	82:6473597d706e	7556	uint32_t OFFSET : 32; //!< [31:0]
bogdanm	82:6473597d706e	7557	} B;
bogdanm	82:6473597d706e	7558	} hw_enet_atoff_t;
bogdanm	82:6473597d706e	7559	#endif
bogdanm	82:6473597d706e	7560
bogdanm	82:6473597d706e	7561	/*!
bogdanm	82:6473597d706e	7562	* @name Constants and macros for entire ENET_ATOFF register
bogdanm	82:6473597d706e	7563	*/
bogdanm	82:6473597d706e	7564	//@{
bogdanm	82:6473597d706e	7565	#define HW_ENET_ATOFF_ADDR(x) (REGS_ENET_BASE(x) + 0x408U)
bogdanm	82:6473597d706e	7566
bogdanm	82:6473597d706e	7567	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7568	#define HW_ENET_ATOFF(x) ((__IO hw_enet_atoff_t ) HW_ENET_ATOFF_ADDR(x))
bogdanm	82:6473597d706e	7569	#define HW_ENET_ATOFF_RD(x) (HW_ENET_ATOFF(x).U)
bogdanm	82:6473597d706e	7570	#define HW_ENET_ATOFF_WR(x, v) (HW_ENET_ATOFF(x).U = (v))
bogdanm	82:6473597d706e	7571	#define HW_ENET_ATOFF_SET(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) \| (v)))
bogdanm	82:6473597d706e	7572	#define HW_ENET_ATOFF_CLR(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) & ~(v)))
bogdanm	82:6473597d706e	7573	#define HW_ENET_ATOFF_TOG(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) ^ (v)))
bogdanm	82:6473597d706e	7574	#endif
bogdanm	82:6473597d706e	7575	//@}
bogdanm	82:6473597d706e	7576
bogdanm	82:6473597d706e	7577	/*
bogdanm	82:6473597d706e	7578	* Constants & macros for individual ENET_ATOFF bitfields
bogdanm	82:6473597d706e	7579	*/
bogdanm	82:6473597d706e	7580
bogdanm	82:6473597d706e	7581	/*!
bogdanm	82:6473597d706e	7582	* @name Register ENET_ATOFF, field OFFSET[31:0] (RW)
bogdanm	82:6473597d706e	7583	*
bogdanm	82:6473597d706e	7584	* Offset value for one-shot event generation. When the timer reaches the value,
bogdanm	82:6473597d706e	7585	* an event can be generated to reset the counter. If the increment value in
bogdanm	82:6473597d706e	7586	* ATINC is given in true nanoseconds, this value is also given in true nanoseconds.
bogdanm	82:6473597d706e	7587	*/
bogdanm	82:6473597d706e	7588	//@{
bogdanm	82:6473597d706e	7589	#define BP_ENET_ATOFF_OFFSET (0U) //!< Bit position for ENET_ATOFF_OFFSET.
bogdanm	82:6473597d706e	7590	#define BM_ENET_ATOFF_OFFSET (0xFFFFFFFFU) //!< Bit mask for ENET_ATOFF_OFFSET.
bogdanm	82:6473597d706e	7591	#define BS_ENET_ATOFF_OFFSET (32U) //!< Bit field size in bits for ENET_ATOFF_OFFSET.
bogdanm	82:6473597d706e	7592
bogdanm	82:6473597d706e	7593	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7594	//! @brief Read current value of the ENET_ATOFF_OFFSET field.
bogdanm	82:6473597d706e	7595	#define BR_ENET_ATOFF_OFFSET(x) (HW_ENET_ATOFF(x).U)
bogdanm	82:6473597d706e	7596	#endif
bogdanm	82:6473597d706e	7597
bogdanm	82:6473597d706e	7598	//! @brief Format value for bitfield ENET_ATOFF_OFFSET.
bogdanm	82:6473597d706e	7599	#define BF_ENET_ATOFF_OFFSET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATOFF_OFFSET), uint32_t) & BM_ENET_ATOFF_OFFSET)
bogdanm	82:6473597d706e	7600
bogdanm	82:6473597d706e	7601	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7602	//! @brief Set the OFFSET field to a new value.
bogdanm	82:6473597d706e	7603	#define BW_ENET_ATOFF_OFFSET(x, v) (HW_ENET_ATOFF_WR(x, v))
bogdanm	82:6473597d706e	7604	#endif
bogdanm	82:6473597d706e	7605	//@}
bogdanm	82:6473597d706e	7606
bogdanm	82:6473597d706e	7607	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7608	// HW_ENET_ATPER - Timer Period Register
bogdanm	82:6473597d706e	7609	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7610
bogdanm	82:6473597d706e	7611	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7612	/*!
bogdanm	82:6473597d706e	7613	* @brief HW_ENET_ATPER - Timer Period Register (RW)
bogdanm	82:6473597d706e	7614	*
bogdanm	82:6473597d706e	7615	* Reset value: 0x3B9ACA00U
bogdanm	82:6473597d706e	7616	*/
bogdanm	82:6473597d706e	7617	typedef union _hw_enet_atper
bogdanm	82:6473597d706e	7618	{
bogdanm	82:6473597d706e	7619	uint32_t U;
bogdanm	82:6473597d706e	7620	struct _hw_enet_atper_bitfields
bogdanm	82:6473597d706e	7621	{
bogdanm	82:6473597d706e	7622	uint32_t PERIOD : 32; //!< [31:0]
bogdanm	82:6473597d706e	7623	} B;
bogdanm	82:6473597d706e	7624	} hw_enet_atper_t;
bogdanm	82:6473597d706e	7625	#endif
bogdanm	82:6473597d706e	7626
bogdanm	82:6473597d706e	7627	/*!
bogdanm	82:6473597d706e	7628	* @name Constants and macros for entire ENET_ATPER register
bogdanm	82:6473597d706e	7629	*/
bogdanm	82:6473597d706e	7630	//@{
bogdanm	82:6473597d706e	7631	#define HW_ENET_ATPER_ADDR(x) (REGS_ENET_BASE(x) + 0x40CU)
bogdanm	82:6473597d706e	7632
bogdanm	82:6473597d706e	7633	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7634	#define HW_ENET_ATPER(x) ((__IO hw_enet_atper_t ) HW_ENET_ATPER_ADDR(x))
bogdanm	82:6473597d706e	7635	#define HW_ENET_ATPER_RD(x) (HW_ENET_ATPER(x).U)
bogdanm	82:6473597d706e	7636	#define HW_ENET_ATPER_WR(x, v) (HW_ENET_ATPER(x).U = (v))
bogdanm	82:6473597d706e	7637	#define HW_ENET_ATPER_SET(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) \| (v)))
bogdanm	82:6473597d706e	7638	#define HW_ENET_ATPER_CLR(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) & ~(v)))
bogdanm	82:6473597d706e	7639	#define HW_ENET_ATPER_TOG(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) ^ (v)))
bogdanm	82:6473597d706e	7640	#endif
bogdanm	82:6473597d706e	7641	//@}
bogdanm	82:6473597d706e	7642
bogdanm	82:6473597d706e	7643	/*
bogdanm	82:6473597d706e	7644	* Constants & macros for individual ENET_ATPER bitfields
bogdanm	82:6473597d706e	7645	*/
bogdanm	82:6473597d706e	7646
bogdanm	82:6473597d706e	7647	/*!
bogdanm	82:6473597d706e	7648	* @name Register ENET_ATPER, field PERIOD[31:0] (RW)
bogdanm	82:6473597d706e	7649	*
bogdanm	82:6473597d706e	7650	* Value for generating periodic events. Each instance the timer reaches this
bogdanm	82:6473597d706e	7651	* value, the period event occurs and the timer restarts. If the increment value in
bogdanm	82:6473597d706e	7652	* ATINC is given in true nanoseconds, this value is also given in true
bogdanm	82:6473597d706e	7653	* nanoseconds. The value should be initialized to 1,000,000,000 (1 x 10 9 ) to represent
bogdanm	82:6473597d706e	7654	* a timer wrap around of one second. The increment value set in ATINC should be
bogdanm	82:6473597d706e	7655	* set to the true nanoseconds of the period of clock ts_clk, hence implementing
bogdanm	82:6473597d706e	7656	* a true 1 second counter.
bogdanm	82:6473597d706e	7657	*/
bogdanm	82:6473597d706e	7658	//@{
bogdanm	82:6473597d706e	7659	#define BP_ENET_ATPER_PERIOD (0U) //!< Bit position for ENET_ATPER_PERIOD.
bogdanm	82:6473597d706e	7660	#define BM_ENET_ATPER_PERIOD (0xFFFFFFFFU) //!< Bit mask for ENET_ATPER_PERIOD.
bogdanm	82:6473597d706e	7661	#define BS_ENET_ATPER_PERIOD (32U) //!< Bit field size in bits for ENET_ATPER_PERIOD.
bogdanm	82:6473597d706e	7662
bogdanm	82:6473597d706e	7663	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7664	//! @brief Read current value of the ENET_ATPER_PERIOD field.
bogdanm	82:6473597d706e	7665	#define BR_ENET_ATPER_PERIOD(x) (HW_ENET_ATPER(x).U)
bogdanm	82:6473597d706e	7666	#endif
bogdanm	82:6473597d706e	7667
bogdanm	82:6473597d706e	7668	//! @brief Format value for bitfield ENET_ATPER_PERIOD.
bogdanm	82:6473597d706e	7669	#define BF_ENET_ATPER_PERIOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATPER_PERIOD), uint32_t) & BM_ENET_ATPER_PERIOD)
bogdanm	82:6473597d706e	7670
bogdanm	82:6473597d706e	7671	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7672	//! @brief Set the PERIOD field to a new value.
bogdanm	82:6473597d706e	7673	#define BW_ENET_ATPER_PERIOD(x, v) (HW_ENET_ATPER_WR(x, v))
bogdanm	82:6473597d706e	7674	#endif
bogdanm	82:6473597d706e	7675	//@}
bogdanm	82:6473597d706e	7676
bogdanm	82:6473597d706e	7677	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7678	// HW_ENET_ATCOR - Timer Correction Register
bogdanm	82:6473597d706e	7679	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7680
bogdanm	82:6473597d706e	7681	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7682	/*!
bogdanm	82:6473597d706e	7683	* @brief HW_ENET_ATCOR - Timer Correction Register (RW)
bogdanm	82:6473597d706e	7684	*
bogdanm	82:6473597d706e	7685	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	7686	*/
bogdanm	82:6473597d706e	7687	typedef union _hw_enet_atcor
bogdanm	82:6473597d706e	7688	{
bogdanm	82:6473597d706e	7689	uint32_t U;
bogdanm	82:6473597d706e	7690	struct _hw_enet_atcor_bitfields
bogdanm	82:6473597d706e	7691	{
bogdanm	82:6473597d706e	7692	uint32_t COR : 31; //!< [30:0] Correction Counter Wrap-Around Value
bogdanm	82:6473597d706e	7693	uint32_t RESERVED0 : 1; //!< [31]
bogdanm	82:6473597d706e	7694	} B;
bogdanm	82:6473597d706e	7695	} hw_enet_atcor_t;
bogdanm	82:6473597d706e	7696	#endif
bogdanm	82:6473597d706e	7697
bogdanm	82:6473597d706e	7698	/*!
bogdanm	82:6473597d706e	7699	* @name Constants and macros for entire ENET_ATCOR register
bogdanm	82:6473597d706e	7700	*/
bogdanm	82:6473597d706e	7701	//@{
bogdanm	82:6473597d706e	7702	#define HW_ENET_ATCOR_ADDR(x) (REGS_ENET_BASE(x) + 0x410U)
bogdanm	82:6473597d706e	7703
bogdanm	82:6473597d706e	7704	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7705	#define HW_ENET_ATCOR(x) ((__IO hw_enet_atcor_t ) HW_ENET_ATCOR_ADDR(x))
bogdanm	82:6473597d706e	7706	#define HW_ENET_ATCOR_RD(x) (HW_ENET_ATCOR(x).U)
bogdanm	82:6473597d706e	7707	#define HW_ENET_ATCOR_WR(x, v) (HW_ENET_ATCOR(x).U = (v))
bogdanm	82:6473597d706e	7708	#define HW_ENET_ATCOR_SET(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) \| (v)))
bogdanm	82:6473597d706e	7709	#define HW_ENET_ATCOR_CLR(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	7710	#define HW_ENET_ATCOR_TOG(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	7711	#endif
bogdanm	82:6473597d706e	7712	//@}
bogdanm	82:6473597d706e	7713
bogdanm	82:6473597d706e	7714	/*
bogdanm	82:6473597d706e	7715	* Constants & macros for individual ENET_ATCOR bitfields
bogdanm	82:6473597d706e	7716	*/
bogdanm	82:6473597d706e	7717
bogdanm	82:6473597d706e	7718	/*!
bogdanm	82:6473597d706e	7719	* @name Register ENET_ATCOR, field COR[30:0] (RW)
bogdanm	82:6473597d706e	7720	*
bogdanm	82:6473597d706e	7721	* Defines after how many timer clock cycles (ts_clk) the correction counter
bogdanm	82:6473597d706e	7722	* should be reset and trigger a correction increment on the timer. The amount of
bogdanm	82:6473597d706e	7723	* correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
bogdanm	82:6473597d706e	7724	* counter and no corrections occur. This value is given in clock cycles, not in
bogdanm	82:6473597d706e	7725	* nanoseconds as all other values.
bogdanm	82:6473597d706e	7726	*/
bogdanm	82:6473597d706e	7727	//@{
bogdanm	82:6473597d706e	7728	#define BP_ENET_ATCOR_COR (0U) //!< Bit position for ENET_ATCOR_COR.
bogdanm	82:6473597d706e	7729	#define BM_ENET_ATCOR_COR (0x7FFFFFFFU) //!< Bit mask for ENET_ATCOR_COR.
bogdanm	82:6473597d706e	7730	#define BS_ENET_ATCOR_COR (31U) //!< Bit field size in bits for ENET_ATCOR_COR.
bogdanm	82:6473597d706e	7731
bogdanm	82:6473597d706e	7732	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7733	//! @brief Read current value of the ENET_ATCOR_COR field.
bogdanm	82:6473597d706e	7734	#define BR_ENET_ATCOR_COR(x) (HW_ENET_ATCOR(x).B.COR)
bogdanm	82:6473597d706e	7735	#endif
bogdanm	82:6473597d706e	7736
bogdanm	82:6473597d706e	7737	//! @brief Format value for bitfield ENET_ATCOR_COR.
bogdanm	82:6473597d706e	7738	#define BF_ENET_ATCOR_COR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCOR_COR), uint32_t) & BM_ENET_ATCOR_COR)
bogdanm	82:6473597d706e	7739
bogdanm	82:6473597d706e	7740	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7741	//! @brief Set the COR field to a new value.
bogdanm	82:6473597d706e	7742	#define BW_ENET_ATCOR_COR(x, v) (HW_ENET_ATCOR_WR(x, (HW_ENET_ATCOR_RD(x) & ~BM_ENET_ATCOR_COR) \| BF_ENET_ATCOR_COR(v)))
bogdanm	82:6473597d706e	7743	#endif
bogdanm	82:6473597d706e	7744	//@}
bogdanm	82:6473597d706e	7745
bogdanm	82:6473597d706e	7746	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7747	// HW_ENET_ATINC - Time-Stamping Clock Period Register
bogdanm	82:6473597d706e	7748	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7749
bogdanm	82:6473597d706e	7750	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7751	/*!
bogdanm	82:6473597d706e	7752	* @brief HW_ENET_ATINC - Time-Stamping Clock Period Register (RW)
bogdanm	82:6473597d706e	7753	*
bogdanm	82:6473597d706e	7754	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	7755	*/
bogdanm	82:6473597d706e	7756	typedef union _hw_enet_atinc
bogdanm	82:6473597d706e	7757	{
bogdanm	82:6473597d706e	7758	uint32_t U;
bogdanm	82:6473597d706e	7759	struct _hw_enet_atinc_bitfields
bogdanm	82:6473597d706e	7760	{
bogdanm	82:6473597d706e	7761	uint32_t INC : 7; //!< [6:0] Clock Period Of The Timestamping Clock
bogdanm	82:6473597d706e	7762	//! (ts_clk) In Nanoseconds
bogdanm	82:6473597d706e	7763	uint32_t RESERVED0 : 1; //!< [7]
bogdanm	82:6473597d706e	7764	uint32_t INC_CORR : 7; //!< [14:8] Correction Increment Value
bogdanm	82:6473597d706e	7765	uint32_t RESERVED1 : 17; //!< [31:15]
bogdanm	82:6473597d706e	7766	} B;
bogdanm	82:6473597d706e	7767	} hw_enet_atinc_t;
bogdanm	82:6473597d706e	7768	#endif
bogdanm	82:6473597d706e	7769
bogdanm	82:6473597d706e	7770	/*!
bogdanm	82:6473597d706e	7771	* @name Constants and macros for entire ENET_ATINC register
bogdanm	82:6473597d706e	7772	*/
bogdanm	82:6473597d706e	7773	//@{
bogdanm	82:6473597d706e	7774	#define HW_ENET_ATINC_ADDR(x) (REGS_ENET_BASE(x) + 0x414U)
bogdanm	82:6473597d706e	7775
bogdanm	82:6473597d706e	7776	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7777	#define HW_ENET_ATINC(x) ((__IO hw_enet_atinc_t ) HW_ENET_ATINC_ADDR(x))
bogdanm	82:6473597d706e	7778	#define HW_ENET_ATINC_RD(x) (HW_ENET_ATINC(x).U)
bogdanm	82:6473597d706e	7779	#define HW_ENET_ATINC_WR(x, v) (HW_ENET_ATINC(x).U = (v))
bogdanm	82:6473597d706e	7780	#define HW_ENET_ATINC_SET(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) \| (v)))
bogdanm	82:6473597d706e	7781	#define HW_ENET_ATINC_CLR(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) & ~(v)))
bogdanm	82:6473597d706e	7782	#define HW_ENET_ATINC_TOG(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) ^ (v)))
bogdanm	82:6473597d706e	7783	#endif
bogdanm	82:6473597d706e	7784	//@}
bogdanm	82:6473597d706e	7785
bogdanm	82:6473597d706e	7786	/*
bogdanm	82:6473597d706e	7787	* Constants & macros for individual ENET_ATINC bitfields
bogdanm	82:6473597d706e	7788	*/
bogdanm	82:6473597d706e	7789
bogdanm	82:6473597d706e	7790	/*!
bogdanm	82:6473597d706e	7791	* @name Register ENET_ATINC, field INC[6:0] (RW)
bogdanm	82:6473597d706e	7792	*
bogdanm	82:6473597d706e	7793	* The timer increments by this amount each clock cycle. For example, set to 10
bogdanm	82:6473597d706e	7794	* for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
bogdanm	82:6473597d706e	7795	* that is an integer fraction of the period set in ATPER.
bogdanm	82:6473597d706e	7796	*/
bogdanm	82:6473597d706e	7797	//@{
bogdanm	82:6473597d706e	7798	#define BP_ENET_ATINC_INC (0U) //!< Bit position for ENET_ATINC_INC.
bogdanm	82:6473597d706e	7799	#define BM_ENET_ATINC_INC (0x0000007FU) //!< Bit mask for ENET_ATINC_INC.
bogdanm	82:6473597d706e	7800	#define BS_ENET_ATINC_INC (7U) //!< Bit field size in bits for ENET_ATINC_INC.
bogdanm	82:6473597d706e	7801
bogdanm	82:6473597d706e	7802	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7803	//! @brief Read current value of the ENET_ATINC_INC field.
bogdanm	82:6473597d706e	7804	#define BR_ENET_ATINC_INC(x) (HW_ENET_ATINC(x).B.INC)
bogdanm	82:6473597d706e	7805	#endif
bogdanm	82:6473597d706e	7806
bogdanm	82:6473597d706e	7807	//! @brief Format value for bitfield ENET_ATINC_INC.
bogdanm	82:6473597d706e	7808	#define BF_ENET_ATINC_INC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATINC_INC), uint32_t) & BM_ENET_ATINC_INC)
bogdanm	82:6473597d706e	7809
bogdanm	82:6473597d706e	7810	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7811	//! @brief Set the INC field to a new value.
bogdanm	82:6473597d706e	7812	#define BW_ENET_ATINC_INC(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC) \| BF_ENET_ATINC_INC(v)))
bogdanm	82:6473597d706e	7813	#endif
bogdanm	82:6473597d706e	7814	//@}
bogdanm	82:6473597d706e	7815
bogdanm	82:6473597d706e	7816	/*!
bogdanm	82:6473597d706e	7817	* @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
bogdanm	82:6473597d706e	7818	*
bogdanm	82:6473597d706e	7819	* This value is added every time the correction timer expires (every clock
bogdanm	82:6473597d706e	7820	* cycle given in ATCOR). A value less than INC slows down the timer. A value greater
bogdanm	82:6473597d706e	7821	* than INC speeds up the timer.
bogdanm	82:6473597d706e	7822	*/
bogdanm	82:6473597d706e	7823	//@{
bogdanm	82:6473597d706e	7824	#define BP_ENET_ATINC_INC_CORR (8U) //!< Bit position for ENET_ATINC_INC_CORR.
bogdanm	82:6473597d706e	7825	#define BM_ENET_ATINC_INC_CORR (0x00007F00U) //!< Bit mask for ENET_ATINC_INC_CORR.
bogdanm	82:6473597d706e	7826	#define BS_ENET_ATINC_INC_CORR (7U) //!< Bit field size in bits for ENET_ATINC_INC_CORR.
bogdanm	82:6473597d706e	7827
bogdanm	82:6473597d706e	7828	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7829	//! @brief Read current value of the ENET_ATINC_INC_CORR field.
bogdanm	82:6473597d706e	7830	#define BR_ENET_ATINC_INC_CORR(x) (HW_ENET_ATINC(x).B.INC_CORR)
bogdanm	82:6473597d706e	7831	#endif
bogdanm	82:6473597d706e	7832
bogdanm	82:6473597d706e	7833	//! @brief Format value for bitfield ENET_ATINC_INC_CORR.
bogdanm	82:6473597d706e	7834	#define BF_ENET_ATINC_INC_CORR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATINC_INC_CORR), uint32_t) & BM_ENET_ATINC_INC_CORR)
bogdanm	82:6473597d706e	7835
bogdanm	82:6473597d706e	7836	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7837	//! @brief Set the INC_CORR field to a new value.
bogdanm	82:6473597d706e	7838	#define BW_ENET_ATINC_INC_CORR(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC_CORR) \| BF_ENET_ATINC_INC_CORR(v)))
bogdanm	82:6473597d706e	7839	#endif
bogdanm	82:6473597d706e	7840	//@}
bogdanm	82:6473597d706e	7841
bogdanm	82:6473597d706e	7842	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7843	// HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
bogdanm	82:6473597d706e	7844	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7845
bogdanm	82:6473597d706e	7846	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7847	/*!
bogdanm	82:6473597d706e	7848	* @brief HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
bogdanm	82:6473597d706e	7849	*
bogdanm	82:6473597d706e	7850	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	7851	*/
bogdanm	82:6473597d706e	7852	typedef union _hw_enet_atstmp
bogdanm	82:6473597d706e	7853	{
bogdanm	82:6473597d706e	7854	uint32_t U;
bogdanm	82:6473597d706e	7855	struct _hw_enet_atstmp_bitfields
bogdanm	82:6473597d706e	7856	{
bogdanm	82:6473597d706e	7857	uint32_t TIMESTAMP : 32; //!< [31:0]
bogdanm	82:6473597d706e	7858	} B;
bogdanm	82:6473597d706e	7859	} hw_enet_atstmp_t;
bogdanm	82:6473597d706e	7860	#endif
bogdanm	82:6473597d706e	7861
bogdanm	82:6473597d706e	7862	/*!
bogdanm	82:6473597d706e	7863	* @name Constants and macros for entire ENET_ATSTMP register
bogdanm	82:6473597d706e	7864	*/
bogdanm	82:6473597d706e	7865	//@{
bogdanm	82:6473597d706e	7866	#define HW_ENET_ATSTMP_ADDR(x) (REGS_ENET_BASE(x) + 0x418U)
bogdanm	82:6473597d706e	7867
bogdanm	82:6473597d706e	7868	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7869	#define HW_ENET_ATSTMP(x) ((__I hw_enet_atstmp_t ) HW_ENET_ATSTMP_ADDR(x))
bogdanm	82:6473597d706e	7870	#define HW_ENET_ATSTMP_RD(x) (HW_ENET_ATSTMP(x).U)
bogdanm	82:6473597d706e	7871	#endif
bogdanm	82:6473597d706e	7872	//@}
bogdanm	82:6473597d706e	7873
bogdanm	82:6473597d706e	7874	/*
bogdanm	82:6473597d706e	7875	* Constants & macros for individual ENET_ATSTMP bitfields
bogdanm	82:6473597d706e	7876	*/
bogdanm	82:6473597d706e	7877
bogdanm	82:6473597d706e	7878	/*!
bogdanm	82:6473597d706e	7879	* @name Register ENET_ATSTMP, field TIMESTAMP[31:0] (RO)
bogdanm	82:6473597d706e	7880	*
bogdanm	82:6473597d706e	7881	* Timestamp of the last frame transmitted by the core that had TxBD[TS] set .
bogdanm	82:6473597d706e	7882	* This register is only valid when EIR[TS_AVAIL] is set.
bogdanm	82:6473597d706e	7883	*/
bogdanm	82:6473597d706e	7884	//@{
bogdanm	82:6473597d706e	7885	#define BP_ENET_ATSTMP_TIMESTAMP (0U) //!< Bit position for ENET_ATSTMP_TIMESTAMP.
bogdanm	82:6473597d706e	7886	#define BM_ENET_ATSTMP_TIMESTAMP (0xFFFFFFFFU) //!< Bit mask for ENET_ATSTMP_TIMESTAMP.
bogdanm	82:6473597d706e	7887	#define BS_ENET_ATSTMP_TIMESTAMP (32U) //!< Bit field size in bits for ENET_ATSTMP_TIMESTAMP.
bogdanm	82:6473597d706e	7888
bogdanm	82:6473597d706e	7889	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7890	//! @brief Read current value of the ENET_ATSTMP_TIMESTAMP field.
bogdanm	82:6473597d706e	7891	#define BR_ENET_ATSTMP_TIMESTAMP(x) (HW_ENET_ATSTMP(x).U)
bogdanm	82:6473597d706e	7892	#endif
bogdanm	82:6473597d706e	7893	//@}
bogdanm	82:6473597d706e	7894
bogdanm	82:6473597d706e	7895	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7896	// HW_ENET_TGSR - Timer Global Status Register
bogdanm	82:6473597d706e	7897	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	7898
bogdanm	82:6473597d706e	7899	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7900	/*!
bogdanm	82:6473597d706e	7901	* @brief HW_ENET_TGSR - Timer Global Status Register (RW)
bogdanm	82:6473597d706e	7902	*
bogdanm	82:6473597d706e	7903	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	7904	*/
bogdanm	82:6473597d706e	7905	typedef union _hw_enet_tgsr
bogdanm	82:6473597d706e	7906	{
bogdanm	82:6473597d706e	7907	uint32_t U;
bogdanm	82:6473597d706e	7908	struct _hw_enet_tgsr_bitfields
bogdanm	82:6473597d706e	7909	{
bogdanm	82:6473597d706e	7910	uint32_t TF0 : 1; //!< [0] Copy Of Timer Flag For Channel 0
bogdanm	82:6473597d706e	7911	uint32_t TF1 : 1; //!< [1] Copy Of Timer Flag For Channel 1
bogdanm	82:6473597d706e	7912	uint32_t TF2 : 1; //!< [2] Copy Of Timer Flag For Channel 2
bogdanm	82:6473597d706e	7913	uint32_t TF3 : 1; //!< [3] Copy Of Timer Flag For Channel 3
bogdanm	82:6473597d706e	7914	uint32_t RESERVED0 : 28; //!< [31:4]
bogdanm	82:6473597d706e	7915	} B;
bogdanm	82:6473597d706e	7916	} hw_enet_tgsr_t;
bogdanm	82:6473597d706e	7917	#endif
bogdanm	82:6473597d706e	7918
bogdanm	82:6473597d706e	7919	/*!
bogdanm	82:6473597d706e	7920	* @name Constants and macros for entire ENET_TGSR register
bogdanm	82:6473597d706e	7921	*/
bogdanm	82:6473597d706e	7922	//@{
bogdanm	82:6473597d706e	7923	#define HW_ENET_TGSR_ADDR(x) (REGS_ENET_BASE(x) + 0x604U)
bogdanm	82:6473597d706e	7924
bogdanm	82:6473597d706e	7925	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7926	#define HW_ENET_TGSR(x) ((__IO hw_enet_tgsr_t ) HW_ENET_TGSR_ADDR(x))
bogdanm	82:6473597d706e	7927	#define HW_ENET_TGSR_RD(x) (HW_ENET_TGSR(x).U)
bogdanm	82:6473597d706e	7928	#define HW_ENET_TGSR_WR(x, v) (HW_ENET_TGSR(x).U = (v))
bogdanm	82:6473597d706e	7929	#define HW_ENET_TGSR_SET(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) \| (v)))
bogdanm	82:6473597d706e	7930	#define HW_ENET_TGSR_CLR(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	7931	#define HW_ENET_TGSR_TOG(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	7932	#endif
bogdanm	82:6473597d706e	7933	//@}
bogdanm	82:6473597d706e	7934
bogdanm	82:6473597d706e	7935	/*
bogdanm	82:6473597d706e	7936	* Constants & macros for individual ENET_TGSR bitfields
bogdanm	82:6473597d706e	7937	*/
bogdanm	82:6473597d706e	7938
bogdanm	82:6473597d706e	7939	/*!
bogdanm	82:6473597d706e	7940	* @name Register ENET_TGSR, field TF0[0] (W1C)
bogdanm	82:6473597d706e	7941	*
bogdanm	82:6473597d706e	7942	* Values:
bogdanm	82:6473597d706e	7943	* - 0 - Timer Flag for Channel 0 is clear
bogdanm	82:6473597d706e	7944	* - 1 - Timer Flag for Channel 0 is set
bogdanm	82:6473597d706e	7945	*/
bogdanm	82:6473597d706e	7946	//@{
bogdanm	82:6473597d706e	7947	#define BP_ENET_TGSR_TF0 (0U) //!< Bit position for ENET_TGSR_TF0.
bogdanm	82:6473597d706e	7948	#define BM_ENET_TGSR_TF0 (0x00000001U) //!< Bit mask for ENET_TGSR_TF0.
bogdanm	82:6473597d706e	7949	#define BS_ENET_TGSR_TF0 (1U) //!< Bit field size in bits for ENET_TGSR_TF0.
bogdanm	82:6473597d706e	7950
bogdanm	82:6473597d706e	7951	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7952	//! @brief Read current value of the ENET_TGSR_TF0 field.
bogdanm	82:6473597d706e	7953	#define BR_ENET_TGSR_TF0(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0))
bogdanm	82:6473597d706e	7954	#endif
bogdanm	82:6473597d706e	7955
bogdanm	82:6473597d706e	7956	//! @brief Format value for bitfield ENET_TGSR_TF0.
bogdanm	82:6473597d706e	7957	#define BF_ENET_TGSR_TF0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF0), uint32_t) & BM_ENET_TGSR_TF0)
bogdanm	82:6473597d706e	7958
bogdanm	82:6473597d706e	7959	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7960	//! @brief Set the TF0 field to a new value.
bogdanm	82:6473597d706e	7961	#define BW_ENET_TGSR_TF0(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0) = (v))
bogdanm	82:6473597d706e	7962	#endif
bogdanm	82:6473597d706e	7963	//@}
bogdanm	82:6473597d706e	7964
bogdanm	82:6473597d706e	7965	/*!
bogdanm	82:6473597d706e	7966	* @name Register ENET_TGSR, field TF1[1] (W1C)
bogdanm	82:6473597d706e	7967	*
bogdanm	82:6473597d706e	7968	* Values:
bogdanm	82:6473597d706e	7969	* - 0 - Timer Flag for Channel 1 is clear
bogdanm	82:6473597d706e	7970	* - 1 - Timer Flag for Channel 1 is set
bogdanm	82:6473597d706e	7971	*/
bogdanm	82:6473597d706e	7972	//@{
bogdanm	82:6473597d706e	7973	#define BP_ENET_TGSR_TF1 (1U) //!< Bit position for ENET_TGSR_TF1.
bogdanm	82:6473597d706e	7974	#define BM_ENET_TGSR_TF1 (0x00000002U) //!< Bit mask for ENET_TGSR_TF1.
bogdanm	82:6473597d706e	7975	#define BS_ENET_TGSR_TF1 (1U) //!< Bit field size in bits for ENET_TGSR_TF1.
bogdanm	82:6473597d706e	7976
bogdanm	82:6473597d706e	7977	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7978	//! @brief Read current value of the ENET_TGSR_TF1 field.
bogdanm	82:6473597d706e	7979	#define BR_ENET_TGSR_TF1(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1))
bogdanm	82:6473597d706e	7980	#endif
bogdanm	82:6473597d706e	7981
bogdanm	82:6473597d706e	7982	//! @brief Format value for bitfield ENET_TGSR_TF1.
bogdanm	82:6473597d706e	7983	#define BF_ENET_TGSR_TF1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF1), uint32_t) & BM_ENET_TGSR_TF1)
bogdanm	82:6473597d706e	7984
bogdanm	82:6473597d706e	7985	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	7986	//! @brief Set the TF1 field to a new value.
bogdanm	82:6473597d706e	7987	#define BW_ENET_TGSR_TF1(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1) = (v))
bogdanm	82:6473597d706e	7988	#endif
bogdanm	82:6473597d706e	7989	//@}
bogdanm	82:6473597d706e	7990
bogdanm	82:6473597d706e	7991	/*!
bogdanm	82:6473597d706e	7992	* @name Register ENET_TGSR, field TF2[2] (W1C)
bogdanm	82:6473597d706e	7993	*
bogdanm	82:6473597d706e	7994	* Values:
bogdanm	82:6473597d706e	7995	* - 0 - Timer Flag for Channel 2 is clear
bogdanm	82:6473597d706e	7996	* - 1 - Timer Flag for Channel 2 is set
bogdanm	82:6473597d706e	7997	*/
bogdanm	82:6473597d706e	7998	//@{
bogdanm	82:6473597d706e	7999	#define BP_ENET_TGSR_TF2 (2U) //!< Bit position for ENET_TGSR_TF2.
bogdanm	82:6473597d706e	8000	#define BM_ENET_TGSR_TF2 (0x00000004U) //!< Bit mask for ENET_TGSR_TF2.
bogdanm	82:6473597d706e	8001	#define BS_ENET_TGSR_TF2 (1U) //!< Bit field size in bits for ENET_TGSR_TF2.
bogdanm	82:6473597d706e	8002
bogdanm	82:6473597d706e	8003	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8004	//! @brief Read current value of the ENET_TGSR_TF2 field.
bogdanm	82:6473597d706e	8005	#define BR_ENET_TGSR_TF2(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2))
bogdanm	82:6473597d706e	8006	#endif
bogdanm	82:6473597d706e	8007
bogdanm	82:6473597d706e	8008	//! @brief Format value for bitfield ENET_TGSR_TF2.
bogdanm	82:6473597d706e	8009	#define BF_ENET_TGSR_TF2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF2), uint32_t) & BM_ENET_TGSR_TF2)
bogdanm	82:6473597d706e	8010
bogdanm	82:6473597d706e	8011	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8012	//! @brief Set the TF2 field to a new value.
bogdanm	82:6473597d706e	8013	#define BW_ENET_TGSR_TF2(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2) = (v))
bogdanm	82:6473597d706e	8014	#endif
bogdanm	82:6473597d706e	8015	//@}
bogdanm	82:6473597d706e	8016
bogdanm	82:6473597d706e	8017	/*!
bogdanm	82:6473597d706e	8018	* @name Register ENET_TGSR, field TF3[3] (W1C)
bogdanm	82:6473597d706e	8019	*
bogdanm	82:6473597d706e	8020	* Values:
bogdanm	82:6473597d706e	8021	* - 0 - Timer Flag for Channel 3 is clear
bogdanm	82:6473597d706e	8022	* - 1 - Timer Flag for Channel 3 is set
bogdanm	82:6473597d706e	8023	*/
bogdanm	82:6473597d706e	8024	//@{
bogdanm	82:6473597d706e	8025	#define BP_ENET_TGSR_TF3 (3U) //!< Bit position for ENET_TGSR_TF3.
bogdanm	82:6473597d706e	8026	#define BM_ENET_TGSR_TF3 (0x00000008U) //!< Bit mask for ENET_TGSR_TF3.
bogdanm	82:6473597d706e	8027	#define BS_ENET_TGSR_TF3 (1U) //!< Bit field size in bits for ENET_TGSR_TF3.
bogdanm	82:6473597d706e	8028
bogdanm	82:6473597d706e	8029	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8030	//! @brief Read current value of the ENET_TGSR_TF3 field.
bogdanm	82:6473597d706e	8031	#define BR_ENET_TGSR_TF3(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3))
bogdanm	82:6473597d706e	8032	#endif
bogdanm	82:6473597d706e	8033
bogdanm	82:6473597d706e	8034	//! @brief Format value for bitfield ENET_TGSR_TF3.
bogdanm	82:6473597d706e	8035	#define BF_ENET_TGSR_TF3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF3), uint32_t) & BM_ENET_TGSR_TF3)
bogdanm	82:6473597d706e	8036
bogdanm	82:6473597d706e	8037	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8038	//! @brief Set the TF3 field to a new value.
bogdanm	82:6473597d706e	8039	#define BW_ENET_TGSR_TF3(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3) = (v))
bogdanm	82:6473597d706e	8040	#endif
bogdanm	82:6473597d706e	8041	//@}
bogdanm	82:6473597d706e	8042
bogdanm	82:6473597d706e	8043	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	8044	// HW_ENET_TCSRn - Timer Control Status Register
bogdanm	82:6473597d706e	8045	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	8046
bogdanm	82:6473597d706e	8047	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8048	/*!
bogdanm	82:6473597d706e	8049	* @brief HW_ENET_TCSRn - Timer Control Status Register (RW)
bogdanm	82:6473597d706e	8050	*
bogdanm	82:6473597d706e	8051	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	8052	*/
bogdanm	82:6473597d706e	8053	typedef union _hw_enet_tcsrn
bogdanm	82:6473597d706e	8054	{
bogdanm	82:6473597d706e	8055	uint32_t U;
bogdanm	82:6473597d706e	8056	struct _hw_enet_tcsrn_bitfields
bogdanm	82:6473597d706e	8057	{
bogdanm	82:6473597d706e	8058	uint32_t TDRE : 1; //!< [0] Timer DMA Request Enable
bogdanm	82:6473597d706e	8059	uint32_t RESERVED0 : 1; //!< [1]
bogdanm	82:6473597d706e	8060	uint32_t TMODE : 4; //!< [5:2] Timer Mode
bogdanm	82:6473597d706e	8061	uint32_t TIE : 1; //!< [6] Timer Interrupt Enable
bogdanm	82:6473597d706e	8062	uint32_t TF : 1; //!< [7] Timer Flag
bogdanm	82:6473597d706e	8063	uint32_t RESERVED1 : 24; //!< [31:8]
bogdanm	82:6473597d706e	8064	} B;
bogdanm	82:6473597d706e	8065	} hw_enet_tcsrn_t;
bogdanm	82:6473597d706e	8066	#endif
bogdanm	82:6473597d706e	8067
bogdanm	82:6473597d706e	8068	/*!
bogdanm	82:6473597d706e	8069	* @name Constants and macros for entire ENET_TCSRn register
bogdanm	82:6473597d706e	8070	*/
bogdanm	82:6473597d706e	8071	//@{
bogdanm	82:6473597d706e	8072	#define HW_ENET_TCSRn_COUNT (4U)
bogdanm	82:6473597d706e	8073
bogdanm	82:6473597d706e	8074	#define HW_ENET_TCSRn_ADDR(x, n) (REGS_ENET_BASE(x) + 0x608U + (0x8U * n))
bogdanm	82:6473597d706e	8075
bogdanm	82:6473597d706e	8076	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8077	#define HW_ENET_TCSRn(x, n) ((__IO hw_enet_tcsrn_t ) HW_ENET_TCSRn_ADDR(x, n))
bogdanm	82:6473597d706e	8078	#define HW_ENET_TCSRn_RD(x, n) (HW_ENET_TCSRn(x, n).U)
bogdanm	82:6473597d706e	8079	#define HW_ENET_TCSRn_WR(x, n, v) (HW_ENET_TCSRn(x, n).U = (v))
bogdanm	82:6473597d706e	8080	#define HW_ENET_TCSRn_SET(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	8081	#define HW_ENET_TCSRn_CLR(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	8082	#define HW_ENET_TCSRn_TOG(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	8083	#endif
bogdanm	82:6473597d706e	8084	//@}
bogdanm	82:6473597d706e	8085
bogdanm	82:6473597d706e	8086	/*
bogdanm	82:6473597d706e	8087	* Constants & macros for individual ENET_TCSRn bitfields
bogdanm	82:6473597d706e	8088	*/
bogdanm	82:6473597d706e	8089
bogdanm	82:6473597d706e	8090	/*!
bogdanm	82:6473597d706e	8091	* @name Register ENET_TCSRn, field TDRE[0] (RW)
bogdanm	82:6473597d706e	8092	*
bogdanm	82:6473597d706e	8093	* Values:
bogdanm	82:6473597d706e	8094	* - 0 - DMA request is disabled
bogdanm	82:6473597d706e	8095	* - 1 - DMA request is enabled
bogdanm	82:6473597d706e	8096	*/
bogdanm	82:6473597d706e	8097	//@{
bogdanm	82:6473597d706e	8098	#define BP_ENET_TCSRn_TDRE (0U) //!< Bit position for ENET_TCSRn_TDRE.
bogdanm	82:6473597d706e	8099	#define BM_ENET_TCSRn_TDRE (0x00000001U) //!< Bit mask for ENET_TCSRn_TDRE.
bogdanm	82:6473597d706e	8100	#define BS_ENET_TCSRn_TDRE (1U) //!< Bit field size in bits for ENET_TCSRn_TDRE.
bogdanm	82:6473597d706e	8101
bogdanm	82:6473597d706e	8102	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8103	//! @brief Read current value of the ENET_TCSRn_TDRE field.
bogdanm	82:6473597d706e	8104	#define BR_ENET_TCSRn_TDRE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE))
bogdanm	82:6473597d706e	8105	#endif
bogdanm	82:6473597d706e	8106
bogdanm	82:6473597d706e	8107	//! @brief Format value for bitfield ENET_TCSRn_TDRE.
bogdanm	82:6473597d706e	8108	#define BF_ENET_TCSRn_TDRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TDRE), uint32_t) & BM_ENET_TCSRn_TDRE)
bogdanm	82:6473597d706e	8109
bogdanm	82:6473597d706e	8110	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8111	//! @brief Set the TDRE field to a new value.
bogdanm	82:6473597d706e	8112	#define BW_ENET_TCSRn_TDRE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE) = (v))
bogdanm	82:6473597d706e	8113	#endif
bogdanm	82:6473597d706e	8114	//@}
bogdanm	82:6473597d706e	8115
bogdanm	82:6473597d706e	8116	/*!
bogdanm	82:6473597d706e	8117	* @name Register ENET_TCSRn, field TMODE[5:2] (RW)
bogdanm	82:6473597d706e	8118	*
bogdanm	82:6473597d706e	8119	* Updating the Timer Mode field takes a few cycles to register because it is
bogdanm	82:6473597d706e	8120	* synchronized to the 1588 clock. The version of Timer Mode returned on a read is
bogdanm	82:6473597d706e	8121	* from the 1588 clock domain. When changing Timer Mode, always disable the
bogdanm	82:6473597d706e	8122	* channel and read this register to verify the channel is disabled first.
bogdanm	82:6473597d706e	8123	*
bogdanm	82:6473597d706e	8124	* Values:
bogdanm	82:6473597d706e	8125	* - 0000 - Timer Channel is disabled.
bogdanm	82:6473597d706e	8126	* - 0001 - Timer Channel is configured for Input Capture on rising edge
bogdanm	82:6473597d706e	8127	* - 0010 - Timer Channel is configured for Input Capture on falling edge
bogdanm	82:6473597d706e	8128	* - 0011 - Timer Channel is configured for Input Capture on both edges
bogdanm	82:6473597d706e	8129	* - 0100 - Timer Channel is configured for Output Compare - software only
bogdanm	82:6473597d706e	8130	* - 0101 - Timer Channel is configured for Output Compare - toggle output on
bogdanm	82:6473597d706e	8131	* compare
bogdanm	82:6473597d706e	8132	* - 0110 - Timer Channel is configured for Output Compare - clear output on
bogdanm	82:6473597d706e	8133	* compare
bogdanm	82:6473597d706e	8134	* - 0111 - Timer Channel is configured for Output Compare - set output on
bogdanm	82:6473597d706e	8135	* compare
bogdanm	82:6473597d706e	8136	* - 1000 - Reserved
bogdanm	82:6473597d706e	8137	* - 1010 - Timer Channel is configured for Output Compare - clear output on
bogdanm	82:6473597d706e	8138	* compare, set output on overflow
bogdanm	82:6473597d706e	8139	* - 10x1 - Timer Channel is configured for Output Compare - set output on
bogdanm	82:6473597d706e	8140	* compare, clear output on overflow
bogdanm	82:6473597d706e	8141	* - 1100 - Reserved
bogdanm	82:6473597d706e	8142	* - 1110 - Timer Channel is configured for Output Compare - pulse output low on
bogdanm	82:6473597d706e	8143	* compare for one 1588 clock cycle
bogdanm	82:6473597d706e	8144	* - 1111 - Timer Channel is configured for Output Compare - pulse output high
bogdanm	82:6473597d706e	8145	* on compare for one 1588 clock cycle
bogdanm	82:6473597d706e	8146	*/
bogdanm	82:6473597d706e	8147	//@{
bogdanm	82:6473597d706e	8148	#define BP_ENET_TCSRn_TMODE (2U) //!< Bit position for ENET_TCSRn_TMODE.
bogdanm	82:6473597d706e	8149	#define BM_ENET_TCSRn_TMODE (0x0000003CU) //!< Bit mask for ENET_TCSRn_TMODE.
bogdanm	82:6473597d706e	8150	#define BS_ENET_TCSRn_TMODE (4U) //!< Bit field size in bits for ENET_TCSRn_TMODE.
bogdanm	82:6473597d706e	8151
bogdanm	82:6473597d706e	8152	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8153	//! @brief Read current value of the ENET_TCSRn_TMODE field.
bogdanm	82:6473597d706e	8154	#define BR_ENET_TCSRn_TMODE(x, n) (HW_ENET_TCSRn(x, n).B.TMODE)
bogdanm	82:6473597d706e	8155	#endif
bogdanm	82:6473597d706e	8156
bogdanm	82:6473597d706e	8157	//! @brief Format value for bitfield ENET_TCSRn_TMODE.
bogdanm	82:6473597d706e	8158	#define BF_ENET_TCSRn_TMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TMODE), uint32_t) & BM_ENET_TCSRn_TMODE)
bogdanm	82:6473597d706e	8159
bogdanm	82:6473597d706e	8160	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8161	//! @brief Set the TMODE field to a new value.
bogdanm	82:6473597d706e	8162	#define BW_ENET_TCSRn_TMODE(x, n, v) (HW_ENET_TCSRn_WR(x, n, (HW_ENET_TCSRn_RD(x, n) & ~BM_ENET_TCSRn_TMODE) \| BF_ENET_TCSRn_TMODE(v)))
bogdanm	82:6473597d706e	8163	#endif
bogdanm	82:6473597d706e	8164	//@}
bogdanm	82:6473597d706e	8165
bogdanm	82:6473597d706e	8166	/*!
bogdanm	82:6473597d706e	8167	* @name Register ENET_TCSRn, field TIE[6] (RW)
bogdanm	82:6473597d706e	8168	*
bogdanm	82:6473597d706e	8169	* Values:
bogdanm	82:6473597d706e	8170	* - 0 - Interrupt is disabled
bogdanm	82:6473597d706e	8171	* - 1 - Interrupt is enabled
bogdanm	82:6473597d706e	8172	*/
bogdanm	82:6473597d706e	8173	//@{
bogdanm	82:6473597d706e	8174	#define BP_ENET_TCSRn_TIE (6U) //!< Bit position for ENET_TCSRn_TIE.
bogdanm	82:6473597d706e	8175	#define BM_ENET_TCSRn_TIE (0x00000040U) //!< Bit mask for ENET_TCSRn_TIE.
bogdanm	82:6473597d706e	8176	#define BS_ENET_TCSRn_TIE (1U) //!< Bit field size in bits for ENET_TCSRn_TIE.
bogdanm	82:6473597d706e	8177
bogdanm	82:6473597d706e	8178	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8179	//! @brief Read current value of the ENET_TCSRn_TIE field.
bogdanm	82:6473597d706e	8180	#define BR_ENET_TCSRn_TIE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE))
bogdanm	82:6473597d706e	8181	#endif
bogdanm	82:6473597d706e	8182
bogdanm	82:6473597d706e	8183	//! @brief Format value for bitfield ENET_TCSRn_TIE.
bogdanm	82:6473597d706e	8184	#define BF_ENET_TCSRn_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TIE), uint32_t) & BM_ENET_TCSRn_TIE)
bogdanm	82:6473597d706e	8185
bogdanm	82:6473597d706e	8186	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8187	//! @brief Set the TIE field to a new value.
bogdanm	82:6473597d706e	8188	#define BW_ENET_TCSRn_TIE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE) = (v))
bogdanm	82:6473597d706e	8189	#endif
bogdanm	82:6473597d706e	8190	//@}
bogdanm	82:6473597d706e	8191
bogdanm	82:6473597d706e	8192	/*!
bogdanm	82:6473597d706e	8193	* @name Register ENET_TCSRn, field TF[7] (W1C)
bogdanm	82:6473597d706e	8194	*
bogdanm	82:6473597d706e	8195	* Sets when input capture or output compare occurs. This flag is double
bogdanm	82:6473597d706e	8196	* buffered between the module clock and 1588 clock domains. When this field is 1, it
bogdanm	82:6473597d706e	8197	* can be cleared to 0 by writing 1 to it.
bogdanm	82:6473597d706e	8198	*
bogdanm	82:6473597d706e	8199	* Values:
bogdanm	82:6473597d706e	8200	* - 0 - Input Capture or Output Compare has not occurred
bogdanm	82:6473597d706e	8201	* - 1 - Input Capture or Output Compare has occurred
bogdanm	82:6473597d706e	8202	*/
bogdanm	82:6473597d706e	8203	//@{
bogdanm	82:6473597d706e	8204	#define BP_ENET_TCSRn_TF (7U) //!< Bit position for ENET_TCSRn_TF.
bogdanm	82:6473597d706e	8205	#define BM_ENET_TCSRn_TF (0x00000080U) //!< Bit mask for ENET_TCSRn_TF.
bogdanm	82:6473597d706e	8206	#define BS_ENET_TCSRn_TF (1U) //!< Bit field size in bits for ENET_TCSRn_TF.
bogdanm	82:6473597d706e	8207
bogdanm	82:6473597d706e	8208	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8209	//! @brief Read current value of the ENET_TCSRn_TF field.
bogdanm	82:6473597d706e	8210	#define BR_ENET_TCSRn_TF(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF))
bogdanm	82:6473597d706e	8211	#endif
bogdanm	82:6473597d706e	8212
bogdanm	82:6473597d706e	8213	//! @brief Format value for bitfield ENET_TCSRn_TF.
bogdanm	82:6473597d706e	8214	#define BF_ENET_TCSRn_TF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TF), uint32_t) & BM_ENET_TCSRn_TF)
bogdanm	82:6473597d706e	8215
bogdanm	82:6473597d706e	8216	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8217	//! @brief Set the TF field to a new value.
bogdanm	82:6473597d706e	8218	#define BW_ENET_TCSRn_TF(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF) = (v))
bogdanm	82:6473597d706e	8219	#endif
bogdanm	82:6473597d706e	8220	//@}
bogdanm	82:6473597d706e	8221	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	8222	// HW_ENET_TCCRn - Timer Compare Capture Register
bogdanm	82:6473597d706e	8223	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	8224
bogdanm	82:6473597d706e	8225	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8226	/*!
bogdanm	82:6473597d706e	8227	* @brief HW_ENET_TCCRn - Timer Compare Capture Register (RW)
bogdanm	82:6473597d706e	8228	*
bogdanm	82:6473597d706e	8229	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	8230	*/
bogdanm	82:6473597d706e	8231	typedef union _hw_enet_tccrn
bogdanm	82:6473597d706e	8232	{
bogdanm	82:6473597d706e	8233	uint32_t U;
bogdanm	82:6473597d706e	8234	struct _hw_enet_tccrn_bitfields
bogdanm	82:6473597d706e	8235	{
bogdanm	82:6473597d706e	8236	uint32_t TCC : 32; //!< [31:0] Timer Capture Compare
bogdanm	82:6473597d706e	8237	} B;
bogdanm	82:6473597d706e	8238	} hw_enet_tccrn_t;
bogdanm	82:6473597d706e	8239	#endif
bogdanm	82:6473597d706e	8240
bogdanm	82:6473597d706e	8241	/*!
bogdanm	82:6473597d706e	8242	* @name Constants and macros for entire ENET_TCCRn register
bogdanm	82:6473597d706e	8243	*/
bogdanm	82:6473597d706e	8244	//@{
bogdanm	82:6473597d706e	8245	#define HW_ENET_TCCRn_COUNT (4U)
bogdanm	82:6473597d706e	8246
bogdanm	82:6473597d706e	8247	#define HW_ENET_TCCRn_ADDR(x, n) (REGS_ENET_BASE(x) + 0x60CU + (0x8U * n))
bogdanm	82:6473597d706e	8248
bogdanm	82:6473597d706e	8249	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8250	#define HW_ENET_TCCRn(x, n) ((__IO hw_enet_tccrn_t ) HW_ENET_TCCRn_ADDR(x, n))
bogdanm	82:6473597d706e	8251	#define HW_ENET_TCCRn_RD(x, n) (HW_ENET_TCCRn(x, n).U)
bogdanm	82:6473597d706e	8252	#define HW_ENET_TCCRn_WR(x, n, v) (HW_ENET_TCCRn(x, n).U = (v))
bogdanm	82:6473597d706e	8253	#define HW_ENET_TCCRn_SET(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	8254	#define HW_ENET_TCCRn_CLR(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	8255	#define HW_ENET_TCCRn_TOG(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	8256	#endif
bogdanm	82:6473597d706e	8257	//@}
bogdanm	82:6473597d706e	8258
bogdanm	82:6473597d706e	8259	/*
bogdanm	82:6473597d706e	8260	* Constants & macros for individual ENET_TCCRn bitfields
bogdanm	82:6473597d706e	8261	*/
bogdanm	82:6473597d706e	8262
bogdanm	82:6473597d706e	8263	/*!
bogdanm	82:6473597d706e	8264	* @name Register ENET_TCCRn, field TCC[31:0] (RW)
bogdanm	82:6473597d706e	8265	*
bogdanm	82:6473597d706e	8266	* This register is double buffered between the module clock and 1588 clock
bogdanm	82:6473597d706e	8267	* domains. When configured for compare, the 1588 clock domain updates with the value
bogdanm	82:6473597d706e	8268	* in the module clock domain whenever the Timer Channel is first enabled and on
bogdanm	82:6473597d706e	8269	* each subsequent compare. Write to this register with the first compare value
bogdanm	82:6473597d706e	8270	* before enabling the Timer Channel. When the Timer Channel is enabled, write
bogdanm	82:6473597d706e	8271	* the second compare value either immediately, or at least before the first
bogdanm	82:6473597d706e	8272	* compare occurs. After each compare, write the next compare value before the previous
bogdanm	82:6473597d706e	8273	* compare occurs and before clearing the Timer Flag. The compare occurs one
bogdanm	82:6473597d706e	8274	* 1588 clock cycle after the IEEE 1588 Counter increments past the compare value in
bogdanm	82:6473597d706e	8275	* the 1588 clock domain. If the compare value is less than the value of the
bogdanm	82:6473597d706e	8276	* 1588 Counter when the Timer Channel is first enabled, then the compare does not
bogdanm	82:6473597d706e	8277	* occur until following the next overflow of the 1588 Counter. If the compare
bogdanm	82:6473597d706e	8278	* value is greater than the IEEE 1588 Counter when the 1588 Counter overflows, or
bogdanm	82:6473597d706e	8279	* the compare value is less than the value of the IEEE 1588 Counter after the
bogdanm	82:6473597d706e	8280	* overflow, then the compare occurs one 1588 clock cycle following the overflow.
bogdanm	82:6473597d706e	8281	* When configured for Capture, the value of the IEEE 1588 Counter is captured into
bogdanm	82:6473597d706e	8282	* the 1588 clock domain and then updated into the module clock domain, provided
bogdanm	82:6473597d706e	8283	* the Timer Flag is clear. Always read the capture value before clearing the
bogdanm	82:6473597d706e	8284	* Timer Flag.
bogdanm	82:6473597d706e	8285	*/
bogdanm	82:6473597d706e	8286	//@{
bogdanm	82:6473597d706e	8287	#define BP_ENET_TCCRn_TCC (0U) //!< Bit position for ENET_TCCRn_TCC.
bogdanm	82:6473597d706e	8288	#define BM_ENET_TCCRn_TCC (0xFFFFFFFFU) //!< Bit mask for ENET_TCCRn_TCC.
bogdanm	82:6473597d706e	8289	#define BS_ENET_TCCRn_TCC (32U) //!< Bit field size in bits for ENET_TCCRn_TCC.
bogdanm	82:6473597d706e	8290
bogdanm	82:6473597d706e	8291	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8292	//! @brief Read current value of the ENET_TCCRn_TCC field.
bogdanm	82:6473597d706e	8293	#define BR_ENET_TCCRn_TCC(x, n) (HW_ENET_TCCRn(x, n).U)
bogdanm	82:6473597d706e	8294	#endif
bogdanm	82:6473597d706e	8295
bogdanm	82:6473597d706e	8296	//! @brief Format value for bitfield ENET_TCCRn_TCC.
bogdanm	82:6473597d706e	8297	#define BF_ENET_TCCRn_TCC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCCRn_TCC), uint32_t) & BM_ENET_TCCRn_TCC)
bogdanm	82:6473597d706e	8298
bogdanm	82:6473597d706e	8299	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8300	//! @brief Set the TCC field to a new value.
bogdanm	82:6473597d706e	8301	#define BW_ENET_TCCRn_TCC(x, n, v) (HW_ENET_TCCRn_WR(x, n, v))
bogdanm	82:6473597d706e	8302	#endif
bogdanm	82:6473597d706e	8303	//@}
bogdanm	82:6473597d706e	8304
bogdanm	82:6473597d706e	8305	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	8306	// hw_enet_t - module struct
bogdanm	82:6473597d706e	8307	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	8308	/*!
bogdanm	82:6473597d706e	8309	* @brief All ENET module registers.
bogdanm	82:6473597d706e	8310	*/
bogdanm	82:6473597d706e	8311	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	8312	#pragma pack(1)
bogdanm	82:6473597d706e	8313	typedef struct _hw_enet
bogdanm	82:6473597d706e	8314	{
bogdanm	82:6473597d706e	8315	uint8_t _reserved0[4];
bogdanm	82:6473597d706e	8316	__IO hw_enet_eir_t EIR; //!< [0x4] Interrupt Event Register
bogdanm	82:6473597d706e	8317	__IO hw_enet_eimr_t EIMR; //!< [0x8] Interrupt Mask Register
bogdanm	82:6473597d706e	8318	uint8_t _reserved1[4];
bogdanm	82:6473597d706e	8319	__IO hw_enet_rdar_t RDAR; //!< [0x10] Receive Descriptor Active Register
bogdanm	82:6473597d706e	8320	__IO hw_enet_tdar_t TDAR; //!< [0x14] Transmit Descriptor Active Register
bogdanm	82:6473597d706e	8321	uint8_t _reserved2[12];
bogdanm	82:6473597d706e	8322	__IO hw_enet_ecr_t ECR; //!< [0x24] Ethernet Control Register
bogdanm	82:6473597d706e	8323	uint8_t _reserved3[24];
bogdanm	82:6473597d706e	8324	__IO hw_enet_mmfr_t MMFR; //!< [0x40] MII Management Frame Register
bogdanm	82:6473597d706e	8325	__IO hw_enet_mscr_t MSCR; //!< [0x44] MII Speed Control Register
bogdanm	82:6473597d706e	8326	uint8_t _reserved4[28];
bogdanm	82:6473597d706e	8327	__IO hw_enet_mibc_t MIBC; //!< [0x64] MIB Control Register
bogdanm	82:6473597d706e	8328	uint8_t _reserved5[28];
bogdanm	82:6473597d706e	8329	__IO hw_enet_rcr_t RCR; //!< [0x84] Receive Control Register
bogdanm	82:6473597d706e	8330	uint8_t _reserved6[60];
bogdanm	82:6473597d706e	8331	__IO hw_enet_tcr_t TCR; //!< [0xC4] Transmit Control Register
bogdanm	82:6473597d706e	8332	uint8_t _reserved7[28];
bogdanm	82:6473597d706e	8333	__IO hw_enet_palr_t PALR; //!< [0xE4] Physical Address Lower Register
bogdanm	82:6473597d706e	8334	__IO hw_enet_paur_t PAUR; //!< [0xE8] Physical Address Upper Register
bogdanm	82:6473597d706e	8335	__IO hw_enet_opd_t OPD; //!< [0xEC] Opcode/Pause Duration Register
bogdanm	82:6473597d706e	8336	uint8_t _reserved8[40];
bogdanm	82:6473597d706e	8337	__IO hw_enet_iaur_t IAUR; //!< [0x118] Descriptor Individual Upper Address Register
bogdanm	82:6473597d706e	8338	__IO hw_enet_ialr_t IALR; //!< [0x11C] Descriptor Individual Lower Address Register
bogdanm	82:6473597d706e	8339	__IO hw_enet_gaur_t GAUR; //!< [0x120] Descriptor Group Upper Address Register
bogdanm	82:6473597d706e	8340	__IO hw_enet_galr_t GALR; //!< [0x124] Descriptor Group Lower Address Register
bogdanm	82:6473597d706e	8341	uint8_t _reserved9[28];
bogdanm	82:6473597d706e	8342	__IO hw_enet_tfwr_t TFWR; //!< [0x144] Transmit FIFO Watermark Register
bogdanm	82:6473597d706e	8343	uint8_t _reserved10[56];
bogdanm	82:6473597d706e	8344	__IO hw_enet_rdsr_t RDSR; //!< [0x180] Receive Descriptor Ring Start Register
bogdanm	82:6473597d706e	8345	__IO hw_enet_tdsr_t TDSR; //!< [0x184] Transmit Buffer Descriptor Ring Start Register
bogdanm	82:6473597d706e	8346	__IO hw_enet_mrbr_t MRBR; //!< [0x188] Maximum Receive Buffer Size Register
bogdanm	82:6473597d706e	8347	uint8_t _reserved11[4];
bogdanm	82:6473597d706e	8348	__IO hw_enet_rsfl_t RSFL; //!< [0x190] Receive FIFO Section Full Threshold
bogdanm	82:6473597d706e	8349	__IO hw_enet_rsem_t RSEM; //!< [0x194] Receive FIFO Section Empty Threshold
bogdanm	82:6473597d706e	8350	__IO hw_enet_raem_t RAEM; //!< [0x198] Receive FIFO Almost Empty Threshold
bogdanm	82:6473597d706e	8351	__IO hw_enet_rafl_t RAFL; //!< [0x19C] Receive FIFO Almost Full Threshold
bogdanm	82:6473597d706e	8352	__IO hw_enet_tsem_t TSEM; //!< [0x1A0] Transmit FIFO Section Empty Threshold
bogdanm	82:6473597d706e	8353	__IO hw_enet_taem_t TAEM; //!< [0x1A4] Transmit FIFO Almost Empty Threshold
bogdanm	82:6473597d706e	8354	__IO hw_enet_tafl_t TAFL; //!< [0x1A8] Transmit FIFO Almost Full Threshold
bogdanm	82:6473597d706e	8355	__IO hw_enet_tipg_t TIPG; //!< [0x1AC] Transmit Inter-Packet Gap
bogdanm	82:6473597d706e	8356	__IO hw_enet_ftrl_t FTRL; //!< [0x1B0] Frame Truncation Length
bogdanm	82:6473597d706e	8357	uint8_t _reserved12[12];
bogdanm	82:6473597d706e	8358	__IO hw_enet_tacc_t TACC; //!< [0x1C0] Transmit Accelerator Function Configuration
bogdanm	82:6473597d706e	8359	__IO hw_enet_racc_t RACC; //!< [0x1C4] Receive Accelerator Function Configuration
bogdanm	82:6473597d706e	8360	uint8_t _reserved13[60];
bogdanm	82:6473597d706e	8361	__I hw_enet_rmon_t_packets_t RMON_T_PACKETS; //!< [0x204] Tx Packet Count Statistic Register
bogdanm	82:6473597d706e	8362	__I hw_enet_rmon_t_bc_pkt_t RMON_T_BC_PKT; //!< [0x208] Tx Broadcast Packets Statistic Register
bogdanm	82:6473597d706e	8363	__I hw_enet_rmon_t_mc_pkt_t RMON_T_MC_PKT; //!< [0x20C] Tx Multicast Packets Statistic Register
bogdanm	82:6473597d706e	8364	__I hw_enet_rmon_t_crc_align_t RMON_T_CRC_ALIGN; //!< [0x210] Tx Packets with CRC/Align Error Statistic Register
bogdanm	82:6473597d706e	8365	__I hw_enet_rmon_t_undersize_t RMON_T_UNDERSIZE; //!< [0x214] Tx Packets Less Than Bytes and Good CRC Statistic Register
bogdanm	82:6473597d706e	8366	__I hw_enet_rmon_t_oversize_t RMON_T_OVERSIZE; //!< [0x218] Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
bogdanm	82:6473597d706e	8367	__I hw_enet_rmon_t_frag_t RMON_T_FRAG; //!< [0x21C] Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
bogdanm	82:6473597d706e	8368	__I hw_enet_rmon_t_jab_t RMON_T_JAB; //!< [0x220] Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
bogdanm	82:6473597d706e	8369	__I hw_enet_rmon_t_col_t RMON_T_COL; //!< [0x224] Tx Collision Count Statistic Register
bogdanm	82:6473597d706e	8370	__I hw_enet_rmon_t_p64_t RMON_T_P64; //!< [0x228] Tx 64-Byte Packets Statistic Register
bogdanm	82:6473597d706e	8371	__I hw_enet_rmon_t_p65to127_t RMON_T_P65TO127; //!< [0x22C] Tx 65- to 127-byte Packets Statistic Register
bogdanm	82:6473597d706e	8372	__I hw_enet_rmon_t_p128to255_t RMON_T_P128TO255; //!< [0x230] Tx 128- to 255-byte Packets Statistic Register
bogdanm	82:6473597d706e	8373	__I hw_enet_rmon_t_p256to511_t RMON_T_P256TO511; //!< [0x234] Tx 256- to 511-byte Packets Statistic Register
bogdanm	82:6473597d706e	8374	__I hw_enet_rmon_t_p512to1023_t RMON_T_P512TO1023; //!< [0x238] Tx 512- to 1023-byte Packets Statistic Register
bogdanm	82:6473597d706e	8375	__I hw_enet_rmon_t_p1024to2047_t RMON_T_P1024TO2047; //!< [0x23C] Tx 1024- to 2047-byte Packets Statistic Register
bogdanm	82:6473597d706e	8376	__I hw_enet_rmon_t_p_gte2048_t RMON_T_P_GTE2048; //!< [0x240] Tx Packets Greater Than 2048 Bytes Statistic Register
bogdanm	82:6473597d706e	8377	__I hw_enet_rmon_t_octets_t RMON_T_OCTETS; //!< [0x244] Tx Octets Statistic Register
bogdanm	82:6473597d706e	8378	uint8_t _reserved14[4];
bogdanm	82:6473597d706e	8379	__I hw_enet_ieee_t_frame_ok_t IEEE_T_FRAME_OK; //!< [0x24C] Frames Transmitted OK Statistic Register
bogdanm	82:6473597d706e	8380	__I hw_enet_ieee_t_1col_t IEEE_T_1COL; //!< [0x250] Frames Transmitted with Single Collision Statistic Register
bogdanm	82:6473597d706e	8381	__I hw_enet_ieee_t_mcol_t IEEE_T_MCOL; //!< [0x254] Frames Transmitted with Multiple Collisions Statistic Register
bogdanm	82:6473597d706e	8382	__I hw_enet_ieee_t_def_t IEEE_T_DEF; //!< [0x258] Frames Transmitted after Deferral Delay Statistic Register
bogdanm	82:6473597d706e	8383	__I hw_enet_ieee_t_lcol_t IEEE_T_LCOL; //!< [0x25C] Frames Transmitted with Late Collision Statistic Register
bogdanm	82:6473597d706e	8384	__I hw_enet_ieee_t_excol_t IEEE_T_EXCOL; //!< [0x260] Frames Transmitted with Excessive Collisions Statistic Register
bogdanm	82:6473597d706e	8385	__I hw_enet_ieee_t_macerr_t IEEE_T_MACERR; //!< [0x264] Frames Transmitted with Tx FIFO Underrun Statistic Register
bogdanm	82:6473597d706e	8386	__I hw_enet_ieee_t_cserr_t IEEE_T_CSERR; //!< [0x268] Frames Transmitted with Carrier Sense Error Statistic Register
bogdanm	82:6473597d706e	8387	uint8_t _reserved15[4];
bogdanm	82:6473597d706e	8388	__I hw_enet_ieee_t_fdxfc_t IEEE_T_FDXFC; //!< [0x270] Flow Control Pause Frames Transmitted Statistic Register
bogdanm	82:6473597d706e	8389	__I hw_enet_ieee_t_octets_ok_t IEEE_T_OCTETS_OK; //!< [0x274] Octet Count for Frames Transmitted w/o Error Statistic Register
bogdanm	82:6473597d706e	8390	uint8_t _reserved16[12];
bogdanm	82:6473597d706e	8391	__I hw_enet_rmon_r_packets_t RMON_R_PACKETS; //!< [0x284] Rx Packet Count Statistic Register
bogdanm	82:6473597d706e	8392	__I hw_enet_rmon_r_bc_pkt_t RMON_R_BC_PKT; //!< [0x288] Rx Broadcast Packets Statistic Register
bogdanm	82:6473597d706e	8393	__I hw_enet_rmon_r_mc_pkt_t RMON_R_MC_PKT; //!< [0x28C] Rx Multicast Packets Statistic Register
bogdanm	82:6473597d706e	8394	__I hw_enet_rmon_r_crc_align_t RMON_R_CRC_ALIGN; //!< [0x290] Rx Packets with CRC/Align Error Statistic Register
bogdanm	82:6473597d706e	8395	__I hw_enet_rmon_r_undersize_t RMON_R_UNDERSIZE; //!< [0x294] Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
bogdanm	82:6473597d706e	8396	__I hw_enet_rmon_r_oversize_t RMON_R_OVERSIZE; //!< [0x298] Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
bogdanm	82:6473597d706e	8397	__I hw_enet_rmon_r_frag_t RMON_R_FRAG; //!< [0x29C] Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
bogdanm	82:6473597d706e	8398	__I hw_enet_rmon_r_jab_t RMON_R_JAB; //!< [0x2A0] Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
bogdanm	82:6473597d706e	8399	uint8_t _reserved17[4];
bogdanm	82:6473597d706e	8400	__I hw_enet_rmon_r_p64_t RMON_R_P64; //!< [0x2A8] Rx 64-Byte Packets Statistic Register
bogdanm	82:6473597d706e	8401	__I hw_enet_rmon_r_p65to127_t RMON_R_P65TO127; //!< [0x2AC] Rx 65- to 127-Byte Packets Statistic Register
bogdanm	82:6473597d706e	8402	__I hw_enet_rmon_r_p128to255_t RMON_R_P128TO255; //!< [0x2B0] Rx 128- to 255-Byte Packets Statistic Register
bogdanm	82:6473597d706e	8403	__I hw_enet_rmon_r_p256to511_t RMON_R_P256TO511; //!< [0x2B4] Rx 256- to 511-Byte Packets Statistic Register
bogdanm	82:6473597d706e	8404	__I hw_enet_rmon_r_p512to1023_t RMON_R_P512TO1023; //!< [0x2B8] Rx 512- to 1023-Byte Packets Statistic Register
bogdanm	82:6473597d706e	8405	__I hw_enet_rmon_r_p1024to2047_t RMON_R_P1024TO2047; //!< [0x2BC] Rx 1024- to 2047-Byte Packets Statistic Register
bogdanm	82:6473597d706e	8406	__I hw_enet_rmon_r_gte2048_t RMON_R_GTE2048; //!< [0x2C0] Rx Packets Greater than 2048 Bytes Statistic Register
bogdanm	82:6473597d706e	8407	__I hw_enet_rmon_r_octets_t RMON_R_OCTETS; //!< [0x2C4] Rx Octets Statistic Register
bogdanm	82:6473597d706e	8408	__I hw_enet_ieee_r_drop_t IEEE_R_DROP; //!< [0x2C8] Frames not Counted Correctly Statistic Register
bogdanm	82:6473597d706e	8409	__I hw_enet_ieee_r_frame_ok_t IEEE_R_FRAME_OK; //!< [0x2CC] Frames Received OK Statistic Register
bogdanm	82:6473597d706e	8410	__I hw_enet_ieee_r_crc_t IEEE_R_CRC; //!< [0x2D0] Frames Received with CRC Error Statistic Register
bogdanm	82:6473597d706e	8411	__I hw_enet_ieee_r_align_t IEEE_R_ALIGN; //!< [0x2D4] Frames Received with Alignment Error Statistic Register
bogdanm	82:6473597d706e	8412	__I hw_enet_ieee_r_macerr_t IEEE_R_MACERR; //!< [0x2D8] Receive FIFO Overflow Count Statistic Register
bogdanm	82:6473597d706e	8413	__I hw_enet_ieee_r_fdxfc_t IEEE_R_FDXFC; //!< [0x2DC] Flow Control Pause Frames Received Statistic Register
bogdanm	82:6473597d706e	8414	__I hw_enet_ieee_r_octets_ok_t IEEE_R_OCTETS_OK; //!< [0x2E0] Octet Count for Frames Received without Error Statistic Register
bogdanm	82:6473597d706e	8415	uint8_t _reserved18[284];
bogdanm	82:6473597d706e	8416	__IO hw_enet_atcr_t ATCR; //!< [0x400] Adjustable Timer Control Register
bogdanm	82:6473597d706e	8417	__IO hw_enet_atvr_t ATVR; //!< [0x404] Timer Value Register
bogdanm	82:6473597d706e	8418	__IO hw_enet_atoff_t ATOFF; //!< [0x408] Timer Offset Register
bogdanm	82:6473597d706e	8419	__IO hw_enet_atper_t ATPER; //!< [0x40C] Timer Period Register
bogdanm	82:6473597d706e	8420	__IO hw_enet_atcor_t ATCOR; //!< [0x410] Timer Correction Register
bogdanm	82:6473597d706e	8421	__IO hw_enet_atinc_t ATINC; //!< [0x414] Time-Stamping Clock Period Register
bogdanm	82:6473597d706e	8422	__I hw_enet_atstmp_t ATSTMP; //!< [0x418] Timestamp of Last Transmitted Frame
bogdanm	82:6473597d706e	8423	uint8_t _reserved19[488];
bogdanm	82:6473597d706e	8424	__IO hw_enet_tgsr_t TGSR; //!< [0x604] Timer Global Status Register
bogdanm	82:6473597d706e	8425	struct {
bogdanm	82:6473597d706e	8426	__IO hw_enet_tcsrn_t TCSRn; //!< [0x608] Timer Control Status Register
bogdanm	82:6473597d706e	8427	__IO hw_enet_tccrn_t TCCRn; //!< [0x60C] Timer Compare Capture Register
bogdanm	82:6473597d706e	8428	} CHANNEL[4];
bogdanm	82:6473597d706e	8429	} hw_enet_t;
bogdanm	82:6473597d706e	8430	#pragma pack()
bogdanm	82:6473597d706e	8431
bogdanm	82:6473597d706e	8432	//! @brief Macro to access all ENET registers.
bogdanm	82:6473597d706e	8433	//! @param x ENET instance number.
bogdanm	82:6473597d706e	8434	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	8435	//! use the '&' operator, like <code>&HW_ENET(0)</code>.
bogdanm	82:6473597d706e	8436	#define HW_ENET(x) ((hw_enet_t ) REGS_ENET_BASE(x))
bogdanm	82:6473597d706e	8437	#endif
bogdanm	82:6473597d706e	8438
bogdanm	82:6473597d706e	8439	#endif // __HW_ENET_REGISTERS_H__
bogdanm	82:6473597d706e	8440	// v22/130726/0.9
bogdanm	82:6473597d706e	8441	// EOF

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Type:	Library
Created:	25 Jun 2015
Imports:	24
Forks:	0
Commits:	103
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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_enet.h@89:552587b429a1, 2014-09-12 (annotated)

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