Julien Kern / mbed

mbed library

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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_cmt.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:
bogdanm
Date:
Fri Sep 12 16:41:52 2014 +0100
Revision:
89:552587b429a1
Parent:
TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_cmt.h@82:6473597d706e 
Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_CMT_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_CMT_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 CMT
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * Carrier Modulator Transmitter
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
bogdanm 82:6473597d706e 33 * - HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
bogdanm 82:6473597d706e 34 * - HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
bogdanm 82:6473597d706e 35 * - HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
bogdanm 82:6473597d706e 36 * - HW_CMT_OC - CMT Output Control Register
bogdanm 82:6473597d706e 37 * - HW_CMT_MSC - CMT Modulator Status and Control Register
bogdanm 82:6473597d706e 38 * - HW_CMT_CMD1 - CMT Modulator Data Register Mark High
bogdanm 82:6473597d706e 39 * - HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
bogdanm 82:6473597d706e 40 * - HW_CMT_CMD3 - CMT Modulator Data Register Space High
bogdanm 82:6473597d706e 41 * - HW_CMT_CMD4 - CMT Modulator Data Register Space Low
bogdanm 82:6473597d706e 42 * - HW_CMT_PPS - CMT Primary Prescaler Register
bogdanm 82:6473597d706e 43 * - HW_CMT_DMA - CMT Direct Memory Access Register
bogdanm 82:6473597d706e 44 *
bogdanm 82:6473597d706e 45 * - hw_cmt_t - Struct containing all module registers.
bogdanm 82:6473597d706e 46 */
bogdanm 82:6473597d706e 47
bogdanm 82:6473597d706e 48 //! @name Module base addresses
bogdanm 82:6473597d706e 49 //@{
bogdanm 82:6473597d706e 50 #ifndef REGS_CMT_BASE
bogdanm 82:6473597d706e 51 #define HW_CMT_INSTANCE_COUNT (1U) //!< Number of instances of the CMT module.
bogdanm 82:6473597d706e 52 #define REGS_CMT_BASE (0x40062000U) //!< Base address for CMT.
bogdanm 82:6473597d706e 53 #endif
bogdanm 82:6473597d706e 54 //@}
bogdanm 82:6473597d706e 55
bogdanm 82:6473597d706e 56 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 57 // HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
bogdanm 82:6473597d706e 58 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 59
bogdanm 82:6473597d706e 60 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 61 /*!
bogdanm 82:6473597d706e 62 * @brief HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
bogdanm 82:6473597d706e 63 *
bogdanm 82:6473597d706e 64 * Reset value: 0x00U
bogdanm 82:6473597d706e 65 *
bogdanm 82:6473597d706e 66 * This data register contains the primary high value for generating the carrier
bogdanm 82:6473597d706e 67 * output.
bogdanm 82:6473597d706e 68 */
bogdanm 82:6473597d706e 69 typedef union _hw_cmt_cgh1
bogdanm 82:6473597d706e 70 {
bogdanm 82:6473597d706e 71 uint8_t U;
bogdanm 82:6473597d706e 72 struct _hw_cmt_cgh1_bitfields
bogdanm 82:6473597d706e 73 {
bogdanm 82:6473597d706e 74 uint8_t PH : 8; //!< [7:0] Primary Carrier High Time Data Value
bogdanm 82:6473597d706e 75 } B;
bogdanm 82:6473597d706e 76 } hw_cmt_cgh1_t;
bogdanm 82:6473597d706e 77 #endif
bogdanm 82:6473597d706e 78
bogdanm 82:6473597d706e 79 /*!
bogdanm 82:6473597d706e 80 * @name Constants and macros for entire CMT_CGH1 register
bogdanm 82:6473597d706e 81 */
bogdanm 82:6473597d706e 82 //@{
bogdanm 82:6473597d706e 83 #define HW_CMT_CGH1_ADDR (REGS_CMT_BASE + 0x0U)
bogdanm 82:6473597d706e 84
bogdanm 82:6473597d706e 85 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 86 #define HW_CMT_CGH1 (*(__IO hw_cmt_cgh1_t *) HW_CMT_CGH1_ADDR)
bogdanm 82:6473597d706e 87 #define HW_CMT_CGH1_RD() (HW_CMT_CGH1.U)
bogdanm 82:6473597d706e 88 #define HW_CMT_CGH1_WR(v) (HW_CMT_CGH1.U = (v))
bogdanm 82:6473597d706e 89 #define HW_CMT_CGH1_SET(v) (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() | (v)))
bogdanm 82:6473597d706e 90 #define HW_CMT_CGH1_CLR(v) (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() & ~(v)))
bogdanm 82:6473597d706e 91 #define HW_CMT_CGH1_TOG(v) (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() ^ (v)))
bogdanm 82:6473597d706e 92 #endif
bogdanm 82:6473597d706e 93 //@}
bogdanm 82:6473597d706e 94
bogdanm 82:6473597d706e 95 /*
bogdanm 82:6473597d706e 96 * Constants & macros for individual CMT_CGH1 bitfields
bogdanm 82:6473597d706e 97 */
bogdanm 82:6473597d706e 98
bogdanm 82:6473597d706e 99 /*!
bogdanm 82:6473597d706e 100 * @name Register CMT_CGH1, field PH[7:0] (RW)
bogdanm 82:6473597d706e 101 *
bogdanm 82:6473597d706e 102 * Contains the number of input clocks required to generate the carrier high
bogdanm 82:6473597d706e 103 * time period. When operating in Time mode, this register is always selected. When
bogdanm 82:6473597d706e 104 * operating in FSK mode, this register and the secondary register pair are
bogdanm 82:6473597d706e 105 * alternately selected under the control of the modulator. The primary carrier high
bogdanm 82:6473597d706e 106 * time value is undefined out of reset. This register must be written to nonzero
bogdanm 82:6473597d706e 107 * values before the carrier generator is enabled to avoid spurious results.
bogdanm 82:6473597d706e 108 */
bogdanm 82:6473597d706e 109 //@{
bogdanm 82:6473597d706e 110 #define BP_CMT_CGH1_PH (0U) //!< Bit position for CMT_CGH1_PH.
bogdanm 82:6473597d706e 111 #define BM_CMT_CGH1_PH (0xFFU) //!< Bit mask for CMT_CGH1_PH.
bogdanm 82:6473597d706e 112 #define BS_CMT_CGH1_PH (8U) //!< Bit field size in bits for CMT_CGH1_PH.
bogdanm 82:6473597d706e 113
bogdanm 82:6473597d706e 114 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 115 //! @brief Read current value of the CMT_CGH1_PH field.
bogdanm 82:6473597d706e 116 #define BR_CMT_CGH1_PH (HW_CMT_CGH1.U)
bogdanm 82:6473597d706e 117 #endif
bogdanm 82:6473597d706e 118
bogdanm 82:6473597d706e 119 //! @brief Format value for bitfield CMT_CGH1_PH.
bogdanm 82:6473597d706e 120 #define BF_CMT_CGH1_PH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGH1_PH), uint8_t) & BM_CMT_CGH1_PH)
bogdanm 82:6473597d706e 121
bogdanm 82:6473597d706e 122 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 123 //! @brief Set the PH field to a new value.
bogdanm 82:6473597d706e 124 #define BW_CMT_CGH1_PH(v) (HW_CMT_CGH1_WR(v))
bogdanm 82:6473597d706e 125 #endif
bogdanm 82:6473597d706e 126 //@}
bogdanm 82:6473597d706e 127
bogdanm 82:6473597d706e 128 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 129 // HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
bogdanm 82:6473597d706e 130 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 131
bogdanm 82:6473597d706e 132 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 133 /*!
bogdanm 82:6473597d706e 134 * @brief HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
bogdanm 82:6473597d706e 135 *
bogdanm 82:6473597d706e 136 * Reset value: 0x00U
bogdanm 82:6473597d706e 137 *
bogdanm 82:6473597d706e 138 * This data register contains the primary low value for generating the carrier
bogdanm 82:6473597d706e 139 * output.
bogdanm 82:6473597d706e 140 */
bogdanm 82:6473597d706e 141 typedef union _hw_cmt_cgl1
bogdanm 82:6473597d706e 142 {
bogdanm 82:6473597d706e 143 uint8_t U;
bogdanm 82:6473597d706e 144 struct _hw_cmt_cgl1_bitfields
bogdanm 82:6473597d706e 145 {
bogdanm 82:6473597d706e 146 uint8_t PL : 8; //!< [7:0] Primary Carrier Low Time Data Value
bogdanm 82:6473597d706e 147 } B;
bogdanm 82:6473597d706e 148 } hw_cmt_cgl1_t;
bogdanm 82:6473597d706e 149 #endif
bogdanm 82:6473597d706e 150
bogdanm 82:6473597d706e 151 /*!
bogdanm 82:6473597d706e 152 * @name Constants and macros for entire CMT_CGL1 register
bogdanm 82:6473597d706e 153 */
bogdanm 82:6473597d706e 154 //@{
bogdanm 82:6473597d706e 155 #define HW_CMT_CGL1_ADDR (REGS_CMT_BASE + 0x1U)
bogdanm 82:6473597d706e 156
bogdanm 82:6473597d706e 157 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 158 #define HW_CMT_CGL1 (*(__IO hw_cmt_cgl1_t *) HW_CMT_CGL1_ADDR)
bogdanm 82:6473597d706e 159 #define HW_CMT_CGL1_RD() (HW_CMT_CGL1.U)
bogdanm 82:6473597d706e 160 #define HW_CMT_CGL1_WR(v) (HW_CMT_CGL1.U = (v))
bogdanm 82:6473597d706e 161 #define HW_CMT_CGL1_SET(v) (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() | (v)))
bogdanm 82:6473597d706e 162 #define HW_CMT_CGL1_CLR(v) (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() & ~(v)))
bogdanm 82:6473597d706e 163 #define HW_CMT_CGL1_TOG(v) (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() ^ (v)))
bogdanm 82:6473597d706e 164 #endif
bogdanm 82:6473597d706e 165 //@}
bogdanm 82:6473597d706e 166
bogdanm 82:6473597d706e 167 /*
bogdanm 82:6473597d706e 168 * Constants & macros for individual CMT_CGL1 bitfields
bogdanm 82:6473597d706e 169 */
bogdanm 82:6473597d706e 170
bogdanm 82:6473597d706e 171 /*!
bogdanm 82:6473597d706e 172 * @name Register CMT_CGL1, field PL[7:0] (RW)
bogdanm 82:6473597d706e 173 *
bogdanm 82:6473597d706e 174 * Contains the number of input clocks required to generate the carrier low time
bogdanm 82:6473597d706e 175 * period. When operating in Time mode, this register is always selected. When
bogdanm 82:6473597d706e 176 * operating in FSK mode, this register and the secondary register pair are
bogdanm 82:6473597d706e 177 * alternately selected under the control of the modulator. The primary carrier low
bogdanm 82:6473597d706e 178 * time value is undefined out of reset. This register must be written to nonzero
bogdanm 82:6473597d706e 179 * values before the carrier generator is enabled to avoid spurious results.
bogdanm 82:6473597d706e 180 */
bogdanm 82:6473597d706e 181 //@{
bogdanm 82:6473597d706e 182 #define BP_CMT_CGL1_PL (0U) //!< Bit position for CMT_CGL1_PL.
bogdanm 82:6473597d706e 183 #define BM_CMT_CGL1_PL (0xFFU) //!< Bit mask for CMT_CGL1_PL.
bogdanm 82:6473597d706e 184 #define BS_CMT_CGL1_PL (8U) //!< Bit field size in bits for CMT_CGL1_PL.
bogdanm 82:6473597d706e 185
bogdanm 82:6473597d706e 186 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 187 //! @brief Read current value of the CMT_CGL1_PL field.
bogdanm 82:6473597d706e 188 #define BR_CMT_CGL1_PL (HW_CMT_CGL1.U)
bogdanm 82:6473597d706e 189 #endif
bogdanm 82:6473597d706e 190
bogdanm 82:6473597d706e 191 //! @brief Format value for bitfield CMT_CGL1_PL.
bogdanm 82:6473597d706e 192 #define BF_CMT_CGL1_PL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGL1_PL), uint8_t) & BM_CMT_CGL1_PL)
bogdanm 82:6473597d706e 193
bogdanm 82:6473597d706e 194 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 195 //! @brief Set the PL field to a new value.
bogdanm 82:6473597d706e 196 #define BW_CMT_CGL1_PL(v) (HW_CMT_CGL1_WR(v))
bogdanm 82:6473597d706e 197 #endif
bogdanm 82:6473597d706e 198 //@}
bogdanm 82:6473597d706e 199
bogdanm 82:6473597d706e 200 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 201 // HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
bogdanm 82:6473597d706e 202 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 203
bogdanm 82:6473597d706e 204 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 205 /*!
bogdanm 82:6473597d706e 206 * @brief HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
bogdanm 82:6473597d706e 207 *
bogdanm 82:6473597d706e 208 * Reset value: 0x00U
bogdanm 82:6473597d706e 209 *
bogdanm 82:6473597d706e 210 * This data register contains the secondary high value for generating the
bogdanm 82:6473597d706e 211 * carrier output.
bogdanm 82:6473597d706e 212 */
bogdanm 82:6473597d706e 213 typedef union _hw_cmt_cgh2
bogdanm 82:6473597d706e 214 {
bogdanm 82:6473597d706e 215 uint8_t U;
bogdanm 82:6473597d706e 216 struct _hw_cmt_cgh2_bitfields
bogdanm 82:6473597d706e 217 {
bogdanm 82:6473597d706e 218 uint8_t SH : 8; //!< [7:0] Secondary Carrier High Time Data Value
bogdanm 82:6473597d706e 219 } B;
bogdanm 82:6473597d706e 220 } hw_cmt_cgh2_t;
bogdanm 82:6473597d706e 221 #endif
bogdanm 82:6473597d706e 222
bogdanm 82:6473597d706e 223 /*!
bogdanm 82:6473597d706e 224 * @name Constants and macros for entire CMT_CGH2 register
bogdanm 82:6473597d706e 225 */
bogdanm 82:6473597d706e 226 //@{
bogdanm 82:6473597d706e 227 #define HW_CMT_CGH2_ADDR (REGS_CMT_BASE + 0x2U)
bogdanm 82:6473597d706e 228
bogdanm 82:6473597d706e 229 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 230 #define HW_CMT_CGH2 (*(__IO hw_cmt_cgh2_t *) HW_CMT_CGH2_ADDR)
bogdanm 82:6473597d706e 231 #define HW_CMT_CGH2_RD() (HW_CMT_CGH2.U)
bogdanm 82:6473597d706e 232 #define HW_CMT_CGH2_WR(v) (HW_CMT_CGH2.U = (v))
bogdanm 82:6473597d706e 233 #define HW_CMT_CGH2_SET(v) (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() | (v)))
bogdanm 82:6473597d706e 234 #define HW_CMT_CGH2_CLR(v) (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() & ~(v)))
bogdanm 82:6473597d706e 235 #define HW_CMT_CGH2_TOG(v) (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() ^ (v)))
bogdanm 82:6473597d706e 236 #endif
bogdanm 82:6473597d706e 237 //@}
bogdanm 82:6473597d706e 238
bogdanm 82:6473597d706e 239 /*
bogdanm 82:6473597d706e 240 * Constants & macros for individual CMT_CGH2 bitfields
bogdanm 82:6473597d706e 241 */
bogdanm 82:6473597d706e 242
bogdanm 82:6473597d706e 243 /*!
bogdanm 82:6473597d706e 244 * @name Register CMT_CGH2, field SH[7:0] (RW)
bogdanm 82:6473597d706e 245 *
bogdanm 82:6473597d706e 246 * Contains the number of input clocks required to generate the carrier high
bogdanm 82:6473597d706e 247 * time period. When operating in Time mode, this register is never selected. When
bogdanm 82:6473597d706e 248 * operating in FSK mode, this register and the primary register pair are
bogdanm 82:6473597d706e 249 * alternately selected under control of the modulator. The secondary carrier high time
bogdanm 82:6473597d706e 250 * value is undefined out of reset. This register must be written to nonzero
bogdanm 82:6473597d706e 251 * values before the carrier generator is enabled when operating in FSK mode.
bogdanm 82:6473597d706e 252 */
bogdanm 82:6473597d706e 253 //@{
bogdanm 82:6473597d706e 254 #define BP_CMT_CGH2_SH (0U) //!< Bit position for CMT_CGH2_SH.
bogdanm 82:6473597d706e 255 #define BM_CMT_CGH2_SH (0xFFU) //!< Bit mask for CMT_CGH2_SH.
bogdanm 82:6473597d706e 256 #define BS_CMT_CGH2_SH (8U) //!< Bit field size in bits for CMT_CGH2_SH.
bogdanm 82:6473597d706e 257
bogdanm 82:6473597d706e 258 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 259 //! @brief Read current value of the CMT_CGH2_SH field.
bogdanm 82:6473597d706e 260 #define BR_CMT_CGH2_SH (HW_CMT_CGH2.U)
bogdanm 82:6473597d706e 261 #endif
bogdanm 82:6473597d706e 262
bogdanm 82:6473597d706e 263 //! @brief Format value for bitfield CMT_CGH2_SH.
bogdanm 82:6473597d706e 264 #define BF_CMT_CGH2_SH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGH2_SH), uint8_t) & BM_CMT_CGH2_SH)
bogdanm 82:6473597d706e 265
bogdanm 82:6473597d706e 266 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 267 //! @brief Set the SH field to a new value.
bogdanm 82:6473597d706e 268 #define BW_CMT_CGH2_SH(v) (HW_CMT_CGH2_WR(v))
bogdanm 82:6473597d706e 269 #endif
bogdanm 82:6473597d706e 270 //@}
bogdanm 82:6473597d706e 271
bogdanm 82:6473597d706e 272 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 273 // HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
bogdanm 82:6473597d706e 274 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 275
bogdanm 82:6473597d706e 276 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 277 /*!
bogdanm 82:6473597d706e 278 * @brief HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
bogdanm 82:6473597d706e 279 *
bogdanm 82:6473597d706e 280 * Reset value: 0x00U
bogdanm 82:6473597d706e 281 *
bogdanm 82:6473597d706e 282 * This data register contains the secondary low value for generating the
bogdanm 82:6473597d706e 283 * carrier output.
bogdanm 82:6473597d706e 284 */
bogdanm 82:6473597d706e 285 typedef union _hw_cmt_cgl2
bogdanm 82:6473597d706e 286 {
bogdanm 82:6473597d706e 287 uint8_t U;
bogdanm 82:6473597d706e 288 struct _hw_cmt_cgl2_bitfields
bogdanm 82:6473597d706e 289 {
bogdanm 82:6473597d706e 290 uint8_t SL : 8; //!< [7:0] Secondary Carrier Low Time Data Value
bogdanm 82:6473597d706e 291 } B;
bogdanm 82:6473597d706e 292 } hw_cmt_cgl2_t;
bogdanm 82:6473597d706e 293 #endif
bogdanm 82:6473597d706e 294
bogdanm 82:6473597d706e 295 /*!
bogdanm 82:6473597d706e 296 * @name Constants and macros for entire CMT_CGL2 register
bogdanm 82:6473597d706e 297 */
bogdanm 82:6473597d706e 298 //@{
bogdanm 82:6473597d706e 299 #define HW_CMT_CGL2_ADDR (REGS_CMT_BASE + 0x3U)
bogdanm 82:6473597d706e 300
bogdanm 82:6473597d706e 301 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 302 #define HW_CMT_CGL2 (*(__IO hw_cmt_cgl2_t *) HW_CMT_CGL2_ADDR)
bogdanm 82:6473597d706e 303 #define HW_CMT_CGL2_RD() (HW_CMT_CGL2.U)
bogdanm 82:6473597d706e 304 #define HW_CMT_CGL2_WR(v) (HW_CMT_CGL2.U = (v))
bogdanm 82:6473597d706e 305 #define HW_CMT_CGL2_SET(v) (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() | (v)))
bogdanm 82:6473597d706e 306 #define HW_CMT_CGL2_CLR(v) (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() & ~(v)))
bogdanm 82:6473597d706e 307 #define HW_CMT_CGL2_TOG(v) (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() ^ (v)))
bogdanm 82:6473597d706e 308 #endif
bogdanm 82:6473597d706e 309 //@}
bogdanm 82:6473597d706e 310
bogdanm 82:6473597d706e 311 /*
bogdanm 82:6473597d706e 312 * Constants & macros for individual CMT_CGL2 bitfields
bogdanm 82:6473597d706e 313 */
bogdanm 82:6473597d706e 314
bogdanm 82:6473597d706e 315 /*!
bogdanm 82:6473597d706e 316 * @name Register CMT_CGL2, field SL[7:0] (RW)
bogdanm 82:6473597d706e 317 *
bogdanm 82:6473597d706e 318 * Contains the number of input clocks required to generate the carrier low time
bogdanm 82:6473597d706e 319 * period. When operating in Time mode, this register is never selected. When
bogdanm 82:6473597d706e 320 * operating in FSK mode, this register and the primary register pair are
bogdanm 82:6473597d706e 321 * alternately selected under the control of the modulator. The secondary carrier low time
bogdanm 82:6473597d706e 322 * value is undefined out of reset. This register must be written to nonzero
bogdanm 82:6473597d706e 323 * values before the carrier generator is enabled when operating in FSK mode.
bogdanm 82:6473597d706e 324 */
bogdanm 82:6473597d706e 325 //@{
bogdanm 82:6473597d706e 326 #define BP_CMT_CGL2_SL (0U) //!< Bit position for CMT_CGL2_SL.
bogdanm 82:6473597d706e 327 #define BM_CMT_CGL2_SL (0xFFU) //!< Bit mask for CMT_CGL2_SL.
bogdanm 82:6473597d706e 328 #define BS_CMT_CGL2_SL (8U) //!< Bit field size in bits for CMT_CGL2_SL.
bogdanm 82:6473597d706e 329
bogdanm 82:6473597d706e 330 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 331 //! @brief Read current value of the CMT_CGL2_SL field.
bogdanm 82:6473597d706e 332 #define BR_CMT_CGL2_SL (HW_CMT_CGL2.U)
bogdanm 82:6473597d706e 333 #endif
bogdanm 82:6473597d706e 334
bogdanm 82:6473597d706e 335 //! @brief Format value for bitfield CMT_CGL2_SL.
bogdanm 82:6473597d706e 336 #define BF_CMT_CGL2_SL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGL2_SL), uint8_t) & BM_CMT_CGL2_SL)
bogdanm 82:6473597d706e 337
bogdanm 82:6473597d706e 338 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 339 //! @brief Set the SL field to a new value.
bogdanm 82:6473597d706e 340 #define BW_CMT_CGL2_SL(v) (HW_CMT_CGL2_WR(v))
bogdanm 82:6473597d706e 341 #endif
bogdanm 82:6473597d706e 342 //@}
bogdanm 82:6473597d706e 343
bogdanm 82:6473597d706e 344 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 345 // HW_CMT_OC - CMT Output Control Register
bogdanm 82:6473597d706e 346 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 347
bogdanm 82:6473597d706e 348 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 349 /*!
bogdanm 82:6473597d706e 350 * @brief HW_CMT_OC - CMT Output Control Register (RW)
bogdanm 82:6473597d706e 351 *
bogdanm 82:6473597d706e 352 * Reset value: 0x00U
bogdanm 82:6473597d706e 353 *
bogdanm 82:6473597d706e 354 * This register is used to control the IRO signal of the CMT module.
bogdanm 82:6473597d706e 355 */
bogdanm 82:6473597d706e 356 typedef union _hw_cmt_oc
bogdanm 82:6473597d706e 357 {
bogdanm 82:6473597d706e 358 uint8_t U;
bogdanm 82:6473597d706e 359 struct _hw_cmt_oc_bitfields
bogdanm 82:6473597d706e 360 {
bogdanm 82:6473597d706e 361 uint8_t RESERVED0 : 5; //!< [4:0]
bogdanm 82:6473597d706e 362 uint8_t IROPEN : 1; //!< [5] IRO Pin Enable
bogdanm 82:6473597d706e 363 uint8_t CMTPOL : 1; //!< [6] CMT Output Polarity
bogdanm 82:6473597d706e 364 uint8_t IROL : 1; //!< [7] IRO Latch Control
bogdanm 82:6473597d706e 365 } B;
bogdanm 82:6473597d706e 366 } hw_cmt_oc_t;
bogdanm 82:6473597d706e 367 #endif
bogdanm 82:6473597d706e 368
bogdanm 82:6473597d706e 369 /*!
bogdanm 82:6473597d706e 370 * @name Constants and macros for entire CMT_OC register
bogdanm 82:6473597d706e 371 */
bogdanm 82:6473597d706e 372 //@{
bogdanm 82:6473597d706e 373 #define HW_CMT_OC_ADDR (REGS_CMT_BASE + 0x4U)
bogdanm 82:6473597d706e 374
bogdanm 82:6473597d706e 375 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 376 #define HW_CMT_OC (*(__IO hw_cmt_oc_t *) HW_CMT_OC_ADDR)
bogdanm 82:6473597d706e 377 #define HW_CMT_OC_RD() (HW_CMT_OC.U)
bogdanm 82:6473597d706e 378 #define HW_CMT_OC_WR(v) (HW_CMT_OC.U = (v))
bogdanm 82:6473597d706e 379 #define HW_CMT_OC_SET(v) (HW_CMT_OC_WR(HW_CMT_OC_RD() | (v)))
bogdanm 82:6473597d706e 380 #define HW_CMT_OC_CLR(v) (HW_CMT_OC_WR(HW_CMT_OC_RD() & ~(v)))
bogdanm 82:6473597d706e 381 #define HW_CMT_OC_TOG(v) (HW_CMT_OC_WR(HW_CMT_OC_RD() ^ (v)))
bogdanm 82:6473597d706e 382 #endif
bogdanm 82:6473597d706e 383 //@}
bogdanm 82:6473597d706e 384
bogdanm 82:6473597d706e 385 /*
bogdanm 82:6473597d706e 386 * Constants & macros for individual CMT_OC bitfields
bogdanm 82:6473597d706e 387 */
bogdanm 82:6473597d706e 388
bogdanm 82:6473597d706e 389 /*!
bogdanm 82:6473597d706e 390 * @name Register CMT_OC, field IROPEN[5] (RW)
bogdanm 82:6473597d706e 391 *
bogdanm 82:6473597d706e 392 * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
bogdanm 82:6473597d706e 393 * output that drives out either the CMT transmitter output or the state of IROL
bogdanm 82:6473597d706e 394 * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
bogdanm 82:6473597d706e 395 * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
bogdanm 82:6473597d706e 396 * signal is disabled, it is in a high-impedance state and is unable to draw any
bogdanm 82:6473597d706e 397 * current. This signal is disabled during reset.
bogdanm 82:6473597d706e 398 *
bogdanm 82:6473597d706e 399 * Values:
bogdanm 82:6473597d706e 400 * - 0 - The IRO signal is disabled.
bogdanm 82:6473597d706e 401 * - 1 - The IRO signal is enabled as output.
bogdanm 82:6473597d706e 402 */
bogdanm 82:6473597d706e 403 //@{
bogdanm 82:6473597d706e 404 #define BP_CMT_OC_IROPEN (5U) //!< Bit position for CMT_OC_IROPEN.
bogdanm 82:6473597d706e 405 #define BM_CMT_OC_IROPEN (0x20U) //!< Bit mask for CMT_OC_IROPEN.
bogdanm 82:6473597d706e 406 #define BS_CMT_OC_IROPEN (1U) //!< Bit field size in bits for CMT_OC_IROPEN.
bogdanm 82:6473597d706e 407
bogdanm 82:6473597d706e 408 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 409 //! @brief Read current value of the CMT_OC_IROPEN field.
bogdanm 82:6473597d706e 410 #define BR_CMT_OC_IROPEN (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROPEN))
bogdanm 82:6473597d706e 411 #endif
bogdanm 82:6473597d706e 412
bogdanm 82:6473597d706e 413 //! @brief Format value for bitfield CMT_OC_IROPEN.
bogdanm 82:6473597d706e 414 #define BF_CMT_OC_IROPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_IROPEN), uint8_t) & BM_CMT_OC_IROPEN)
bogdanm 82:6473597d706e 415
bogdanm 82:6473597d706e 416 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 417 //! @brief Set the IROPEN field to a new value.
bogdanm 82:6473597d706e 418 #define BW_CMT_OC_IROPEN(v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROPEN) = (v))
bogdanm 82:6473597d706e 419 #endif
bogdanm 82:6473597d706e 420 //@}
bogdanm 82:6473597d706e 421
bogdanm 82:6473597d706e 422 /*!
bogdanm 82:6473597d706e 423 * @name Register CMT_OC, field CMTPOL[6] (RW)
bogdanm 82:6473597d706e 424 *
bogdanm 82:6473597d706e 425 * Controls the polarity of the IRO signal.
bogdanm 82:6473597d706e 426 *
bogdanm 82:6473597d706e 427 * Values:
bogdanm 82:6473597d706e 428 * - 0 - The IRO signal is active-low.
bogdanm 82:6473597d706e 429 * - 1 - The IRO signal is active-high.
bogdanm 82:6473597d706e 430 */
bogdanm 82:6473597d706e 431 //@{
bogdanm 82:6473597d706e 432 #define BP_CMT_OC_CMTPOL (6U) //!< Bit position for CMT_OC_CMTPOL.
bogdanm 82:6473597d706e 433 #define BM_CMT_OC_CMTPOL (0x40U) //!< Bit mask for CMT_OC_CMTPOL.
bogdanm 82:6473597d706e 434 #define BS_CMT_OC_CMTPOL (1U) //!< Bit field size in bits for CMT_OC_CMTPOL.
bogdanm 82:6473597d706e 435
bogdanm 82:6473597d706e 436 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 437 //! @brief Read current value of the CMT_OC_CMTPOL field.
bogdanm 82:6473597d706e 438 #define BR_CMT_OC_CMTPOL (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_CMTPOL))
bogdanm 82:6473597d706e 439 #endif
bogdanm 82:6473597d706e 440
bogdanm 82:6473597d706e 441 //! @brief Format value for bitfield CMT_OC_CMTPOL.
bogdanm 82:6473597d706e 442 #define BF_CMT_OC_CMTPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_CMTPOL), uint8_t) & BM_CMT_OC_CMTPOL)
bogdanm 82:6473597d706e 443
bogdanm 82:6473597d706e 444 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 445 //! @brief Set the CMTPOL field to a new value.
bogdanm 82:6473597d706e 446 #define BW_CMT_OC_CMTPOL(v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_CMTPOL) = (v))
bogdanm 82:6473597d706e 447 #endif
bogdanm 82:6473597d706e 448 //@}
bogdanm 82:6473597d706e 449
bogdanm 82:6473597d706e 450 /*!
bogdanm 82:6473597d706e 451 * @name Register CMT_OC, field IROL[7] (RW)
bogdanm 82:6473597d706e 452 *
bogdanm 82:6473597d706e 453 * Reads the state of the IRO latch. Writing to IROL changes the state of the
bogdanm 82:6473597d706e 454 * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
bogdanm 82:6473597d706e 455 */
bogdanm 82:6473597d706e 456 //@{
bogdanm 82:6473597d706e 457 #define BP_CMT_OC_IROL (7U) //!< Bit position for CMT_OC_IROL.
bogdanm 82:6473597d706e 458 #define BM_CMT_OC_IROL (0x80U) //!< Bit mask for CMT_OC_IROL.
bogdanm 82:6473597d706e 459 #define BS_CMT_OC_IROL (1U) //!< Bit field size in bits for CMT_OC_IROL.
bogdanm 82:6473597d706e 460
bogdanm 82:6473597d706e 461 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 462 //! @brief Read current value of the CMT_OC_IROL field.
bogdanm 82:6473597d706e 463 #define BR_CMT_OC_IROL (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROL))
bogdanm 82:6473597d706e 464 #endif
bogdanm 82:6473597d706e 465
bogdanm 82:6473597d706e 466 //! @brief Format value for bitfield CMT_OC_IROL.
bogdanm 82:6473597d706e 467 #define BF_CMT_OC_IROL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_IROL), uint8_t) & BM_CMT_OC_IROL)
bogdanm 82:6473597d706e 468
bogdanm 82:6473597d706e 469 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 470 //! @brief Set the IROL field to a new value.
bogdanm 82:6473597d706e 471 #define BW_CMT_OC_IROL(v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROL) = (v))
bogdanm 82:6473597d706e 472 #endif
bogdanm 82:6473597d706e 473 //@}
bogdanm 82:6473597d706e 474
bogdanm 82:6473597d706e 475 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 476 // HW_CMT_MSC - CMT Modulator Status and Control Register
bogdanm 82:6473597d706e 477 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 478
bogdanm 82:6473597d706e 479 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 480 /*!
bogdanm 82:6473597d706e 481 * @brief HW_CMT_MSC - CMT Modulator Status and Control Register (RW)
bogdanm 82:6473597d706e 482 *
bogdanm 82:6473597d706e 483 * Reset value: 0x00U
bogdanm 82:6473597d706e 484 *
bogdanm 82:6473597d706e 485 * This register contains the modulator and carrier generator enable (MCGEN),
bogdanm 82:6473597d706e 486 * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
bogdanm 82:6473597d706e 487 * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
bogdanm 82:6473597d706e 488 * (EOCF) status bit.
bogdanm 82:6473597d706e 489 */
bogdanm 82:6473597d706e 490 typedef union _hw_cmt_msc
bogdanm 82:6473597d706e 491 {
bogdanm 82:6473597d706e 492 uint8_t U;
bogdanm 82:6473597d706e 493 struct _hw_cmt_msc_bitfields
bogdanm 82:6473597d706e 494 {
bogdanm 82:6473597d706e 495 uint8_t MCGEN : 1; //!< [0] Modulator and Carrier Generator Enable
bogdanm 82:6473597d706e 496 uint8_t EOCIE : 1; //!< [1] End of Cycle Interrupt Enable
bogdanm 82:6473597d706e 497 uint8_t FSK : 1; //!< [2] FSK Mode Select
bogdanm 82:6473597d706e 498 uint8_t BASE : 1; //!< [3] Baseband Enable
bogdanm 82:6473597d706e 499 uint8_t EXSPC : 1; //!< [4] Extended Space Enable
bogdanm 82:6473597d706e 500 uint8_t CMTDIV : 2; //!< [6:5] CMT Clock Divide Prescaler
bogdanm 82:6473597d706e 501 uint8_t EOCF : 1; //!< [7] End Of Cycle Status Flag
bogdanm 82:6473597d706e 502 } B;
bogdanm 82:6473597d706e 503 } hw_cmt_msc_t;
bogdanm 82:6473597d706e 504 #endif
bogdanm 82:6473597d706e 505
bogdanm 82:6473597d706e 506 /*!
bogdanm 82:6473597d706e 507 * @name Constants and macros for entire CMT_MSC register
bogdanm 82:6473597d706e 508 */
bogdanm 82:6473597d706e 509 //@{
bogdanm 82:6473597d706e 510 #define HW_CMT_MSC_ADDR (REGS_CMT_BASE + 0x5U)
bogdanm 82:6473597d706e 511
bogdanm 82:6473597d706e 512 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 513 #define HW_CMT_MSC (*(__IO hw_cmt_msc_t *) HW_CMT_MSC_ADDR)
bogdanm 82:6473597d706e 514 #define HW_CMT_MSC_RD() (HW_CMT_MSC.U)
bogdanm 82:6473597d706e 515 #define HW_CMT_MSC_WR(v) (HW_CMT_MSC.U = (v))
bogdanm 82:6473597d706e 516 #define HW_CMT_MSC_SET(v) (HW_CMT_MSC_WR(HW_CMT_MSC_RD() | (v)))
bogdanm 82:6473597d706e 517 #define HW_CMT_MSC_CLR(v) (HW_CMT_MSC_WR(HW_CMT_MSC_RD() & ~(v)))
bogdanm 82:6473597d706e 518 #define HW_CMT_MSC_TOG(v) (HW_CMT_MSC_WR(HW_CMT_MSC_RD() ^ (v)))
bogdanm 82:6473597d706e 519 #endif
bogdanm 82:6473597d706e 520 //@}
bogdanm 82:6473597d706e 521
bogdanm 82:6473597d706e 522 /*
bogdanm 82:6473597d706e 523 * Constants & macros for individual CMT_MSC bitfields
bogdanm 82:6473597d706e 524 */
bogdanm 82:6473597d706e 525
bogdanm 82:6473597d706e 526 /*!
bogdanm 82:6473597d706e 527 * @name Register CMT_MSC, field MCGEN[0] (RW)
bogdanm 82:6473597d706e 528 *
bogdanm 82:6473597d706e 529 * Setting MCGEN will initialize the carrier generator and modulator and will
bogdanm 82:6473597d706e 530 * enable all clocks. When enabled, the carrier generator and modulator will
bogdanm 82:6473597d706e 531 * function continuously. When MCGEN is cleared, the current modulator cycle will be
bogdanm 82:6473597d706e 532 * allowed to expire before all carrier and modulator clocks are disabled to save
bogdanm 82:6473597d706e 533 * power and the modulator output is forced low. To prevent spurious operation,
bogdanm 82:6473597d706e 534 * the user should initialize all data and control registers before enabling the
bogdanm 82:6473597d706e 535 * system.
bogdanm 82:6473597d706e 536 *
bogdanm 82:6473597d706e 537 * Values:
bogdanm 82:6473597d706e 538 * - 0 - Modulator and carrier generator disabled
bogdanm 82:6473597d706e 539 * - 1 - Modulator and carrier generator enabled
bogdanm 82:6473597d706e 540 */
bogdanm 82:6473597d706e 541 //@{
bogdanm 82:6473597d706e 542 #define BP_CMT_MSC_MCGEN (0U) //!< Bit position for CMT_MSC_MCGEN.
bogdanm 82:6473597d706e 543 #define BM_CMT_MSC_MCGEN (0x01U) //!< Bit mask for CMT_MSC_MCGEN.
bogdanm 82:6473597d706e 544 #define BS_CMT_MSC_MCGEN (1U) //!< Bit field size in bits for CMT_MSC_MCGEN.
bogdanm 82:6473597d706e 545
bogdanm 82:6473597d706e 546 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 547 //! @brief Read current value of the CMT_MSC_MCGEN field.
bogdanm 82:6473597d706e 548 #define BR_CMT_MSC_MCGEN (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_MCGEN))
bogdanm 82:6473597d706e 549 #endif
bogdanm 82:6473597d706e 550
bogdanm 82:6473597d706e 551 //! @brief Format value for bitfield CMT_MSC_MCGEN.
bogdanm 82:6473597d706e 552 #define BF_CMT_MSC_MCGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_MCGEN), uint8_t) & BM_CMT_MSC_MCGEN)
bogdanm 82:6473597d706e 553
bogdanm 82:6473597d706e 554 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 555 //! @brief Set the MCGEN field to a new value.
bogdanm 82:6473597d706e 556 #define BW_CMT_MSC_MCGEN(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_MCGEN) = (v))
bogdanm 82:6473597d706e 557 #endif
bogdanm 82:6473597d706e 558 //@}
bogdanm 82:6473597d706e 559
bogdanm 82:6473597d706e 560 /*!
bogdanm 82:6473597d706e 561 * @name Register CMT_MSC, field EOCIE[1] (RW)
bogdanm 82:6473597d706e 562 *
bogdanm 82:6473597d706e 563 * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
bogdanm 82:6473597d706e 564 *
bogdanm 82:6473597d706e 565 * Values:
bogdanm 82:6473597d706e 566 * - 0 - CPU interrupt is disabled.
bogdanm 82:6473597d706e 567 * - 1 - CPU interrupt is enabled.
bogdanm 82:6473597d706e 568 */
bogdanm 82:6473597d706e 569 //@{
bogdanm 82:6473597d706e 570 #define BP_CMT_MSC_EOCIE (1U) //!< Bit position for CMT_MSC_EOCIE.
bogdanm 82:6473597d706e 571 #define BM_CMT_MSC_EOCIE (0x02U) //!< Bit mask for CMT_MSC_EOCIE.
bogdanm 82:6473597d706e 572 #define BS_CMT_MSC_EOCIE (1U) //!< Bit field size in bits for CMT_MSC_EOCIE.
bogdanm 82:6473597d706e 573
bogdanm 82:6473597d706e 574 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 575 //! @brief Read current value of the CMT_MSC_EOCIE field.
bogdanm 82:6473597d706e 576 #define BR_CMT_MSC_EOCIE (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCIE))
bogdanm 82:6473597d706e 577 #endif
bogdanm 82:6473597d706e 578
bogdanm 82:6473597d706e 579 //! @brief Format value for bitfield CMT_MSC_EOCIE.
bogdanm 82:6473597d706e 580 #define BF_CMT_MSC_EOCIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_EOCIE), uint8_t) & BM_CMT_MSC_EOCIE)
bogdanm 82:6473597d706e 581
bogdanm 82:6473597d706e 582 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 583 //! @brief Set the EOCIE field to a new value.
bogdanm 82:6473597d706e 584 #define BW_CMT_MSC_EOCIE(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCIE) = (v))
bogdanm 82:6473597d706e 585 #endif
bogdanm 82:6473597d706e 586 //@}
bogdanm 82:6473597d706e 587
bogdanm 82:6473597d706e 588 /*!
bogdanm 82:6473597d706e 589 * @name Register CMT_MSC, field FSK[2] (RW)
bogdanm 82:6473597d706e 590 *
bogdanm 82:6473597d706e 591 * Enables FSK operation.
bogdanm 82:6473597d706e 592 *
bogdanm 82:6473597d706e 593 * Values:
bogdanm 82:6473597d706e 594 * - 0 - The CMT operates in Time or Baseband mode.
bogdanm 82:6473597d706e 595 * - 1 - The CMT operates in FSK mode.
bogdanm 82:6473597d706e 596 */
bogdanm 82:6473597d706e 597 //@{
bogdanm 82:6473597d706e 598 #define BP_CMT_MSC_FSK (2U) //!< Bit position for CMT_MSC_FSK.
bogdanm 82:6473597d706e 599 #define BM_CMT_MSC_FSK (0x04U) //!< Bit mask for CMT_MSC_FSK.
bogdanm 82:6473597d706e 600 #define BS_CMT_MSC_FSK (1U) //!< Bit field size in bits for CMT_MSC_FSK.
bogdanm 82:6473597d706e 601
bogdanm 82:6473597d706e 602 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 603 //! @brief Read current value of the CMT_MSC_FSK field.
bogdanm 82:6473597d706e 604 #define BR_CMT_MSC_FSK (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_FSK))
bogdanm 82:6473597d706e 605 #endif
bogdanm 82:6473597d706e 606
bogdanm 82:6473597d706e 607 //! @brief Format value for bitfield CMT_MSC_FSK.
bogdanm 82:6473597d706e 608 #define BF_CMT_MSC_FSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_FSK), uint8_t) & BM_CMT_MSC_FSK)
bogdanm 82:6473597d706e 609
bogdanm 82:6473597d706e 610 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 611 //! @brief Set the FSK field to a new value.
bogdanm 82:6473597d706e 612 #define BW_CMT_MSC_FSK(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_FSK) = (v))
bogdanm 82:6473597d706e 613 #endif
bogdanm 82:6473597d706e 614 //@}
bogdanm 82:6473597d706e 615
bogdanm 82:6473597d706e 616 /*!
bogdanm 82:6473597d706e 617 * @name Register CMT_MSC, field BASE[3] (RW)
bogdanm 82:6473597d706e 618 *
bogdanm 82:6473597d706e 619 * When set, BASE disables the carrier generator and forces the carrier output
bogdanm 82:6473597d706e 620 * high for generation of baseband protocols. When BASE is cleared, the carrier
bogdanm 82:6473597d706e 621 * generator is enabled and the carrier output toggles at the frequency determined
bogdanm 82:6473597d706e 622 * by values stored in the carrier data registers. This field is cleared by
bogdanm 82:6473597d706e 623 * reset. This field is not double-buffered and must not be written to during a
bogdanm 82:6473597d706e 624 * transmission.
bogdanm 82:6473597d706e 625 *
bogdanm 82:6473597d706e 626 * Values:
bogdanm 82:6473597d706e 627 * - 0 - Baseband mode is disabled.
bogdanm 82:6473597d706e 628 * - 1 - Baseband mode is enabled.
bogdanm 82:6473597d706e 629 */
bogdanm 82:6473597d706e 630 //@{
bogdanm 82:6473597d706e 631 #define BP_CMT_MSC_BASE (3U) //!< Bit position for CMT_MSC_BASE.
bogdanm 82:6473597d706e 632 #define BM_CMT_MSC_BASE (0x08U) //!< Bit mask for CMT_MSC_BASE.
bogdanm 82:6473597d706e 633 #define BS_CMT_MSC_BASE (1U) //!< Bit field size in bits for CMT_MSC_BASE.
bogdanm 82:6473597d706e 634
bogdanm 82:6473597d706e 635 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 636 //! @brief Read current value of the CMT_MSC_BASE field.
bogdanm 82:6473597d706e 637 #define BR_CMT_MSC_BASE (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_BASE))
bogdanm 82:6473597d706e 638 #endif
bogdanm 82:6473597d706e 639
bogdanm 82:6473597d706e 640 //! @brief Format value for bitfield CMT_MSC_BASE.
bogdanm 82:6473597d706e 641 #define BF_CMT_MSC_BASE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_BASE), uint8_t) & BM_CMT_MSC_BASE)
bogdanm 82:6473597d706e 642
bogdanm 82:6473597d706e 643 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 644 //! @brief Set the BASE field to a new value.
bogdanm 82:6473597d706e 645 #define BW_CMT_MSC_BASE(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_BASE) = (v))
bogdanm 82:6473597d706e 646 #endif
bogdanm 82:6473597d706e 647 //@}
bogdanm 82:6473597d706e 648
bogdanm 82:6473597d706e 649 /*!
bogdanm 82:6473597d706e 650 * @name Register CMT_MSC, field EXSPC[4] (RW)
bogdanm 82:6473597d706e 651 *
bogdanm 82:6473597d706e 652 * Enables the extended space operation.
bogdanm 82:6473597d706e 653 *
bogdanm 82:6473597d706e 654 * Values:
bogdanm 82:6473597d706e 655 * - 0 - Extended space is disabled.
bogdanm 82:6473597d706e 656 * - 1 - Extended space is enabled.
bogdanm 82:6473597d706e 657 */
bogdanm 82:6473597d706e 658 //@{
bogdanm 82:6473597d706e 659 #define BP_CMT_MSC_EXSPC (4U) //!< Bit position for CMT_MSC_EXSPC.
bogdanm 82:6473597d706e 660 #define BM_CMT_MSC_EXSPC (0x10U) //!< Bit mask for CMT_MSC_EXSPC.
bogdanm 82:6473597d706e 661 #define BS_CMT_MSC_EXSPC (1U) //!< Bit field size in bits for CMT_MSC_EXSPC.
bogdanm 82:6473597d706e 662
bogdanm 82:6473597d706e 663 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 664 //! @brief Read current value of the CMT_MSC_EXSPC field.
bogdanm 82:6473597d706e 665 #define BR_CMT_MSC_EXSPC (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EXSPC))
bogdanm 82:6473597d706e 666 #endif
bogdanm 82:6473597d706e 667
bogdanm 82:6473597d706e 668 //! @brief Format value for bitfield CMT_MSC_EXSPC.
bogdanm 82:6473597d706e 669 #define BF_CMT_MSC_EXSPC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_EXSPC), uint8_t) & BM_CMT_MSC_EXSPC)
bogdanm 82:6473597d706e 670
bogdanm 82:6473597d706e 671 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 672 //! @brief Set the EXSPC field to a new value.
bogdanm 82:6473597d706e 673 #define BW_CMT_MSC_EXSPC(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EXSPC) = (v))
bogdanm 82:6473597d706e 674 #endif
bogdanm 82:6473597d706e 675 //@}
bogdanm 82:6473597d706e 676
bogdanm 82:6473597d706e 677 /*!
bogdanm 82:6473597d706e 678 * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
bogdanm 82:6473597d706e 679 *
bogdanm 82:6473597d706e 680 * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
bogdanm 82:6473597d706e 681 * divided by 2 ,4, or 8 . This field must not be changed during a transmission
bogdanm 82:6473597d706e 682 * because it is not double-buffered.
bogdanm 82:6473597d706e 683 *
bogdanm 82:6473597d706e 684 * Values:
bogdanm 82:6473597d706e 685 * - 00 - IF * 1
bogdanm 82:6473597d706e 686 * - 01 - IF * 2
bogdanm 82:6473597d706e 687 * - 10 - IF * 4
bogdanm 82:6473597d706e 688 * - 11 - IF * 8
bogdanm 82:6473597d706e 689 */
bogdanm 82:6473597d706e 690 //@{
bogdanm 82:6473597d706e 691 #define BP_CMT_MSC_CMTDIV (5U) //!< Bit position for CMT_MSC_CMTDIV.
bogdanm 82:6473597d706e 692 #define BM_CMT_MSC_CMTDIV (0x60U) //!< Bit mask for CMT_MSC_CMTDIV.
bogdanm 82:6473597d706e 693 #define BS_CMT_MSC_CMTDIV (2U) //!< Bit field size in bits for CMT_MSC_CMTDIV.
bogdanm 82:6473597d706e 694
bogdanm 82:6473597d706e 695 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 696 //! @brief Read current value of the CMT_MSC_CMTDIV field.
bogdanm 82:6473597d706e 697 #define BR_CMT_MSC_CMTDIV (HW_CMT_MSC.B.CMTDIV)
bogdanm 82:6473597d706e 698 #endif
bogdanm 82:6473597d706e 699
bogdanm 82:6473597d706e 700 //! @brief Format value for bitfield CMT_MSC_CMTDIV.
bogdanm 82:6473597d706e 701 #define BF_CMT_MSC_CMTDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_CMTDIV), uint8_t) & BM_CMT_MSC_CMTDIV)
bogdanm 82:6473597d706e 702
bogdanm 82:6473597d706e 703 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 704 //! @brief Set the CMTDIV field to a new value.
bogdanm 82:6473597d706e 705 #define BW_CMT_MSC_CMTDIV(v) (HW_CMT_MSC_WR((HW_CMT_MSC_RD() & ~BM_CMT_MSC_CMTDIV) | BF_CMT_MSC_CMTDIV(v)))
bogdanm 82:6473597d706e 706 #endif
bogdanm 82:6473597d706e 707 //@}
bogdanm 82:6473597d706e 708
bogdanm 82:6473597d706e 709 /*!
bogdanm 82:6473597d706e 710 * @name Register CMT_MSC, field EOCF[7] (RO)
bogdanm 82:6473597d706e 711 *
bogdanm 82:6473597d706e 712 * Sets when: The modulator is not currently active and MCGEN is set to begin
bogdanm 82:6473597d706e 713 * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
bogdanm 82:6473597d706e 714 * set. This is recognized when a match occurs between the contents of the space
bogdanm 82:6473597d706e 715 * period register and the down counter. At this time, the counter is
bogdanm 82:6473597d706e 716 * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
bogdanm 82:6473597d706e 717 * the space period register is loaded with, possibly new contents of the space
bogdanm 82:6473597d706e 718 * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
bogdanm 82:6473597d706e 719 * access of CMD2 or CMD4, or by the DMA transfer.
bogdanm 82:6473597d706e 720 *
bogdanm 82:6473597d706e 721 * Values:
bogdanm 82:6473597d706e 722 * - 0 - End of modulation cycle has not occured since the flag last cleared.
bogdanm 82:6473597d706e 723 * - 1 - End of modulator cycle has occurred.
bogdanm 82:6473597d706e 724 */
bogdanm 82:6473597d706e 725 //@{
bogdanm 82:6473597d706e 726 #define BP_CMT_MSC_EOCF (7U) //!< Bit position for CMT_MSC_EOCF.
bogdanm 82:6473597d706e 727 #define BM_CMT_MSC_EOCF (0x80U) //!< Bit mask for CMT_MSC_EOCF.
bogdanm 82:6473597d706e 728 #define BS_CMT_MSC_EOCF (1U) //!< Bit field size in bits for CMT_MSC_EOCF.
bogdanm 82:6473597d706e 729
bogdanm 82:6473597d706e 730 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 731 //! @brief Read current value of the CMT_MSC_EOCF field.
bogdanm 82:6473597d706e 732 #define BR_CMT_MSC_EOCF (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCF))
bogdanm 82:6473597d706e 733 #endif
bogdanm 82:6473597d706e 734 //@}
bogdanm 82:6473597d706e 735
bogdanm 82:6473597d706e 736 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 737 // HW_CMT_CMD1 - CMT Modulator Data Register Mark High
bogdanm 82:6473597d706e 738 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 739
bogdanm 82:6473597d706e 740 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 741 /*!
bogdanm 82:6473597d706e 742 * @brief HW_CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
bogdanm 82:6473597d706e 743 *
bogdanm 82:6473597d706e 744 * Reset value: 0x00U
bogdanm 82:6473597d706e 745 *
bogdanm 82:6473597d706e 746 * The contents of this register are transferred to the modulator down counter
bogdanm 82:6473597d706e 747 * upon the completion of a modulation period.
bogdanm 82:6473597d706e 748 */
bogdanm 82:6473597d706e 749 typedef union _hw_cmt_cmd1
bogdanm 82:6473597d706e 750 {
bogdanm 82:6473597d706e 751 uint8_t U;
bogdanm 82:6473597d706e 752 struct _hw_cmt_cmd1_bitfields
bogdanm 82:6473597d706e 753 {
bogdanm 82:6473597d706e 754 uint8_t MB : 8; //!< [7:0]
bogdanm 82:6473597d706e 755 } B;
bogdanm 82:6473597d706e 756 } hw_cmt_cmd1_t;
bogdanm 82:6473597d706e 757 #endif
bogdanm 82:6473597d706e 758
bogdanm 82:6473597d706e 759 /*!
bogdanm 82:6473597d706e 760 * @name Constants and macros for entire CMT_CMD1 register
bogdanm 82:6473597d706e 761 */
bogdanm 82:6473597d706e 762 //@{
bogdanm 82:6473597d706e 763 #define HW_CMT_CMD1_ADDR (REGS_CMT_BASE + 0x6U)
bogdanm 82:6473597d706e 764
bogdanm 82:6473597d706e 765 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 766 #define HW_CMT_CMD1 (*(__IO hw_cmt_cmd1_t *) HW_CMT_CMD1_ADDR)
bogdanm 82:6473597d706e 767 #define HW_CMT_CMD1_RD() (HW_CMT_CMD1.U)
bogdanm 82:6473597d706e 768 #define HW_CMT_CMD1_WR(v) (HW_CMT_CMD1.U = (v))
bogdanm 82:6473597d706e 769 #define HW_CMT_CMD1_SET(v) (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() | (v)))
bogdanm 82:6473597d706e 770 #define HW_CMT_CMD1_CLR(v) (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() & ~(v)))
bogdanm 82:6473597d706e 771 #define HW_CMT_CMD1_TOG(v) (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() ^ (v)))
bogdanm 82:6473597d706e 772 #endif
bogdanm 82:6473597d706e 773 //@}
bogdanm 82:6473597d706e 774
bogdanm 82:6473597d706e 775 /*
bogdanm 82:6473597d706e 776 * Constants & macros for individual CMT_CMD1 bitfields
bogdanm 82:6473597d706e 777 */
bogdanm 82:6473597d706e 778
bogdanm 82:6473597d706e 779 /*!
bogdanm 82:6473597d706e 780 * @name Register CMT_CMD1, field MB[7:0] (RW)
bogdanm 82:6473597d706e 781 *
bogdanm 82:6473597d706e 782 * Controls the upper mark periods of the modulator for all modes.
bogdanm 82:6473597d706e 783 */
bogdanm 82:6473597d706e 784 //@{
bogdanm 82:6473597d706e 785 #define BP_CMT_CMD1_MB (0U) //!< Bit position for CMT_CMD1_MB.
bogdanm 82:6473597d706e 786 #define BM_CMT_CMD1_MB (0xFFU) //!< Bit mask for CMT_CMD1_MB.
bogdanm 82:6473597d706e 787 #define BS_CMT_CMD1_MB (8U) //!< Bit field size in bits for CMT_CMD1_MB.
bogdanm 82:6473597d706e 788
bogdanm 82:6473597d706e 789 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 790 //! @brief Read current value of the CMT_CMD1_MB field.
bogdanm 82:6473597d706e 791 #define BR_CMT_CMD1_MB (HW_CMT_CMD1.U)
bogdanm 82:6473597d706e 792 #endif
bogdanm 82:6473597d706e 793
bogdanm 82:6473597d706e 794 //! @brief Format value for bitfield CMT_CMD1_MB.
bogdanm 82:6473597d706e 795 #define BF_CMT_CMD1_MB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD1_MB), uint8_t) & BM_CMT_CMD1_MB)
bogdanm 82:6473597d706e 796
bogdanm 82:6473597d706e 797 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 798 //! @brief Set the MB field to a new value.
bogdanm 82:6473597d706e 799 #define BW_CMT_CMD1_MB(v) (HW_CMT_CMD1_WR(v))
bogdanm 82:6473597d706e 800 #endif
bogdanm 82:6473597d706e 801 //@}
bogdanm 82:6473597d706e 802
bogdanm 82:6473597d706e 803 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 804 // HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
bogdanm 82:6473597d706e 805 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 806
bogdanm 82:6473597d706e 807 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 808 /*!
bogdanm 82:6473597d706e 809 * @brief HW_CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
bogdanm 82:6473597d706e 810 *
bogdanm 82:6473597d706e 811 * Reset value: 0x00U
bogdanm 82:6473597d706e 812 *
bogdanm 82:6473597d706e 813 * The contents of this register are transferred to the modulator down counter
bogdanm 82:6473597d706e 814 * upon the completion of a modulation period.
bogdanm 82:6473597d706e 815 */
bogdanm 82:6473597d706e 816 typedef union _hw_cmt_cmd2
bogdanm 82:6473597d706e 817 {
bogdanm 82:6473597d706e 818 uint8_t U;
bogdanm 82:6473597d706e 819 struct _hw_cmt_cmd2_bitfields
bogdanm 82:6473597d706e 820 {
bogdanm 82:6473597d706e 821 uint8_t MB : 8; //!< [7:0]
bogdanm 82:6473597d706e 822 } B;
bogdanm 82:6473597d706e 823 } hw_cmt_cmd2_t;
bogdanm 82:6473597d706e 824 #endif
bogdanm 82:6473597d706e 825
bogdanm 82:6473597d706e 826 /*!
bogdanm 82:6473597d706e 827 * @name Constants and macros for entire CMT_CMD2 register
bogdanm 82:6473597d706e 828 */
bogdanm 82:6473597d706e 829 //@{
bogdanm 82:6473597d706e 830 #define HW_CMT_CMD2_ADDR (REGS_CMT_BASE + 0x7U)
bogdanm 82:6473597d706e 831
bogdanm 82:6473597d706e 832 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 833 #define HW_CMT_CMD2 (*(__IO hw_cmt_cmd2_t *) HW_CMT_CMD2_ADDR)
bogdanm 82:6473597d706e 834 #define HW_CMT_CMD2_RD() (HW_CMT_CMD2.U)
bogdanm 82:6473597d706e 835 #define HW_CMT_CMD2_WR(v) (HW_CMT_CMD2.U = (v))
bogdanm 82:6473597d706e 836 #define HW_CMT_CMD2_SET(v) (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() | (v)))
bogdanm 82:6473597d706e 837 #define HW_CMT_CMD2_CLR(v) (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() & ~(v)))
bogdanm 82:6473597d706e 838 #define HW_CMT_CMD2_TOG(v) (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() ^ (v)))
bogdanm 82:6473597d706e 839 #endif
bogdanm 82:6473597d706e 840 //@}
bogdanm 82:6473597d706e 841
bogdanm 82:6473597d706e 842 /*
bogdanm 82:6473597d706e 843 * Constants & macros for individual CMT_CMD2 bitfields
bogdanm 82:6473597d706e 844 */
bogdanm 82:6473597d706e 845
bogdanm 82:6473597d706e 846 /*!
bogdanm 82:6473597d706e 847 * @name Register CMT_CMD2, field MB[7:0] (RW)
bogdanm 82:6473597d706e 848 *
bogdanm 82:6473597d706e 849 * Controls the lower mark periods of the modulator for all modes.
bogdanm 82:6473597d706e 850 */
bogdanm 82:6473597d706e 851 //@{
bogdanm 82:6473597d706e 852 #define BP_CMT_CMD2_MB (0U) //!< Bit position for CMT_CMD2_MB.
bogdanm 82:6473597d706e 853 #define BM_CMT_CMD2_MB (0xFFU) //!< Bit mask for CMT_CMD2_MB.
bogdanm 82:6473597d706e 854 #define BS_CMT_CMD2_MB (8U) //!< Bit field size in bits for CMT_CMD2_MB.
bogdanm 82:6473597d706e 855
bogdanm 82:6473597d706e 856 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 857 //! @brief Read current value of the CMT_CMD2_MB field.
bogdanm 82:6473597d706e 858 #define BR_CMT_CMD2_MB (HW_CMT_CMD2.U)
bogdanm 82:6473597d706e 859 #endif
bogdanm 82:6473597d706e 860
bogdanm 82:6473597d706e 861 //! @brief Format value for bitfield CMT_CMD2_MB.
bogdanm 82:6473597d706e 862 #define BF_CMT_CMD2_MB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD2_MB), uint8_t) & BM_CMT_CMD2_MB)
bogdanm 82:6473597d706e 863
bogdanm 82:6473597d706e 864 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 865 //! @brief Set the MB field to a new value.
bogdanm 82:6473597d706e 866 #define BW_CMT_CMD2_MB(v) (HW_CMT_CMD2_WR(v))
bogdanm 82:6473597d706e 867 #endif
bogdanm 82:6473597d706e 868 //@}
bogdanm 82:6473597d706e 869
bogdanm 82:6473597d706e 870 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 871 // HW_CMT_CMD3 - CMT Modulator Data Register Space High
bogdanm 82:6473597d706e 872 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 873
bogdanm 82:6473597d706e 874 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 875 /*!
bogdanm 82:6473597d706e 876 * @brief HW_CMT_CMD3 - CMT Modulator Data Register Space High (RW)
bogdanm 82:6473597d706e 877 *
bogdanm 82:6473597d706e 878 * Reset value: 0x00U
bogdanm 82:6473597d706e 879 *
bogdanm 82:6473597d706e 880 * The contents of this register are transferred to the space period register
bogdanm 82:6473597d706e 881 * upon the completion of a modulation period.
bogdanm 82:6473597d706e 882 */
bogdanm 82:6473597d706e 883 typedef union _hw_cmt_cmd3
bogdanm 82:6473597d706e 884 {
bogdanm 82:6473597d706e 885 uint8_t U;
bogdanm 82:6473597d706e 886 struct _hw_cmt_cmd3_bitfields
bogdanm 82:6473597d706e 887 {
bogdanm 82:6473597d706e 888 uint8_t SB : 8; //!< [7:0]
bogdanm 82:6473597d706e 889 } B;
bogdanm 82:6473597d706e 890 } hw_cmt_cmd3_t;
bogdanm 82:6473597d706e 891 #endif
bogdanm 82:6473597d706e 892
bogdanm 82:6473597d706e 893 /*!
bogdanm 82:6473597d706e 894 * @name Constants and macros for entire CMT_CMD3 register
bogdanm 82:6473597d706e 895 */
bogdanm 82:6473597d706e 896 //@{
bogdanm 82:6473597d706e 897 #define HW_CMT_CMD3_ADDR (REGS_CMT_BASE + 0x8U)
bogdanm 82:6473597d706e 898
bogdanm 82:6473597d706e 899 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 900 #define HW_CMT_CMD3 (*(__IO hw_cmt_cmd3_t *) HW_CMT_CMD3_ADDR)
bogdanm 82:6473597d706e 901 #define HW_CMT_CMD3_RD() (HW_CMT_CMD3.U)
bogdanm 82:6473597d706e 902 #define HW_CMT_CMD3_WR(v) (HW_CMT_CMD3.U = (v))
bogdanm 82:6473597d706e 903 #define HW_CMT_CMD3_SET(v) (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() | (v)))
bogdanm 82:6473597d706e 904 #define HW_CMT_CMD3_CLR(v) (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() & ~(v)))
bogdanm 82:6473597d706e 905 #define HW_CMT_CMD3_TOG(v) (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() ^ (v)))
bogdanm 82:6473597d706e 906 #endif
bogdanm 82:6473597d706e 907 //@}
bogdanm 82:6473597d706e 908
bogdanm 82:6473597d706e 909 /*
bogdanm 82:6473597d706e 910 * Constants & macros for individual CMT_CMD3 bitfields
bogdanm 82:6473597d706e 911 */
bogdanm 82:6473597d706e 912
bogdanm 82:6473597d706e 913 /*!
bogdanm 82:6473597d706e 914 * @name Register CMT_CMD3, field SB[7:0] (RW)
bogdanm 82:6473597d706e 915 *
bogdanm 82:6473597d706e 916 * Controls the upper space periods of the modulator for all modes.
bogdanm 82:6473597d706e 917 */
bogdanm 82:6473597d706e 918 //@{
bogdanm 82:6473597d706e 919 #define BP_CMT_CMD3_SB (0U) //!< Bit position for CMT_CMD3_SB.
bogdanm 82:6473597d706e 920 #define BM_CMT_CMD3_SB (0xFFU) //!< Bit mask for CMT_CMD3_SB.
bogdanm 82:6473597d706e 921 #define BS_CMT_CMD3_SB (8U) //!< Bit field size in bits for CMT_CMD3_SB.
bogdanm 82:6473597d706e 922
bogdanm 82:6473597d706e 923 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 924 //! @brief Read current value of the CMT_CMD3_SB field.
bogdanm 82:6473597d706e 925 #define BR_CMT_CMD3_SB (HW_CMT_CMD3.U)
bogdanm 82:6473597d706e 926 #endif
bogdanm 82:6473597d706e 927
bogdanm 82:6473597d706e 928 //! @brief Format value for bitfield CMT_CMD3_SB.
bogdanm 82:6473597d706e 929 #define BF_CMT_CMD3_SB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD3_SB), uint8_t) & BM_CMT_CMD3_SB)
bogdanm 82:6473597d706e 930
bogdanm 82:6473597d706e 931 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 932 //! @brief Set the SB field to a new value.
bogdanm 82:6473597d706e 933 #define BW_CMT_CMD3_SB(v) (HW_CMT_CMD3_WR(v))
bogdanm 82:6473597d706e 934 #endif
bogdanm 82:6473597d706e 935 //@}
bogdanm 82:6473597d706e 936
bogdanm 82:6473597d706e 937 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 938 // HW_CMT_CMD4 - CMT Modulator Data Register Space Low
bogdanm 82:6473597d706e 939 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 940
bogdanm 82:6473597d706e 941 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 942 /*!
bogdanm 82:6473597d706e 943 * @brief HW_CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
bogdanm 82:6473597d706e 944 *
bogdanm 82:6473597d706e 945 * Reset value: 0x00U
bogdanm 82:6473597d706e 946 *
bogdanm 82:6473597d706e 947 * The contents of this register are transferred to the space period register
bogdanm 82:6473597d706e 948 * upon the completion of a modulation period.
bogdanm 82:6473597d706e 949 */
bogdanm 82:6473597d706e 950 typedef union _hw_cmt_cmd4
bogdanm 82:6473597d706e 951 {
bogdanm 82:6473597d706e 952 uint8_t U;
bogdanm 82:6473597d706e 953 struct _hw_cmt_cmd4_bitfields
bogdanm 82:6473597d706e 954 {
bogdanm 82:6473597d706e 955 uint8_t SB : 8; //!< [7:0]
bogdanm 82:6473597d706e 956 } B;
bogdanm 82:6473597d706e 957 } hw_cmt_cmd4_t;
bogdanm 82:6473597d706e 958 #endif
bogdanm 82:6473597d706e 959
bogdanm 82:6473597d706e 960 /*!
bogdanm 82:6473597d706e 961 * @name Constants and macros for entire CMT_CMD4 register
bogdanm 82:6473597d706e 962 */
bogdanm 82:6473597d706e 963 //@{
bogdanm 82:6473597d706e 964 #define HW_CMT_CMD4_ADDR (REGS_CMT_BASE + 0x9U)
bogdanm 82:6473597d706e 965
bogdanm 82:6473597d706e 966 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 967 #define HW_CMT_CMD4 (*(__IO hw_cmt_cmd4_t *) HW_CMT_CMD4_ADDR)
bogdanm 82:6473597d706e 968 #define HW_CMT_CMD4_RD() (HW_CMT_CMD4.U)
bogdanm 82:6473597d706e 969 #define HW_CMT_CMD4_WR(v) (HW_CMT_CMD4.U = (v))
bogdanm 82:6473597d706e 970 #define HW_CMT_CMD4_SET(v) (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() | (v)))
bogdanm 82:6473597d706e 971 #define HW_CMT_CMD4_CLR(v) (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() & ~(v)))
bogdanm 82:6473597d706e 972 #define HW_CMT_CMD4_TOG(v) (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() ^ (v)))
bogdanm 82:6473597d706e 973 #endif
bogdanm 82:6473597d706e 974 //@}
bogdanm 82:6473597d706e 975
bogdanm 82:6473597d706e 976 /*
bogdanm 82:6473597d706e 977 * Constants & macros for individual CMT_CMD4 bitfields
bogdanm 82:6473597d706e 978 */
bogdanm 82:6473597d706e 979
bogdanm 82:6473597d706e 980 /*!
bogdanm 82:6473597d706e 981 * @name Register CMT_CMD4, field SB[7:0] (RW)
bogdanm 82:6473597d706e 982 *
bogdanm 82:6473597d706e 983 * Controls the lower space periods of the modulator for all modes.
bogdanm 82:6473597d706e 984 */
bogdanm 82:6473597d706e 985 //@{
bogdanm 82:6473597d706e 986 #define BP_CMT_CMD4_SB (0U) //!< Bit position for CMT_CMD4_SB.
bogdanm 82:6473597d706e 987 #define BM_CMT_CMD4_SB (0xFFU) //!< Bit mask for CMT_CMD4_SB.
bogdanm 82:6473597d706e 988 #define BS_CMT_CMD4_SB (8U) //!< Bit field size in bits for CMT_CMD4_SB.
bogdanm 82:6473597d706e 989
bogdanm 82:6473597d706e 990 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 991 //! @brief Read current value of the CMT_CMD4_SB field.
bogdanm 82:6473597d706e 992 #define BR_CMT_CMD4_SB (HW_CMT_CMD4.U)
bogdanm 82:6473597d706e 993 #endif
bogdanm 82:6473597d706e 994
bogdanm 82:6473597d706e 995 //! @brief Format value for bitfield CMT_CMD4_SB.
bogdanm 82:6473597d706e 996 #define BF_CMT_CMD4_SB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD4_SB), uint8_t) & BM_CMT_CMD4_SB)
bogdanm 82:6473597d706e 997
bogdanm 82:6473597d706e 998 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 999 //! @brief Set the SB field to a new value.
bogdanm 82:6473597d706e 1000 #define BW_CMT_CMD4_SB(v) (HW_CMT_CMD4_WR(v))
bogdanm 82:6473597d706e 1001 #endif
bogdanm 82:6473597d706e 1002 //@}
bogdanm 82:6473597d706e 1003
bogdanm 82:6473597d706e 1004 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1005 // HW_CMT_PPS - CMT Primary Prescaler Register
bogdanm 82:6473597d706e 1006 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1007
bogdanm 82:6473597d706e 1008 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1009 /*!
bogdanm 82:6473597d706e 1010 * @brief HW_CMT_PPS - CMT Primary Prescaler Register (RW)
bogdanm 82:6473597d706e 1011 *
bogdanm 82:6473597d706e 1012 * Reset value: 0x00U
bogdanm 82:6473597d706e 1013 *
bogdanm 82:6473597d706e 1014 * This register is used to set the Primary Prescaler Divider field (PPSDIV).
bogdanm 82:6473597d706e 1015 */
bogdanm 82:6473597d706e 1016 typedef union _hw_cmt_pps
bogdanm 82:6473597d706e 1017 {
bogdanm 82:6473597d706e 1018 uint8_t U;
bogdanm 82:6473597d706e 1019 struct _hw_cmt_pps_bitfields
bogdanm 82:6473597d706e 1020 {
bogdanm 82:6473597d706e 1021 uint8_t PPSDIV : 4; //!< [3:0] Primary Prescaler Divider
bogdanm 82:6473597d706e 1022 uint8_t RESERVED0 : 4; //!< [7:4]
bogdanm 82:6473597d706e 1023 } B;
bogdanm 82:6473597d706e 1024 } hw_cmt_pps_t;
bogdanm 82:6473597d706e 1025 #endif
bogdanm 82:6473597d706e 1026
bogdanm 82:6473597d706e 1027 /*!
bogdanm 82:6473597d706e 1028 * @name Constants and macros for entire CMT_PPS register
bogdanm 82:6473597d706e 1029 */
bogdanm 82:6473597d706e 1030 //@{
bogdanm 82:6473597d706e 1031 #define HW_CMT_PPS_ADDR (REGS_CMT_BASE + 0xAU)
bogdanm 82:6473597d706e 1032
bogdanm 82:6473597d706e 1033 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1034 #define HW_CMT_PPS (*(__IO hw_cmt_pps_t *) HW_CMT_PPS_ADDR)
bogdanm 82:6473597d706e 1035 #define HW_CMT_PPS_RD() (HW_CMT_PPS.U)
bogdanm 82:6473597d706e 1036 #define HW_CMT_PPS_WR(v) (HW_CMT_PPS.U = (v))
bogdanm 82:6473597d706e 1037 #define HW_CMT_PPS_SET(v) (HW_CMT_PPS_WR(HW_CMT_PPS_RD() | (v)))
bogdanm 82:6473597d706e 1038 #define HW_CMT_PPS_CLR(v) (HW_CMT_PPS_WR(HW_CMT_PPS_RD() & ~(v)))
bogdanm 82:6473597d706e 1039 #define HW_CMT_PPS_TOG(v) (HW_CMT_PPS_WR(HW_CMT_PPS_RD() ^ (v)))
bogdanm 82:6473597d706e 1040 #endif
bogdanm 82:6473597d706e 1041 //@}
bogdanm 82:6473597d706e 1042
bogdanm 82:6473597d706e 1043 /*
bogdanm 82:6473597d706e 1044 * Constants & macros for individual CMT_PPS bitfields
bogdanm 82:6473597d706e 1045 */
bogdanm 82:6473597d706e 1046
bogdanm 82:6473597d706e 1047 /*!
bogdanm 82:6473597d706e 1048 * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
bogdanm 82:6473597d706e 1049 *
bogdanm 82:6473597d706e 1050 * Divides the CMT clock to generate the Intermediate Frequency clock enable to
bogdanm 82:6473597d706e 1051 * the secondary prescaler.
bogdanm 82:6473597d706e 1052 *
bogdanm 82:6473597d706e 1053 * Values:
bogdanm 82:6473597d706e 1054 * - 0000 - Bus clock * 1
bogdanm 82:6473597d706e 1055 * - 0001 - Bus clock * 2
bogdanm 82:6473597d706e 1056 * - 0010 - Bus clock * 3
bogdanm 82:6473597d706e 1057 * - 0011 - Bus clock * 4
bogdanm 82:6473597d706e 1058 * - 0100 - Bus clock * 5
bogdanm 82:6473597d706e 1059 * - 0101 - Bus clock * 6
bogdanm 82:6473597d706e 1060 * - 0110 - Bus clock * 7
bogdanm 82:6473597d706e 1061 * - 0111 - Bus clock * 8
bogdanm 82:6473597d706e 1062 * - 1000 - Bus clock * 9
bogdanm 82:6473597d706e 1063 * - 1001 - Bus clock * 10
bogdanm 82:6473597d706e 1064 * - 1010 - Bus clock * 11
bogdanm 82:6473597d706e 1065 * - 1011 - Bus clock * 12
bogdanm 82:6473597d706e 1066 * - 1100 - Bus clock * 13
bogdanm 82:6473597d706e 1067 * - 1101 - Bus clock * 14
bogdanm 82:6473597d706e 1068 * - 1110 - Bus clock * 15
bogdanm 82:6473597d706e 1069 * - 1111 - Bus clock * 16
bogdanm 82:6473597d706e 1070 */
bogdanm 82:6473597d706e 1071 //@{
bogdanm 82:6473597d706e 1072 #define BP_CMT_PPS_PPSDIV (0U) //!< Bit position for CMT_PPS_PPSDIV.
bogdanm 82:6473597d706e 1073 #define BM_CMT_PPS_PPSDIV (0x0FU) //!< Bit mask for CMT_PPS_PPSDIV.
bogdanm 82:6473597d706e 1074 #define BS_CMT_PPS_PPSDIV (4U) //!< Bit field size in bits for CMT_PPS_PPSDIV.
bogdanm 82:6473597d706e 1075
bogdanm 82:6473597d706e 1076 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1077 //! @brief Read current value of the CMT_PPS_PPSDIV field.
bogdanm 82:6473597d706e 1078 #define BR_CMT_PPS_PPSDIV (HW_CMT_PPS.B.PPSDIV)
bogdanm 82:6473597d706e 1079 #endif
bogdanm 82:6473597d706e 1080
bogdanm 82:6473597d706e 1081 //! @brief Format value for bitfield CMT_PPS_PPSDIV.
bogdanm 82:6473597d706e 1082 #define BF_CMT_PPS_PPSDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_PPS_PPSDIV), uint8_t) & BM_CMT_PPS_PPSDIV)
bogdanm 82:6473597d706e 1083
bogdanm 82:6473597d706e 1084 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1085 //! @brief Set the PPSDIV field to a new value.
bogdanm 82:6473597d706e 1086 #define BW_CMT_PPS_PPSDIV(v) (HW_CMT_PPS_WR((HW_CMT_PPS_RD() & ~BM_CMT_PPS_PPSDIV) | BF_CMT_PPS_PPSDIV(v)))
bogdanm 82:6473597d706e 1087 #endif
bogdanm 82:6473597d706e 1088 //@}
bogdanm 82:6473597d706e 1089
bogdanm 82:6473597d706e 1090 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1091 // HW_CMT_DMA - CMT Direct Memory Access Register
bogdanm 82:6473597d706e 1092 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1093
bogdanm 82:6473597d706e 1094 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1095 /*!
bogdanm 82:6473597d706e 1096 * @brief HW_CMT_DMA - CMT Direct Memory Access Register (RW)
bogdanm 82:6473597d706e 1097 *
bogdanm 82:6473597d706e 1098 * Reset value: 0x00U
bogdanm 82:6473597d706e 1099 *
bogdanm 82:6473597d706e 1100 * This register is used to enable/disable direct memory access (DMA).
bogdanm 82:6473597d706e 1101 */
bogdanm 82:6473597d706e 1102 typedef union _hw_cmt_dma
bogdanm 82:6473597d706e 1103 {
bogdanm 82:6473597d706e 1104 uint8_t U;
bogdanm 82:6473597d706e 1105 struct _hw_cmt_dma_bitfields
bogdanm 82:6473597d706e 1106 {
bogdanm 82:6473597d706e 1107 uint8_t DMAb : 1; //!< [0] DMA Enable
bogdanm 82:6473597d706e 1108 uint8_t RESERVED0 : 7; //!< [7:1]
bogdanm 82:6473597d706e 1109 } B;
bogdanm 82:6473597d706e 1110 } hw_cmt_dma_t;
bogdanm 82:6473597d706e 1111 #endif
bogdanm 82:6473597d706e 1112
bogdanm 82:6473597d706e 1113 /*!
bogdanm 82:6473597d706e 1114 * @name Constants and macros for entire CMT_DMA register
bogdanm 82:6473597d706e 1115 */
bogdanm 82:6473597d706e 1116 //@{
bogdanm 82:6473597d706e 1117 #define HW_CMT_DMA_ADDR (REGS_CMT_BASE + 0xBU)
bogdanm 82:6473597d706e 1118
bogdanm 82:6473597d706e 1119 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1120 #define HW_CMT_DMA (*(__IO hw_cmt_dma_t *) HW_CMT_DMA_ADDR)
bogdanm 82:6473597d706e 1121 #define HW_CMT_DMA_RD() (HW_CMT_DMA.U)
bogdanm 82:6473597d706e 1122 #define HW_CMT_DMA_WR(v) (HW_CMT_DMA.U = (v))
bogdanm 82:6473597d706e 1123 #define HW_CMT_DMA_SET(v) (HW_CMT_DMA_WR(HW_CMT_DMA_RD() | (v)))
bogdanm 82:6473597d706e 1124 #define HW_CMT_DMA_CLR(v) (HW_CMT_DMA_WR(HW_CMT_DMA_RD() & ~(v)))
bogdanm 82:6473597d706e 1125 #define HW_CMT_DMA_TOG(v) (HW_CMT_DMA_WR(HW_CMT_DMA_RD() ^ (v)))
bogdanm 82:6473597d706e 1126 #endif
bogdanm 82:6473597d706e 1127 //@}
bogdanm 82:6473597d706e 1128
bogdanm 82:6473597d706e 1129 /*
bogdanm 82:6473597d706e 1130 * Constants & macros for individual CMT_DMA bitfields
bogdanm 82:6473597d706e 1131 */
bogdanm 82:6473597d706e 1132
bogdanm 82:6473597d706e 1133 /*!
bogdanm 82:6473597d706e 1134 * @name Register CMT_DMA, field DMA[0] (RW)
bogdanm 82:6473597d706e 1135 *
bogdanm 82:6473597d706e 1136 * Enables the DMA protocol.
bogdanm 82:6473597d706e 1137 *
bogdanm 82:6473597d706e 1138 * Values:
bogdanm 82:6473597d706e 1139 * - 0 - DMA transfer request and done are disabled.
bogdanm 82:6473597d706e 1140 * - 1 - DMA transfer request and done are enabled.
bogdanm 82:6473597d706e 1141 */
bogdanm 82:6473597d706e 1142 //@{
bogdanm 82:6473597d706e 1143 #define BP_CMT_DMA_DMA (0U) //!< Bit position for CMT_DMA_DMA.
bogdanm 82:6473597d706e 1144 #define BM_CMT_DMA_DMA (0x01U) //!< Bit mask for CMT_DMA_DMA.
bogdanm 82:6473597d706e 1145 #define BS_CMT_DMA_DMA (1U) //!< Bit field size in bits for CMT_DMA_DMA.
bogdanm 82:6473597d706e 1146
bogdanm 82:6473597d706e 1147 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1148 //! @brief Read current value of the CMT_DMA_DMA field.
bogdanm 82:6473597d706e 1149 #define BR_CMT_DMA_DMA (BITBAND_ACCESS8(HW_CMT_DMA_ADDR, BP_CMT_DMA_DMA))
bogdanm 82:6473597d706e 1150 #endif
bogdanm 82:6473597d706e 1151
bogdanm 82:6473597d706e 1152 //! @brief Format value for bitfield CMT_DMA_DMA.
bogdanm 82:6473597d706e 1153 #define BF_CMT_DMA_DMA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_DMA_DMA), uint8_t) & BM_CMT_DMA_DMA)
bogdanm 82:6473597d706e 1154
bogdanm 82:6473597d706e 1155 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1156 //! @brief Set the DMA field to a new value.
bogdanm 82:6473597d706e 1157 #define BW_CMT_DMA_DMA(v) (BITBAND_ACCESS8(HW_CMT_DMA_ADDR, BP_CMT_DMA_DMA) = (v))
bogdanm 82:6473597d706e 1158 #endif
bogdanm 82:6473597d706e 1159 //@}
bogdanm 82:6473597d706e 1160
bogdanm 82:6473597d706e 1161 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1162 // hw_cmt_t - module struct
bogdanm 82:6473597d706e 1163 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1164 /*!
bogdanm 82:6473597d706e 1165 * @brief All CMT module registers.
bogdanm 82:6473597d706e 1166 */
bogdanm 82:6473597d706e 1167 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1168 #pragma pack(1)
bogdanm 82:6473597d706e 1169 typedef struct _hw_cmt
bogdanm 82:6473597d706e 1170 {
bogdanm 82:6473597d706e 1171 __IO hw_cmt_cgh1_t CGH1; //!< [0x0] CMT Carrier Generator High Data Register 1
bogdanm 82:6473597d706e 1172 __IO hw_cmt_cgl1_t CGL1; //!< [0x1] CMT Carrier Generator Low Data Register 1
bogdanm 82:6473597d706e 1173 __IO hw_cmt_cgh2_t CGH2; //!< [0x2] CMT Carrier Generator High Data Register 2
bogdanm 82:6473597d706e 1174 __IO hw_cmt_cgl2_t CGL2; //!< [0x3] CMT Carrier Generator Low Data Register 2
bogdanm 82:6473597d706e 1175 __IO hw_cmt_oc_t OC; //!< [0x4] CMT Output Control Register
bogdanm 82:6473597d706e 1176 __IO hw_cmt_msc_t MSC; //!< [0x5] CMT Modulator Status and Control Register
bogdanm 82:6473597d706e 1177 __IO hw_cmt_cmd1_t CMD1; //!< [0x6] CMT Modulator Data Register Mark High
bogdanm 82:6473597d706e 1178 __IO hw_cmt_cmd2_t CMD2; //!< [0x7] CMT Modulator Data Register Mark Low
bogdanm 82:6473597d706e 1179 __IO hw_cmt_cmd3_t CMD3; //!< [0x8] CMT Modulator Data Register Space High
bogdanm 82:6473597d706e 1180 __IO hw_cmt_cmd4_t CMD4; //!< [0x9] CMT Modulator Data Register Space Low
bogdanm 82:6473597d706e 1181 __IO hw_cmt_pps_t PPS; //!< [0xA] CMT Primary Prescaler Register
bogdanm 82:6473597d706e 1182 __IO hw_cmt_dma_t DMA; //!< [0xB] CMT Direct Memory Access Register
bogdanm 82:6473597d706e 1183 } hw_cmt_t;
bogdanm 82:6473597d706e 1184 #pragma pack()
bogdanm 82:6473597d706e 1185
bogdanm 82:6473597d706e 1186 //! @brief Macro to access all CMT registers.
bogdanm 82:6473597d706e 1187 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 1188 //! use the '&' operator, like <code>&HW_CMT</code>.
bogdanm 82:6473597d706e 1189 #define HW_CMT (*(hw_cmt_t *) REGS_CMT_BASE)
bogdanm 82:6473597d706e 1190 #endif
bogdanm 82:6473597d706e 1191
bogdanm 82:6473597d706e 1192 #endif // __HW_CMT_REGISTERS_H__
bogdanm 82:6473597d706e 1193 // v22/130726/0.9
bogdanm 82:6473597d706e 1194 // EOF