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TARGET_ARCH_MAX/stm32f4xx_ll_sdmmc.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Child:: 92:4fc01daae5a5

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	89:552587b429a1	1	/**
bogdanm	89:552587b429a1	2	******************************************************************************
bogdanm	89:552587b429a1	3	* @file stm32f4xx_ll_sdmmc.h
bogdanm	89:552587b429a1	4	* @author MCD Application Team
bogdanm	89:552587b429a1	5	* @version V1.1.0RC2
bogdanm	89:552587b429a1	6	* @date 14-May-2014
bogdanm	89:552587b429a1	7	* @brief Header file of SDMMC HAL module.
bogdanm	89:552587b429a1	8	******************************************************************************
bogdanm	89:552587b429a1	9	* @attention
bogdanm	89:552587b429a1	10	*
bogdanm	89:552587b429a1	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	89:552587b429a1	12	*
bogdanm	89:552587b429a1	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	89:552587b429a1	14	* are permitted provided that the following conditions are met:
bogdanm	89:552587b429a1	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	89:552587b429a1	16	* this list of conditions and the following disclaimer.
bogdanm	89:552587b429a1	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	89:552587b429a1	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	89:552587b429a1	19	* and/or other materials provided with the distribution.
bogdanm	89:552587b429a1	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	89:552587b429a1	21	* may be used to endorse or promote products derived from this software
bogdanm	89:552587b429a1	22	* without specific prior written permission.
bogdanm	89:552587b429a1	23	*
bogdanm	89:552587b429a1	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	89:552587b429a1	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	89:552587b429a1	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	89:552587b429a1	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	89:552587b429a1	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	89:552587b429a1	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	89:552587b429a1	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	89:552587b429a1	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	89:552587b429a1	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	89:552587b429a1	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	89:552587b429a1	34	*
bogdanm	89:552587b429a1	35	******************************************************************************
bogdanm	89:552587b429a1	36	*/
bogdanm	89:552587b429a1	37
bogdanm	89:552587b429a1	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	89:552587b429a1	39	#ifndef __STM32F4xx_LL_SDMMC_H
bogdanm	89:552587b429a1	40	#define __STM32F4xx_LL_SDMMC_H
bogdanm	89:552587b429a1	41
bogdanm	89:552587b429a1	42	#ifdef __cplusplus
bogdanm	89:552587b429a1	43	extern "C" {
bogdanm	89:552587b429a1	44	#endif
bogdanm	89:552587b429a1	45
bogdanm	89:552587b429a1	46	/* Includes ------------------------------------------------------------------*/
bogdanm	89:552587b429a1	47	#include "stm32f4xx_hal_def.h"
bogdanm	89:552587b429a1	48
bogdanm	89:552587b429a1	49	/** @addtogroup STM32F4xx_Driver
bogdanm	89:552587b429a1	50	* @{
bogdanm	89:552587b429a1	51	*/
bogdanm	89:552587b429a1	52
bogdanm	89:552587b429a1	53	/** @addtogroup SDMMC
bogdanm	89:552587b429a1	54	* @{
bogdanm	89:552587b429a1	55	*/
bogdanm	89:552587b429a1	56
bogdanm	89:552587b429a1	57	/* Exported types ------------------------------------------------------------*/
bogdanm	89:552587b429a1	58
bogdanm	89:552587b429a1	59	/**
bogdanm	89:552587b429a1	60	* @brief SDMMC Configuration Structure definition
bogdanm	89:552587b429a1	61	*/
bogdanm	89:552587b429a1	62	typedef struct
bogdanm	89:552587b429a1	63	{
bogdanm	89:552587b429a1	64	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
bogdanm	89:552587b429a1	65	This parameter can be a value of @ref SDIO_Clock_Edge */
bogdanm	89:552587b429a1	66
bogdanm	89:552587b429a1	67	uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
bogdanm	89:552587b429a1	68	enabled or disabled.
bogdanm	89:552587b429a1	69	This parameter can be a value of @ref SDIO_Clock_Bypass */
bogdanm	89:552587b429a1	70
bogdanm	89:552587b429a1	71	uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
bogdanm	89:552587b429a1	72	disabled when the bus is idle.
bogdanm	89:552587b429a1	73	This parameter can be a value of @ref SDIO_Clock_Power_Save */
bogdanm	89:552587b429a1	74
bogdanm	89:552587b429a1	75	uint32_t BusWide; /*!< Specifies the SDIO bus width.
bogdanm	89:552587b429a1	76	This parameter can be a value of @ref SDIO_Bus_Wide */
bogdanm	89:552587b429a1	77
bogdanm	89:552587b429a1	78	uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
bogdanm	89:552587b429a1	79	This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
bogdanm	89:552587b429a1	80
bogdanm	89:552587b429a1	81	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
bogdanm	89:552587b429a1	82	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	89:552587b429a1	83
bogdanm	89:552587b429a1	84	}SDIO_InitTypeDef;
bogdanm	89:552587b429a1	85
bogdanm	89:552587b429a1	86
bogdanm	89:552587b429a1	87	/**
bogdanm	89:552587b429a1	88	* @brief SDIO Command Control structure
bogdanm	89:552587b429a1	89	*/
bogdanm	89:552587b429a1	90	typedef struct
bogdanm	89:552587b429a1	91	{
bogdanm	89:552587b429a1	92	uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
bogdanm	89:552587b429a1	93	to a card as part of a command message. If a command
bogdanm	89:552587b429a1	94	contains an argument, it must be loaded into this register
bogdanm	89:552587b429a1	95	before writing the command to the command register. */
bogdanm	89:552587b429a1	96
bogdanm	89:552587b429a1	97	uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
bogdanm	89:552587b429a1	98	Max_Data = 64 */
bogdanm	89:552587b429a1	99
bogdanm	89:552587b429a1	100	uint32_t Response; /*!< Specifies the SDIO response type.
bogdanm	89:552587b429a1	101	This parameter can be a value of @ref SDIO_Response_Type */
bogdanm	89:552587b429a1	102
bogdanm	89:552587b429a1	103	uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
bogdanm	89:552587b429a1	104	enabled or disabled.
bogdanm	89:552587b429a1	105	This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
bogdanm	89:552587b429a1	106
bogdanm	89:552587b429a1	107	uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
bogdanm	89:552587b429a1	108	is enabled or disabled.
bogdanm	89:552587b429a1	109	This parameter can be a value of @ref SDIO_CPSM_State */
bogdanm	89:552587b429a1	110	}SDIO_CmdInitTypeDef;
bogdanm	89:552587b429a1	111
bogdanm	89:552587b429a1	112
bogdanm	89:552587b429a1	113	/**
bogdanm	89:552587b429a1	114	* @brief SDIO Data Control structure
bogdanm	89:552587b429a1	115	*/
bogdanm	89:552587b429a1	116	typedef struct
bogdanm	89:552587b429a1	117	{
bogdanm	89:552587b429a1	118	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
bogdanm	89:552587b429a1	119
bogdanm	89:552587b429a1	120	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
bogdanm	89:552587b429a1	121
bogdanm	89:552587b429a1	122	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
bogdanm	89:552587b429a1	123	This parameter can be a value of @ref SDIO_Data_Block_Size */
bogdanm	89:552587b429a1	124
bogdanm	89:552587b429a1	125	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
bogdanm	89:552587b429a1	126	is a read or write.
bogdanm	89:552587b429a1	127	This parameter can be a value of @ref SDIO_Transfer_Direction */
bogdanm	89:552587b429a1	128
bogdanm	89:552587b429a1	129	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
bogdanm	89:552587b429a1	130	This parameter can be a value of @ref SDIO_Transfer_Type */
bogdanm	89:552587b429a1	131
bogdanm	89:552587b429a1	132	uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
bogdanm	89:552587b429a1	133	is enabled or disabled.
bogdanm	89:552587b429a1	134	This parameter can be a value of @ref SDIO_DPSM_State */
bogdanm	89:552587b429a1	135	}SDIO_DataInitTypeDef;
bogdanm	89:552587b429a1	136
bogdanm	89:552587b429a1	137	/* Exported constants --------------------------------------------------------*/
bogdanm	89:552587b429a1	138
bogdanm	89:552587b429a1	139	/** @defgroup SDIO_Exported_Constants
bogdanm	89:552587b429a1	140	* @{
bogdanm	89:552587b429a1	141	*/
bogdanm	89:552587b429a1	142
bogdanm	89:552587b429a1	143	/** @defgroup SDIO_Clock_Edge
bogdanm	89:552587b429a1	144	* @{
bogdanm	89:552587b429a1	145	*/
bogdanm	89:552587b429a1	146	#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	147	#define SDIO_CLOCK_EDGE_FALLING ((uint32_t)0x00002000)
bogdanm	89:552587b429a1	148
bogdanm	89:552587b429a1	149	#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) \|\| \
bogdanm	89:552587b429a1	150	((EDGE) == SDIO_CLOCK_EDGE_FALLING))
bogdanm	89:552587b429a1	151	/**
bogdanm	89:552587b429a1	152	* @}
bogdanm	89:552587b429a1	153	*/
bogdanm	89:552587b429a1	154
bogdanm	89:552587b429a1	155	/** @defgroup SDIO_Clock_Bypass
bogdanm	89:552587b429a1	156	* @{
bogdanm	89:552587b429a1	157	*/
bogdanm	89:552587b429a1	158	#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	159	#define SDIO_CLOCK_BYPASS_ENABLE ((uint32_t)0x00000400)
bogdanm	89:552587b429a1	160
bogdanm	89:552587b429a1	161	#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) \|\| \
bogdanm	89:552587b429a1	162	((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
bogdanm	89:552587b429a1	163	/**
bogdanm	89:552587b429a1	164	* @}
bogdanm	89:552587b429a1	165	*/
bogdanm	89:552587b429a1	166
bogdanm	89:552587b429a1	167	/** @defgroup SDIO_Clock_Power_Save
bogdanm	89:552587b429a1	168	* @{
bogdanm	89:552587b429a1	169	*/
bogdanm	89:552587b429a1	170	#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	171	#define SDIO_CLOCK_POWER_SAVE_ENABLE ((uint32_t)0x00000200)
bogdanm	89:552587b429a1	172
bogdanm	89:552587b429a1	173	#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) \|\| \
bogdanm	89:552587b429a1	174	((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
bogdanm	89:552587b429a1	175	/**
bogdanm	89:552587b429a1	176	* @}
bogdanm	89:552587b429a1	177	*/
bogdanm	89:552587b429a1	178
bogdanm	89:552587b429a1	179	/** @defgroup SDIO_Bus_Wide
bogdanm	89:552587b429a1	180	* @{
bogdanm	89:552587b429a1	181	*/
bogdanm	89:552587b429a1	182	#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	183	#define SDIO_BUS_WIDE_4B ((uint32_t)0x00000800)
bogdanm	89:552587b429a1	184	#define SDIO_BUS_WIDE_8B ((uint32_t)0x00001000)
bogdanm	89:552587b429a1	185
bogdanm	89:552587b429a1	186	#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) \|\| \
bogdanm	89:552587b429a1	187	((WIDE) == SDIO_BUS_WIDE_4B) \|\| \
bogdanm	89:552587b429a1	188	((WIDE) == SDIO_BUS_WIDE_8B))
bogdanm	89:552587b429a1	189	/**
bogdanm	89:552587b429a1	190	* @}
bogdanm	89:552587b429a1	191	*/
bogdanm	89:552587b429a1	192
bogdanm	89:552587b429a1	193	/** @defgroup SDIO_Hardware_Flow_Control
bogdanm	89:552587b429a1	194	* @{
bogdanm	89:552587b429a1	195	*/
bogdanm	89:552587b429a1	196	#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	197	#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE ((uint32_t)0x00004000)
bogdanm	89:552587b429a1	198
bogdanm	89:552587b429a1	199	#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
bogdanm	89:552587b429a1	200	((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
bogdanm	89:552587b429a1	201	/**
bogdanm	89:552587b429a1	202	* @}
bogdanm	89:552587b429a1	203	*/
bogdanm	89:552587b429a1	204
bogdanm	89:552587b429a1	205	/** @defgroup SDIO_Clock_Division
bogdanm	89:552587b429a1	206	* @{
bogdanm	89:552587b429a1	207	*/
bogdanm	89:552587b429a1	208	#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
bogdanm	89:552587b429a1	209	/**
bogdanm	89:552587b429a1	210	* @}
bogdanm	89:552587b429a1	211	*/
bogdanm	89:552587b429a1	212
bogdanm	89:552587b429a1	213	/**
bogdanm	89:552587b429a1	214	* @}
bogdanm	89:552587b429a1	215	*/
bogdanm	89:552587b429a1	216
bogdanm	89:552587b429a1	217	/** @defgroup SDIO_Command_Index
bogdanm	89:552587b429a1	218	* @{
bogdanm	89:552587b429a1	219	*/
bogdanm	89:552587b429a1	220	#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
bogdanm	89:552587b429a1	221	/**
bogdanm	89:552587b429a1	222	* @}
bogdanm	89:552587b429a1	223	*/
bogdanm	89:552587b429a1	224
bogdanm	89:552587b429a1	225	/** @defgroup SDIO_Response_Type
bogdanm	89:552587b429a1	226	* @{
bogdanm	89:552587b429a1	227	*/
bogdanm	89:552587b429a1	228	#define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	229	#define SDIO_RESPONSE_SHORT ((uint32_t)0x00000040)
bogdanm	89:552587b429a1	230	#define SDIO_RESPONSE_LONG ((uint32_t)0x000000C0)
bogdanm	89:552587b429a1	231
bogdanm	89:552587b429a1	232	#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) \|\| \
bogdanm	89:552587b429a1	233	((RESPONSE) == SDIO_RESPONSE_SHORT) \|\| \
bogdanm	89:552587b429a1	234	((RESPONSE) == SDIO_RESPONSE_LONG))
bogdanm	89:552587b429a1	235	/**
bogdanm	89:552587b429a1	236	* @}
bogdanm	89:552587b429a1	237	*/
bogdanm	89:552587b429a1	238
bogdanm	89:552587b429a1	239	/** @defgroup SDIO_Wait_Interrupt_State
bogdanm	89:552587b429a1	240	* @{
bogdanm	89:552587b429a1	241	*/
bogdanm	89:552587b429a1	242	#define SDIO_WAIT_NO ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	243	#define SDIO_WAIT_IT ((uint32_t)0x00000100)
bogdanm	89:552587b429a1	244	#define SDIO_WAIT_PEND ((uint32_t)0x00000200)
bogdanm	89:552587b429a1	245
bogdanm	89:552587b429a1	246	#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) \|\| \
bogdanm	89:552587b429a1	247	((WAIT) == SDIO_WAIT_IT) \|\| \
bogdanm	89:552587b429a1	248	((WAIT) == SDIO_WAIT_PEND))
bogdanm	89:552587b429a1	249	/**
bogdanm	89:552587b429a1	250	* @}
bogdanm	89:552587b429a1	251	*/
bogdanm	89:552587b429a1	252
bogdanm	89:552587b429a1	253	/** @defgroup SDIO_CPSM_State
bogdanm	89:552587b429a1	254	* @{
bogdanm	89:552587b429a1	255	*/
bogdanm	89:552587b429a1	256	#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	257	#define SDIO_CPSM_ENABLE ((uint32_t)0x00000400)
bogdanm	89:552587b429a1	258
bogdanm	89:552587b429a1	259	#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) \|\| \
bogdanm	89:552587b429a1	260	((CPSM) == SDIO_CPSM_ENABLE))
bogdanm	89:552587b429a1	261	/**
bogdanm	89:552587b429a1	262	* @}
bogdanm	89:552587b429a1	263	*/
bogdanm	89:552587b429a1	264
bogdanm	89:552587b429a1	265	/** @defgroup SDIO_Response_Registers
bogdanm	89:552587b429a1	266	* @{
bogdanm	89:552587b429a1	267	*/
bogdanm	89:552587b429a1	268	#define SDIO_RESP1 ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	269	#define SDIO_RESP2 ((uint32_t)0x00000004)
bogdanm	89:552587b429a1	270	#define SDIO_RESP3 ((uint32_t)0x00000008)
bogdanm	89:552587b429a1	271	#define SDIO_RESP4 ((uint32_t)0x0000000C)
bogdanm	89:552587b429a1	272
bogdanm	89:552587b429a1	273	#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) \|\| \
bogdanm	89:552587b429a1	274	((RESP) == SDIO_RESP2) \|\| \
bogdanm	89:552587b429a1	275	((RESP) == SDIO_RESP3) \|\| \
bogdanm	89:552587b429a1	276	((RESP) == SDIO_RESP4))
bogdanm	89:552587b429a1	277	/**
bogdanm	89:552587b429a1	278	* @}
bogdanm	89:552587b429a1	279	*/
bogdanm	89:552587b429a1	280
bogdanm	89:552587b429a1	281	/** @defgroup SDIO_Data_Length
bogdanm	89:552587b429a1	282	* @{
bogdanm	89:552587b429a1	283	*/
bogdanm	89:552587b429a1	284	#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
bogdanm	89:552587b429a1	285	/**
bogdanm	89:552587b429a1	286	* @}
bogdanm	89:552587b429a1	287	*/
bogdanm	89:552587b429a1	288
bogdanm	89:552587b429a1	289	/** @defgroup SDIO_Data_Block_Size
bogdanm	89:552587b429a1	290	* @{
bogdanm	89:552587b429a1	291	*/
bogdanm	89:552587b429a1	292	#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	293	#define SDIO_DATABLOCK_SIZE_2B ((uint32_t)0x00000010)
bogdanm	89:552587b429a1	294	#define SDIO_DATABLOCK_SIZE_4B ((uint32_t)0x00000020)
bogdanm	89:552587b429a1	295	#define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
bogdanm	89:552587b429a1	296	#define SDIO_DATABLOCK_SIZE_16B ((uint32_t)0x00000040)
bogdanm	89:552587b429a1	297	#define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
bogdanm	89:552587b429a1	298	#define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
bogdanm	89:552587b429a1	299	#define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
bogdanm	89:552587b429a1	300	#define SDIO_DATABLOCK_SIZE_256B ((uint32_t)0x00000080)
bogdanm	89:552587b429a1	301	#define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
bogdanm	89:552587b429a1	302	#define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
bogdanm	89:552587b429a1	303	#define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
bogdanm	89:552587b429a1	304	#define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
bogdanm	89:552587b429a1	305	#define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
bogdanm	89:552587b429a1	306	#define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
bogdanm	89:552587b429a1	307
bogdanm	89:552587b429a1	308	#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) \|\| \
bogdanm	89:552587b429a1	309	((SIZE) == SDIO_DATABLOCK_SIZE_2B) \|\| \
bogdanm	89:552587b429a1	310	((SIZE) == SDIO_DATABLOCK_SIZE_4B) \|\| \
bogdanm	89:552587b429a1	311	((SIZE) == SDIO_DATABLOCK_SIZE_8B) \|\| \
bogdanm	89:552587b429a1	312	((SIZE) == SDIO_DATABLOCK_SIZE_16B) \|\| \
bogdanm	89:552587b429a1	313	((SIZE) == SDIO_DATABLOCK_SIZE_32B) \|\| \
bogdanm	89:552587b429a1	314	((SIZE) == SDIO_DATABLOCK_SIZE_64B) \|\| \
bogdanm	89:552587b429a1	315	((SIZE) == SDIO_DATABLOCK_SIZE_128B) \|\| \
bogdanm	89:552587b429a1	316	((SIZE) == SDIO_DATABLOCK_SIZE_256B) \|\| \
bogdanm	89:552587b429a1	317	((SIZE) == SDIO_DATABLOCK_SIZE_512B) \|\| \
bogdanm	89:552587b429a1	318	((SIZE) == SDIO_DATABLOCK_SIZE_1024B) \|\| \
bogdanm	89:552587b429a1	319	((SIZE) == SDIO_DATABLOCK_SIZE_2048B) \|\| \
bogdanm	89:552587b429a1	320	((SIZE) == SDIO_DATABLOCK_SIZE_4096B) \|\| \
bogdanm	89:552587b429a1	321	((SIZE) == SDIO_DATABLOCK_SIZE_8192B) \|\| \
bogdanm	89:552587b429a1	322	((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
bogdanm	89:552587b429a1	323	/**
bogdanm	89:552587b429a1	324	* @}
bogdanm	89:552587b429a1	325	*/
bogdanm	89:552587b429a1	326
bogdanm	89:552587b429a1	327	/** @defgroup SDIO_Transfer_Direction
bogdanm	89:552587b429a1	328	* @{
bogdanm	89:552587b429a1	329	*/
bogdanm	89:552587b429a1	330	#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	331	#define SDIO_TRANSFER_DIR_TO_SDIO ((uint32_t)0x00000002)
bogdanm	89:552587b429a1	332
bogdanm	89:552587b429a1	333	#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) \|\| \
bogdanm	89:552587b429a1	334	((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
bogdanm	89:552587b429a1	335	/**
bogdanm	89:552587b429a1	336	* @}
bogdanm	89:552587b429a1	337	*/
bogdanm	89:552587b429a1	338
bogdanm	89:552587b429a1	339	/** @defgroup SDIO_Transfer_Type
bogdanm	89:552587b429a1	340	* @{
bogdanm	89:552587b429a1	341	*/
bogdanm	89:552587b429a1	342	#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	343	#define SDIO_TRANSFER_MODE_STREAM ((uint32_t)0x00000004)
bogdanm	89:552587b429a1	344
bogdanm	89:552587b429a1	345	#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) \|\| \
bogdanm	89:552587b429a1	346	((MODE) == SDIO_TRANSFER_MODE_STREAM))
bogdanm	89:552587b429a1	347	/**
bogdanm	89:552587b429a1	348	* @}
bogdanm	89:552587b429a1	349	*/
bogdanm	89:552587b429a1	350
bogdanm	89:552587b429a1	351	/** @defgroup SDIO_DPSM_State
bogdanm	89:552587b429a1	352	* @{
bogdanm	89:552587b429a1	353	*/
bogdanm	89:552587b429a1	354	#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	355	#define SDIO_DPSM_ENABLE ((uint32_t)0x00000001)
bogdanm	89:552587b429a1	356
bogdanm	89:552587b429a1	357	#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) \|\|\
bogdanm	89:552587b429a1	358	((DPSM) == SDIO_DPSM_ENABLE))
bogdanm	89:552587b429a1	359	/**
bogdanm	89:552587b429a1	360	* @}
bogdanm	89:552587b429a1	361	*/
bogdanm	89:552587b429a1	362
bogdanm	89:552587b429a1	363	/** @defgroup SDIO_Read_Wait_Mode
bogdanm	89:552587b429a1	364	* @{
bogdanm	89:552587b429a1	365	*/
bogdanm	89:552587b429a1	366	#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	367	#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001)
bogdanm	89:552587b429a1	368
bogdanm	89:552587b429a1	369	#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) \|\| \
bogdanm	89:552587b429a1	370	((MODE) == SDIO_READ_WAIT_MODE_DATA2))
bogdanm	89:552587b429a1	371	/**
bogdanm	89:552587b429a1	372	* @}
bogdanm	89:552587b429a1	373	*/
bogdanm	89:552587b429a1	374
bogdanm	89:552587b429a1	375	/** @defgroup SDIO_Interrupt_sources
bogdanm	89:552587b429a1	376	* @{
bogdanm	89:552587b429a1	377	*/
bogdanm	89:552587b429a1	378	#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
bogdanm	89:552587b429a1	379	#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
bogdanm	89:552587b429a1	380	#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
bogdanm	89:552587b429a1	381	#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
bogdanm	89:552587b429a1	382	#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
bogdanm	89:552587b429a1	383	#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
bogdanm	89:552587b429a1	384	#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
bogdanm	89:552587b429a1	385	#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
bogdanm	89:552587b429a1	386	#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
bogdanm	89:552587b429a1	387	#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
bogdanm	89:552587b429a1	388	#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
bogdanm	89:552587b429a1	389	#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
bogdanm	89:552587b429a1	390	#define SDIO_IT_TXACT ((uint32_t)0x00001000)
bogdanm	89:552587b429a1	391	#define SDIO_IT_RXACT ((uint32_t)0x00002000)
bogdanm	89:552587b429a1	392	#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
bogdanm	89:552587b429a1	393	#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
bogdanm	89:552587b429a1	394	#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
bogdanm	89:552587b429a1	395	#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
bogdanm	89:552587b429a1	396	#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
bogdanm	89:552587b429a1	397	#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
bogdanm	89:552587b429a1	398	#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
bogdanm	89:552587b429a1	399	#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
bogdanm	89:552587b429a1	400	#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
bogdanm	89:552587b429a1	401	#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
bogdanm	89:552587b429a1	402
bogdanm	89:552587b429a1	403	#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
bogdanm	89:552587b429a1	404	/**
bogdanm	89:552587b429a1	405	* @}
bogdanm	89:552587b429a1	406	*/
bogdanm	89:552587b429a1	407
bogdanm	89:552587b429a1	408	/** @defgroup SDIO_Flags
bogdanm	89:552587b429a1	409	* @{
bogdanm	89:552587b429a1	410	*/
bogdanm	89:552587b429a1	411	#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
bogdanm	89:552587b429a1	412	#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
bogdanm	89:552587b429a1	413	#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
bogdanm	89:552587b429a1	414	#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
bogdanm	89:552587b429a1	415	#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
bogdanm	89:552587b429a1	416	#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
bogdanm	89:552587b429a1	417	#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
bogdanm	89:552587b429a1	418	#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
bogdanm	89:552587b429a1	419	#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
bogdanm	89:552587b429a1	420	#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
bogdanm	89:552587b429a1	421	#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
bogdanm	89:552587b429a1	422	#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
bogdanm	89:552587b429a1	423	#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
bogdanm	89:552587b429a1	424	#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
bogdanm	89:552587b429a1	425	#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
bogdanm	89:552587b429a1	426	#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
bogdanm	89:552587b429a1	427	#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
bogdanm	89:552587b429a1	428	#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
bogdanm	89:552587b429a1	429	#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
bogdanm	89:552587b429a1	430	#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
bogdanm	89:552587b429a1	431	#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
bogdanm	89:552587b429a1	432	#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
bogdanm	89:552587b429a1	433	#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
bogdanm	89:552587b429a1	434	#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
bogdanm	89:552587b429a1	435
bogdanm	89:552587b429a1	436	#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) \|\| \
bogdanm	89:552587b429a1	437	((FLAG) == SDIO_FLAG_DCRCFAIL) \|\| \
bogdanm	89:552587b429a1	438	((FLAG) == SDIO_FLAG_CTIMEOUT) \|\| \
bogdanm	89:552587b429a1	439	((FLAG) == SDIO_FLAG_DTIMEOUT) \|\| \
bogdanm	89:552587b429a1	440	((FLAG) == SDIO_FLAG_TXUNDERR) \|\| \
bogdanm	89:552587b429a1	441	((FLAG) == SDIO_FLAG_RXOVERR) \|\| \
bogdanm	89:552587b429a1	442	((FLAG) == SDIO_FLAG_CMDREND) \|\| \
bogdanm	89:552587b429a1	443	((FLAG) == SDIO_FLAG_CMDSENT) \|\| \
bogdanm	89:552587b429a1	444	((FLAG) == SDIO_FLAG_DATAEND) \|\| \
bogdanm	89:552587b429a1	445	((FLAG) == SDIO_FLAG_STBITERR) \|\| \
bogdanm	89:552587b429a1	446	((FLAG) == SDIO_FLAG_DBCKEND) \|\| \
bogdanm	89:552587b429a1	447	((FLAG) == SDIO_FLAG_CMDACT) \|\| \
bogdanm	89:552587b429a1	448	((FLAG) == SDIO_FLAG_TXACT) \|\| \
bogdanm	89:552587b429a1	449	((FLAG) == SDIO_FLAG_RXACT) \|\| \
bogdanm	89:552587b429a1	450	((FLAG) == SDIO_FLAG_TXFIFOHE) \|\| \
bogdanm	89:552587b429a1	451	((FLAG) == SDIO_FLAG_RXFIFOHF) \|\| \
bogdanm	89:552587b429a1	452	((FLAG) == SDIO_FLAG_TXFIFOF) \|\| \
bogdanm	89:552587b429a1	453	((FLAG) == SDIO_FLAG_RXFIFOF) \|\| \
bogdanm	89:552587b429a1	454	((FLAG) == SDIO_FLAG_TXFIFOE) \|\| \
bogdanm	89:552587b429a1	455	((FLAG) == SDIO_FLAG_RXFIFOE) \|\| \
bogdanm	89:552587b429a1	456	((FLAG) == SDIO_FLAG_TXDAVL) \|\| \
bogdanm	89:552587b429a1	457	((FLAG) == SDIO_FLAG_RXDAVL) \|\| \
bogdanm	89:552587b429a1	458	((FLAG) == SDIO_FLAG_SDIOIT) \|\| \
bogdanm	89:552587b429a1	459	((FLAG) == SDIO_FLAG_CEATAEND))
bogdanm	89:552587b429a1	460
bogdanm	89:552587b429a1	461	#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
bogdanm	89:552587b429a1	462
bogdanm	89:552587b429a1	463	#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) \|\| \
bogdanm	89:552587b429a1	464	((IT) == SDIO_IT_DCRCFAIL) \|\| \
bogdanm	89:552587b429a1	465	((IT) == SDIO_IT_CTIMEOUT) \|\| \
bogdanm	89:552587b429a1	466	((IT) == SDIO_IT_DTIMEOUT) \|\| \
bogdanm	89:552587b429a1	467	((IT) == SDIO_IT_TXUNDERR) \|\| \
bogdanm	89:552587b429a1	468	((IT) == SDIO_IT_RXOVERR) \|\| \
bogdanm	89:552587b429a1	469	((IT) == SDIO_IT_CMDREND) \|\| \
bogdanm	89:552587b429a1	470	((IT) == SDIO_IT_CMDSENT) \|\| \
bogdanm	89:552587b429a1	471	((IT) == SDIO_IT_DATAEND) \|\| \
bogdanm	89:552587b429a1	472	((IT) == SDIO_IT_STBITERR) \|\| \
bogdanm	89:552587b429a1	473	((IT) == SDIO_IT_DBCKEND) \|\| \
bogdanm	89:552587b429a1	474	((IT) == SDIO_IT_CMDACT) \|\| \
bogdanm	89:552587b429a1	475	((IT) == SDIO_IT_TXACT) \|\| \
bogdanm	89:552587b429a1	476	((IT) == SDIO_IT_RXACT) \|\| \
bogdanm	89:552587b429a1	477	((IT) == SDIO_IT_TXFIFOHE) \|\| \
bogdanm	89:552587b429a1	478	((IT) == SDIO_IT_RXFIFOHF) \|\| \
bogdanm	89:552587b429a1	479	((IT) == SDIO_IT_TXFIFOF) \|\| \
bogdanm	89:552587b429a1	480	((IT) == SDIO_IT_RXFIFOF) \|\| \
bogdanm	89:552587b429a1	481	((IT) == SDIO_IT_TXFIFOE) \|\| \
bogdanm	89:552587b429a1	482	((IT) == SDIO_IT_RXFIFOE) \|\| \
bogdanm	89:552587b429a1	483	((IT) == SDIO_IT_TXDAVL) \|\| \
bogdanm	89:552587b429a1	484	((IT) == SDIO_IT_RXDAVL) \|\| \
bogdanm	89:552587b429a1	485	((IT) == SDIO_IT_SDIOIT) \|\| \
bogdanm	89:552587b429a1	486	((IT) == SDIO_IT_CEATAEND))
bogdanm	89:552587b429a1	487
bogdanm	89:552587b429a1	488	#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
bogdanm	89:552587b429a1	489
bogdanm	89:552587b429a1	490	/**
bogdanm	89:552587b429a1	491	* @}
bogdanm	89:552587b429a1	492	*/
bogdanm	89:552587b429a1	493
bogdanm	89:552587b429a1	494
bogdanm	89:552587b429a1	495	/** @defgroup SDIO_Instance_definition
bogdanm	89:552587b429a1	496	* @{
bogdanm	89:552587b429a1	497	*/
bogdanm	89:552587b429a1	498	#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
bogdanm	89:552587b429a1	499
bogdanm	89:552587b429a1	500	/**
bogdanm	89:552587b429a1	501	* @}
bogdanm	89:552587b429a1	502	*/
bogdanm	89:552587b429a1	503
bogdanm	89:552587b429a1	504	/* Exported macro ------------------------------------------------------------*/
bogdanm	89:552587b429a1	505	/* ------------ SDIO registers bit address in the alias region -------------- */
bogdanm	89:552587b429a1	506	#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
bogdanm	89:552587b429a1	507
bogdanm	89:552587b429a1	508	/* --- CLKCR Register ---*/
bogdanm	89:552587b429a1	509	/* Alias word address of CLKEN bit */
bogdanm	89:552587b429a1	510	#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
bogdanm	89:552587b429a1	511	#define CLKEN_BitNumber 0x08
bogdanm	89:552587b429a1	512	#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
bogdanm	89:552587b429a1	513
bogdanm	89:552587b429a1	514	/* --- CMD Register ---*/
bogdanm	89:552587b429a1	515	/* Alias word address of SDIOSUSPEND bit */
bogdanm	89:552587b429a1	516	#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
bogdanm	89:552587b429a1	517	#define SDIOSUSPEND_BitNumber 0x0B
bogdanm	89:552587b429a1	518	#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
bogdanm	89:552587b429a1	519
bogdanm	89:552587b429a1	520	/* Alias word address of ENCMDCOMPL bit */
bogdanm	89:552587b429a1	521	#define ENCMDCOMPL_BitNumber 0x0C
bogdanm	89:552587b429a1	522	#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
bogdanm	89:552587b429a1	523
bogdanm	89:552587b429a1	524	/* Alias word address of NIEN bit */
bogdanm	89:552587b429a1	525	#define NIEN_BitNumber 0x0D
bogdanm	89:552587b429a1	526	#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
bogdanm	89:552587b429a1	527
bogdanm	89:552587b429a1	528	/* Alias word address of ATACMD bit */
bogdanm	89:552587b429a1	529	#define ATACMD_BitNumber 0x0E
bogdanm	89:552587b429a1	530	#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
bogdanm	89:552587b429a1	531
bogdanm	89:552587b429a1	532	/* --- DCTRL Register ---*/
bogdanm	89:552587b429a1	533	/* Alias word address of DMAEN bit */
bogdanm	89:552587b429a1	534	#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
bogdanm	89:552587b429a1	535	#define DMAEN_BitNumber 0x03
bogdanm	89:552587b429a1	536	#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
bogdanm	89:552587b429a1	537
bogdanm	89:552587b429a1	538	/* Alias word address of RWSTART bit */
bogdanm	89:552587b429a1	539	#define RWSTART_BitNumber 0x08
bogdanm	89:552587b429a1	540	#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
bogdanm	89:552587b429a1	541
bogdanm	89:552587b429a1	542	/* Alias word address of RWSTOP bit */
bogdanm	89:552587b429a1	543	#define RWSTOP_BitNumber 0x09
bogdanm	89:552587b429a1	544	#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
bogdanm	89:552587b429a1	545
bogdanm	89:552587b429a1	546	/* Alias word address of RWMOD bit */
bogdanm	89:552587b429a1	547	#define RWMOD_BitNumber 0x0A
bogdanm	89:552587b429a1	548	#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
bogdanm	89:552587b429a1	549
bogdanm	89:552587b429a1	550	/* Alias word address of SDIOEN bit */
bogdanm	89:552587b429a1	551	#define SDIOEN_BitNumber 0x0B
bogdanm	89:552587b429a1	552	#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
bogdanm	89:552587b429a1	553
bogdanm	89:552587b429a1	554	/* ---------------------- SDIO registers bit mask --------------------------- */
bogdanm	89:552587b429a1	555	/* --- CLKCR Register ---*/
bogdanm	89:552587b429a1	556	/* CLKCR register clear mask */
bogdanm	89:552587b429a1	557	#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
bogdanm	89:552587b429a1	558
bogdanm	89:552587b429a1	559	/* --- PWRCTRL Register ---*/
bogdanm	89:552587b429a1	560	/* SDIO PWRCTRL Mask */
bogdanm	89:552587b429a1	561	#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
bogdanm	89:552587b429a1	562
bogdanm	89:552587b429a1	563	/* --- DCTRL Register ---*/
bogdanm	89:552587b429a1	564	/* SDIO DCTRL Clear Mask */
bogdanm	89:552587b429a1	565	#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
bogdanm	89:552587b429a1	566
bogdanm	89:552587b429a1	567	/* --- CMD Register ---*/
bogdanm	89:552587b429a1	568	/* CMD Register clear mask */
bogdanm	89:552587b429a1	569	#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
bogdanm	89:552587b429a1	570
bogdanm	89:552587b429a1	571	/* SDIO RESP Registers Address */
bogdanm	89:552587b429a1	572	#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
bogdanm	89:552587b429a1	573
bogdanm	89:552587b429a1	574	/* SD FLASH SDIO Interface */
bogdanm	89:552587b429a1	575	#define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80)
bogdanm	89:552587b429a1	576
bogdanm	89:552587b429a1	577	/* SDIO Intialization Frequency (400KHz max) */
bogdanm	89:552587b429a1	578	#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
bogdanm	89:552587b429a1	579
bogdanm	89:552587b429a1	580	/* SDIO Data Transfer Frequency (25MHz max) */
bogdanm	89:552587b429a1	581	#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
bogdanm	89:552587b429a1	582
bogdanm	89:552587b429a1	583	/** @defgroup SDIO_Interrupt_Clock
bogdanm	89:552587b429a1	584	* @brief macros to handle interrupts and specific clock configurations
bogdanm	89:552587b429a1	585	* @{
bogdanm	89:552587b429a1	586	*/
bogdanm	89:552587b429a1	587
bogdanm	89:552587b429a1	588	/**
bogdanm	89:552587b429a1	589	* @brief Enable the SDIO device.
bogdanm	89:552587b429a1	590	* @param None
bogdanm	89:552587b429a1	591	* @retval None
bogdanm	89:552587b429a1	592	*/
bogdanm	89:552587b429a1	593	#define __SDIO_ENABLE() ((__IO uint32_t )CLKCR_CLKEN_BB = ENABLE)
bogdanm	89:552587b429a1	594
bogdanm	89:552587b429a1	595	/**
bogdanm	89:552587b429a1	596	* @brief Disable the SDIO device.
bogdanm	89:552587b429a1	597	* @param None
bogdanm	89:552587b429a1	598	* @retval None
bogdanm	89:552587b429a1	599	*/
bogdanm	89:552587b429a1	600	#define __SDIO_DISABLE() ((__IO uint32_t )CLKCR_CLKEN_BB = DISABLE)
bogdanm	89:552587b429a1	601
bogdanm	89:552587b429a1	602	/**
bogdanm	89:552587b429a1	603	* @brief Enable the SDIO DMA transfer.
bogdanm	89:552587b429a1	604	* @param None
bogdanm	89:552587b429a1	605	* @retval None
bogdanm	89:552587b429a1	606	*/
bogdanm	89:552587b429a1	607	#define __SDIO_DMA_ENABLE() ((__IO uint32_t )DCTRL_DMAEN_BB = ENABLE)
bogdanm	89:552587b429a1	608
bogdanm	89:552587b429a1	609	/**
bogdanm	89:552587b429a1	610	* @brief Disable the SDIO DMA transfer.
bogdanm	89:552587b429a1	611	* @param None
bogdanm	89:552587b429a1	612	* @retval None
bogdanm	89:552587b429a1	613	*/
bogdanm	89:552587b429a1	614	#define __SDIO_DMA_DISABLE() ((__IO uint32_t )DCTRL_DMAEN_BB = DISABLE)
bogdanm	89:552587b429a1	615
bogdanm	89:552587b429a1	616	/**
bogdanm	89:552587b429a1	617	* @brief Enable the SDIO device interrupt.
bogdanm	89:552587b429a1	618	* @param __INSTANCE__ : Pointer to SDIO register base
bogdanm	89:552587b429a1	619	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
bogdanm	89:552587b429a1	620	* This parameter can be one or a combination of the following values:
bogdanm	89:552587b429a1	621	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm	89:552587b429a1	622	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm	89:552587b429a1	623	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm	89:552587b429a1	624	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm	89:552587b429a1	625	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm	89:552587b429a1	626	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm	89:552587b429a1	627	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm	89:552587b429a1	628	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm	89:552587b429a1	629	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm	89:552587b429a1	630	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm	89:552587b429a1	631	* bus mode interrupt
bogdanm	89:552587b429a1	632	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm	89:552587b429a1	633	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm	89:552587b429a1	634	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm	89:552587b429a1	635	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm	89:552587b429a1	636	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm	89:552587b429a1	637	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm	89:552587b429a1	638	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm	89:552587b429a1	639	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm	89:552587b429a1	640	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm	89:552587b429a1	641	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm	89:552587b429a1	642	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm	89:552587b429a1	643	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm	89:552587b429a1	644	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm	89:552587b429a1	645	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm	89:552587b429a1	646	* @retval None
bogdanm	89:552587b429a1	647	*/
bogdanm	89:552587b429a1	648	#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
bogdanm	89:552587b429a1	649
bogdanm	89:552587b429a1	650	/**
bogdanm	89:552587b429a1	651	* @brief Disable the SDIO device interrupt.
bogdanm	89:552587b429a1	652	* @param __INSTANCE__ : Pointer to SDIO register base
bogdanm	89:552587b429a1	653	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
bogdanm	89:552587b429a1	654	* This parameter can be one or a combination of the following values:
bogdanm	89:552587b429a1	655	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm	89:552587b429a1	656	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm	89:552587b429a1	657	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm	89:552587b429a1	658	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm	89:552587b429a1	659	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm	89:552587b429a1	660	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm	89:552587b429a1	661	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm	89:552587b429a1	662	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm	89:552587b429a1	663	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm	89:552587b429a1	664	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm	89:552587b429a1	665	* bus mode interrupt
bogdanm	89:552587b429a1	666	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm	89:552587b429a1	667	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm	89:552587b429a1	668	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm	89:552587b429a1	669	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm	89:552587b429a1	670	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm	89:552587b429a1	671	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm	89:552587b429a1	672	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm	89:552587b429a1	673	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm	89:552587b429a1	674	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm	89:552587b429a1	675	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm	89:552587b429a1	676	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm	89:552587b429a1	677	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm	89:552587b429a1	678	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm	89:552587b429a1	679	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm	89:552587b429a1	680	* @retval None
bogdanm	89:552587b429a1	681	*/
bogdanm	89:552587b429a1	682	#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
bogdanm	89:552587b429a1	683
bogdanm	89:552587b429a1	684	/**
bogdanm	89:552587b429a1	685	* @brief Checks whether the specified SDIO flag is set or not.
bogdanm	89:552587b429a1	686	* @param __INSTANCE__ : Pointer to SDIO register base
bogdanm	89:552587b429a1	687	* @param __FLAG__: specifies the flag to check.
bogdanm	89:552587b429a1	688	* This parameter can be one of the following values:
bogdanm	89:552587b429a1	689	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
bogdanm	89:552587b429a1	690	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
bogdanm	89:552587b429a1	691	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
bogdanm	89:552587b429a1	692	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
bogdanm	89:552587b429a1	693	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
bogdanm	89:552587b429a1	694	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
bogdanm	89:552587b429a1	695	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
bogdanm	89:552587b429a1	696	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
bogdanm	89:552587b429a1	697	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
bogdanm	89:552587b429a1	698	* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
bogdanm	89:552587b429a1	699	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
bogdanm	89:552587b429a1	700	* @arg SDIO_FLAG_CMDACT: Command transfer in progress
bogdanm	89:552587b429a1	701	* @arg SDIO_FLAG_TXACT: Data transmit in progress
bogdanm	89:552587b429a1	702	* @arg SDIO_FLAG_RXACT: Data receive in progress
bogdanm	89:552587b429a1	703	* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
bogdanm	89:552587b429a1	704	* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
bogdanm	89:552587b429a1	705	* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
bogdanm	89:552587b429a1	706	* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
bogdanm	89:552587b429a1	707	* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
bogdanm	89:552587b429a1	708	* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
bogdanm	89:552587b429a1	709	* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
bogdanm	89:552587b429a1	710	* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
bogdanm	89:552587b429a1	711	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
bogdanm	89:552587b429a1	712	* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm	89:552587b429a1	713	* @retval The new state of SDIO_FLAG (SET or RESET).
bogdanm	89:552587b429a1	714	*/
bogdanm	89:552587b429a1	715	#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
bogdanm	89:552587b429a1	716
bogdanm	89:552587b429a1	717
bogdanm	89:552587b429a1	718	/**
bogdanm	89:552587b429a1	719	* @brief Clears the SDIO's pending flags.
bogdanm	89:552587b429a1	720	* @param __INSTANCE__ : Pointer to SDIO register base
bogdanm	89:552587b429a1	721	* @param __FLAG__: specifies the flag to clear.
bogdanm	89:552587b429a1	722	* This parameter can be one or a combination of the following values:
bogdanm	89:552587b429a1	723	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
bogdanm	89:552587b429a1	724	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
bogdanm	89:552587b429a1	725	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
bogdanm	89:552587b429a1	726	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
bogdanm	89:552587b429a1	727	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
bogdanm	89:552587b429a1	728	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
bogdanm	89:552587b429a1	729	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
bogdanm	89:552587b429a1	730	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
bogdanm	89:552587b429a1	731	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
bogdanm	89:552587b429a1	732	* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
bogdanm	89:552587b429a1	733	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
bogdanm	89:552587b429a1	734	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
bogdanm	89:552587b429a1	735	* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm	89:552587b429a1	736	* @retval None
bogdanm	89:552587b429a1	737	*/
bogdanm	89:552587b429a1	738	#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
bogdanm	89:552587b429a1	739
bogdanm	89:552587b429a1	740	/**
bogdanm	89:552587b429a1	741	* @brief Checks whether the specified SDIO interrupt has occurred or not.
bogdanm	89:552587b429a1	742	* @param __INSTANCE__ : Pointer to SDIO register base
bogdanm	89:552587b429a1	743	* @param __INTERRUPT__: specifies the SDIO interrupt source to check.
bogdanm	89:552587b429a1	744	* This parameter can be one of the following values:
bogdanm	89:552587b429a1	745	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm	89:552587b429a1	746	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm	89:552587b429a1	747	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm	89:552587b429a1	748	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm	89:552587b429a1	749	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm	89:552587b429a1	750	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm	89:552587b429a1	751	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm	89:552587b429a1	752	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm	89:552587b429a1	753	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm	89:552587b429a1	754	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm	89:552587b429a1	755	* bus mode interrupt
bogdanm	89:552587b429a1	756	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm	89:552587b429a1	757	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm	89:552587b429a1	758	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm	89:552587b429a1	759	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm	89:552587b429a1	760	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm	89:552587b429a1	761	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm	89:552587b429a1	762	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm	89:552587b429a1	763	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm	89:552587b429a1	764	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm	89:552587b429a1	765	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm	89:552587b429a1	766	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm	89:552587b429a1	767	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm	89:552587b429a1	768	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm	89:552587b429a1	769	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm	89:552587b429a1	770	* @retval The new state of SDIO_IT (SET or RESET).
bogdanm	89:552587b429a1	771	*/
bogdanm	89:552587b429a1	772	#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
bogdanm	89:552587b429a1	773
bogdanm	89:552587b429a1	774	/**
bogdanm	89:552587b429a1	775	* @brief Clears the SDIO's interrupt pending bits.
bogdanm	89:552587b429a1	776	* @param __INSTANCE__ : Pointer to SDIO register base
bogdanm	89:552587b429a1	777	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	89:552587b429a1	778	* This parameter can be one or a combination of the following values:
bogdanm	89:552587b429a1	779	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm	89:552587b429a1	780	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm	89:552587b429a1	781	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm	89:552587b429a1	782	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm	89:552587b429a1	783	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm	89:552587b429a1	784	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm	89:552587b429a1	785	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm	89:552587b429a1	786	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm	89:552587b429a1	787	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
bogdanm	89:552587b429a1	788	* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm	89:552587b429a1	789	* bus mode interrupt
bogdanm	89:552587b429a1	790	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm	89:552587b429a1	791	* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm	89:552587b429a1	792	* @retval None
bogdanm	89:552587b429a1	793	*/
bogdanm	89:552587b429a1	794	#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
bogdanm	89:552587b429a1	795
bogdanm	89:552587b429a1	796	/**
bogdanm	89:552587b429a1	797	* @brief Enable Start the SD I/O Read Wait operation.
bogdanm	89:552587b429a1	798	* @param None
bogdanm	89:552587b429a1	799	* @retval None
bogdanm	89:552587b429a1	800	*/
bogdanm	89:552587b429a1	801	#define __SDIO_START_READWAIT_ENABLE() ((__IO uint32_t ) DCTRL_RWSTART_BB = ENABLE)
bogdanm	89:552587b429a1	802
bogdanm	89:552587b429a1	803	/**
bogdanm	89:552587b429a1	804	* @brief Disable Start the SD I/O Read Wait operations.
bogdanm	89:552587b429a1	805	* @param None
bogdanm	89:552587b429a1	806	* @retval None
bogdanm	89:552587b429a1	807	*/
bogdanm	89:552587b429a1	808	#define __SDIO_START_READWAIT_DISABLE() ((__IO uint32_t ) DCTRL_RWSTART_BB = DISABLE)
bogdanm	89:552587b429a1	809
bogdanm	89:552587b429a1	810	/**
bogdanm	89:552587b429a1	811	* @brief Enable Start the SD I/O Read Wait operation.
bogdanm	89:552587b429a1	812	* @param None
bogdanm	89:552587b429a1	813	* @retval None
bogdanm	89:552587b429a1	814	*/
bogdanm	89:552587b429a1	815	#define __SDIO_STOP_READWAIT_ENABLE() ((__IO uint32_t ) DCTRL_RWSTOP_BB = ENABLE)
bogdanm	89:552587b429a1	816
bogdanm	89:552587b429a1	817	/**
bogdanm	89:552587b429a1	818	* @brief Disable Stop the SD I/O Read Wait operations.
bogdanm	89:552587b429a1	819	* @param None
bogdanm	89:552587b429a1	820	* @retval None
bogdanm	89:552587b429a1	821	*/
bogdanm	89:552587b429a1	822	#define __SDIO_STOP_READWAIT_DISABLE() ((__IO uint32_t ) DCTRL_RWSTOP_BB = DISABLE)
bogdanm	89:552587b429a1	823
bogdanm	89:552587b429a1	824	/**
bogdanm	89:552587b429a1	825	* @brief Enable the SD I/O Mode Operation.
bogdanm	89:552587b429a1	826	* @param None
bogdanm	89:552587b429a1	827	* @retval None
bogdanm	89:552587b429a1	828	*/
bogdanm	89:552587b429a1	829	#define __SDIO_OPERATION_ENABLE() ((__IO uint32_t ) DCTRL_SDIOEN_BB = ENABLE)
bogdanm	89:552587b429a1	830
bogdanm	89:552587b429a1	831	/**
bogdanm	89:552587b429a1	832	* @brief Disable the SD I/O Mode Operation.
bogdanm	89:552587b429a1	833	* @param None
bogdanm	89:552587b429a1	834	* @retval None
bogdanm	89:552587b429a1	835	*/
bogdanm	89:552587b429a1	836	#define __SDIO_OPERATION_DISABLE() ((__IO uint32_t ) DCTRL_SDIOEN_BB = DISABLE)
bogdanm	89:552587b429a1	837
bogdanm	89:552587b429a1	838	/**
bogdanm	89:552587b429a1	839	* @brief Enable the SD I/O Suspend command sending.
bogdanm	89:552587b429a1	840	* @param None
bogdanm	89:552587b429a1	841	* @retval None
bogdanm	89:552587b429a1	842	*/
bogdanm	89:552587b429a1	843	#define __SDIO_SUSPEND_CMD_ENABLE() ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = ENABLE)
bogdanm	89:552587b429a1	844
bogdanm	89:552587b429a1	845	/**
bogdanm	89:552587b429a1	846	* @brief Disable the SD I/O Suspend command sending.
bogdanm	89:552587b429a1	847	* @param None
bogdanm	89:552587b429a1	848	* @retval None
bogdanm	89:552587b429a1	849	*/
bogdanm	89:552587b429a1	850	#define __SDIO_SUSPEND_CMD_DISABLE() ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = DISABLE)
bogdanm	89:552587b429a1	851
bogdanm	89:552587b429a1	852	/**
bogdanm	89:552587b429a1	853	* @brief Enable the command completion signal.
bogdanm	89:552587b429a1	854	* @param None
bogdanm	89:552587b429a1	855	* @retval None
bogdanm	89:552587b429a1	856	*/
bogdanm	89:552587b429a1	857	#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = ENABLE)
bogdanm	89:552587b429a1	858
bogdanm	89:552587b429a1	859	/**
bogdanm	89:552587b429a1	860	* @brief Disable the command completion signal.
bogdanm	89:552587b429a1	861	* @param None
bogdanm	89:552587b429a1	862	* @retval None
bogdanm	89:552587b429a1	863	*/
bogdanm	89:552587b429a1	864	#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = DISABLE)
bogdanm	89:552587b429a1	865
bogdanm	89:552587b429a1	866	/**
bogdanm	89:552587b429a1	867	* @brief Enable the CE-ATA interrupt.
bogdanm	89:552587b429a1	868	* @param None
bogdanm	89:552587b429a1	869	* @retval None
bogdanm	89:552587b429a1	870	*/
bogdanm	89:552587b429a1	871	#define __SDIO_CEATA_ENABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)0)
bogdanm	89:552587b429a1	872
bogdanm	89:552587b429a1	873	/**
bogdanm	89:552587b429a1	874	* @brief Disable the CE-ATA interrupt.
bogdanm	89:552587b429a1	875	* @param None
bogdanm	89:552587b429a1	876	* @retval None
bogdanm	89:552587b429a1	877	*/
bogdanm	89:552587b429a1	878	#define __SDIO_CEATA_DISABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)1)
bogdanm	89:552587b429a1	879
bogdanm	89:552587b429a1	880	/**
bogdanm	89:552587b429a1	881	* @brief Enable send CE-ATA command (CMD61).
bogdanm	89:552587b429a1	882	* @param None
bogdanm	89:552587b429a1	883	* @retval None
bogdanm	89:552587b429a1	884	*/
bogdanm	89:552587b429a1	885	#define __SDIO_CEATA_SENDCMD_ENABLE() ((__IO uint32_t ) CMD_ATACMD_BB = ENABLE)
bogdanm	89:552587b429a1	886
bogdanm	89:552587b429a1	887	/**
bogdanm	89:552587b429a1	888	* @brief Disable send CE-ATA command (CMD61).
bogdanm	89:552587b429a1	889	* @param None
bogdanm	89:552587b429a1	890	* @retval None
bogdanm	89:552587b429a1	891	*/
bogdanm	89:552587b429a1	892	#define __SDIO_CEATA_SENDCMD_DISABLE() ((__IO uint32_t ) CMD_ATACMD_BB = DISABLE)
bogdanm	89:552587b429a1	893
bogdanm	89:552587b429a1	894	/**
bogdanm	89:552587b429a1	895	* @}
bogdanm	89:552587b429a1	896	*/
bogdanm	89:552587b429a1	897
bogdanm	89:552587b429a1	898	/* Exported functions --------------------------------------------------------*/
bogdanm	89:552587b429a1	899
bogdanm	89:552587b429a1	900	/* Initialization/de-initialization functions **********************************/
bogdanm	89:552587b429a1	901	HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
bogdanm	89:552587b429a1	902
bogdanm	89:552587b429a1	903	/* I/O operation functions *****************************************************/
bogdanm	89:552587b429a1	904	/* Blocking mode: Polling */
bogdanm	89:552587b429a1	905	uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
bogdanm	89:552587b429a1	906	HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef SDIOx, uint32_t pWriteData);
bogdanm	89:552587b429a1	907
bogdanm	89:552587b429a1	908	/* Peripheral Control functions ************************************************/
bogdanm	89:552587b429a1	909	HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
bogdanm	89:552587b429a1	910	HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
bogdanm	89:552587b429a1	911	uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
bogdanm	89:552587b429a1	912
bogdanm	89:552587b429a1	913	/* Command path state machine (CPSM) management functions */
bogdanm	89:552587b429a1	914	HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef SDIOx, SDIO_CmdInitTypeDef SDIO_CmdInitStruct);
bogdanm	89:552587b429a1	915	uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
bogdanm	89:552587b429a1	916	uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
bogdanm	89:552587b429a1	917
bogdanm	89:552587b429a1	918	/* Data path state machine (DPSM) management functions */
bogdanm	89:552587b429a1	919	HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef SDIOx, SDIO_DataInitTypeDef SDIO_DataInitStruct);
bogdanm	89:552587b429a1	920	uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
bogdanm	89:552587b429a1	921	uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
bogdanm	89:552587b429a1	922
bogdanm	89:552587b429a1	923	/* SDIO IO Cards mode management functions */
bogdanm	89:552587b429a1	924	HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
bogdanm	89:552587b429a1	925
bogdanm	89:552587b429a1	926	#ifdef __cplusplus
bogdanm	89:552587b429a1	927	}
bogdanm	89:552587b429a1	928	#endif
bogdanm	89:552587b429a1	929
bogdanm	89:552587b429a1	930	#endif /* __STM32F4xx_LL_SDMMC_H */
bogdanm	89:552587b429a1	931
bogdanm	89:552587b429a1	932	/**
bogdanm	89:552587b429a1	933	* @}
bogdanm	89:552587b429a1	934	*/
bogdanm	89:552587b429a1	935
bogdanm	89:552587b429a1	936	/**
bogdanm	89:552587b429a1	937	* @}
bogdanm	89:552587b429a1	938	*/
bogdanm	89:552587b429a1	939
bogdanm	89:552587b429a1	940	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	25 Jun 2015
Imports:	24
Forks:	0
Commits:	103
Dependents:	1
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TARGET_ARCH_MAX/stm32f4xx_ll_sdmmc.h@89:552587b429a1, 2014-09-12 (annotated)

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