Renesas / mbed-src_GR-PEACH_rev_b

mbed library sources for GR-PEACH rev.B.

Fork of mbed-src by mbed official

targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c@500:04797f1feae2, 2015-03-31 (annotated)

Committer:
mbed_official
Date:
Tue Mar 31 16:15:13 2015 +0100
Revision:
500:04797f1feae2
Parent:
443:ed48b4122bfb 
Synchronized with git revision 251f3f8b55a4dc98b831c80e032464ed45cce309



Full URL: https://github.com/mbedmicro/mbed/commit/251f3f8b55a4dc98b831c80e032464ed45cce309/



[RZ/A1H]Add some function(USB 2port, NVIC wrapper) and modify some settings(OS, Terminal).

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /* mbed Microcontroller Library
mbed_official 390:35c2c1cf29cd 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 390:35c2c1cf29cd 3 *
mbed_official 390:35c2c1cf29cd 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 390:35c2c1cf29cd 5 * you may not use this file except in compliance with the License.
mbed_official 390:35c2c1cf29cd 6 * You may obtain a copy of the License at
mbed_official 390:35c2c1cf29cd 7 *
mbed_official 390:35c2c1cf29cd 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 390:35c2c1cf29cd 9 *
mbed_official 390:35c2c1cf29cd 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 390:35c2c1cf29cd 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 390:35c2c1cf29cd 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 390:35c2c1cf29cd 13 * See the License for the specific language governing permissions and
mbed_official 390:35c2c1cf29cd 14 * limitations under the License.
mbed_official 390:35c2c1cf29cd 15 */
mbed_official 390:35c2c1cf29cd 16 #include "mbed_assert.h"
mbed_official 390:35c2c1cf29cd 17 #include <math.h>
mbed_official 390:35c2c1cf29cd 18
mbed_official 390:35c2c1cf29cd 19 #include "spi_api.h"
mbed_official 390:35c2c1cf29cd 20 #include "cmsis.h"
mbed_official 390:35c2c1cf29cd 21 #include "pinmap.h"
mbed_official 390:35c2c1cf29cd 22 #include "mbed_error.h"
mbed_official 441:d2c15dda23c1 23 #include "RZ_A1_Init.h"
mbed_official 390:35c2c1cf29cd 24
mbed_official 390:35c2c1cf29cd 25 static const PinMap PinMap_SPI_SCLK[] = {
mbed_official 390:35c2c1cf29cd 26 {P10_12, SPI_0, 4},
mbed_official 500:04797f1feae2 27 {P4_4 , SPI_1, 2},
mbed_official 390:35c2c1cf29cd 28 {P11_12, SPI_1, 2},
mbed_official 441:d2c15dda23c1 29 {P8_3 , SPI_2, 3},
mbed_official 441:d2c15dda23c1 30 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 31 };
mbed_official 390:35c2c1cf29cd 32
mbed_official 390:35c2c1cf29cd 33 static const PinMap PinMap_SPI_SSEL[] = {
mbed_official 390:35c2c1cf29cd 34 {P10_13, SPI_0, 4},
mbed_official 500:04797f1feae2 35 {P4_5 , SPI_1, 2},
mbed_official 390:35c2c1cf29cd 36 {P11_13, SPI_1, 2},
mbed_official 441:d2c15dda23c1 37 {P8_4 , SPI_2, 3},
mbed_official 441:d2c15dda23c1 38 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 39 };
mbed_official 390:35c2c1cf29cd 40
mbed_official 390:35c2c1cf29cd 41 static const PinMap PinMap_SPI_MOSI[] = {
mbed_official 390:35c2c1cf29cd 42 {P10_14, SPI_0, 4},
mbed_official 500:04797f1feae2 43 {P4_6 , SPI_1, 2},
mbed_official 390:35c2c1cf29cd 44 {P11_14, SPI_1, 2},
mbed_official 441:d2c15dda23c1 45 {P8_5 , SPI_2, 3},
mbed_official 441:d2c15dda23c1 46 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 47 };
mbed_official 390:35c2c1cf29cd 48
mbed_official 390:35c2c1cf29cd 49 static const PinMap PinMap_SPI_MISO[] = {
mbed_official 390:35c2c1cf29cd 50 {P10_15, SPI_0, 4},
mbed_official 500:04797f1feae2 51 {P4_7 , SPI_1, 2},
mbed_official 390:35c2c1cf29cd 52 {P11_15, SPI_1, 2},
mbed_official 441:d2c15dda23c1 53 {P8_6 , SPI_2, 3},
mbed_official 441:d2c15dda23c1 54 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 55 };
mbed_official 390:35c2c1cf29cd 56
mbed_official 441:d2c15dda23c1 57 static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST;
mbed_official 390:35c2c1cf29cd 58
mbed_official 390:35c2c1cf29cd 59 static inline void spi_disable(spi_t *obj);
mbed_official 390:35c2c1cf29cd 60 static inline void spi_enable(spi_t *obj);
mbed_official 390:35c2c1cf29cd 61 static inline int spi_readable(spi_t *obj);
mbed_official 390:35c2c1cf29cd 62 static inline void spi_write(spi_t *obj, int value);
mbed_official 390:35c2c1cf29cd 63 static inline int spi_read(spi_t *obj);
mbed_official 390:35c2c1cf29cd 64
mbed_official 390:35c2c1cf29cd 65 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
mbed_official 390:35c2c1cf29cd 66 // determine the SPI to use
mbed_official 441:d2c15dda23c1 67 volatile uint8_t dummy;
mbed_official 441:d2c15dda23c1 68 uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
mbed_official 441:d2c15dda23c1 69 uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
mbed_official 441:d2c15dda23c1 70 uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
mbed_official 441:d2c15dda23c1 71 uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
mbed_official 441:d2c15dda23c1 72 uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
mbed_official 441:d2c15dda23c1 73 uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
mbed_official 441:d2c15dda23c1 74 uint32_t spi = pinmap_merge(spi_data, spi_cntl);
mbed_official 441:d2c15dda23c1 75
mbed_official 441:d2c15dda23c1 76 MBED_ASSERT((int)spi != NC);
mbed_official 441:d2c15dda23c1 77
mbed_official 441:d2c15dda23c1 78 obj->spi = (struct st_rspi *)RSPI[spi];
mbed_official 441:d2c15dda23c1 79
mbed_official 390:35c2c1cf29cd 80 // enable power and clocking
mbed_official 441:d2c15dda23c1 81 switch (spi) {
mbed_official 390:35c2c1cf29cd 82 case SPI_0: CPGSTBCR10 &= ~(0x80); break;
mbed_official 390:35c2c1cf29cd 83 case SPI_1: CPGSTBCR10 &= ~(0x40); break;
mbed_official 420:8e6e2662709e 84 case SPI_2: CPGSTBCR10 &= ~(0x20); break;
mbed_official 390:35c2c1cf29cd 85 }
mbed_official 390:35c2c1cf29cd 86 dummy = CPGSTBCR10;
mbed_official 390:35c2c1cf29cd 87
mbed_official 441:d2c15dda23c1 88 obj->spi->SPCR = 0x00; // CTRL to 0
mbed_official 441:d2c15dda23c1 89 obj->spi->SPSCR = 0x00; // no sequential operation
mbed_official 441:d2c15dda23c1 90 obj->spi->SSLP = 0x00; // SSL 'L' active
mbed_official 441:d2c15dda23c1 91 obj->spi->SPDCR = 0x20; // byte access
mbed_official 441:d2c15dda23c1 92 obj->spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK
mbed_official 441:d2c15dda23c1 93 obj->spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK
mbed_official 441:d2c15dda23c1 94 obj->spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK
mbed_official 441:d2c15dda23c1 95 obj->spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0
mbed_official 441:d2c15dda23c1 96 obj->spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1
mbed_official 441:d2c15dda23c1 97 obj->spi->SPBFCR = 0x30; // and reset buffer
mbed_official 390:35c2c1cf29cd 98
mbed_official 390:35c2c1cf29cd 99 // set default format and frequency
mbed_official 441:d2c15dda23c1 100 if ((int)ssel == NC) {
mbed_official 390:35c2c1cf29cd 101 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
mbed_official 390:35c2c1cf29cd 102 } else {
mbed_official 390:35c2c1cf29cd 103 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
mbed_official 390:35c2c1cf29cd 104 }
mbed_official 390:35c2c1cf29cd 105 spi_frequency(obj, 1000000);
mbed_official 390:35c2c1cf29cd 106
mbed_official 390:35c2c1cf29cd 107 // pin out the spi pins
mbed_official 390:35c2c1cf29cd 108 pinmap_pinout(mosi, PinMap_SPI_MOSI);
mbed_official 390:35c2c1cf29cd 109 pinmap_pinout(miso, PinMap_SPI_MISO);
mbed_official 390:35c2c1cf29cd 110 pinmap_pinout(sclk, PinMap_SPI_SCLK);
mbed_official 441:d2c15dda23c1 111 if ((int)ssel != NC) {
mbed_official 390:35c2c1cf29cd 112 pinmap_pinout(ssel, PinMap_SPI_SSEL);
mbed_official 390:35c2c1cf29cd 113 }
mbed_official 390:35c2c1cf29cd 114 }
mbed_official 390:35c2c1cf29cd 115
mbed_official 390:35c2c1cf29cd 116 void spi_free(spi_t *obj) {}
mbed_official 390:35c2c1cf29cd 117
mbed_official 390:35c2c1cf29cd 118 void spi_format(spi_t *obj, int bits, int mode, int slave) {
mbed_official 441:d2c15dda23c1 119 int DSS; // DSS (data select size)
mbed_official 441:d2c15dda23c1 120 int polarity = (mode & 0x2) ? 1 : 0;
mbed_official 441:d2c15dda23c1 121 int phase = (mode & 0x1) ? 1 : 0;
mbed_official 441:d2c15dda23c1 122 uint16_t tmp = 0;
mbed_official 441:d2c15dda23c1 123 uint16_t mask = 0xf03;
mbed_official 443:ed48b4122bfb 124 uint16_t wk_spcmd0;
mbed_official 441:d2c15dda23c1 125 uint8_t splw;
mbed_official 390:35c2c1cf29cd 126
mbed_official 441:d2c15dda23c1 127 switch (mode) {
mbed_official 441:d2c15dda23c1 128 case 0:
mbed_official 441:d2c15dda23c1 129 case 1:
mbed_official 441:d2c15dda23c1 130 case 2:
mbed_official 441:d2c15dda23c1 131 case 3:
mbed_official 441:d2c15dda23c1 132 // Do Nothing
mbed_official 441:d2c15dda23c1 133 break;
mbed_official 441:d2c15dda23c1 134 default:
mbed_official 441:d2c15dda23c1 135 error("SPI format error");
mbed_official 441:d2c15dda23c1 136 return;
mbed_official 441:d2c15dda23c1 137 }
mbed_official 390:35c2c1cf29cd 138
mbed_official 390:35c2c1cf29cd 139 switch (bits) {
mbed_official 390:35c2c1cf29cd 140 case 8:
mbed_official 441:d2c15dda23c1 141 DSS = 0x7;
mbed_official 441:d2c15dda23c1 142 splw = 0x20;
mbed_official 441:d2c15dda23c1 143 break;
mbed_official 390:35c2c1cf29cd 144 case 16:
mbed_official 441:d2c15dda23c1 145 DSS = 0xf;
mbed_official 441:d2c15dda23c1 146 splw = 0x40;
mbed_official 441:d2c15dda23c1 147 break;
mbed_official 390:35c2c1cf29cd 148 case 32:
mbed_official 441:d2c15dda23c1 149 DSS = 0x2;
mbed_official 441:d2c15dda23c1 150 splw = 0x60;
mbed_official 441:d2c15dda23c1 151 break;
mbed_official 390:35c2c1cf29cd 152 default:
mbed_official 390:35c2c1cf29cd 153 error("SPI module don't support other than 8/16/32bits");
mbed_official 441:d2c15dda23c1 154 return;
mbed_official 390:35c2c1cf29cd 155 }
mbed_official 441:d2c15dda23c1 156 tmp |= phase;
mbed_official 441:d2c15dda23c1 157 tmp |= (polarity << 1);
mbed_official 390:35c2c1cf29cd 158 tmp |= (DSS << 8);
mbed_official 441:d2c15dda23c1 159 obj->bits = bits;
mbed_official 390:35c2c1cf29cd 160
mbed_official 441:d2c15dda23c1 161 spi_disable(obj);
mbed_official 443:ed48b4122bfb 162 wk_spcmd0 = obj->spi->SPCMD0;
mbed_official 443:ed48b4122bfb 163 wk_spcmd0 &= ~mask;
mbed_official 443:ed48b4122bfb 164 wk_spcmd0 |= (mask & tmp);
mbed_official 443:ed48b4122bfb 165 obj->spi->SPCMD0 = wk_spcmd0;
mbed_official 441:d2c15dda23c1 166 obj->spi->SPDCR = splw;
mbed_official 390:35c2c1cf29cd 167 if (slave) {
mbed_official 441:d2c15dda23c1 168 obj->spi->SPCR &=~(1 << 3); // MSTR to 0
mbed_official 390:35c2c1cf29cd 169 } else {
mbed_official 441:d2c15dda23c1 170 obj->spi->SPCR |= (1 << 3); // MSTR to 1
mbed_official 390:35c2c1cf29cd 171 }
mbed_official 390:35c2c1cf29cd 172 spi_enable(obj);
mbed_official 390:35c2c1cf29cd 173 }
mbed_official 390:35c2c1cf29cd 174
mbed_official 390:35c2c1cf29cd 175 void spi_frequency(spi_t *obj, int hz) {
mbed_official 441:d2c15dda23c1 176 uint32_t pclk_base;
mbed_official 441:d2c15dda23c1 177 uint32_t div;
mbed_official 441:d2c15dda23c1 178 uint32_t brdv = 0;
mbed_official 441:d2c15dda23c1 179 uint32_t hz_max;
mbed_official 441:d2c15dda23c1 180 uint32_t hz_min;
mbed_official 441:d2c15dda23c1 181 uint16_t mask = 0x000c;
mbed_official 443:ed48b4122bfb 182 uint16_t wk_spcmd0;
mbed_official 390:35c2c1cf29cd 183
mbed_official 441:d2c15dda23c1 184 /* set PCLK */
mbed_official 441:d2c15dda23c1 185 if (RZ_A1_IsClockMode0() == false) {
mbed_official 441:d2c15dda23c1 186 pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
mbed_official 390:35c2c1cf29cd 187 } else {
mbed_official 441:d2c15dda23c1 188 pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
mbed_official 441:d2c15dda23c1 189 }
mbed_official 441:d2c15dda23c1 190
mbed_official 441:d2c15dda23c1 191 hz_min = pclk_base / 2 / 256 / 8;
mbed_official 441:d2c15dda23c1 192 hz_max = pclk_base / 2;
mbed_official 441:d2c15dda23c1 193 if ((hz < hz_min) || (hz > hz_max)) {
mbed_official 390:35c2c1cf29cd 194 error("Couldn't setup requested SPI frequency");
mbed_official 390:35c2c1cf29cd 195 return;
mbed_official 390:35c2c1cf29cd 196 }
mbed_official 390:35c2c1cf29cd 197
mbed_official 441:d2c15dda23c1 198 div = (pclk_base / hz / 2);
mbed_official 441:d2c15dda23c1 199 while (div > 256) {
mbed_official 441:d2c15dda23c1 200 div >>= 1;
mbed_official 441:d2c15dda23c1 201 brdv++;
mbed_official 441:d2c15dda23c1 202 }
mbed_official 441:d2c15dda23c1 203 div -= 1;
mbed_official 441:d2c15dda23c1 204 brdv = (brdv << 2);
mbed_official 390:35c2c1cf29cd 205
mbed_official 441:d2c15dda23c1 206 spi_disable(obj);
mbed_official 441:d2c15dda23c1 207 obj->spi->SPBR = div;
mbed_official 443:ed48b4122bfb 208 wk_spcmd0 = obj->spi->SPCMD0;
mbed_official 443:ed48b4122bfb 209 wk_spcmd0 &= ~mask;
mbed_official 443:ed48b4122bfb 210 wk_spcmd0 |= (mask & brdv);
mbed_official 443:ed48b4122bfb 211 obj->spi->SPCMD0 = wk_spcmd0;
mbed_official 390:35c2c1cf29cd 212 spi_enable(obj);
mbed_official 390:35c2c1cf29cd 213 }
mbed_official 390:35c2c1cf29cd 214
mbed_official 390:35c2c1cf29cd 215 static inline void spi_disable(spi_t *obj) {
mbed_official 441:d2c15dda23c1 216 obj->spi->SPCR &= ~(1 << 6); // SPE to 0
mbed_official 390:35c2c1cf29cd 217 }
mbed_official 390:35c2c1cf29cd 218
mbed_official 390:35c2c1cf29cd 219 static inline void spi_enable(spi_t *obj) {
mbed_official 441:d2c15dda23c1 220 obj->spi->SPCR |= (1 << 6); // SPE to 1
mbed_official 390:35c2c1cf29cd 221 }
mbed_official 390:35c2c1cf29cd 222
mbed_official 390:35c2c1cf29cd 223 static inline int spi_readable(spi_t *obj) {
mbed_official 441:d2c15dda23c1 224 return obj->spi->SPSR & (1 << 7); // SPRF
mbed_official 390:35c2c1cf29cd 225 }
mbed_official 390:35c2c1cf29cd 226
mbed_official 390:35c2c1cf29cd 227 static inline int spi_tend(spi_t *obj) {
mbed_official 441:d2c15dda23c1 228 return obj->spi->SPSR & (1 << 6); // TEND
mbed_official 390:35c2c1cf29cd 229 }
mbed_official 390:35c2c1cf29cd 230
mbed_official 390:35c2c1cf29cd 231 static inline void spi_write(spi_t *obj, int value) {
mbed_official 441:d2c15dda23c1 232 if (obj->bits == 8) {
mbed_official 441:d2c15dda23c1 233 obj->spi->SPDR.UINT8[0] = (uint8_t)value;
mbed_official 441:d2c15dda23c1 234 } else if (obj->bits == 16) {
mbed_official 441:d2c15dda23c1 235 obj->spi->SPDR.UINT16[0] = (uint16_t)value;
mbed_official 441:d2c15dda23c1 236 } else {
mbed_official 441:d2c15dda23c1 237 obj->spi->SPDR.UINT32 = (uint32_t)value;
mbed_official 441:d2c15dda23c1 238 }
mbed_official 390:35c2c1cf29cd 239 }
mbed_official 390:35c2c1cf29cd 240
mbed_official 390:35c2c1cf29cd 241 static inline int spi_read(spi_t *obj) {
mbed_official 441:d2c15dda23c1 242 int read_data;
mbed_official 441:d2c15dda23c1 243
mbed_official 441:d2c15dda23c1 244 if (obj->bits == 8) {
mbed_official 441:d2c15dda23c1 245 read_data = obj->spi->SPDR.UINT8[0];
mbed_official 441:d2c15dda23c1 246 } else if (obj->bits == 16) {
mbed_official 441:d2c15dda23c1 247 read_data = obj->spi->SPDR.UINT16[0];
mbed_official 441:d2c15dda23c1 248 } else {
mbed_official 441:d2c15dda23c1 249 read_data = obj->spi->SPDR.UINT32;
mbed_official 441:d2c15dda23c1 250 }
mbed_official 441:d2c15dda23c1 251
mbed_official 441:d2c15dda23c1 252 return read_data;
mbed_official 390:35c2c1cf29cd 253 }
mbed_official 390:35c2c1cf29cd 254
mbed_official 390:35c2c1cf29cd 255 int spi_master_write(spi_t *obj, int value) {
mbed_official 390:35c2c1cf29cd 256 spi_write(obj, value);
mbed_official 390:35c2c1cf29cd 257 while(!spi_tend(obj));
mbed_official 390:35c2c1cf29cd 258 return spi_read(obj);
mbed_official 390:35c2c1cf29cd 259 }
mbed_official 390:35c2c1cf29cd 260
mbed_official 390:35c2c1cf29cd 261 int spi_slave_receive(spi_t *obj) {
mbed_official 390:35c2c1cf29cd 262 return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
mbed_official 390:35c2c1cf29cd 263 }
mbed_official 390:35c2c1cf29cd 264
mbed_official 390:35c2c1cf29cd 265 int spi_slave_read(spi_t *obj) {
mbed_official 441:d2c15dda23c1 266 return spi_read(obj);
mbed_official 390:35c2c1cf29cd 267 }
mbed_official 390:35c2c1cf29cd 268
mbed_official 390:35c2c1cf29cd 269 void spi_slave_write(spi_t *obj, int value) {
mbed_official 441:d2c15dda23c1 270 spi_write(obj, value);
mbed_official 390:35c2c1cf29cd 271 }
mbed_official 390:35c2c1cf29cd 272
mbed_official 390:35c2c1cf29cd 273 int spi_busy(spi_t *obj) {
mbed_official 441:d2c15dda23c1 274 return 0;
mbed_official 390:35c2c1cf29cd 275 }