Revision 500:04797f1feae2, committed 2015-03-31

Comitter:

mbed_official

Date:

Tue Mar 31 16:15:13 2015 +0100

Parent:

499:d0e9408fd176

Child:

501:36015dec7d16

Commit message:

Synchronized with git revision 251f3f8b55a4dc98b831c80e032464ed45cce309

Full URL: https://github.com/mbedmicro/mbed/commit/251f3f8b55a4dc98b831c80e032464ed45cce309/

[RZ/A1H]Add some function(USB 2port, NVIC wrapper) and modify some settings(OS, Terminal).

Changed in this revision

--- a/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h	Sat Mar 28 08:15:07 2015 +0000
+++ b/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h	Tue Mar 31 16:15:13 2015 +0100
@@ -644,6 +644,8 @@
 
 #include "pl310.h"
 #include "gic.h"
+#include "nvic_wrapper.h"
+#include "cmsis_nvic.h"
 
 #include "ostm_iodefine.h"
 #include "gpio_iodefine.h"

--- a/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s	Sat Mar 28 08:15:07 2015 +0000
+++ b/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s	Tue Mar 31 16:15:13 2015 +0100
@@ -173,7 +173,7 @@
  
 @ Setup Stack for each exceptional mode 
 /*    ldr     r0, =__StackTop  */
-    ldr     r0, =__initial_sp
+    ldr     r0, =(__StackTop - USR_Stack_Size)
 
 @ Enter Undefined Instruction Mode and set its Stack Pointer 
     msr     cpsr_c, #(Mode_UND | I_Bit | F_Bit)
@@ -521,9 +521,9 @@
 __user_initial_stackheap:
 
                 LDR     R0, =  __HeapBase
-                LDR     R1, =(__StackLimit + USR_Stack_Size)
+                LDR     R1, =(__StackTop)
                 LDR     R2, = (__HeapBase +  Heap_Size)
-                LDR     R3, = __StackLimit
+                LDR     R3, = (__StackTop - USR_Stack_Size)
                 BX      LR
 
                 .endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.c	Tue Mar 31 16:15:13 2015 +0100
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "MBRZA1H.h"
+
+extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    InterruptHandlerRegister(IRQn, (IRQHandler)vector);
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t vectors = (uint32_t)IRQTable[IRQn];
+    return vectors;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.h	Tue Mar 31 16:15:13 2015 +0100
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.c	Tue Mar 31 16:15:13 2015 +0100
@@ -0,0 +1,229 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         nvic_wrapper.c
+* $Rev:  $
+* $Date:: $
+* @brief        Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9)
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "MBRZA1H.h"
+#include "wdt_iodefine.h"
+#include "nvic_wrapper.h"
+#include "gic.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define PRIO_BITS            (7)   /* Set binary point to 0 in gic.c */
+#define WDT_WTCNT_WRITE      (0x5A00)
+#define WDT_WTCSR_WRITE      (0xA500)
+#define WDT_WRCSR_WOVF_WRITE (0xA500)
+#define WDT_WRCSR_RSTE_WRITE (0x5A00)
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    GIC_SetBinaryPoint(PriorityGroup);
+}
+
+
+uint32_t NVIC_GetPriorityGrouping(void)
+{
+    return GIC_GetBinaryPoint(0);
+}
+
+
+void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    GIC_EnableIRQ(IRQn);
+}
+
+
+void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    GIC_DisableIRQ(IRQn);
+}
+
+
+uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    uint32_t pending;
+    
+    pending = GIC_GetIRQStatus(IRQn);
+    pending = (pending & 0x00000001);
+    
+    return pending;
+}
+
+
+void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    GIC_SetPendingIRQ(IRQn);
+}
+
+
+void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    GIC_ClearPendingIRQ(IRQn);
+}
+
+
+uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+    uint32_t active;
+    
+    active = GIC_GetIRQStatus(IRQn);
+    active = ((active >> 1) & 0x00000001);
+    
+    return active;
+}
+
+
+void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    GIC_SetPriority(IRQn, (priority << 3));
+}
+
+
+uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+    uint32_t priority_field;
+    
+    priority_field = GIC_GetPriority(IRQn);
+    priority_field = (priority_field >> 3);
+    return priority_field;
+}
+
+
+uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS;
+
+    return (
+             ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+             ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+           );
+}
+
+
+void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS;
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+    *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+void NVIC_SystemReset(void)
+{
+    uint16_t reg;
+    uint8_t  dummy_read;
+    /* Use Watch Dog Timer to system reset */
+    
+    /* Set WT/IT bit of WTCSR to 1 = Watch Dog */
+    /* CLK = 000, 1xP0phi(=33.3333MHz) = 7.7us */
+    reg = (WDT_WTCSR_WRITE | 0x0058);
+    WDTWTCSR = reg;
+    
+    /* Clear Count reg */
+    reg = (WDT_WTCNT_WRITE | 0x0000);
+    WDTWTCNT = reg;
+    
+    /* Clear WOVF flag */
+    dummy_read = WDTWRCSR;
+    reg = (WDT_WRCSR_WOVF_WRITE | (dummy_read & 0x0000));
+    WDTWRCSR = reg;
+    /* Enable Internal Reset */
+    reg = (WDT_WRCSR_RSTE_WRITE | 0x005F);
+    WDTWRCSR = reg;
+    
+    /* Watch Dog start */
+    reg = (WDT_WTCSR_WRITE | 0x0078);
+    WDTWTCSR = reg;
+    
+    while(1);                      /* wait Internal Reset */
+}
+
+/* ##################################    SysTick function  ############################################ */
+uint32_t SysTick_Config(uint32_t ticks)
+{
+    /* Not support this function */
+    /* Use mbed Ticker */
+    return (1);     /* impossible */
+}
+
+
+/* ##################################### Debug In/Output function ########################################### */
+uint32_t ITM_SendChar (uint32_t ch)
+{
+    /* Not support this function */
+    /* Use mbed Serial */
+    return (ch);
+}
+
+
+int32_t ITM_ReceiveChar (void) {
+    /* Not support this function */
+    /* Use mbed Serial */
+    return (-1);    /* no character available */
+}
+
+
+int32_t ITM_CheckChar (void) {
+    /* Not support this function */
+    /* Use mbed Serial */
+    return (0);                                 /* no character available */
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.h	Tue Mar 31 16:15:13 2015 +0100
@@ -0,0 +1,84 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         nvic_wrapper.h
+* $Rev:  $
+* $Date:: $
+* @brief        Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9)
+******************************************************************************/
+
+#ifndef NVIC_WRAPPER_H
+#define NVIC_WRAPPER_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/* NVIC functions */
+void     NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+uint32_t NVIC_GetPriorityGrouping(void);
+void     NVIC_EnableIRQ(IRQn_Type IRQn);
+void     NVIC_DisableIRQ(IRQn_Type IRQn);
+uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void     NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void     NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t NVIC_GetActive(IRQn_Type IRQn);
+void     NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
+uint32_t NVIC_GetPriority(IRQn_Type IRQn);
+uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority);
+void     NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+void     NVIC_SystemReset(void);
+/* SysTick function */
+uint32_t SysTick_Config(uint32_t ticks);
+/* Debug In/Output function */
+uint32_t ITM_SendChar (uint32_t ch);
+int32_t  ITM_ReceiveChar (void);
+int32_t  ITM_CheckChar (void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* NVIC_WRAPPER_H */

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h	Sat Mar 28 08:15:07 2015 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h	Tue Mar 31 16:15:13 2015 +0100
@@ -68,6 +68,7 @@
     PWM10_PIN,
     PWM11_PIN,
     PWM12_PIN,
+    PWM13_PIN,
 } PWMName;
 
 typedef enum {
@@ -99,35 +100,6 @@
 #define STDIO_UART_RX     USBRX
 #define STDIO_UART        UART2
 
-// Default peripherals
-#define MBED_SPI0         p5, p6, p7, p8
-#define MBED_SPI1         p11, p12, p13, p14
-
-#define MBED_UART0        p9, p10
-#define MBED_UART1        p13, p14
-#define MBED_UART2        p28, p27
-#define MBED_UARTUSB      USBTX, USBRX
-
-#define MBED_I2C0         p28, p27
-#define MBED_I2C1         p9, p10
-
-#define MBED_CAN0         p30, p29
-
-#define MBED_ANALOGOUT0   p18
-
-#define MBED_ANALOGIN0    p15
-#define MBED_ANALOGIN1    p16
-#define MBED_ANALOGIN2    p17
-#define MBED_ANALOGIN3    p18
-#define MBED_ANALOGIN4    p19
-#define MBED_ANALOGIN5    p20
-
-#define MBED_PWMOUT0      p26
-#define MBED_PWMOUT1      p25
-#define MBED_PWMOUT2      p24
-#define MBED_PWMOUT3      p23
-#define MBED_PWMOUT4      p22
-#define MBED_PWMOUT5      p21
 
 
 #ifdef __cplusplus

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h	Sat Mar 28 08:15:07 2015 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h	Tue Mar 31 16:15:13 2015 +0100
@@ -44,22 +44,11 @@
     P10_0,P10_1,P10_2,P10_3,P10_4,P10_5,P10_6,P10_7,P10_8,P10_9,P10_10,P10_11,P10_12,P10_13,P10_14,P10_15,
     P11_0,P11_1,P11_2,P11_3,P11_4,P11_5,P11_6,P11_7,P11_8,P11_9,P11_10,P11_11,P11_12,P11_13,P11_14,P11_15, 
 
-    // mbed DIP Pin Names
-    p10 = P0_1,
-    p21 = P2_5,
-    p22 = P2_4,
-    p23 = P2_3,
-    p24 = P2_2,
-    p25 = P2_1,
-    p26 = P2_0,
-    p29 = P0_5,
-    p30 = P0_4,
-
-    // Other mbed Pin Names
-    LED1 = P4_4,
-    LED2 = P3_2,
-    LED3 = P4_6,
-    LED4 = P4_7,
+    // mbed Pin Names
+    LED1 = P6_13,
+    LED2 = P6_14,
+    LED3 = P6_15,
+    LED4 = P6_12,
 
     LED_RED  = LED1,
     LED_GREEN= LED2,
@@ -72,12 +61,12 @@
     // Arduiono Pin Names
     D0 = P2_15,
     D1 = P2_14,
-    D2 = P11_15,
-    D3 = P11_14,
-    D4 = P11_13,
-    D5 = P11_12,
-    D6 = P8_11,
-    D7 = P8_13,
+    D2 = P4_7,
+    D3 = P4_6,
+    D4 = P4_5,
+    D5 = P4_4,
+    D6 = P8_13,
+    D7 = P8_11,
     D8 = P8_15,
     D9 = P8_14,
     D10 = P10_13,
@@ -98,7 +87,6 @@
     I2C_SDA = D14,
 
     USER_BUTTON0 = P6_0,
-    USER_BUTTON1 = P6_1,
 
     // Not connected
     NC = (int)0xFFFFFFFF

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c	Sat Mar 28 08:15:07 2015 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c	Tue Mar 31 16:15:13 2015 +0100
@@ -33,21 +33,25 @@
     group = PINGROUP(pin);
     if (group > 11) return;
 
-    obj->reg_set = (volatile uint32_t *)PORT(group);
+    obj->reg_set = (volatile uint32_t *) PSR(group);
     obj->reg_in  = (volatile uint32_t *) PPR(group);
-    obj->reg_dir = (volatile uint32_t *)  PM(group);
+    obj->reg_dir = (volatile uint32_t *)PMSR(group);
     obj->reg_buf = (volatile uint32_t *)PIBC(group);
 }
 
 void gpio_mode(gpio_t *obj, PinMode mode) {
-// pullup, pulldown, open...etc
+/* Pull up and Pull down settings aren't supported because RZ/A1H doesn't have pull up/down for pins(signals). */
 }
 
 void gpio_dir(gpio_t *obj, PinDirection direction) {
     switch (direction) {
-        case PIN_INPUT : *obj->reg_dir |=  obj->mask;
-                         *obj->reg_buf |=  obj->mask; break;
-        case PIN_OUTPUT: *obj->reg_dir &= ~obj->mask; 
-                         *obj->reg_buf &= ~obj->mask; break;
+        case PIN_INPUT :
+            *obj->reg_dir = (obj->mask << 16) | obj->mask;
+            *obj->reg_buf |=  obj->mask;
+            break;
+        case PIN_OUTPUT:
+            *obj->reg_dir = (obj->mask << 16) | 0;
+            *obj->reg_buf &= ~obj->mask;
+            break;
     }
 }

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h	Sat Mar 28 08:15:07 2015 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h	Tue Mar 31 16:15:13 2015 +0100
@@ -33,10 +33,7 @@
 } gpio_t;
 
 static inline void gpio_write(gpio_t *obj, int value) {
-    if (value)
-        *obj->reg_set |= obj->mask;
-    else
-        *obj->reg_set &= ~obj->mask;
+    *obj->reg_set = (obj->mask << 16) | ((value != 0) ? obj->mask : 0);
 }
 
 static inline int gpio_read(gpio_t *obj) {

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c	Sat Mar 28 08:15:07 2015 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c	Tue Mar 31 16:15:13 2015 +0100
@@ -36,6 +36,7 @@
     {P8_12    , PWM10_PIN, 6},
     {P8_9     , PWM11_PIN, 6},
     {P8_10    , PWM12_PIN, 6},
+    {P4_5     , PWM13_PIN, 4},
     {NC, NC, 0}
 };
 
@@ -53,6 +54,7 @@
      PWM1E,          // PWM10_PIN
      PWM1B,          // PWM11_PIN
      PWM1C,          // PWM12_PIN
+     PWM2F,          // PWM13_PIN
 };
 
 static __IO uint16_t *PWM_MATCH[] = {
@@ -69,6 +71,7 @@
     &PWMPWBFR_1E,    // PWM10_PIN
     &PWMPWBFR_1A,    // PWM11_PIN
     &PWMPWBFR_1C,    // PWM12_PIN
+    &PWMPWBFR_2E,    // PWM13_PIN
 };
 
 static uint16_t init_period_ch1 = 0;

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c	Sat Mar 28 08:15:07 2015 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c	Tue Mar 31 16:15:13 2015 +0100
@@ -56,7 +56,9 @@
 static const PinMap PinMap_UART_TX[] = {
     {P2_14 , UART0, 6},
     {P2_5  , UART1, 6},
+    {P4_12 , UART1, 7},
     {P6_3  , UART2, 7},
+    {P4_14 , UART2, 7},
     {P5_3  , UART3, 5},
     {P8_8  , UART3, 7},
     {P5_0  , UART4, 5},
@@ -73,7 +75,9 @@
 static const PinMap PinMap_UART_RX[] = {
     {P2_15 , UART0, 6},
     {P2_6  , UART1, 6},
+    {P4_13 , UART1, 7},
     {P6_2  , UART2, 7},
+    {P4_15 , UART2, 7},
     {P5_4  , UART3, 5},
     {P8_9  , UART3, 7},
     {P5_1  , UART4, 5},

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c	Sat Mar 28 08:15:07 2015 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c	Tue Mar 31 16:15:13 2015 +0100
@@ -24,6 +24,7 @@
 
 static const PinMap PinMap_SPI_SCLK[] = {
     {P10_12, SPI_0, 4},
+    {P4_4  , SPI_1, 2},
     {P11_12, SPI_1, 2},
     {P8_3  , SPI_2, 3},
     {NC    , NC   , 0}
@@ -31,6 +32,7 @@
 
 static const PinMap PinMap_SPI_SSEL[] = {
     {P10_13, SPI_0, 4},
+    {P4_5  , SPI_1, 2},
     {P11_13, SPI_1, 2},
     {P8_4  , SPI_2, 3},
     {NC    , NC   , 0}
@@ -38,6 +40,7 @@
 
 static const PinMap PinMap_SPI_MOSI[] = {
     {P10_14, SPI_0, 4},
+    {P4_6  , SPI_1, 2},
     {P11_14, SPI_1, 2},
     {P8_5  , SPI_2, 3},
     {NC    , NC   , 0}
@@ -45,6 +48,7 @@
 
 static const PinMap PinMap_SPI_MISO[] = {
     {P10_15, SPI_0, 4},
+    {P4_7  , SPI_1, 2},
     {P11_15, SPI_1, 2},
     {P8_6  , SPI_2, 3},
     {NC    , NC   , 0}