I had the privilege of picking up an MBED over the Christmas holiday and
I just had some basic questions.

Specifically, I was just wondering if anyone had documentation that listed
the # of expected clock cycles for basic commands (such as toggling a
digital output line, etc.).

Unfortunately, I don't have access to an o-scope over the holiday... so I was
using the timer system to gauge how fast different operations were running.

One of the experiments I'm doing is measuring the time it takes to toggle a
digitalout pin a certain # of times (with the timer).  As I increase the # of
toggles (whether I use a loop or just discretely type in more toggles) the
effective frequency increases (which I can believe).  I'm just wondering
what the actual upper limit should be on things like this.

Thanks!

 

Thanks!

So I finally got to check some of the things I was curious about
with an oscilloscope... and I just wanted to verify that what I was
seeing made sense.

First:
I can only toggle a DigitalOut signal @ approximately 1.6MHz with
the following code:

DigitalOut sig(p5);

int main() {

     sig = 0;
     sig = 1;   
     sig = 0;
     sig = 1;

}

Second:
I can toggle a DigitalOut signal @ ~715KHz with this code:

DigitalOut sig(p5);

int main() {

     sig = 0;

     while (1) {
          sig = !sig;
     }
}

Third:
When using the BusOut library, the signals making up the Bus
don't transition at the same time:

-----------------------------

BusOut Bus_Signals(p5, p6, p7, p8);

int main() {

     while(1) {
          for(int i=0; i<16; i++) {
               Bus_Signals = i;
          }
     }
}

For example, when going from 15->0, one by one, the signals will fall back to
0, ~312ns between p5 and p6, ~624ns between p5 and p7, etc.
By the way, it appears that the LSB of this bus will only run ~155KHz.

I was just wanting some feedback as to whether all of this makes sense or
if it seems slow.  My first example is running at 1.6MHz.  If my math is correct,
that would mean each toggle of the DigitalOut signal takes 30 clocks.

Thanks!

Hi Tyler,

Thanks for posting the results! This all looks about right.

If you're interested, it might be nice if you could wrap the tests up in to more of a self-test "benchmark", as we'll look to optimise the library implementations sometime and it'd be interesting to see the speed-ups we can get; currently there is quite an internal call heirachy and no inlining or optimisation whilst we're experimenting on portability across different architectures, and that makes it slow, but we should be able to speed it up when we're happy how it should work.

The BusIn/Out is totally abstract; just an array of DigitalIn/Outs, so certainly wont be fast or simultaneous transitions; it is meant as a convenient way to make up an arbitrary bus out of pins, rather than map to an internal "port". Good for hoovering up left over pins, wherever they may lie.

Simon

Thanks for the info!

I was planning on trying to put together a little benchmark/characterization suite
that I could run.  I'll throw together a notebook entry when I have something of a
little more substance.

Tyler