雄介 太田 / mbed

mbed(SerialHalfDuplex入り)

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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_ftm.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_FTM_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_FTM_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 FTM
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * FlexTimer Module
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_FTM_SC - Status And Control
bogdanm 82:6473597d706e 33 * - HW_FTM_CNT - Counter
bogdanm 82:6473597d706e 34 * - HW_FTM_MOD - Modulo
bogdanm 82:6473597d706e 35 * - HW_FTM_CnSC - Channel (n) Status And Control
bogdanm 82:6473597d706e 36 * - HW_FTM_CnV - Channel (n) Value
bogdanm 82:6473597d706e 37 * - HW_FTM_CNTIN - Counter Initial Value
bogdanm 82:6473597d706e 38 * - HW_FTM_STATUS - Capture And Compare Status
bogdanm 82:6473597d706e 39 * - HW_FTM_MODE - Features Mode Selection
bogdanm 82:6473597d706e 40 * - HW_FTM_SYNC - Synchronization
bogdanm 82:6473597d706e 41 * - HW_FTM_OUTINIT - Initial State For Channels Output
bogdanm 82:6473597d706e 42 * - HW_FTM_OUTMASK - Output Mask
bogdanm 82:6473597d706e 43 * - HW_FTM_COMBINE - Function For Linked Channels
bogdanm 82:6473597d706e 44 * - HW_FTM_DEADTIME - Deadtime Insertion Control
bogdanm 82:6473597d706e 45 * - HW_FTM_EXTTRIG - FTM External Trigger
bogdanm 82:6473597d706e 46 * - HW_FTM_POL - Channels Polarity
bogdanm 82:6473597d706e 47 * - HW_FTM_FMS - Fault Mode Status
bogdanm 82:6473597d706e 48 * - HW_FTM_FILTER - Input Capture Filter Control
bogdanm 82:6473597d706e 49 * - HW_FTM_FLTCTRL - Fault Control
bogdanm 82:6473597d706e 50 * - HW_FTM_QDCTRL - Quadrature Decoder Control And Status
bogdanm 82:6473597d706e 51 * - HW_FTM_CONF - Configuration
bogdanm 82:6473597d706e 52 * - HW_FTM_FLTPOL - FTM Fault Input Polarity
bogdanm 82:6473597d706e 53 * - HW_FTM_SYNCONF - Synchronization Configuration
bogdanm 82:6473597d706e 54 * - HW_FTM_INVCTRL - FTM Inverting Control
bogdanm 82:6473597d706e 55 * - HW_FTM_SWOCTRL - FTM Software Output Control
bogdanm 82:6473597d706e 56 * - HW_FTM_PWMLOAD - FTM PWM Load
bogdanm 82:6473597d706e 57 *
bogdanm 82:6473597d706e 58 * - hw_ftm_t - Struct containing all module registers.
bogdanm 82:6473597d706e 59 */
bogdanm 82:6473597d706e 60
bogdanm 82:6473597d706e 61 //! @name Module base addresses
bogdanm 82:6473597d706e 62 //@{
bogdanm 82:6473597d706e 63 #ifndef REGS_FTM_BASE
bogdanm 82:6473597d706e 64 #define HW_FTM_INSTANCE_COUNT (4U) //!< Number of instances of the FTM module.
bogdanm 82:6473597d706e 65 #define HW_FTM0 (0U) //!< Instance number for FTM0.
bogdanm 82:6473597d706e 66 #define HW_FTM1 (1U) //!< Instance number for FTM1.
bogdanm 82:6473597d706e 67 #define HW_FTM2 (2U) //!< Instance number for FTM2.
bogdanm 82:6473597d706e 68 #define HW_FTM3 (3U) //!< Instance number for FTM3.
bogdanm 82:6473597d706e 69 #define REGS_FTM0_BASE (0x40038000U) //!< Base address for FTM0.
bogdanm 82:6473597d706e 70 #define REGS_FTM1_BASE (0x40039000U) //!< Base address for FTM1.
bogdanm 82:6473597d706e 71 #define REGS_FTM2_BASE (0x4003A000U) //!< Base address for FTM2.
bogdanm 82:6473597d706e 72 #define REGS_FTM3_BASE (0x400B9000U) //!< Base address for FTM3.
bogdanm 82:6473597d706e 73
bogdanm 82:6473597d706e 74 //! @brief Table of base addresses for FTM instances.
bogdanm 82:6473597d706e 75 static const uint32_t __g_regs_FTM_base_addresses[] = {
bogdanm 82:6473597d706e 76 REGS_FTM0_BASE,
bogdanm 82:6473597d706e 77 REGS_FTM1_BASE,
bogdanm 82:6473597d706e 78 REGS_FTM2_BASE,
bogdanm 82:6473597d706e 79 REGS_FTM3_BASE,
bogdanm 82:6473597d706e 80 };
bogdanm 82:6473597d706e 81
bogdanm 82:6473597d706e 82 //! @brief Get the base address of FTM by instance number.
bogdanm 82:6473597d706e 83 //! @param x FTM instance number, from 0 through 3.
bogdanm 82:6473597d706e 84 #define REGS_FTM_BASE(x) (__g_regs_FTM_base_addresses[(x)])
bogdanm 82:6473597d706e 85
bogdanm 82:6473597d706e 86 //! @brief Get the instance number given a base address.
bogdanm 82:6473597d706e 87 //! @param b Base address for an instance of FTM.
bogdanm 82:6473597d706e 88 #define REGS_FTM_INSTANCE(b) ((b) == REGS_FTM0_BASE ? HW_FTM0 : (b) == REGS_FTM1_BASE ? HW_FTM1 : (b) == REGS_FTM2_BASE ? HW_FTM2 : (b) == REGS_FTM3_BASE ? HW_FTM3 : 0)
bogdanm 82:6473597d706e 89 #endif
bogdanm 82:6473597d706e 90 //@}
bogdanm 82:6473597d706e 91
bogdanm 82:6473597d706e 92 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 93 // HW_FTM_SC - Status And Control
bogdanm 82:6473597d706e 94 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 95
bogdanm 82:6473597d706e 96 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 97 /*!
bogdanm 82:6473597d706e 98 * @brief HW_FTM_SC - Status And Control (RW)
bogdanm 82:6473597d706e 99 *
bogdanm 82:6473597d706e 100 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 101 *
bogdanm 82:6473597d706e 102 * SC contains the overflow status flag and control bits used to configure the
bogdanm 82:6473597d706e 103 * interrupt enable, FTM configuration, clock source, and prescaler factor. These
bogdanm 82:6473597d706e 104 * controls relate to all channels within this module.
bogdanm 82:6473597d706e 105 */
bogdanm 82:6473597d706e 106 typedef union _hw_ftm_sc
bogdanm 82:6473597d706e 107 {
bogdanm 82:6473597d706e 108 uint32_t U;
bogdanm 82:6473597d706e 109 struct _hw_ftm_sc_bitfields
bogdanm 82:6473597d706e 110 {
bogdanm 82:6473597d706e 111 uint32_t PS : 3; //!< [2:0] Prescale Factor Selection
bogdanm 82:6473597d706e 112 uint32_t CLKS : 2; //!< [4:3] Clock Source Selection
bogdanm 82:6473597d706e 113 uint32_t CPWMS : 1; //!< [5] Center-Aligned PWM Select
bogdanm 82:6473597d706e 114 uint32_t TOIE : 1; //!< [6] Timer Overflow Interrupt Enable
bogdanm 82:6473597d706e 115 uint32_t TOF : 1; //!< [7] Timer Overflow Flag
bogdanm 82:6473597d706e 116 uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm 82:6473597d706e 117 } B;
bogdanm 82:6473597d706e 118 } hw_ftm_sc_t;
bogdanm 82:6473597d706e 119 #endif
bogdanm 82:6473597d706e 120
bogdanm 82:6473597d706e 121 /*!
bogdanm 82:6473597d706e 122 * @name Constants and macros for entire FTM_SC register
bogdanm 82:6473597d706e 123 */
bogdanm 82:6473597d706e 124 //@{
bogdanm 82:6473597d706e 125 #define HW_FTM_SC_ADDR(x) (REGS_FTM_BASE(x) + 0x0U)
bogdanm 82:6473597d706e 126
bogdanm 82:6473597d706e 127 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 128 #define HW_FTM_SC(x) (*(__IO hw_ftm_sc_t *) HW_FTM_SC_ADDR(x))
bogdanm 82:6473597d706e 129 #define HW_FTM_SC_RD(x) (HW_FTM_SC(x).U)
bogdanm 82:6473597d706e 130 #define HW_FTM_SC_WR(x, v) (HW_FTM_SC(x).U = (v))
bogdanm 82:6473597d706e 131 #define HW_FTM_SC_SET(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) | (v)))
bogdanm 82:6473597d706e 132 #define HW_FTM_SC_CLR(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) & ~(v)))
bogdanm 82:6473597d706e 133 #define HW_FTM_SC_TOG(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) ^ (v)))
bogdanm 82:6473597d706e 134 #endif
bogdanm 82:6473597d706e 135 //@}
bogdanm 82:6473597d706e 136
bogdanm 82:6473597d706e 137 /*
bogdanm 82:6473597d706e 138 * Constants & macros for individual FTM_SC bitfields
bogdanm 82:6473597d706e 139 */
bogdanm 82:6473597d706e 140
bogdanm 82:6473597d706e 141 /*!
bogdanm 82:6473597d706e 142 * @name Register FTM_SC, field PS[2:0] (RW)
bogdanm 82:6473597d706e 143 *
bogdanm 82:6473597d706e 144 * Selects one of 8 division factors for the clock source selected by CLKS. The
bogdanm 82:6473597d706e 145 * new prescaler factor affects the clock source on the next system clock cycle
bogdanm 82:6473597d706e 146 * after the new value is updated into the register bits. This field is write
bogdanm 82:6473597d706e 147 * protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 148 *
bogdanm 82:6473597d706e 149 * Values:
bogdanm 82:6473597d706e 150 * - 000 - Divide by 1
bogdanm 82:6473597d706e 151 * - 001 - Divide by 2
bogdanm 82:6473597d706e 152 * - 010 - Divide by 4
bogdanm 82:6473597d706e 153 * - 011 - Divide by 8
bogdanm 82:6473597d706e 154 * - 100 - Divide by 16
bogdanm 82:6473597d706e 155 * - 101 - Divide by 32
bogdanm 82:6473597d706e 156 * - 110 - Divide by 64
bogdanm 82:6473597d706e 157 * - 111 - Divide by 128
bogdanm 82:6473597d706e 158 */
bogdanm 82:6473597d706e 159 //@{
bogdanm 82:6473597d706e 160 #define BP_FTM_SC_PS (0U) //!< Bit position for FTM_SC_PS.
bogdanm 82:6473597d706e 161 #define BM_FTM_SC_PS (0x00000007U) //!< Bit mask for FTM_SC_PS.
bogdanm 82:6473597d706e 162 #define BS_FTM_SC_PS (3U) //!< Bit field size in bits for FTM_SC_PS.
bogdanm 82:6473597d706e 163
bogdanm 82:6473597d706e 164 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 165 //! @brief Read current value of the FTM_SC_PS field.
bogdanm 82:6473597d706e 166 #define BR_FTM_SC_PS(x) (HW_FTM_SC(x).B.PS)
bogdanm 82:6473597d706e 167 #endif
bogdanm 82:6473597d706e 168
bogdanm 82:6473597d706e 169 //! @brief Format value for bitfield FTM_SC_PS.
bogdanm 82:6473597d706e 170 #define BF_FTM_SC_PS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_PS), uint32_t) & BM_FTM_SC_PS)
bogdanm 82:6473597d706e 171
bogdanm 82:6473597d706e 172 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 173 //! @brief Set the PS field to a new value.
bogdanm 82:6473597d706e 174 #define BW_FTM_SC_PS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_PS) | BF_FTM_SC_PS(v)))
bogdanm 82:6473597d706e 175 #endif
bogdanm 82:6473597d706e 176 //@}
bogdanm 82:6473597d706e 177
bogdanm 82:6473597d706e 178 /*!
bogdanm 82:6473597d706e 179 * @name Register FTM_SC, field CLKS[4:3] (RW)
bogdanm 82:6473597d706e 180 *
bogdanm 82:6473597d706e 181 * Selects one of the three FTM counter clock sources. This field is write
bogdanm 82:6473597d706e 182 * protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 183 *
bogdanm 82:6473597d706e 184 * Values:
bogdanm 82:6473597d706e 185 * - 00 - No clock selected. This in effect disables the FTM counter.
bogdanm 82:6473597d706e 186 * - 01 - System clock
bogdanm 82:6473597d706e 187 * - 10 - Fixed frequency clock
bogdanm 82:6473597d706e 188 * - 11 - External clock
bogdanm 82:6473597d706e 189 */
bogdanm 82:6473597d706e 190 //@{
bogdanm 82:6473597d706e 191 #define BP_FTM_SC_CLKS (3U) //!< Bit position for FTM_SC_CLKS.
bogdanm 82:6473597d706e 192 #define BM_FTM_SC_CLKS (0x00000018U) //!< Bit mask for FTM_SC_CLKS.
bogdanm 82:6473597d706e 193 #define BS_FTM_SC_CLKS (2U) //!< Bit field size in bits for FTM_SC_CLKS.
bogdanm 82:6473597d706e 194
bogdanm 82:6473597d706e 195 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 196 //! @brief Read current value of the FTM_SC_CLKS field.
bogdanm 82:6473597d706e 197 #define BR_FTM_SC_CLKS(x) (HW_FTM_SC(x).B.CLKS)
bogdanm 82:6473597d706e 198 #endif
bogdanm 82:6473597d706e 199
bogdanm 82:6473597d706e 200 //! @brief Format value for bitfield FTM_SC_CLKS.
bogdanm 82:6473597d706e 201 #define BF_FTM_SC_CLKS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_CLKS), uint32_t) & BM_FTM_SC_CLKS)
bogdanm 82:6473597d706e 202
bogdanm 82:6473597d706e 203 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 204 //! @brief Set the CLKS field to a new value.
bogdanm 82:6473597d706e 205 #define BW_FTM_SC_CLKS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_CLKS) | BF_FTM_SC_CLKS(v)))
bogdanm 82:6473597d706e 206 #endif
bogdanm 82:6473597d706e 207 //@}
bogdanm 82:6473597d706e 208
bogdanm 82:6473597d706e 209 /*!
bogdanm 82:6473597d706e 210 * @name Register FTM_SC, field CPWMS[5] (RW)
bogdanm 82:6473597d706e 211 *
bogdanm 82:6473597d706e 212 * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
bogdanm 82:6473597d706e 213 * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
bogdanm 82:6473597d706e 214 * = 1.
bogdanm 82:6473597d706e 215 *
bogdanm 82:6473597d706e 216 * Values:
bogdanm 82:6473597d706e 217 * - 0 - FTM counter operates in Up Counting mode.
bogdanm 82:6473597d706e 218 * - 1 - FTM counter operates in Up-Down Counting mode.
bogdanm 82:6473597d706e 219 */
bogdanm 82:6473597d706e 220 //@{
bogdanm 82:6473597d706e 221 #define BP_FTM_SC_CPWMS (5U) //!< Bit position for FTM_SC_CPWMS.
bogdanm 82:6473597d706e 222 #define BM_FTM_SC_CPWMS (0x00000020U) //!< Bit mask for FTM_SC_CPWMS.
bogdanm 82:6473597d706e 223 #define BS_FTM_SC_CPWMS (1U) //!< Bit field size in bits for FTM_SC_CPWMS.
bogdanm 82:6473597d706e 224
bogdanm 82:6473597d706e 225 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 226 //! @brief Read current value of the FTM_SC_CPWMS field.
bogdanm 82:6473597d706e 227 #define BR_FTM_SC_CPWMS(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS))
bogdanm 82:6473597d706e 228 #endif
bogdanm 82:6473597d706e 229
bogdanm 82:6473597d706e 230 //! @brief Format value for bitfield FTM_SC_CPWMS.
bogdanm 82:6473597d706e 231 #define BF_FTM_SC_CPWMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_CPWMS), uint32_t) & BM_FTM_SC_CPWMS)
bogdanm 82:6473597d706e 232
bogdanm 82:6473597d706e 233 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 234 //! @brief Set the CPWMS field to a new value.
bogdanm 82:6473597d706e 235 #define BW_FTM_SC_CPWMS(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS) = (v))
bogdanm 82:6473597d706e 236 #endif
bogdanm 82:6473597d706e 237 //@}
bogdanm 82:6473597d706e 238
bogdanm 82:6473597d706e 239 /*!
bogdanm 82:6473597d706e 240 * @name Register FTM_SC, field TOIE[6] (RW)
bogdanm 82:6473597d706e 241 *
bogdanm 82:6473597d706e 242 * Enables FTM overflow interrupts.
bogdanm 82:6473597d706e 243 *
bogdanm 82:6473597d706e 244 * Values:
bogdanm 82:6473597d706e 245 * - 0 - Disable TOF interrupts. Use software polling.
bogdanm 82:6473597d706e 246 * - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
bogdanm 82:6473597d706e 247 */
bogdanm 82:6473597d706e 248 //@{
bogdanm 82:6473597d706e 249 #define BP_FTM_SC_TOIE (6U) //!< Bit position for FTM_SC_TOIE.
bogdanm 82:6473597d706e 250 #define BM_FTM_SC_TOIE (0x00000040U) //!< Bit mask for FTM_SC_TOIE.
bogdanm 82:6473597d706e 251 #define BS_FTM_SC_TOIE (1U) //!< Bit field size in bits for FTM_SC_TOIE.
bogdanm 82:6473597d706e 252
bogdanm 82:6473597d706e 253 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 254 //! @brief Read current value of the FTM_SC_TOIE field.
bogdanm 82:6473597d706e 255 #define BR_FTM_SC_TOIE(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE))
bogdanm 82:6473597d706e 256 #endif
bogdanm 82:6473597d706e 257
bogdanm 82:6473597d706e 258 //! @brief Format value for bitfield FTM_SC_TOIE.
bogdanm 82:6473597d706e 259 #define BF_FTM_SC_TOIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_TOIE), uint32_t) & BM_FTM_SC_TOIE)
bogdanm 82:6473597d706e 260
bogdanm 82:6473597d706e 261 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 262 //! @brief Set the TOIE field to a new value.
bogdanm 82:6473597d706e 263 #define BW_FTM_SC_TOIE(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE) = (v))
bogdanm 82:6473597d706e 264 #endif
bogdanm 82:6473597d706e 265 //@}
bogdanm 82:6473597d706e 266
bogdanm 82:6473597d706e 267 /*!
bogdanm 82:6473597d706e 268 * @name Register FTM_SC, field TOF[7] (ROWZ)
bogdanm 82:6473597d706e 269 *
bogdanm 82:6473597d706e 270 * Set by hardware when the FTM counter passes the value in the MOD register.
bogdanm 82:6473597d706e 271 * The TOF bit is cleared by reading the SC register while TOF is set and then
bogdanm 82:6473597d706e 272 * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
bogdanm 82:6473597d706e 273 * occurs between the read and write operations, the write operation has no
bogdanm 82:6473597d706e 274 * effect; therefore, TOF remains set indicating an overflow has occurred. In this
bogdanm 82:6473597d706e 275 * case, a TOF interrupt request is not lost due to the clearing sequence for a
bogdanm 82:6473597d706e 276 * previous TOF.
bogdanm 82:6473597d706e 277 *
bogdanm 82:6473597d706e 278 * Values:
bogdanm 82:6473597d706e 279 * - 0 - FTM counter has not overflowed.
bogdanm 82:6473597d706e 280 * - 1 - FTM counter has overflowed.
bogdanm 82:6473597d706e 281 */
bogdanm 82:6473597d706e 282 //@{
bogdanm 82:6473597d706e 283 #define BP_FTM_SC_TOF (7U) //!< Bit position for FTM_SC_TOF.
bogdanm 82:6473597d706e 284 #define BM_FTM_SC_TOF (0x00000080U) //!< Bit mask for FTM_SC_TOF.
bogdanm 82:6473597d706e 285 #define BS_FTM_SC_TOF (1U) //!< Bit field size in bits for FTM_SC_TOF.
bogdanm 82:6473597d706e 286
bogdanm 82:6473597d706e 287 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 288 //! @brief Read current value of the FTM_SC_TOF field.
bogdanm 82:6473597d706e 289 #define BR_FTM_SC_TOF(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF))
bogdanm 82:6473597d706e 290 #endif
bogdanm 82:6473597d706e 291 //@}
bogdanm 82:6473597d706e 292
bogdanm 82:6473597d706e 293 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 294 // HW_FTM_CNT - Counter
bogdanm 82:6473597d706e 295 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 296
bogdanm 82:6473597d706e 297 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 298 /*!
bogdanm 82:6473597d706e 299 * @brief HW_FTM_CNT - Counter (RW)
bogdanm 82:6473597d706e 300 *
bogdanm 82:6473597d706e 301 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 302 *
bogdanm 82:6473597d706e 303 * The CNT register contains the FTM counter value. Reset clears the CNT
bogdanm 82:6473597d706e 304 * register. Writing any value to COUNT updates the counter with its initial value,
bogdanm 82:6473597d706e 305 * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
bogdanm 82:6473597d706e 306 * may read.
bogdanm 82:6473597d706e 307 */
bogdanm 82:6473597d706e 308 typedef union _hw_ftm_cnt
bogdanm 82:6473597d706e 309 {
bogdanm 82:6473597d706e 310 uint32_t U;
bogdanm 82:6473597d706e 311 struct _hw_ftm_cnt_bitfields
bogdanm 82:6473597d706e 312 {
bogdanm 82:6473597d706e 313 uint32_t COUNT : 16; //!< [15:0] Counter Value
bogdanm 82:6473597d706e 314 uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm 82:6473597d706e 315 } B;
bogdanm 82:6473597d706e 316 } hw_ftm_cnt_t;
bogdanm 82:6473597d706e 317 #endif
bogdanm 82:6473597d706e 318
bogdanm 82:6473597d706e 319 /*!
bogdanm 82:6473597d706e 320 * @name Constants and macros for entire FTM_CNT register
bogdanm 82:6473597d706e 321 */
bogdanm 82:6473597d706e 322 //@{
bogdanm 82:6473597d706e 323 #define HW_FTM_CNT_ADDR(x) (REGS_FTM_BASE(x) + 0x4U)
bogdanm 82:6473597d706e 324
bogdanm 82:6473597d706e 325 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 326 #define HW_FTM_CNT(x) (*(__IO hw_ftm_cnt_t *) HW_FTM_CNT_ADDR(x))
bogdanm 82:6473597d706e 327 #define HW_FTM_CNT_RD(x) (HW_FTM_CNT(x).U)
bogdanm 82:6473597d706e 328 #define HW_FTM_CNT_WR(x, v) (HW_FTM_CNT(x).U = (v))
bogdanm 82:6473597d706e 329 #define HW_FTM_CNT_SET(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) | (v)))
bogdanm 82:6473597d706e 330 #define HW_FTM_CNT_CLR(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) & ~(v)))
bogdanm 82:6473597d706e 331 #define HW_FTM_CNT_TOG(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) ^ (v)))
bogdanm 82:6473597d706e 332 #endif
bogdanm 82:6473597d706e 333 //@}
bogdanm 82:6473597d706e 334
bogdanm 82:6473597d706e 335 /*
bogdanm 82:6473597d706e 336 * Constants & macros for individual FTM_CNT bitfields
bogdanm 82:6473597d706e 337 */
bogdanm 82:6473597d706e 338
bogdanm 82:6473597d706e 339 /*!
bogdanm 82:6473597d706e 340 * @name Register FTM_CNT, field COUNT[15:0] (RW)
bogdanm 82:6473597d706e 341 */
bogdanm 82:6473597d706e 342 //@{
bogdanm 82:6473597d706e 343 #define BP_FTM_CNT_COUNT (0U) //!< Bit position for FTM_CNT_COUNT.
bogdanm 82:6473597d706e 344 #define BM_FTM_CNT_COUNT (0x0000FFFFU) //!< Bit mask for FTM_CNT_COUNT.
bogdanm 82:6473597d706e 345 #define BS_FTM_CNT_COUNT (16U) //!< Bit field size in bits for FTM_CNT_COUNT.
bogdanm 82:6473597d706e 346
bogdanm 82:6473597d706e 347 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 348 //! @brief Read current value of the FTM_CNT_COUNT field.
bogdanm 82:6473597d706e 349 #define BR_FTM_CNT_COUNT(x) (HW_FTM_CNT(x).B.COUNT)
bogdanm 82:6473597d706e 350 #endif
bogdanm 82:6473597d706e 351
bogdanm 82:6473597d706e 352 //! @brief Format value for bitfield FTM_CNT_COUNT.
bogdanm 82:6473597d706e 353 #define BF_FTM_CNT_COUNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CNT_COUNT), uint32_t) & BM_FTM_CNT_COUNT)
bogdanm 82:6473597d706e 354
bogdanm 82:6473597d706e 355 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 356 //! @brief Set the COUNT field to a new value.
bogdanm 82:6473597d706e 357 #define BW_FTM_CNT_COUNT(x, v) (HW_FTM_CNT_WR(x, (HW_FTM_CNT_RD(x) & ~BM_FTM_CNT_COUNT) | BF_FTM_CNT_COUNT(v)))
bogdanm 82:6473597d706e 358 #endif
bogdanm 82:6473597d706e 359 //@}
bogdanm 82:6473597d706e 360
bogdanm 82:6473597d706e 361 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 362 // HW_FTM_MOD - Modulo
bogdanm 82:6473597d706e 363 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 364
bogdanm 82:6473597d706e 365 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 366 /*!
bogdanm 82:6473597d706e 367 * @brief HW_FTM_MOD - Modulo (RW)
bogdanm 82:6473597d706e 368 *
bogdanm 82:6473597d706e 369 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 370 *
bogdanm 82:6473597d706e 371 * The Modulo register contains the modulo value for the FTM counter. After the
bogdanm 82:6473597d706e 372 * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
bogdanm 82:6473597d706e 373 * the next clock, and the next value of FTM counter depends on the selected
bogdanm 82:6473597d706e 374 * counting method; see Counter. Writing to the MOD register latches the value into a
bogdanm 82:6473597d706e 375 * buffer. The MOD register is updated with the value of its write buffer
bogdanm 82:6473597d706e 376 * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
bogdanm 82:6473597d706e 377 * mechanism may be manually reset by writing to the SC register whether BDM is
bogdanm 82:6473597d706e 378 * active or not. Initialize the FTM counter, by writing to CNT, before writing
bogdanm 82:6473597d706e 379 * to the MOD register to avoid confusion about when the first counter overflow
bogdanm 82:6473597d706e 380 * will occur.
bogdanm 82:6473597d706e 381 */
bogdanm 82:6473597d706e 382 typedef union _hw_ftm_mod
bogdanm 82:6473597d706e 383 {
bogdanm 82:6473597d706e 384 uint32_t U;
bogdanm 82:6473597d706e 385 struct _hw_ftm_mod_bitfields
bogdanm 82:6473597d706e 386 {
bogdanm 82:6473597d706e 387 uint32_t MOD : 16; //!< [15:0]
bogdanm 82:6473597d706e 388 uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm 82:6473597d706e 389 } B;
bogdanm 82:6473597d706e 390 } hw_ftm_mod_t;
bogdanm 82:6473597d706e 391 #endif
bogdanm 82:6473597d706e 392
bogdanm 82:6473597d706e 393 /*!
bogdanm 82:6473597d706e 394 * @name Constants and macros for entire FTM_MOD register
bogdanm 82:6473597d706e 395 */
bogdanm 82:6473597d706e 396 //@{
bogdanm 82:6473597d706e 397 #define HW_FTM_MOD_ADDR(x) (REGS_FTM_BASE(x) + 0x8U)
bogdanm 82:6473597d706e 398
bogdanm 82:6473597d706e 399 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 400 #define HW_FTM_MOD(x) (*(__IO hw_ftm_mod_t *) HW_FTM_MOD_ADDR(x))
bogdanm 82:6473597d706e 401 #define HW_FTM_MOD_RD(x) (HW_FTM_MOD(x).U)
bogdanm 82:6473597d706e 402 #define HW_FTM_MOD_WR(x, v) (HW_FTM_MOD(x).U = (v))
bogdanm 82:6473597d706e 403 #define HW_FTM_MOD_SET(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) | (v)))
bogdanm 82:6473597d706e 404 #define HW_FTM_MOD_CLR(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) & ~(v)))
bogdanm 82:6473597d706e 405 #define HW_FTM_MOD_TOG(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) ^ (v)))
bogdanm 82:6473597d706e 406 #endif
bogdanm 82:6473597d706e 407 //@}
bogdanm 82:6473597d706e 408
bogdanm 82:6473597d706e 409 /*
bogdanm 82:6473597d706e 410 * Constants & macros for individual FTM_MOD bitfields
bogdanm 82:6473597d706e 411 */
bogdanm 82:6473597d706e 412
bogdanm 82:6473597d706e 413 /*!
bogdanm 82:6473597d706e 414 * @name Register FTM_MOD, field MOD[15:0] (RW)
bogdanm 82:6473597d706e 415 *
bogdanm 82:6473597d706e 416 * Modulo Value
bogdanm 82:6473597d706e 417 */
bogdanm 82:6473597d706e 418 //@{
bogdanm 82:6473597d706e 419 #define BP_FTM_MOD_MOD (0U) //!< Bit position for FTM_MOD_MOD.
bogdanm 82:6473597d706e 420 #define BM_FTM_MOD_MOD (0x0000FFFFU) //!< Bit mask for FTM_MOD_MOD.
bogdanm 82:6473597d706e 421 #define BS_FTM_MOD_MOD (16U) //!< Bit field size in bits for FTM_MOD_MOD.
bogdanm 82:6473597d706e 422
bogdanm 82:6473597d706e 423 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 424 //! @brief Read current value of the FTM_MOD_MOD field.
bogdanm 82:6473597d706e 425 #define BR_FTM_MOD_MOD(x) (HW_FTM_MOD(x).B.MOD)
bogdanm 82:6473597d706e 426 #endif
bogdanm 82:6473597d706e 427
bogdanm 82:6473597d706e 428 //! @brief Format value for bitfield FTM_MOD_MOD.
bogdanm 82:6473597d706e 429 #define BF_FTM_MOD_MOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MOD_MOD), uint32_t) & BM_FTM_MOD_MOD)
bogdanm 82:6473597d706e 430
bogdanm 82:6473597d706e 431 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 432 //! @brief Set the MOD field to a new value.
bogdanm 82:6473597d706e 433 #define BW_FTM_MOD_MOD(x, v) (HW_FTM_MOD_WR(x, (HW_FTM_MOD_RD(x) & ~BM_FTM_MOD_MOD) | BF_FTM_MOD_MOD(v)))
bogdanm 82:6473597d706e 434 #endif
bogdanm 82:6473597d706e 435 //@}
bogdanm 82:6473597d706e 436
bogdanm 82:6473597d706e 437 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 438 // HW_FTM_CnSC - Channel (n) Status And Control
bogdanm 82:6473597d706e 439 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 440
bogdanm 82:6473597d706e 441 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 442 /*!
bogdanm 82:6473597d706e 443 * @brief HW_FTM_CnSC - Channel (n) Status And Control (RW)
bogdanm 82:6473597d706e 444 *
bogdanm 82:6473597d706e 445 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 446 *
bogdanm 82:6473597d706e 447 * CnSC contains the channel-interrupt-status flag and control bits used to
bogdanm 82:6473597d706e 448 * configure the interrupt enable, channel configuration, and pin function. Mode,
bogdanm 82:6473597d706e 449 * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
bogdanm 82:6473597d706e 450 * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
bogdanm 82:6473597d706e 451 * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
bogdanm 82:6473597d706e 452 * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
bogdanm 82:6473597d706e 453 * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
bogdanm 82:6473597d706e 454 * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
bogdanm 82:6473597d706e 455 * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
bogdanm 82:6473597d706e 456 * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
bogdanm 82:6473597d706e 457 * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
bogdanm 82:6473597d706e 458 * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
bogdanm 82:6473597d706e 459 * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
bogdanm 82:6473597d706e 460 * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
bogdanm 82:6473597d706e 461 * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
bogdanm 82:6473597d706e 462 * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
bogdanm 82:6473597d706e 463 * Enabled Rising and falling edges
bogdanm 82:6473597d706e 464 */
bogdanm 82:6473597d706e 465 typedef union _hw_ftm_cnsc
bogdanm 82:6473597d706e 466 {
bogdanm 82:6473597d706e 467 uint32_t U;
bogdanm 82:6473597d706e 468 struct _hw_ftm_cnsc_bitfields
bogdanm 82:6473597d706e 469 {
bogdanm 82:6473597d706e 470 uint32_t DMAb : 1; //!< [0] DMA Enable
bogdanm 82:6473597d706e 471 uint32_t RESERVED0 : 1; //!< [1]
bogdanm 82:6473597d706e 472 uint32_t ELSA : 1; //!< [2] Edge or Level Select
bogdanm 82:6473597d706e 473 uint32_t ELSB : 1; //!< [3] Edge or Level Select
bogdanm 82:6473597d706e 474 uint32_t MSA : 1; //!< [4] Channel Mode Select
bogdanm 82:6473597d706e 475 uint32_t MSB : 1; //!< [5] Channel Mode Select
bogdanm 82:6473597d706e 476 uint32_t CHIE : 1; //!< [6] Channel Interrupt Enable
bogdanm 82:6473597d706e 477 uint32_t CHF : 1; //!< [7] Channel Flag
bogdanm 82:6473597d706e 478 uint32_t RESERVED1 : 24; //!< [31:8]
bogdanm 82:6473597d706e 479 } B;
bogdanm 82:6473597d706e 480 } hw_ftm_cnsc_t;
bogdanm 82:6473597d706e 481 #endif
bogdanm 82:6473597d706e 482
bogdanm 82:6473597d706e 483 /*!
bogdanm 82:6473597d706e 484 * @name Constants and macros for entire FTM_CnSC register
bogdanm 82:6473597d706e 485 */
bogdanm 82:6473597d706e 486 //@{
bogdanm 82:6473597d706e 487 #define HW_FTM_CnSC_COUNT (8U)
bogdanm 82:6473597d706e 488
bogdanm 82:6473597d706e 489 #define HW_FTM_CnSC_ADDR(x, n) (REGS_FTM_BASE(x) + 0xCU + (0x8U * n))
bogdanm 82:6473597d706e 490
bogdanm 82:6473597d706e 491 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 492 #define HW_FTM_CnSC(x, n) (*(__IO hw_ftm_cnsc_t *) HW_FTM_CnSC_ADDR(x, n))
bogdanm 82:6473597d706e 493 #define HW_FTM_CnSC_RD(x, n) (HW_FTM_CnSC(x, n).U)
bogdanm 82:6473597d706e 494 #define HW_FTM_CnSC_WR(x, n, v) (HW_FTM_CnSC(x, n).U = (v))
bogdanm 82:6473597d706e 495 #define HW_FTM_CnSC_SET(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) | (v)))
bogdanm 82:6473597d706e 496 #define HW_FTM_CnSC_CLR(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) & ~(v)))
bogdanm 82:6473597d706e 497 #define HW_FTM_CnSC_TOG(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) ^ (v)))
bogdanm 82:6473597d706e 498 #endif
bogdanm 82:6473597d706e 499 //@}
bogdanm 82:6473597d706e 500
bogdanm 82:6473597d706e 501 /*
bogdanm 82:6473597d706e 502 * Constants & macros for individual FTM_CnSC bitfields
bogdanm 82:6473597d706e 503 */
bogdanm 82:6473597d706e 504
bogdanm 82:6473597d706e 505 /*!
bogdanm 82:6473597d706e 506 * @name Register FTM_CnSC, field DMA[0] (RW)
bogdanm 82:6473597d706e 507 *
bogdanm 82:6473597d706e 508 * Enables DMA transfers for the channel.
bogdanm 82:6473597d706e 509 *
bogdanm 82:6473597d706e 510 * Values:
bogdanm 82:6473597d706e 511 * - 0 - Disable DMA transfers.
bogdanm 82:6473597d706e 512 * - 1 - Enable DMA transfers.
bogdanm 82:6473597d706e 513 */
bogdanm 82:6473597d706e 514 //@{
bogdanm 82:6473597d706e 515 #define BP_FTM_CnSC_DMA (0U) //!< Bit position for FTM_CnSC_DMA.
bogdanm 82:6473597d706e 516 #define BM_FTM_CnSC_DMA (0x00000001U) //!< Bit mask for FTM_CnSC_DMA.
bogdanm 82:6473597d706e 517 #define BS_FTM_CnSC_DMA (1U) //!< Bit field size in bits for FTM_CnSC_DMA.
bogdanm 82:6473597d706e 518
bogdanm 82:6473597d706e 519 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 520 //! @brief Read current value of the FTM_CnSC_DMA field.
bogdanm 82:6473597d706e 521 #define BR_FTM_CnSC_DMA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA))
bogdanm 82:6473597d706e 522 #endif
bogdanm 82:6473597d706e 523
bogdanm 82:6473597d706e 524 //! @brief Format value for bitfield FTM_CnSC_DMA.
bogdanm 82:6473597d706e 525 #define BF_FTM_CnSC_DMA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_DMA), uint32_t) & BM_FTM_CnSC_DMA)
bogdanm 82:6473597d706e 526
bogdanm 82:6473597d706e 527 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 528 //! @brief Set the DMA field to a new value.
bogdanm 82:6473597d706e 529 #define BW_FTM_CnSC_DMA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA) = (v))
bogdanm 82:6473597d706e 530 #endif
bogdanm 82:6473597d706e 531 //@}
bogdanm 82:6473597d706e 532
bogdanm 82:6473597d706e 533 /*!
bogdanm 82:6473597d706e 534 * @name Register FTM_CnSC, field ELSA[2] (RW)
bogdanm 82:6473597d706e 535 *
bogdanm 82:6473597d706e 536 * The functionality of ELSB and ELSA depends on the channel mode. See
bogdanm 82:6473597d706e 537 * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
bogdanm 82:6473597d706e 538 * = 1.
bogdanm 82:6473597d706e 539 */
bogdanm 82:6473597d706e 540 //@{
bogdanm 82:6473597d706e 541 #define BP_FTM_CnSC_ELSA (2U) //!< Bit position for FTM_CnSC_ELSA.
bogdanm 82:6473597d706e 542 #define BM_FTM_CnSC_ELSA (0x00000004U) //!< Bit mask for FTM_CnSC_ELSA.
bogdanm 82:6473597d706e 543 #define BS_FTM_CnSC_ELSA (1U) //!< Bit field size in bits for FTM_CnSC_ELSA.
bogdanm 82:6473597d706e 544
bogdanm 82:6473597d706e 545 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 546 //! @brief Read current value of the FTM_CnSC_ELSA field.
bogdanm 82:6473597d706e 547 #define BR_FTM_CnSC_ELSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA))
bogdanm 82:6473597d706e 548 #endif
bogdanm 82:6473597d706e 549
bogdanm 82:6473597d706e 550 //! @brief Format value for bitfield FTM_CnSC_ELSA.
bogdanm 82:6473597d706e 551 #define BF_FTM_CnSC_ELSA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_ELSA), uint32_t) & BM_FTM_CnSC_ELSA)
bogdanm 82:6473597d706e 552
bogdanm 82:6473597d706e 553 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 554 //! @brief Set the ELSA field to a new value.
bogdanm 82:6473597d706e 555 #define BW_FTM_CnSC_ELSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA) = (v))
bogdanm 82:6473597d706e 556 #endif
bogdanm 82:6473597d706e 557 //@}
bogdanm 82:6473597d706e 558
bogdanm 82:6473597d706e 559 /*!
bogdanm 82:6473597d706e 560 * @name Register FTM_CnSC, field ELSB[3] (RW)
bogdanm 82:6473597d706e 561 *
bogdanm 82:6473597d706e 562 * The functionality of ELSB and ELSA depends on the channel mode. See
bogdanm 82:6473597d706e 563 * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
bogdanm 82:6473597d706e 564 * = 1.
bogdanm 82:6473597d706e 565 */
bogdanm 82:6473597d706e 566 //@{
bogdanm 82:6473597d706e 567 #define BP_FTM_CnSC_ELSB (3U) //!< Bit position for FTM_CnSC_ELSB.
bogdanm 82:6473597d706e 568 #define BM_FTM_CnSC_ELSB (0x00000008U) //!< Bit mask for FTM_CnSC_ELSB.
bogdanm 82:6473597d706e 569 #define BS_FTM_CnSC_ELSB (1U) //!< Bit field size in bits for FTM_CnSC_ELSB.
bogdanm 82:6473597d706e 570
bogdanm 82:6473597d706e 571 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 572 //! @brief Read current value of the FTM_CnSC_ELSB field.
bogdanm 82:6473597d706e 573 #define BR_FTM_CnSC_ELSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB))
bogdanm 82:6473597d706e 574 #endif
bogdanm 82:6473597d706e 575
bogdanm 82:6473597d706e 576 //! @brief Format value for bitfield FTM_CnSC_ELSB.
bogdanm 82:6473597d706e 577 #define BF_FTM_CnSC_ELSB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_ELSB), uint32_t) & BM_FTM_CnSC_ELSB)
bogdanm 82:6473597d706e 578
bogdanm 82:6473597d706e 579 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 580 //! @brief Set the ELSB field to a new value.
bogdanm 82:6473597d706e 581 #define BW_FTM_CnSC_ELSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB) = (v))
bogdanm 82:6473597d706e 582 #endif
bogdanm 82:6473597d706e 583 //@}
bogdanm 82:6473597d706e 584
bogdanm 82:6473597d706e 585 /*!
bogdanm 82:6473597d706e 586 * @name Register FTM_CnSC, field MSA[4] (RW)
bogdanm 82:6473597d706e 587 *
bogdanm 82:6473597d706e 588 * Used for further selections in the channel logic. Its functionality is
bogdanm 82:6473597d706e 589 * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
bogdanm 82:6473597d706e 590 * can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 591 */
bogdanm 82:6473597d706e 592 //@{
bogdanm 82:6473597d706e 593 #define BP_FTM_CnSC_MSA (4U) //!< Bit position for FTM_CnSC_MSA.
bogdanm 82:6473597d706e 594 #define BM_FTM_CnSC_MSA (0x00000010U) //!< Bit mask for FTM_CnSC_MSA.
bogdanm 82:6473597d706e 595 #define BS_FTM_CnSC_MSA (1U) //!< Bit field size in bits for FTM_CnSC_MSA.
bogdanm 82:6473597d706e 596
bogdanm 82:6473597d706e 597 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 598 //! @brief Read current value of the FTM_CnSC_MSA field.
bogdanm 82:6473597d706e 599 #define BR_FTM_CnSC_MSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA))
bogdanm 82:6473597d706e 600 #endif
bogdanm 82:6473597d706e 601
bogdanm 82:6473597d706e 602 //! @brief Format value for bitfield FTM_CnSC_MSA.
bogdanm 82:6473597d706e 603 #define BF_FTM_CnSC_MSA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_MSA), uint32_t) & BM_FTM_CnSC_MSA)
bogdanm 82:6473597d706e 604
bogdanm 82:6473597d706e 605 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 606 //! @brief Set the MSA field to a new value.
bogdanm 82:6473597d706e 607 #define BW_FTM_CnSC_MSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA) = (v))
bogdanm 82:6473597d706e 608 #endif
bogdanm 82:6473597d706e 609 //@}
bogdanm 82:6473597d706e 610
bogdanm 82:6473597d706e 611 /*!
bogdanm 82:6473597d706e 612 * @name Register FTM_CnSC, field MSB[5] (RW)
bogdanm 82:6473597d706e 613 *
bogdanm 82:6473597d706e 614 * Used for further selections in the channel logic. Its functionality is
bogdanm 82:6473597d706e 615 * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
bogdanm 82:6473597d706e 616 * can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 617 */
bogdanm 82:6473597d706e 618 //@{
bogdanm 82:6473597d706e 619 #define BP_FTM_CnSC_MSB (5U) //!< Bit position for FTM_CnSC_MSB.
bogdanm 82:6473597d706e 620 #define BM_FTM_CnSC_MSB (0x00000020U) //!< Bit mask for FTM_CnSC_MSB.
bogdanm 82:6473597d706e 621 #define BS_FTM_CnSC_MSB (1U) //!< Bit field size in bits for FTM_CnSC_MSB.
bogdanm 82:6473597d706e 622
bogdanm 82:6473597d706e 623 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 624 //! @brief Read current value of the FTM_CnSC_MSB field.
bogdanm 82:6473597d706e 625 #define BR_FTM_CnSC_MSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB))
bogdanm 82:6473597d706e 626 #endif
bogdanm 82:6473597d706e 627
bogdanm 82:6473597d706e 628 //! @brief Format value for bitfield FTM_CnSC_MSB.
bogdanm 82:6473597d706e 629 #define BF_FTM_CnSC_MSB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_MSB), uint32_t) & BM_FTM_CnSC_MSB)
bogdanm 82:6473597d706e 630
bogdanm 82:6473597d706e 631 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 632 //! @brief Set the MSB field to a new value.
bogdanm 82:6473597d706e 633 #define BW_FTM_CnSC_MSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB) = (v))
bogdanm 82:6473597d706e 634 #endif
bogdanm 82:6473597d706e 635 //@}
bogdanm 82:6473597d706e 636
bogdanm 82:6473597d706e 637 /*!
bogdanm 82:6473597d706e 638 * @name Register FTM_CnSC, field CHIE[6] (RW)
bogdanm 82:6473597d706e 639 *
bogdanm 82:6473597d706e 640 * Enables channel interrupts.
bogdanm 82:6473597d706e 641 *
bogdanm 82:6473597d706e 642 * Values:
bogdanm 82:6473597d706e 643 * - 0 - Disable channel interrupts. Use software polling.
bogdanm 82:6473597d706e 644 * - 1 - Enable channel interrupts.
bogdanm 82:6473597d706e 645 */
bogdanm 82:6473597d706e 646 //@{
bogdanm 82:6473597d706e 647 #define BP_FTM_CnSC_CHIE (6U) //!< Bit position for FTM_CnSC_CHIE.
bogdanm 82:6473597d706e 648 #define BM_FTM_CnSC_CHIE (0x00000040U) //!< Bit mask for FTM_CnSC_CHIE.
bogdanm 82:6473597d706e 649 #define BS_FTM_CnSC_CHIE (1U) //!< Bit field size in bits for FTM_CnSC_CHIE.
bogdanm 82:6473597d706e 650
bogdanm 82:6473597d706e 651 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 652 //! @brief Read current value of the FTM_CnSC_CHIE field.
bogdanm 82:6473597d706e 653 #define BR_FTM_CnSC_CHIE(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE))
bogdanm 82:6473597d706e 654 #endif
bogdanm 82:6473597d706e 655
bogdanm 82:6473597d706e 656 //! @brief Format value for bitfield FTM_CnSC_CHIE.
bogdanm 82:6473597d706e 657 #define BF_FTM_CnSC_CHIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_CHIE), uint32_t) & BM_FTM_CnSC_CHIE)
bogdanm 82:6473597d706e 658
bogdanm 82:6473597d706e 659 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 660 //! @brief Set the CHIE field to a new value.
bogdanm 82:6473597d706e 661 #define BW_FTM_CnSC_CHIE(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE) = (v))
bogdanm 82:6473597d706e 662 #endif
bogdanm 82:6473597d706e 663 //@}
bogdanm 82:6473597d706e 664
bogdanm 82:6473597d706e 665 /*!
bogdanm 82:6473597d706e 666 * @name Register FTM_CnSC, field CHF[7] (ROWZ)
bogdanm 82:6473597d706e 667 *
bogdanm 82:6473597d706e 668 * Set by hardware when an event occurs on the channel. CHF is cleared by
bogdanm 82:6473597d706e 669 * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
bogdanm 82:6473597d706e 670 * Writing a 1 to CHF has no effect. If another event occurs between the read and
bogdanm 82:6473597d706e 671 * write operations, the write operation has no effect; therefore, CHF remains set
bogdanm 82:6473597d706e 672 * indicating an event has occurred. In this case a CHF interrupt request is not
bogdanm 82:6473597d706e 673 * lost due to the clearing sequence for a previous CHF.
bogdanm 82:6473597d706e 674 *
bogdanm 82:6473597d706e 675 * Values:
bogdanm 82:6473597d706e 676 * - 0 - No channel event has occurred.
bogdanm 82:6473597d706e 677 * - 1 - A channel event has occurred.
bogdanm 82:6473597d706e 678 */
bogdanm 82:6473597d706e 679 //@{
bogdanm 82:6473597d706e 680 #define BP_FTM_CnSC_CHF (7U) //!< Bit position for FTM_CnSC_CHF.
bogdanm 82:6473597d706e 681 #define BM_FTM_CnSC_CHF (0x00000080U) //!< Bit mask for FTM_CnSC_CHF.
bogdanm 82:6473597d706e 682 #define BS_FTM_CnSC_CHF (1U) //!< Bit field size in bits for FTM_CnSC_CHF.
bogdanm 82:6473597d706e 683
bogdanm 82:6473597d706e 684 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 685 //! @brief Read current value of the FTM_CnSC_CHF field.
bogdanm 82:6473597d706e 686 #define BR_FTM_CnSC_CHF(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF))
bogdanm 82:6473597d706e 687 #endif
bogdanm 82:6473597d706e 688 //@}
bogdanm 82:6473597d706e 689 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 690 // HW_FTM_CnV - Channel (n) Value
bogdanm 82:6473597d706e 691 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 692
bogdanm 82:6473597d706e 693 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 694 /*!
bogdanm 82:6473597d706e 695 * @brief HW_FTM_CnV - Channel (n) Value (RW)
bogdanm 82:6473597d706e 696 *
bogdanm 82:6473597d706e 697 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 698 *
bogdanm 82:6473597d706e 699 * These registers contain the captured FTM counter value for the input modes or
bogdanm 82:6473597d706e 700 * the match value for the output modes. In Input Capture, Capture Test, and
bogdanm 82:6473597d706e 701 * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
bogdanm 82:6473597d706e 702 * writing to a CnV register latches the value into a buffer. A CnV register is
bogdanm 82:6473597d706e 703 * updated with the value of its write buffer according to Registers updated from
bogdanm 82:6473597d706e 704 * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
bogdanm 82:6473597d706e 705 * reset by writing to the CnSC register whether BDM mode is active or not.
bogdanm 82:6473597d706e 706 */
bogdanm 82:6473597d706e 707 typedef union _hw_ftm_cnv
bogdanm 82:6473597d706e 708 {
bogdanm 82:6473597d706e 709 uint32_t U;
bogdanm 82:6473597d706e 710 struct _hw_ftm_cnv_bitfields
bogdanm 82:6473597d706e 711 {
bogdanm 82:6473597d706e 712 uint32_t VAL : 16; //!< [15:0] Channel Value
bogdanm 82:6473597d706e 713 uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm 82:6473597d706e 714 } B;
bogdanm 82:6473597d706e 715 } hw_ftm_cnv_t;
bogdanm 82:6473597d706e 716 #endif
bogdanm 82:6473597d706e 717
bogdanm 82:6473597d706e 718 /*!
bogdanm 82:6473597d706e 719 * @name Constants and macros for entire FTM_CnV register
bogdanm 82:6473597d706e 720 */
bogdanm 82:6473597d706e 721 //@{
bogdanm 82:6473597d706e 722 #define HW_FTM_CnV_COUNT (8U)
bogdanm 82:6473597d706e 723
bogdanm 82:6473597d706e 724 #define HW_FTM_CnV_ADDR(x, n) (REGS_FTM_BASE(x) + 0x10U + (0x8U * n))
bogdanm 82:6473597d706e 725
bogdanm 82:6473597d706e 726 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 727 #define HW_FTM_CnV(x, n) (*(__IO hw_ftm_cnv_t *) HW_FTM_CnV_ADDR(x, n))
bogdanm 82:6473597d706e 728 #define HW_FTM_CnV_RD(x, n) (HW_FTM_CnV(x, n).U)
bogdanm 82:6473597d706e 729 #define HW_FTM_CnV_WR(x, n, v) (HW_FTM_CnV(x, n).U = (v))
bogdanm 82:6473597d706e 730 #define HW_FTM_CnV_SET(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) | (v)))
bogdanm 82:6473597d706e 731 #define HW_FTM_CnV_CLR(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) & ~(v)))
bogdanm 82:6473597d706e 732 #define HW_FTM_CnV_TOG(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) ^ (v)))
bogdanm 82:6473597d706e 733 #endif
bogdanm 82:6473597d706e 734 //@}
bogdanm 82:6473597d706e 735
bogdanm 82:6473597d706e 736 /*
bogdanm 82:6473597d706e 737 * Constants & macros for individual FTM_CnV bitfields
bogdanm 82:6473597d706e 738 */
bogdanm 82:6473597d706e 739
bogdanm 82:6473597d706e 740 /*!
bogdanm 82:6473597d706e 741 * @name Register FTM_CnV, field VAL[15:0] (RW)
bogdanm 82:6473597d706e 742 *
bogdanm 82:6473597d706e 743 * Captured FTM counter value of the input modes or the match value for the
bogdanm 82:6473597d706e 744 * output modes
bogdanm 82:6473597d706e 745 */
bogdanm 82:6473597d706e 746 //@{
bogdanm 82:6473597d706e 747 #define BP_FTM_CnV_VAL (0U) //!< Bit position for FTM_CnV_VAL.
bogdanm 82:6473597d706e 748 #define BM_FTM_CnV_VAL (0x0000FFFFU) //!< Bit mask for FTM_CnV_VAL.
bogdanm 82:6473597d706e 749 #define BS_FTM_CnV_VAL (16U) //!< Bit field size in bits for FTM_CnV_VAL.
bogdanm 82:6473597d706e 750
bogdanm 82:6473597d706e 751 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 752 //! @brief Read current value of the FTM_CnV_VAL field.
bogdanm 82:6473597d706e 753 #define BR_FTM_CnV_VAL(x, n) (HW_FTM_CnV(x, n).B.VAL)
bogdanm 82:6473597d706e 754 #endif
bogdanm 82:6473597d706e 755
bogdanm 82:6473597d706e 756 //! @brief Format value for bitfield FTM_CnV_VAL.
bogdanm 82:6473597d706e 757 #define BF_FTM_CnV_VAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnV_VAL), uint32_t) & BM_FTM_CnV_VAL)
bogdanm 82:6473597d706e 758
bogdanm 82:6473597d706e 759 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 760 //! @brief Set the VAL field to a new value.
bogdanm 82:6473597d706e 761 #define BW_FTM_CnV_VAL(x, n, v) (HW_FTM_CnV_WR(x, n, (HW_FTM_CnV_RD(x, n) & ~BM_FTM_CnV_VAL) | BF_FTM_CnV_VAL(v)))
bogdanm 82:6473597d706e 762 #endif
bogdanm 82:6473597d706e 763 //@}
bogdanm 82:6473597d706e 764
bogdanm 82:6473597d706e 765 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 766 // HW_FTM_CNTIN - Counter Initial Value
bogdanm 82:6473597d706e 767 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 768
bogdanm 82:6473597d706e 769 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 770 /*!
bogdanm 82:6473597d706e 771 * @brief HW_FTM_CNTIN - Counter Initial Value (RW)
bogdanm 82:6473597d706e 772 *
bogdanm 82:6473597d706e 773 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 774 *
bogdanm 82:6473597d706e 775 * The Counter Initial Value register contains the initial value for the FTM
bogdanm 82:6473597d706e 776 * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
bogdanm 82:6473597d706e 777 * register is updated with the value of its write buffer according to Registers
bogdanm 82:6473597d706e 778 * updated from write buffers. When the FTM clock is initially selected, by
bogdanm 82:6473597d706e 779 * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
bogdanm 82:6473597d706e 780 * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
bogdanm 82:6473597d706e 781 * write the new value to the the CNTIN register and then initialize the FTM
bogdanm 82:6473597d706e 782 * counter by writing any value to the CNT register.
bogdanm 82:6473597d706e 783 */
bogdanm 82:6473597d706e 784 typedef union _hw_ftm_cntin
bogdanm 82:6473597d706e 785 {
bogdanm 82:6473597d706e 786 uint32_t U;
bogdanm 82:6473597d706e 787 struct _hw_ftm_cntin_bitfields
bogdanm 82:6473597d706e 788 {
bogdanm 82:6473597d706e 789 uint32_t INIT : 16; //!< [15:0]
bogdanm 82:6473597d706e 790 uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm 82:6473597d706e 791 } B;
bogdanm 82:6473597d706e 792 } hw_ftm_cntin_t;
bogdanm 82:6473597d706e 793 #endif
bogdanm 82:6473597d706e 794
bogdanm 82:6473597d706e 795 /*!
bogdanm 82:6473597d706e 796 * @name Constants and macros for entire FTM_CNTIN register
bogdanm 82:6473597d706e 797 */
bogdanm 82:6473597d706e 798 //@{
bogdanm 82:6473597d706e 799 #define HW_FTM_CNTIN_ADDR(x) (REGS_FTM_BASE(x) + 0x4CU)
bogdanm 82:6473597d706e 800
bogdanm 82:6473597d706e 801 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 802 #define HW_FTM_CNTIN(x) (*(__IO hw_ftm_cntin_t *) HW_FTM_CNTIN_ADDR(x))
bogdanm 82:6473597d706e 803 #define HW_FTM_CNTIN_RD(x) (HW_FTM_CNTIN(x).U)
bogdanm 82:6473597d706e 804 #define HW_FTM_CNTIN_WR(x, v) (HW_FTM_CNTIN(x).U = (v))
bogdanm 82:6473597d706e 805 #define HW_FTM_CNTIN_SET(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) | (v)))
bogdanm 82:6473597d706e 806 #define HW_FTM_CNTIN_CLR(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) & ~(v)))
bogdanm 82:6473597d706e 807 #define HW_FTM_CNTIN_TOG(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) ^ (v)))
bogdanm 82:6473597d706e 808 #endif
bogdanm 82:6473597d706e 809 //@}
bogdanm 82:6473597d706e 810
bogdanm 82:6473597d706e 811 /*
bogdanm 82:6473597d706e 812 * Constants & macros for individual FTM_CNTIN bitfields
bogdanm 82:6473597d706e 813 */
bogdanm 82:6473597d706e 814
bogdanm 82:6473597d706e 815 /*!
bogdanm 82:6473597d706e 816 * @name Register FTM_CNTIN, field INIT[15:0] (RW)
bogdanm 82:6473597d706e 817 *
bogdanm 82:6473597d706e 818 * Initial Value Of The FTM Counter
bogdanm 82:6473597d706e 819 */
bogdanm 82:6473597d706e 820 //@{
bogdanm 82:6473597d706e 821 #define BP_FTM_CNTIN_INIT (0U) //!< Bit position for FTM_CNTIN_INIT.
bogdanm 82:6473597d706e 822 #define BM_FTM_CNTIN_INIT (0x0000FFFFU) //!< Bit mask for FTM_CNTIN_INIT.
bogdanm 82:6473597d706e 823 #define BS_FTM_CNTIN_INIT (16U) //!< Bit field size in bits for FTM_CNTIN_INIT.
bogdanm 82:6473597d706e 824
bogdanm 82:6473597d706e 825 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 826 //! @brief Read current value of the FTM_CNTIN_INIT field.
bogdanm 82:6473597d706e 827 #define BR_FTM_CNTIN_INIT(x) (HW_FTM_CNTIN(x).B.INIT)
bogdanm 82:6473597d706e 828 #endif
bogdanm 82:6473597d706e 829
bogdanm 82:6473597d706e 830 //! @brief Format value for bitfield FTM_CNTIN_INIT.
bogdanm 82:6473597d706e 831 #define BF_FTM_CNTIN_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CNTIN_INIT), uint32_t) & BM_FTM_CNTIN_INIT)
bogdanm 82:6473597d706e 832
bogdanm 82:6473597d706e 833 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 834 //! @brief Set the INIT field to a new value.
bogdanm 82:6473597d706e 835 #define BW_FTM_CNTIN_INIT(x, v) (HW_FTM_CNTIN_WR(x, (HW_FTM_CNTIN_RD(x) & ~BM_FTM_CNTIN_INIT) | BF_FTM_CNTIN_INIT(v)))
bogdanm 82:6473597d706e 836 #endif
bogdanm 82:6473597d706e 837 //@}
bogdanm 82:6473597d706e 838
bogdanm 82:6473597d706e 839 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 840 // HW_FTM_STATUS - Capture And Compare Status
bogdanm 82:6473597d706e 841 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 842
bogdanm 82:6473597d706e 843 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 844 /*!
bogdanm 82:6473597d706e 845 * @brief HW_FTM_STATUS - Capture And Compare Status (RW)
bogdanm 82:6473597d706e 846 *
bogdanm 82:6473597d706e 847 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 848 *
bogdanm 82:6473597d706e 849 * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
bogdanm 82:6473597d706e 850 * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
bogdanm 82:6473597d706e 851 * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
bogdanm 82:6473597d706e 852 * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
bogdanm 82:6473597d706e 853 * STATUS. Hardware sets the individual channel flags when an event occurs on the
bogdanm 82:6473597d706e 854 * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
bogdanm 82:6473597d706e 855 * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
bogdanm 82:6473597d706e 856 * occurs between the read and write operations, the write operation has no effect;
bogdanm 82:6473597d706e 857 * therefore, CHnF remains set indicating an event has occurred. In this case, a
bogdanm 82:6473597d706e 858 * CHnF interrupt request is not lost due to the clearing sequence for a previous
bogdanm 82:6473597d706e 859 * CHnF. The STATUS register should be used only in Combine mode.
bogdanm 82:6473597d706e 860 */
bogdanm 82:6473597d706e 861 typedef union _hw_ftm_status
bogdanm 82:6473597d706e 862 {
bogdanm 82:6473597d706e 863 uint32_t U;
bogdanm 82:6473597d706e 864 struct _hw_ftm_status_bitfields
bogdanm 82:6473597d706e 865 {
bogdanm 82:6473597d706e 866 uint32_t CH0F : 1; //!< [0] Channel 0 Flag
bogdanm 82:6473597d706e 867 uint32_t CH1F : 1; //!< [1] Channel 1 Flag
bogdanm 82:6473597d706e 868 uint32_t CH2F : 1; //!< [2] Channel 2 Flag
bogdanm 82:6473597d706e 869 uint32_t CH3F : 1; //!< [3] Channel 3 Flag
bogdanm 82:6473597d706e 870 uint32_t CH4F : 1; //!< [4] Channel 4 Flag
bogdanm 82:6473597d706e 871 uint32_t CH5F : 1; //!< [5] Channel 5 Flag
bogdanm 82:6473597d706e 872 uint32_t CH6F : 1; //!< [6] Channel 6 Flag
bogdanm 82:6473597d706e 873 uint32_t CH7F : 1; //!< [7] Channel 7 Flag
bogdanm 82:6473597d706e 874 uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm 82:6473597d706e 875 } B;
bogdanm 82:6473597d706e 876 } hw_ftm_status_t;
bogdanm 82:6473597d706e 877 #endif
bogdanm 82:6473597d706e 878
bogdanm 82:6473597d706e 879 /*!
bogdanm 82:6473597d706e 880 * @name Constants and macros for entire FTM_STATUS register
bogdanm 82:6473597d706e 881 */
bogdanm 82:6473597d706e 882 //@{
bogdanm 82:6473597d706e 883 #define HW_FTM_STATUS_ADDR(x) (REGS_FTM_BASE(x) + 0x50U)
bogdanm 82:6473597d706e 884
bogdanm 82:6473597d706e 885 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 886 #define HW_FTM_STATUS(x) (*(__IO hw_ftm_status_t *) HW_FTM_STATUS_ADDR(x))
bogdanm 82:6473597d706e 887 #define HW_FTM_STATUS_RD(x) (HW_FTM_STATUS(x).U)
bogdanm 82:6473597d706e 888 #define HW_FTM_STATUS_WR(x, v) (HW_FTM_STATUS(x).U = (v))
bogdanm 82:6473597d706e 889 #define HW_FTM_STATUS_SET(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) | (v)))
bogdanm 82:6473597d706e 890 #define HW_FTM_STATUS_CLR(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) & ~(v)))
bogdanm 82:6473597d706e 891 #define HW_FTM_STATUS_TOG(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) ^ (v)))
bogdanm 82:6473597d706e 892 #endif
bogdanm 82:6473597d706e 893 //@}
bogdanm 82:6473597d706e 894
bogdanm 82:6473597d706e 895 /*
bogdanm 82:6473597d706e 896 * Constants & macros for individual FTM_STATUS bitfields
bogdanm 82:6473597d706e 897 */
bogdanm 82:6473597d706e 898
bogdanm 82:6473597d706e 899 /*!
bogdanm 82:6473597d706e 900 * @name Register FTM_STATUS, field CH0F[0] (W1C)
bogdanm 82:6473597d706e 901 *
bogdanm 82:6473597d706e 902 * See the register description.
bogdanm 82:6473597d706e 903 *
bogdanm 82:6473597d706e 904 * Values:
bogdanm 82:6473597d706e 905 * - 0 - No channel event has occurred.
bogdanm 82:6473597d706e 906 * - 1 - A channel event has occurred.
bogdanm 82:6473597d706e 907 */
bogdanm 82:6473597d706e 908 //@{
bogdanm 82:6473597d706e 909 #define BP_FTM_STATUS_CH0F (0U) //!< Bit position for FTM_STATUS_CH0F.
bogdanm 82:6473597d706e 910 #define BM_FTM_STATUS_CH0F (0x00000001U) //!< Bit mask for FTM_STATUS_CH0F.
bogdanm 82:6473597d706e 911 #define BS_FTM_STATUS_CH0F (1U) //!< Bit field size in bits for FTM_STATUS_CH0F.
bogdanm 82:6473597d706e 912
bogdanm 82:6473597d706e 913 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 914 //! @brief Read current value of the FTM_STATUS_CH0F field.
bogdanm 82:6473597d706e 915 #define BR_FTM_STATUS_CH0F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F))
bogdanm 82:6473597d706e 916 #endif
bogdanm 82:6473597d706e 917
bogdanm 82:6473597d706e 918 //! @brief Format value for bitfield FTM_STATUS_CH0F.
bogdanm 82:6473597d706e 919 #define BF_FTM_STATUS_CH0F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH0F), uint32_t) & BM_FTM_STATUS_CH0F)
bogdanm 82:6473597d706e 920
bogdanm 82:6473597d706e 921 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 922 //! @brief Set the CH0F field to a new value.
bogdanm 82:6473597d706e 923 #define BW_FTM_STATUS_CH0F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F) = (v))
bogdanm 82:6473597d706e 924 #endif
bogdanm 82:6473597d706e 925 //@}
bogdanm 82:6473597d706e 926
bogdanm 82:6473597d706e 927 /*!
bogdanm 82:6473597d706e 928 * @name Register FTM_STATUS, field CH1F[1] (W1C)
bogdanm 82:6473597d706e 929 *
bogdanm 82:6473597d706e 930 * See the register description.
bogdanm 82:6473597d706e 931 *
bogdanm 82:6473597d706e 932 * Values:
bogdanm 82:6473597d706e 933 * - 0 - No channel event has occurred.
bogdanm 82:6473597d706e 934 * - 1 - A channel event has occurred.
bogdanm 82:6473597d706e 935 */
bogdanm 82:6473597d706e 936 //@{
bogdanm 82:6473597d706e 937 #define BP_FTM_STATUS_CH1F (1U) //!< Bit position for FTM_STATUS_CH1F.
bogdanm 82:6473597d706e 938 #define BM_FTM_STATUS_CH1F (0x00000002U) //!< Bit mask for FTM_STATUS_CH1F.
bogdanm 82:6473597d706e 939 #define BS_FTM_STATUS_CH1F (1U) //!< Bit field size in bits for FTM_STATUS_CH1F.
bogdanm 82:6473597d706e 940
bogdanm 82:6473597d706e 941 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 942 //! @brief Read current value of the FTM_STATUS_CH1F field.
bogdanm 82:6473597d706e 943 #define BR_FTM_STATUS_CH1F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F))
bogdanm 82:6473597d706e 944 #endif
bogdanm 82:6473597d706e 945
bogdanm 82:6473597d706e 946 //! @brief Format value for bitfield FTM_STATUS_CH1F.
bogdanm 82:6473597d706e 947 #define BF_FTM_STATUS_CH1F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH1F), uint32_t) & BM_FTM_STATUS_CH1F)
bogdanm 82:6473597d706e 948
bogdanm 82:6473597d706e 949 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 950 //! @brief Set the CH1F field to a new value.
bogdanm 82:6473597d706e 951 #define BW_FTM_STATUS_CH1F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F) = (v))
bogdanm 82:6473597d706e 952 #endif
bogdanm 82:6473597d706e 953 //@}
bogdanm 82:6473597d706e 954
bogdanm 82:6473597d706e 955 /*!
bogdanm 82:6473597d706e 956 * @name Register FTM_STATUS, field CH2F[2] (W1C)
bogdanm 82:6473597d706e 957 *
bogdanm 82:6473597d706e 958 * See the register description.
bogdanm 82:6473597d706e 959 *
bogdanm 82:6473597d706e 960 * Values:
bogdanm 82:6473597d706e 961 * - 0 - No channel event has occurred.
bogdanm 82:6473597d706e 962 * - 1 - A channel event has occurred.
bogdanm 82:6473597d706e 963 */
bogdanm 82:6473597d706e 964 //@{
bogdanm 82:6473597d706e 965 #define BP_FTM_STATUS_CH2F (2U) //!< Bit position for FTM_STATUS_CH2F.
bogdanm 82:6473597d706e 966 #define BM_FTM_STATUS_CH2F (0x00000004U) //!< Bit mask for FTM_STATUS_CH2F.
bogdanm 82:6473597d706e 967 #define BS_FTM_STATUS_CH2F (1U) //!< Bit field size in bits for FTM_STATUS_CH2F.
bogdanm 82:6473597d706e 968
bogdanm 82:6473597d706e 969 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 970 //! @brief Read current value of the FTM_STATUS_CH2F field.
bogdanm 82:6473597d706e 971 #define BR_FTM_STATUS_CH2F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F))
bogdanm 82:6473597d706e 972 #endif
bogdanm 82:6473597d706e 973
bogdanm 82:6473597d706e 974 //! @brief Format value for bitfield FTM_STATUS_CH2F.
bogdanm 82:6473597d706e 975 #define BF_FTM_STATUS_CH2F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH2F), uint32_t) & BM_FTM_STATUS_CH2F)
bogdanm 82:6473597d706e 976
bogdanm 82:6473597d706e 977 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 978 //! @brief Set the CH2F field to a new value.
bogdanm 82:6473597d706e 979 #define BW_FTM_STATUS_CH2F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F) = (v))
bogdanm 82:6473597d706e 980 #endif
bogdanm 82:6473597d706e 981 //@}
bogdanm 82:6473597d706e 982
bogdanm 82:6473597d706e 983 /*!
bogdanm 82:6473597d706e 984 * @name Register FTM_STATUS, field CH3F[3] (W1C)
bogdanm 82:6473597d706e 985 *
bogdanm 82:6473597d706e 986 * See the register description.
bogdanm 82:6473597d706e 987 *
bogdanm 82:6473597d706e 988 * Values:
bogdanm 82:6473597d706e 989 * - 0 - No channel event has occurred.
bogdanm 82:6473597d706e 990 * - 1 - A channel event has occurred.
bogdanm 82:6473597d706e 991 */
bogdanm 82:6473597d706e 992 //@{
bogdanm 82:6473597d706e 993 #define BP_FTM_STATUS_CH3F (3U) //!< Bit position for FTM_STATUS_CH3F.
bogdanm 82:6473597d706e 994 #define BM_FTM_STATUS_CH3F (0x00000008U) //!< Bit mask for FTM_STATUS_CH3F.
bogdanm 82:6473597d706e 995 #define BS_FTM_STATUS_CH3F (1U) //!< Bit field size in bits for FTM_STATUS_CH3F.
bogdanm 82:6473597d706e 996
bogdanm 82:6473597d706e 997 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 998 //! @brief Read current value of the FTM_STATUS_CH3F field.
bogdanm 82:6473597d706e 999 #define BR_FTM_STATUS_CH3F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F))
bogdanm 82:6473597d706e 1000 #endif
bogdanm 82:6473597d706e 1001
bogdanm 82:6473597d706e 1002 //! @brief Format value for bitfield FTM_STATUS_CH3F.
bogdanm 82:6473597d706e 1003 #define BF_FTM_STATUS_CH3F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH3F), uint32_t) & BM_FTM_STATUS_CH3F)
bogdanm 82:6473597d706e 1004
bogdanm 82:6473597d706e 1005 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1006 //! @brief Set the CH3F field to a new value.
bogdanm 82:6473597d706e 1007 #define BW_FTM_STATUS_CH3F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F) = (v))
bogdanm 82:6473597d706e 1008 #endif
bogdanm 82:6473597d706e 1009 //@}
bogdanm 82:6473597d706e 1010
bogdanm 82:6473597d706e 1011 /*!
bogdanm 82:6473597d706e 1012 * @name Register FTM_STATUS, field CH4F[4] (W1C)
bogdanm 82:6473597d706e 1013 *
bogdanm 82:6473597d706e 1014 * See the register description.
bogdanm 82:6473597d706e 1015 *
bogdanm 82:6473597d706e 1016 * Values:
bogdanm 82:6473597d706e 1017 * - 0 - No channel event has occurred.
bogdanm 82:6473597d706e 1018 * - 1 - A channel event has occurred.
bogdanm 82:6473597d706e 1019 */
bogdanm 82:6473597d706e 1020 //@{
bogdanm 82:6473597d706e 1021 #define BP_FTM_STATUS_CH4F (4U) //!< Bit position for FTM_STATUS_CH4F.
bogdanm 82:6473597d706e 1022 #define BM_FTM_STATUS_CH4F (0x00000010U) //!< Bit mask for FTM_STATUS_CH4F.
bogdanm 82:6473597d706e 1023 #define BS_FTM_STATUS_CH4F (1U) //!< Bit field size in bits for FTM_STATUS_CH4F.
bogdanm 82:6473597d706e 1024
bogdanm 82:6473597d706e 1025 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1026 //! @brief Read current value of the FTM_STATUS_CH4F field.
bogdanm 82:6473597d706e 1027 #define BR_FTM_STATUS_CH4F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F))
bogdanm 82:6473597d706e 1028 #endif
bogdanm 82:6473597d706e 1029
bogdanm 82:6473597d706e 1030 //! @brief Format value for bitfield FTM_STATUS_CH4F.
bogdanm 82:6473597d706e 1031 #define BF_FTM_STATUS_CH4F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH4F), uint32_t) & BM_FTM_STATUS_CH4F)
bogdanm 82:6473597d706e 1032
bogdanm 82:6473597d706e 1033 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1034 //! @brief Set the CH4F field to a new value.
bogdanm 82:6473597d706e 1035 #define BW_FTM_STATUS_CH4F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F) = (v))
bogdanm 82:6473597d706e 1036 #endif
bogdanm 82:6473597d706e 1037 //@}
bogdanm 82:6473597d706e 1038
bogdanm 82:6473597d706e 1039 /*!
bogdanm 82:6473597d706e 1040 * @name Register FTM_STATUS, field CH5F[5] (W1C)
bogdanm 82:6473597d706e 1041 *
bogdanm 82:6473597d706e 1042 * See the register description.
bogdanm 82:6473597d706e 1043 *
bogdanm 82:6473597d706e 1044 * Values:
bogdanm 82:6473597d706e 1045 * - 0 - No channel event has occurred.
bogdanm 82:6473597d706e 1046 * - 1 - A channel event has occurred.
bogdanm 82:6473597d706e 1047 */
bogdanm 82:6473597d706e 1048 //@{
bogdanm 82:6473597d706e 1049 #define BP_FTM_STATUS_CH5F (5U) //!< Bit position for FTM_STATUS_CH5F.
bogdanm 82:6473597d706e 1050 #define BM_FTM_STATUS_CH5F (0x00000020U) //!< Bit mask for FTM_STATUS_CH5F.
bogdanm 82:6473597d706e 1051 #define BS_FTM_STATUS_CH5F (1U) //!< Bit field size in bits for FTM_STATUS_CH5F.
bogdanm 82:6473597d706e 1052
bogdanm 82:6473597d706e 1053 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1054 //! @brief Read current value of the FTM_STATUS_CH5F field.
bogdanm 82:6473597d706e 1055 #define BR_FTM_STATUS_CH5F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F))
bogdanm 82:6473597d706e 1056 #endif
bogdanm 82:6473597d706e 1057
bogdanm 82:6473597d706e 1058 //! @brief Format value for bitfield FTM_STATUS_CH5F.
bogdanm 82:6473597d706e 1059 #define BF_FTM_STATUS_CH5F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH5F), uint32_t) & BM_FTM_STATUS_CH5F)
bogdanm 82:6473597d706e 1060
bogdanm 82:6473597d706e 1061 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1062 //! @brief Set the CH5F field to a new value.
bogdanm 82:6473597d706e 1063 #define BW_FTM_STATUS_CH5F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F) = (v))
bogdanm 82:6473597d706e 1064 #endif
bogdanm 82:6473597d706e 1065 //@}
bogdanm 82:6473597d706e 1066
bogdanm 82:6473597d706e 1067 /*!
bogdanm 82:6473597d706e 1068 * @name Register FTM_STATUS, field CH6F[6] (W1C)
bogdanm 82:6473597d706e 1069 *
bogdanm 82:6473597d706e 1070 * See the register description.
bogdanm 82:6473597d706e 1071 *
bogdanm 82:6473597d706e 1072 * Values:
bogdanm 82:6473597d706e 1073 * - 0 - No channel event has occurred.
bogdanm 82:6473597d706e 1074 * - 1 - A channel event has occurred.
bogdanm 82:6473597d706e 1075 */
bogdanm 82:6473597d706e 1076 //@{
bogdanm 82:6473597d706e 1077 #define BP_FTM_STATUS_CH6F (6U) //!< Bit position for FTM_STATUS_CH6F.
bogdanm 82:6473597d706e 1078 #define BM_FTM_STATUS_CH6F (0x00000040U) //!< Bit mask for FTM_STATUS_CH6F.
bogdanm 82:6473597d706e 1079 #define BS_FTM_STATUS_CH6F (1U) //!< Bit field size in bits for FTM_STATUS_CH6F.
bogdanm 82:6473597d706e 1080
bogdanm 82:6473597d706e 1081 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1082 //! @brief Read current value of the FTM_STATUS_CH6F field.
bogdanm 82:6473597d706e 1083 #define BR_FTM_STATUS_CH6F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F))
bogdanm 82:6473597d706e 1084 #endif
bogdanm 82:6473597d706e 1085
bogdanm 82:6473597d706e 1086 //! @brief Format value for bitfield FTM_STATUS_CH6F.
bogdanm 82:6473597d706e 1087 #define BF_FTM_STATUS_CH6F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH6F), uint32_t) & BM_FTM_STATUS_CH6F)
bogdanm 82:6473597d706e 1088
bogdanm 82:6473597d706e 1089 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1090 //! @brief Set the CH6F field to a new value.
bogdanm 82:6473597d706e 1091 #define BW_FTM_STATUS_CH6F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F) = (v))
bogdanm 82:6473597d706e 1092 #endif
bogdanm 82:6473597d706e 1093 //@}
bogdanm 82:6473597d706e 1094
bogdanm 82:6473597d706e 1095 /*!
bogdanm 82:6473597d706e 1096 * @name Register FTM_STATUS, field CH7F[7] (W1C)
bogdanm 82:6473597d706e 1097 *
bogdanm 82:6473597d706e 1098 * See the register description.
bogdanm 82:6473597d706e 1099 *
bogdanm 82:6473597d706e 1100 * Values:
bogdanm 82:6473597d706e 1101 * - 0 - No channel event has occurred.
bogdanm 82:6473597d706e 1102 * - 1 - A channel event has occurred.
bogdanm 82:6473597d706e 1103 */
bogdanm 82:6473597d706e 1104 //@{
bogdanm 82:6473597d706e 1105 #define BP_FTM_STATUS_CH7F (7U) //!< Bit position for FTM_STATUS_CH7F.
bogdanm 82:6473597d706e 1106 #define BM_FTM_STATUS_CH7F (0x00000080U) //!< Bit mask for FTM_STATUS_CH7F.
bogdanm 82:6473597d706e 1107 #define BS_FTM_STATUS_CH7F (1U) //!< Bit field size in bits for FTM_STATUS_CH7F.
bogdanm 82:6473597d706e 1108
bogdanm 82:6473597d706e 1109 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1110 //! @brief Read current value of the FTM_STATUS_CH7F field.
bogdanm 82:6473597d706e 1111 #define BR_FTM_STATUS_CH7F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F))
bogdanm 82:6473597d706e 1112 #endif
bogdanm 82:6473597d706e 1113
bogdanm 82:6473597d706e 1114 //! @brief Format value for bitfield FTM_STATUS_CH7F.
bogdanm 82:6473597d706e 1115 #define BF_FTM_STATUS_CH7F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH7F), uint32_t) & BM_FTM_STATUS_CH7F)
bogdanm 82:6473597d706e 1116
bogdanm 82:6473597d706e 1117 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1118 //! @brief Set the CH7F field to a new value.
bogdanm 82:6473597d706e 1119 #define BW_FTM_STATUS_CH7F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F) = (v))
bogdanm 82:6473597d706e 1120 #endif
bogdanm 82:6473597d706e 1121 //@}
bogdanm 82:6473597d706e 1122
bogdanm 82:6473597d706e 1123 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1124 // HW_FTM_MODE - Features Mode Selection
bogdanm 82:6473597d706e 1125 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1126
bogdanm 82:6473597d706e 1127 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1128 /*!
bogdanm 82:6473597d706e 1129 * @brief HW_FTM_MODE - Features Mode Selection (RW)
bogdanm 82:6473597d706e 1130 *
bogdanm 82:6473597d706e 1131 * Reset value: 0x00000004U
bogdanm 82:6473597d706e 1132 *
bogdanm 82:6473597d706e 1133 * This register contains the global enable bit for FTM-specific features and
bogdanm 82:6473597d706e 1134 * the control bits used to configure: Fault control mode and interrupt Capture
bogdanm 82:6473597d706e 1135 * Test mode PWM synchronization Write protection Channel output initialization
bogdanm 82:6473597d706e 1136 * These controls relate to all channels within this module.
bogdanm 82:6473597d706e 1137 */
bogdanm 82:6473597d706e 1138 typedef union _hw_ftm_mode
bogdanm 82:6473597d706e 1139 {
bogdanm 82:6473597d706e 1140 uint32_t U;
bogdanm 82:6473597d706e 1141 struct _hw_ftm_mode_bitfields
bogdanm 82:6473597d706e 1142 {
bogdanm 82:6473597d706e 1143 uint32_t FTMEN : 1; //!< [0] FTM Enable
bogdanm 82:6473597d706e 1144 uint32_t INIT : 1; //!< [1] Initialize The Channels Output
bogdanm 82:6473597d706e 1145 uint32_t WPDIS : 1; //!< [2] Write Protection Disable
bogdanm 82:6473597d706e 1146 uint32_t PWMSYNC : 1; //!< [3] PWM Synchronization Mode
bogdanm 82:6473597d706e 1147 uint32_t CAPTEST : 1; //!< [4] Capture Test Mode Enable
bogdanm 82:6473597d706e 1148 uint32_t FAULTM : 2; //!< [6:5] Fault Control Mode
bogdanm 82:6473597d706e 1149 uint32_t FAULTIE : 1; //!< [7] Fault Interrupt Enable
bogdanm 82:6473597d706e 1150 uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm 82:6473597d706e 1151 } B;
bogdanm 82:6473597d706e 1152 } hw_ftm_mode_t;
bogdanm 82:6473597d706e 1153 #endif
bogdanm 82:6473597d706e 1154
bogdanm 82:6473597d706e 1155 /*!
bogdanm 82:6473597d706e 1156 * @name Constants and macros for entire FTM_MODE register
bogdanm 82:6473597d706e 1157 */
bogdanm 82:6473597d706e 1158 //@{
bogdanm 82:6473597d706e 1159 #define HW_FTM_MODE_ADDR(x) (REGS_FTM_BASE(x) + 0x54U)
bogdanm 82:6473597d706e 1160
bogdanm 82:6473597d706e 1161 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1162 #define HW_FTM_MODE(x) (*(__IO hw_ftm_mode_t *) HW_FTM_MODE_ADDR(x))
bogdanm 82:6473597d706e 1163 #define HW_FTM_MODE_RD(x) (HW_FTM_MODE(x).U)
bogdanm 82:6473597d706e 1164 #define HW_FTM_MODE_WR(x, v) (HW_FTM_MODE(x).U = (v))
bogdanm 82:6473597d706e 1165 #define HW_FTM_MODE_SET(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) | (v)))
bogdanm 82:6473597d706e 1166 #define HW_FTM_MODE_CLR(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) & ~(v)))
bogdanm 82:6473597d706e 1167 #define HW_FTM_MODE_TOG(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) ^ (v)))
bogdanm 82:6473597d706e 1168 #endif
bogdanm 82:6473597d706e 1169 //@}
bogdanm 82:6473597d706e 1170
bogdanm 82:6473597d706e 1171 /*
bogdanm 82:6473597d706e 1172 * Constants & macros for individual FTM_MODE bitfields
bogdanm 82:6473597d706e 1173 */
bogdanm 82:6473597d706e 1174
bogdanm 82:6473597d706e 1175 /*!
bogdanm 82:6473597d706e 1176 * @name Register FTM_MODE, field FTMEN[0] (RW)
bogdanm 82:6473597d706e 1177 *
bogdanm 82:6473597d706e 1178 * This field is write protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 1179 *
bogdanm 82:6473597d706e 1180 * Values:
bogdanm 82:6473597d706e 1181 * - 0 - Only the TPM-compatible registers (first set of registers) can be used
bogdanm 82:6473597d706e 1182 * without any restriction. Do not use the FTM-specific registers.
bogdanm 82:6473597d706e 1183 * - 1 - All registers including the FTM-specific registers (second set of
bogdanm 82:6473597d706e 1184 * registers) are available for use with no restrictions.
bogdanm 82:6473597d706e 1185 */
bogdanm 82:6473597d706e 1186 //@{
bogdanm 82:6473597d706e 1187 #define BP_FTM_MODE_FTMEN (0U) //!< Bit position for FTM_MODE_FTMEN.
bogdanm 82:6473597d706e 1188 #define BM_FTM_MODE_FTMEN (0x00000001U) //!< Bit mask for FTM_MODE_FTMEN.
bogdanm 82:6473597d706e 1189 #define BS_FTM_MODE_FTMEN (1U) //!< Bit field size in bits for FTM_MODE_FTMEN.
bogdanm 82:6473597d706e 1190
bogdanm 82:6473597d706e 1191 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1192 //! @brief Read current value of the FTM_MODE_FTMEN field.
bogdanm 82:6473597d706e 1193 #define BR_FTM_MODE_FTMEN(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN))
bogdanm 82:6473597d706e 1194 #endif
bogdanm 82:6473597d706e 1195
bogdanm 82:6473597d706e 1196 //! @brief Format value for bitfield FTM_MODE_FTMEN.
bogdanm 82:6473597d706e 1197 #define BF_FTM_MODE_FTMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FTMEN), uint32_t) & BM_FTM_MODE_FTMEN)
bogdanm 82:6473597d706e 1198
bogdanm 82:6473597d706e 1199 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1200 //! @brief Set the FTMEN field to a new value.
bogdanm 82:6473597d706e 1201 #define BW_FTM_MODE_FTMEN(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN) = (v))
bogdanm 82:6473597d706e 1202 #endif
bogdanm 82:6473597d706e 1203 //@}
bogdanm 82:6473597d706e 1204
bogdanm 82:6473597d706e 1205 /*!
bogdanm 82:6473597d706e 1206 * @name Register FTM_MODE, field INIT[1] (RW)
bogdanm 82:6473597d706e 1207 *
bogdanm 82:6473597d706e 1208 * When a 1 is written to INIT bit the channels output is initialized according
bogdanm 82:6473597d706e 1209 * to the state of their corresponding bit in the OUTINIT register. Writing a 0
bogdanm 82:6473597d706e 1210 * to INIT bit has no effect. The INIT bit is always read as 0.
bogdanm 82:6473597d706e 1211 */
bogdanm 82:6473597d706e 1212 //@{
bogdanm 82:6473597d706e 1213 #define BP_FTM_MODE_INIT (1U) //!< Bit position for FTM_MODE_INIT.
bogdanm 82:6473597d706e 1214 #define BM_FTM_MODE_INIT (0x00000002U) //!< Bit mask for FTM_MODE_INIT.
bogdanm 82:6473597d706e 1215 #define BS_FTM_MODE_INIT (1U) //!< Bit field size in bits for FTM_MODE_INIT.
bogdanm 82:6473597d706e 1216
bogdanm 82:6473597d706e 1217 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1218 //! @brief Read current value of the FTM_MODE_INIT field.
bogdanm 82:6473597d706e 1219 #define BR_FTM_MODE_INIT(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT))
bogdanm 82:6473597d706e 1220 #endif
bogdanm 82:6473597d706e 1221
bogdanm 82:6473597d706e 1222 //! @brief Format value for bitfield FTM_MODE_INIT.
bogdanm 82:6473597d706e 1223 #define BF_FTM_MODE_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_INIT), uint32_t) & BM_FTM_MODE_INIT)
bogdanm 82:6473597d706e 1224
bogdanm 82:6473597d706e 1225 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1226 //! @brief Set the INIT field to a new value.
bogdanm 82:6473597d706e 1227 #define BW_FTM_MODE_INIT(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT) = (v))
bogdanm 82:6473597d706e 1228 #endif
bogdanm 82:6473597d706e 1229 //@}
bogdanm 82:6473597d706e 1230
bogdanm 82:6473597d706e 1231 /*!
bogdanm 82:6473597d706e 1232 * @name Register FTM_MODE, field WPDIS[2] (RW)
bogdanm 82:6473597d706e 1233 *
bogdanm 82:6473597d706e 1234 * When write protection is enabled (WPDIS = 0), write protected bits cannot be
bogdanm 82:6473597d706e 1235 * written. When write protection is disabled (WPDIS = 1), write protected bits
bogdanm 82:6473597d706e 1236 * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
bogdanm 82:6473597d706e 1237 * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
bogdanm 82:6473597d706e 1238 * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
bogdanm 82:6473597d706e 1239 *
bogdanm 82:6473597d706e 1240 * Values:
bogdanm 82:6473597d706e 1241 * - 0 - Write protection is enabled.
bogdanm 82:6473597d706e 1242 * - 1 - Write protection is disabled.
bogdanm 82:6473597d706e 1243 */
bogdanm 82:6473597d706e 1244 //@{
bogdanm 82:6473597d706e 1245 #define BP_FTM_MODE_WPDIS (2U) //!< Bit position for FTM_MODE_WPDIS.
bogdanm 82:6473597d706e 1246 #define BM_FTM_MODE_WPDIS (0x00000004U) //!< Bit mask for FTM_MODE_WPDIS.
bogdanm 82:6473597d706e 1247 #define BS_FTM_MODE_WPDIS (1U) //!< Bit field size in bits for FTM_MODE_WPDIS.
bogdanm 82:6473597d706e 1248
bogdanm 82:6473597d706e 1249 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1250 //! @brief Read current value of the FTM_MODE_WPDIS field.
bogdanm 82:6473597d706e 1251 #define BR_FTM_MODE_WPDIS(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS))
bogdanm 82:6473597d706e 1252 #endif
bogdanm 82:6473597d706e 1253
bogdanm 82:6473597d706e 1254 //! @brief Format value for bitfield FTM_MODE_WPDIS.
bogdanm 82:6473597d706e 1255 #define BF_FTM_MODE_WPDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_WPDIS), uint32_t) & BM_FTM_MODE_WPDIS)
bogdanm 82:6473597d706e 1256
bogdanm 82:6473597d706e 1257 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1258 //! @brief Set the WPDIS field to a new value.
bogdanm 82:6473597d706e 1259 #define BW_FTM_MODE_WPDIS(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS) = (v))
bogdanm 82:6473597d706e 1260 #endif
bogdanm 82:6473597d706e 1261 //@}
bogdanm 82:6473597d706e 1262
bogdanm 82:6473597d706e 1263 /*!
bogdanm 82:6473597d706e 1264 * @name Register FTM_MODE, field PWMSYNC[3] (RW)
bogdanm 82:6473597d706e 1265 *
bogdanm 82:6473597d706e 1266 * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
bogdanm 82:6473597d706e 1267 * synchronization. See PWM synchronization. The PWMSYNC bit configures the
bogdanm 82:6473597d706e 1268 * synchronization when SYNCMODE is 0.
bogdanm 82:6473597d706e 1269 *
bogdanm 82:6473597d706e 1270 * Values:
bogdanm 82:6473597d706e 1271 * - 0 - No restrictions. Software and hardware triggers can be used by MOD,
bogdanm 82:6473597d706e 1272 * CnV, OUTMASK, and FTM counter synchronization.
bogdanm 82:6473597d706e 1273 * - 1 - Software trigger can only be used by MOD and CnV synchronization, and
bogdanm 82:6473597d706e 1274 * hardware triggers can only be used by OUTMASK and FTM counter
bogdanm 82:6473597d706e 1275 * synchronization.
bogdanm 82:6473597d706e 1276 */
bogdanm 82:6473597d706e 1277 //@{
bogdanm 82:6473597d706e 1278 #define BP_FTM_MODE_PWMSYNC (3U) //!< Bit position for FTM_MODE_PWMSYNC.
bogdanm 82:6473597d706e 1279 #define BM_FTM_MODE_PWMSYNC (0x00000008U) //!< Bit mask for FTM_MODE_PWMSYNC.
bogdanm 82:6473597d706e 1280 #define BS_FTM_MODE_PWMSYNC (1U) //!< Bit field size in bits for FTM_MODE_PWMSYNC.
bogdanm 82:6473597d706e 1281
bogdanm 82:6473597d706e 1282 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1283 //! @brief Read current value of the FTM_MODE_PWMSYNC field.
bogdanm 82:6473597d706e 1284 #define BR_FTM_MODE_PWMSYNC(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC))
bogdanm 82:6473597d706e 1285 #endif
bogdanm 82:6473597d706e 1286
bogdanm 82:6473597d706e 1287 //! @brief Format value for bitfield FTM_MODE_PWMSYNC.
bogdanm 82:6473597d706e 1288 #define BF_FTM_MODE_PWMSYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_PWMSYNC), uint32_t) & BM_FTM_MODE_PWMSYNC)
bogdanm 82:6473597d706e 1289
bogdanm 82:6473597d706e 1290 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1291 //! @brief Set the PWMSYNC field to a new value.
bogdanm 82:6473597d706e 1292 #define BW_FTM_MODE_PWMSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC) = (v))
bogdanm 82:6473597d706e 1293 #endif
bogdanm 82:6473597d706e 1294 //@}
bogdanm 82:6473597d706e 1295
bogdanm 82:6473597d706e 1296 /*!
bogdanm 82:6473597d706e 1297 * @name Register FTM_MODE, field CAPTEST[4] (RW)
bogdanm 82:6473597d706e 1298 *
bogdanm 82:6473597d706e 1299 * Enables the capture test mode. This field is write protected. It can be
bogdanm 82:6473597d706e 1300 * written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 1301 *
bogdanm 82:6473597d706e 1302 * Values:
bogdanm 82:6473597d706e 1303 * - 0 - Capture test mode is disabled.
bogdanm 82:6473597d706e 1304 * - 1 - Capture test mode is enabled.
bogdanm 82:6473597d706e 1305 */
bogdanm 82:6473597d706e 1306 //@{
bogdanm 82:6473597d706e 1307 #define BP_FTM_MODE_CAPTEST (4U) //!< Bit position for FTM_MODE_CAPTEST.
bogdanm 82:6473597d706e 1308 #define BM_FTM_MODE_CAPTEST (0x00000010U) //!< Bit mask for FTM_MODE_CAPTEST.
bogdanm 82:6473597d706e 1309 #define BS_FTM_MODE_CAPTEST (1U) //!< Bit field size in bits for FTM_MODE_CAPTEST.
bogdanm 82:6473597d706e 1310
bogdanm 82:6473597d706e 1311 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1312 //! @brief Read current value of the FTM_MODE_CAPTEST field.
bogdanm 82:6473597d706e 1313 #define BR_FTM_MODE_CAPTEST(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST))
bogdanm 82:6473597d706e 1314 #endif
bogdanm 82:6473597d706e 1315
bogdanm 82:6473597d706e 1316 //! @brief Format value for bitfield FTM_MODE_CAPTEST.
bogdanm 82:6473597d706e 1317 #define BF_FTM_MODE_CAPTEST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_CAPTEST), uint32_t) & BM_FTM_MODE_CAPTEST)
bogdanm 82:6473597d706e 1318
bogdanm 82:6473597d706e 1319 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1320 //! @brief Set the CAPTEST field to a new value.
bogdanm 82:6473597d706e 1321 #define BW_FTM_MODE_CAPTEST(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST) = (v))
bogdanm 82:6473597d706e 1322 #endif
bogdanm 82:6473597d706e 1323 //@}
bogdanm 82:6473597d706e 1324
bogdanm 82:6473597d706e 1325 /*!
bogdanm 82:6473597d706e 1326 * @name Register FTM_MODE, field FAULTM[6:5] (RW)
bogdanm 82:6473597d706e 1327 *
bogdanm 82:6473597d706e 1328 * Defines the FTM fault control mode. This field is write protected. It can be
bogdanm 82:6473597d706e 1329 * written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 1330 *
bogdanm 82:6473597d706e 1331 * Values:
bogdanm 82:6473597d706e 1332 * - 00 - Fault control is disabled for all channels.
bogdanm 82:6473597d706e 1333 * - 01 - Fault control is enabled for even channels only (channels 0, 2, 4, and
bogdanm 82:6473597d706e 1334 * 6), and the selected mode is the manual fault clearing.
bogdanm 82:6473597d706e 1335 * - 10 - Fault control is enabled for all channels, and the selected mode is
bogdanm 82:6473597d706e 1336 * the manual fault clearing.
bogdanm 82:6473597d706e 1337 * - 11 - Fault control is enabled for all channels, and the selected mode is
bogdanm 82:6473597d706e 1338 * the automatic fault clearing.
bogdanm 82:6473597d706e 1339 */
bogdanm 82:6473597d706e 1340 //@{
bogdanm 82:6473597d706e 1341 #define BP_FTM_MODE_FAULTM (5U) //!< Bit position for FTM_MODE_FAULTM.
bogdanm 82:6473597d706e 1342 #define BM_FTM_MODE_FAULTM (0x00000060U) //!< Bit mask for FTM_MODE_FAULTM.
bogdanm 82:6473597d706e 1343 #define BS_FTM_MODE_FAULTM (2U) //!< Bit field size in bits for FTM_MODE_FAULTM.
bogdanm 82:6473597d706e 1344
bogdanm 82:6473597d706e 1345 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1346 //! @brief Read current value of the FTM_MODE_FAULTM field.
bogdanm 82:6473597d706e 1347 #define BR_FTM_MODE_FAULTM(x) (HW_FTM_MODE(x).B.FAULTM)
bogdanm 82:6473597d706e 1348 #endif
bogdanm 82:6473597d706e 1349
bogdanm 82:6473597d706e 1350 //! @brief Format value for bitfield FTM_MODE_FAULTM.
bogdanm 82:6473597d706e 1351 #define BF_FTM_MODE_FAULTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FAULTM), uint32_t) & BM_FTM_MODE_FAULTM)
bogdanm 82:6473597d706e 1352
bogdanm 82:6473597d706e 1353 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1354 //! @brief Set the FAULTM field to a new value.
bogdanm 82:6473597d706e 1355 #define BW_FTM_MODE_FAULTM(x, v) (HW_FTM_MODE_WR(x, (HW_FTM_MODE_RD(x) & ~BM_FTM_MODE_FAULTM) | BF_FTM_MODE_FAULTM(v)))
bogdanm 82:6473597d706e 1356 #endif
bogdanm 82:6473597d706e 1357 //@}
bogdanm 82:6473597d706e 1358
bogdanm 82:6473597d706e 1359 /*!
bogdanm 82:6473597d706e 1360 * @name Register FTM_MODE, field FAULTIE[7] (RW)
bogdanm 82:6473597d706e 1361 *
bogdanm 82:6473597d706e 1362 * Enables the generation of an interrupt when a fault is detected by FTM and
bogdanm 82:6473597d706e 1363 * the FTM fault control is enabled.
bogdanm 82:6473597d706e 1364 *
bogdanm 82:6473597d706e 1365 * Values:
bogdanm 82:6473597d706e 1366 * - 0 - Fault control interrupt is disabled.
bogdanm 82:6473597d706e 1367 * - 1 - Fault control interrupt is enabled.
bogdanm 82:6473597d706e 1368 */
bogdanm 82:6473597d706e 1369 //@{
bogdanm 82:6473597d706e 1370 #define BP_FTM_MODE_FAULTIE (7U) //!< Bit position for FTM_MODE_FAULTIE.
bogdanm 82:6473597d706e 1371 #define BM_FTM_MODE_FAULTIE (0x00000080U) //!< Bit mask for FTM_MODE_FAULTIE.
bogdanm 82:6473597d706e 1372 #define BS_FTM_MODE_FAULTIE (1U) //!< Bit field size in bits for FTM_MODE_FAULTIE.
bogdanm 82:6473597d706e 1373
bogdanm 82:6473597d706e 1374 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1375 //! @brief Read current value of the FTM_MODE_FAULTIE field.
bogdanm 82:6473597d706e 1376 #define BR_FTM_MODE_FAULTIE(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE))
bogdanm 82:6473597d706e 1377 #endif
bogdanm 82:6473597d706e 1378
bogdanm 82:6473597d706e 1379 //! @brief Format value for bitfield FTM_MODE_FAULTIE.
bogdanm 82:6473597d706e 1380 #define BF_FTM_MODE_FAULTIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FAULTIE), uint32_t) & BM_FTM_MODE_FAULTIE)
bogdanm 82:6473597d706e 1381
bogdanm 82:6473597d706e 1382 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1383 //! @brief Set the FAULTIE field to a new value.
bogdanm 82:6473597d706e 1384 #define BW_FTM_MODE_FAULTIE(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE) = (v))
bogdanm 82:6473597d706e 1385 #endif
bogdanm 82:6473597d706e 1386 //@}
bogdanm 82:6473597d706e 1387
bogdanm 82:6473597d706e 1388 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1389 // HW_FTM_SYNC - Synchronization
bogdanm 82:6473597d706e 1390 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1391
bogdanm 82:6473597d706e 1392 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1393 /*!
bogdanm 82:6473597d706e 1394 * @brief HW_FTM_SYNC - Synchronization (RW)
bogdanm 82:6473597d706e 1395 *
bogdanm 82:6473597d706e 1396 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 1397 *
bogdanm 82:6473597d706e 1398 * This register configures the PWM synchronization. A synchronization event can
bogdanm 82:6473597d706e 1399 * perform the synchronized update of MOD, CV, and OUTMASK registers with the
bogdanm 82:6473597d706e 1400 * value of their write buffer and the FTM counter initialization. The software
bogdanm 82:6473597d706e 1401 * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
bogdanm 82:6473597d706e 1402 * potential conflict if used together when SYNCMODE = 0. Use only hardware or
bogdanm 82:6473597d706e 1403 * software triggers but not both at the same time, otherwise unpredictable behavior
bogdanm 82:6473597d706e 1404 * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
bogdanm 82:6473597d706e 1405 * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
bogdanm 82:6473597d706e 1406 * all enabled channels simultaneously. The use of the loading point selection
bogdanm 82:6473597d706e 1407 * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
bogdanm 82:6473597d706e 1408 * bits, is likely to result in unpredictable behavior. The synchronization
bogdanm 82:6473597d706e 1409 * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
bogdanm 82:6473597d706e 1410 * register) bits. See PWM synchronization.
bogdanm 82:6473597d706e 1411 */
bogdanm 82:6473597d706e 1412 typedef union _hw_ftm_sync
bogdanm 82:6473597d706e 1413 {
bogdanm 82:6473597d706e 1414 uint32_t U;
bogdanm 82:6473597d706e 1415 struct _hw_ftm_sync_bitfields
bogdanm 82:6473597d706e 1416 {
bogdanm 82:6473597d706e 1417 uint32_t CNTMIN : 1; //!< [0] Minimum Loading Point Enable
bogdanm 82:6473597d706e 1418 uint32_t CNTMAX : 1; //!< [1] Maximum Loading Point Enable
bogdanm 82:6473597d706e 1419 uint32_t REINIT : 1; //!< [2] FTM Counter Reinitialization By
bogdanm 82:6473597d706e 1420 //! Synchronization (FTM counter synchronization)
bogdanm 82:6473597d706e 1421 uint32_t SYNCHOM : 1; //!< [3] Output Mask Synchronization
bogdanm 82:6473597d706e 1422 uint32_t TRIG0 : 1; //!< [4] PWM Synchronization Hardware Trigger 0
bogdanm 82:6473597d706e 1423 uint32_t TRIG1 : 1; //!< [5] PWM Synchronization Hardware Trigger 1
bogdanm 82:6473597d706e 1424 uint32_t TRIG2 : 1; //!< [6] PWM Synchronization Hardware Trigger 2
bogdanm 82:6473597d706e 1425 uint32_t SWSYNC : 1; //!< [7] PWM Synchronization Software Trigger
bogdanm 82:6473597d706e 1426 uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm 82:6473597d706e 1427 } B;
bogdanm 82:6473597d706e 1428 } hw_ftm_sync_t;
bogdanm 82:6473597d706e 1429 #endif
bogdanm 82:6473597d706e 1430
bogdanm 82:6473597d706e 1431 /*!
bogdanm 82:6473597d706e 1432 * @name Constants and macros for entire FTM_SYNC register
bogdanm 82:6473597d706e 1433 */
bogdanm 82:6473597d706e 1434 //@{
bogdanm 82:6473597d706e 1435 #define HW_FTM_SYNC_ADDR(x) (REGS_FTM_BASE(x) + 0x58U)
bogdanm 82:6473597d706e 1436
bogdanm 82:6473597d706e 1437 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1438 #define HW_FTM_SYNC(x) (*(__IO hw_ftm_sync_t *) HW_FTM_SYNC_ADDR(x))
bogdanm 82:6473597d706e 1439 #define HW_FTM_SYNC_RD(x) (HW_FTM_SYNC(x).U)
bogdanm 82:6473597d706e 1440 #define HW_FTM_SYNC_WR(x, v) (HW_FTM_SYNC(x).U = (v))
bogdanm 82:6473597d706e 1441 #define HW_FTM_SYNC_SET(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) | (v)))
bogdanm 82:6473597d706e 1442 #define HW_FTM_SYNC_CLR(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) & ~(v)))
bogdanm 82:6473597d706e 1443 #define HW_FTM_SYNC_TOG(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) ^ (v)))
bogdanm 82:6473597d706e 1444 #endif
bogdanm 82:6473597d706e 1445 //@}
bogdanm 82:6473597d706e 1446
bogdanm 82:6473597d706e 1447 /*
bogdanm 82:6473597d706e 1448 * Constants & macros for individual FTM_SYNC bitfields
bogdanm 82:6473597d706e 1449 */
bogdanm 82:6473597d706e 1450
bogdanm 82:6473597d706e 1451 /*!
bogdanm 82:6473597d706e 1452 * @name Register FTM_SYNC, field CNTMIN[0] (RW)
bogdanm 82:6473597d706e 1453 *
bogdanm 82:6473597d706e 1454 * Selects the minimum loading point to PWM synchronization. See Boundary cycle
bogdanm 82:6473597d706e 1455 * and loading points. If CNTMIN is one, the selected loading point is when the
bogdanm 82:6473597d706e 1456 * FTM counter reaches its minimum value (CNTIN register).
bogdanm 82:6473597d706e 1457 *
bogdanm 82:6473597d706e 1458 * Values:
bogdanm 82:6473597d706e 1459 * - 0 - The minimum loading point is disabled.
bogdanm 82:6473597d706e 1460 * - 1 - The minimum loading point is enabled.
bogdanm 82:6473597d706e 1461 */
bogdanm 82:6473597d706e 1462 //@{
bogdanm 82:6473597d706e 1463 #define BP_FTM_SYNC_CNTMIN (0U) //!< Bit position for FTM_SYNC_CNTMIN.
bogdanm 82:6473597d706e 1464 #define BM_FTM_SYNC_CNTMIN (0x00000001U) //!< Bit mask for FTM_SYNC_CNTMIN.
bogdanm 82:6473597d706e 1465 #define BS_FTM_SYNC_CNTMIN (1U) //!< Bit field size in bits for FTM_SYNC_CNTMIN.
bogdanm 82:6473597d706e 1466
bogdanm 82:6473597d706e 1467 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1468 //! @brief Read current value of the FTM_SYNC_CNTMIN field.
bogdanm 82:6473597d706e 1469 #define BR_FTM_SYNC_CNTMIN(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN))
bogdanm 82:6473597d706e 1470 #endif
bogdanm 82:6473597d706e 1471
bogdanm 82:6473597d706e 1472 //! @brief Format value for bitfield FTM_SYNC_CNTMIN.
bogdanm 82:6473597d706e 1473 #define BF_FTM_SYNC_CNTMIN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_CNTMIN), uint32_t) & BM_FTM_SYNC_CNTMIN)
bogdanm 82:6473597d706e 1474
bogdanm 82:6473597d706e 1475 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1476 //! @brief Set the CNTMIN field to a new value.
bogdanm 82:6473597d706e 1477 #define BW_FTM_SYNC_CNTMIN(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN) = (v))
bogdanm 82:6473597d706e 1478 #endif
bogdanm 82:6473597d706e 1479 //@}
bogdanm 82:6473597d706e 1480
bogdanm 82:6473597d706e 1481 /*!
bogdanm 82:6473597d706e 1482 * @name Register FTM_SYNC, field CNTMAX[1] (RW)
bogdanm 82:6473597d706e 1483 *
bogdanm 82:6473597d706e 1484 * Selects the maximum loading point to PWM synchronization. See Boundary cycle
bogdanm 82:6473597d706e 1485 * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
bogdanm 82:6473597d706e 1486 * counter reaches its maximum value (MOD register).
bogdanm 82:6473597d706e 1487 *
bogdanm 82:6473597d706e 1488 * Values:
bogdanm 82:6473597d706e 1489 * - 0 - The maximum loading point is disabled.
bogdanm 82:6473597d706e 1490 * - 1 - The maximum loading point is enabled.
bogdanm 82:6473597d706e 1491 */
bogdanm 82:6473597d706e 1492 //@{
bogdanm 82:6473597d706e 1493 #define BP_FTM_SYNC_CNTMAX (1U) //!< Bit position for FTM_SYNC_CNTMAX.
bogdanm 82:6473597d706e 1494 #define BM_FTM_SYNC_CNTMAX (0x00000002U) //!< Bit mask for FTM_SYNC_CNTMAX.
bogdanm 82:6473597d706e 1495 #define BS_FTM_SYNC_CNTMAX (1U) //!< Bit field size in bits for FTM_SYNC_CNTMAX.
bogdanm 82:6473597d706e 1496
bogdanm 82:6473597d706e 1497 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1498 //! @brief Read current value of the FTM_SYNC_CNTMAX field.
bogdanm 82:6473597d706e 1499 #define BR_FTM_SYNC_CNTMAX(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX))
bogdanm 82:6473597d706e 1500 #endif
bogdanm 82:6473597d706e 1501
bogdanm 82:6473597d706e 1502 //! @brief Format value for bitfield FTM_SYNC_CNTMAX.
bogdanm 82:6473597d706e 1503 #define BF_FTM_SYNC_CNTMAX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_CNTMAX), uint32_t) & BM_FTM_SYNC_CNTMAX)
bogdanm 82:6473597d706e 1504
bogdanm 82:6473597d706e 1505 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1506 //! @brief Set the CNTMAX field to a new value.
bogdanm 82:6473597d706e 1507 #define BW_FTM_SYNC_CNTMAX(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX) = (v))
bogdanm 82:6473597d706e 1508 #endif
bogdanm 82:6473597d706e 1509 //@}
bogdanm 82:6473597d706e 1510
bogdanm 82:6473597d706e 1511 /*!
bogdanm 82:6473597d706e 1512 * @name Register FTM_SYNC, field REINIT[2] (RW)
bogdanm 82:6473597d706e 1513 *
bogdanm 82:6473597d706e 1514 * Determines if the FTM counter is reinitialized when the selected trigger for
bogdanm 82:6473597d706e 1515 * the synchronization is detected. The REINIT bit configures the synchronization
bogdanm 82:6473597d706e 1516 * when SYNCMODE is zero.
bogdanm 82:6473597d706e 1517 *
bogdanm 82:6473597d706e 1518 * Values:
bogdanm 82:6473597d706e 1519 * - 0 - FTM counter continues to count normally.
bogdanm 82:6473597d706e 1520 * - 1 - FTM counter is updated with its initial value when the selected trigger
bogdanm 82:6473597d706e 1521 * is detected.
bogdanm 82:6473597d706e 1522 */
bogdanm 82:6473597d706e 1523 //@{
bogdanm 82:6473597d706e 1524 #define BP_FTM_SYNC_REINIT (2U) //!< Bit position for FTM_SYNC_REINIT.
bogdanm 82:6473597d706e 1525 #define BM_FTM_SYNC_REINIT (0x00000004U) //!< Bit mask for FTM_SYNC_REINIT.
bogdanm 82:6473597d706e 1526 #define BS_FTM_SYNC_REINIT (1U) //!< Bit field size in bits for FTM_SYNC_REINIT.
bogdanm 82:6473597d706e 1527
bogdanm 82:6473597d706e 1528 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1529 //! @brief Read current value of the FTM_SYNC_REINIT field.
bogdanm 82:6473597d706e 1530 #define BR_FTM_SYNC_REINIT(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT))
bogdanm 82:6473597d706e 1531 #endif
bogdanm 82:6473597d706e 1532
bogdanm 82:6473597d706e 1533 //! @brief Format value for bitfield FTM_SYNC_REINIT.
bogdanm 82:6473597d706e 1534 #define BF_FTM_SYNC_REINIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_REINIT), uint32_t) & BM_FTM_SYNC_REINIT)
bogdanm 82:6473597d706e 1535
bogdanm 82:6473597d706e 1536 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1537 //! @brief Set the REINIT field to a new value.
bogdanm 82:6473597d706e 1538 #define BW_FTM_SYNC_REINIT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT) = (v))
bogdanm 82:6473597d706e 1539 #endif
bogdanm 82:6473597d706e 1540 //@}
bogdanm 82:6473597d706e 1541
bogdanm 82:6473597d706e 1542 /*!
bogdanm 82:6473597d706e 1543 * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
bogdanm 82:6473597d706e 1544 *
bogdanm 82:6473597d706e 1545 * Selects when the OUTMASK register is updated with the value of its buffer.
bogdanm 82:6473597d706e 1546 *
bogdanm 82:6473597d706e 1547 * Values:
bogdanm 82:6473597d706e 1548 * - 0 - OUTMASK register is updated with the value of its buffer in all rising
bogdanm 82:6473597d706e 1549 * edges of the system clock.
bogdanm 82:6473597d706e 1550 * - 1 - OUTMASK register is updated with the value of its buffer only by the
bogdanm 82:6473597d706e 1551 * PWM synchronization.
bogdanm 82:6473597d706e 1552 */
bogdanm 82:6473597d706e 1553 //@{
bogdanm 82:6473597d706e 1554 #define BP_FTM_SYNC_SYNCHOM (3U) //!< Bit position for FTM_SYNC_SYNCHOM.
bogdanm 82:6473597d706e 1555 #define BM_FTM_SYNC_SYNCHOM (0x00000008U) //!< Bit mask for FTM_SYNC_SYNCHOM.
bogdanm 82:6473597d706e 1556 #define BS_FTM_SYNC_SYNCHOM (1U) //!< Bit field size in bits for FTM_SYNC_SYNCHOM.
bogdanm 82:6473597d706e 1557
bogdanm 82:6473597d706e 1558 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1559 //! @brief Read current value of the FTM_SYNC_SYNCHOM field.
bogdanm 82:6473597d706e 1560 #define BR_FTM_SYNC_SYNCHOM(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM))
bogdanm 82:6473597d706e 1561 #endif
bogdanm 82:6473597d706e 1562
bogdanm 82:6473597d706e 1563 //! @brief Format value for bitfield FTM_SYNC_SYNCHOM.
bogdanm 82:6473597d706e 1564 #define BF_FTM_SYNC_SYNCHOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_SYNCHOM), uint32_t) & BM_FTM_SYNC_SYNCHOM)
bogdanm 82:6473597d706e 1565
bogdanm 82:6473597d706e 1566 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1567 //! @brief Set the SYNCHOM field to a new value.
bogdanm 82:6473597d706e 1568 #define BW_FTM_SYNC_SYNCHOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM) = (v))
bogdanm 82:6473597d706e 1569 #endif
bogdanm 82:6473597d706e 1570 //@}
bogdanm 82:6473597d706e 1571
bogdanm 82:6473597d706e 1572 /*!
bogdanm 82:6473597d706e 1573 * @name Register FTM_SYNC, field TRIG0[4] (RW)
bogdanm 82:6473597d706e 1574 *
bogdanm 82:6473597d706e 1575 * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
bogdanm 82:6473597d706e 1576 * occurs when a rising edge is detected at the trigger 0 input signal.
bogdanm 82:6473597d706e 1577 *
bogdanm 82:6473597d706e 1578 * Values:
bogdanm 82:6473597d706e 1579 * - 0 - Trigger is disabled.
bogdanm 82:6473597d706e 1580 * - 1 - Trigger is enabled.
bogdanm 82:6473597d706e 1581 */
bogdanm 82:6473597d706e 1582 //@{
bogdanm 82:6473597d706e 1583 #define BP_FTM_SYNC_TRIG0 (4U) //!< Bit position for FTM_SYNC_TRIG0.
bogdanm 82:6473597d706e 1584 #define BM_FTM_SYNC_TRIG0 (0x00000010U) //!< Bit mask for FTM_SYNC_TRIG0.
bogdanm 82:6473597d706e 1585 #define BS_FTM_SYNC_TRIG0 (1U) //!< Bit field size in bits for FTM_SYNC_TRIG0.
bogdanm 82:6473597d706e 1586
bogdanm 82:6473597d706e 1587 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1588 //! @brief Read current value of the FTM_SYNC_TRIG0 field.
bogdanm 82:6473597d706e 1589 #define BR_FTM_SYNC_TRIG0(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0))
bogdanm 82:6473597d706e 1590 #endif
bogdanm 82:6473597d706e 1591
bogdanm 82:6473597d706e 1592 //! @brief Format value for bitfield FTM_SYNC_TRIG0.
bogdanm 82:6473597d706e 1593 #define BF_FTM_SYNC_TRIG0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG0), uint32_t) & BM_FTM_SYNC_TRIG0)
bogdanm 82:6473597d706e 1594
bogdanm 82:6473597d706e 1595 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1596 //! @brief Set the TRIG0 field to a new value.
bogdanm 82:6473597d706e 1597 #define BW_FTM_SYNC_TRIG0(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0) = (v))
bogdanm 82:6473597d706e 1598 #endif
bogdanm 82:6473597d706e 1599 //@}
bogdanm 82:6473597d706e 1600
bogdanm 82:6473597d706e 1601 /*!
bogdanm 82:6473597d706e 1602 * @name Register FTM_SYNC, field TRIG1[5] (RW)
bogdanm 82:6473597d706e 1603 *
bogdanm 82:6473597d706e 1604 * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
bogdanm 82:6473597d706e 1605 * happens when a rising edge is detected at the trigger 1 input signal.
bogdanm 82:6473597d706e 1606 *
bogdanm 82:6473597d706e 1607 * Values:
bogdanm 82:6473597d706e 1608 * - 0 - Trigger is disabled.
bogdanm 82:6473597d706e 1609 * - 1 - Trigger is enabled.
bogdanm 82:6473597d706e 1610 */
bogdanm 82:6473597d706e 1611 //@{
bogdanm 82:6473597d706e 1612 #define BP_FTM_SYNC_TRIG1 (5U) //!< Bit position for FTM_SYNC_TRIG1.
bogdanm 82:6473597d706e 1613 #define BM_FTM_SYNC_TRIG1 (0x00000020U) //!< Bit mask for FTM_SYNC_TRIG1.
bogdanm 82:6473597d706e 1614 #define BS_FTM_SYNC_TRIG1 (1U) //!< Bit field size in bits for FTM_SYNC_TRIG1.
bogdanm 82:6473597d706e 1615
bogdanm 82:6473597d706e 1616 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1617 //! @brief Read current value of the FTM_SYNC_TRIG1 field.
bogdanm 82:6473597d706e 1618 #define BR_FTM_SYNC_TRIG1(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1))
bogdanm 82:6473597d706e 1619 #endif
bogdanm 82:6473597d706e 1620
bogdanm 82:6473597d706e 1621 //! @brief Format value for bitfield FTM_SYNC_TRIG1.
bogdanm 82:6473597d706e 1622 #define BF_FTM_SYNC_TRIG1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG1), uint32_t) & BM_FTM_SYNC_TRIG1)
bogdanm 82:6473597d706e 1623
bogdanm 82:6473597d706e 1624 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1625 //! @brief Set the TRIG1 field to a new value.
bogdanm 82:6473597d706e 1626 #define BW_FTM_SYNC_TRIG1(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1) = (v))
bogdanm 82:6473597d706e 1627 #endif
bogdanm 82:6473597d706e 1628 //@}
bogdanm 82:6473597d706e 1629
bogdanm 82:6473597d706e 1630 /*!
bogdanm 82:6473597d706e 1631 * @name Register FTM_SYNC, field TRIG2[6] (RW)
bogdanm 82:6473597d706e 1632 *
bogdanm 82:6473597d706e 1633 * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
bogdanm 82:6473597d706e 1634 * happens when a rising edge is detected at the trigger 2 input signal.
bogdanm 82:6473597d706e 1635 *
bogdanm 82:6473597d706e 1636 * Values:
bogdanm 82:6473597d706e 1637 * - 0 - Trigger is disabled.
bogdanm 82:6473597d706e 1638 * - 1 - Trigger is enabled.
bogdanm 82:6473597d706e 1639 */
bogdanm 82:6473597d706e 1640 //@{
bogdanm 82:6473597d706e 1641 #define BP_FTM_SYNC_TRIG2 (6U) //!< Bit position for FTM_SYNC_TRIG2.
bogdanm 82:6473597d706e 1642 #define BM_FTM_SYNC_TRIG2 (0x00000040U) //!< Bit mask for FTM_SYNC_TRIG2.
bogdanm 82:6473597d706e 1643 #define BS_FTM_SYNC_TRIG2 (1U) //!< Bit field size in bits for FTM_SYNC_TRIG2.
bogdanm 82:6473597d706e 1644
bogdanm 82:6473597d706e 1645 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1646 //! @brief Read current value of the FTM_SYNC_TRIG2 field.
bogdanm 82:6473597d706e 1647 #define BR_FTM_SYNC_TRIG2(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2))
bogdanm 82:6473597d706e 1648 #endif
bogdanm 82:6473597d706e 1649
bogdanm 82:6473597d706e 1650 //! @brief Format value for bitfield FTM_SYNC_TRIG2.
bogdanm 82:6473597d706e 1651 #define BF_FTM_SYNC_TRIG2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG2), uint32_t) & BM_FTM_SYNC_TRIG2)
bogdanm 82:6473597d706e 1652
bogdanm 82:6473597d706e 1653 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1654 //! @brief Set the TRIG2 field to a new value.
bogdanm 82:6473597d706e 1655 #define BW_FTM_SYNC_TRIG2(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2) = (v))
bogdanm 82:6473597d706e 1656 #endif
bogdanm 82:6473597d706e 1657 //@}
bogdanm 82:6473597d706e 1658
bogdanm 82:6473597d706e 1659 /*!
bogdanm 82:6473597d706e 1660 * @name Register FTM_SYNC, field SWSYNC[7] (RW)
bogdanm 82:6473597d706e 1661 *
bogdanm 82:6473597d706e 1662 * Selects the software trigger as the PWM synchronization trigger. The software
bogdanm 82:6473597d706e 1663 * trigger happens when a 1 is written to SWSYNC bit.
bogdanm 82:6473597d706e 1664 *
bogdanm 82:6473597d706e 1665 * Values:
bogdanm 82:6473597d706e 1666 * - 0 - Software trigger is not selected.
bogdanm 82:6473597d706e 1667 * - 1 - Software trigger is selected.
bogdanm 82:6473597d706e 1668 */
bogdanm 82:6473597d706e 1669 //@{
bogdanm 82:6473597d706e 1670 #define BP_FTM_SYNC_SWSYNC (7U) //!< Bit position for FTM_SYNC_SWSYNC.
bogdanm 82:6473597d706e 1671 #define BM_FTM_SYNC_SWSYNC (0x00000080U) //!< Bit mask for FTM_SYNC_SWSYNC.
bogdanm 82:6473597d706e 1672 #define BS_FTM_SYNC_SWSYNC (1U) //!< Bit field size in bits for FTM_SYNC_SWSYNC.
bogdanm 82:6473597d706e 1673
bogdanm 82:6473597d706e 1674 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1675 //! @brief Read current value of the FTM_SYNC_SWSYNC field.
bogdanm 82:6473597d706e 1676 #define BR_FTM_SYNC_SWSYNC(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC))
bogdanm 82:6473597d706e 1677 #endif
bogdanm 82:6473597d706e 1678
bogdanm 82:6473597d706e 1679 //! @brief Format value for bitfield FTM_SYNC_SWSYNC.
bogdanm 82:6473597d706e 1680 #define BF_FTM_SYNC_SWSYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_SWSYNC), uint32_t) & BM_FTM_SYNC_SWSYNC)
bogdanm 82:6473597d706e 1681
bogdanm 82:6473597d706e 1682 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1683 //! @brief Set the SWSYNC field to a new value.
bogdanm 82:6473597d706e 1684 #define BW_FTM_SYNC_SWSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC) = (v))
bogdanm 82:6473597d706e 1685 #endif
bogdanm 82:6473597d706e 1686 //@}
bogdanm 82:6473597d706e 1687
bogdanm 82:6473597d706e 1688 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1689 // HW_FTM_OUTINIT - Initial State For Channels Output
bogdanm 82:6473597d706e 1690 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1691
bogdanm 82:6473597d706e 1692 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1693 /*!
bogdanm 82:6473597d706e 1694 * @brief HW_FTM_OUTINIT - Initial State For Channels Output (RW)
bogdanm 82:6473597d706e 1695 *
bogdanm 82:6473597d706e 1696 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 1697 */
bogdanm 82:6473597d706e 1698 typedef union _hw_ftm_outinit
bogdanm 82:6473597d706e 1699 {
bogdanm 82:6473597d706e 1700 uint32_t U;
bogdanm 82:6473597d706e 1701 struct _hw_ftm_outinit_bitfields
bogdanm 82:6473597d706e 1702 {
bogdanm 82:6473597d706e 1703 uint32_t CH0OI : 1; //!< [0] Channel 0 Output Initialization Value
bogdanm 82:6473597d706e 1704 uint32_t CH1OI : 1; //!< [1] Channel 1 Output Initialization Value
bogdanm 82:6473597d706e 1705 uint32_t CH2OI : 1; //!< [2] Channel 2 Output Initialization Value
bogdanm 82:6473597d706e 1706 uint32_t CH3OI : 1; //!< [3] Channel 3 Output Initialization Value
bogdanm 82:6473597d706e 1707 uint32_t CH4OI : 1; //!< [4] Channel 4 Output Initialization Value
bogdanm 82:6473597d706e 1708 uint32_t CH5OI : 1; //!< [5] Channel 5 Output Initialization Value
bogdanm 82:6473597d706e 1709 uint32_t CH6OI : 1; //!< [6] Channel 6 Output Initialization Value
bogdanm 82:6473597d706e 1710 uint32_t CH7OI : 1; //!< [7] Channel 7 Output Initialization Value
bogdanm 82:6473597d706e 1711 uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm 82:6473597d706e 1712 } B;
bogdanm 82:6473597d706e 1713 } hw_ftm_outinit_t;
bogdanm 82:6473597d706e 1714 #endif
bogdanm 82:6473597d706e 1715
bogdanm 82:6473597d706e 1716 /*!
bogdanm 82:6473597d706e 1717 * @name Constants and macros for entire FTM_OUTINIT register
bogdanm 82:6473597d706e 1718 */
bogdanm 82:6473597d706e 1719 //@{
bogdanm 82:6473597d706e 1720 #define HW_FTM_OUTINIT_ADDR(x) (REGS_FTM_BASE(x) + 0x5CU)
bogdanm 82:6473597d706e 1721
bogdanm 82:6473597d706e 1722 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1723 #define HW_FTM_OUTINIT(x) (*(__IO hw_ftm_outinit_t *) HW_FTM_OUTINIT_ADDR(x))
bogdanm 82:6473597d706e 1724 #define HW_FTM_OUTINIT_RD(x) (HW_FTM_OUTINIT(x).U)
bogdanm 82:6473597d706e 1725 #define HW_FTM_OUTINIT_WR(x, v) (HW_FTM_OUTINIT(x).U = (v))
bogdanm 82:6473597d706e 1726 #define HW_FTM_OUTINIT_SET(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) | (v)))
bogdanm 82:6473597d706e 1727 #define HW_FTM_OUTINIT_CLR(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) & ~(v)))
bogdanm 82:6473597d706e 1728 #define HW_FTM_OUTINIT_TOG(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) ^ (v)))
bogdanm 82:6473597d706e 1729 #endif
bogdanm 82:6473597d706e 1730 //@}
bogdanm 82:6473597d706e 1731
bogdanm 82:6473597d706e 1732 /*
bogdanm 82:6473597d706e 1733 * Constants & macros for individual FTM_OUTINIT bitfields
bogdanm 82:6473597d706e 1734 */
bogdanm 82:6473597d706e 1735
bogdanm 82:6473597d706e 1736 /*!
bogdanm 82:6473597d706e 1737 * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
bogdanm 82:6473597d706e 1738 *
bogdanm 82:6473597d706e 1739 * Selects the value that is forced into the channel output when the
bogdanm 82:6473597d706e 1740 * initialization occurs.
bogdanm 82:6473597d706e 1741 *
bogdanm 82:6473597d706e 1742 * Values:
bogdanm 82:6473597d706e 1743 * - 0 - The initialization value is 0.
bogdanm 82:6473597d706e 1744 * - 1 - The initialization value is 1.
bogdanm 82:6473597d706e 1745 */
bogdanm 82:6473597d706e 1746 //@{
bogdanm 82:6473597d706e 1747 #define BP_FTM_OUTINIT_CH0OI (0U) //!< Bit position for FTM_OUTINIT_CH0OI.
bogdanm 82:6473597d706e 1748 #define BM_FTM_OUTINIT_CH0OI (0x00000001U) //!< Bit mask for FTM_OUTINIT_CH0OI.
bogdanm 82:6473597d706e 1749 #define BS_FTM_OUTINIT_CH0OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH0OI.
bogdanm 82:6473597d706e 1750
bogdanm 82:6473597d706e 1751 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1752 //! @brief Read current value of the FTM_OUTINIT_CH0OI field.
bogdanm 82:6473597d706e 1753 #define BR_FTM_OUTINIT_CH0OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI))
bogdanm 82:6473597d706e 1754 #endif
bogdanm 82:6473597d706e 1755
bogdanm 82:6473597d706e 1756 //! @brief Format value for bitfield FTM_OUTINIT_CH0OI.
bogdanm 82:6473597d706e 1757 #define BF_FTM_OUTINIT_CH0OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH0OI), uint32_t) & BM_FTM_OUTINIT_CH0OI)
bogdanm 82:6473597d706e 1758
bogdanm 82:6473597d706e 1759 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1760 //! @brief Set the CH0OI field to a new value.
bogdanm 82:6473597d706e 1761 #define BW_FTM_OUTINIT_CH0OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI) = (v))
bogdanm 82:6473597d706e 1762 #endif
bogdanm 82:6473597d706e 1763 //@}
bogdanm 82:6473597d706e 1764
bogdanm 82:6473597d706e 1765 /*!
bogdanm 82:6473597d706e 1766 * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
bogdanm 82:6473597d706e 1767 *
bogdanm 82:6473597d706e 1768 * Selects the value that is forced into the channel output when the
bogdanm 82:6473597d706e 1769 * initialization occurs.
bogdanm 82:6473597d706e 1770 *
bogdanm 82:6473597d706e 1771 * Values:
bogdanm 82:6473597d706e 1772 * - 0 - The initialization value is 0.
bogdanm 82:6473597d706e 1773 * - 1 - The initialization value is 1.
bogdanm 82:6473597d706e 1774 */
bogdanm 82:6473597d706e 1775 //@{
bogdanm 82:6473597d706e 1776 #define BP_FTM_OUTINIT_CH1OI (1U) //!< Bit position for FTM_OUTINIT_CH1OI.
bogdanm 82:6473597d706e 1777 #define BM_FTM_OUTINIT_CH1OI (0x00000002U) //!< Bit mask for FTM_OUTINIT_CH1OI.
bogdanm 82:6473597d706e 1778 #define BS_FTM_OUTINIT_CH1OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH1OI.
bogdanm 82:6473597d706e 1779
bogdanm 82:6473597d706e 1780 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1781 //! @brief Read current value of the FTM_OUTINIT_CH1OI field.
bogdanm 82:6473597d706e 1782 #define BR_FTM_OUTINIT_CH1OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI))
bogdanm 82:6473597d706e 1783 #endif
bogdanm 82:6473597d706e 1784
bogdanm 82:6473597d706e 1785 //! @brief Format value for bitfield FTM_OUTINIT_CH1OI.
bogdanm 82:6473597d706e 1786 #define BF_FTM_OUTINIT_CH1OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH1OI), uint32_t) & BM_FTM_OUTINIT_CH1OI)
bogdanm 82:6473597d706e 1787
bogdanm 82:6473597d706e 1788 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1789 //! @brief Set the CH1OI field to a new value.
bogdanm 82:6473597d706e 1790 #define BW_FTM_OUTINIT_CH1OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI) = (v))
bogdanm 82:6473597d706e 1791 #endif
bogdanm 82:6473597d706e 1792 //@}
bogdanm 82:6473597d706e 1793
bogdanm 82:6473597d706e 1794 /*!
bogdanm 82:6473597d706e 1795 * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
bogdanm 82:6473597d706e 1796 *
bogdanm 82:6473597d706e 1797 * Selects the value that is forced into the channel output when the
bogdanm 82:6473597d706e 1798 * initialization occurs.
bogdanm 82:6473597d706e 1799 *
bogdanm 82:6473597d706e 1800 * Values:
bogdanm 82:6473597d706e 1801 * - 0 - The initialization value is 0.
bogdanm 82:6473597d706e 1802 * - 1 - The initialization value is 1.
bogdanm 82:6473597d706e 1803 */
bogdanm 82:6473597d706e 1804 //@{
bogdanm 82:6473597d706e 1805 #define BP_FTM_OUTINIT_CH2OI (2U) //!< Bit position for FTM_OUTINIT_CH2OI.
bogdanm 82:6473597d706e 1806 #define BM_FTM_OUTINIT_CH2OI (0x00000004U) //!< Bit mask for FTM_OUTINIT_CH2OI.
bogdanm 82:6473597d706e 1807 #define BS_FTM_OUTINIT_CH2OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH2OI.
bogdanm 82:6473597d706e 1808
bogdanm 82:6473597d706e 1809 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1810 //! @brief Read current value of the FTM_OUTINIT_CH2OI field.
bogdanm 82:6473597d706e 1811 #define BR_FTM_OUTINIT_CH2OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI))
bogdanm 82:6473597d706e 1812 #endif
bogdanm 82:6473597d706e 1813
bogdanm 82:6473597d706e 1814 //! @brief Format value for bitfield FTM_OUTINIT_CH2OI.
bogdanm 82:6473597d706e 1815 #define BF_FTM_OUTINIT_CH2OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH2OI), uint32_t) & BM_FTM_OUTINIT_CH2OI)
bogdanm 82:6473597d706e 1816
bogdanm 82:6473597d706e 1817 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1818 //! @brief Set the CH2OI field to a new value.
bogdanm 82:6473597d706e 1819 #define BW_FTM_OUTINIT_CH2OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI) = (v))
bogdanm 82:6473597d706e 1820 #endif
bogdanm 82:6473597d706e 1821 //@}
bogdanm 82:6473597d706e 1822
bogdanm 82:6473597d706e 1823 /*!
bogdanm 82:6473597d706e 1824 * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
bogdanm 82:6473597d706e 1825 *
bogdanm 82:6473597d706e 1826 * Selects the value that is forced into the channel output when the
bogdanm 82:6473597d706e 1827 * initialization occurs.
bogdanm 82:6473597d706e 1828 *
bogdanm 82:6473597d706e 1829 * Values:
bogdanm 82:6473597d706e 1830 * - 0 - The initialization value is 0.
bogdanm 82:6473597d706e 1831 * - 1 - The initialization value is 1.
bogdanm 82:6473597d706e 1832 */
bogdanm 82:6473597d706e 1833 //@{
bogdanm 82:6473597d706e 1834 #define BP_FTM_OUTINIT_CH3OI (3U) //!< Bit position for FTM_OUTINIT_CH3OI.
bogdanm 82:6473597d706e 1835 #define BM_FTM_OUTINIT_CH3OI (0x00000008U) //!< Bit mask for FTM_OUTINIT_CH3OI.
bogdanm 82:6473597d706e 1836 #define BS_FTM_OUTINIT_CH3OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH3OI.
bogdanm 82:6473597d706e 1837
bogdanm 82:6473597d706e 1838 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1839 //! @brief Read current value of the FTM_OUTINIT_CH3OI field.
bogdanm 82:6473597d706e 1840 #define BR_FTM_OUTINIT_CH3OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI))
bogdanm 82:6473597d706e 1841 #endif
bogdanm 82:6473597d706e 1842
bogdanm 82:6473597d706e 1843 //! @brief Format value for bitfield FTM_OUTINIT_CH3OI.
bogdanm 82:6473597d706e 1844 #define BF_FTM_OUTINIT_CH3OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH3OI), uint32_t) & BM_FTM_OUTINIT_CH3OI)
bogdanm 82:6473597d706e 1845
bogdanm 82:6473597d706e 1846 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1847 //! @brief Set the CH3OI field to a new value.
bogdanm 82:6473597d706e 1848 #define BW_FTM_OUTINIT_CH3OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI) = (v))
bogdanm 82:6473597d706e 1849 #endif
bogdanm 82:6473597d706e 1850 //@}
bogdanm 82:6473597d706e 1851
bogdanm 82:6473597d706e 1852 /*!
bogdanm 82:6473597d706e 1853 * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
bogdanm 82:6473597d706e 1854 *
bogdanm 82:6473597d706e 1855 * Selects the value that is forced into the channel output when the
bogdanm 82:6473597d706e 1856 * initialization occurs.
bogdanm 82:6473597d706e 1857 *
bogdanm 82:6473597d706e 1858 * Values:
bogdanm 82:6473597d706e 1859 * - 0 - The initialization value is 0.
bogdanm 82:6473597d706e 1860 * - 1 - The initialization value is 1.
bogdanm 82:6473597d706e 1861 */
bogdanm 82:6473597d706e 1862 //@{
bogdanm 82:6473597d706e 1863 #define BP_FTM_OUTINIT_CH4OI (4U) //!< Bit position for FTM_OUTINIT_CH4OI.
bogdanm 82:6473597d706e 1864 #define BM_FTM_OUTINIT_CH4OI (0x00000010U) //!< Bit mask for FTM_OUTINIT_CH4OI.
bogdanm 82:6473597d706e 1865 #define BS_FTM_OUTINIT_CH4OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH4OI.
bogdanm 82:6473597d706e 1866
bogdanm 82:6473597d706e 1867 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1868 //! @brief Read current value of the FTM_OUTINIT_CH4OI field.
bogdanm 82:6473597d706e 1869 #define BR_FTM_OUTINIT_CH4OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI))
bogdanm 82:6473597d706e 1870 #endif
bogdanm 82:6473597d706e 1871
bogdanm 82:6473597d706e 1872 //! @brief Format value for bitfield FTM_OUTINIT_CH4OI.
bogdanm 82:6473597d706e 1873 #define BF_FTM_OUTINIT_CH4OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH4OI), uint32_t) & BM_FTM_OUTINIT_CH4OI)
bogdanm 82:6473597d706e 1874
bogdanm 82:6473597d706e 1875 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1876 //! @brief Set the CH4OI field to a new value.
bogdanm 82:6473597d706e 1877 #define BW_FTM_OUTINIT_CH4OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI) = (v))
bogdanm 82:6473597d706e 1878 #endif
bogdanm 82:6473597d706e 1879 //@}
bogdanm 82:6473597d706e 1880
bogdanm 82:6473597d706e 1881 /*!
bogdanm 82:6473597d706e 1882 * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
bogdanm 82:6473597d706e 1883 *
bogdanm 82:6473597d706e 1884 * Selects the value that is forced into the channel output when the
bogdanm 82:6473597d706e 1885 * initialization occurs.
bogdanm 82:6473597d706e 1886 *
bogdanm 82:6473597d706e 1887 * Values:
bogdanm 82:6473597d706e 1888 * - 0 - The initialization value is 0.
bogdanm 82:6473597d706e 1889 * - 1 - The initialization value is 1.
bogdanm 82:6473597d706e 1890 */
bogdanm 82:6473597d706e 1891 //@{
bogdanm 82:6473597d706e 1892 #define BP_FTM_OUTINIT_CH5OI (5U) //!< Bit position for FTM_OUTINIT_CH5OI.
bogdanm 82:6473597d706e 1893 #define BM_FTM_OUTINIT_CH5OI (0x00000020U) //!< Bit mask for FTM_OUTINIT_CH5OI.
bogdanm 82:6473597d706e 1894 #define BS_FTM_OUTINIT_CH5OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH5OI.
bogdanm 82:6473597d706e 1895
bogdanm 82:6473597d706e 1896 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1897 //! @brief Read current value of the FTM_OUTINIT_CH5OI field.
bogdanm 82:6473597d706e 1898 #define BR_FTM_OUTINIT_CH5OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI))
bogdanm 82:6473597d706e 1899 #endif
bogdanm 82:6473597d706e 1900
bogdanm 82:6473597d706e 1901 //! @brief Format value for bitfield FTM_OUTINIT_CH5OI.
bogdanm 82:6473597d706e 1902 #define BF_FTM_OUTINIT_CH5OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH5OI), uint32_t) & BM_FTM_OUTINIT_CH5OI)
bogdanm 82:6473597d706e 1903
bogdanm 82:6473597d706e 1904 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1905 //! @brief Set the CH5OI field to a new value.
bogdanm 82:6473597d706e 1906 #define BW_FTM_OUTINIT_CH5OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI) = (v))
bogdanm 82:6473597d706e 1907 #endif
bogdanm 82:6473597d706e 1908 //@}
bogdanm 82:6473597d706e 1909
bogdanm 82:6473597d706e 1910 /*!
bogdanm 82:6473597d706e 1911 * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
bogdanm 82:6473597d706e 1912 *
bogdanm 82:6473597d706e 1913 * Selects the value that is forced into the channel output when the
bogdanm 82:6473597d706e 1914 * initialization occurs.
bogdanm 82:6473597d706e 1915 *
bogdanm 82:6473597d706e 1916 * Values:
bogdanm 82:6473597d706e 1917 * - 0 - The initialization value is 0.
bogdanm 82:6473597d706e 1918 * - 1 - The initialization value is 1.
bogdanm 82:6473597d706e 1919 */
bogdanm 82:6473597d706e 1920 //@{
bogdanm 82:6473597d706e 1921 #define BP_FTM_OUTINIT_CH6OI (6U) //!< Bit position for FTM_OUTINIT_CH6OI.
bogdanm 82:6473597d706e 1922 #define BM_FTM_OUTINIT_CH6OI (0x00000040U) //!< Bit mask for FTM_OUTINIT_CH6OI.
bogdanm 82:6473597d706e 1923 #define BS_FTM_OUTINIT_CH6OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH6OI.
bogdanm 82:6473597d706e 1924
bogdanm 82:6473597d706e 1925 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1926 //! @brief Read current value of the FTM_OUTINIT_CH6OI field.
bogdanm 82:6473597d706e 1927 #define BR_FTM_OUTINIT_CH6OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI))
bogdanm 82:6473597d706e 1928 #endif
bogdanm 82:6473597d706e 1929
bogdanm 82:6473597d706e 1930 //! @brief Format value for bitfield FTM_OUTINIT_CH6OI.
bogdanm 82:6473597d706e 1931 #define BF_FTM_OUTINIT_CH6OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH6OI), uint32_t) & BM_FTM_OUTINIT_CH6OI)
bogdanm 82:6473597d706e 1932
bogdanm 82:6473597d706e 1933 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1934 //! @brief Set the CH6OI field to a new value.
bogdanm 82:6473597d706e 1935 #define BW_FTM_OUTINIT_CH6OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI) = (v))
bogdanm 82:6473597d706e 1936 #endif
bogdanm 82:6473597d706e 1937 //@}
bogdanm 82:6473597d706e 1938
bogdanm 82:6473597d706e 1939 /*!
bogdanm 82:6473597d706e 1940 * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
bogdanm 82:6473597d706e 1941 *
bogdanm 82:6473597d706e 1942 * Selects the value that is forced into the channel output when the
bogdanm 82:6473597d706e 1943 * initialization occurs.
bogdanm 82:6473597d706e 1944 *
bogdanm 82:6473597d706e 1945 * Values:
bogdanm 82:6473597d706e 1946 * - 0 - The initialization value is 0.
bogdanm 82:6473597d706e 1947 * - 1 - The initialization value is 1.
bogdanm 82:6473597d706e 1948 */
bogdanm 82:6473597d706e 1949 //@{
bogdanm 82:6473597d706e 1950 #define BP_FTM_OUTINIT_CH7OI (7U) //!< Bit position for FTM_OUTINIT_CH7OI.
bogdanm 82:6473597d706e 1951 #define BM_FTM_OUTINIT_CH7OI (0x00000080U) //!< Bit mask for FTM_OUTINIT_CH7OI.
bogdanm 82:6473597d706e 1952 #define BS_FTM_OUTINIT_CH7OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH7OI.
bogdanm 82:6473597d706e 1953
bogdanm 82:6473597d706e 1954 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1955 //! @brief Read current value of the FTM_OUTINIT_CH7OI field.
bogdanm 82:6473597d706e 1956 #define BR_FTM_OUTINIT_CH7OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI))
bogdanm 82:6473597d706e 1957 #endif
bogdanm 82:6473597d706e 1958
bogdanm 82:6473597d706e 1959 //! @brief Format value for bitfield FTM_OUTINIT_CH7OI.
bogdanm 82:6473597d706e 1960 #define BF_FTM_OUTINIT_CH7OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH7OI), uint32_t) & BM_FTM_OUTINIT_CH7OI)
bogdanm 82:6473597d706e 1961
bogdanm 82:6473597d706e 1962 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1963 //! @brief Set the CH7OI field to a new value.
bogdanm 82:6473597d706e 1964 #define BW_FTM_OUTINIT_CH7OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI) = (v))
bogdanm 82:6473597d706e 1965 #endif
bogdanm 82:6473597d706e 1966 //@}
bogdanm 82:6473597d706e 1967
bogdanm 82:6473597d706e 1968 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1969 // HW_FTM_OUTMASK - Output Mask
bogdanm 82:6473597d706e 1970 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1971
bogdanm 82:6473597d706e 1972 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1973 /*!
bogdanm 82:6473597d706e 1974 * @brief HW_FTM_OUTMASK - Output Mask (RW)
bogdanm 82:6473597d706e 1975 *
bogdanm 82:6473597d706e 1976 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 1977 *
bogdanm 82:6473597d706e 1978 * This register provides a mask for each FTM channel. The mask of a channel
bogdanm 82:6473597d706e 1979 * determines if its output responds, that is, it is masked or not, when a match
bogdanm 82:6473597d706e 1980 * occurs. This feature is used for BLDC control where the PWM signal is presented
bogdanm 82:6473597d706e 1981 * to an electric motor at specific times to provide electronic commutation. Any
bogdanm 82:6473597d706e 1982 * write to the OUTMASK register, stores the value in its write buffer. The
bogdanm 82:6473597d706e 1983 * register is updated with the value of its write buffer according to PWM
bogdanm 82:6473597d706e 1984 * synchronization.
bogdanm 82:6473597d706e 1985 */
bogdanm 82:6473597d706e 1986 typedef union _hw_ftm_outmask
bogdanm 82:6473597d706e 1987 {
bogdanm 82:6473597d706e 1988 uint32_t U;
bogdanm 82:6473597d706e 1989 struct _hw_ftm_outmask_bitfields
bogdanm 82:6473597d706e 1990 {
bogdanm 82:6473597d706e 1991 uint32_t CH0OM : 1; //!< [0] Channel 0 Output Mask
bogdanm 82:6473597d706e 1992 uint32_t CH1OM : 1; //!< [1] Channel 1 Output Mask
bogdanm 82:6473597d706e 1993 uint32_t CH2OM : 1; //!< [2] Channel 2 Output Mask
bogdanm 82:6473597d706e 1994 uint32_t CH3OM : 1; //!< [3] Channel 3 Output Mask
bogdanm 82:6473597d706e 1995 uint32_t CH4OM : 1; //!< [4] Channel 4 Output Mask
bogdanm 82:6473597d706e 1996 uint32_t CH5OM : 1; //!< [5] Channel 5 Output Mask
bogdanm 82:6473597d706e 1997 uint32_t CH6OM : 1; //!< [6] Channel 6 Output Mask
bogdanm 82:6473597d706e 1998 uint32_t CH7OM : 1; //!< [7] Channel 7 Output Mask
bogdanm 82:6473597d706e 1999 uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm 82:6473597d706e 2000 } B;
bogdanm 82:6473597d706e 2001 } hw_ftm_outmask_t;
bogdanm 82:6473597d706e 2002 #endif
bogdanm 82:6473597d706e 2003
bogdanm 82:6473597d706e 2004 /*!
bogdanm 82:6473597d706e 2005 * @name Constants and macros for entire FTM_OUTMASK register
bogdanm 82:6473597d706e 2006 */
bogdanm 82:6473597d706e 2007 //@{
bogdanm 82:6473597d706e 2008 #define HW_FTM_OUTMASK_ADDR(x) (REGS_FTM_BASE(x) + 0x60U)
bogdanm 82:6473597d706e 2009
bogdanm 82:6473597d706e 2010 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2011 #define HW_FTM_OUTMASK(x) (*(__IO hw_ftm_outmask_t *) HW_FTM_OUTMASK_ADDR(x))
bogdanm 82:6473597d706e 2012 #define HW_FTM_OUTMASK_RD(x) (HW_FTM_OUTMASK(x).U)
bogdanm 82:6473597d706e 2013 #define HW_FTM_OUTMASK_WR(x, v) (HW_FTM_OUTMASK(x).U = (v))
bogdanm 82:6473597d706e 2014 #define HW_FTM_OUTMASK_SET(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) | (v)))
bogdanm 82:6473597d706e 2015 #define HW_FTM_OUTMASK_CLR(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) & ~(v)))
bogdanm 82:6473597d706e 2016 #define HW_FTM_OUTMASK_TOG(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) ^ (v)))
bogdanm 82:6473597d706e 2017 #endif
bogdanm 82:6473597d706e 2018 //@}
bogdanm 82:6473597d706e 2019
bogdanm 82:6473597d706e 2020 /*
bogdanm 82:6473597d706e 2021 * Constants & macros for individual FTM_OUTMASK bitfields
bogdanm 82:6473597d706e 2022 */
bogdanm 82:6473597d706e 2023
bogdanm 82:6473597d706e 2024 /*!
bogdanm 82:6473597d706e 2025 * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
bogdanm 82:6473597d706e 2026 *
bogdanm 82:6473597d706e 2027 * Defines if the channel output is masked or unmasked.
bogdanm 82:6473597d706e 2028 *
bogdanm 82:6473597d706e 2029 * Values:
bogdanm 82:6473597d706e 2030 * - 0 - Channel output is not masked. It continues to operate normally.
bogdanm 82:6473597d706e 2031 * - 1 - Channel output is masked. It is forced to its inactive state.
bogdanm 82:6473597d706e 2032 */
bogdanm 82:6473597d706e 2033 //@{
bogdanm 82:6473597d706e 2034 #define BP_FTM_OUTMASK_CH0OM (0U) //!< Bit position for FTM_OUTMASK_CH0OM.
bogdanm 82:6473597d706e 2035 #define BM_FTM_OUTMASK_CH0OM (0x00000001U) //!< Bit mask for FTM_OUTMASK_CH0OM.
bogdanm 82:6473597d706e 2036 #define BS_FTM_OUTMASK_CH0OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH0OM.
bogdanm 82:6473597d706e 2037
bogdanm 82:6473597d706e 2038 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2039 //! @brief Read current value of the FTM_OUTMASK_CH0OM field.
bogdanm 82:6473597d706e 2040 #define BR_FTM_OUTMASK_CH0OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM))
bogdanm 82:6473597d706e 2041 #endif
bogdanm 82:6473597d706e 2042
bogdanm 82:6473597d706e 2043 //! @brief Format value for bitfield FTM_OUTMASK_CH0OM.
bogdanm 82:6473597d706e 2044 #define BF_FTM_OUTMASK_CH0OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH0OM), uint32_t) & BM_FTM_OUTMASK_CH0OM)
bogdanm 82:6473597d706e 2045
bogdanm 82:6473597d706e 2046 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2047 //! @brief Set the CH0OM field to a new value.
bogdanm 82:6473597d706e 2048 #define BW_FTM_OUTMASK_CH0OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM) = (v))
bogdanm 82:6473597d706e 2049 #endif
bogdanm 82:6473597d706e 2050 //@}
bogdanm 82:6473597d706e 2051
bogdanm 82:6473597d706e 2052 /*!
bogdanm 82:6473597d706e 2053 * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
bogdanm 82:6473597d706e 2054 *
bogdanm 82:6473597d706e 2055 * Defines if the channel output is masked or unmasked.
bogdanm 82:6473597d706e 2056 *
bogdanm 82:6473597d706e 2057 * Values:
bogdanm 82:6473597d706e 2058 * - 0 - Channel output is not masked. It continues to operate normally.
bogdanm 82:6473597d706e 2059 * - 1 - Channel output is masked. It is forced to its inactive state.
bogdanm 82:6473597d706e 2060 */
bogdanm 82:6473597d706e 2061 //@{
bogdanm 82:6473597d706e 2062 #define BP_FTM_OUTMASK_CH1OM (1U) //!< Bit position for FTM_OUTMASK_CH1OM.
bogdanm 82:6473597d706e 2063 #define BM_FTM_OUTMASK_CH1OM (0x00000002U) //!< Bit mask for FTM_OUTMASK_CH1OM.
bogdanm 82:6473597d706e 2064 #define BS_FTM_OUTMASK_CH1OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH1OM.
bogdanm 82:6473597d706e 2065
bogdanm 82:6473597d706e 2066 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2067 //! @brief Read current value of the FTM_OUTMASK_CH1OM field.
bogdanm 82:6473597d706e 2068 #define BR_FTM_OUTMASK_CH1OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM))
bogdanm 82:6473597d706e 2069 #endif
bogdanm 82:6473597d706e 2070
bogdanm 82:6473597d706e 2071 //! @brief Format value for bitfield FTM_OUTMASK_CH1OM.
bogdanm 82:6473597d706e 2072 #define BF_FTM_OUTMASK_CH1OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH1OM), uint32_t) & BM_FTM_OUTMASK_CH1OM)
bogdanm 82:6473597d706e 2073
bogdanm 82:6473597d706e 2074 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2075 //! @brief Set the CH1OM field to a new value.
bogdanm 82:6473597d706e 2076 #define BW_FTM_OUTMASK_CH1OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM) = (v))
bogdanm 82:6473597d706e 2077 #endif
bogdanm 82:6473597d706e 2078 //@}
bogdanm 82:6473597d706e 2079
bogdanm 82:6473597d706e 2080 /*!
bogdanm 82:6473597d706e 2081 * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
bogdanm 82:6473597d706e 2082 *
bogdanm 82:6473597d706e 2083 * Defines if the channel output is masked or unmasked.
bogdanm 82:6473597d706e 2084 *
bogdanm 82:6473597d706e 2085 * Values:
bogdanm 82:6473597d706e 2086 * - 0 - Channel output is not masked. It continues to operate normally.
bogdanm 82:6473597d706e 2087 * - 1 - Channel output is masked. It is forced to its inactive state.
bogdanm 82:6473597d706e 2088 */
bogdanm 82:6473597d706e 2089 //@{
bogdanm 82:6473597d706e 2090 #define BP_FTM_OUTMASK_CH2OM (2U) //!< Bit position for FTM_OUTMASK_CH2OM.
bogdanm 82:6473597d706e 2091 #define BM_FTM_OUTMASK_CH2OM (0x00000004U) //!< Bit mask for FTM_OUTMASK_CH2OM.
bogdanm 82:6473597d706e 2092 #define BS_FTM_OUTMASK_CH2OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH2OM.
bogdanm 82:6473597d706e 2093
bogdanm 82:6473597d706e 2094 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2095 //! @brief Read current value of the FTM_OUTMASK_CH2OM field.
bogdanm 82:6473597d706e 2096 #define BR_FTM_OUTMASK_CH2OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM))
bogdanm 82:6473597d706e 2097 #endif
bogdanm 82:6473597d706e 2098
bogdanm 82:6473597d706e 2099 //! @brief Format value for bitfield FTM_OUTMASK_CH2OM.
bogdanm 82:6473597d706e 2100 #define BF_FTM_OUTMASK_CH2OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH2OM), uint32_t) & BM_FTM_OUTMASK_CH2OM)
bogdanm 82:6473597d706e 2101
bogdanm 82:6473597d706e 2102 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2103 //! @brief Set the CH2OM field to a new value.
bogdanm 82:6473597d706e 2104 #define BW_FTM_OUTMASK_CH2OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM) = (v))
bogdanm 82:6473597d706e 2105 #endif
bogdanm 82:6473597d706e 2106 //@}
bogdanm 82:6473597d706e 2107
bogdanm 82:6473597d706e 2108 /*!
bogdanm 82:6473597d706e 2109 * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
bogdanm 82:6473597d706e 2110 *
bogdanm 82:6473597d706e 2111 * Defines if the channel output is masked or unmasked.
bogdanm 82:6473597d706e 2112 *
bogdanm 82:6473597d706e 2113 * Values:
bogdanm 82:6473597d706e 2114 * - 0 - Channel output is not masked. It continues to operate normally.
bogdanm 82:6473597d706e 2115 * - 1 - Channel output is masked. It is forced to its inactive state.
bogdanm 82:6473597d706e 2116 */
bogdanm 82:6473597d706e 2117 //@{
bogdanm 82:6473597d706e 2118 #define BP_FTM_OUTMASK_CH3OM (3U) //!< Bit position for FTM_OUTMASK_CH3OM.
bogdanm 82:6473597d706e 2119 #define BM_FTM_OUTMASK_CH3OM (0x00000008U) //!< Bit mask for FTM_OUTMASK_CH3OM.
bogdanm 82:6473597d706e 2120 #define BS_FTM_OUTMASK_CH3OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH3OM.
bogdanm 82:6473597d706e 2121
bogdanm 82:6473597d706e 2122 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2123 //! @brief Read current value of the FTM_OUTMASK_CH3OM field.
bogdanm 82:6473597d706e 2124 #define BR_FTM_OUTMASK_CH3OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM))
bogdanm 82:6473597d706e 2125 #endif
bogdanm 82:6473597d706e 2126
bogdanm 82:6473597d706e 2127 //! @brief Format value for bitfield FTM_OUTMASK_CH3OM.
bogdanm 82:6473597d706e 2128 #define BF_FTM_OUTMASK_CH3OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH3OM), uint32_t) & BM_FTM_OUTMASK_CH3OM)
bogdanm 82:6473597d706e 2129
bogdanm 82:6473597d706e 2130 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2131 //! @brief Set the CH3OM field to a new value.
bogdanm 82:6473597d706e 2132 #define BW_FTM_OUTMASK_CH3OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM) = (v))
bogdanm 82:6473597d706e 2133 #endif
bogdanm 82:6473597d706e 2134 //@}
bogdanm 82:6473597d706e 2135
bogdanm 82:6473597d706e 2136 /*!
bogdanm 82:6473597d706e 2137 * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
bogdanm 82:6473597d706e 2138 *
bogdanm 82:6473597d706e 2139 * Defines if the channel output is masked or unmasked.
bogdanm 82:6473597d706e 2140 *
bogdanm 82:6473597d706e 2141 * Values:
bogdanm 82:6473597d706e 2142 * - 0 - Channel output is not masked. It continues to operate normally.
bogdanm 82:6473597d706e 2143 * - 1 - Channel output is masked. It is forced to its inactive state.
bogdanm 82:6473597d706e 2144 */
bogdanm 82:6473597d706e 2145 //@{
bogdanm 82:6473597d706e 2146 #define BP_FTM_OUTMASK_CH4OM (4U) //!< Bit position for FTM_OUTMASK_CH4OM.
bogdanm 82:6473597d706e 2147 #define BM_FTM_OUTMASK_CH4OM (0x00000010U) //!< Bit mask for FTM_OUTMASK_CH4OM.
bogdanm 82:6473597d706e 2148 #define BS_FTM_OUTMASK_CH4OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH4OM.
bogdanm 82:6473597d706e 2149
bogdanm 82:6473597d706e 2150 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2151 //! @brief Read current value of the FTM_OUTMASK_CH4OM field.
bogdanm 82:6473597d706e 2152 #define BR_FTM_OUTMASK_CH4OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM))
bogdanm 82:6473597d706e 2153 #endif
bogdanm 82:6473597d706e 2154
bogdanm 82:6473597d706e 2155 //! @brief Format value for bitfield FTM_OUTMASK_CH4OM.
bogdanm 82:6473597d706e 2156 #define BF_FTM_OUTMASK_CH4OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH4OM), uint32_t) & BM_FTM_OUTMASK_CH4OM)
bogdanm 82:6473597d706e 2157
bogdanm 82:6473597d706e 2158 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2159 //! @brief Set the CH4OM field to a new value.
bogdanm 82:6473597d706e 2160 #define BW_FTM_OUTMASK_CH4OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM) = (v))
bogdanm 82:6473597d706e 2161 #endif
bogdanm 82:6473597d706e 2162 //@}
bogdanm 82:6473597d706e 2163
bogdanm 82:6473597d706e 2164 /*!
bogdanm 82:6473597d706e 2165 * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
bogdanm 82:6473597d706e 2166 *
bogdanm 82:6473597d706e 2167 * Defines if the channel output is masked or unmasked.
bogdanm 82:6473597d706e 2168 *
bogdanm 82:6473597d706e 2169 * Values:
bogdanm 82:6473597d706e 2170 * - 0 - Channel output is not masked. It continues to operate normally.
bogdanm 82:6473597d706e 2171 * - 1 - Channel output is masked. It is forced to its inactive state.
bogdanm 82:6473597d706e 2172 */
bogdanm 82:6473597d706e 2173 //@{
bogdanm 82:6473597d706e 2174 #define BP_FTM_OUTMASK_CH5OM (5U) //!< Bit position for FTM_OUTMASK_CH5OM.
bogdanm 82:6473597d706e 2175 #define BM_FTM_OUTMASK_CH5OM (0x00000020U) //!< Bit mask for FTM_OUTMASK_CH5OM.
bogdanm 82:6473597d706e 2176 #define BS_FTM_OUTMASK_CH5OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH5OM.
bogdanm 82:6473597d706e 2177
bogdanm 82:6473597d706e 2178 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2179 //! @brief Read current value of the FTM_OUTMASK_CH5OM field.
bogdanm 82:6473597d706e 2180 #define BR_FTM_OUTMASK_CH5OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM))
bogdanm 82:6473597d706e 2181 #endif
bogdanm 82:6473597d706e 2182
bogdanm 82:6473597d706e 2183 //! @brief Format value for bitfield FTM_OUTMASK_CH5OM.
bogdanm 82:6473597d706e 2184 #define BF_FTM_OUTMASK_CH5OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH5OM), uint32_t) & BM_FTM_OUTMASK_CH5OM)
bogdanm 82:6473597d706e 2185
bogdanm 82:6473597d706e 2186 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2187 //! @brief Set the CH5OM field to a new value.
bogdanm 82:6473597d706e 2188 #define BW_FTM_OUTMASK_CH5OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM) = (v))
bogdanm 82:6473597d706e 2189 #endif
bogdanm 82:6473597d706e 2190 //@}
bogdanm 82:6473597d706e 2191
bogdanm 82:6473597d706e 2192 /*!
bogdanm 82:6473597d706e 2193 * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
bogdanm 82:6473597d706e 2194 *
bogdanm 82:6473597d706e 2195 * Defines if the channel output is masked or unmasked.
bogdanm 82:6473597d706e 2196 *
bogdanm 82:6473597d706e 2197 * Values:
bogdanm 82:6473597d706e 2198 * - 0 - Channel output is not masked. It continues to operate normally.
bogdanm 82:6473597d706e 2199 * - 1 - Channel output is masked. It is forced to its inactive state.
bogdanm 82:6473597d706e 2200 */
bogdanm 82:6473597d706e 2201 //@{
bogdanm 82:6473597d706e 2202 #define BP_FTM_OUTMASK_CH6OM (6U) //!< Bit position for FTM_OUTMASK_CH6OM.
bogdanm 82:6473597d706e 2203 #define BM_FTM_OUTMASK_CH6OM (0x00000040U) //!< Bit mask for FTM_OUTMASK_CH6OM.
bogdanm 82:6473597d706e 2204 #define BS_FTM_OUTMASK_CH6OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH6OM.
bogdanm 82:6473597d706e 2205
bogdanm 82:6473597d706e 2206 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2207 //! @brief Read current value of the FTM_OUTMASK_CH6OM field.
bogdanm 82:6473597d706e 2208 #define BR_FTM_OUTMASK_CH6OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM))
bogdanm 82:6473597d706e 2209 #endif
bogdanm 82:6473597d706e 2210
bogdanm 82:6473597d706e 2211 //! @brief Format value for bitfield FTM_OUTMASK_CH6OM.
bogdanm 82:6473597d706e 2212 #define BF_FTM_OUTMASK_CH6OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH6OM), uint32_t) & BM_FTM_OUTMASK_CH6OM)
bogdanm 82:6473597d706e 2213
bogdanm 82:6473597d706e 2214 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2215 //! @brief Set the CH6OM field to a new value.
bogdanm 82:6473597d706e 2216 #define BW_FTM_OUTMASK_CH6OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM) = (v))
bogdanm 82:6473597d706e 2217 #endif
bogdanm 82:6473597d706e 2218 //@}
bogdanm 82:6473597d706e 2219
bogdanm 82:6473597d706e 2220 /*!
bogdanm 82:6473597d706e 2221 * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
bogdanm 82:6473597d706e 2222 *
bogdanm 82:6473597d706e 2223 * Defines if the channel output is masked or unmasked.
bogdanm 82:6473597d706e 2224 *
bogdanm 82:6473597d706e 2225 * Values:
bogdanm 82:6473597d706e 2226 * - 0 - Channel output is not masked. It continues to operate normally.
bogdanm 82:6473597d706e 2227 * - 1 - Channel output is masked. It is forced to its inactive state.
bogdanm 82:6473597d706e 2228 */
bogdanm 82:6473597d706e 2229 //@{
bogdanm 82:6473597d706e 2230 #define BP_FTM_OUTMASK_CH7OM (7U) //!< Bit position for FTM_OUTMASK_CH7OM.
bogdanm 82:6473597d706e 2231 #define BM_FTM_OUTMASK_CH7OM (0x00000080U) //!< Bit mask for FTM_OUTMASK_CH7OM.
bogdanm 82:6473597d706e 2232 #define BS_FTM_OUTMASK_CH7OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH7OM.
bogdanm 82:6473597d706e 2233
bogdanm 82:6473597d706e 2234 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2235 //! @brief Read current value of the FTM_OUTMASK_CH7OM field.
bogdanm 82:6473597d706e 2236 #define BR_FTM_OUTMASK_CH7OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM))
bogdanm 82:6473597d706e 2237 #endif
bogdanm 82:6473597d706e 2238
bogdanm 82:6473597d706e 2239 //! @brief Format value for bitfield FTM_OUTMASK_CH7OM.
bogdanm 82:6473597d706e 2240 #define BF_FTM_OUTMASK_CH7OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH7OM), uint32_t) & BM_FTM_OUTMASK_CH7OM)
bogdanm 82:6473597d706e 2241
bogdanm 82:6473597d706e 2242 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2243 //! @brief Set the CH7OM field to a new value.
bogdanm 82:6473597d706e 2244 #define BW_FTM_OUTMASK_CH7OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM) = (v))
bogdanm 82:6473597d706e 2245 #endif
bogdanm 82:6473597d706e 2246 //@}
bogdanm 82:6473597d706e 2247
bogdanm 82:6473597d706e 2248 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2249 // HW_FTM_COMBINE - Function For Linked Channels
bogdanm 82:6473597d706e 2250 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2251
bogdanm 82:6473597d706e 2252 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2253 /*!
bogdanm 82:6473597d706e 2254 * @brief HW_FTM_COMBINE - Function For Linked Channels (RW)
bogdanm 82:6473597d706e 2255 *
bogdanm 82:6473597d706e 2256 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 2257 *
bogdanm 82:6473597d706e 2258 * This register contains the control bits used to configure the fault control,
bogdanm 82:6473597d706e 2259 * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
bogdanm 82:6473597d706e 2260 * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
bogdanm 82:6473597d706e 2261 * 4, and 6.
bogdanm 82:6473597d706e 2262 */
bogdanm 82:6473597d706e 2263 typedef union _hw_ftm_combine
bogdanm 82:6473597d706e 2264 {
bogdanm 82:6473597d706e 2265 uint32_t U;
bogdanm 82:6473597d706e 2266 struct _hw_ftm_combine_bitfields
bogdanm 82:6473597d706e 2267 {
bogdanm 82:6473597d706e 2268 uint32_t COMBINE0 : 1; //!< [0] Combine Channels For n = 0
bogdanm 82:6473597d706e 2269 uint32_t COMP0 : 1; //!< [1] Complement Of Channel (n) For n = 0
bogdanm 82:6473597d706e 2270 uint32_t DECAPEN0 : 1; //!< [2] Dual Edge Capture Mode Enable For n =
bogdanm 82:6473597d706e 2271 //! 0
bogdanm 82:6473597d706e 2272 uint32_t DECAP0 : 1; //!< [3] Dual Edge Capture Mode Captures For n =
bogdanm 82:6473597d706e 2273 //! 0
bogdanm 82:6473597d706e 2274 uint32_t DTEN0 : 1; //!< [4] Deadtime Enable For n = 0
bogdanm 82:6473597d706e 2275 uint32_t SYNCEN0 : 1; //!< [5] Synchronization Enable For n = 0
bogdanm 82:6473597d706e 2276 uint32_t FAULTEN0 : 1; //!< [6] Fault Control Enable For n = 0
bogdanm 82:6473597d706e 2277 uint32_t RESERVED0 : 1; //!< [7]
bogdanm 82:6473597d706e 2278 uint32_t COMBINE1 : 1; //!< [8] Combine Channels For n = 2
bogdanm 82:6473597d706e 2279 uint32_t COMP1 : 1; //!< [9] Complement Of Channel (n) For n = 2
bogdanm 82:6473597d706e 2280 uint32_t DECAPEN1 : 1; //!< [10] Dual Edge Capture Mode Enable For n
bogdanm 82:6473597d706e 2281 //! = 2
bogdanm 82:6473597d706e 2282 uint32_t DECAP1 : 1; //!< [11] Dual Edge Capture Mode Captures For n
bogdanm 82:6473597d706e 2283 //! = 2
bogdanm 82:6473597d706e 2284 uint32_t DTEN1 : 1; //!< [12] Deadtime Enable For n = 2
bogdanm 82:6473597d706e 2285 uint32_t SYNCEN1 : 1; //!< [13] Synchronization Enable For n = 2
bogdanm 82:6473597d706e 2286 uint32_t FAULTEN1 : 1; //!< [14] Fault Control Enable For n = 2
bogdanm 82:6473597d706e 2287 uint32_t RESERVED1 : 1; //!< [15]
bogdanm 82:6473597d706e 2288 uint32_t COMBINE2 : 1; //!< [16] Combine Channels For n = 4
bogdanm 82:6473597d706e 2289 uint32_t COMP2 : 1; //!< [17] Complement Of Channel (n) For n = 4
bogdanm 82:6473597d706e 2290 uint32_t DECAPEN2 : 1; //!< [18] Dual Edge Capture Mode Enable For n
bogdanm 82:6473597d706e 2291 //! = 4
bogdanm 82:6473597d706e 2292 uint32_t DECAP2 : 1; //!< [19] Dual Edge Capture Mode Captures For n
bogdanm 82:6473597d706e 2293 //! = 4
bogdanm 82:6473597d706e 2294 uint32_t DTEN2 : 1; //!< [20] Deadtime Enable For n = 4
bogdanm 82:6473597d706e 2295 uint32_t SYNCEN2 : 1; //!< [21] Synchronization Enable For n = 4
bogdanm 82:6473597d706e 2296 uint32_t FAULTEN2 : 1; //!< [22] Fault Control Enable For n = 4
bogdanm 82:6473597d706e 2297 uint32_t RESERVED2 : 1; //!< [23]
bogdanm 82:6473597d706e 2298 uint32_t COMBINE3 : 1; //!< [24] Combine Channels For n = 6
bogdanm 82:6473597d706e 2299 uint32_t COMP3 : 1; //!< [25] Complement Of Channel (n) for n = 6
bogdanm 82:6473597d706e 2300 uint32_t DECAPEN3 : 1; //!< [26] Dual Edge Capture Mode Enable For n
bogdanm 82:6473597d706e 2301 //! = 6
bogdanm 82:6473597d706e 2302 uint32_t DECAP3 : 1; //!< [27] Dual Edge Capture Mode Captures For n
bogdanm 82:6473597d706e 2303 //! = 6
bogdanm 82:6473597d706e 2304 uint32_t DTEN3 : 1; //!< [28] Deadtime Enable For n = 6
bogdanm 82:6473597d706e 2305 uint32_t SYNCEN3 : 1; //!< [29] Synchronization Enable For n = 6
bogdanm 82:6473597d706e 2306 uint32_t FAULTEN3 : 1; //!< [30] Fault Control Enable For n = 6
bogdanm 82:6473597d706e 2307 uint32_t RESERVED3 : 1; //!< [31]
bogdanm 82:6473597d706e 2308 } B;
bogdanm 82:6473597d706e 2309 } hw_ftm_combine_t;
bogdanm 82:6473597d706e 2310 #endif
bogdanm 82:6473597d706e 2311
bogdanm 82:6473597d706e 2312 /*!
bogdanm 82:6473597d706e 2313 * @name Constants and macros for entire FTM_COMBINE register
bogdanm 82:6473597d706e 2314 */
bogdanm 82:6473597d706e 2315 //@{
bogdanm 82:6473597d706e 2316 #define HW_FTM_COMBINE_ADDR(x) (REGS_FTM_BASE(x) + 0x64U)
bogdanm 82:6473597d706e 2317
bogdanm 82:6473597d706e 2318 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2319 #define HW_FTM_COMBINE(x) (*(__IO hw_ftm_combine_t *) HW_FTM_COMBINE_ADDR(x))
bogdanm 82:6473597d706e 2320 #define HW_FTM_COMBINE_RD(x) (HW_FTM_COMBINE(x).U)
bogdanm 82:6473597d706e 2321 #define HW_FTM_COMBINE_WR(x, v) (HW_FTM_COMBINE(x).U = (v))
bogdanm 82:6473597d706e 2322 #define HW_FTM_COMBINE_SET(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) | (v)))
bogdanm 82:6473597d706e 2323 #define HW_FTM_COMBINE_CLR(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) & ~(v)))
bogdanm 82:6473597d706e 2324 #define HW_FTM_COMBINE_TOG(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) ^ (v)))
bogdanm 82:6473597d706e 2325 #endif
bogdanm 82:6473597d706e 2326 //@}
bogdanm 82:6473597d706e 2327
bogdanm 82:6473597d706e 2328 /*
bogdanm 82:6473597d706e 2329 * Constants & macros for individual FTM_COMBINE bitfields
bogdanm 82:6473597d706e 2330 */
bogdanm 82:6473597d706e 2331
bogdanm 82:6473597d706e 2332 /*!
bogdanm 82:6473597d706e 2333 * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
bogdanm 82:6473597d706e 2334 *
bogdanm 82:6473597d706e 2335 * Enables the combine feature for channels (n) and (n+1). This field is write
bogdanm 82:6473597d706e 2336 * protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2337 *
bogdanm 82:6473597d706e 2338 * Values:
bogdanm 82:6473597d706e 2339 * - 0 - Channels (n) and (n+1) are independent.
bogdanm 82:6473597d706e 2340 * - 1 - Channels (n) and (n+1) are combined.
bogdanm 82:6473597d706e 2341 */
bogdanm 82:6473597d706e 2342 //@{
bogdanm 82:6473597d706e 2343 #define BP_FTM_COMBINE_COMBINE0 (0U) //!< Bit position for FTM_COMBINE_COMBINE0.
bogdanm 82:6473597d706e 2344 #define BM_FTM_COMBINE_COMBINE0 (0x00000001U) //!< Bit mask for FTM_COMBINE_COMBINE0.
bogdanm 82:6473597d706e 2345 #define BS_FTM_COMBINE_COMBINE0 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE0.
bogdanm 82:6473597d706e 2346
bogdanm 82:6473597d706e 2347 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2348 //! @brief Read current value of the FTM_COMBINE_COMBINE0 field.
bogdanm 82:6473597d706e 2349 #define BR_FTM_COMBINE_COMBINE0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0))
bogdanm 82:6473597d706e 2350 #endif
bogdanm 82:6473597d706e 2351
bogdanm 82:6473597d706e 2352 //! @brief Format value for bitfield FTM_COMBINE_COMBINE0.
bogdanm 82:6473597d706e 2353 #define BF_FTM_COMBINE_COMBINE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE0), uint32_t) & BM_FTM_COMBINE_COMBINE0)
bogdanm 82:6473597d706e 2354
bogdanm 82:6473597d706e 2355 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2356 //! @brief Set the COMBINE0 field to a new value.
bogdanm 82:6473597d706e 2357 #define BW_FTM_COMBINE_COMBINE0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0) = (v))
bogdanm 82:6473597d706e 2358 #endif
bogdanm 82:6473597d706e 2359 //@}
bogdanm 82:6473597d706e 2360
bogdanm 82:6473597d706e 2361 /*!
bogdanm 82:6473597d706e 2362 * @name Register FTM_COMBINE, field COMP0[1] (RW)
bogdanm 82:6473597d706e 2363 *
bogdanm 82:6473597d706e 2364 * Enables Complementary mode for the combined channels. In Complementary mode
bogdanm 82:6473597d706e 2365 * the channel (n+1) output is the inverse of the channel (n) output. This field
bogdanm 82:6473597d706e 2366 * is write protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2367 *
bogdanm 82:6473597d706e 2368 * Values:
bogdanm 82:6473597d706e 2369 * - 0 - The channel (n+1) output is the same as the channel (n) output.
bogdanm 82:6473597d706e 2370 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
bogdanm 82:6473597d706e 2371 */
bogdanm 82:6473597d706e 2372 //@{
bogdanm 82:6473597d706e 2373 #define BP_FTM_COMBINE_COMP0 (1U) //!< Bit position for FTM_COMBINE_COMP0.
bogdanm 82:6473597d706e 2374 #define BM_FTM_COMBINE_COMP0 (0x00000002U) //!< Bit mask for FTM_COMBINE_COMP0.
bogdanm 82:6473597d706e 2375 #define BS_FTM_COMBINE_COMP0 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP0.
bogdanm 82:6473597d706e 2376
bogdanm 82:6473597d706e 2377 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2378 //! @brief Read current value of the FTM_COMBINE_COMP0 field.
bogdanm 82:6473597d706e 2379 #define BR_FTM_COMBINE_COMP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0))
bogdanm 82:6473597d706e 2380 #endif
bogdanm 82:6473597d706e 2381
bogdanm 82:6473597d706e 2382 //! @brief Format value for bitfield FTM_COMBINE_COMP0.
bogdanm 82:6473597d706e 2383 #define BF_FTM_COMBINE_COMP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP0), uint32_t) & BM_FTM_COMBINE_COMP0)
bogdanm 82:6473597d706e 2384
bogdanm 82:6473597d706e 2385 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2386 //! @brief Set the COMP0 field to a new value.
bogdanm 82:6473597d706e 2387 #define BW_FTM_COMBINE_COMP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0) = (v))
bogdanm 82:6473597d706e 2388 #endif
bogdanm 82:6473597d706e 2389 //@}
bogdanm 82:6473597d706e 2390
bogdanm 82:6473597d706e 2391 /*!
bogdanm 82:6473597d706e 2392 * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
bogdanm 82:6473597d706e 2393 *
bogdanm 82:6473597d706e 2394 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
bogdanm 82:6473597d706e 2395 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
bogdanm 82:6473597d706e 2396 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
bogdanm 82:6473597d706e 2397 * when FTMEN = 1. This field is write protected. It can be written only when
bogdanm 82:6473597d706e 2398 * MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2399 *
bogdanm 82:6473597d706e 2400 * Values:
bogdanm 82:6473597d706e 2401 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
bogdanm 82:6473597d706e 2402 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
bogdanm 82:6473597d706e 2403 */
bogdanm 82:6473597d706e 2404 //@{
bogdanm 82:6473597d706e 2405 #define BP_FTM_COMBINE_DECAPEN0 (2U) //!< Bit position for FTM_COMBINE_DECAPEN0.
bogdanm 82:6473597d706e 2406 #define BM_FTM_COMBINE_DECAPEN0 (0x00000004U) //!< Bit mask for FTM_COMBINE_DECAPEN0.
bogdanm 82:6473597d706e 2407 #define BS_FTM_COMBINE_DECAPEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN0.
bogdanm 82:6473597d706e 2408
bogdanm 82:6473597d706e 2409 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2410 //! @brief Read current value of the FTM_COMBINE_DECAPEN0 field.
bogdanm 82:6473597d706e 2411 #define BR_FTM_COMBINE_DECAPEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0))
bogdanm 82:6473597d706e 2412 #endif
bogdanm 82:6473597d706e 2413
bogdanm 82:6473597d706e 2414 //! @brief Format value for bitfield FTM_COMBINE_DECAPEN0.
bogdanm 82:6473597d706e 2415 #define BF_FTM_COMBINE_DECAPEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN0), uint32_t) & BM_FTM_COMBINE_DECAPEN0)
bogdanm 82:6473597d706e 2416
bogdanm 82:6473597d706e 2417 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2418 //! @brief Set the DECAPEN0 field to a new value.
bogdanm 82:6473597d706e 2419 #define BW_FTM_COMBINE_DECAPEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0) = (v))
bogdanm 82:6473597d706e 2420 #endif
bogdanm 82:6473597d706e 2421 //@}
bogdanm 82:6473597d706e 2422
bogdanm 82:6473597d706e 2423 /*!
bogdanm 82:6473597d706e 2424 * @name Register FTM_COMBINE, field DECAP0[3] (RW)
bogdanm 82:6473597d706e 2425 *
bogdanm 82:6473597d706e 2426 * Enables the capture of the FTM counter value according to the channel (n)
bogdanm 82:6473597d706e 2427 * input event and the configuration of the dual edge capture bits. This field
bogdanm 82:6473597d706e 2428 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
bogdanm 82:6473597d706e 2429 * hardware if dual edge capture - one-shot mode is selected and when the capture
bogdanm 82:6473597d706e 2430 * of channel (n+1) event is made.
bogdanm 82:6473597d706e 2431 *
bogdanm 82:6473597d706e 2432 * Values:
bogdanm 82:6473597d706e 2433 * - 0 - The dual edge captures are inactive.
bogdanm 82:6473597d706e 2434 * - 1 - The dual edge captures are active.
bogdanm 82:6473597d706e 2435 */
bogdanm 82:6473597d706e 2436 //@{
bogdanm 82:6473597d706e 2437 #define BP_FTM_COMBINE_DECAP0 (3U) //!< Bit position for FTM_COMBINE_DECAP0.
bogdanm 82:6473597d706e 2438 #define BM_FTM_COMBINE_DECAP0 (0x00000008U) //!< Bit mask for FTM_COMBINE_DECAP0.
bogdanm 82:6473597d706e 2439 #define BS_FTM_COMBINE_DECAP0 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP0.
bogdanm 82:6473597d706e 2440
bogdanm 82:6473597d706e 2441 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2442 //! @brief Read current value of the FTM_COMBINE_DECAP0 field.
bogdanm 82:6473597d706e 2443 #define BR_FTM_COMBINE_DECAP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0))
bogdanm 82:6473597d706e 2444 #endif
bogdanm 82:6473597d706e 2445
bogdanm 82:6473597d706e 2446 //! @brief Format value for bitfield FTM_COMBINE_DECAP0.
bogdanm 82:6473597d706e 2447 #define BF_FTM_COMBINE_DECAP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP0), uint32_t) & BM_FTM_COMBINE_DECAP0)
bogdanm 82:6473597d706e 2448
bogdanm 82:6473597d706e 2449 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2450 //! @brief Set the DECAP0 field to a new value.
bogdanm 82:6473597d706e 2451 #define BW_FTM_COMBINE_DECAP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0) = (v))
bogdanm 82:6473597d706e 2452 #endif
bogdanm 82:6473597d706e 2453 //@}
bogdanm 82:6473597d706e 2454
bogdanm 82:6473597d706e 2455 /*!
bogdanm 82:6473597d706e 2456 * @name Register FTM_COMBINE, field DTEN0[4] (RW)
bogdanm 82:6473597d706e 2457 *
bogdanm 82:6473597d706e 2458 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
bogdanm 82:6473597d706e 2459 * write protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2460 *
bogdanm 82:6473597d706e 2461 * Values:
bogdanm 82:6473597d706e 2462 * - 0 - The deadtime insertion in this pair of channels is disabled.
bogdanm 82:6473597d706e 2463 * - 1 - The deadtime insertion in this pair of channels is enabled.
bogdanm 82:6473597d706e 2464 */
bogdanm 82:6473597d706e 2465 //@{
bogdanm 82:6473597d706e 2466 #define BP_FTM_COMBINE_DTEN0 (4U) //!< Bit position for FTM_COMBINE_DTEN0.
bogdanm 82:6473597d706e 2467 #define BM_FTM_COMBINE_DTEN0 (0x00000010U) //!< Bit mask for FTM_COMBINE_DTEN0.
bogdanm 82:6473597d706e 2468 #define BS_FTM_COMBINE_DTEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN0.
bogdanm 82:6473597d706e 2469
bogdanm 82:6473597d706e 2470 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2471 //! @brief Read current value of the FTM_COMBINE_DTEN0 field.
bogdanm 82:6473597d706e 2472 #define BR_FTM_COMBINE_DTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0))
bogdanm 82:6473597d706e 2473 #endif
bogdanm 82:6473597d706e 2474
bogdanm 82:6473597d706e 2475 //! @brief Format value for bitfield FTM_COMBINE_DTEN0.
bogdanm 82:6473597d706e 2476 #define BF_FTM_COMBINE_DTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN0), uint32_t) & BM_FTM_COMBINE_DTEN0)
bogdanm 82:6473597d706e 2477
bogdanm 82:6473597d706e 2478 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2479 //! @brief Set the DTEN0 field to a new value.
bogdanm 82:6473597d706e 2480 #define BW_FTM_COMBINE_DTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0) = (v))
bogdanm 82:6473597d706e 2481 #endif
bogdanm 82:6473597d706e 2482 //@}
bogdanm 82:6473597d706e 2483
bogdanm 82:6473597d706e 2484 /*!
bogdanm 82:6473597d706e 2485 * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
bogdanm 82:6473597d706e 2486 *
bogdanm 82:6473597d706e 2487 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
bogdanm 82:6473597d706e 2488 *
bogdanm 82:6473597d706e 2489 * Values:
bogdanm 82:6473597d706e 2490 * - 0 - The PWM synchronization in this pair of channels is disabled.
bogdanm 82:6473597d706e 2491 * - 1 - The PWM synchronization in this pair of channels is enabled.
bogdanm 82:6473597d706e 2492 */
bogdanm 82:6473597d706e 2493 //@{
bogdanm 82:6473597d706e 2494 #define BP_FTM_COMBINE_SYNCEN0 (5U) //!< Bit position for FTM_COMBINE_SYNCEN0.
bogdanm 82:6473597d706e 2495 #define BM_FTM_COMBINE_SYNCEN0 (0x00000020U) //!< Bit mask for FTM_COMBINE_SYNCEN0.
bogdanm 82:6473597d706e 2496 #define BS_FTM_COMBINE_SYNCEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN0.
bogdanm 82:6473597d706e 2497
bogdanm 82:6473597d706e 2498 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2499 //! @brief Read current value of the FTM_COMBINE_SYNCEN0 field.
bogdanm 82:6473597d706e 2500 #define BR_FTM_COMBINE_SYNCEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0))
bogdanm 82:6473597d706e 2501 #endif
bogdanm 82:6473597d706e 2502
bogdanm 82:6473597d706e 2503 //! @brief Format value for bitfield FTM_COMBINE_SYNCEN0.
bogdanm 82:6473597d706e 2504 #define BF_FTM_COMBINE_SYNCEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN0), uint32_t) & BM_FTM_COMBINE_SYNCEN0)
bogdanm 82:6473597d706e 2505
bogdanm 82:6473597d706e 2506 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2507 //! @brief Set the SYNCEN0 field to a new value.
bogdanm 82:6473597d706e 2508 #define BW_FTM_COMBINE_SYNCEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0) = (v))
bogdanm 82:6473597d706e 2509 #endif
bogdanm 82:6473597d706e 2510 //@}
bogdanm 82:6473597d706e 2511
bogdanm 82:6473597d706e 2512 /*!
bogdanm 82:6473597d706e 2513 * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
bogdanm 82:6473597d706e 2514 *
bogdanm 82:6473597d706e 2515 * Enables the fault control in channels (n) and (n+1). This field is write
bogdanm 82:6473597d706e 2516 * protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2517 *
bogdanm 82:6473597d706e 2518 * Values:
bogdanm 82:6473597d706e 2519 * - 0 - The fault control in this pair of channels is disabled.
bogdanm 82:6473597d706e 2520 * - 1 - The fault control in this pair of channels is enabled.
bogdanm 82:6473597d706e 2521 */
bogdanm 82:6473597d706e 2522 //@{
bogdanm 82:6473597d706e 2523 #define BP_FTM_COMBINE_FAULTEN0 (6U) //!< Bit position for FTM_COMBINE_FAULTEN0.
bogdanm 82:6473597d706e 2524 #define BM_FTM_COMBINE_FAULTEN0 (0x00000040U) //!< Bit mask for FTM_COMBINE_FAULTEN0.
bogdanm 82:6473597d706e 2525 #define BS_FTM_COMBINE_FAULTEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN0.
bogdanm 82:6473597d706e 2526
bogdanm 82:6473597d706e 2527 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2528 //! @brief Read current value of the FTM_COMBINE_FAULTEN0 field.
bogdanm 82:6473597d706e 2529 #define BR_FTM_COMBINE_FAULTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0))
bogdanm 82:6473597d706e 2530 #endif
bogdanm 82:6473597d706e 2531
bogdanm 82:6473597d706e 2532 //! @brief Format value for bitfield FTM_COMBINE_FAULTEN0.
bogdanm 82:6473597d706e 2533 #define BF_FTM_COMBINE_FAULTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN0), uint32_t) & BM_FTM_COMBINE_FAULTEN0)
bogdanm 82:6473597d706e 2534
bogdanm 82:6473597d706e 2535 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2536 //! @brief Set the FAULTEN0 field to a new value.
bogdanm 82:6473597d706e 2537 #define BW_FTM_COMBINE_FAULTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0) = (v))
bogdanm 82:6473597d706e 2538 #endif
bogdanm 82:6473597d706e 2539 //@}
bogdanm 82:6473597d706e 2540
bogdanm 82:6473597d706e 2541 /*!
bogdanm 82:6473597d706e 2542 * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
bogdanm 82:6473597d706e 2543 *
bogdanm 82:6473597d706e 2544 * Enables the combine feature for channels (n) and (n+1). This field is write
bogdanm 82:6473597d706e 2545 * protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2546 *
bogdanm 82:6473597d706e 2547 * Values:
bogdanm 82:6473597d706e 2548 * - 0 - Channels (n) and (n+1) are independent.
bogdanm 82:6473597d706e 2549 * - 1 - Channels (n) and (n+1) are combined.
bogdanm 82:6473597d706e 2550 */
bogdanm 82:6473597d706e 2551 //@{
bogdanm 82:6473597d706e 2552 #define BP_FTM_COMBINE_COMBINE1 (8U) //!< Bit position for FTM_COMBINE_COMBINE1.
bogdanm 82:6473597d706e 2553 #define BM_FTM_COMBINE_COMBINE1 (0x00000100U) //!< Bit mask for FTM_COMBINE_COMBINE1.
bogdanm 82:6473597d706e 2554 #define BS_FTM_COMBINE_COMBINE1 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE1.
bogdanm 82:6473597d706e 2555
bogdanm 82:6473597d706e 2556 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2557 //! @brief Read current value of the FTM_COMBINE_COMBINE1 field.
bogdanm 82:6473597d706e 2558 #define BR_FTM_COMBINE_COMBINE1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1))
bogdanm 82:6473597d706e 2559 #endif
bogdanm 82:6473597d706e 2560
bogdanm 82:6473597d706e 2561 //! @brief Format value for bitfield FTM_COMBINE_COMBINE1.
bogdanm 82:6473597d706e 2562 #define BF_FTM_COMBINE_COMBINE1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE1), uint32_t) & BM_FTM_COMBINE_COMBINE1)
bogdanm 82:6473597d706e 2563
bogdanm 82:6473597d706e 2564 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2565 //! @brief Set the COMBINE1 field to a new value.
bogdanm 82:6473597d706e 2566 #define BW_FTM_COMBINE_COMBINE1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1) = (v))
bogdanm 82:6473597d706e 2567 #endif
bogdanm 82:6473597d706e 2568 //@}
bogdanm 82:6473597d706e 2569
bogdanm 82:6473597d706e 2570 /*!
bogdanm 82:6473597d706e 2571 * @name Register FTM_COMBINE, field COMP1[9] (RW)
bogdanm 82:6473597d706e 2572 *
bogdanm 82:6473597d706e 2573 * Enables Complementary mode for the combined channels. In Complementary mode
bogdanm 82:6473597d706e 2574 * the channel (n+1) output is the inverse of the channel (n) output. This field
bogdanm 82:6473597d706e 2575 * is write protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2576 *
bogdanm 82:6473597d706e 2577 * Values:
bogdanm 82:6473597d706e 2578 * - 0 - The channel (n+1) output is the same as the channel (n) output.
bogdanm 82:6473597d706e 2579 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
bogdanm 82:6473597d706e 2580 */
bogdanm 82:6473597d706e 2581 //@{
bogdanm 82:6473597d706e 2582 #define BP_FTM_COMBINE_COMP1 (9U) //!< Bit position for FTM_COMBINE_COMP1.
bogdanm 82:6473597d706e 2583 #define BM_FTM_COMBINE_COMP1 (0x00000200U) //!< Bit mask for FTM_COMBINE_COMP1.
bogdanm 82:6473597d706e 2584 #define BS_FTM_COMBINE_COMP1 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP1.
bogdanm 82:6473597d706e 2585
bogdanm 82:6473597d706e 2586 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2587 //! @brief Read current value of the FTM_COMBINE_COMP1 field.
bogdanm 82:6473597d706e 2588 #define BR_FTM_COMBINE_COMP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1))
bogdanm 82:6473597d706e 2589 #endif
bogdanm 82:6473597d706e 2590
bogdanm 82:6473597d706e 2591 //! @brief Format value for bitfield FTM_COMBINE_COMP1.
bogdanm 82:6473597d706e 2592 #define BF_FTM_COMBINE_COMP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP1), uint32_t) & BM_FTM_COMBINE_COMP1)
bogdanm 82:6473597d706e 2593
bogdanm 82:6473597d706e 2594 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2595 //! @brief Set the COMP1 field to a new value.
bogdanm 82:6473597d706e 2596 #define BW_FTM_COMBINE_COMP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1) = (v))
bogdanm 82:6473597d706e 2597 #endif
bogdanm 82:6473597d706e 2598 //@}
bogdanm 82:6473597d706e 2599
bogdanm 82:6473597d706e 2600 /*!
bogdanm 82:6473597d706e 2601 * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
bogdanm 82:6473597d706e 2602 *
bogdanm 82:6473597d706e 2603 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
bogdanm 82:6473597d706e 2604 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
bogdanm 82:6473597d706e 2605 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
bogdanm 82:6473597d706e 2606 * when FTMEN = 1. This field is write protected. It can be written only when
bogdanm 82:6473597d706e 2607 * MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2608 *
bogdanm 82:6473597d706e 2609 * Values:
bogdanm 82:6473597d706e 2610 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
bogdanm 82:6473597d706e 2611 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
bogdanm 82:6473597d706e 2612 */
bogdanm 82:6473597d706e 2613 //@{
bogdanm 82:6473597d706e 2614 #define BP_FTM_COMBINE_DECAPEN1 (10U) //!< Bit position for FTM_COMBINE_DECAPEN1.
bogdanm 82:6473597d706e 2615 #define BM_FTM_COMBINE_DECAPEN1 (0x00000400U) //!< Bit mask for FTM_COMBINE_DECAPEN1.
bogdanm 82:6473597d706e 2616 #define BS_FTM_COMBINE_DECAPEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN1.
bogdanm 82:6473597d706e 2617
bogdanm 82:6473597d706e 2618 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2619 //! @brief Read current value of the FTM_COMBINE_DECAPEN1 field.
bogdanm 82:6473597d706e 2620 #define BR_FTM_COMBINE_DECAPEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1))
bogdanm 82:6473597d706e 2621 #endif
bogdanm 82:6473597d706e 2622
bogdanm 82:6473597d706e 2623 //! @brief Format value for bitfield FTM_COMBINE_DECAPEN1.
bogdanm 82:6473597d706e 2624 #define BF_FTM_COMBINE_DECAPEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN1), uint32_t) & BM_FTM_COMBINE_DECAPEN1)
bogdanm 82:6473597d706e 2625
bogdanm 82:6473597d706e 2626 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2627 //! @brief Set the DECAPEN1 field to a new value.
bogdanm 82:6473597d706e 2628 #define BW_FTM_COMBINE_DECAPEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1) = (v))
bogdanm 82:6473597d706e 2629 #endif
bogdanm 82:6473597d706e 2630 //@}
bogdanm 82:6473597d706e 2631
bogdanm 82:6473597d706e 2632 /*!
bogdanm 82:6473597d706e 2633 * @name Register FTM_COMBINE, field DECAP1[11] (RW)
bogdanm 82:6473597d706e 2634 *
bogdanm 82:6473597d706e 2635 * Enables the capture of the FTM counter value according to the channel (n)
bogdanm 82:6473597d706e 2636 * input event and the configuration of the dual edge capture bits. This field
bogdanm 82:6473597d706e 2637 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
bogdanm 82:6473597d706e 2638 * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
bogdanm 82:6473597d706e 2639 * of channel (n+1) event is made.
bogdanm 82:6473597d706e 2640 *
bogdanm 82:6473597d706e 2641 * Values:
bogdanm 82:6473597d706e 2642 * - 0 - The dual edge captures are inactive.
bogdanm 82:6473597d706e 2643 * - 1 - The dual edge captures are active.
bogdanm 82:6473597d706e 2644 */
bogdanm 82:6473597d706e 2645 //@{
bogdanm 82:6473597d706e 2646 #define BP_FTM_COMBINE_DECAP1 (11U) //!< Bit position for FTM_COMBINE_DECAP1.
bogdanm 82:6473597d706e 2647 #define BM_FTM_COMBINE_DECAP1 (0x00000800U) //!< Bit mask for FTM_COMBINE_DECAP1.
bogdanm 82:6473597d706e 2648 #define BS_FTM_COMBINE_DECAP1 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP1.
bogdanm 82:6473597d706e 2649
bogdanm 82:6473597d706e 2650 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2651 //! @brief Read current value of the FTM_COMBINE_DECAP1 field.
bogdanm 82:6473597d706e 2652 #define BR_FTM_COMBINE_DECAP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1))
bogdanm 82:6473597d706e 2653 #endif
bogdanm 82:6473597d706e 2654
bogdanm 82:6473597d706e 2655 //! @brief Format value for bitfield FTM_COMBINE_DECAP1.
bogdanm 82:6473597d706e 2656 #define BF_FTM_COMBINE_DECAP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP1), uint32_t) & BM_FTM_COMBINE_DECAP1)
bogdanm 82:6473597d706e 2657
bogdanm 82:6473597d706e 2658 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2659 //! @brief Set the DECAP1 field to a new value.
bogdanm 82:6473597d706e 2660 #define BW_FTM_COMBINE_DECAP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1) = (v))
bogdanm 82:6473597d706e 2661 #endif
bogdanm 82:6473597d706e 2662 //@}
bogdanm 82:6473597d706e 2663
bogdanm 82:6473597d706e 2664 /*!
bogdanm 82:6473597d706e 2665 * @name Register FTM_COMBINE, field DTEN1[12] (RW)
bogdanm 82:6473597d706e 2666 *
bogdanm 82:6473597d706e 2667 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
bogdanm 82:6473597d706e 2668 * write protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2669 *
bogdanm 82:6473597d706e 2670 * Values:
bogdanm 82:6473597d706e 2671 * - 0 - The deadtime insertion in this pair of channels is disabled.
bogdanm 82:6473597d706e 2672 * - 1 - The deadtime insertion in this pair of channels is enabled.
bogdanm 82:6473597d706e 2673 */
bogdanm 82:6473597d706e 2674 //@{
bogdanm 82:6473597d706e 2675 #define BP_FTM_COMBINE_DTEN1 (12U) //!< Bit position for FTM_COMBINE_DTEN1.
bogdanm 82:6473597d706e 2676 #define BM_FTM_COMBINE_DTEN1 (0x00001000U) //!< Bit mask for FTM_COMBINE_DTEN1.
bogdanm 82:6473597d706e 2677 #define BS_FTM_COMBINE_DTEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN1.
bogdanm 82:6473597d706e 2678
bogdanm 82:6473597d706e 2679 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2680 //! @brief Read current value of the FTM_COMBINE_DTEN1 field.
bogdanm 82:6473597d706e 2681 #define BR_FTM_COMBINE_DTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1))
bogdanm 82:6473597d706e 2682 #endif
bogdanm 82:6473597d706e 2683
bogdanm 82:6473597d706e 2684 //! @brief Format value for bitfield FTM_COMBINE_DTEN1.
bogdanm 82:6473597d706e 2685 #define BF_FTM_COMBINE_DTEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN1), uint32_t) & BM_FTM_COMBINE_DTEN1)
bogdanm 82:6473597d706e 2686
bogdanm 82:6473597d706e 2687 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2688 //! @brief Set the DTEN1 field to a new value.
bogdanm 82:6473597d706e 2689 #define BW_FTM_COMBINE_DTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1) = (v))
bogdanm 82:6473597d706e 2690 #endif
bogdanm 82:6473597d706e 2691 //@}
bogdanm 82:6473597d706e 2692
bogdanm 82:6473597d706e 2693 /*!
bogdanm 82:6473597d706e 2694 * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
bogdanm 82:6473597d706e 2695 *
bogdanm 82:6473597d706e 2696 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
bogdanm 82:6473597d706e 2697 *
bogdanm 82:6473597d706e 2698 * Values:
bogdanm 82:6473597d706e 2699 * - 0 - The PWM synchronization in this pair of channels is disabled.
bogdanm 82:6473597d706e 2700 * - 1 - The PWM synchronization in this pair of channels is enabled.
bogdanm 82:6473597d706e 2701 */
bogdanm 82:6473597d706e 2702 //@{
bogdanm 82:6473597d706e 2703 #define BP_FTM_COMBINE_SYNCEN1 (13U) //!< Bit position for FTM_COMBINE_SYNCEN1.
bogdanm 82:6473597d706e 2704 #define BM_FTM_COMBINE_SYNCEN1 (0x00002000U) //!< Bit mask for FTM_COMBINE_SYNCEN1.
bogdanm 82:6473597d706e 2705 #define BS_FTM_COMBINE_SYNCEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN1.
bogdanm 82:6473597d706e 2706
bogdanm 82:6473597d706e 2707 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2708 //! @brief Read current value of the FTM_COMBINE_SYNCEN1 field.
bogdanm 82:6473597d706e 2709 #define BR_FTM_COMBINE_SYNCEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1))
bogdanm 82:6473597d706e 2710 #endif
bogdanm 82:6473597d706e 2711
bogdanm 82:6473597d706e 2712 //! @brief Format value for bitfield FTM_COMBINE_SYNCEN1.
bogdanm 82:6473597d706e 2713 #define BF_FTM_COMBINE_SYNCEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN1), uint32_t) & BM_FTM_COMBINE_SYNCEN1)
bogdanm 82:6473597d706e 2714
bogdanm 82:6473597d706e 2715 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2716 //! @brief Set the SYNCEN1 field to a new value.
bogdanm 82:6473597d706e 2717 #define BW_FTM_COMBINE_SYNCEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1) = (v))
bogdanm 82:6473597d706e 2718 #endif
bogdanm 82:6473597d706e 2719 //@}
bogdanm 82:6473597d706e 2720
bogdanm 82:6473597d706e 2721 /*!
bogdanm 82:6473597d706e 2722 * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
bogdanm 82:6473597d706e 2723 *
bogdanm 82:6473597d706e 2724 * Enables the fault control in channels (n) and (n+1). This field is write
bogdanm 82:6473597d706e 2725 * protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2726 *
bogdanm 82:6473597d706e 2727 * Values:
bogdanm 82:6473597d706e 2728 * - 0 - The fault control in this pair of channels is disabled.
bogdanm 82:6473597d706e 2729 * - 1 - The fault control in this pair of channels is enabled.
bogdanm 82:6473597d706e 2730 */
bogdanm 82:6473597d706e 2731 //@{
bogdanm 82:6473597d706e 2732 #define BP_FTM_COMBINE_FAULTEN1 (14U) //!< Bit position for FTM_COMBINE_FAULTEN1.
bogdanm 82:6473597d706e 2733 #define BM_FTM_COMBINE_FAULTEN1 (0x00004000U) //!< Bit mask for FTM_COMBINE_FAULTEN1.
bogdanm 82:6473597d706e 2734 #define BS_FTM_COMBINE_FAULTEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN1.
bogdanm 82:6473597d706e 2735
bogdanm 82:6473597d706e 2736 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2737 //! @brief Read current value of the FTM_COMBINE_FAULTEN1 field.
bogdanm 82:6473597d706e 2738 #define BR_FTM_COMBINE_FAULTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1))
bogdanm 82:6473597d706e 2739 #endif
bogdanm 82:6473597d706e 2740
bogdanm 82:6473597d706e 2741 //! @brief Format value for bitfield FTM_COMBINE_FAULTEN1.
bogdanm 82:6473597d706e 2742 #define BF_FTM_COMBINE_FAULTEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN1), uint32_t) & BM_FTM_COMBINE_FAULTEN1)
bogdanm 82:6473597d706e 2743
bogdanm 82:6473597d706e 2744 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2745 //! @brief Set the FAULTEN1 field to a new value.
bogdanm 82:6473597d706e 2746 #define BW_FTM_COMBINE_FAULTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1) = (v))
bogdanm 82:6473597d706e 2747 #endif
bogdanm 82:6473597d706e 2748 //@}
bogdanm 82:6473597d706e 2749
bogdanm 82:6473597d706e 2750 /*!
bogdanm 82:6473597d706e 2751 * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
bogdanm 82:6473597d706e 2752 *
bogdanm 82:6473597d706e 2753 * Enables the combine feature for channels (n) and (n+1). This field is write
bogdanm 82:6473597d706e 2754 * protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2755 *
bogdanm 82:6473597d706e 2756 * Values:
bogdanm 82:6473597d706e 2757 * - 0 - Channels (n) and (n+1) are independent.
bogdanm 82:6473597d706e 2758 * - 1 - Channels (n) and (n+1) are combined.
bogdanm 82:6473597d706e 2759 */
bogdanm 82:6473597d706e 2760 //@{
bogdanm 82:6473597d706e 2761 #define BP_FTM_COMBINE_COMBINE2 (16U) //!< Bit position for FTM_COMBINE_COMBINE2.
bogdanm 82:6473597d706e 2762 #define BM_FTM_COMBINE_COMBINE2 (0x00010000U) //!< Bit mask for FTM_COMBINE_COMBINE2.
bogdanm 82:6473597d706e 2763 #define BS_FTM_COMBINE_COMBINE2 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE2.
bogdanm 82:6473597d706e 2764
bogdanm 82:6473597d706e 2765 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2766 //! @brief Read current value of the FTM_COMBINE_COMBINE2 field.
bogdanm 82:6473597d706e 2767 #define BR_FTM_COMBINE_COMBINE2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2))
bogdanm 82:6473597d706e 2768 #endif
bogdanm 82:6473597d706e 2769
bogdanm 82:6473597d706e 2770 //! @brief Format value for bitfield FTM_COMBINE_COMBINE2.
bogdanm 82:6473597d706e 2771 #define BF_FTM_COMBINE_COMBINE2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE2), uint32_t) & BM_FTM_COMBINE_COMBINE2)
bogdanm 82:6473597d706e 2772
bogdanm 82:6473597d706e 2773 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2774 //! @brief Set the COMBINE2 field to a new value.
bogdanm 82:6473597d706e 2775 #define BW_FTM_COMBINE_COMBINE2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2) = (v))
bogdanm 82:6473597d706e 2776 #endif
bogdanm 82:6473597d706e 2777 //@}
bogdanm 82:6473597d706e 2778
bogdanm 82:6473597d706e 2779 /*!
bogdanm 82:6473597d706e 2780 * @name Register FTM_COMBINE, field COMP2[17] (RW)
bogdanm 82:6473597d706e 2781 *
bogdanm 82:6473597d706e 2782 * Enables Complementary mode for the combined channels. In Complementary mode
bogdanm 82:6473597d706e 2783 * the channel (n+1) output is the inverse of the channel (n) output. This field
bogdanm 82:6473597d706e 2784 * is write protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2785 *
bogdanm 82:6473597d706e 2786 * Values:
bogdanm 82:6473597d706e 2787 * - 0 - The channel (n+1) output is the same as the channel (n) output.
bogdanm 82:6473597d706e 2788 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
bogdanm 82:6473597d706e 2789 */
bogdanm 82:6473597d706e 2790 //@{
bogdanm 82:6473597d706e 2791 #define BP_FTM_COMBINE_COMP2 (17U) //!< Bit position for FTM_COMBINE_COMP2.
bogdanm 82:6473597d706e 2792 #define BM_FTM_COMBINE_COMP2 (0x00020000U) //!< Bit mask for FTM_COMBINE_COMP2.
bogdanm 82:6473597d706e 2793 #define BS_FTM_COMBINE_COMP2 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP2.
bogdanm 82:6473597d706e 2794
bogdanm 82:6473597d706e 2795 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2796 //! @brief Read current value of the FTM_COMBINE_COMP2 field.
bogdanm 82:6473597d706e 2797 #define BR_FTM_COMBINE_COMP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2))
bogdanm 82:6473597d706e 2798 #endif
bogdanm 82:6473597d706e 2799
bogdanm 82:6473597d706e 2800 //! @brief Format value for bitfield FTM_COMBINE_COMP2.
bogdanm 82:6473597d706e 2801 #define BF_FTM_COMBINE_COMP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP2), uint32_t) & BM_FTM_COMBINE_COMP2)
bogdanm 82:6473597d706e 2802
bogdanm 82:6473597d706e 2803 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2804 //! @brief Set the COMP2 field to a new value.
bogdanm 82:6473597d706e 2805 #define BW_FTM_COMBINE_COMP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2) = (v))
bogdanm 82:6473597d706e 2806 #endif
bogdanm 82:6473597d706e 2807 //@}
bogdanm 82:6473597d706e 2808
bogdanm 82:6473597d706e 2809 /*!
bogdanm 82:6473597d706e 2810 * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
bogdanm 82:6473597d706e 2811 *
bogdanm 82:6473597d706e 2812 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
bogdanm 82:6473597d706e 2813 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
bogdanm 82:6473597d706e 2814 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
bogdanm 82:6473597d706e 2815 * when FTMEN = 1. This field is write protected. It can be written only when
bogdanm 82:6473597d706e 2816 * MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2817 *
bogdanm 82:6473597d706e 2818 * Values:
bogdanm 82:6473597d706e 2819 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
bogdanm 82:6473597d706e 2820 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
bogdanm 82:6473597d706e 2821 */
bogdanm 82:6473597d706e 2822 //@{
bogdanm 82:6473597d706e 2823 #define BP_FTM_COMBINE_DECAPEN2 (18U) //!< Bit position for FTM_COMBINE_DECAPEN2.
bogdanm 82:6473597d706e 2824 #define BM_FTM_COMBINE_DECAPEN2 (0x00040000U) //!< Bit mask for FTM_COMBINE_DECAPEN2.
bogdanm 82:6473597d706e 2825 #define BS_FTM_COMBINE_DECAPEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN2.
bogdanm 82:6473597d706e 2826
bogdanm 82:6473597d706e 2827 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2828 //! @brief Read current value of the FTM_COMBINE_DECAPEN2 field.
bogdanm 82:6473597d706e 2829 #define BR_FTM_COMBINE_DECAPEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2))
bogdanm 82:6473597d706e 2830 #endif
bogdanm 82:6473597d706e 2831
bogdanm 82:6473597d706e 2832 //! @brief Format value for bitfield FTM_COMBINE_DECAPEN2.
bogdanm 82:6473597d706e 2833 #define BF_FTM_COMBINE_DECAPEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN2), uint32_t) & BM_FTM_COMBINE_DECAPEN2)
bogdanm 82:6473597d706e 2834
bogdanm 82:6473597d706e 2835 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2836 //! @brief Set the DECAPEN2 field to a new value.
bogdanm 82:6473597d706e 2837 #define BW_FTM_COMBINE_DECAPEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2) = (v))
bogdanm 82:6473597d706e 2838 #endif
bogdanm 82:6473597d706e 2839 //@}
bogdanm 82:6473597d706e 2840
bogdanm 82:6473597d706e 2841 /*!
bogdanm 82:6473597d706e 2842 * @name Register FTM_COMBINE, field DECAP2[19] (RW)
bogdanm 82:6473597d706e 2843 *
bogdanm 82:6473597d706e 2844 * Enables the capture of the FTM counter value according to the channel (n)
bogdanm 82:6473597d706e 2845 * input event and the configuration of the dual edge capture bits. This field
bogdanm 82:6473597d706e 2846 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
bogdanm 82:6473597d706e 2847 * hardware if dual edge capture - one-shot mode is selected and when the capture
bogdanm 82:6473597d706e 2848 * of channel (n+1) event is made.
bogdanm 82:6473597d706e 2849 *
bogdanm 82:6473597d706e 2850 * Values:
bogdanm 82:6473597d706e 2851 * - 0 - The dual edge captures are inactive.
bogdanm 82:6473597d706e 2852 * - 1 - The dual edge captures are active.
bogdanm 82:6473597d706e 2853 */
bogdanm 82:6473597d706e 2854 //@{
bogdanm 82:6473597d706e 2855 #define BP_FTM_COMBINE_DECAP2 (19U) //!< Bit position for FTM_COMBINE_DECAP2.
bogdanm 82:6473597d706e 2856 #define BM_FTM_COMBINE_DECAP2 (0x00080000U) //!< Bit mask for FTM_COMBINE_DECAP2.
bogdanm 82:6473597d706e 2857 #define BS_FTM_COMBINE_DECAP2 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP2.
bogdanm 82:6473597d706e 2858
bogdanm 82:6473597d706e 2859 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2860 //! @brief Read current value of the FTM_COMBINE_DECAP2 field.
bogdanm 82:6473597d706e 2861 #define BR_FTM_COMBINE_DECAP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2))
bogdanm 82:6473597d706e 2862 #endif
bogdanm 82:6473597d706e 2863
bogdanm 82:6473597d706e 2864 //! @brief Format value for bitfield FTM_COMBINE_DECAP2.
bogdanm 82:6473597d706e 2865 #define BF_FTM_COMBINE_DECAP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP2), uint32_t) & BM_FTM_COMBINE_DECAP2)
bogdanm 82:6473597d706e 2866
bogdanm 82:6473597d706e 2867 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2868 //! @brief Set the DECAP2 field to a new value.
bogdanm 82:6473597d706e 2869 #define BW_FTM_COMBINE_DECAP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2) = (v))
bogdanm 82:6473597d706e 2870 #endif
bogdanm 82:6473597d706e 2871 //@}
bogdanm 82:6473597d706e 2872
bogdanm 82:6473597d706e 2873 /*!
bogdanm 82:6473597d706e 2874 * @name Register FTM_COMBINE, field DTEN2[20] (RW)
bogdanm 82:6473597d706e 2875 *
bogdanm 82:6473597d706e 2876 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
bogdanm 82:6473597d706e 2877 * write protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2878 *
bogdanm 82:6473597d706e 2879 * Values:
bogdanm 82:6473597d706e 2880 * - 0 - The deadtime insertion in this pair of channels is disabled.
bogdanm 82:6473597d706e 2881 * - 1 - The deadtime insertion in this pair of channels is enabled.
bogdanm 82:6473597d706e 2882 */
bogdanm 82:6473597d706e 2883 //@{
bogdanm 82:6473597d706e 2884 #define BP_FTM_COMBINE_DTEN2 (20U) //!< Bit position for FTM_COMBINE_DTEN2.
bogdanm 82:6473597d706e 2885 #define BM_FTM_COMBINE_DTEN2 (0x00100000U) //!< Bit mask for FTM_COMBINE_DTEN2.
bogdanm 82:6473597d706e 2886 #define BS_FTM_COMBINE_DTEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN2.
bogdanm 82:6473597d706e 2887
bogdanm 82:6473597d706e 2888 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2889 //! @brief Read current value of the FTM_COMBINE_DTEN2 field.
bogdanm 82:6473597d706e 2890 #define BR_FTM_COMBINE_DTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2))
bogdanm 82:6473597d706e 2891 #endif
bogdanm 82:6473597d706e 2892
bogdanm 82:6473597d706e 2893 //! @brief Format value for bitfield FTM_COMBINE_DTEN2.
bogdanm 82:6473597d706e 2894 #define BF_FTM_COMBINE_DTEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN2), uint32_t) & BM_FTM_COMBINE_DTEN2)
bogdanm 82:6473597d706e 2895
bogdanm 82:6473597d706e 2896 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2897 //! @brief Set the DTEN2 field to a new value.
bogdanm 82:6473597d706e 2898 #define BW_FTM_COMBINE_DTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2) = (v))
bogdanm 82:6473597d706e 2899 #endif
bogdanm 82:6473597d706e 2900 //@}
bogdanm 82:6473597d706e 2901
bogdanm 82:6473597d706e 2902 /*!
bogdanm 82:6473597d706e 2903 * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
bogdanm 82:6473597d706e 2904 *
bogdanm 82:6473597d706e 2905 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
bogdanm 82:6473597d706e 2906 *
bogdanm 82:6473597d706e 2907 * Values:
bogdanm 82:6473597d706e 2908 * - 0 - The PWM synchronization in this pair of channels is disabled.
bogdanm 82:6473597d706e 2909 * - 1 - The PWM synchronization in this pair of channels is enabled.
bogdanm 82:6473597d706e 2910 */
bogdanm 82:6473597d706e 2911 //@{
bogdanm 82:6473597d706e 2912 #define BP_FTM_COMBINE_SYNCEN2 (21U) //!< Bit position for FTM_COMBINE_SYNCEN2.
bogdanm 82:6473597d706e 2913 #define BM_FTM_COMBINE_SYNCEN2 (0x00200000U) //!< Bit mask for FTM_COMBINE_SYNCEN2.
bogdanm 82:6473597d706e 2914 #define BS_FTM_COMBINE_SYNCEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN2.
bogdanm 82:6473597d706e 2915
bogdanm 82:6473597d706e 2916 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2917 //! @brief Read current value of the FTM_COMBINE_SYNCEN2 field.
bogdanm 82:6473597d706e 2918 #define BR_FTM_COMBINE_SYNCEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2))
bogdanm 82:6473597d706e 2919 #endif
bogdanm 82:6473597d706e 2920
bogdanm 82:6473597d706e 2921 //! @brief Format value for bitfield FTM_COMBINE_SYNCEN2.
bogdanm 82:6473597d706e 2922 #define BF_FTM_COMBINE_SYNCEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN2), uint32_t) & BM_FTM_COMBINE_SYNCEN2)
bogdanm 82:6473597d706e 2923
bogdanm 82:6473597d706e 2924 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2925 //! @brief Set the SYNCEN2 field to a new value.
bogdanm 82:6473597d706e 2926 #define BW_FTM_COMBINE_SYNCEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2) = (v))
bogdanm 82:6473597d706e 2927 #endif
bogdanm 82:6473597d706e 2928 //@}
bogdanm 82:6473597d706e 2929
bogdanm 82:6473597d706e 2930 /*!
bogdanm 82:6473597d706e 2931 * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
bogdanm 82:6473597d706e 2932 *
bogdanm 82:6473597d706e 2933 * Enables the fault control in channels (n) and (n+1). This field is write
bogdanm 82:6473597d706e 2934 * protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2935 *
bogdanm 82:6473597d706e 2936 * Values:
bogdanm 82:6473597d706e 2937 * - 0 - The fault control in this pair of channels is disabled.
bogdanm 82:6473597d706e 2938 * - 1 - The fault control in this pair of channels is enabled.
bogdanm 82:6473597d706e 2939 */
bogdanm 82:6473597d706e 2940 //@{
bogdanm 82:6473597d706e 2941 #define BP_FTM_COMBINE_FAULTEN2 (22U) //!< Bit position for FTM_COMBINE_FAULTEN2.
bogdanm 82:6473597d706e 2942 #define BM_FTM_COMBINE_FAULTEN2 (0x00400000U) //!< Bit mask for FTM_COMBINE_FAULTEN2.
bogdanm 82:6473597d706e 2943 #define BS_FTM_COMBINE_FAULTEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN2.
bogdanm 82:6473597d706e 2944
bogdanm 82:6473597d706e 2945 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2946 //! @brief Read current value of the FTM_COMBINE_FAULTEN2 field.
bogdanm 82:6473597d706e 2947 #define BR_FTM_COMBINE_FAULTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2))
bogdanm 82:6473597d706e 2948 #endif
bogdanm 82:6473597d706e 2949
bogdanm 82:6473597d706e 2950 //! @brief Format value for bitfield FTM_COMBINE_FAULTEN2.
bogdanm 82:6473597d706e 2951 #define BF_FTM_COMBINE_FAULTEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN2), uint32_t) & BM_FTM_COMBINE_FAULTEN2)
bogdanm 82:6473597d706e 2952
bogdanm 82:6473597d706e 2953 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2954 //! @brief Set the FAULTEN2 field to a new value.
bogdanm 82:6473597d706e 2955 #define BW_FTM_COMBINE_FAULTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2) = (v))
bogdanm 82:6473597d706e 2956 #endif
bogdanm 82:6473597d706e 2957 //@}
bogdanm 82:6473597d706e 2958
bogdanm 82:6473597d706e 2959 /*!
bogdanm 82:6473597d706e 2960 * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
bogdanm 82:6473597d706e 2961 *
bogdanm 82:6473597d706e 2962 * Enables the combine feature for channels (n) and (n+1). This field is write
bogdanm 82:6473597d706e 2963 * protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2964 *
bogdanm 82:6473597d706e 2965 * Values:
bogdanm 82:6473597d706e 2966 * - 0 - Channels (n) and (n+1) are independent.
bogdanm 82:6473597d706e 2967 * - 1 - Channels (n) and (n+1) are combined.
bogdanm 82:6473597d706e 2968 */
bogdanm 82:6473597d706e 2969 //@{
bogdanm 82:6473597d706e 2970 #define BP_FTM_COMBINE_COMBINE3 (24U) //!< Bit position for FTM_COMBINE_COMBINE3.
bogdanm 82:6473597d706e 2971 #define BM_FTM_COMBINE_COMBINE3 (0x01000000U) //!< Bit mask for FTM_COMBINE_COMBINE3.
bogdanm 82:6473597d706e 2972 #define BS_FTM_COMBINE_COMBINE3 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE3.
bogdanm 82:6473597d706e 2973
bogdanm 82:6473597d706e 2974 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2975 //! @brief Read current value of the FTM_COMBINE_COMBINE3 field.
bogdanm 82:6473597d706e 2976 #define BR_FTM_COMBINE_COMBINE3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3))
bogdanm 82:6473597d706e 2977 #endif
bogdanm 82:6473597d706e 2978
bogdanm 82:6473597d706e 2979 //! @brief Format value for bitfield FTM_COMBINE_COMBINE3.
bogdanm 82:6473597d706e 2980 #define BF_FTM_COMBINE_COMBINE3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE3), uint32_t) & BM_FTM_COMBINE_COMBINE3)
bogdanm 82:6473597d706e 2981
bogdanm 82:6473597d706e 2982 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2983 //! @brief Set the COMBINE3 field to a new value.
bogdanm 82:6473597d706e 2984 #define BW_FTM_COMBINE_COMBINE3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3) = (v))
bogdanm 82:6473597d706e 2985 #endif
bogdanm 82:6473597d706e 2986 //@}
bogdanm 82:6473597d706e 2987
bogdanm 82:6473597d706e 2988 /*!
bogdanm 82:6473597d706e 2989 * @name Register FTM_COMBINE, field COMP3[25] (RW)
bogdanm 82:6473597d706e 2990 *
bogdanm 82:6473597d706e 2991 * Enables Complementary mode for the combined channels. In Complementary mode
bogdanm 82:6473597d706e 2992 * the channel (n+1) output is the inverse of the channel (n) output. This field
bogdanm 82:6473597d706e 2993 * is write protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 2994 *
bogdanm 82:6473597d706e 2995 * Values:
bogdanm 82:6473597d706e 2996 * - 0 - The channel (n+1) output is the same as the channel (n) output.
bogdanm 82:6473597d706e 2997 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
bogdanm 82:6473597d706e 2998 */
bogdanm 82:6473597d706e 2999 //@{
bogdanm 82:6473597d706e 3000 #define BP_FTM_COMBINE_COMP3 (25U) //!< Bit position for FTM_COMBINE_COMP3.
bogdanm 82:6473597d706e 3001 #define BM_FTM_COMBINE_COMP3 (0x02000000U) //!< Bit mask for FTM_COMBINE_COMP3.
bogdanm 82:6473597d706e 3002 #define BS_FTM_COMBINE_COMP3 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP3.
bogdanm 82:6473597d706e 3003
bogdanm 82:6473597d706e 3004 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3005 //! @brief Read current value of the FTM_COMBINE_COMP3 field.
bogdanm 82:6473597d706e 3006 #define BR_FTM_COMBINE_COMP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3))
bogdanm 82:6473597d706e 3007 #endif
bogdanm 82:6473597d706e 3008
bogdanm 82:6473597d706e 3009 //! @brief Format value for bitfield FTM_COMBINE_COMP3.
bogdanm 82:6473597d706e 3010 #define BF_FTM_COMBINE_COMP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP3), uint32_t) & BM_FTM_COMBINE_COMP3)
bogdanm 82:6473597d706e 3011
bogdanm 82:6473597d706e 3012 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3013 //! @brief Set the COMP3 field to a new value.
bogdanm 82:6473597d706e 3014 #define BW_FTM_COMBINE_COMP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3) = (v))
bogdanm 82:6473597d706e 3015 #endif
bogdanm 82:6473597d706e 3016 //@}
bogdanm 82:6473597d706e 3017
bogdanm 82:6473597d706e 3018 /*!
bogdanm 82:6473597d706e 3019 * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
bogdanm 82:6473597d706e 3020 *
bogdanm 82:6473597d706e 3021 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
bogdanm 82:6473597d706e 3022 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
bogdanm 82:6473597d706e 3023 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
bogdanm 82:6473597d706e 3024 * when FTMEN = 1. This field is write protected. It can be written only when
bogdanm 82:6473597d706e 3025 * MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 3026 *
bogdanm 82:6473597d706e 3027 * Values:
bogdanm 82:6473597d706e 3028 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
bogdanm 82:6473597d706e 3029 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
bogdanm 82:6473597d706e 3030 */
bogdanm 82:6473597d706e 3031 //@{
bogdanm 82:6473597d706e 3032 #define BP_FTM_COMBINE_DECAPEN3 (26U) //!< Bit position for FTM_COMBINE_DECAPEN3.
bogdanm 82:6473597d706e 3033 #define BM_FTM_COMBINE_DECAPEN3 (0x04000000U) //!< Bit mask for FTM_COMBINE_DECAPEN3.
bogdanm 82:6473597d706e 3034 #define BS_FTM_COMBINE_DECAPEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN3.
bogdanm 82:6473597d706e 3035
bogdanm 82:6473597d706e 3036 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3037 //! @brief Read current value of the FTM_COMBINE_DECAPEN3 field.
bogdanm 82:6473597d706e 3038 #define BR_FTM_COMBINE_DECAPEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3))
bogdanm 82:6473597d706e 3039 #endif
bogdanm 82:6473597d706e 3040
bogdanm 82:6473597d706e 3041 //! @brief Format value for bitfield FTM_COMBINE_DECAPEN3.
bogdanm 82:6473597d706e 3042 #define BF_FTM_COMBINE_DECAPEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN3), uint32_t) & BM_FTM_COMBINE_DECAPEN3)
bogdanm 82:6473597d706e 3043
bogdanm 82:6473597d706e 3044 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3045 //! @brief Set the DECAPEN3 field to a new value.
bogdanm 82:6473597d706e 3046 #define BW_FTM_COMBINE_DECAPEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3) = (v))
bogdanm 82:6473597d706e 3047 #endif
bogdanm 82:6473597d706e 3048 //@}
bogdanm 82:6473597d706e 3049
bogdanm 82:6473597d706e 3050 /*!
bogdanm 82:6473597d706e 3051 * @name Register FTM_COMBINE, field DECAP3[27] (RW)
bogdanm 82:6473597d706e 3052 *
bogdanm 82:6473597d706e 3053 * Enables the capture of the FTM counter value according to the channel (n)
bogdanm 82:6473597d706e 3054 * input event and the configuration of the dual edge capture bits. This field
bogdanm 82:6473597d706e 3055 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
bogdanm 82:6473597d706e 3056 * hardware if dual edge capture - one-shot mode is selected and when the capture
bogdanm 82:6473597d706e 3057 * of channel (n+1) event is made.
bogdanm 82:6473597d706e 3058 *
bogdanm 82:6473597d706e 3059 * Values:
bogdanm 82:6473597d706e 3060 * - 0 - The dual edge captures are inactive.
bogdanm 82:6473597d706e 3061 * - 1 - The dual edge captures are active.
bogdanm 82:6473597d706e 3062 */
bogdanm 82:6473597d706e 3063 //@{
bogdanm 82:6473597d706e 3064 #define BP_FTM_COMBINE_DECAP3 (27U) //!< Bit position for FTM_COMBINE_DECAP3.
bogdanm 82:6473597d706e 3065 #define BM_FTM_COMBINE_DECAP3 (0x08000000U) //!< Bit mask for FTM_COMBINE_DECAP3.
bogdanm 82:6473597d706e 3066 #define BS_FTM_COMBINE_DECAP3 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP3.
bogdanm 82:6473597d706e 3067
bogdanm 82:6473597d706e 3068 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3069 //! @brief Read current value of the FTM_COMBINE_DECAP3 field.
bogdanm 82:6473597d706e 3070 #define BR_FTM_COMBINE_DECAP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3))
bogdanm 82:6473597d706e 3071 #endif
bogdanm 82:6473597d706e 3072
bogdanm 82:6473597d706e 3073 //! @brief Format value for bitfield FTM_COMBINE_DECAP3.
bogdanm 82:6473597d706e 3074 #define BF_FTM_COMBINE_DECAP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP3), uint32_t) & BM_FTM_COMBINE_DECAP3)
bogdanm 82:6473597d706e 3075
bogdanm 82:6473597d706e 3076 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3077 //! @brief Set the DECAP3 field to a new value.
bogdanm 82:6473597d706e 3078 #define BW_FTM_COMBINE_DECAP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3) = (v))
bogdanm 82:6473597d706e 3079 #endif
bogdanm 82:6473597d706e 3080 //@}
bogdanm 82:6473597d706e 3081
bogdanm 82:6473597d706e 3082 /*!
bogdanm 82:6473597d706e 3083 * @name Register FTM_COMBINE, field DTEN3[28] (RW)
bogdanm 82:6473597d706e 3084 *
bogdanm 82:6473597d706e 3085 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
bogdanm 82:6473597d706e 3086 * write protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 3087 *
bogdanm 82:6473597d706e 3088 * Values:
bogdanm 82:6473597d706e 3089 * - 0 - The deadtime insertion in this pair of channels is disabled.
bogdanm 82:6473597d706e 3090 * - 1 - The deadtime insertion in this pair of channels is enabled.
bogdanm 82:6473597d706e 3091 */
bogdanm 82:6473597d706e 3092 //@{
bogdanm 82:6473597d706e 3093 #define BP_FTM_COMBINE_DTEN3 (28U) //!< Bit position for FTM_COMBINE_DTEN3.
bogdanm 82:6473597d706e 3094 #define BM_FTM_COMBINE_DTEN3 (0x10000000U) //!< Bit mask for FTM_COMBINE_DTEN3.
bogdanm 82:6473597d706e 3095 #define BS_FTM_COMBINE_DTEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN3.
bogdanm 82:6473597d706e 3096
bogdanm 82:6473597d706e 3097 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3098 //! @brief Read current value of the FTM_COMBINE_DTEN3 field.
bogdanm 82:6473597d706e 3099 #define BR_FTM_COMBINE_DTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3))
bogdanm 82:6473597d706e 3100 #endif
bogdanm 82:6473597d706e 3101
bogdanm 82:6473597d706e 3102 //! @brief Format value for bitfield FTM_COMBINE_DTEN3.
bogdanm 82:6473597d706e 3103 #define BF_FTM_COMBINE_DTEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN3), uint32_t) & BM_FTM_COMBINE_DTEN3)
bogdanm 82:6473597d706e 3104
bogdanm 82:6473597d706e 3105 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3106 //! @brief Set the DTEN3 field to a new value.
bogdanm 82:6473597d706e 3107 #define BW_FTM_COMBINE_DTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3) = (v))
bogdanm 82:6473597d706e 3108 #endif
bogdanm 82:6473597d706e 3109 //@}
bogdanm 82:6473597d706e 3110
bogdanm 82:6473597d706e 3111 /*!
bogdanm 82:6473597d706e 3112 * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
bogdanm 82:6473597d706e 3113 *
bogdanm 82:6473597d706e 3114 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
bogdanm 82:6473597d706e 3115 *
bogdanm 82:6473597d706e 3116 * Values:
bogdanm 82:6473597d706e 3117 * - 0 - The PWM synchronization in this pair of channels is disabled.
bogdanm 82:6473597d706e 3118 * - 1 - The PWM synchronization in this pair of channels is enabled.
bogdanm 82:6473597d706e 3119 */
bogdanm 82:6473597d706e 3120 //@{
bogdanm 82:6473597d706e 3121 #define BP_FTM_COMBINE_SYNCEN3 (29U) //!< Bit position for FTM_COMBINE_SYNCEN3.
bogdanm 82:6473597d706e 3122 #define BM_FTM_COMBINE_SYNCEN3 (0x20000000U) //!< Bit mask for FTM_COMBINE_SYNCEN3.
bogdanm 82:6473597d706e 3123 #define BS_FTM_COMBINE_SYNCEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN3.
bogdanm 82:6473597d706e 3124
bogdanm 82:6473597d706e 3125 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3126 //! @brief Read current value of the FTM_COMBINE_SYNCEN3 field.
bogdanm 82:6473597d706e 3127 #define BR_FTM_COMBINE_SYNCEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3))
bogdanm 82:6473597d706e 3128 #endif
bogdanm 82:6473597d706e 3129
bogdanm 82:6473597d706e 3130 //! @brief Format value for bitfield FTM_COMBINE_SYNCEN3.
bogdanm 82:6473597d706e 3131 #define BF_FTM_COMBINE_SYNCEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN3), uint32_t) & BM_FTM_COMBINE_SYNCEN3)
bogdanm 82:6473597d706e 3132
bogdanm 82:6473597d706e 3133 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3134 //! @brief Set the SYNCEN3 field to a new value.
bogdanm 82:6473597d706e 3135 #define BW_FTM_COMBINE_SYNCEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3) = (v))
bogdanm 82:6473597d706e 3136 #endif
bogdanm 82:6473597d706e 3137 //@}
bogdanm 82:6473597d706e 3138
bogdanm 82:6473597d706e 3139 /*!
bogdanm 82:6473597d706e 3140 * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
bogdanm 82:6473597d706e 3141 *
bogdanm 82:6473597d706e 3142 * Enables the fault control in channels (n) and (n+1). This field is write
bogdanm 82:6473597d706e 3143 * protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 3144 *
bogdanm 82:6473597d706e 3145 * Values:
bogdanm 82:6473597d706e 3146 * - 0 - The fault control in this pair of channels is disabled.
bogdanm 82:6473597d706e 3147 * - 1 - The fault control in this pair of channels is enabled.
bogdanm 82:6473597d706e 3148 */
bogdanm 82:6473597d706e 3149 //@{
bogdanm 82:6473597d706e 3150 #define BP_FTM_COMBINE_FAULTEN3 (30U) //!< Bit position for FTM_COMBINE_FAULTEN3.
bogdanm 82:6473597d706e 3151 #define BM_FTM_COMBINE_FAULTEN3 (0x40000000U) //!< Bit mask for FTM_COMBINE_FAULTEN3.
bogdanm 82:6473597d706e 3152 #define BS_FTM_COMBINE_FAULTEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN3.
bogdanm 82:6473597d706e 3153
bogdanm 82:6473597d706e 3154 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3155 //! @brief Read current value of the FTM_COMBINE_FAULTEN3 field.
bogdanm 82:6473597d706e 3156 #define BR_FTM_COMBINE_FAULTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3))
bogdanm 82:6473597d706e 3157 #endif
bogdanm 82:6473597d706e 3158
bogdanm 82:6473597d706e 3159 //! @brief Format value for bitfield FTM_COMBINE_FAULTEN3.
bogdanm 82:6473597d706e 3160 #define BF_FTM_COMBINE_FAULTEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN3), uint32_t) & BM_FTM_COMBINE_FAULTEN3)
bogdanm 82:6473597d706e 3161
bogdanm 82:6473597d706e 3162 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3163 //! @brief Set the FAULTEN3 field to a new value.
bogdanm 82:6473597d706e 3164 #define BW_FTM_COMBINE_FAULTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3) = (v))
bogdanm 82:6473597d706e 3165 #endif
bogdanm 82:6473597d706e 3166 //@}
bogdanm 82:6473597d706e 3167
bogdanm 82:6473597d706e 3168 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3169 // HW_FTM_DEADTIME - Deadtime Insertion Control
bogdanm 82:6473597d706e 3170 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3171
bogdanm 82:6473597d706e 3172 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3173 /*!
bogdanm 82:6473597d706e 3174 * @brief HW_FTM_DEADTIME - Deadtime Insertion Control (RW)
bogdanm 82:6473597d706e 3175 *
bogdanm 82:6473597d706e 3176 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 3177 *
bogdanm 82:6473597d706e 3178 * This register selects the deadtime prescaler factor and deadtime value. All
bogdanm 82:6473597d706e 3179 * FTM channels use this clock prescaler and this deadtime value for the deadtime
bogdanm 82:6473597d706e 3180 * insertion.
bogdanm 82:6473597d706e 3181 */
bogdanm 82:6473597d706e 3182 typedef union _hw_ftm_deadtime
bogdanm 82:6473597d706e 3183 {
bogdanm 82:6473597d706e 3184 uint32_t U;
bogdanm 82:6473597d706e 3185 struct _hw_ftm_deadtime_bitfields
bogdanm 82:6473597d706e 3186 {
bogdanm 82:6473597d706e 3187 uint32_t DTVAL : 6; //!< [5:0] Deadtime Value
bogdanm 82:6473597d706e 3188 uint32_t DTPS : 2; //!< [7:6] Deadtime Prescaler Value
bogdanm 82:6473597d706e 3189 uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm 82:6473597d706e 3190 } B;
bogdanm 82:6473597d706e 3191 } hw_ftm_deadtime_t;
bogdanm 82:6473597d706e 3192 #endif
bogdanm 82:6473597d706e 3193
bogdanm 82:6473597d706e 3194 /*!
bogdanm 82:6473597d706e 3195 * @name Constants and macros for entire FTM_DEADTIME register
bogdanm 82:6473597d706e 3196 */
bogdanm 82:6473597d706e 3197 //@{
bogdanm 82:6473597d706e 3198 #define HW_FTM_DEADTIME_ADDR(x) (REGS_FTM_BASE(x) + 0x68U)
bogdanm 82:6473597d706e 3199
bogdanm 82:6473597d706e 3200 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3201 #define HW_FTM_DEADTIME(x) (*(__IO hw_ftm_deadtime_t *) HW_FTM_DEADTIME_ADDR(x))
bogdanm 82:6473597d706e 3202 #define HW_FTM_DEADTIME_RD(x) (HW_FTM_DEADTIME(x).U)
bogdanm 82:6473597d706e 3203 #define HW_FTM_DEADTIME_WR(x, v) (HW_FTM_DEADTIME(x).U = (v))
bogdanm 82:6473597d706e 3204 #define HW_FTM_DEADTIME_SET(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) | (v)))
bogdanm 82:6473597d706e 3205 #define HW_FTM_DEADTIME_CLR(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) & ~(v)))
bogdanm 82:6473597d706e 3206 #define HW_FTM_DEADTIME_TOG(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) ^ (v)))
bogdanm 82:6473597d706e 3207 #endif
bogdanm 82:6473597d706e 3208 //@}
bogdanm 82:6473597d706e 3209
bogdanm 82:6473597d706e 3210 /*
bogdanm 82:6473597d706e 3211 * Constants & macros for individual FTM_DEADTIME bitfields
bogdanm 82:6473597d706e 3212 */
bogdanm 82:6473597d706e 3213
bogdanm 82:6473597d706e 3214 /*!
bogdanm 82:6473597d706e 3215 * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
bogdanm 82:6473597d706e 3216 *
bogdanm 82:6473597d706e 3217 * Selects the deadtime insertion value for the deadtime counter. The deadtime
bogdanm 82:6473597d706e 3218 * counter is clocked by a scaled version of the system clock. See the description
bogdanm 82:6473597d706e 3219 * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
bogdanm 82:6473597d706e 3220 * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
bogdanm 82:6473597d706e 3221 * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
bogdanm 82:6473597d706e 3222 * This pattern continues up to a possible 63 counts. This field is write
bogdanm 82:6473597d706e 3223 * protected. It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 3224 */
bogdanm 82:6473597d706e 3225 //@{
bogdanm 82:6473597d706e 3226 #define BP_FTM_DEADTIME_DTVAL (0U) //!< Bit position for FTM_DEADTIME_DTVAL.
bogdanm 82:6473597d706e 3227 #define BM_FTM_DEADTIME_DTVAL (0x0000003FU) //!< Bit mask for FTM_DEADTIME_DTVAL.
bogdanm 82:6473597d706e 3228 #define BS_FTM_DEADTIME_DTVAL (6U) //!< Bit field size in bits for FTM_DEADTIME_DTVAL.
bogdanm 82:6473597d706e 3229
bogdanm 82:6473597d706e 3230 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3231 //! @brief Read current value of the FTM_DEADTIME_DTVAL field.
bogdanm 82:6473597d706e 3232 #define BR_FTM_DEADTIME_DTVAL(x) (HW_FTM_DEADTIME(x).B.DTVAL)
bogdanm 82:6473597d706e 3233 #endif
bogdanm 82:6473597d706e 3234
bogdanm 82:6473597d706e 3235 //! @brief Format value for bitfield FTM_DEADTIME_DTVAL.
bogdanm 82:6473597d706e 3236 #define BF_FTM_DEADTIME_DTVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_DEADTIME_DTVAL), uint32_t) & BM_FTM_DEADTIME_DTVAL)
bogdanm 82:6473597d706e 3237
bogdanm 82:6473597d706e 3238 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3239 //! @brief Set the DTVAL field to a new value.
bogdanm 82:6473597d706e 3240 #define BW_FTM_DEADTIME_DTVAL(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTVAL) | BF_FTM_DEADTIME_DTVAL(v)))
bogdanm 82:6473597d706e 3241 #endif
bogdanm 82:6473597d706e 3242 //@}
bogdanm 82:6473597d706e 3243
bogdanm 82:6473597d706e 3244 /*!
bogdanm 82:6473597d706e 3245 * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
bogdanm 82:6473597d706e 3246 *
bogdanm 82:6473597d706e 3247 * Selects the division factor of the system clock. This prescaled clock is used
bogdanm 82:6473597d706e 3248 * by the deadtime counter. This field is write protected. It can be written
bogdanm 82:6473597d706e 3249 * only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 3250 *
bogdanm 82:6473597d706e 3251 * Values:
bogdanm 82:6473597d706e 3252 * - 0x - Divide the system clock by 1.
bogdanm 82:6473597d706e 3253 * - 10 - Divide the system clock by 4.
bogdanm 82:6473597d706e 3254 * - 11 - Divide the system clock by 16.
bogdanm 82:6473597d706e 3255 */
bogdanm 82:6473597d706e 3256 //@{
bogdanm 82:6473597d706e 3257 #define BP_FTM_DEADTIME_DTPS (6U) //!< Bit position for FTM_DEADTIME_DTPS.
bogdanm 82:6473597d706e 3258 #define BM_FTM_DEADTIME_DTPS (0x000000C0U) //!< Bit mask for FTM_DEADTIME_DTPS.
bogdanm 82:6473597d706e 3259 #define BS_FTM_DEADTIME_DTPS (2U) //!< Bit field size in bits for FTM_DEADTIME_DTPS.
bogdanm 82:6473597d706e 3260
bogdanm 82:6473597d706e 3261 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3262 //! @brief Read current value of the FTM_DEADTIME_DTPS field.
bogdanm 82:6473597d706e 3263 #define BR_FTM_DEADTIME_DTPS(x) (HW_FTM_DEADTIME(x).B.DTPS)
bogdanm 82:6473597d706e 3264 #endif
bogdanm 82:6473597d706e 3265
bogdanm 82:6473597d706e 3266 //! @brief Format value for bitfield FTM_DEADTIME_DTPS.
bogdanm 82:6473597d706e 3267 #define BF_FTM_DEADTIME_DTPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_DEADTIME_DTPS), uint32_t) & BM_FTM_DEADTIME_DTPS)
bogdanm 82:6473597d706e 3268
bogdanm 82:6473597d706e 3269 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3270 //! @brief Set the DTPS field to a new value.
bogdanm 82:6473597d706e 3271 #define BW_FTM_DEADTIME_DTPS(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTPS) | BF_FTM_DEADTIME_DTPS(v)))
bogdanm 82:6473597d706e 3272 #endif
bogdanm 82:6473597d706e 3273 //@}
bogdanm 82:6473597d706e 3274
bogdanm 82:6473597d706e 3275 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3276 // HW_FTM_EXTTRIG - FTM External Trigger
bogdanm 82:6473597d706e 3277 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3278
bogdanm 82:6473597d706e 3279 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3280 /*!
bogdanm 82:6473597d706e 3281 * @brief HW_FTM_EXTTRIG - FTM External Trigger (RW)
bogdanm 82:6473597d706e 3282 *
bogdanm 82:6473597d706e 3283 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 3284 *
bogdanm 82:6473597d706e 3285 * This register: Indicates when a channel trigger was generated Enables the
bogdanm 82:6473597d706e 3286 * generation of a trigger when the FTM counter is equal to its initial value
bogdanm 82:6473597d706e 3287 * Selects which channels are used in the generation of the channel triggers Several
bogdanm 82:6473597d706e 3288 * channels can be selected to generate multiple triggers in one PWM period.
bogdanm 82:6473597d706e 3289 * Channels 6 and 7 are not used to generate channel triggers.
bogdanm 82:6473597d706e 3290 */
bogdanm 82:6473597d706e 3291 typedef union _hw_ftm_exttrig
bogdanm 82:6473597d706e 3292 {
bogdanm 82:6473597d706e 3293 uint32_t U;
bogdanm 82:6473597d706e 3294 struct _hw_ftm_exttrig_bitfields
bogdanm 82:6473597d706e 3295 {
bogdanm 82:6473597d706e 3296 uint32_t CH2TRIG : 1; //!< [0] Channel 2 Trigger Enable
bogdanm 82:6473597d706e 3297 uint32_t CH3TRIG : 1; //!< [1] Channel 3 Trigger Enable
bogdanm 82:6473597d706e 3298 uint32_t CH4TRIG : 1; //!< [2] Channel 4 Trigger Enable
bogdanm 82:6473597d706e 3299 uint32_t CH5TRIG : 1; //!< [3] Channel 5 Trigger Enable
bogdanm 82:6473597d706e 3300 uint32_t CH0TRIG : 1; //!< [4] Channel 0 Trigger Enable
bogdanm 82:6473597d706e 3301 uint32_t CH1TRIG : 1; //!< [5] Channel 1 Trigger Enable
bogdanm 82:6473597d706e 3302 uint32_t INITTRIGEN : 1; //!< [6] Initialization Trigger Enable
bogdanm 82:6473597d706e 3303 uint32_t TRIGF : 1; //!< [7] Channel Trigger Flag
bogdanm 82:6473597d706e 3304 uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm 82:6473597d706e 3305 } B;
bogdanm 82:6473597d706e 3306 } hw_ftm_exttrig_t;
bogdanm 82:6473597d706e 3307 #endif
bogdanm 82:6473597d706e 3308
bogdanm 82:6473597d706e 3309 /*!
bogdanm 82:6473597d706e 3310 * @name Constants and macros for entire FTM_EXTTRIG register
bogdanm 82:6473597d706e 3311 */
bogdanm 82:6473597d706e 3312 //@{
bogdanm 82:6473597d706e 3313 #define HW_FTM_EXTTRIG_ADDR(x) (REGS_FTM_BASE(x) + 0x6CU)
bogdanm 82:6473597d706e 3314
bogdanm 82:6473597d706e 3315 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3316 #define HW_FTM_EXTTRIG(x) (*(__IO hw_ftm_exttrig_t *) HW_FTM_EXTTRIG_ADDR(x))
bogdanm 82:6473597d706e 3317 #define HW_FTM_EXTTRIG_RD(x) (HW_FTM_EXTTRIG(x).U)
bogdanm 82:6473597d706e 3318 #define HW_FTM_EXTTRIG_WR(x, v) (HW_FTM_EXTTRIG(x).U = (v))
bogdanm 82:6473597d706e 3319 #define HW_FTM_EXTTRIG_SET(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) | (v)))
bogdanm 82:6473597d706e 3320 #define HW_FTM_EXTTRIG_CLR(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) & ~(v)))
bogdanm 82:6473597d706e 3321 #define HW_FTM_EXTTRIG_TOG(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) ^ (v)))
bogdanm 82:6473597d706e 3322 #endif
bogdanm 82:6473597d706e 3323 //@}
bogdanm 82:6473597d706e 3324
bogdanm 82:6473597d706e 3325 /*
bogdanm 82:6473597d706e 3326 * Constants & macros for individual FTM_EXTTRIG bitfields
bogdanm 82:6473597d706e 3327 */
bogdanm 82:6473597d706e 3328
bogdanm 82:6473597d706e 3329 /*!
bogdanm 82:6473597d706e 3330 * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
bogdanm 82:6473597d706e 3331 *
bogdanm 82:6473597d706e 3332 * Enables the generation of the channel trigger when the FTM counter is equal
bogdanm 82:6473597d706e 3333 * to the CnV register.
bogdanm 82:6473597d706e 3334 *
bogdanm 82:6473597d706e 3335 * Values:
bogdanm 82:6473597d706e 3336 * - 0 - The generation of the channel trigger is disabled.
bogdanm 82:6473597d706e 3337 * - 1 - The generation of the channel trigger is enabled.
bogdanm 82:6473597d706e 3338 */
bogdanm 82:6473597d706e 3339 //@{
bogdanm 82:6473597d706e 3340 #define BP_FTM_EXTTRIG_CH2TRIG (0U) //!< Bit position for FTM_EXTTRIG_CH2TRIG.
bogdanm 82:6473597d706e 3341 #define BM_FTM_EXTTRIG_CH2TRIG (0x00000001U) //!< Bit mask for FTM_EXTTRIG_CH2TRIG.
bogdanm 82:6473597d706e 3342 #define BS_FTM_EXTTRIG_CH2TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH2TRIG.
bogdanm 82:6473597d706e 3343
bogdanm 82:6473597d706e 3344 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3345 //! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field.
bogdanm 82:6473597d706e 3346 #define BR_FTM_EXTTRIG_CH2TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG))
bogdanm 82:6473597d706e 3347 #endif
bogdanm 82:6473597d706e 3348
bogdanm 82:6473597d706e 3349 //! @brief Format value for bitfield FTM_EXTTRIG_CH2TRIG.
bogdanm 82:6473597d706e 3350 #define BF_FTM_EXTTRIG_CH2TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH2TRIG), uint32_t) & BM_FTM_EXTTRIG_CH2TRIG)
bogdanm 82:6473597d706e 3351
bogdanm 82:6473597d706e 3352 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3353 //! @brief Set the CH2TRIG field to a new value.
bogdanm 82:6473597d706e 3354 #define BW_FTM_EXTTRIG_CH2TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG) = (v))
bogdanm 82:6473597d706e 3355 #endif
bogdanm 82:6473597d706e 3356 //@}
bogdanm 82:6473597d706e 3357
bogdanm 82:6473597d706e 3358 /*!
bogdanm 82:6473597d706e 3359 * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
bogdanm 82:6473597d706e 3360 *
bogdanm 82:6473597d706e 3361 * Enables the generation of the channel trigger when the FTM counter is equal
bogdanm 82:6473597d706e 3362 * to the CnV register.
bogdanm 82:6473597d706e 3363 *
bogdanm 82:6473597d706e 3364 * Values:
bogdanm 82:6473597d706e 3365 * - 0 - The generation of the channel trigger is disabled.
bogdanm 82:6473597d706e 3366 * - 1 - The generation of the channel trigger is enabled.
bogdanm 82:6473597d706e 3367 */
bogdanm 82:6473597d706e 3368 //@{
bogdanm 82:6473597d706e 3369 #define BP_FTM_EXTTRIG_CH3TRIG (1U) //!< Bit position for FTM_EXTTRIG_CH3TRIG.
bogdanm 82:6473597d706e 3370 #define BM_FTM_EXTTRIG_CH3TRIG (0x00000002U) //!< Bit mask for FTM_EXTTRIG_CH3TRIG.
bogdanm 82:6473597d706e 3371 #define BS_FTM_EXTTRIG_CH3TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH3TRIG.
bogdanm 82:6473597d706e 3372
bogdanm 82:6473597d706e 3373 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3374 //! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field.
bogdanm 82:6473597d706e 3375 #define BR_FTM_EXTTRIG_CH3TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG))
bogdanm 82:6473597d706e 3376 #endif
bogdanm 82:6473597d706e 3377
bogdanm 82:6473597d706e 3378 //! @brief Format value for bitfield FTM_EXTTRIG_CH3TRIG.
bogdanm 82:6473597d706e 3379 #define BF_FTM_EXTTRIG_CH3TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH3TRIG), uint32_t) & BM_FTM_EXTTRIG_CH3TRIG)
bogdanm 82:6473597d706e 3380
bogdanm 82:6473597d706e 3381 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3382 //! @brief Set the CH3TRIG field to a new value.
bogdanm 82:6473597d706e 3383 #define BW_FTM_EXTTRIG_CH3TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG) = (v))
bogdanm 82:6473597d706e 3384 #endif
bogdanm 82:6473597d706e 3385 //@}
bogdanm 82:6473597d706e 3386
bogdanm 82:6473597d706e 3387 /*!
bogdanm 82:6473597d706e 3388 * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
bogdanm 82:6473597d706e 3389 *
bogdanm 82:6473597d706e 3390 * Enables the generation of the channel trigger when the FTM counter is equal
bogdanm 82:6473597d706e 3391 * to the CnV register.
bogdanm 82:6473597d706e 3392 *
bogdanm 82:6473597d706e 3393 * Values:
bogdanm 82:6473597d706e 3394 * - 0 - The generation of the channel trigger is disabled.
bogdanm 82:6473597d706e 3395 * - 1 - The generation of the channel trigger is enabled.
bogdanm 82:6473597d706e 3396 */
bogdanm 82:6473597d706e 3397 //@{
bogdanm 82:6473597d706e 3398 #define BP_FTM_EXTTRIG_CH4TRIG (2U) //!< Bit position for FTM_EXTTRIG_CH4TRIG.
bogdanm 82:6473597d706e 3399 #define BM_FTM_EXTTRIG_CH4TRIG (0x00000004U) //!< Bit mask for FTM_EXTTRIG_CH4TRIG.
bogdanm 82:6473597d706e 3400 #define BS_FTM_EXTTRIG_CH4TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH4TRIG.
bogdanm 82:6473597d706e 3401
bogdanm 82:6473597d706e 3402 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3403 //! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field.
bogdanm 82:6473597d706e 3404 #define BR_FTM_EXTTRIG_CH4TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG))
bogdanm 82:6473597d706e 3405 #endif
bogdanm 82:6473597d706e 3406
bogdanm 82:6473597d706e 3407 //! @brief Format value for bitfield FTM_EXTTRIG_CH4TRIG.
bogdanm 82:6473597d706e 3408 #define BF_FTM_EXTTRIG_CH4TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH4TRIG), uint32_t) & BM_FTM_EXTTRIG_CH4TRIG)
bogdanm 82:6473597d706e 3409
bogdanm 82:6473597d706e 3410 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3411 //! @brief Set the CH4TRIG field to a new value.
bogdanm 82:6473597d706e 3412 #define BW_FTM_EXTTRIG_CH4TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG) = (v))
bogdanm 82:6473597d706e 3413 #endif
bogdanm 82:6473597d706e 3414 //@}
bogdanm 82:6473597d706e 3415
bogdanm 82:6473597d706e 3416 /*!
bogdanm 82:6473597d706e 3417 * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
bogdanm 82:6473597d706e 3418 *
bogdanm 82:6473597d706e 3419 * Enables the generation of the channel trigger when the FTM counter is equal
bogdanm 82:6473597d706e 3420 * to the CnV register.
bogdanm 82:6473597d706e 3421 *
bogdanm 82:6473597d706e 3422 * Values:
bogdanm 82:6473597d706e 3423 * - 0 - The generation of the channel trigger is disabled.
bogdanm 82:6473597d706e 3424 * - 1 - The generation of the channel trigger is enabled.
bogdanm 82:6473597d706e 3425 */
bogdanm 82:6473597d706e 3426 //@{
bogdanm 82:6473597d706e 3427 #define BP_FTM_EXTTRIG_CH5TRIG (3U) //!< Bit position for FTM_EXTTRIG_CH5TRIG.
bogdanm 82:6473597d706e 3428 #define BM_FTM_EXTTRIG_CH5TRIG (0x00000008U) //!< Bit mask for FTM_EXTTRIG_CH5TRIG.
bogdanm 82:6473597d706e 3429 #define BS_FTM_EXTTRIG_CH5TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH5TRIG.
bogdanm 82:6473597d706e 3430
bogdanm 82:6473597d706e 3431 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3432 //! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field.
bogdanm 82:6473597d706e 3433 #define BR_FTM_EXTTRIG_CH5TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG))
bogdanm 82:6473597d706e 3434 #endif
bogdanm 82:6473597d706e 3435
bogdanm 82:6473597d706e 3436 //! @brief Format value for bitfield FTM_EXTTRIG_CH5TRIG.
bogdanm 82:6473597d706e 3437 #define BF_FTM_EXTTRIG_CH5TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH5TRIG), uint32_t) & BM_FTM_EXTTRIG_CH5TRIG)
bogdanm 82:6473597d706e 3438
bogdanm 82:6473597d706e 3439 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3440 //! @brief Set the CH5TRIG field to a new value.
bogdanm 82:6473597d706e 3441 #define BW_FTM_EXTTRIG_CH5TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG) = (v))
bogdanm 82:6473597d706e 3442 #endif
bogdanm 82:6473597d706e 3443 //@}
bogdanm 82:6473597d706e 3444
bogdanm 82:6473597d706e 3445 /*!
bogdanm 82:6473597d706e 3446 * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
bogdanm 82:6473597d706e 3447 *
bogdanm 82:6473597d706e 3448 * Enables the generation of the channel trigger when the FTM counter is equal
bogdanm 82:6473597d706e 3449 * to the CnV register.
bogdanm 82:6473597d706e 3450 *
bogdanm 82:6473597d706e 3451 * Values:
bogdanm 82:6473597d706e 3452 * - 0 - The generation of the channel trigger is disabled.
bogdanm 82:6473597d706e 3453 * - 1 - The generation of the channel trigger is enabled.
bogdanm 82:6473597d706e 3454 */
bogdanm 82:6473597d706e 3455 //@{
bogdanm 82:6473597d706e 3456 #define BP_FTM_EXTTRIG_CH0TRIG (4U) //!< Bit position for FTM_EXTTRIG_CH0TRIG.
bogdanm 82:6473597d706e 3457 #define BM_FTM_EXTTRIG_CH0TRIG (0x00000010U) //!< Bit mask for FTM_EXTTRIG_CH0TRIG.
bogdanm 82:6473597d706e 3458 #define BS_FTM_EXTTRIG_CH0TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH0TRIG.
bogdanm 82:6473597d706e 3459
bogdanm 82:6473597d706e 3460 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3461 //! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field.
bogdanm 82:6473597d706e 3462 #define BR_FTM_EXTTRIG_CH0TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG))
bogdanm 82:6473597d706e 3463 #endif
bogdanm 82:6473597d706e 3464
bogdanm 82:6473597d706e 3465 //! @brief Format value for bitfield FTM_EXTTRIG_CH0TRIG.
bogdanm 82:6473597d706e 3466 #define BF_FTM_EXTTRIG_CH0TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH0TRIG), uint32_t) & BM_FTM_EXTTRIG_CH0TRIG)
bogdanm 82:6473597d706e 3467
bogdanm 82:6473597d706e 3468 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3469 //! @brief Set the CH0TRIG field to a new value.
bogdanm 82:6473597d706e 3470 #define BW_FTM_EXTTRIG_CH0TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG) = (v))
bogdanm 82:6473597d706e 3471 #endif
bogdanm 82:6473597d706e 3472 //@}
bogdanm 82:6473597d706e 3473
bogdanm 82:6473597d706e 3474 /*!
bogdanm 82:6473597d706e 3475 * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
bogdanm 82:6473597d706e 3476 *
bogdanm 82:6473597d706e 3477 * Enables the generation of the channel trigger when the FTM counter is equal
bogdanm 82:6473597d706e 3478 * to the CnV register.
bogdanm 82:6473597d706e 3479 *
bogdanm 82:6473597d706e 3480 * Values:
bogdanm 82:6473597d706e 3481 * - 0 - The generation of the channel trigger is disabled.
bogdanm 82:6473597d706e 3482 * - 1 - The generation of the channel trigger is enabled.
bogdanm 82:6473597d706e 3483 */
bogdanm 82:6473597d706e 3484 //@{
bogdanm 82:6473597d706e 3485 #define BP_FTM_EXTTRIG_CH1TRIG (5U) //!< Bit position for FTM_EXTTRIG_CH1TRIG.
bogdanm 82:6473597d706e 3486 #define BM_FTM_EXTTRIG_CH1TRIG (0x00000020U) //!< Bit mask for FTM_EXTTRIG_CH1TRIG.
bogdanm 82:6473597d706e 3487 #define BS_FTM_EXTTRIG_CH1TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH1TRIG.
bogdanm 82:6473597d706e 3488
bogdanm 82:6473597d706e 3489 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3490 //! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field.
bogdanm 82:6473597d706e 3491 #define BR_FTM_EXTTRIG_CH1TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG))
bogdanm 82:6473597d706e 3492 #endif
bogdanm 82:6473597d706e 3493
bogdanm 82:6473597d706e 3494 //! @brief Format value for bitfield FTM_EXTTRIG_CH1TRIG.
bogdanm 82:6473597d706e 3495 #define BF_FTM_EXTTRIG_CH1TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH1TRIG), uint32_t) & BM_FTM_EXTTRIG_CH1TRIG)
bogdanm 82:6473597d706e 3496
bogdanm 82:6473597d706e 3497 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3498 //! @brief Set the CH1TRIG field to a new value.
bogdanm 82:6473597d706e 3499 #define BW_FTM_EXTTRIG_CH1TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG) = (v))
bogdanm 82:6473597d706e 3500 #endif
bogdanm 82:6473597d706e 3501 //@}
bogdanm 82:6473597d706e 3502
bogdanm 82:6473597d706e 3503 /*!
bogdanm 82:6473597d706e 3504 * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
bogdanm 82:6473597d706e 3505 *
bogdanm 82:6473597d706e 3506 * Enables the generation of the trigger when the FTM counter is equal to the
bogdanm 82:6473597d706e 3507 * CNTIN register.
bogdanm 82:6473597d706e 3508 *
bogdanm 82:6473597d706e 3509 * Values:
bogdanm 82:6473597d706e 3510 * - 0 - The generation of initialization trigger is disabled.
bogdanm 82:6473597d706e 3511 * - 1 - The generation of initialization trigger is enabled.
bogdanm 82:6473597d706e 3512 */
bogdanm 82:6473597d706e 3513 //@{
bogdanm 82:6473597d706e 3514 #define BP_FTM_EXTTRIG_INITTRIGEN (6U) //!< Bit position for FTM_EXTTRIG_INITTRIGEN.
bogdanm 82:6473597d706e 3515 #define BM_FTM_EXTTRIG_INITTRIGEN (0x00000040U) //!< Bit mask for FTM_EXTTRIG_INITTRIGEN.
bogdanm 82:6473597d706e 3516 #define BS_FTM_EXTTRIG_INITTRIGEN (1U) //!< Bit field size in bits for FTM_EXTTRIG_INITTRIGEN.
bogdanm 82:6473597d706e 3517
bogdanm 82:6473597d706e 3518 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3519 //! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field.
bogdanm 82:6473597d706e 3520 #define BR_FTM_EXTTRIG_INITTRIGEN(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN))
bogdanm 82:6473597d706e 3521 #endif
bogdanm 82:6473597d706e 3522
bogdanm 82:6473597d706e 3523 //! @brief Format value for bitfield FTM_EXTTRIG_INITTRIGEN.
bogdanm 82:6473597d706e 3524 #define BF_FTM_EXTTRIG_INITTRIGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_INITTRIGEN), uint32_t) & BM_FTM_EXTTRIG_INITTRIGEN)
bogdanm 82:6473597d706e 3525
bogdanm 82:6473597d706e 3526 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3527 //! @brief Set the INITTRIGEN field to a new value.
bogdanm 82:6473597d706e 3528 #define BW_FTM_EXTTRIG_INITTRIGEN(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN) = (v))
bogdanm 82:6473597d706e 3529 #endif
bogdanm 82:6473597d706e 3530 //@}
bogdanm 82:6473597d706e 3531
bogdanm 82:6473597d706e 3532 /*!
bogdanm 82:6473597d706e 3533 * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
bogdanm 82:6473597d706e 3534 *
bogdanm 82:6473597d706e 3535 * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
bogdanm 82:6473597d706e 3536 * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
bogdanm 82:6473597d706e 3537 * has no effect. If another channel trigger is generated before the clearing
bogdanm 82:6473597d706e 3538 * sequence is completed, the sequence is reset so TRIGF remains set after the clear
bogdanm 82:6473597d706e 3539 * sequence is completed for the earlier TRIGF.
bogdanm 82:6473597d706e 3540 *
bogdanm 82:6473597d706e 3541 * Values:
bogdanm 82:6473597d706e 3542 * - 0 - No channel trigger was generated.
bogdanm 82:6473597d706e 3543 * - 1 - A channel trigger was generated.
bogdanm 82:6473597d706e 3544 */
bogdanm 82:6473597d706e 3545 //@{
bogdanm 82:6473597d706e 3546 #define BP_FTM_EXTTRIG_TRIGF (7U) //!< Bit position for FTM_EXTTRIG_TRIGF.
bogdanm 82:6473597d706e 3547 #define BM_FTM_EXTTRIG_TRIGF (0x00000080U) //!< Bit mask for FTM_EXTTRIG_TRIGF.
bogdanm 82:6473597d706e 3548 #define BS_FTM_EXTTRIG_TRIGF (1U) //!< Bit field size in bits for FTM_EXTTRIG_TRIGF.
bogdanm 82:6473597d706e 3549
bogdanm 82:6473597d706e 3550 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3551 //! @brief Read current value of the FTM_EXTTRIG_TRIGF field.
bogdanm 82:6473597d706e 3552 #define BR_FTM_EXTTRIG_TRIGF(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF))
bogdanm 82:6473597d706e 3553 #endif
bogdanm 82:6473597d706e 3554 //@}
bogdanm 82:6473597d706e 3555
bogdanm 82:6473597d706e 3556 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3557 // HW_FTM_POL - Channels Polarity
bogdanm 82:6473597d706e 3558 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3559
bogdanm 82:6473597d706e 3560 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3561 /*!
bogdanm 82:6473597d706e 3562 * @brief HW_FTM_POL - Channels Polarity (RW)
bogdanm 82:6473597d706e 3563 *
bogdanm 82:6473597d706e 3564 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 3565 *
bogdanm 82:6473597d706e 3566 * This register defines the output polarity of the FTM channels. The safe value
bogdanm 82:6473597d706e 3567 * that is driven in a channel output when the fault control is enabled and a
bogdanm 82:6473597d706e 3568 * fault condition is detected is the inactive state of the channel. That is, the
bogdanm 82:6473597d706e 3569 * safe value of a channel is the value of its POL bit.
bogdanm 82:6473597d706e 3570 */
bogdanm 82:6473597d706e 3571 typedef union _hw_ftm_pol
bogdanm 82:6473597d706e 3572 {
bogdanm 82:6473597d706e 3573 uint32_t U;
bogdanm 82:6473597d706e 3574 struct _hw_ftm_pol_bitfields
bogdanm 82:6473597d706e 3575 {
bogdanm 82:6473597d706e 3576 uint32_t POL0 : 1; //!< [0] Channel 0 Polarity
bogdanm 82:6473597d706e 3577 uint32_t POL1 : 1; //!< [1] Channel 1 Polarity
bogdanm 82:6473597d706e 3578 uint32_t POL2 : 1; //!< [2] Channel 2 Polarity
bogdanm 82:6473597d706e 3579 uint32_t POL3 : 1; //!< [3] Channel 3 Polarity
bogdanm 82:6473597d706e 3580 uint32_t POL4 : 1; //!< [4] Channel 4 Polarity
bogdanm 82:6473597d706e 3581 uint32_t POL5 : 1; //!< [5] Channel 5 Polarity
bogdanm 82:6473597d706e 3582 uint32_t POL6 : 1; //!< [6] Channel 6 Polarity
bogdanm 82:6473597d706e 3583 uint32_t POL7 : 1; //!< [7] Channel 7 Polarity
bogdanm 82:6473597d706e 3584 uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm 82:6473597d706e 3585 } B;
bogdanm 82:6473597d706e 3586 } hw_ftm_pol_t;
bogdanm 82:6473597d706e 3587 #endif
bogdanm 82:6473597d706e 3588
bogdanm 82:6473597d706e 3589 /*!
bogdanm 82:6473597d706e 3590 * @name Constants and macros for entire FTM_POL register
bogdanm 82:6473597d706e 3591 */
bogdanm 82:6473597d706e 3592 //@{
bogdanm 82:6473597d706e 3593 #define HW_FTM_POL_ADDR(x) (REGS_FTM_BASE(x) + 0x70U)
bogdanm 82:6473597d706e 3594
bogdanm 82:6473597d706e 3595 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3596 #define HW_FTM_POL(x) (*(__IO hw_ftm_pol_t *) HW_FTM_POL_ADDR(x))
bogdanm 82:6473597d706e 3597 #define HW_FTM_POL_RD(x) (HW_FTM_POL(x).U)
bogdanm 82:6473597d706e 3598 #define HW_FTM_POL_WR(x, v) (HW_FTM_POL(x).U = (v))
bogdanm 82:6473597d706e 3599 #define HW_FTM_POL_SET(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) | (v)))
bogdanm 82:6473597d706e 3600 #define HW_FTM_POL_CLR(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) & ~(v)))
bogdanm 82:6473597d706e 3601 #define HW_FTM_POL_TOG(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) ^ (v)))
bogdanm 82:6473597d706e 3602 #endif
bogdanm 82:6473597d706e 3603 //@}
bogdanm 82:6473597d706e 3604
bogdanm 82:6473597d706e 3605 /*
bogdanm 82:6473597d706e 3606 * Constants & macros for individual FTM_POL bitfields
bogdanm 82:6473597d706e 3607 */
bogdanm 82:6473597d706e 3608
bogdanm 82:6473597d706e 3609 /*!
bogdanm 82:6473597d706e 3610 * @name Register FTM_POL, field POL0[0] (RW)
bogdanm 82:6473597d706e 3611 *
bogdanm 82:6473597d706e 3612 * Defines the polarity of the channel output. This field is write protected. It
bogdanm 82:6473597d706e 3613 * can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 3614 *
bogdanm 82:6473597d706e 3615 * Values:
bogdanm 82:6473597d706e 3616 * - 0 - The channel polarity is active high.
bogdanm 82:6473597d706e 3617 * - 1 - The channel polarity is active low.
bogdanm 82:6473597d706e 3618 */
bogdanm 82:6473597d706e 3619 //@{
bogdanm 82:6473597d706e 3620 #define BP_FTM_POL_POL0 (0U) //!< Bit position for FTM_POL_POL0.
bogdanm 82:6473597d706e 3621 #define BM_FTM_POL_POL0 (0x00000001U) //!< Bit mask for FTM_POL_POL0.
bogdanm 82:6473597d706e 3622 #define BS_FTM_POL_POL0 (1U) //!< Bit field size in bits for FTM_POL_POL0.
bogdanm 82:6473597d706e 3623
bogdanm 82:6473597d706e 3624 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3625 //! @brief Read current value of the FTM_POL_POL0 field.
bogdanm 82:6473597d706e 3626 #define BR_FTM_POL_POL0(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0))
bogdanm 82:6473597d706e 3627 #endif
bogdanm 82:6473597d706e 3628
bogdanm 82:6473597d706e 3629 //! @brief Format value for bitfield FTM_POL_POL0.
bogdanm 82:6473597d706e 3630 #define BF_FTM_POL_POL0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL0), uint32_t) & BM_FTM_POL_POL0)
bogdanm 82:6473597d706e 3631
bogdanm 82:6473597d706e 3632 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3633 //! @brief Set the POL0 field to a new value.
bogdanm 82:6473597d706e 3634 #define BW_FTM_POL_POL0(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0) = (v))
bogdanm 82:6473597d706e 3635 #endif
bogdanm 82:6473597d706e 3636 //@}
bogdanm 82:6473597d706e 3637
bogdanm 82:6473597d706e 3638 /*!
bogdanm 82:6473597d706e 3639 * @name Register FTM_POL, field POL1[1] (RW)
bogdanm 82:6473597d706e 3640 *
bogdanm 82:6473597d706e 3641 * Defines the polarity of the channel output. This field is write protected. It
bogdanm 82:6473597d706e 3642 * can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 3643 *
bogdanm 82:6473597d706e 3644 * Values:
bogdanm 82:6473597d706e 3645 * - 0 - The channel polarity is active high.
bogdanm 82:6473597d706e 3646 * - 1 - The channel polarity is active low.
bogdanm 82:6473597d706e 3647 */
bogdanm 82:6473597d706e 3648 //@{
bogdanm 82:6473597d706e 3649 #define BP_FTM_POL_POL1 (1U) //!< Bit position for FTM_POL_POL1.
bogdanm 82:6473597d706e 3650 #define BM_FTM_POL_POL1 (0x00000002U) //!< Bit mask for FTM_POL_POL1.
bogdanm 82:6473597d706e 3651 #define BS_FTM_POL_POL1 (1U) //!< Bit field size in bits for FTM_POL_POL1.
bogdanm 82:6473597d706e 3652
bogdanm 82:6473597d706e 3653 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3654 //! @brief Read current value of the FTM_POL_POL1 field.
bogdanm 82:6473597d706e 3655 #define BR_FTM_POL_POL1(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1))
bogdanm 82:6473597d706e 3656 #endif
bogdanm 82:6473597d706e 3657
bogdanm 82:6473597d706e 3658 //! @brief Format value for bitfield FTM_POL_POL1.
bogdanm 82:6473597d706e 3659 #define BF_FTM_POL_POL1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL1), uint32_t) & BM_FTM_POL_POL1)
bogdanm 82:6473597d706e 3660
bogdanm 82:6473597d706e 3661 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3662 //! @brief Set the POL1 field to a new value.
bogdanm 82:6473597d706e 3663 #define BW_FTM_POL_POL1(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1) = (v))
bogdanm 82:6473597d706e 3664 #endif
bogdanm 82:6473597d706e 3665 //@}
bogdanm 82:6473597d706e 3666
bogdanm 82:6473597d706e 3667 /*!
bogdanm 82:6473597d706e 3668 * @name Register FTM_POL, field POL2[2] (RW)
bogdanm 82:6473597d706e 3669 *
bogdanm 82:6473597d706e 3670 * Defines the polarity of the channel output. This field is write protected. It
bogdanm 82:6473597d706e 3671 * can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 3672 *
bogdanm 82:6473597d706e 3673 * Values:
bogdanm 82:6473597d706e 3674 * - 0 - The channel polarity is active high.
bogdanm 82:6473597d706e 3675 * - 1 - The channel polarity is active low.
bogdanm 82:6473597d706e 3676 */
bogdanm 82:6473597d706e 3677 //@{
bogdanm 82:6473597d706e 3678 #define BP_FTM_POL_POL2 (2U) //!< Bit position for FTM_POL_POL2.
bogdanm 82:6473597d706e 3679 #define BM_FTM_POL_POL2 (0x00000004U) //!< Bit mask for FTM_POL_POL2.
bogdanm 82:6473597d706e 3680 #define BS_FTM_POL_POL2 (1U) //!< Bit field size in bits for FTM_POL_POL2.
bogdanm 82:6473597d706e 3681
bogdanm 82:6473597d706e 3682 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3683 //! @brief Read current value of the FTM_POL_POL2 field.
bogdanm 82:6473597d706e 3684 #define BR_FTM_POL_POL2(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2))
bogdanm 82:6473597d706e 3685 #endif
bogdanm 82:6473597d706e 3686
bogdanm 82:6473597d706e 3687 //! @brief Format value for bitfield FTM_POL_POL2.
bogdanm 82:6473597d706e 3688 #define BF_FTM_POL_POL2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL2), uint32_t) & BM_FTM_POL_POL2)
bogdanm 82:6473597d706e 3689
bogdanm 82:6473597d706e 3690 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3691 //! @brief Set the POL2 field to a new value.
bogdanm 82:6473597d706e 3692 #define BW_FTM_POL_POL2(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2) = (v))
bogdanm 82:6473597d706e 3693 #endif
bogdanm 82:6473597d706e 3694 //@}
bogdanm 82:6473597d706e 3695
bogdanm 82:6473597d706e 3696 /*!
bogdanm 82:6473597d706e 3697 * @name Register FTM_POL, field POL3[3] (RW)
bogdanm 82:6473597d706e 3698 *
bogdanm 82:6473597d706e 3699 * Defines the polarity of the channel output. This field is write protected. It
bogdanm 82:6473597d706e 3700 * can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 3701 *
bogdanm 82:6473597d706e 3702 * Values:
bogdanm 82:6473597d706e 3703 * - 0 - The channel polarity is active high.
bogdanm 82:6473597d706e 3704 * - 1 - The channel polarity is active low.
bogdanm 82:6473597d706e 3705 */
bogdanm 82:6473597d706e 3706 //@{
bogdanm 82:6473597d706e 3707 #define BP_FTM_POL_POL3 (3U) //!< Bit position for FTM_POL_POL3.
bogdanm 82:6473597d706e 3708 #define BM_FTM_POL_POL3 (0x00000008U) //!< Bit mask for FTM_POL_POL3.
bogdanm 82:6473597d706e 3709 #define BS_FTM_POL_POL3 (1U) //!< Bit field size in bits for FTM_POL_POL3.
bogdanm 82:6473597d706e 3710
bogdanm 82:6473597d706e 3711 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3712 //! @brief Read current value of the FTM_POL_POL3 field.
bogdanm 82:6473597d706e 3713 #define BR_FTM_POL_POL3(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3))
bogdanm 82:6473597d706e 3714 #endif
bogdanm 82:6473597d706e 3715
bogdanm 82:6473597d706e 3716 //! @brief Format value for bitfield FTM_POL_POL3.
bogdanm 82:6473597d706e 3717 #define BF_FTM_POL_POL3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL3), uint32_t) & BM_FTM_POL_POL3)
bogdanm 82:6473597d706e 3718
bogdanm 82:6473597d706e 3719 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3720 //! @brief Set the POL3 field to a new value.
bogdanm 82:6473597d706e 3721 #define BW_FTM_POL_POL3(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3) = (v))
bogdanm 82:6473597d706e 3722 #endif
bogdanm 82:6473597d706e 3723 //@}
bogdanm 82:6473597d706e 3724
bogdanm 82:6473597d706e 3725 /*!
bogdanm 82:6473597d706e 3726 * @name Register FTM_POL, field POL4[4] (RW)
bogdanm 82:6473597d706e 3727 *
bogdanm 82:6473597d706e 3728 * Defines the polarity of the channel output. This field is write protected. It
bogdanm 82:6473597d706e 3729 * can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 3730 *
bogdanm 82:6473597d706e 3731 * Values:
bogdanm 82:6473597d706e 3732 * - 0 - The channel polarity is active high.
bogdanm 82:6473597d706e 3733 * - 1 - The channel polarity is active low.
bogdanm 82:6473597d706e 3734 */
bogdanm 82:6473597d706e 3735 //@{
bogdanm 82:6473597d706e 3736 #define BP_FTM_POL_POL4 (4U) //!< Bit position for FTM_POL_POL4.
bogdanm 82:6473597d706e 3737 #define BM_FTM_POL_POL4 (0x00000010U) //!< Bit mask for FTM_POL_POL4.
bogdanm 82:6473597d706e 3738 #define BS_FTM_POL_POL4 (1U) //!< Bit field size in bits for FTM_POL_POL4.
bogdanm 82:6473597d706e 3739
bogdanm 82:6473597d706e 3740 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3741 //! @brief Read current value of the FTM_POL_POL4 field.
bogdanm 82:6473597d706e 3742 #define BR_FTM_POL_POL4(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4))
bogdanm 82:6473597d706e 3743 #endif
bogdanm 82:6473597d706e 3744
bogdanm 82:6473597d706e 3745 //! @brief Format value for bitfield FTM_POL_POL4.
bogdanm 82:6473597d706e 3746 #define BF_FTM_POL_POL4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL4), uint32_t) & BM_FTM_POL_POL4)
bogdanm 82:6473597d706e 3747
bogdanm 82:6473597d706e 3748 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3749 //! @brief Set the POL4 field to a new value.
bogdanm 82:6473597d706e 3750 #define BW_FTM_POL_POL4(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4) = (v))
bogdanm 82:6473597d706e 3751 #endif
bogdanm 82:6473597d706e 3752 //@}
bogdanm 82:6473597d706e 3753
bogdanm 82:6473597d706e 3754 /*!
bogdanm 82:6473597d706e 3755 * @name Register FTM_POL, field POL5[5] (RW)
bogdanm 82:6473597d706e 3756 *
bogdanm 82:6473597d706e 3757 * Defines the polarity of the channel output. This field is write protected. It
bogdanm 82:6473597d706e 3758 * can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 3759 *
bogdanm 82:6473597d706e 3760 * Values:
bogdanm 82:6473597d706e 3761 * - 0 - The channel polarity is active high.
bogdanm 82:6473597d706e 3762 * - 1 - The channel polarity is active low.
bogdanm 82:6473597d706e 3763 */
bogdanm 82:6473597d706e 3764 //@{
bogdanm 82:6473597d706e 3765 #define BP_FTM_POL_POL5 (5U) //!< Bit position for FTM_POL_POL5.
bogdanm 82:6473597d706e 3766 #define BM_FTM_POL_POL5 (0x00000020U) //!< Bit mask for FTM_POL_POL5.
bogdanm 82:6473597d706e 3767 #define BS_FTM_POL_POL5 (1U) //!< Bit field size in bits for FTM_POL_POL5.
bogdanm 82:6473597d706e 3768
bogdanm 82:6473597d706e 3769 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3770 //! @brief Read current value of the FTM_POL_POL5 field.
bogdanm 82:6473597d706e 3771 #define BR_FTM_POL_POL5(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5))
bogdanm 82:6473597d706e 3772 #endif
bogdanm 82:6473597d706e 3773
bogdanm 82:6473597d706e 3774 //! @brief Format value for bitfield FTM_POL_POL5.
bogdanm 82:6473597d706e 3775 #define BF_FTM_POL_POL5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL5), uint32_t) & BM_FTM_POL_POL5)
bogdanm 82:6473597d706e 3776
bogdanm 82:6473597d706e 3777 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3778 //! @brief Set the POL5 field to a new value.
bogdanm 82:6473597d706e 3779 #define BW_FTM_POL_POL5(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5) = (v))
bogdanm 82:6473597d706e 3780 #endif
bogdanm 82:6473597d706e 3781 //@}
bogdanm 82:6473597d706e 3782
bogdanm 82:6473597d706e 3783 /*!
bogdanm 82:6473597d706e 3784 * @name Register FTM_POL, field POL6[6] (RW)
bogdanm 82:6473597d706e 3785 *
bogdanm 82:6473597d706e 3786 * Defines the polarity of the channel output. This field is write protected. It
bogdanm 82:6473597d706e 3787 * can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 3788 *
bogdanm 82:6473597d706e 3789 * Values:
bogdanm 82:6473597d706e 3790 * - 0 - The channel polarity is active high.
bogdanm 82:6473597d706e 3791 * - 1 - The channel polarity is active low.
bogdanm 82:6473597d706e 3792 */
bogdanm 82:6473597d706e 3793 //@{
bogdanm 82:6473597d706e 3794 #define BP_FTM_POL_POL6 (6U) //!< Bit position for FTM_POL_POL6.
bogdanm 82:6473597d706e 3795 #define BM_FTM_POL_POL6 (0x00000040U) //!< Bit mask for FTM_POL_POL6.
bogdanm 82:6473597d706e 3796 #define BS_FTM_POL_POL6 (1U) //!< Bit field size in bits for FTM_POL_POL6.
bogdanm 82:6473597d706e 3797
bogdanm 82:6473597d706e 3798 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3799 //! @brief Read current value of the FTM_POL_POL6 field.
bogdanm 82:6473597d706e 3800 #define BR_FTM_POL_POL6(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6))
bogdanm 82:6473597d706e 3801 #endif
bogdanm 82:6473597d706e 3802
bogdanm 82:6473597d706e 3803 //! @brief Format value for bitfield FTM_POL_POL6.
bogdanm 82:6473597d706e 3804 #define BF_FTM_POL_POL6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL6), uint32_t) & BM_FTM_POL_POL6)
bogdanm 82:6473597d706e 3805
bogdanm 82:6473597d706e 3806 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3807 //! @brief Set the POL6 field to a new value.
bogdanm 82:6473597d706e 3808 #define BW_FTM_POL_POL6(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6) = (v))
bogdanm 82:6473597d706e 3809 #endif
bogdanm 82:6473597d706e 3810 //@}
bogdanm 82:6473597d706e 3811
bogdanm 82:6473597d706e 3812 /*!
bogdanm 82:6473597d706e 3813 * @name Register FTM_POL, field POL7[7] (RW)
bogdanm 82:6473597d706e 3814 *
bogdanm 82:6473597d706e 3815 * Defines the polarity of the channel output. This field is write protected. It
bogdanm 82:6473597d706e 3816 * can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 3817 *
bogdanm 82:6473597d706e 3818 * Values:
bogdanm 82:6473597d706e 3819 * - 0 - The channel polarity is active high.
bogdanm 82:6473597d706e 3820 * - 1 - The channel polarity is active low.
bogdanm 82:6473597d706e 3821 */
bogdanm 82:6473597d706e 3822 //@{
bogdanm 82:6473597d706e 3823 #define BP_FTM_POL_POL7 (7U) //!< Bit position for FTM_POL_POL7.
bogdanm 82:6473597d706e 3824 #define BM_FTM_POL_POL7 (0x00000080U) //!< Bit mask for FTM_POL_POL7.
bogdanm 82:6473597d706e 3825 #define BS_FTM_POL_POL7 (1U) //!< Bit field size in bits for FTM_POL_POL7.
bogdanm 82:6473597d706e 3826
bogdanm 82:6473597d706e 3827 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3828 //! @brief Read current value of the FTM_POL_POL7 field.
bogdanm 82:6473597d706e 3829 #define BR_FTM_POL_POL7(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7))
bogdanm 82:6473597d706e 3830 #endif
bogdanm 82:6473597d706e 3831
bogdanm 82:6473597d706e 3832 //! @brief Format value for bitfield FTM_POL_POL7.
bogdanm 82:6473597d706e 3833 #define BF_FTM_POL_POL7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL7), uint32_t) & BM_FTM_POL_POL7)
bogdanm 82:6473597d706e 3834
bogdanm 82:6473597d706e 3835 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3836 //! @brief Set the POL7 field to a new value.
bogdanm 82:6473597d706e 3837 #define BW_FTM_POL_POL7(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7) = (v))
bogdanm 82:6473597d706e 3838 #endif
bogdanm 82:6473597d706e 3839 //@}
bogdanm 82:6473597d706e 3840
bogdanm 82:6473597d706e 3841 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3842 // HW_FTM_FMS - Fault Mode Status
bogdanm 82:6473597d706e 3843 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3844
bogdanm 82:6473597d706e 3845 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3846 /*!
bogdanm 82:6473597d706e 3847 * @brief HW_FTM_FMS - Fault Mode Status (RW)
bogdanm 82:6473597d706e 3848 *
bogdanm 82:6473597d706e 3849 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 3850 *
bogdanm 82:6473597d706e 3851 * This register contains the fault detection flags, write protection enable
bogdanm 82:6473597d706e 3852 * bit, and the logic OR of the enabled fault inputs.
bogdanm 82:6473597d706e 3853 */
bogdanm 82:6473597d706e 3854 typedef union _hw_ftm_fms
bogdanm 82:6473597d706e 3855 {
bogdanm 82:6473597d706e 3856 uint32_t U;
bogdanm 82:6473597d706e 3857 struct _hw_ftm_fms_bitfields
bogdanm 82:6473597d706e 3858 {
bogdanm 82:6473597d706e 3859 uint32_t FAULTF0 : 1; //!< [0] Fault Detection Flag 0
bogdanm 82:6473597d706e 3860 uint32_t FAULTF1 : 1; //!< [1] Fault Detection Flag 1
bogdanm 82:6473597d706e 3861 uint32_t FAULTF2 : 1; //!< [2] Fault Detection Flag 2
bogdanm 82:6473597d706e 3862 uint32_t FAULTF3 : 1; //!< [3] Fault Detection Flag 3
bogdanm 82:6473597d706e 3863 uint32_t RESERVED0 : 1; //!< [4]
bogdanm 82:6473597d706e 3864 uint32_t FAULTIN : 1; //!< [5] Fault Inputs
bogdanm 82:6473597d706e 3865 uint32_t WPEN : 1; //!< [6] Write Protection Enable
bogdanm 82:6473597d706e 3866 uint32_t FAULTF : 1; //!< [7] Fault Detection Flag
bogdanm 82:6473597d706e 3867 uint32_t RESERVED1 : 24; //!< [31:8]
bogdanm 82:6473597d706e 3868 } B;
bogdanm 82:6473597d706e 3869 } hw_ftm_fms_t;
bogdanm 82:6473597d706e 3870 #endif
bogdanm 82:6473597d706e 3871
bogdanm 82:6473597d706e 3872 /*!
bogdanm 82:6473597d706e 3873 * @name Constants and macros for entire FTM_FMS register
bogdanm 82:6473597d706e 3874 */
bogdanm 82:6473597d706e 3875 //@{
bogdanm 82:6473597d706e 3876 #define HW_FTM_FMS_ADDR(x) (REGS_FTM_BASE(x) + 0x74U)
bogdanm 82:6473597d706e 3877
bogdanm 82:6473597d706e 3878 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3879 #define HW_FTM_FMS(x) (*(__IO hw_ftm_fms_t *) HW_FTM_FMS_ADDR(x))
bogdanm 82:6473597d706e 3880 #define HW_FTM_FMS_RD(x) (HW_FTM_FMS(x).U)
bogdanm 82:6473597d706e 3881 #define HW_FTM_FMS_WR(x, v) (HW_FTM_FMS(x).U = (v))
bogdanm 82:6473597d706e 3882 #define HW_FTM_FMS_SET(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) | (v)))
bogdanm 82:6473597d706e 3883 #define HW_FTM_FMS_CLR(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) & ~(v)))
bogdanm 82:6473597d706e 3884 #define HW_FTM_FMS_TOG(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) ^ (v)))
bogdanm 82:6473597d706e 3885 #endif
bogdanm 82:6473597d706e 3886 //@}
bogdanm 82:6473597d706e 3887
bogdanm 82:6473597d706e 3888 /*
bogdanm 82:6473597d706e 3889 * Constants & macros for individual FTM_FMS bitfields
bogdanm 82:6473597d706e 3890 */
bogdanm 82:6473597d706e 3891
bogdanm 82:6473597d706e 3892 /*!
bogdanm 82:6473597d706e 3893 * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
bogdanm 82:6473597d706e 3894 *
bogdanm 82:6473597d706e 3895 * Set by hardware when fault control is enabled, the corresponding fault input
bogdanm 82:6473597d706e 3896 * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
bogdanm 82:6473597d706e 3897 * by reading the FMS register while FAULTF0 is set and then writing a 0 to
bogdanm 82:6473597d706e 3898 * FAULTF0 while there is no existing fault condition at the corresponding fault
bogdanm 82:6473597d706e 3899 * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
bogdanm 82:6473597d706e 3900 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
bogdanm 82:6473597d706e 3901 * fault input before the clearing sequence is completed, the sequence is reset
bogdanm 82:6473597d706e 3902 * so FAULTF0 remains set after the clearing sequence is completed for the
bogdanm 82:6473597d706e 3903 * earlier fault condition.
bogdanm 82:6473597d706e 3904 *
bogdanm 82:6473597d706e 3905 * Values:
bogdanm 82:6473597d706e 3906 * - 0 - No fault condition was detected at the fault input.
bogdanm 82:6473597d706e 3907 * - 1 - A fault condition was detected at the fault input.
bogdanm 82:6473597d706e 3908 */
bogdanm 82:6473597d706e 3909 //@{
bogdanm 82:6473597d706e 3910 #define BP_FTM_FMS_FAULTF0 (0U) //!< Bit position for FTM_FMS_FAULTF0.
bogdanm 82:6473597d706e 3911 #define BM_FTM_FMS_FAULTF0 (0x00000001U) //!< Bit mask for FTM_FMS_FAULTF0.
bogdanm 82:6473597d706e 3912 #define BS_FTM_FMS_FAULTF0 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF0.
bogdanm 82:6473597d706e 3913
bogdanm 82:6473597d706e 3914 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3915 //! @brief Read current value of the FTM_FMS_FAULTF0 field.
bogdanm 82:6473597d706e 3916 #define BR_FTM_FMS_FAULTF0(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0))
bogdanm 82:6473597d706e 3917 #endif
bogdanm 82:6473597d706e 3918 //@}
bogdanm 82:6473597d706e 3919
bogdanm 82:6473597d706e 3920 /*!
bogdanm 82:6473597d706e 3921 * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
bogdanm 82:6473597d706e 3922 *
bogdanm 82:6473597d706e 3923 * Set by hardware when fault control is enabled, the corresponding fault input
bogdanm 82:6473597d706e 3924 * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
bogdanm 82:6473597d706e 3925 * by reading the FMS register while FAULTF1 is set and then writing a 0 to
bogdanm 82:6473597d706e 3926 * FAULTF1 while there is no existing fault condition at the corresponding fault
bogdanm 82:6473597d706e 3927 * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
bogdanm 82:6473597d706e 3928 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
bogdanm 82:6473597d706e 3929 * fault input before the clearing sequence is completed, the sequence is reset
bogdanm 82:6473597d706e 3930 * so FAULTF1 remains set after the clearing sequence is completed for the
bogdanm 82:6473597d706e 3931 * earlier fault condition.
bogdanm 82:6473597d706e 3932 *
bogdanm 82:6473597d706e 3933 * Values:
bogdanm 82:6473597d706e 3934 * - 0 - No fault condition was detected at the fault input.
bogdanm 82:6473597d706e 3935 * - 1 - A fault condition was detected at the fault input.
bogdanm 82:6473597d706e 3936 */
bogdanm 82:6473597d706e 3937 //@{
bogdanm 82:6473597d706e 3938 #define BP_FTM_FMS_FAULTF1 (1U) //!< Bit position for FTM_FMS_FAULTF1.
bogdanm 82:6473597d706e 3939 #define BM_FTM_FMS_FAULTF1 (0x00000002U) //!< Bit mask for FTM_FMS_FAULTF1.
bogdanm 82:6473597d706e 3940 #define BS_FTM_FMS_FAULTF1 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF1.
bogdanm 82:6473597d706e 3941
bogdanm 82:6473597d706e 3942 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3943 //! @brief Read current value of the FTM_FMS_FAULTF1 field.
bogdanm 82:6473597d706e 3944 #define BR_FTM_FMS_FAULTF1(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1))
bogdanm 82:6473597d706e 3945 #endif
bogdanm 82:6473597d706e 3946 //@}
bogdanm 82:6473597d706e 3947
bogdanm 82:6473597d706e 3948 /*!
bogdanm 82:6473597d706e 3949 * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
bogdanm 82:6473597d706e 3950 *
bogdanm 82:6473597d706e 3951 * Set by hardware when fault control is enabled, the corresponding fault input
bogdanm 82:6473597d706e 3952 * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
bogdanm 82:6473597d706e 3953 * by reading the FMS register while FAULTF2 is set and then writing a 0 to
bogdanm 82:6473597d706e 3954 * FAULTF2 while there is no existing fault condition at the corresponding fault
bogdanm 82:6473597d706e 3955 * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
bogdanm 82:6473597d706e 3956 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
bogdanm 82:6473597d706e 3957 * fault input before the clearing sequence is completed, the sequence is reset
bogdanm 82:6473597d706e 3958 * so FAULTF2 remains set after the clearing sequence is completed for the
bogdanm 82:6473597d706e 3959 * earlier fault condition.
bogdanm 82:6473597d706e 3960 *
bogdanm 82:6473597d706e 3961 * Values:
bogdanm 82:6473597d706e 3962 * - 0 - No fault condition was detected at the fault input.
bogdanm 82:6473597d706e 3963 * - 1 - A fault condition was detected at the fault input.
bogdanm 82:6473597d706e 3964 */
bogdanm 82:6473597d706e 3965 //@{
bogdanm 82:6473597d706e 3966 #define BP_FTM_FMS_FAULTF2 (2U) //!< Bit position for FTM_FMS_FAULTF2.
bogdanm 82:6473597d706e 3967 #define BM_FTM_FMS_FAULTF2 (0x00000004U) //!< Bit mask for FTM_FMS_FAULTF2.
bogdanm 82:6473597d706e 3968 #define BS_FTM_FMS_FAULTF2 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF2.
bogdanm 82:6473597d706e 3969
bogdanm 82:6473597d706e 3970 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3971 //! @brief Read current value of the FTM_FMS_FAULTF2 field.
bogdanm 82:6473597d706e 3972 #define BR_FTM_FMS_FAULTF2(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2))
bogdanm 82:6473597d706e 3973 #endif
bogdanm 82:6473597d706e 3974 //@}
bogdanm 82:6473597d706e 3975
bogdanm 82:6473597d706e 3976 /*!
bogdanm 82:6473597d706e 3977 * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
bogdanm 82:6473597d706e 3978 *
bogdanm 82:6473597d706e 3979 * Set by hardware when fault control is enabled, the corresponding fault input
bogdanm 82:6473597d706e 3980 * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
bogdanm 82:6473597d706e 3981 * by reading the FMS register while FAULTF3 is set and then writing a 0 to
bogdanm 82:6473597d706e 3982 * FAULTF3 while there is no existing fault condition at the corresponding fault
bogdanm 82:6473597d706e 3983 * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
bogdanm 82:6473597d706e 3984 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
bogdanm 82:6473597d706e 3985 * fault input before the clearing sequence is completed, the sequence is reset
bogdanm 82:6473597d706e 3986 * so FAULTF3 remains set after the clearing sequence is completed for the
bogdanm 82:6473597d706e 3987 * earlier fault condition.
bogdanm 82:6473597d706e 3988 *
bogdanm 82:6473597d706e 3989 * Values:
bogdanm 82:6473597d706e 3990 * - 0 - No fault condition was detected at the fault input.
bogdanm 82:6473597d706e 3991 * - 1 - A fault condition was detected at the fault input.
bogdanm 82:6473597d706e 3992 */
bogdanm 82:6473597d706e 3993 //@{
bogdanm 82:6473597d706e 3994 #define BP_FTM_FMS_FAULTF3 (3U) //!< Bit position for FTM_FMS_FAULTF3.
bogdanm 82:6473597d706e 3995 #define BM_FTM_FMS_FAULTF3 (0x00000008U) //!< Bit mask for FTM_FMS_FAULTF3.
bogdanm 82:6473597d706e 3996 #define BS_FTM_FMS_FAULTF3 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF3.
bogdanm 82:6473597d706e 3997
bogdanm 82:6473597d706e 3998 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3999 //! @brief Read current value of the FTM_FMS_FAULTF3 field.
bogdanm 82:6473597d706e 4000 #define BR_FTM_FMS_FAULTF3(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3))
bogdanm 82:6473597d706e 4001 #endif
bogdanm 82:6473597d706e 4002 //@}
bogdanm 82:6473597d706e 4003
bogdanm 82:6473597d706e 4004 /*!
bogdanm 82:6473597d706e 4005 * @name Register FTM_FMS, field FAULTIN[5] (RO)
bogdanm 82:6473597d706e 4006 *
bogdanm 82:6473597d706e 4007 * Represents the logic OR of the enabled fault inputs after their filter (if
bogdanm 82:6473597d706e 4008 * their filter is enabled) when fault control is enabled.
bogdanm 82:6473597d706e 4009 *
bogdanm 82:6473597d706e 4010 * Values:
bogdanm 82:6473597d706e 4011 * - 0 - The logic OR of the enabled fault inputs is 0.
bogdanm 82:6473597d706e 4012 * - 1 - The logic OR of the enabled fault inputs is 1.
bogdanm 82:6473597d706e 4013 */
bogdanm 82:6473597d706e 4014 //@{
bogdanm 82:6473597d706e 4015 #define BP_FTM_FMS_FAULTIN (5U) //!< Bit position for FTM_FMS_FAULTIN.
bogdanm 82:6473597d706e 4016 #define BM_FTM_FMS_FAULTIN (0x00000020U) //!< Bit mask for FTM_FMS_FAULTIN.
bogdanm 82:6473597d706e 4017 #define BS_FTM_FMS_FAULTIN (1U) //!< Bit field size in bits for FTM_FMS_FAULTIN.
bogdanm 82:6473597d706e 4018
bogdanm 82:6473597d706e 4019 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4020 //! @brief Read current value of the FTM_FMS_FAULTIN field.
bogdanm 82:6473597d706e 4021 #define BR_FTM_FMS_FAULTIN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTIN))
bogdanm 82:6473597d706e 4022 #endif
bogdanm 82:6473597d706e 4023 //@}
bogdanm 82:6473597d706e 4024
bogdanm 82:6473597d706e 4025 /*!
bogdanm 82:6473597d706e 4026 * @name Register FTM_FMS, field WPEN[6] (RW)
bogdanm 82:6473597d706e 4027 *
bogdanm 82:6473597d706e 4028 * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
bogdanm 82:6473597d706e 4029 * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
bogdanm 82:6473597d706e 4030 * WPDIS. Writing 0 to WPEN has no effect.
bogdanm 82:6473597d706e 4031 *
bogdanm 82:6473597d706e 4032 * Values:
bogdanm 82:6473597d706e 4033 * - 0 - Write protection is disabled. Write protected bits can be written.
bogdanm 82:6473597d706e 4034 * - 1 - Write protection is enabled. Write protected bits cannot be written.
bogdanm 82:6473597d706e 4035 */
bogdanm 82:6473597d706e 4036 //@{
bogdanm 82:6473597d706e 4037 #define BP_FTM_FMS_WPEN (6U) //!< Bit position for FTM_FMS_WPEN.
bogdanm 82:6473597d706e 4038 #define BM_FTM_FMS_WPEN (0x00000040U) //!< Bit mask for FTM_FMS_WPEN.
bogdanm 82:6473597d706e 4039 #define BS_FTM_FMS_WPEN (1U) //!< Bit field size in bits for FTM_FMS_WPEN.
bogdanm 82:6473597d706e 4040
bogdanm 82:6473597d706e 4041 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4042 //! @brief Read current value of the FTM_FMS_WPEN field.
bogdanm 82:6473597d706e 4043 #define BR_FTM_FMS_WPEN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN))
bogdanm 82:6473597d706e 4044 #endif
bogdanm 82:6473597d706e 4045
bogdanm 82:6473597d706e 4046 //! @brief Format value for bitfield FTM_FMS_WPEN.
bogdanm 82:6473597d706e 4047 #define BF_FTM_FMS_WPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FMS_WPEN), uint32_t) & BM_FTM_FMS_WPEN)
bogdanm 82:6473597d706e 4048
bogdanm 82:6473597d706e 4049 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4050 //! @brief Set the WPEN field to a new value.
bogdanm 82:6473597d706e 4051 #define BW_FTM_FMS_WPEN(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN) = (v))
bogdanm 82:6473597d706e 4052 #endif
bogdanm 82:6473597d706e 4053 //@}
bogdanm 82:6473597d706e 4054
bogdanm 82:6473597d706e 4055 /*!
bogdanm 82:6473597d706e 4056 * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
bogdanm 82:6473597d706e 4057 *
bogdanm 82:6473597d706e 4058 * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
bogdanm 82:6473597d706e 4059 * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
bogdanm 82:6473597d706e 4060 * a 0 to FAULTF while there is no existing fault condition at the enabled fault
bogdanm 82:6473597d706e 4061 * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
bogdanm 82:6473597d706e 4062 * detected in an enabled fault input before the clearing sequence is completed, the
bogdanm 82:6473597d706e 4063 * sequence is reset so FAULTF remains set after the clearing sequence is
bogdanm 82:6473597d706e 4064 * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
bogdanm 82:6473597d706e 4065 * are cleared individually.
bogdanm 82:6473597d706e 4066 *
bogdanm 82:6473597d706e 4067 * Values:
bogdanm 82:6473597d706e 4068 * - 0 - No fault condition was detected.
bogdanm 82:6473597d706e 4069 * - 1 - A fault condition was detected.
bogdanm 82:6473597d706e 4070 */
bogdanm 82:6473597d706e 4071 //@{
bogdanm 82:6473597d706e 4072 #define BP_FTM_FMS_FAULTF (7U) //!< Bit position for FTM_FMS_FAULTF.
bogdanm 82:6473597d706e 4073 #define BM_FTM_FMS_FAULTF (0x00000080U) //!< Bit mask for FTM_FMS_FAULTF.
bogdanm 82:6473597d706e 4074 #define BS_FTM_FMS_FAULTF (1U) //!< Bit field size in bits for FTM_FMS_FAULTF.
bogdanm 82:6473597d706e 4075
bogdanm 82:6473597d706e 4076 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4077 //! @brief Read current value of the FTM_FMS_FAULTF field.
bogdanm 82:6473597d706e 4078 #define BR_FTM_FMS_FAULTF(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF))
bogdanm 82:6473597d706e 4079 #endif
bogdanm 82:6473597d706e 4080 //@}
bogdanm 82:6473597d706e 4081
bogdanm 82:6473597d706e 4082 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4083 // HW_FTM_FILTER - Input Capture Filter Control
bogdanm 82:6473597d706e 4084 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4085
bogdanm 82:6473597d706e 4086 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4087 /*!
bogdanm 82:6473597d706e 4088 * @brief HW_FTM_FILTER - Input Capture Filter Control (RW)
bogdanm 82:6473597d706e 4089 *
bogdanm 82:6473597d706e 4090 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 4091 *
bogdanm 82:6473597d706e 4092 * This register selects the filter value for the inputs of channels. Channels
bogdanm 82:6473597d706e 4093 * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
bogdanm 82:6473597d706e 4094 * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
bogdanm 82:6473597d706e 4095 * in input modes. Failure to do this could result in a missing valid signal.
bogdanm 82:6473597d706e 4096 */
bogdanm 82:6473597d706e 4097 typedef union _hw_ftm_filter
bogdanm 82:6473597d706e 4098 {
bogdanm 82:6473597d706e 4099 uint32_t U;
bogdanm 82:6473597d706e 4100 struct _hw_ftm_filter_bitfields
bogdanm 82:6473597d706e 4101 {
bogdanm 82:6473597d706e 4102 uint32_t CH0FVAL : 4; //!< [3:0] Channel 0 Input Filter
bogdanm 82:6473597d706e 4103 uint32_t CH1FVAL : 4; //!< [7:4] Channel 1 Input Filter
bogdanm 82:6473597d706e 4104 uint32_t CH2FVAL : 4; //!< [11:8] Channel 2 Input Filter
bogdanm 82:6473597d706e 4105 uint32_t CH3FVAL : 4; //!< [15:12] Channel 3 Input Filter
bogdanm 82:6473597d706e 4106 uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm 82:6473597d706e 4107 } B;
bogdanm 82:6473597d706e 4108 } hw_ftm_filter_t;
bogdanm 82:6473597d706e 4109 #endif
bogdanm 82:6473597d706e 4110
bogdanm 82:6473597d706e 4111 /*!
bogdanm 82:6473597d706e 4112 * @name Constants and macros for entire FTM_FILTER register
bogdanm 82:6473597d706e 4113 */
bogdanm 82:6473597d706e 4114 //@{
bogdanm 82:6473597d706e 4115 #define HW_FTM_FILTER_ADDR(x) (REGS_FTM_BASE(x) + 0x78U)
bogdanm 82:6473597d706e 4116
bogdanm 82:6473597d706e 4117 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4118 #define HW_FTM_FILTER(x) (*(__IO hw_ftm_filter_t *) HW_FTM_FILTER_ADDR(x))
bogdanm 82:6473597d706e 4119 #define HW_FTM_FILTER_RD(x) (HW_FTM_FILTER(x).U)
bogdanm 82:6473597d706e 4120 #define HW_FTM_FILTER_WR(x, v) (HW_FTM_FILTER(x).U = (v))
bogdanm 82:6473597d706e 4121 #define HW_FTM_FILTER_SET(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) | (v)))
bogdanm 82:6473597d706e 4122 #define HW_FTM_FILTER_CLR(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) & ~(v)))
bogdanm 82:6473597d706e 4123 #define HW_FTM_FILTER_TOG(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) ^ (v)))
bogdanm 82:6473597d706e 4124 #endif
bogdanm 82:6473597d706e 4125 //@}
bogdanm 82:6473597d706e 4126
bogdanm 82:6473597d706e 4127 /*
bogdanm 82:6473597d706e 4128 * Constants & macros for individual FTM_FILTER bitfields
bogdanm 82:6473597d706e 4129 */
bogdanm 82:6473597d706e 4130
bogdanm 82:6473597d706e 4131 /*!
bogdanm 82:6473597d706e 4132 * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
bogdanm 82:6473597d706e 4133 *
bogdanm 82:6473597d706e 4134 * Selects the filter value for the channel input. The filter is disabled when
bogdanm 82:6473597d706e 4135 * the value is zero.
bogdanm 82:6473597d706e 4136 */
bogdanm 82:6473597d706e 4137 //@{
bogdanm 82:6473597d706e 4138 #define BP_FTM_FILTER_CH0FVAL (0U) //!< Bit position for FTM_FILTER_CH0FVAL.
bogdanm 82:6473597d706e 4139 #define BM_FTM_FILTER_CH0FVAL (0x0000000FU) //!< Bit mask for FTM_FILTER_CH0FVAL.
bogdanm 82:6473597d706e 4140 #define BS_FTM_FILTER_CH0FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH0FVAL.
bogdanm 82:6473597d706e 4141
bogdanm 82:6473597d706e 4142 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4143 //! @brief Read current value of the FTM_FILTER_CH0FVAL field.
bogdanm 82:6473597d706e 4144 #define BR_FTM_FILTER_CH0FVAL(x) (HW_FTM_FILTER(x).B.CH0FVAL)
bogdanm 82:6473597d706e 4145 #endif
bogdanm 82:6473597d706e 4146
bogdanm 82:6473597d706e 4147 //! @brief Format value for bitfield FTM_FILTER_CH0FVAL.
bogdanm 82:6473597d706e 4148 #define BF_FTM_FILTER_CH0FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH0FVAL), uint32_t) & BM_FTM_FILTER_CH0FVAL)
bogdanm 82:6473597d706e 4149
bogdanm 82:6473597d706e 4150 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4151 //! @brief Set the CH0FVAL field to a new value.
bogdanm 82:6473597d706e 4152 #define BW_FTM_FILTER_CH0FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH0FVAL) | BF_FTM_FILTER_CH0FVAL(v)))
bogdanm 82:6473597d706e 4153 #endif
bogdanm 82:6473597d706e 4154 //@}
bogdanm 82:6473597d706e 4155
bogdanm 82:6473597d706e 4156 /*!
bogdanm 82:6473597d706e 4157 * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
bogdanm 82:6473597d706e 4158 *
bogdanm 82:6473597d706e 4159 * Selects the filter value for the channel input. The filter is disabled when
bogdanm 82:6473597d706e 4160 * the value is zero.
bogdanm 82:6473597d706e 4161 */
bogdanm 82:6473597d706e 4162 //@{
bogdanm 82:6473597d706e 4163 #define BP_FTM_FILTER_CH1FVAL (4U) //!< Bit position for FTM_FILTER_CH1FVAL.
bogdanm 82:6473597d706e 4164 #define BM_FTM_FILTER_CH1FVAL (0x000000F0U) //!< Bit mask for FTM_FILTER_CH1FVAL.
bogdanm 82:6473597d706e 4165 #define BS_FTM_FILTER_CH1FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH1FVAL.
bogdanm 82:6473597d706e 4166
bogdanm 82:6473597d706e 4167 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4168 //! @brief Read current value of the FTM_FILTER_CH1FVAL field.
bogdanm 82:6473597d706e 4169 #define BR_FTM_FILTER_CH1FVAL(x) (HW_FTM_FILTER(x).B.CH1FVAL)
bogdanm 82:6473597d706e 4170 #endif
bogdanm 82:6473597d706e 4171
bogdanm 82:6473597d706e 4172 //! @brief Format value for bitfield FTM_FILTER_CH1FVAL.
bogdanm 82:6473597d706e 4173 #define BF_FTM_FILTER_CH1FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH1FVAL), uint32_t) & BM_FTM_FILTER_CH1FVAL)
bogdanm 82:6473597d706e 4174
bogdanm 82:6473597d706e 4175 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4176 //! @brief Set the CH1FVAL field to a new value.
bogdanm 82:6473597d706e 4177 #define BW_FTM_FILTER_CH1FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH1FVAL) | BF_FTM_FILTER_CH1FVAL(v)))
bogdanm 82:6473597d706e 4178 #endif
bogdanm 82:6473597d706e 4179 //@}
bogdanm 82:6473597d706e 4180
bogdanm 82:6473597d706e 4181 /*!
bogdanm 82:6473597d706e 4182 * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
bogdanm 82:6473597d706e 4183 *
bogdanm 82:6473597d706e 4184 * Selects the filter value for the channel input. The filter is disabled when
bogdanm 82:6473597d706e 4185 * the value is zero.
bogdanm 82:6473597d706e 4186 */
bogdanm 82:6473597d706e 4187 //@{
bogdanm 82:6473597d706e 4188 #define BP_FTM_FILTER_CH2FVAL (8U) //!< Bit position for FTM_FILTER_CH2FVAL.
bogdanm 82:6473597d706e 4189 #define BM_FTM_FILTER_CH2FVAL (0x00000F00U) //!< Bit mask for FTM_FILTER_CH2FVAL.
bogdanm 82:6473597d706e 4190 #define BS_FTM_FILTER_CH2FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH2FVAL.
bogdanm 82:6473597d706e 4191
bogdanm 82:6473597d706e 4192 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4193 //! @brief Read current value of the FTM_FILTER_CH2FVAL field.
bogdanm 82:6473597d706e 4194 #define BR_FTM_FILTER_CH2FVAL(x) (HW_FTM_FILTER(x).B.CH2FVAL)
bogdanm 82:6473597d706e 4195 #endif
bogdanm 82:6473597d706e 4196
bogdanm 82:6473597d706e 4197 //! @brief Format value for bitfield FTM_FILTER_CH2FVAL.
bogdanm 82:6473597d706e 4198 #define BF_FTM_FILTER_CH2FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH2FVAL), uint32_t) & BM_FTM_FILTER_CH2FVAL)
bogdanm 82:6473597d706e 4199
bogdanm 82:6473597d706e 4200 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4201 //! @brief Set the CH2FVAL field to a new value.
bogdanm 82:6473597d706e 4202 #define BW_FTM_FILTER_CH2FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH2FVAL) | BF_FTM_FILTER_CH2FVAL(v)))
bogdanm 82:6473597d706e 4203 #endif
bogdanm 82:6473597d706e 4204 //@}
bogdanm 82:6473597d706e 4205
bogdanm 82:6473597d706e 4206 /*!
bogdanm 82:6473597d706e 4207 * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
bogdanm 82:6473597d706e 4208 *
bogdanm 82:6473597d706e 4209 * Selects the filter value for the channel input. The filter is disabled when
bogdanm 82:6473597d706e 4210 * the value is zero.
bogdanm 82:6473597d706e 4211 */
bogdanm 82:6473597d706e 4212 //@{
bogdanm 82:6473597d706e 4213 #define BP_FTM_FILTER_CH3FVAL (12U) //!< Bit position for FTM_FILTER_CH3FVAL.
bogdanm 82:6473597d706e 4214 #define BM_FTM_FILTER_CH3FVAL (0x0000F000U) //!< Bit mask for FTM_FILTER_CH3FVAL.
bogdanm 82:6473597d706e 4215 #define BS_FTM_FILTER_CH3FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH3FVAL.
bogdanm 82:6473597d706e 4216
bogdanm 82:6473597d706e 4217 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4218 //! @brief Read current value of the FTM_FILTER_CH3FVAL field.
bogdanm 82:6473597d706e 4219 #define BR_FTM_FILTER_CH3FVAL(x) (HW_FTM_FILTER(x).B.CH3FVAL)
bogdanm 82:6473597d706e 4220 #endif
bogdanm 82:6473597d706e 4221
bogdanm 82:6473597d706e 4222 //! @brief Format value for bitfield FTM_FILTER_CH3FVAL.
bogdanm 82:6473597d706e 4223 #define BF_FTM_FILTER_CH3FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH3FVAL), uint32_t) & BM_FTM_FILTER_CH3FVAL)
bogdanm 82:6473597d706e 4224
bogdanm 82:6473597d706e 4225 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4226 //! @brief Set the CH3FVAL field to a new value.
bogdanm 82:6473597d706e 4227 #define BW_FTM_FILTER_CH3FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH3FVAL) | BF_FTM_FILTER_CH3FVAL(v)))
bogdanm 82:6473597d706e 4228 #endif
bogdanm 82:6473597d706e 4229 //@}
bogdanm 82:6473597d706e 4230
bogdanm 82:6473597d706e 4231 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4232 // HW_FTM_FLTCTRL - Fault Control
bogdanm 82:6473597d706e 4233 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4234
bogdanm 82:6473597d706e 4235 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4236 /*!
bogdanm 82:6473597d706e 4237 * @brief HW_FTM_FLTCTRL - Fault Control (RW)
bogdanm 82:6473597d706e 4238 *
bogdanm 82:6473597d706e 4239 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 4240 *
bogdanm 82:6473597d706e 4241 * This register selects the filter value for the fault inputs, enables the
bogdanm 82:6473597d706e 4242 * fault inputs and the fault inputs filter.
bogdanm 82:6473597d706e 4243 */
bogdanm 82:6473597d706e 4244 typedef union _hw_ftm_fltctrl
bogdanm 82:6473597d706e 4245 {
bogdanm 82:6473597d706e 4246 uint32_t U;
bogdanm 82:6473597d706e 4247 struct _hw_ftm_fltctrl_bitfields
bogdanm 82:6473597d706e 4248 {
bogdanm 82:6473597d706e 4249 uint32_t FAULT0EN : 1; //!< [0] Fault Input 0 Enable
bogdanm 82:6473597d706e 4250 uint32_t FAULT1EN : 1; //!< [1] Fault Input 1 Enable
bogdanm 82:6473597d706e 4251 uint32_t FAULT2EN : 1; //!< [2] Fault Input 2 Enable
bogdanm 82:6473597d706e 4252 uint32_t FAULT3EN : 1; //!< [3] Fault Input 3 Enable
bogdanm 82:6473597d706e 4253 uint32_t FFLTR0EN : 1; //!< [4] Fault Input 0 Filter Enable
bogdanm 82:6473597d706e 4254 uint32_t FFLTR1EN : 1; //!< [5] Fault Input 1 Filter Enable
bogdanm 82:6473597d706e 4255 uint32_t FFLTR2EN : 1; //!< [6] Fault Input 2 Filter Enable
bogdanm 82:6473597d706e 4256 uint32_t FFLTR3EN : 1; //!< [7] Fault Input 3 Filter Enable
bogdanm 82:6473597d706e 4257 uint32_t FFVAL : 4; //!< [11:8] Fault Input Filter
bogdanm 82:6473597d706e 4258 uint32_t RESERVED0 : 20; //!< [31:12]
bogdanm 82:6473597d706e 4259 } B;
bogdanm 82:6473597d706e 4260 } hw_ftm_fltctrl_t;
bogdanm 82:6473597d706e 4261 #endif
bogdanm 82:6473597d706e 4262
bogdanm 82:6473597d706e 4263 /*!
bogdanm 82:6473597d706e 4264 * @name Constants and macros for entire FTM_FLTCTRL register
bogdanm 82:6473597d706e 4265 */
bogdanm 82:6473597d706e 4266 //@{
bogdanm 82:6473597d706e 4267 #define HW_FTM_FLTCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x7CU)
bogdanm 82:6473597d706e 4268
bogdanm 82:6473597d706e 4269 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4270 #define HW_FTM_FLTCTRL(x) (*(__IO hw_ftm_fltctrl_t *) HW_FTM_FLTCTRL_ADDR(x))
bogdanm 82:6473597d706e 4271 #define HW_FTM_FLTCTRL_RD(x) (HW_FTM_FLTCTRL(x).U)
bogdanm 82:6473597d706e 4272 #define HW_FTM_FLTCTRL_WR(x, v) (HW_FTM_FLTCTRL(x).U = (v))
bogdanm 82:6473597d706e 4273 #define HW_FTM_FLTCTRL_SET(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) | (v)))
bogdanm 82:6473597d706e 4274 #define HW_FTM_FLTCTRL_CLR(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) & ~(v)))
bogdanm 82:6473597d706e 4275 #define HW_FTM_FLTCTRL_TOG(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) ^ (v)))
bogdanm 82:6473597d706e 4276 #endif
bogdanm 82:6473597d706e 4277 //@}
bogdanm 82:6473597d706e 4278
bogdanm 82:6473597d706e 4279 /*
bogdanm 82:6473597d706e 4280 * Constants & macros for individual FTM_FLTCTRL bitfields
bogdanm 82:6473597d706e 4281 */
bogdanm 82:6473597d706e 4282
bogdanm 82:6473597d706e 4283 /*!
bogdanm 82:6473597d706e 4284 * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
bogdanm 82:6473597d706e 4285 *
bogdanm 82:6473597d706e 4286 * Enables the fault input. This field is write protected. It can be written
bogdanm 82:6473597d706e 4287 * only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 4288 *
bogdanm 82:6473597d706e 4289 * Values:
bogdanm 82:6473597d706e 4290 * - 0 - Fault input is disabled.
bogdanm 82:6473597d706e 4291 * - 1 - Fault input is enabled.
bogdanm 82:6473597d706e 4292 */
bogdanm 82:6473597d706e 4293 //@{
bogdanm 82:6473597d706e 4294 #define BP_FTM_FLTCTRL_FAULT0EN (0U) //!< Bit position for FTM_FLTCTRL_FAULT0EN.
bogdanm 82:6473597d706e 4295 #define BM_FTM_FLTCTRL_FAULT0EN (0x00000001U) //!< Bit mask for FTM_FLTCTRL_FAULT0EN.
bogdanm 82:6473597d706e 4296 #define BS_FTM_FLTCTRL_FAULT0EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT0EN.
bogdanm 82:6473597d706e 4297
bogdanm 82:6473597d706e 4298 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4299 //! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field.
bogdanm 82:6473597d706e 4300 #define BR_FTM_FLTCTRL_FAULT0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN))
bogdanm 82:6473597d706e 4301 #endif
bogdanm 82:6473597d706e 4302
bogdanm 82:6473597d706e 4303 //! @brief Format value for bitfield FTM_FLTCTRL_FAULT0EN.
bogdanm 82:6473597d706e 4304 #define BF_FTM_FLTCTRL_FAULT0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT0EN), uint32_t) & BM_FTM_FLTCTRL_FAULT0EN)
bogdanm 82:6473597d706e 4305
bogdanm 82:6473597d706e 4306 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4307 //! @brief Set the FAULT0EN field to a new value.
bogdanm 82:6473597d706e 4308 #define BW_FTM_FLTCTRL_FAULT0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN) = (v))
bogdanm 82:6473597d706e 4309 #endif
bogdanm 82:6473597d706e 4310 //@}
bogdanm 82:6473597d706e 4311
bogdanm 82:6473597d706e 4312 /*!
bogdanm 82:6473597d706e 4313 * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
bogdanm 82:6473597d706e 4314 *
bogdanm 82:6473597d706e 4315 * Enables the fault input. This field is write protected. It can be written
bogdanm 82:6473597d706e 4316 * only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 4317 *
bogdanm 82:6473597d706e 4318 * Values:
bogdanm 82:6473597d706e 4319 * - 0 - Fault input is disabled.
bogdanm 82:6473597d706e 4320 * - 1 - Fault input is enabled.
bogdanm 82:6473597d706e 4321 */
bogdanm 82:6473597d706e 4322 //@{
bogdanm 82:6473597d706e 4323 #define BP_FTM_FLTCTRL_FAULT1EN (1U) //!< Bit position for FTM_FLTCTRL_FAULT1EN.
bogdanm 82:6473597d706e 4324 #define BM_FTM_FLTCTRL_FAULT1EN (0x00000002U) //!< Bit mask for FTM_FLTCTRL_FAULT1EN.
bogdanm 82:6473597d706e 4325 #define BS_FTM_FLTCTRL_FAULT1EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT1EN.
bogdanm 82:6473597d706e 4326
bogdanm 82:6473597d706e 4327 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4328 //! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field.
bogdanm 82:6473597d706e 4329 #define BR_FTM_FLTCTRL_FAULT1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN))
bogdanm 82:6473597d706e 4330 #endif
bogdanm 82:6473597d706e 4331
bogdanm 82:6473597d706e 4332 //! @brief Format value for bitfield FTM_FLTCTRL_FAULT1EN.
bogdanm 82:6473597d706e 4333 #define BF_FTM_FLTCTRL_FAULT1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT1EN), uint32_t) & BM_FTM_FLTCTRL_FAULT1EN)
bogdanm 82:6473597d706e 4334
bogdanm 82:6473597d706e 4335 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4336 //! @brief Set the FAULT1EN field to a new value.
bogdanm 82:6473597d706e 4337 #define BW_FTM_FLTCTRL_FAULT1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN) = (v))
bogdanm 82:6473597d706e 4338 #endif
bogdanm 82:6473597d706e 4339 //@}
bogdanm 82:6473597d706e 4340
bogdanm 82:6473597d706e 4341 /*!
bogdanm 82:6473597d706e 4342 * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
bogdanm 82:6473597d706e 4343 *
bogdanm 82:6473597d706e 4344 * Enables the fault input. This field is write protected. It can be written
bogdanm 82:6473597d706e 4345 * only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 4346 *
bogdanm 82:6473597d706e 4347 * Values:
bogdanm 82:6473597d706e 4348 * - 0 - Fault input is disabled.
bogdanm 82:6473597d706e 4349 * - 1 - Fault input is enabled.
bogdanm 82:6473597d706e 4350 */
bogdanm 82:6473597d706e 4351 //@{
bogdanm 82:6473597d706e 4352 #define BP_FTM_FLTCTRL_FAULT2EN (2U) //!< Bit position for FTM_FLTCTRL_FAULT2EN.
bogdanm 82:6473597d706e 4353 #define BM_FTM_FLTCTRL_FAULT2EN (0x00000004U) //!< Bit mask for FTM_FLTCTRL_FAULT2EN.
bogdanm 82:6473597d706e 4354 #define BS_FTM_FLTCTRL_FAULT2EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT2EN.
bogdanm 82:6473597d706e 4355
bogdanm 82:6473597d706e 4356 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4357 //! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field.
bogdanm 82:6473597d706e 4358 #define BR_FTM_FLTCTRL_FAULT2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN))
bogdanm 82:6473597d706e 4359 #endif
bogdanm 82:6473597d706e 4360
bogdanm 82:6473597d706e 4361 //! @brief Format value for bitfield FTM_FLTCTRL_FAULT2EN.
bogdanm 82:6473597d706e 4362 #define BF_FTM_FLTCTRL_FAULT2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT2EN), uint32_t) & BM_FTM_FLTCTRL_FAULT2EN)
bogdanm 82:6473597d706e 4363
bogdanm 82:6473597d706e 4364 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4365 //! @brief Set the FAULT2EN field to a new value.
bogdanm 82:6473597d706e 4366 #define BW_FTM_FLTCTRL_FAULT2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN) = (v))
bogdanm 82:6473597d706e 4367 #endif
bogdanm 82:6473597d706e 4368 //@}
bogdanm 82:6473597d706e 4369
bogdanm 82:6473597d706e 4370 /*!
bogdanm 82:6473597d706e 4371 * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
bogdanm 82:6473597d706e 4372 *
bogdanm 82:6473597d706e 4373 * Enables the fault input. This field is write protected. It can be written
bogdanm 82:6473597d706e 4374 * only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 4375 *
bogdanm 82:6473597d706e 4376 * Values:
bogdanm 82:6473597d706e 4377 * - 0 - Fault input is disabled.
bogdanm 82:6473597d706e 4378 * - 1 - Fault input is enabled.
bogdanm 82:6473597d706e 4379 */
bogdanm 82:6473597d706e 4380 //@{
bogdanm 82:6473597d706e 4381 #define BP_FTM_FLTCTRL_FAULT3EN (3U) //!< Bit position for FTM_FLTCTRL_FAULT3EN.
bogdanm 82:6473597d706e 4382 #define BM_FTM_FLTCTRL_FAULT3EN (0x00000008U) //!< Bit mask for FTM_FLTCTRL_FAULT3EN.
bogdanm 82:6473597d706e 4383 #define BS_FTM_FLTCTRL_FAULT3EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT3EN.
bogdanm 82:6473597d706e 4384
bogdanm 82:6473597d706e 4385 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4386 //! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field.
bogdanm 82:6473597d706e 4387 #define BR_FTM_FLTCTRL_FAULT3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN))
bogdanm 82:6473597d706e 4388 #endif
bogdanm 82:6473597d706e 4389
bogdanm 82:6473597d706e 4390 //! @brief Format value for bitfield FTM_FLTCTRL_FAULT3EN.
bogdanm 82:6473597d706e 4391 #define BF_FTM_FLTCTRL_FAULT3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT3EN), uint32_t) & BM_FTM_FLTCTRL_FAULT3EN)
bogdanm 82:6473597d706e 4392
bogdanm 82:6473597d706e 4393 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4394 //! @brief Set the FAULT3EN field to a new value.
bogdanm 82:6473597d706e 4395 #define BW_FTM_FLTCTRL_FAULT3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN) = (v))
bogdanm 82:6473597d706e 4396 #endif
bogdanm 82:6473597d706e 4397 //@}
bogdanm 82:6473597d706e 4398
bogdanm 82:6473597d706e 4399 /*!
bogdanm 82:6473597d706e 4400 * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
bogdanm 82:6473597d706e 4401 *
bogdanm 82:6473597d706e 4402 * Enables the filter for the fault input. This field is write protected. It can
bogdanm 82:6473597d706e 4403 * be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 4404 *
bogdanm 82:6473597d706e 4405 * Values:
bogdanm 82:6473597d706e 4406 * - 0 - Fault input filter is disabled.
bogdanm 82:6473597d706e 4407 * - 1 - Fault input filter is enabled.
bogdanm 82:6473597d706e 4408 */
bogdanm 82:6473597d706e 4409 //@{
bogdanm 82:6473597d706e 4410 #define BP_FTM_FLTCTRL_FFLTR0EN (4U) //!< Bit position for FTM_FLTCTRL_FFLTR0EN.
bogdanm 82:6473597d706e 4411 #define BM_FTM_FLTCTRL_FFLTR0EN (0x00000010U) //!< Bit mask for FTM_FLTCTRL_FFLTR0EN.
bogdanm 82:6473597d706e 4412 #define BS_FTM_FLTCTRL_FFLTR0EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR0EN.
bogdanm 82:6473597d706e 4413
bogdanm 82:6473597d706e 4414 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4415 //! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field.
bogdanm 82:6473597d706e 4416 #define BR_FTM_FLTCTRL_FFLTR0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN))
bogdanm 82:6473597d706e 4417 #endif
bogdanm 82:6473597d706e 4418
bogdanm 82:6473597d706e 4419 //! @brief Format value for bitfield FTM_FLTCTRL_FFLTR0EN.
bogdanm 82:6473597d706e 4420 #define BF_FTM_FLTCTRL_FFLTR0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR0EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR0EN)
bogdanm 82:6473597d706e 4421
bogdanm 82:6473597d706e 4422 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4423 //! @brief Set the FFLTR0EN field to a new value.
bogdanm 82:6473597d706e 4424 #define BW_FTM_FLTCTRL_FFLTR0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN) = (v))
bogdanm 82:6473597d706e 4425 #endif
bogdanm 82:6473597d706e 4426 //@}
bogdanm 82:6473597d706e 4427
bogdanm 82:6473597d706e 4428 /*!
bogdanm 82:6473597d706e 4429 * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
bogdanm 82:6473597d706e 4430 *
bogdanm 82:6473597d706e 4431 * Enables the filter for the fault input. This field is write protected. It can
bogdanm 82:6473597d706e 4432 * be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 4433 *
bogdanm 82:6473597d706e 4434 * Values:
bogdanm 82:6473597d706e 4435 * - 0 - Fault input filter is disabled.
bogdanm 82:6473597d706e 4436 * - 1 - Fault input filter is enabled.
bogdanm 82:6473597d706e 4437 */
bogdanm 82:6473597d706e 4438 //@{
bogdanm 82:6473597d706e 4439 #define BP_FTM_FLTCTRL_FFLTR1EN (5U) //!< Bit position for FTM_FLTCTRL_FFLTR1EN.
bogdanm 82:6473597d706e 4440 #define BM_FTM_FLTCTRL_FFLTR1EN (0x00000020U) //!< Bit mask for FTM_FLTCTRL_FFLTR1EN.
bogdanm 82:6473597d706e 4441 #define BS_FTM_FLTCTRL_FFLTR1EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR1EN.
bogdanm 82:6473597d706e 4442
bogdanm 82:6473597d706e 4443 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4444 //! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field.
bogdanm 82:6473597d706e 4445 #define BR_FTM_FLTCTRL_FFLTR1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN))
bogdanm 82:6473597d706e 4446 #endif
bogdanm 82:6473597d706e 4447
bogdanm 82:6473597d706e 4448 //! @brief Format value for bitfield FTM_FLTCTRL_FFLTR1EN.
bogdanm 82:6473597d706e 4449 #define BF_FTM_FLTCTRL_FFLTR1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR1EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR1EN)
bogdanm 82:6473597d706e 4450
bogdanm 82:6473597d706e 4451 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4452 //! @brief Set the FFLTR1EN field to a new value.
bogdanm 82:6473597d706e 4453 #define BW_FTM_FLTCTRL_FFLTR1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN) = (v))
bogdanm 82:6473597d706e 4454 #endif
bogdanm 82:6473597d706e 4455 //@}
bogdanm 82:6473597d706e 4456
bogdanm 82:6473597d706e 4457 /*!
bogdanm 82:6473597d706e 4458 * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
bogdanm 82:6473597d706e 4459 *
bogdanm 82:6473597d706e 4460 * Enables the filter for the fault input. This field is write protected. It can
bogdanm 82:6473597d706e 4461 * be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 4462 *
bogdanm 82:6473597d706e 4463 * Values:
bogdanm 82:6473597d706e 4464 * - 0 - Fault input filter is disabled.
bogdanm 82:6473597d706e 4465 * - 1 - Fault input filter is enabled.
bogdanm 82:6473597d706e 4466 */
bogdanm 82:6473597d706e 4467 //@{
bogdanm 82:6473597d706e 4468 #define BP_FTM_FLTCTRL_FFLTR2EN (6U) //!< Bit position for FTM_FLTCTRL_FFLTR2EN.
bogdanm 82:6473597d706e 4469 #define BM_FTM_FLTCTRL_FFLTR2EN (0x00000040U) //!< Bit mask for FTM_FLTCTRL_FFLTR2EN.
bogdanm 82:6473597d706e 4470 #define BS_FTM_FLTCTRL_FFLTR2EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR2EN.
bogdanm 82:6473597d706e 4471
bogdanm 82:6473597d706e 4472 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4473 //! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field.
bogdanm 82:6473597d706e 4474 #define BR_FTM_FLTCTRL_FFLTR2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN))
bogdanm 82:6473597d706e 4475 #endif
bogdanm 82:6473597d706e 4476
bogdanm 82:6473597d706e 4477 //! @brief Format value for bitfield FTM_FLTCTRL_FFLTR2EN.
bogdanm 82:6473597d706e 4478 #define BF_FTM_FLTCTRL_FFLTR2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR2EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR2EN)
bogdanm 82:6473597d706e 4479
bogdanm 82:6473597d706e 4480 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4481 //! @brief Set the FFLTR2EN field to a new value.
bogdanm 82:6473597d706e 4482 #define BW_FTM_FLTCTRL_FFLTR2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN) = (v))
bogdanm 82:6473597d706e 4483 #endif
bogdanm 82:6473597d706e 4484 //@}
bogdanm 82:6473597d706e 4485
bogdanm 82:6473597d706e 4486 /*!
bogdanm 82:6473597d706e 4487 * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
bogdanm 82:6473597d706e 4488 *
bogdanm 82:6473597d706e 4489 * Enables the filter for the fault input. This field is write protected. It can
bogdanm 82:6473597d706e 4490 * be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 4491 *
bogdanm 82:6473597d706e 4492 * Values:
bogdanm 82:6473597d706e 4493 * - 0 - Fault input filter is disabled.
bogdanm 82:6473597d706e 4494 * - 1 - Fault input filter is enabled.
bogdanm 82:6473597d706e 4495 */
bogdanm 82:6473597d706e 4496 //@{
bogdanm 82:6473597d706e 4497 #define BP_FTM_FLTCTRL_FFLTR3EN (7U) //!< Bit position for FTM_FLTCTRL_FFLTR3EN.
bogdanm 82:6473597d706e 4498 #define BM_FTM_FLTCTRL_FFLTR3EN (0x00000080U) //!< Bit mask for FTM_FLTCTRL_FFLTR3EN.
bogdanm 82:6473597d706e 4499 #define BS_FTM_FLTCTRL_FFLTR3EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR3EN.
bogdanm 82:6473597d706e 4500
bogdanm 82:6473597d706e 4501 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4502 //! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field.
bogdanm 82:6473597d706e 4503 #define BR_FTM_FLTCTRL_FFLTR3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN))
bogdanm 82:6473597d706e 4504 #endif
bogdanm 82:6473597d706e 4505
bogdanm 82:6473597d706e 4506 //! @brief Format value for bitfield FTM_FLTCTRL_FFLTR3EN.
bogdanm 82:6473597d706e 4507 #define BF_FTM_FLTCTRL_FFLTR3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR3EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR3EN)
bogdanm 82:6473597d706e 4508
bogdanm 82:6473597d706e 4509 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4510 //! @brief Set the FFLTR3EN field to a new value.
bogdanm 82:6473597d706e 4511 #define BW_FTM_FLTCTRL_FFLTR3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN) = (v))
bogdanm 82:6473597d706e 4512 #endif
bogdanm 82:6473597d706e 4513 //@}
bogdanm 82:6473597d706e 4514
bogdanm 82:6473597d706e 4515 /*!
bogdanm 82:6473597d706e 4516 * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
bogdanm 82:6473597d706e 4517 *
bogdanm 82:6473597d706e 4518 * Selects the filter value for the fault inputs. The fault filter is disabled
bogdanm 82:6473597d706e 4519 * when the value is zero. Writing to this field has immediate effect and must be
bogdanm 82:6473597d706e 4520 * done only when the fault control or all fault inputs are disabled. Failure to
bogdanm 82:6473597d706e 4521 * do this could result in a missing fault detection.
bogdanm 82:6473597d706e 4522 */
bogdanm 82:6473597d706e 4523 //@{
bogdanm 82:6473597d706e 4524 #define BP_FTM_FLTCTRL_FFVAL (8U) //!< Bit position for FTM_FLTCTRL_FFVAL.
bogdanm 82:6473597d706e 4525 #define BM_FTM_FLTCTRL_FFVAL (0x00000F00U) //!< Bit mask for FTM_FLTCTRL_FFVAL.
bogdanm 82:6473597d706e 4526 #define BS_FTM_FLTCTRL_FFVAL (4U) //!< Bit field size in bits for FTM_FLTCTRL_FFVAL.
bogdanm 82:6473597d706e 4527
bogdanm 82:6473597d706e 4528 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4529 //! @brief Read current value of the FTM_FLTCTRL_FFVAL field.
bogdanm 82:6473597d706e 4530 #define BR_FTM_FLTCTRL_FFVAL(x) (HW_FTM_FLTCTRL(x).B.FFVAL)
bogdanm 82:6473597d706e 4531 #endif
bogdanm 82:6473597d706e 4532
bogdanm 82:6473597d706e 4533 //! @brief Format value for bitfield FTM_FLTCTRL_FFVAL.
bogdanm 82:6473597d706e 4534 #define BF_FTM_FLTCTRL_FFVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFVAL), uint32_t) & BM_FTM_FLTCTRL_FFVAL)
bogdanm 82:6473597d706e 4535
bogdanm 82:6473597d706e 4536 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4537 //! @brief Set the FFVAL field to a new value.
bogdanm 82:6473597d706e 4538 #define BW_FTM_FLTCTRL_FFVAL(x, v) (HW_FTM_FLTCTRL_WR(x, (HW_FTM_FLTCTRL_RD(x) & ~BM_FTM_FLTCTRL_FFVAL) | BF_FTM_FLTCTRL_FFVAL(v)))
bogdanm 82:6473597d706e 4539 #endif
bogdanm 82:6473597d706e 4540 //@}
bogdanm 82:6473597d706e 4541
bogdanm 82:6473597d706e 4542 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4543 // HW_FTM_QDCTRL - Quadrature Decoder Control And Status
bogdanm 82:6473597d706e 4544 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4545
bogdanm 82:6473597d706e 4546 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4547 /*!
bogdanm 82:6473597d706e 4548 * @brief HW_FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
bogdanm 82:6473597d706e 4549 *
bogdanm 82:6473597d706e 4550 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 4551 *
bogdanm 82:6473597d706e 4552 * This register has the control and status bits for the Quadrature Decoder mode.
bogdanm 82:6473597d706e 4553 */
bogdanm 82:6473597d706e 4554 typedef union _hw_ftm_qdctrl
bogdanm 82:6473597d706e 4555 {
bogdanm 82:6473597d706e 4556 uint32_t U;
bogdanm 82:6473597d706e 4557 struct _hw_ftm_qdctrl_bitfields
bogdanm 82:6473597d706e 4558 {
bogdanm 82:6473597d706e 4559 uint32_t QUADEN : 1; //!< [0] Quadrature Decoder Mode Enable
bogdanm 82:6473597d706e 4560 uint32_t TOFDIR : 1; //!< [1] Timer Overflow Direction In Quadrature
bogdanm 82:6473597d706e 4561 //! Decoder Mode
bogdanm 82:6473597d706e 4562 uint32_t QUADIR : 1; //!< [2] FTM Counter Direction In Quadrature
bogdanm 82:6473597d706e 4563 //! Decoder Mode
bogdanm 82:6473597d706e 4564 uint32_t QUADMODE : 1; //!< [3] Quadrature Decoder Mode
bogdanm 82:6473597d706e 4565 uint32_t PHBPOL : 1; //!< [4] Phase B Input Polarity
bogdanm 82:6473597d706e 4566 uint32_t PHAPOL : 1; //!< [5] Phase A Input Polarity
bogdanm 82:6473597d706e 4567 uint32_t PHBFLTREN : 1; //!< [6] Phase B Input Filter Enable
bogdanm 82:6473597d706e 4568 uint32_t PHAFLTREN : 1; //!< [7] Phase A Input Filter Enable
bogdanm 82:6473597d706e 4569 uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm 82:6473597d706e 4570 } B;
bogdanm 82:6473597d706e 4571 } hw_ftm_qdctrl_t;
bogdanm 82:6473597d706e 4572 #endif
bogdanm 82:6473597d706e 4573
bogdanm 82:6473597d706e 4574 /*!
bogdanm 82:6473597d706e 4575 * @name Constants and macros for entire FTM_QDCTRL register
bogdanm 82:6473597d706e 4576 */
bogdanm 82:6473597d706e 4577 //@{
bogdanm 82:6473597d706e 4578 #define HW_FTM_QDCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x80U)
bogdanm 82:6473597d706e 4579
bogdanm 82:6473597d706e 4580 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4581 #define HW_FTM_QDCTRL(x) (*(__IO hw_ftm_qdctrl_t *) HW_FTM_QDCTRL_ADDR(x))
bogdanm 82:6473597d706e 4582 #define HW_FTM_QDCTRL_RD(x) (HW_FTM_QDCTRL(x).U)
bogdanm 82:6473597d706e 4583 #define HW_FTM_QDCTRL_WR(x, v) (HW_FTM_QDCTRL(x).U = (v))
bogdanm 82:6473597d706e 4584 #define HW_FTM_QDCTRL_SET(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) | (v)))
bogdanm 82:6473597d706e 4585 #define HW_FTM_QDCTRL_CLR(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) & ~(v)))
bogdanm 82:6473597d706e 4586 #define HW_FTM_QDCTRL_TOG(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) ^ (v)))
bogdanm 82:6473597d706e 4587 #endif
bogdanm 82:6473597d706e 4588 //@}
bogdanm 82:6473597d706e 4589
bogdanm 82:6473597d706e 4590 /*
bogdanm 82:6473597d706e 4591 * Constants & macros for individual FTM_QDCTRL bitfields
bogdanm 82:6473597d706e 4592 */
bogdanm 82:6473597d706e 4593
bogdanm 82:6473597d706e 4594 /*!
bogdanm 82:6473597d706e 4595 * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
bogdanm 82:6473597d706e 4596 *
bogdanm 82:6473597d706e 4597 * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
bogdanm 82:6473597d706e 4598 * signals control the FTM counter direction. The Quadrature Decoder mode has
bogdanm 82:6473597d706e 4599 * precedence over the other modes. See #ModeSel1Table. This field is write protected.
bogdanm 82:6473597d706e 4600 * It can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 4601 *
bogdanm 82:6473597d706e 4602 * Values:
bogdanm 82:6473597d706e 4603 * - 0 - Quadrature Decoder mode is disabled.
bogdanm 82:6473597d706e 4604 * - 1 - Quadrature Decoder mode is enabled.
bogdanm 82:6473597d706e 4605 */
bogdanm 82:6473597d706e 4606 //@{
bogdanm 82:6473597d706e 4607 #define BP_FTM_QDCTRL_QUADEN (0U) //!< Bit position for FTM_QDCTRL_QUADEN.
bogdanm 82:6473597d706e 4608 #define BM_FTM_QDCTRL_QUADEN (0x00000001U) //!< Bit mask for FTM_QDCTRL_QUADEN.
bogdanm 82:6473597d706e 4609 #define BS_FTM_QDCTRL_QUADEN (1U) //!< Bit field size in bits for FTM_QDCTRL_QUADEN.
bogdanm 82:6473597d706e 4610
bogdanm 82:6473597d706e 4611 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4612 //! @brief Read current value of the FTM_QDCTRL_QUADEN field.
bogdanm 82:6473597d706e 4613 #define BR_FTM_QDCTRL_QUADEN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN))
bogdanm 82:6473597d706e 4614 #endif
bogdanm 82:6473597d706e 4615
bogdanm 82:6473597d706e 4616 //! @brief Format value for bitfield FTM_QDCTRL_QUADEN.
bogdanm 82:6473597d706e 4617 #define BF_FTM_QDCTRL_QUADEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_QUADEN), uint32_t) & BM_FTM_QDCTRL_QUADEN)
bogdanm 82:6473597d706e 4618
bogdanm 82:6473597d706e 4619 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4620 //! @brief Set the QUADEN field to a new value.
bogdanm 82:6473597d706e 4621 #define BW_FTM_QDCTRL_QUADEN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN) = (v))
bogdanm 82:6473597d706e 4622 #endif
bogdanm 82:6473597d706e 4623 //@}
bogdanm 82:6473597d706e 4624
bogdanm 82:6473597d706e 4625 /*!
bogdanm 82:6473597d706e 4626 * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
bogdanm 82:6473597d706e 4627 *
bogdanm 82:6473597d706e 4628 * Indicates if the TOF bit was set on the top or the bottom of counting.
bogdanm 82:6473597d706e 4629 *
bogdanm 82:6473597d706e 4630 * Values:
bogdanm 82:6473597d706e 4631 * - 0 - TOF bit was set on the bottom of counting. There was an FTM counter
bogdanm 82:6473597d706e 4632 * decrement and FTM counter changes from its minimum value (CNTIN register) to
bogdanm 82:6473597d706e 4633 * its maximum value (MOD register).
bogdanm 82:6473597d706e 4634 * - 1 - TOF bit was set on the top of counting. There was an FTM counter
bogdanm 82:6473597d706e 4635 * increment and FTM counter changes from its maximum value (MOD register) to its
bogdanm 82:6473597d706e 4636 * minimum value (CNTIN register).
bogdanm 82:6473597d706e 4637 */
bogdanm 82:6473597d706e 4638 //@{
bogdanm 82:6473597d706e 4639 #define BP_FTM_QDCTRL_TOFDIR (1U) //!< Bit position for FTM_QDCTRL_TOFDIR.
bogdanm 82:6473597d706e 4640 #define BM_FTM_QDCTRL_TOFDIR (0x00000002U) //!< Bit mask for FTM_QDCTRL_TOFDIR.
bogdanm 82:6473597d706e 4641 #define BS_FTM_QDCTRL_TOFDIR (1U) //!< Bit field size in bits for FTM_QDCTRL_TOFDIR.
bogdanm 82:6473597d706e 4642
bogdanm 82:6473597d706e 4643 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4644 //! @brief Read current value of the FTM_QDCTRL_TOFDIR field.
bogdanm 82:6473597d706e 4645 #define BR_FTM_QDCTRL_TOFDIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_TOFDIR))
bogdanm 82:6473597d706e 4646 #endif
bogdanm 82:6473597d706e 4647 //@}
bogdanm 82:6473597d706e 4648
bogdanm 82:6473597d706e 4649 /*!
bogdanm 82:6473597d706e 4650 * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
bogdanm 82:6473597d706e 4651 *
bogdanm 82:6473597d706e 4652 * Indicates the counting direction.
bogdanm 82:6473597d706e 4653 *
bogdanm 82:6473597d706e 4654 * Values:
bogdanm 82:6473597d706e 4655 * - 0 - Counting direction is decreasing (FTM counter decrement).
bogdanm 82:6473597d706e 4656 * - 1 - Counting direction is increasing (FTM counter increment).
bogdanm 82:6473597d706e 4657 */
bogdanm 82:6473597d706e 4658 //@{
bogdanm 82:6473597d706e 4659 #define BP_FTM_QDCTRL_QUADIR (2U) //!< Bit position for FTM_QDCTRL_QUADIR.
bogdanm 82:6473597d706e 4660 #define BM_FTM_QDCTRL_QUADIR (0x00000004U) //!< Bit mask for FTM_QDCTRL_QUADIR.
bogdanm 82:6473597d706e 4661 #define BS_FTM_QDCTRL_QUADIR (1U) //!< Bit field size in bits for FTM_QDCTRL_QUADIR.
bogdanm 82:6473597d706e 4662
bogdanm 82:6473597d706e 4663 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4664 //! @brief Read current value of the FTM_QDCTRL_QUADIR field.
bogdanm 82:6473597d706e 4665 #define BR_FTM_QDCTRL_QUADIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADIR))
bogdanm 82:6473597d706e 4666 #endif
bogdanm 82:6473597d706e 4667 //@}
bogdanm 82:6473597d706e 4668
bogdanm 82:6473597d706e 4669 /*!
bogdanm 82:6473597d706e 4670 * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
bogdanm 82:6473597d706e 4671 *
bogdanm 82:6473597d706e 4672 * Selects the encoding mode used in the Quadrature Decoder mode.
bogdanm 82:6473597d706e 4673 *
bogdanm 82:6473597d706e 4674 * Values:
bogdanm 82:6473597d706e 4675 * - 0 - Phase A and phase B encoding mode.
bogdanm 82:6473597d706e 4676 * - 1 - Count and direction encoding mode.
bogdanm 82:6473597d706e 4677 */
bogdanm 82:6473597d706e 4678 //@{
bogdanm 82:6473597d706e 4679 #define BP_FTM_QDCTRL_QUADMODE (3U) //!< Bit position for FTM_QDCTRL_QUADMODE.
bogdanm 82:6473597d706e 4680 #define BM_FTM_QDCTRL_QUADMODE (0x00000008U) //!< Bit mask for FTM_QDCTRL_QUADMODE.
bogdanm 82:6473597d706e 4681 #define BS_FTM_QDCTRL_QUADMODE (1U) //!< Bit field size in bits for FTM_QDCTRL_QUADMODE.
bogdanm 82:6473597d706e 4682
bogdanm 82:6473597d706e 4683 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4684 //! @brief Read current value of the FTM_QDCTRL_QUADMODE field.
bogdanm 82:6473597d706e 4685 #define BR_FTM_QDCTRL_QUADMODE(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE))
bogdanm 82:6473597d706e 4686 #endif
bogdanm 82:6473597d706e 4687
bogdanm 82:6473597d706e 4688 //! @brief Format value for bitfield FTM_QDCTRL_QUADMODE.
bogdanm 82:6473597d706e 4689 #define BF_FTM_QDCTRL_QUADMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_QUADMODE), uint32_t) & BM_FTM_QDCTRL_QUADMODE)
bogdanm 82:6473597d706e 4690
bogdanm 82:6473597d706e 4691 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4692 //! @brief Set the QUADMODE field to a new value.
bogdanm 82:6473597d706e 4693 #define BW_FTM_QDCTRL_QUADMODE(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE) = (v))
bogdanm 82:6473597d706e 4694 #endif
bogdanm 82:6473597d706e 4695 //@}
bogdanm 82:6473597d706e 4696
bogdanm 82:6473597d706e 4697 /*!
bogdanm 82:6473597d706e 4698 * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
bogdanm 82:6473597d706e 4699 *
bogdanm 82:6473597d706e 4700 * Selects the polarity for the quadrature decoder phase B input.
bogdanm 82:6473597d706e 4701 *
bogdanm 82:6473597d706e 4702 * Values:
bogdanm 82:6473597d706e 4703 * - 0 - Normal polarity. Phase B input signal is not inverted before
bogdanm 82:6473597d706e 4704 * identifying the rising and falling edges of this signal.
bogdanm 82:6473597d706e 4705 * - 1 - Inverted polarity. Phase B input signal is inverted before identifying
bogdanm 82:6473597d706e 4706 * the rising and falling edges of this signal.
bogdanm 82:6473597d706e 4707 */
bogdanm 82:6473597d706e 4708 //@{
bogdanm 82:6473597d706e 4709 #define BP_FTM_QDCTRL_PHBPOL (4U) //!< Bit position for FTM_QDCTRL_PHBPOL.
bogdanm 82:6473597d706e 4710 #define BM_FTM_QDCTRL_PHBPOL (0x00000010U) //!< Bit mask for FTM_QDCTRL_PHBPOL.
bogdanm 82:6473597d706e 4711 #define BS_FTM_QDCTRL_PHBPOL (1U) //!< Bit field size in bits for FTM_QDCTRL_PHBPOL.
bogdanm 82:6473597d706e 4712
bogdanm 82:6473597d706e 4713 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4714 //! @brief Read current value of the FTM_QDCTRL_PHBPOL field.
bogdanm 82:6473597d706e 4715 #define BR_FTM_QDCTRL_PHBPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL))
bogdanm 82:6473597d706e 4716 #endif
bogdanm 82:6473597d706e 4717
bogdanm 82:6473597d706e 4718 //! @brief Format value for bitfield FTM_QDCTRL_PHBPOL.
bogdanm 82:6473597d706e 4719 #define BF_FTM_QDCTRL_PHBPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHBPOL), uint32_t) & BM_FTM_QDCTRL_PHBPOL)
bogdanm 82:6473597d706e 4720
bogdanm 82:6473597d706e 4721 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4722 //! @brief Set the PHBPOL field to a new value.
bogdanm 82:6473597d706e 4723 #define BW_FTM_QDCTRL_PHBPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL) = (v))
bogdanm 82:6473597d706e 4724 #endif
bogdanm 82:6473597d706e 4725 //@}
bogdanm 82:6473597d706e 4726
bogdanm 82:6473597d706e 4727 /*!
bogdanm 82:6473597d706e 4728 * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
bogdanm 82:6473597d706e 4729 *
bogdanm 82:6473597d706e 4730 * Selects the polarity for the quadrature decoder phase A input.
bogdanm 82:6473597d706e 4731 *
bogdanm 82:6473597d706e 4732 * Values:
bogdanm 82:6473597d706e 4733 * - 0 - Normal polarity. Phase A input signal is not inverted before
bogdanm 82:6473597d706e 4734 * identifying the rising and falling edges of this signal.
bogdanm 82:6473597d706e 4735 * - 1 - Inverted polarity. Phase A input signal is inverted before identifying
bogdanm 82:6473597d706e 4736 * the rising and falling edges of this signal.
bogdanm 82:6473597d706e 4737 */
bogdanm 82:6473597d706e 4738 //@{
bogdanm 82:6473597d706e 4739 #define BP_FTM_QDCTRL_PHAPOL (5U) //!< Bit position for FTM_QDCTRL_PHAPOL.
bogdanm 82:6473597d706e 4740 #define BM_FTM_QDCTRL_PHAPOL (0x00000020U) //!< Bit mask for FTM_QDCTRL_PHAPOL.
bogdanm 82:6473597d706e 4741 #define BS_FTM_QDCTRL_PHAPOL (1U) //!< Bit field size in bits for FTM_QDCTRL_PHAPOL.
bogdanm 82:6473597d706e 4742
bogdanm 82:6473597d706e 4743 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4744 //! @brief Read current value of the FTM_QDCTRL_PHAPOL field.
bogdanm 82:6473597d706e 4745 #define BR_FTM_QDCTRL_PHAPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL))
bogdanm 82:6473597d706e 4746 #endif
bogdanm 82:6473597d706e 4747
bogdanm 82:6473597d706e 4748 //! @brief Format value for bitfield FTM_QDCTRL_PHAPOL.
bogdanm 82:6473597d706e 4749 #define BF_FTM_QDCTRL_PHAPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHAPOL), uint32_t) & BM_FTM_QDCTRL_PHAPOL)
bogdanm 82:6473597d706e 4750
bogdanm 82:6473597d706e 4751 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4752 //! @brief Set the PHAPOL field to a new value.
bogdanm 82:6473597d706e 4753 #define BW_FTM_QDCTRL_PHAPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL) = (v))
bogdanm 82:6473597d706e 4754 #endif
bogdanm 82:6473597d706e 4755 //@}
bogdanm 82:6473597d706e 4756
bogdanm 82:6473597d706e 4757 /*!
bogdanm 82:6473597d706e 4758 * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
bogdanm 82:6473597d706e 4759 *
bogdanm 82:6473597d706e 4760 * Enables the filter for the quadrature decoder phase B input. The filter value
bogdanm 82:6473597d706e 4761 * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
bogdanm 82:6473597d706e 4762 * filter is also disabled when CH1FVAL is zero.
bogdanm 82:6473597d706e 4763 *
bogdanm 82:6473597d706e 4764 * Values:
bogdanm 82:6473597d706e 4765 * - 0 - Phase B input filter is disabled.
bogdanm 82:6473597d706e 4766 * - 1 - Phase B input filter is enabled.
bogdanm 82:6473597d706e 4767 */
bogdanm 82:6473597d706e 4768 //@{
bogdanm 82:6473597d706e 4769 #define BP_FTM_QDCTRL_PHBFLTREN (6U) //!< Bit position for FTM_QDCTRL_PHBFLTREN.
bogdanm 82:6473597d706e 4770 #define BM_FTM_QDCTRL_PHBFLTREN (0x00000040U) //!< Bit mask for FTM_QDCTRL_PHBFLTREN.
bogdanm 82:6473597d706e 4771 #define BS_FTM_QDCTRL_PHBFLTREN (1U) //!< Bit field size in bits for FTM_QDCTRL_PHBFLTREN.
bogdanm 82:6473597d706e 4772
bogdanm 82:6473597d706e 4773 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4774 //! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field.
bogdanm 82:6473597d706e 4775 #define BR_FTM_QDCTRL_PHBFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN))
bogdanm 82:6473597d706e 4776 #endif
bogdanm 82:6473597d706e 4777
bogdanm 82:6473597d706e 4778 //! @brief Format value for bitfield FTM_QDCTRL_PHBFLTREN.
bogdanm 82:6473597d706e 4779 #define BF_FTM_QDCTRL_PHBFLTREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHBFLTREN), uint32_t) & BM_FTM_QDCTRL_PHBFLTREN)
bogdanm 82:6473597d706e 4780
bogdanm 82:6473597d706e 4781 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4782 //! @brief Set the PHBFLTREN field to a new value.
bogdanm 82:6473597d706e 4783 #define BW_FTM_QDCTRL_PHBFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN) = (v))
bogdanm 82:6473597d706e 4784 #endif
bogdanm 82:6473597d706e 4785 //@}
bogdanm 82:6473597d706e 4786
bogdanm 82:6473597d706e 4787 /*!
bogdanm 82:6473597d706e 4788 * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
bogdanm 82:6473597d706e 4789 *
bogdanm 82:6473597d706e 4790 * Enables the filter for the quadrature decoder phase A input. The filter value
bogdanm 82:6473597d706e 4791 * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
bogdanm 82:6473597d706e 4792 * filter is also disabled when CH0FVAL is zero.
bogdanm 82:6473597d706e 4793 *
bogdanm 82:6473597d706e 4794 * Values:
bogdanm 82:6473597d706e 4795 * - 0 - Phase A input filter is disabled.
bogdanm 82:6473597d706e 4796 * - 1 - Phase A input filter is enabled.
bogdanm 82:6473597d706e 4797 */
bogdanm 82:6473597d706e 4798 //@{
bogdanm 82:6473597d706e 4799 #define BP_FTM_QDCTRL_PHAFLTREN (7U) //!< Bit position for FTM_QDCTRL_PHAFLTREN.
bogdanm 82:6473597d706e 4800 #define BM_FTM_QDCTRL_PHAFLTREN (0x00000080U) //!< Bit mask for FTM_QDCTRL_PHAFLTREN.
bogdanm 82:6473597d706e 4801 #define BS_FTM_QDCTRL_PHAFLTREN (1U) //!< Bit field size in bits for FTM_QDCTRL_PHAFLTREN.
bogdanm 82:6473597d706e 4802
bogdanm 82:6473597d706e 4803 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4804 //! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field.
bogdanm 82:6473597d706e 4805 #define BR_FTM_QDCTRL_PHAFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN))
bogdanm 82:6473597d706e 4806 #endif
bogdanm 82:6473597d706e 4807
bogdanm 82:6473597d706e 4808 //! @brief Format value for bitfield FTM_QDCTRL_PHAFLTREN.
bogdanm 82:6473597d706e 4809 #define BF_FTM_QDCTRL_PHAFLTREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHAFLTREN), uint32_t) & BM_FTM_QDCTRL_PHAFLTREN)
bogdanm 82:6473597d706e 4810
bogdanm 82:6473597d706e 4811 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4812 //! @brief Set the PHAFLTREN field to a new value.
bogdanm 82:6473597d706e 4813 #define BW_FTM_QDCTRL_PHAFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN) = (v))
bogdanm 82:6473597d706e 4814 #endif
bogdanm 82:6473597d706e 4815 //@}
bogdanm 82:6473597d706e 4816
bogdanm 82:6473597d706e 4817 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4818 // HW_FTM_CONF - Configuration
bogdanm 82:6473597d706e 4819 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4820
bogdanm 82:6473597d706e 4821 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4822 /*!
bogdanm 82:6473597d706e 4823 * @brief HW_FTM_CONF - Configuration (RW)
bogdanm 82:6473597d706e 4824 *
bogdanm 82:6473597d706e 4825 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 4826 *
bogdanm 82:6473597d706e 4827 * This register selects the number of times that the FTM counter overflow
bogdanm 82:6473597d706e 4828 * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
bogdanm 82:6473597d706e 4829 * of an external global time base, and the global time base signal generation.
bogdanm 82:6473597d706e 4830 */
bogdanm 82:6473597d706e 4831 typedef union _hw_ftm_conf
bogdanm 82:6473597d706e 4832 {
bogdanm 82:6473597d706e 4833 uint32_t U;
bogdanm 82:6473597d706e 4834 struct _hw_ftm_conf_bitfields
bogdanm 82:6473597d706e 4835 {
bogdanm 82:6473597d706e 4836 uint32_t NUMTOF : 5; //!< [4:0] TOF Frequency
bogdanm 82:6473597d706e 4837 uint32_t RESERVED0 : 1; //!< [5]
bogdanm 82:6473597d706e 4838 uint32_t BDMMODE : 2; //!< [7:6] BDM Mode
bogdanm 82:6473597d706e 4839 uint32_t RESERVED1 : 1; //!< [8]
bogdanm 82:6473597d706e 4840 uint32_t GTBEEN : 1; //!< [9] Global Time Base Enable
bogdanm 82:6473597d706e 4841 uint32_t GTBEOUT : 1; //!< [10] Global Time Base Output
bogdanm 82:6473597d706e 4842 uint32_t RESERVED2 : 21; //!< [31:11]
bogdanm 82:6473597d706e 4843 } B;
bogdanm 82:6473597d706e 4844 } hw_ftm_conf_t;
bogdanm 82:6473597d706e 4845 #endif
bogdanm 82:6473597d706e 4846
bogdanm 82:6473597d706e 4847 /*!
bogdanm 82:6473597d706e 4848 * @name Constants and macros for entire FTM_CONF register
bogdanm 82:6473597d706e 4849 */
bogdanm 82:6473597d706e 4850 //@{
bogdanm 82:6473597d706e 4851 #define HW_FTM_CONF_ADDR(x) (REGS_FTM_BASE(x) + 0x84U)
bogdanm 82:6473597d706e 4852
bogdanm 82:6473597d706e 4853 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4854 #define HW_FTM_CONF(x) (*(__IO hw_ftm_conf_t *) HW_FTM_CONF_ADDR(x))
bogdanm 82:6473597d706e 4855 #define HW_FTM_CONF_RD(x) (HW_FTM_CONF(x).U)
bogdanm 82:6473597d706e 4856 #define HW_FTM_CONF_WR(x, v) (HW_FTM_CONF(x).U = (v))
bogdanm 82:6473597d706e 4857 #define HW_FTM_CONF_SET(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) | (v)))
bogdanm 82:6473597d706e 4858 #define HW_FTM_CONF_CLR(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) & ~(v)))
bogdanm 82:6473597d706e 4859 #define HW_FTM_CONF_TOG(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) ^ (v)))
bogdanm 82:6473597d706e 4860 #endif
bogdanm 82:6473597d706e 4861 //@}
bogdanm 82:6473597d706e 4862
bogdanm 82:6473597d706e 4863 /*
bogdanm 82:6473597d706e 4864 * Constants & macros for individual FTM_CONF bitfields
bogdanm 82:6473597d706e 4865 */
bogdanm 82:6473597d706e 4866
bogdanm 82:6473597d706e 4867 /*!
bogdanm 82:6473597d706e 4868 * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
bogdanm 82:6473597d706e 4869 *
bogdanm 82:6473597d706e 4870 * Selects the ratio between the number of counter overflows to the number of
bogdanm 82:6473597d706e 4871 * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
bogdanm 82:6473597d706e 4872 * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
bogdanm 82:6473597d706e 4873 * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
bogdanm 82:6473597d706e 4874 * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
bogdanm 82:6473597d706e 4875 * first counter overflow but not for the next 3 overflows. This pattern continues
bogdanm 82:6473597d706e 4876 * up to a maximum of 31.
bogdanm 82:6473597d706e 4877 */
bogdanm 82:6473597d706e 4878 //@{
bogdanm 82:6473597d706e 4879 #define BP_FTM_CONF_NUMTOF (0U) //!< Bit position for FTM_CONF_NUMTOF.
bogdanm 82:6473597d706e 4880 #define BM_FTM_CONF_NUMTOF (0x0000001FU) //!< Bit mask for FTM_CONF_NUMTOF.
bogdanm 82:6473597d706e 4881 #define BS_FTM_CONF_NUMTOF (5U) //!< Bit field size in bits for FTM_CONF_NUMTOF.
bogdanm 82:6473597d706e 4882
bogdanm 82:6473597d706e 4883 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4884 //! @brief Read current value of the FTM_CONF_NUMTOF field.
bogdanm 82:6473597d706e 4885 #define BR_FTM_CONF_NUMTOF(x) (HW_FTM_CONF(x).B.NUMTOF)
bogdanm 82:6473597d706e 4886 #endif
bogdanm 82:6473597d706e 4887
bogdanm 82:6473597d706e 4888 //! @brief Format value for bitfield FTM_CONF_NUMTOF.
bogdanm 82:6473597d706e 4889 #define BF_FTM_CONF_NUMTOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_NUMTOF), uint32_t) & BM_FTM_CONF_NUMTOF)
bogdanm 82:6473597d706e 4890
bogdanm 82:6473597d706e 4891 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4892 //! @brief Set the NUMTOF field to a new value.
bogdanm 82:6473597d706e 4893 #define BW_FTM_CONF_NUMTOF(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_NUMTOF) | BF_FTM_CONF_NUMTOF(v)))
bogdanm 82:6473597d706e 4894 #endif
bogdanm 82:6473597d706e 4895 //@}
bogdanm 82:6473597d706e 4896
bogdanm 82:6473597d706e 4897 /*!
bogdanm 82:6473597d706e 4898 * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
bogdanm 82:6473597d706e 4899 *
bogdanm 82:6473597d706e 4900 * Selects the FTM behavior in BDM mode. See BDM mode.
bogdanm 82:6473597d706e 4901 */
bogdanm 82:6473597d706e 4902 //@{
bogdanm 82:6473597d706e 4903 #define BP_FTM_CONF_BDMMODE (6U) //!< Bit position for FTM_CONF_BDMMODE.
bogdanm 82:6473597d706e 4904 #define BM_FTM_CONF_BDMMODE (0x000000C0U) //!< Bit mask for FTM_CONF_BDMMODE.
bogdanm 82:6473597d706e 4905 #define BS_FTM_CONF_BDMMODE (2U) //!< Bit field size in bits for FTM_CONF_BDMMODE.
bogdanm 82:6473597d706e 4906
bogdanm 82:6473597d706e 4907 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4908 //! @brief Read current value of the FTM_CONF_BDMMODE field.
bogdanm 82:6473597d706e 4909 #define BR_FTM_CONF_BDMMODE(x) (HW_FTM_CONF(x).B.BDMMODE)
bogdanm 82:6473597d706e 4910 #endif
bogdanm 82:6473597d706e 4911
bogdanm 82:6473597d706e 4912 //! @brief Format value for bitfield FTM_CONF_BDMMODE.
bogdanm 82:6473597d706e 4913 #define BF_FTM_CONF_BDMMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_BDMMODE), uint32_t) & BM_FTM_CONF_BDMMODE)
bogdanm 82:6473597d706e 4914
bogdanm 82:6473597d706e 4915 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4916 //! @brief Set the BDMMODE field to a new value.
bogdanm 82:6473597d706e 4917 #define BW_FTM_CONF_BDMMODE(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_BDMMODE) | BF_FTM_CONF_BDMMODE(v)))
bogdanm 82:6473597d706e 4918 #endif
bogdanm 82:6473597d706e 4919 //@}
bogdanm 82:6473597d706e 4920
bogdanm 82:6473597d706e 4921 /*!
bogdanm 82:6473597d706e 4922 * @name Register FTM_CONF, field GTBEEN[9] (RW)
bogdanm 82:6473597d706e 4923 *
bogdanm 82:6473597d706e 4924 * Configures the FTM to use an external global time base signal that is
bogdanm 82:6473597d706e 4925 * generated by another FTM.
bogdanm 82:6473597d706e 4926 *
bogdanm 82:6473597d706e 4927 * Values:
bogdanm 82:6473597d706e 4928 * - 0 - Use of an external global time base is disabled.
bogdanm 82:6473597d706e 4929 * - 1 - Use of an external global time base is enabled.
bogdanm 82:6473597d706e 4930 */
bogdanm 82:6473597d706e 4931 //@{
bogdanm 82:6473597d706e 4932 #define BP_FTM_CONF_GTBEEN (9U) //!< Bit position for FTM_CONF_GTBEEN.
bogdanm 82:6473597d706e 4933 #define BM_FTM_CONF_GTBEEN (0x00000200U) //!< Bit mask for FTM_CONF_GTBEEN.
bogdanm 82:6473597d706e 4934 #define BS_FTM_CONF_GTBEEN (1U) //!< Bit field size in bits for FTM_CONF_GTBEEN.
bogdanm 82:6473597d706e 4935
bogdanm 82:6473597d706e 4936 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4937 //! @brief Read current value of the FTM_CONF_GTBEEN field.
bogdanm 82:6473597d706e 4938 #define BR_FTM_CONF_GTBEEN(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN))
bogdanm 82:6473597d706e 4939 #endif
bogdanm 82:6473597d706e 4940
bogdanm 82:6473597d706e 4941 //! @brief Format value for bitfield FTM_CONF_GTBEEN.
bogdanm 82:6473597d706e 4942 #define BF_FTM_CONF_GTBEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_GTBEEN), uint32_t) & BM_FTM_CONF_GTBEEN)
bogdanm 82:6473597d706e 4943
bogdanm 82:6473597d706e 4944 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4945 //! @brief Set the GTBEEN field to a new value.
bogdanm 82:6473597d706e 4946 #define BW_FTM_CONF_GTBEEN(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN) = (v))
bogdanm 82:6473597d706e 4947 #endif
bogdanm 82:6473597d706e 4948 //@}
bogdanm 82:6473597d706e 4949
bogdanm 82:6473597d706e 4950 /*!
bogdanm 82:6473597d706e 4951 * @name Register FTM_CONF, field GTBEOUT[10] (RW)
bogdanm 82:6473597d706e 4952 *
bogdanm 82:6473597d706e 4953 * Enables the global time base signal generation to other FTMs.
bogdanm 82:6473597d706e 4954 *
bogdanm 82:6473597d706e 4955 * Values:
bogdanm 82:6473597d706e 4956 * - 0 - A global time base signal generation is disabled.
bogdanm 82:6473597d706e 4957 * - 1 - A global time base signal generation is enabled.
bogdanm 82:6473597d706e 4958 */
bogdanm 82:6473597d706e 4959 //@{
bogdanm 82:6473597d706e 4960 #define BP_FTM_CONF_GTBEOUT (10U) //!< Bit position for FTM_CONF_GTBEOUT.
bogdanm 82:6473597d706e 4961 #define BM_FTM_CONF_GTBEOUT (0x00000400U) //!< Bit mask for FTM_CONF_GTBEOUT.
bogdanm 82:6473597d706e 4962 #define BS_FTM_CONF_GTBEOUT (1U) //!< Bit field size in bits for FTM_CONF_GTBEOUT.
bogdanm 82:6473597d706e 4963
bogdanm 82:6473597d706e 4964 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4965 //! @brief Read current value of the FTM_CONF_GTBEOUT field.
bogdanm 82:6473597d706e 4966 #define BR_FTM_CONF_GTBEOUT(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT))
bogdanm 82:6473597d706e 4967 #endif
bogdanm 82:6473597d706e 4968
bogdanm 82:6473597d706e 4969 //! @brief Format value for bitfield FTM_CONF_GTBEOUT.
bogdanm 82:6473597d706e 4970 #define BF_FTM_CONF_GTBEOUT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_GTBEOUT), uint32_t) & BM_FTM_CONF_GTBEOUT)
bogdanm 82:6473597d706e 4971
bogdanm 82:6473597d706e 4972 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4973 //! @brief Set the GTBEOUT field to a new value.
bogdanm 82:6473597d706e 4974 #define BW_FTM_CONF_GTBEOUT(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT) = (v))
bogdanm 82:6473597d706e 4975 #endif
bogdanm 82:6473597d706e 4976 //@}
bogdanm 82:6473597d706e 4977
bogdanm 82:6473597d706e 4978 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4979 // HW_FTM_FLTPOL - FTM Fault Input Polarity
bogdanm 82:6473597d706e 4980 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4981
bogdanm 82:6473597d706e 4982 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4983 /*!
bogdanm 82:6473597d706e 4984 * @brief HW_FTM_FLTPOL - FTM Fault Input Polarity (RW)
bogdanm 82:6473597d706e 4985 *
bogdanm 82:6473597d706e 4986 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 4987 *
bogdanm 82:6473597d706e 4988 * This register defines the fault inputs polarity.
bogdanm 82:6473597d706e 4989 */
bogdanm 82:6473597d706e 4990 typedef union _hw_ftm_fltpol
bogdanm 82:6473597d706e 4991 {
bogdanm 82:6473597d706e 4992 uint32_t U;
bogdanm 82:6473597d706e 4993 struct _hw_ftm_fltpol_bitfields
bogdanm 82:6473597d706e 4994 {
bogdanm 82:6473597d706e 4995 uint32_t FLT0POL : 1; //!< [0] Fault Input 0 Polarity
bogdanm 82:6473597d706e 4996 uint32_t FLT1POL : 1; //!< [1] Fault Input 1 Polarity
bogdanm 82:6473597d706e 4997 uint32_t FLT2POL : 1; //!< [2] Fault Input 2 Polarity
bogdanm 82:6473597d706e 4998 uint32_t FLT3POL : 1; //!< [3] Fault Input 3 Polarity
bogdanm 82:6473597d706e 4999 uint32_t RESERVED0 : 28; //!< [31:4]
bogdanm 82:6473597d706e 5000 } B;
bogdanm 82:6473597d706e 5001 } hw_ftm_fltpol_t;
bogdanm 82:6473597d706e 5002 #endif
bogdanm 82:6473597d706e 5003
bogdanm 82:6473597d706e 5004 /*!
bogdanm 82:6473597d706e 5005 * @name Constants and macros for entire FTM_FLTPOL register
bogdanm 82:6473597d706e 5006 */
bogdanm 82:6473597d706e 5007 //@{
bogdanm 82:6473597d706e 5008 #define HW_FTM_FLTPOL_ADDR(x) (REGS_FTM_BASE(x) + 0x88U)
bogdanm 82:6473597d706e 5009
bogdanm 82:6473597d706e 5010 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5011 #define HW_FTM_FLTPOL(x) (*(__IO hw_ftm_fltpol_t *) HW_FTM_FLTPOL_ADDR(x))
bogdanm 82:6473597d706e 5012 #define HW_FTM_FLTPOL_RD(x) (HW_FTM_FLTPOL(x).U)
bogdanm 82:6473597d706e 5013 #define HW_FTM_FLTPOL_WR(x, v) (HW_FTM_FLTPOL(x).U = (v))
bogdanm 82:6473597d706e 5014 #define HW_FTM_FLTPOL_SET(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) | (v)))
bogdanm 82:6473597d706e 5015 #define HW_FTM_FLTPOL_CLR(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) & ~(v)))
bogdanm 82:6473597d706e 5016 #define HW_FTM_FLTPOL_TOG(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) ^ (v)))
bogdanm 82:6473597d706e 5017 #endif
bogdanm 82:6473597d706e 5018 //@}
bogdanm 82:6473597d706e 5019
bogdanm 82:6473597d706e 5020 /*
bogdanm 82:6473597d706e 5021 * Constants & macros for individual FTM_FLTPOL bitfields
bogdanm 82:6473597d706e 5022 */
bogdanm 82:6473597d706e 5023
bogdanm 82:6473597d706e 5024 /*!
bogdanm 82:6473597d706e 5025 * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
bogdanm 82:6473597d706e 5026 *
bogdanm 82:6473597d706e 5027 * Defines the polarity of the fault input. This field is write protected. It
bogdanm 82:6473597d706e 5028 * can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 5029 *
bogdanm 82:6473597d706e 5030 * Values:
bogdanm 82:6473597d706e 5031 * - 0 - The fault input polarity is active high. A 1 at the fault input
bogdanm 82:6473597d706e 5032 * indicates a fault.
bogdanm 82:6473597d706e 5033 * - 1 - The fault input polarity is active low. A 0 at the fault input
bogdanm 82:6473597d706e 5034 * indicates a fault.
bogdanm 82:6473597d706e 5035 */
bogdanm 82:6473597d706e 5036 //@{
bogdanm 82:6473597d706e 5037 #define BP_FTM_FLTPOL_FLT0POL (0U) //!< Bit position for FTM_FLTPOL_FLT0POL.
bogdanm 82:6473597d706e 5038 #define BM_FTM_FLTPOL_FLT0POL (0x00000001U) //!< Bit mask for FTM_FLTPOL_FLT0POL.
bogdanm 82:6473597d706e 5039 #define BS_FTM_FLTPOL_FLT0POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT0POL.
bogdanm 82:6473597d706e 5040
bogdanm 82:6473597d706e 5041 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5042 //! @brief Read current value of the FTM_FLTPOL_FLT0POL field.
bogdanm 82:6473597d706e 5043 #define BR_FTM_FLTPOL_FLT0POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL))
bogdanm 82:6473597d706e 5044 #endif
bogdanm 82:6473597d706e 5045
bogdanm 82:6473597d706e 5046 //! @brief Format value for bitfield FTM_FLTPOL_FLT0POL.
bogdanm 82:6473597d706e 5047 #define BF_FTM_FLTPOL_FLT0POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT0POL), uint32_t) & BM_FTM_FLTPOL_FLT0POL)
bogdanm 82:6473597d706e 5048
bogdanm 82:6473597d706e 5049 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5050 //! @brief Set the FLT0POL field to a new value.
bogdanm 82:6473597d706e 5051 #define BW_FTM_FLTPOL_FLT0POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL) = (v))
bogdanm 82:6473597d706e 5052 #endif
bogdanm 82:6473597d706e 5053 //@}
bogdanm 82:6473597d706e 5054
bogdanm 82:6473597d706e 5055 /*!
bogdanm 82:6473597d706e 5056 * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
bogdanm 82:6473597d706e 5057 *
bogdanm 82:6473597d706e 5058 * Defines the polarity of the fault input. This field is write protected. It
bogdanm 82:6473597d706e 5059 * can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 5060 *
bogdanm 82:6473597d706e 5061 * Values:
bogdanm 82:6473597d706e 5062 * - 0 - The fault input polarity is active high. A 1 at the fault input
bogdanm 82:6473597d706e 5063 * indicates a fault.
bogdanm 82:6473597d706e 5064 * - 1 - The fault input polarity is active low. A 0 at the fault input
bogdanm 82:6473597d706e 5065 * indicates a fault.
bogdanm 82:6473597d706e 5066 */
bogdanm 82:6473597d706e 5067 //@{
bogdanm 82:6473597d706e 5068 #define BP_FTM_FLTPOL_FLT1POL (1U) //!< Bit position for FTM_FLTPOL_FLT1POL.
bogdanm 82:6473597d706e 5069 #define BM_FTM_FLTPOL_FLT1POL (0x00000002U) //!< Bit mask for FTM_FLTPOL_FLT1POL.
bogdanm 82:6473597d706e 5070 #define BS_FTM_FLTPOL_FLT1POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT1POL.
bogdanm 82:6473597d706e 5071
bogdanm 82:6473597d706e 5072 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5073 //! @brief Read current value of the FTM_FLTPOL_FLT1POL field.
bogdanm 82:6473597d706e 5074 #define BR_FTM_FLTPOL_FLT1POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL))
bogdanm 82:6473597d706e 5075 #endif
bogdanm 82:6473597d706e 5076
bogdanm 82:6473597d706e 5077 //! @brief Format value for bitfield FTM_FLTPOL_FLT1POL.
bogdanm 82:6473597d706e 5078 #define BF_FTM_FLTPOL_FLT1POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT1POL), uint32_t) & BM_FTM_FLTPOL_FLT1POL)
bogdanm 82:6473597d706e 5079
bogdanm 82:6473597d706e 5080 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5081 //! @brief Set the FLT1POL field to a new value.
bogdanm 82:6473597d706e 5082 #define BW_FTM_FLTPOL_FLT1POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL) = (v))
bogdanm 82:6473597d706e 5083 #endif
bogdanm 82:6473597d706e 5084 //@}
bogdanm 82:6473597d706e 5085
bogdanm 82:6473597d706e 5086 /*!
bogdanm 82:6473597d706e 5087 * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
bogdanm 82:6473597d706e 5088 *
bogdanm 82:6473597d706e 5089 * Defines the polarity of the fault input. This field is write protected. It
bogdanm 82:6473597d706e 5090 * can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 5091 *
bogdanm 82:6473597d706e 5092 * Values:
bogdanm 82:6473597d706e 5093 * - 0 - The fault input polarity is active high. A 1 at the fault input
bogdanm 82:6473597d706e 5094 * indicates a fault.
bogdanm 82:6473597d706e 5095 * - 1 - The fault input polarity is active low. A 0 at the fault input
bogdanm 82:6473597d706e 5096 * indicates a fault.
bogdanm 82:6473597d706e 5097 */
bogdanm 82:6473597d706e 5098 //@{
bogdanm 82:6473597d706e 5099 #define BP_FTM_FLTPOL_FLT2POL (2U) //!< Bit position for FTM_FLTPOL_FLT2POL.
bogdanm 82:6473597d706e 5100 #define BM_FTM_FLTPOL_FLT2POL (0x00000004U) //!< Bit mask for FTM_FLTPOL_FLT2POL.
bogdanm 82:6473597d706e 5101 #define BS_FTM_FLTPOL_FLT2POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT2POL.
bogdanm 82:6473597d706e 5102
bogdanm 82:6473597d706e 5103 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5104 //! @brief Read current value of the FTM_FLTPOL_FLT2POL field.
bogdanm 82:6473597d706e 5105 #define BR_FTM_FLTPOL_FLT2POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL))
bogdanm 82:6473597d706e 5106 #endif
bogdanm 82:6473597d706e 5107
bogdanm 82:6473597d706e 5108 //! @brief Format value for bitfield FTM_FLTPOL_FLT2POL.
bogdanm 82:6473597d706e 5109 #define BF_FTM_FLTPOL_FLT2POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT2POL), uint32_t) & BM_FTM_FLTPOL_FLT2POL)
bogdanm 82:6473597d706e 5110
bogdanm 82:6473597d706e 5111 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5112 //! @brief Set the FLT2POL field to a new value.
bogdanm 82:6473597d706e 5113 #define BW_FTM_FLTPOL_FLT2POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL) = (v))
bogdanm 82:6473597d706e 5114 #endif
bogdanm 82:6473597d706e 5115 //@}
bogdanm 82:6473597d706e 5116
bogdanm 82:6473597d706e 5117 /*!
bogdanm 82:6473597d706e 5118 * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
bogdanm 82:6473597d706e 5119 *
bogdanm 82:6473597d706e 5120 * Defines the polarity of the fault input. This field is write protected. It
bogdanm 82:6473597d706e 5121 * can be written only when MODE[WPDIS] = 1.
bogdanm 82:6473597d706e 5122 *
bogdanm 82:6473597d706e 5123 * Values:
bogdanm 82:6473597d706e 5124 * - 0 - The fault input polarity is active high. A 1 at the fault input
bogdanm 82:6473597d706e 5125 * indicates a fault.
bogdanm 82:6473597d706e 5126 * - 1 - The fault input polarity is active low. A 0 at the fault input
bogdanm 82:6473597d706e 5127 * indicates a fault.
bogdanm 82:6473597d706e 5128 */
bogdanm 82:6473597d706e 5129 //@{
bogdanm 82:6473597d706e 5130 #define BP_FTM_FLTPOL_FLT3POL (3U) //!< Bit position for FTM_FLTPOL_FLT3POL.
bogdanm 82:6473597d706e 5131 #define BM_FTM_FLTPOL_FLT3POL (0x00000008U) //!< Bit mask for FTM_FLTPOL_FLT3POL.
bogdanm 82:6473597d706e 5132 #define BS_FTM_FLTPOL_FLT3POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT3POL.
bogdanm 82:6473597d706e 5133
bogdanm 82:6473597d706e 5134 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5135 //! @brief Read current value of the FTM_FLTPOL_FLT3POL field.
bogdanm 82:6473597d706e 5136 #define BR_FTM_FLTPOL_FLT3POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL))
bogdanm 82:6473597d706e 5137 #endif
bogdanm 82:6473597d706e 5138
bogdanm 82:6473597d706e 5139 //! @brief Format value for bitfield FTM_FLTPOL_FLT3POL.
bogdanm 82:6473597d706e 5140 #define BF_FTM_FLTPOL_FLT3POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT3POL), uint32_t) & BM_FTM_FLTPOL_FLT3POL)
bogdanm 82:6473597d706e 5141
bogdanm 82:6473597d706e 5142 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5143 //! @brief Set the FLT3POL field to a new value.
bogdanm 82:6473597d706e 5144 #define BW_FTM_FLTPOL_FLT3POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL) = (v))
bogdanm 82:6473597d706e 5145 #endif
bogdanm 82:6473597d706e 5146 //@}
bogdanm 82:6473597d706e 5147
bogdanm 82:6473597d706e 5148 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5149 // HW_FTM_SYNCONF - Synchronization Configuration
bogdanm 82:6473597d706e 5150 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5151
bogdanm 82:6473597d706e 5152 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5153 /*!
bogdanm 82:6473597d706e 5154 * @brief HW_FTM_SYNCONF - Synchronization Configuration (RW)
bogdanm 82:6473597d706e 5155 *
bogdanm 82:6473597d706e 5156 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 5157 *
bogdanm 82:6473597d706e 5158 * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
bogdanm 82:6473597d706e 5159 * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
bogdanm 82:6473597d706e 5160 * 0, 1, 2, when the hardware trigger j is detected.
bogdanm 82:6473597d706e 5161 */
bogdanm 82:6473597d706e 5162 typedef union _hw_ftm_synconf
bogdanm 82:6473597d706e 5163 {
bogdanm 82:6473597d706e 5164 uint32_t U;
bogdanm 82:6473597d706e 5165 struct _hw_ftm_synconf_bitfields
bogdanm 82:6473597d706e 5166 {
bogdanm 82:6473597d706e 5167 uint32_t HWTRIGMODE : 1; //!< [0] Hardware Trigger Mode
bogdanm 82:6473597d706e 5168 uint32_t RESERVED0 : 1; //!< [1]
bogdanm 82:6473597d706e 5169 uint32_t CNTINC : 1; //!< [2] CNTIN Register Synchronization
bogdanm 82:6473597d706e 5170 uint32_t RESERVED1 : 1; //!< [3]
bogdanm 82:6473597d706e 5171 uint32_t INVC : 1; //!< [4] INVCTRL Register Synchronization
bogdanm 82:6473597d706e 5172 uint32_t SWOC : 1; //!< [5] SWOCTRL Register Synchronization
bogdanm 82:6473597d706e 5173 uint32_t RESERVED2 : 1; //!< [6]
bogdanm 82:6473597d706e 5174 uint32_t SYNCMODE : 1; //!< [7] Synchronization Mode
bogdanm 82:6473597d706e 5175 uint32_t SWRSTCNT : 1; //!< [8]
bogdanm 82:6473597d706e 5176 uint32_t SWWRBUF : 1; //!< [9]
bogdanm 82:6473597d706e 5177 uint32_t SWOM : 1; //!< [10]
bogdanm 82:6473597d706e 5178 uint32_t SWINVC : 1; //!< [11]
bogdanm 82:6473597d706e 5179 uint32_t SWSOC : 1; //!< [12]
bogdanm 82:6473597d706e 5180 uint32_t RESERVED3 : 3; //!< [15:13]
bogdanm 82:6473597d706e 5181 uint32_t HWRSTCNT : 1; //!< [16]
bogdanm 82:6473597d706e 5182 uint32_t HWWRBUF : 1; //!< [17]
bogdanm 82:6473597d706e 5183 uint32_t HWOM : 1; //!< [18]
bogdanm 82:6473597d706e 5184 uint32_t HWINVC : 1; //!< [19]
bogdanm 82:6473597d706e 5185 uint32_t HWSOC : 1; //!< [20]
bogdanm 82:6473597d706e 5186 uint32_t RESERVED4 : 11; //!< [31:21]
bogdanm 82:6473597d706e 5187 } B;
bogdanm 82:6473597d706e 5188 } hw_ftm_synconf_t;
bogdanm 82:6473597d706e 5189 #endif
bogdanm 82:6473597d706e 5190
bogdanm 82:6473597d706e 5191 /*!
bogdanm 82:6473597d706e 5192 * @name Constants and macros for entire FTM_SYNCONF register
bogdanm 82:6473597d706e 5193 */
bogdanm 82:6473597d706e 5194 //@{
bogdanm 82:6473597d706e 5195 #define HW_FTM_SYNCONF_ADDR(x) (REGS_FTM_BASE(x) + 0x8CU)
bogdanm 82:6473597d706e 5196
bogdanm 82:6473597d706e 5197 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5198 #define HW_FTM_SYNCONF(x) (*(__IO hw_ftm_synconf_t *) HW_FTM_SYNCONF_ADDR(x))
bogdanm 82:6473597d706e 5199 #define HW_FTM_SYNCONF_RD(x) (HW_FTM_SYNCONF(x).U)
bogdanm 82:6473597d706e 5200 #define HW_FTM_SYNCONF_WR(x, v) (HW_FTM_SYNCONF(x).U = (v))
bogdanm 82:6473597d706e 5201 #define HW_FTM_SYNCONF_SET(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) | (v)))
bogdanm 82:6473597d706e 5202 #define HW_FTM_SYNCONF_CLR(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) & ~(v)))
bogdanm 82:6473597d706e 5203 #define HW_FTM_SYNCONF_TOG(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) ^ (v)))
bogdanm 82:6473597d706e 5204 #endif
bogdanm 82:6473597d706e 5205 //@}
bogdanm 82:6473597d706e 5206
bogdanm 82:6473597d706e 5207 /*
bogdanm 82:6473597d706e 5208 * Constants & macros for individual FTM_SYNCONF bitfields
bogdanm 82:6473597d706e 5209 */
bogdanm 82:6473597d706e 5210
bogdanm 82:6473597d706e 5211 /*!
bogdanm 82:6473597d706e 5212 * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
bogdanm 82:6473597d706e 5213 *
bogdanm 82:6473597d706e 5214 * Values:
bogdanm 82:6473597d706e 5215 * - 0 - FTM clears the TRIGj bit when the hardware trigger j is detected, where
bogdanm 82:6473597d706e 5216 * j = 0, 1,2.
bogdanm 82:6473597d706e 5217 * - 1 - FTM does not clear the TRIGj bit when the hardware trigger j is
bogdanm 82:6473597d706e 5218 * detected, where j = 0, 1,2.
bogdanm 82:6473597d706e 5219 */
bogdanm 82:6473597d706e 5220 //@{
bogdanm 82:6473597d706e 5221 #define BP_FTM_SYNCONF_HWTRIGMODE (0U) //!< Bit position for FTM_SYNCONF_HWTRIGMODE.
bogdanm 82:6473597d706e 5222 #define BM_FTM_SYNCONF_HWTRIGMODE (0x00000001U) //!< Bit mask for FTM_SYNCONF_HWTRIGMODE.
bogdanm 82:6473597d706e 5223 #define BS_FTM_SYNCONF_HWTRIGMODE (1U) //!< Bit field size in bits for FTM_SYNCONF_HWTRIGMODE.
bogdanm 82:6473597d706e 5224
bogdanm 82:6473597d706e 5225 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5226 //! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field.
bogdanm 82:6473597d706e 5227 #define BR_FTM_SYNCONF_HWTRIGMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE))
bogdanm 82:6473597d706e 5228 #endif
bogdanm 82:6473597d706e 5229
bogdanm 82:6473597d706e 5230 //! @brief Format value for bitfield FTM_SYNCONF_HWTRIGMODE.
bogdanm 82:6473597d706e 5231 #define BF_FTM_SYNCONF_HWTRIGMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWTRIGMODE), uint32_t) & BM_FTM_SYNCONF_HWTRIGMODE)
bogdanm 82:6473597d706e 5232
bogdanm 82:6473597d706e 5233 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5234 //! @brief Set the HWTRIGMODE field to a new value.
bogdanm 82:6473597d706e 5235 #define BW_FTM_SYNCONF_HWTRIGMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE) = (v))
bogdanm 82:6473597d706e 5236 #endif
bogdanm 82:6473597d706e 5237 //@}
bogdanm 82:6473597d706e 5238
bogdanm 82:6473597d706e 5239 /*!
bogdanm 82:6473597d706e 5240 * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
bogdanm 82:6473597d706e 5241 *
bogdanm 82:6473597d706e 5242 * Values:
bogdanm 82:6473597d706e 5243 * - 0 - CNTIN register is updated with its buffer value at all rising edges of
bogdanm 82:6473597d706e 5244 * system clock.
bogdanm 82:6473597d706e 5245 * - 1 - CNTIN register is updated with its buffer value by the PWM
bogdanm 82:6473597d706e 5246 * synchronization.
bogdanm 82:6473597d706e 5247 */
bogdanm 82:6473597d706e 5248 //@{
bogdanm 82:6473597d706e 5249 #define BP_FTM_SYNCONF_CNTINC (2U) //!< Bit position for FTM_SYNCONF_CNTINC.
bogdanm 82:6473597d706e 5250 #define BM_FTM_SYNCONF_CNTINC (0x00000004U) //!< Bit mask for FTM_SYNCONF_CNTINC.
bogdanm 82:6473597d706e 5251 #define BS_FTM_SYNCONF_CNTINC (1U) //!< Bit field size in bits for FTM_SYNCONF_CNTINC.
bogdanm 82:6473597d706e 5252
bogdanm 82:6473597d706e 5253 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5254 //! @brief Read current value of the FTM_SYNCONF_CNTINC field.
bogdanm 82:6473597d706e 5255 #define BR_FTM_SYNCONF_CNTINC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC))
bogdanm 82:6473597d706e 5256 #endif
bogdanm 82:6473597d706e 5257
bogdanm 82:6473597d706e 5258 //! @brief Format value for bitfield FTM_SYNCONF_CNTINC.
bogdanm 82:6473597d706e 5259 #define BF_FTM_SYNCONF_CNTINC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_CNTINC), uint32_t) & BM_FTM_SYNCONF_CNTINC)
bogdanm 82:6473597d706e 5260
bogdanm 82:6473597d706e 5261 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5262 //! @brief Set the CNTINC field to a new value.
bogdanm 82:6473597d706e 5263 #define BW_FTM_SYNCONF_CNTINC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC) = (v))
bogdanm 82:6473597d706e 5264 #endif
bogdanm 82:6473597d706e 5265 //@}
bogdanm 82:6473597d706e 5266
bogdanm 82:6473597d706e 5267 /*!
bogdanm 82:6473597d706e 5268 * @name Register FTM_SYNCONF, field INVC[4] (RW)
bogdanm 82:6473597d706e 5269 *
bogdanm 82:6473597d706e 5270 * Values:
bogdanm 82:6473597d706e 5271 * - 0 - INVCTRL register is updated with its buffer value at all rising edges
bogdanm 82:6473597d706e 5272 * of system clock.
bogdanm 82:6473597d706e 5273 * - 1 - INVCTRL register is updated with its buffer value by the PWM
bogdanm 82:6473597d706e 5274 * synchronization.
bogdanm 82:6473597d706e 5275 */
bogdanm 82:6473597d706e 5276 //@{
bogdanm 82:6473597d706e 5277 #define BP_FTM_SYNCONF_INVC (4U) //!< Bit position for FTM_SYNCONF_INVC.
bogdanm 82:6473597d706e 5278 #define BM_FTM_SYNCONF_INVC (0x00000010U) //!< Bit mask for FTM_SYNCONF_INVC.
bogdanm 82:6473597d706e 5279 #define BS_FTM_SYNCONF_INVC (1U) //!< Bit field size in bits for FTM_SYNCONF_INVC.
bogdanm 82:6473597d706e 5280
bogdanm 82:6473597d706e 5281 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5282 //! @brief Read current value of the FTM_SYNCONF_INVC field.
bogdanm 82:6473597d706e 5283 #define BR_FTM_SYNCONF_INVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC))
bogdanm 82:6473597d706e 5284 #endif
bogdanm 82:6473597d706e 5285
bogdanm 82:6473597d706e 5286 //! @brief Format value for bitfield FTM_SYNCONF_INVC.
bogdanm 82:6473597d706e 5287 #define BF_FTM_SYNCONF_INVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_INVC), uint32_t) & BM_FTM_SYNCONF_INVC)
bogdanm 82:6473597d706e 5288
bogdanm 82:6473597d706e 5289 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5290 //! @brief Set the INVC field to a new value.
bogdanm 82:6473597d706e 5291 #define BW_FTM_SYNCONF_INVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC) = (v))
bogdanm 82:6473597d706e 5292 #endif
bogdanm 82:6473597d706e 5293 //@}
bogdanm 82:6473597d706e 5294
bogdanm 82:6473597d706e 5295 /*!
bogdanm 82:6473597d706e 5296 * @name Register FTM_SYNCONF, field SWOC[5] (RW)
bogdanm 82:6473597d706e 5297 *
bogdanm 82:6473597d706e 5298 * Values:
bogdanm 82:6473597d706e 5299 * - 0 - SWOCTRL register is updated with its buffer value at all rising edges
bogdanm 82:6473597d706e 5300 * of system clock.
bogdanm 82:6473597d706e 5301 * - 1 - SWOCTRL register is updated with its buffer value by the PWM
bogdanm 82:6473597d706e 5302 * synchronization.
bogdanm 82:6473597d706e 5303 */
bogdanm 82:6473597d706e 5304 //@{
bogdanm 82:6473597d706e 5305 #define BP_FTM_SYNCONF_SWOC (5U) //!< Bit position for FTM_SYNCONF_SWOC.
bogdanm 82:6473597d706e 5306 #define BM_FTM_SYNCONF_SWOC (0x00000020U) //!< Bit mask for FTM_SYNCONF_SWOC.
bogdanm 82:6473597d706e 5307 #define BS_FTM_SYNCONF_SWOC (1U) //!< Bit field size in bits for FTM_SYNCONF_SWOC.
bogdanm 82:6473597d706e 5308
bogdanm 82:6473597d706e 5309 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5310 //! @brief Read current value of the FTM_SYNCONF_SWOC field.
bogdanm 82:6473597d706e 5311 #define BR_FTM_SYNCONF_SWOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC))
bogdanm 82:6473597d706e 5312 #endif
bogdanm 82:6473597d706e 5313
bogdanm 82:6473597d706e 5314 //! @brief Format value for bitfield FTM_SYNCONF_SWOC.
bogdanm 82:6473597d706e 5315 #define BF_FTM_SYNCONF_SWOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWOC), uint32_t) & BM_FTM_SYNCONF_SWOC)
bogdanm 82:6473597d706e 5316
bogdanm 82:6473597d706e 5317 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5318 //! @brief Set the SWOC field to a new value.
bogdanm 82:6473597d706e 5319 #define BW_FTM_SYNCONF_SWOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC) = (v))
bogdanm 82:6473597d706e 5320 #endif
bogdanm 82:6473597d706e 5321 //@}
bogdanm 82:6473597d706e 5322
bogdanm 82:6473597d706e 5323 /*!
bogdanm 82:6473597d706e 5324 * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
bogdanm 82:6473597d706e 5325 *
bogdanm 82:6473597d706e 5326 * Selects the PWM Synchronization mode.
bogdanm 82:6473597d706e 5327 *
bogdanm 82:6473597d706e 5328 * Values:
bogdanm 82:6473597d706e 5329 * - 0 - Legacy PWM synchronization is selected.
bogdanm 82:6473597d706e 5330 * - 1 - Enhanced PWM synchronization is selected.
bogdanm 82:6473597d706e 5331 */
bogdanm 82:6473597d706e 5332 //@{
bogdanm 82:6473597d706e 5333 #define BP_FTM_SYNCONF_SYNCMODE (7U) //!< Bit position for FTM_SYNCONF_SYNCMODE.
bogdanm 82:6473597d706e 5334 #define BM_FTM_SYNCONF_SYNCMODE (0x00000080U) //!< Bit mask for FTM_SYNCONF_SYNCMODE.
bogdanm 82:6473597d706e 5335 #define BS_FTM_SYNCONF_SYNCMODE (1U) //!< Bit field size in bits for FTM_SYNCONF_SYNCMODE.
bogdanm 82:6473597d706e 5336
bogdanm 82:6473597d706e 5337 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5338 //! @brief Read current value of the FTM_SYNCONF_SYNCMODE field.
bogdanm 82:6473597d706e 5339 #define BR_FTM_SYNCONF_SYNCMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE))
bogdanm 82:6473597d706e 5340 #endif
bogdanm 82:6473597d706e 5341
bogdanm 82:6473597d706e 5342 //! @brief Format value for bitfield FTM_SYNCONF_SYNCMODE.
bogdanm 82:6473597d706e 5343 #define BF_FTM_SYNCONF_SYNCMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SYNCMODE), uint32_t) & BM_FTM_SYNCONF_SYNCMODE)
bogdanm 82:6473597d706e 5344
bogdanm 82:6473597d706e 5345 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5346 //! @brief Set the SYNCMODE field to a new value.
bogdanm 82:6473597d706e 5347 #define BW_FTM_SYNCONF_SYNCMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE) = (v))
bogdanm 82:6473597d706e 5348 #endif
bogdanm 82:6473597d706e 5349 //@}
bogdanm 82:6473597d706e 5350
bogdanm 82:6473597d706e 5351 /*!
bogdanm 82:6473597d706e 5352 * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
bogdanm 82:6473597d706e 5353 *
bogdanm 82:6473597d706e 5354 * FTM counter synchronization is activated by the software trigger.
bogdanm 82:6473597d706e 5355 *
bogdanm 82:6473597d706e 5356 * Values:
bogdanm 82:6473597d706e 5357 * - 0 - The software trigger does not activate the FTM counter synchronization.
bogdanm 82:6473597d706e 5358 * - 1 - The software trigger activates the FTM counter synchronization.
bogdanm 82:6473597d706e 5359 */
bogdanm 82:6473597d706e 5360 //@{
bogdanm 82:6473597d706e 5361 #define BP_FTM_SYNCONF_SWRSTCNT (8U) //!< Bit position for FTM_SYNCONF_SWRSTCNT.
bogdanm 82:6473597d706e 5362 #define BM_FTM_SYNCONF_SWRSTCNT (0x00000100U) //!< Bit mask for FTM_SYNCONF_SWRSTCNT.
bogdanm 82:6473597d706e 5363 #define BS_FTM_SYNCONF_SWRSTCNT (1U) //!< Bit field size in bits for FTM_SYNCONF_SWRSTCNT.
bogdanm 82:6473597d706e 5364
bogdanm 82:6473597d706e 5365 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5366 //! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field.
bogdanm 82:6473597d706e 5367 #define BR_FTM_SYNCONF_SWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT))
bogdanm 82:6473597d706e 5368 #endif
bogdanm 82:6473597d706e 5369
bogdanm 82:6473597d706e 5370 //! @brief Format value for bitfield FTM_SYNCONF_SWRSTCNT.
bogdanm 82:6473597d706e 5371 #define BF_FTM_SYNCONF_SWRSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWRSTCNT), uint32_t) & BM_FTM_SYNCONF_SWRSTCNT)
bogdanm 82:6473597d706e 5372
bogdanm 82:6473597d706e 5373 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5374 //! @brief Set the SWRSTCNT field to a new value.
bogdanm 82:6473597d706e 5375 #define BW_FTM_SYNCONF_SWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT) = (v))
bogdanm 82:6473597d706e 5376 #endif
bogdanm 82:6473597d706e 5377 //@}
bogdanm 82:6473597d706e 5378
bogdanm 82:6473597d706e 5379 /*!
bogdanm 82:6473597d706e 5380 * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
bogdanm 82:6473597d706e 5381 *
bogdanm 82:6473597d706e 5382 * MOD, CNTIN, and CV registers synchronization is activated by the software
bogdanm 82:6473597d706e 5383 * trigger.
bogdanm 82:6473597d706e 5384 *
bogdanm 82:6473597d706e 5385 * Values:
bogdanm 82:6473597d706e 5386 * - 0 - The software trigger does not activate MOD, CNTIN, and CV registers
bogdanm 82:6473597d706e 5387 * synchronization.
bogdanm 82:6473597d706e 5388 * - 1 - The software trigger activates MOD, CNTIN, and CV registers
bogdanm 82:6473597d706e 5389 * synchronization.
bogdanm 82:6473597d706e 5390 */
bogdanm 82:6473597d706e 5391 //@{
bogdanm 82:6473597d706e 5392 #define BP_FTM_SYNCONF_SWWRBUF (9U) //!< Bit position for FTM_SYNCONF_SWWRBUF.
bogdanm 82:6473597d706e 5393 #define BM_FTM_SYNCONF_SWWRBUF (0x00000200U) //!< Bit mask for FTM_SYNCONF_SWWRBUF.
bogdanm 82:6473597d706e 5394 #define BS_FTM_SYNCONF_SWWRBUF (1U) //!< Bit field size in bits for FTM_SYNCONF_SWWRBUF.
bogdanm 82:6473597d706e 5395
bogdanm 82:6473597d706e 5396 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5397 //! @brief Read current value of the FTM_SYNCONF_SWWRBUF field.
bogdanm 82:6473597d706e 5398 #define BR_FTM_SYNCONF_SWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF))
bogdanm 82:6473597d706e 5399 #endif
bogdanm 82:6473597d706e 5400
bogdanm 82:6473597d706e 5401 //! @brief Format value for bitfield FTM_SYNCONF_SWWRBUF.
bogdanm 82:6473597d706e 5402 #define BF_FTM_SYNCONF_SWWRBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWWRBUF), uint32_t) & BM_FTM_SYNCONF_SWWRBUF)
bogdanm 82:6473597d706e 5403
bogdanm 82:6473597d706e 5404 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5405 //! @brief Set the SWWRBUF field to a new value.
bogdanm 82:6473597d706e 5406 #define BW_FTM_SYNCONF_SWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF) = (v))
bogdanm 82:6473597d706e 5407 #endif
bogdanm 82:6473597d706e 5408 //@}
bogdanm 82:6473597d706e 5409
bogdanm 82:6473597d706e 5410 /*!
bogdanm 82:6473597d706e 5411 * @name Register FTM_SYNCONF, field SWOM[10] (RW)
bogdanm 82:6473597d706e 5412 *
bogdanm 82:6473597d706e 5413 * Output mask synchronization is activated by the software trigger.
bogdanm 82:6473597d706e 5414 *
bogdanm 82:6473597d706e 5415 * Values:
bogdanm 82:6473597d706e 5416 * - 0 - The software trigger does not activate the OUTMASK register
bogdanm 82:6473597d706e 5417 * synchronization.
bogdanm 82:6473597d706e 5418 * - 1 - The software trigger activates the OUTMASK register synchronization.
bogdanm 82:6473597d706e 5419 */
bogdanm 82:6473597d706e 5420 //@{
bogdanm 82:6473597d706e 5421 #define BP_FTM_SYNCONF_SWOM (10U) //!< Bit position for FTM_SYNCONF_SWOM.
bogdanm 82:6473597d706e 5422 #define BM_FTM_SYNCONF_SWOM (0x00000400U) //!< Bit mask for FTM_SYNCONF_SWOM.
bogdanm 82:6473597d706e 5423 #define BS_FTM_SYNCONF_SWOM (1U) //!< Bit field size in bits for FTM_SYNCONF_SWOM.
bogdanm 82:6473597d706e 5424
bogdanm 82:6473597d706e 5425 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5426 //! @brief Read current value of the FTM_SYNCONF_SWOM field.
bogdanm 82:6473597d706e 5427 #define BR_FTM_SYNCONF_SWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM))
bogdanm 82:6473597d706e 5428 #endif
bogdanm 82:6473597d706e 5429
bogdanm 82:6473597d706e 5430 //! @brief Format value for bitfield FTM_SYNCONF_SWOM.
bogdanm 82:6473597d706e 5431 #define BF_FTM_SYNCONF_SWOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWOM), uint32_t) & BM_FTM_SYNCONF_SWOM)
bogdanm 82:6473597d706e 5432
bogdanm 82:6473597d706e 5433 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5434 //! @brief Set the SWOM field to a new value.
bogdanm 82:6473597d706e 5435 #define BW_FTM_SYNCONF_SWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM) = (v))
bogdanm 82:6473597d706e 5436 #endif
bogdanm 82:6473597d706e 5437 //@}
bogdanm 82:6473597d706e 5438
bogdanm 82:6473597d706e 5439 /*!
bogdanm 82:6473597d706e 5440 * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
bogdanm 82:6473597d706e 5441 *
bogdanm 82:6473597d706e 5442 * Inverting control synchronization is activated by the software trigger.
bogdanm 82:6473597d706e 5443 *
bogdanm 82:6473597d706e 5444 * Values:
bogdanm 82:6473597d706e 5445 * - 0 - The software trigger does not activate the INVCTRL register
bogdanm 82:6473597d706e 5446 * synchronization.
bogdanm 82:6473597d706e 5447 * - 1 - The software trigger activates the INVCTRL register synchronization.
bogdanm 82:6473597d706e 5448 */
bogdanm 82:6473597d706e 5449 //@{
bogdanm 82:6473597d706e 5450 #define BP_FTM_SYNCONF_SWINVC (11U) //!< Bit position for FTM_SYNCONF_SWINVC.
bogdanm 82:6473597d706e 5451 #define BM_FTM_SYNCONF_SWINVC (0x00000800U) //!< Bit mask for FTM_SYNCONF_SWINVC.
bogdanm 82:6473597d706e 5452 #define BS_FTM_SYNCONF_SWINVC (1U) //!< Bit field size in bits for FTM_SYNCONF_SWINVC.
bogdanm 82:6473597d706e 5453
bogdanm 82:6473597d706e 5454 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5455 //! @brief Read current value of the FTM_SYNCONF_SWINVC field.
bogdanm 82:6473597d706e 5456 #define BR_FTM_SYNCONF_SWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC))
bogdanm 82:6473597d706e 5457 #endif
bogdanm 82:6473597d706e 5458
bogdanm 82:6473597d706e 5459 //! @brief Format value for bitfield FTM_SYNCONF_SWINVC.
bogdanm 82:6473597d706e 5460 #define BF_FTM_SYNCONF_SWINVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWINVC), uint32_t) & BM_FTM_SYNCONF_SWINVC)
bogdanm 82:6473597d706e 5461
bogdanm 82:6473597d706e 5462 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5463 //! @brief Set the SWINVC field to a new value.
bogdanm 82:6473597d706e 5464 #define BW_FTM_SYNCONF_SWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC) = (v))
bogdanm 82:6473597d706e 5465 #endif
bogdanm 82:6473597d706e 5466 //@}
bogdanm 82:6473597d706e 5467
bogdanm 82:6473597d706e 5468 /*!
bogdanm 82:6473597d706e 5469 * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
bogdanm 82:6473597d706e 5470 *
bogdanm 82:6473597d706e 5471 * Software output control synchronization is activated by the software trigger.
bogdanm 82:6473597d706e 5472 *
bogdanm 82:6473597d706e 5473 * Values:
bogdanm 82:6473597d706e 5474 * - 0 - The software trigger does not activate the SWOCTRL register
bogdanm 82:6473597d706e 5475 * synchronization.
bogdanm 82:6473597d706e 5476 * - 1 - The software trigger activates the SWOCTRL register synchronization.
bogdanm 82:6473597d706e 5477 */
bogdanm 82:6473597d706e 5478 //@{
bogdanm 82:6473597d706e 5479 #define BP_FTM_SYNCONF_SWSOC (12U) //!< Bit position for FTM_SYNCONF_SWSOC.
bogdanm 82:6473597d706e 5480 #define BM_FTM_SYNCONF_SWSOC (0x00001000U) //!< Bit mask for FTM_SYNCONF_SWSOC.
bogdanm 82:6473597d706e 5481 #define BS_FTM_SYNCONF_SWSOC (1U) //!< Bit field size in bits for FTM_SYNCONF_SWSOC.
bogdanm 82:6473597d706e 5482
bogdanm 82:6473597d706e 5483 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5484 //! @brief Read current value of the FTM_SYNCONF_SWSOC field.
bogdanm 82:6473597d706e 5485 #define BR_FTM_SYNCONF_SWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC))
bogdanm 82:6473597d706e 5486 #endif
bogdanm 82:6473597d706e 5487
bogdanm 82:6473597d706e 5488 //! @brief Format value for bitfield FTM_SYNCONF_SWSOC.
bogdanm 82:6473597d706e 5489 #define BF_FTM_SYNCONF_SWSOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWSOC), uint32_t) & BM_FTM_SYNCONF_SWSOC)
bogdanm 82:6473597d706e 5490
bogdanm 82:6473597d706e 5491 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5492 //! @brief Set the SWSOC field to a new value.
bogdanm 82:6473597d706e 5493 #define BW_FTM_SYNCONF_SWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC) = (v))
bogdanm 82:6473597d706e 5494 #endif
bogdanm 82:6473597d706e 5495 //@}
bogdanm 82:6473597d706e 5496
bogdanm 82:6473597d706e 5497 /*!
bogdanm 82:6473597d706e 5498 * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
bogdanm 82:6473597d706e 5499 *
bogdanm 82:6473597d706e 5500 * FTM counter synchronization is activated by a hardware trigger.
bogdanm 82:6473597d706e 5501 *
bogdanm 82:6473597d706e 5502 * Values:
bogdanm 82:6473597d706e 5503 * - 0 - A hardware trigger does not activate the FTM counter synchronization.
bogdanm 82:6473597d706e 5504 * - 1 - A hardware trigger activates the FTM counter synchronization.
bogdanm 82:6473597d706e 5505 */
bogdanm 82:6473597d706e 5506 //@{
bogdanm 82:6473597d706e 5507 #define BP_FTM_SYNCONF_HWRSTCNT (16U) //!< Bit position for FTM_SYNCONF_HWRSTCNT.
bogdanm 82:6473597d706e 5508 #define BM_FTM_SYNCONF_HWRSTCNT (0x00010000U) //!< Bit mask for FTM_SYNCONF_HWRSTCNT.
bogdanm 82:6473597d706e 5509 #define BS_FTM_SYNCONF_HWRSTCNT (1U) //!< Bit field size in bits for FTM_SYNCONF_HWRSTCNT.
bogdanm 82:6473597d706e 5510
bogdanm 82:6473597d706e 5511 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5512 //! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field.
bogdanm 82:6473597d706e 5513 #define BR_FTM_SYNCONF_HWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT))
bogdanm 82:6473597d706e 5514 #endif
bogdanm 82:6473597d706e 5515
bogdanm 82:6473597d706e 5516 //! @brief Format value for bitfield FTM_SYNCONF_HWRSTCNT.
bogdanm 82:6473597d706e 5517 #define BF_FTM_SYNCONF_HWRSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWRSTCNT), uint32_t) & BM_FTM_SYNCONF_HWRSTCNT)
bogdanm 82:6473597d706e 5518
bogdanm 82:6473597d706e 5519 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5520 //! @brief Set the HWRSTCNT field to a new value.
bogdanm 82:6473597d706e 5521 #define BW_FTM_SYNCONF_HWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT) = (v))
bogdanm 82:6473597d706e 5522 #endif
bogdanm 82:6473597d706e 5523 //@}
bogdanm 82:6473597d706e 5524
bogdanm 82:6473597d706e 5525 /*!
bogdanm 82:6473597d706e 5526 * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
bogdanm 82:6473597d706e 5527 *
bogdanm 82:6473597d706e 5528 * MOD, CNTIN, and CV registers synchronization is activated by a hardware
bogdanm 82:6473597d706e 5529 * trigger.
bogdanm 82:6473597d706e 5530 *
bogdanm 82:6473597d706e 5531 * Values:
bogdanm 82:6473597d706e 5532 * - 0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
bogdanm 82:6473597d706e 5533 * synchronization.
bogdanm 82:6473597d706e 5534 * - 1 - A hardware trigger activates MOD, CNTIN, and CV registers
bogdanm 82:6473597d706e 5535 * synchronization.
bogdanm 82:6473597d706e 5536 */
bogdanm 82:6473597d706e 5537 //@{
bogdanm 82:6473597d706e 5538 #define BP_FTM_SYNCONF_HWWRBUF (17U) //!< Bit position for FTM_SYNCONF_HWWRBUF.
bogdanm 82:6473597d706e 5539 #define BM_FTM_SYNCONF_HWWRBUF (0x00020000U) //!< Bit mask for FTM_SYNCONF_HWWRBUF.
bogdanm 82:6473597d706e 5540 #define BS_FTM_SYNCONF_HWWRBUF (1U) //!< Bit field size in bits for FTM_SYNCONF_HWWRBUF.
bogdanm 82:6473597d706e 5541
bogdanm 82:6473597d706e 5542 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5543 //! @brief Read current value of the FTM_SYNCONF_HWWRBUF field.
bogdanm 82:6473597d706e 5544 #define BR_FTM_SYNCONF_HWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF))
bogdanm 82:6473597d706e 5545 #endif
bogdanm 82:6473597d706e 5546
bogdanm 82:6473597d706e 5547 //! @brief Format value for bitfield FTM_SYNCONF_HWWRBUF.
bogdanm 82:6473597d706e 5548 #define BF_FTM_SYNCONF_HWWRBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWWRBUF), uint32_t) & BM_FTM_SYNCONF_HWWRBUF)
bogdanm 82:6473597d706e 5549
bogdanm 82:6473597d706e 5550 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5551 //! @brief Set the HWWRBUF field to a new value.
bogdanm 82:6473597d706e 5552 #define BW_FTM_SYNCONF_HWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF) = (v))
bogdanm 82:6473597d706e 5553 #endif
bogdanm 82:6473597d706e 5554 //@}
bogdanm 82:6473597d706e 5555
bogdanm 82:6473597d706e 5556 /*!
bogdanm 82:6473597d706e 5557 * @name Register FTM_SYNCONF, field HWOM[18] (RW)
bogdanm 82:6473597d706e 5558 *
bogdanm 82:6473597d706e 5559 * Output mask synchronization is activated by a hardware trigger.
bogdanm 82:6473597d706e 5560 *
bogdanm 82:6473597d706e 5561 * Values:
bogdanm 82:6473597d706e 5562 * - 0 - A hardware trigger does not activate the OUTMASK register
bogdanm 82:6473597d706e 5563 * synchronization.
bogdanm 82:6473597d706e 5564 * - 1 - A hardware trigger activates the OUTMASK register synchronization.
bogdanm 82:6473597d706e 5565 */
bogdanm 82:6473597d706e 5566 //@{
bogdanm 82:6473597d706e 5567 #define BP_FTM_SYNCONF_HWOM (18U) //!< Bit position for FTM_SYNCONF_HWOM.
bogdanm 82:6473597d706e 5568 #define BM_FTM_SYNCONF_HWOM (0x00040000U) //!< Bit mask for FTM_SYNCONF_HWOM.
bogdanm 82:6473597d706e 5569 #define BS_FTM_SYNCONF_HWOM (1U) //!< Bit field size in bits for FTM_SYNCONF_HWOM.
bogdanm 82:6473597d706e 5570
bogdanm 82:6473597d706e 5571 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5572 //! @brief Read current value of the FTM_SYNCONF_HWOM field.
bogdanm 82:6473597d706e 5573 #define BR_FTM_SYNCONF_HWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM))
bogdanm 82:6473597d706e 5574 #endif
bogdanm 82:6473597d706e 5575
bogdanm 82:6473597d706e 5576 //! @brief Format value for bitfield FTM_SYNCONF_HWOM.
bogdanm 82:6473597d706e 5577 #define BF_FTM_SYNCONF_HWOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWOM), uint32_t) & BM_FTM_SYNCONF_HWOM)
bogdanm 82:6473597d706e 5578
bogdanm 82:6473597d706e 5579 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5580 //! @brief Set the HWOM field to a new value.
bogdanm 82:6473597d706e 5581 #define BW_FTM_SYNCONF_HWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM) = (v))
bogdanm 82:6473597d706e 5582 #endif
bogdanm 82:6473597d706e 5583 //@}
bogdanm 82:6473597d706e 5584
bogdanm 82:6473597d706e 5585 /*!
bogdanm 82:6473597d706e 5586 * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
bogdanm 82:6473597d706e 5587 *
bogdanm 82:6473597d706e 5588 * Inverting control synchronization is activated by a hardware trigger.
bogdanm 82:6473597d706e 5589 *
bogdanm 82:6473597d706e 5590 * Values:
bogdanm 82:6473597d706e 5591 * - 0 - A hardware trigger does not activate the INVCTRL register
bogdanm 82:6473597d706e 5592 * synchronization.
bogdanm 82:6473597d706e 5593 * - 1 - A hardware trigger activates the INVCTRL register synchronization.
bogdanm 82:6473597d706e 5594 */
bogdanm 82:6473597d706e 5595 //@{
bogdanm 82:6473597d706e 5596 #define BP_FTM_SYNCONF_HWINVC (19U) //!< Bit position for FTM_SYNCONF_HWINVC.
bogdanm 82:6473597d706e 5597 #define BM_FTM_SYNCONF_HWINVC (0x00080000U) //!< Bit mask for FTM_SYNCONF_HWINVC.
bogdanm 82:6473597d706e 5598 #define BS_FTM_SYNCONF_HWINVC (1U) //!< Bit field size in bits for FTM_SYNCONF_HWINVC.
bogdanm 82:6473597d706e 5599
bogdanm 82:6473597d706e 5600 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5601 //! @brief Read current value of the FTM_SYNCONF_HWINVC field.
bogdanm 82:6473597d706e 5602 #define BR_FTM_SYNCONF_HWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC))
bogdanm 82:6473597d706e 5603 #endif
bogdanm 82:6473597d706e 5604
bogdanm 82:6473597d706e 5605 //! @brief Format value for bitfield FTM_SYNCONF_HWINVC.
bogdanm 82:6473597d706e 5606 #define BF_FTM_SYNCONF_HWINVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWINVC), uint32_t) & BM_FTM_SYNCONF_HWINVC)
bogdanm 82:6473597d706e 5607
bogdanm 82:6473597d706e 5608 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5609 //! @brief Set the HWINVC field to a new value.
bogdanm 82:6473597d706e 5610 #define BW_FTM_SYNCONF_HWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC) = (v))
bogdanm 82:6473597d706e 5611 #endif
bogdanm 82:6473597d706e 5612 //@}
bogdanm 82:6473597d706e 5613
bogdanm 82:6473597d706e 5614 /*!
bogdanm 82:6473597d706e 5615 * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
bogdanm 82:6473597d706e 5616 *
bogdanm 82:6473597d706e 5617 * Software output control synchronization is activated by a hardware trigger.
bogdanm 82:6473597d706e 5618 *
bogdanm 82:6473597d706e 5619 * Values:
bogdanm 82:6473597d706e 5620 * - 0 - A hardware trigger does not activate the SWOCTRL register
bogdanm 82:6473597d706e 5621 * synchronization.
bogdanm 82:6473597d706e 5622 * - 1 - A hardware trigger activates the SWOCTRL register synchronization.
bogdanm 82:6473597d706e 5623 */
bogdanm 82:6473597d706e 5624 //@{
bogdanm 82:6473597d706e 5625 #define BP_FTM_SYNCONF_HWSOC (20U) //!< Bit position for FTM_SYNCONF_HWSOC.
bogdanm 82:6473597d706e 5626 #define BM_FTM_SYNCONF_HWSOC (0x00100000U) //!< Bit mask for FTM_SYNCONF_HWSOC.
bogdanm 82:6473597d706e 5627 #define BS_FTM_SYNCONF_HWSOC (1U) //!< Bit field size in bits for FTM_SYNCONF_HWSOC.
bogdanm 82:6473597d706e 5628
bogdanm 82:6473597d706e 5629 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5630 //! @brief Read current value of the FTM_SYNCONF_HWSOC field.
bogdanm 82:6473597d706e 5631 #define BR_FTM_SYNCONF_HWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC))
bogdanm 82:6473597d706e 5632 #endif
bogdanm 82:6473597d706e 5633
bogdanm 82:6473597d706e 5634 //! @brief Format value for bitfield FTM_SYNCONF_HWSOC.
bogdanm 82:6473597d706e 5635 #define BF_FTM_SYNCONF_HWSOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWSOC), uint32_t) & BM_FTM_SYNCONF_HWSOC)
bogdanm 82:6473597d706e 5636
bogdanm 82:6473597d706e 5637 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5638 //! @brief Set the HWSOC field to a new value.
bogdanm 82:6473597d706e 5639 #define BW_FTM_SYNCONF_HWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC) = (v))
bogdanm 82:6473597d706e 5640 #endif
bogdanm 82:6473597d706e 5641 //@}
bogdanm 82:6473597d706e 5642
bogdanm 82:6473597d706e 5643 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5644 // HW_FTM_INVCTRL - FTM Inverting Control
bogdanm 82:6473597d706e 5645 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5646
bogdanm 82:6473597d706e 5647 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5648 /*!
bogdanm 82:6473597d706e 5649 * @brief HW_FTM_INVCTRL - FTM Inverting Control (RW)
bogdanm 82:6473597d706e 5650 *
bogdanm 82:6473597d706e 5651 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 5652 *
bogdanm 82:6473597d706e 5653 * This register controls when the channel (n) output becomes the channel (n+1)
bogdanm 82:6473597d706e 5654 * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
bogdanm 82:6473597d706e 5655 * bit enables the inverting operation for the corresponding pair channels m. This
bogdanm 82:6473597d706e 5656 * register has a write buffer. The INVmEN bit is updated by the INVCTRL
bogdanm 82:6473597d706e 5657 * register synchronization.
bogdanm 82:6473597d706e 5658 */
bogdanm 82:6473597d706e 5659 typedef union _hw_ftm_invctrl
bogdanm 82:6473597d706e 5660 {
bogdanm 82:6473597d706e 5661 uint32_t U;
bogdanm 82:6473597d706e 5662 struct _hw_ftm_invctrl_bitfields
bogdanm 82:6473597d706e 5663 {
bogdanm 82:6473597d706e 5664 uint32_t INV0EN : 1; //!< [0] Pair Channels 0 Inverting Enable
bogdanm 82:6473597d706e 5665 uint32_t INV1EN : 1; //!< [1] Pair Channels 1 Inverting Enable
bogdanm 82:6473597d706e 5666 uint32_t INV2EN : 1; //!< [2] Pair Channels 2 Inverting Enable
bogdanm 82:6473597d706e 5667 uint32_t INV3EN : 1; //!< [3] Pair Channels 3 Inverting Enable
bogdanm 82:6473597d706e 5668 uint32_t RESERVED0 : 28; //!< [31:4]
bogdanm 82:6473597d706e 5669 } B;
bogdanm 82:6473597d706e 5670 } hw_ftm_invctrl_t;
bogdanm 82:6473597d706e 5671 #endif
bogdanm 82:6473597d706e 5672
bogdanm 82:6473597d706e 5673 /*!
bogdanm 82:6473597d706e 5674 * @name Constants and macros for entire FTM_INVCTRL register
bogdanm 82:6473597d706e 5675 */
bogdanm 82:6473597d706e 5676 //@{
bogdanm 82:6473597d706e 5677 #define HW_FTM_INVCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x90U)
bogdanm 82:6473597d706e 5678
bogdanm 82:6473597d706e 5679 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5680 #define HW_FTM_INVCTRL(x) (*(__IO hw_ftm_invctrl_t *) HW_FTM_INVCTRL_ADDR(x))
bogdanm 82:6473597d706e 5681 #define HW_FTM_INVCTRL_RD(x) (HW_FTM_INVCTRL(x).U)
bogdanm 82:6473597d706e 5682 #define HW_FTM_INVCTRL_WR(x, v) (HW_FTM_INVCTRL(x).U = (v))
bogdanm 82:6473597d706e 5683 #define HW_FTM_INVCTRL_SET(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) | (v)))
bogdanm 82:6473597d706e 5684 #define HW_FTM_INVCTRL_CLR(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) & ~(v)))
bogdanm 82:6473597d706e 5685 #define HW_FTM_INVCTRL_TOG(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) ^ (v)))
bogdanm 82:6473597d706e 5686 #endif
bogdanm 82:6473597d706e 5687 //@}
bogdanm 82:6473597d706e 5688
bogdanm 82:6473597d706e 5689 /*
bogdanm 82:6473597d706e 5690 * Constants & macros for individual FTM_INVCTRL bitfields
bogdanm 82:6473597d706e 5691 */
bogdanm 82:6473597d706e 5692
bogdanm 82:6473597d706e 5693 /*!
bogdanm 82:6473597d706e 5694 * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
bogdanm 82:6473597d706e 5695 *
bogdanm 82:6473597d706e 5696 * Values:
bogdanm 82:6473597d706e 5697 * - 0 - Inverting is disabled.
bogdanm 82:6473597d706e 5698 * - 1 - Inverting is enabled.
bogdanm 82:6473597d706e 5699 */
bogdanm 82:6473597d706e 5700 //@{
bogdanm 82:6473597d706e 5701 #define BP_FTM_INVCTRL_INV0EN (0U) //!< Bit position for FTM_INVCTRL_INV0EN.
bogdanm 82:6473597d706e 5702 #define BM_FTM_INVCTRL_INV0EN (0x00000001U) //!< Bit mask for FTM_INVCTRL_INV0EN.
bogdanm 82:6473597d706e 5703 #define BS_FTM_INVCTRL_INV0EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV0EN.
bogdanm 82:6473597d706e 5704
bogdanm 82:6473597d706e 5705 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5706 //! @brief Read current value of the FTM_INVCTRL_INV0EN field.
bogdanm 82:6473597d706e 5707 #define BR_FTM_INVCTRL_INV0EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN))
bogdanm 82:6473597d706e 5708 #endif
bogdanm 82:6473597d706e 5709
bogdanm 82:6473597d706e 5710 //! @brief Format value for bitfield FTM_INVCTRL_INV0EN.
bogdanm 82:6473597d706e 5711 #define BF_FTM_INVCTRL_INV0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV0EN), uint32_t) & BM_FTM_INVCTRL_INV0EN)
bogdanm 82:6473597d706e 5712
bogdanm 82:6473597d706e 5713 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5714 //! @brief Set the INV0EN field to a new value.
bogdanm 82:6473597d706e 5715 #define BW_FTM_INVCTRL_INV0EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN) = (v))
bogdanm 82:6473597d706e 5716 #endif
bogdanm 82:6473597d706e 5717 //@}
bogdanm 82:6473597d706e 5718
bogdanm 82:6473597d706e 5719 /*!
bogdanm 82:6473597d706e 5720 * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
bogdanm 82:6473597d706e 5721 *
bogdanm 82:6473597d706e 5722 * Values:
bogdanm 82:6473597d706e 5723 * - 0 - Inverting is disabled.
bogdanm 82:6473597d706e 5724 * - 1 - Inverting is enabled.
bogdanm 82:6473597d706e 5725 */
bogdanm 82:6473597d706e 5726 //@{
bogdanm 82:6473597d706e 5727 #define BP_FTM_INVCTRL_INV1EN (1U) //!< Bit position for FTM_INVCTRL_INV1EN.
bogdanm 82:6473597d706e 5728 #define BM_FTM_INVCTRL_INV1EN (0x00000002U) //!< Bit mask for FTM_INVCTRL_INV1EN.
bogdanm 82:6473597d706e 5729 #define BS_FTM_INVCTRL_INV1EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV1EN.
bogdanm 82:6473597d706e 5730
bogdanm 82:6473597d706e 5731 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5732 //! @brief Read current value of the FTM_INVCTRL_INV1EN field.
bogdanm 82:6473597d706e 5733 #define BR_FTM_INVCTRL_INV1EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN))
bogdanm 82:6473597d706e 5734 #endif
bogdanm 82:6473597d706e 5735
bogdanm 82:6473597d706e 5736 //! @brief Format value for bitfield FTM_INVCTRL_INV1EN.
bogdanm 82:6473597d706e 5737 #define BF_FTM_INVCTRL_INV1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV1EN), uint32_t) & BM_FTM_INVCTRL_INV1EN)
bogdanm 82:6473597d706e 5738
bogdanm 82:6473597d706e 5739 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5740 //! @brief Set the INV1EN field to a new value.
bogdanm 82:6473597d706e 5741 #define BW_FTM_INVCTRL_INV1EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN) = (v))
bogdanm 82:6473597d706e 5742 #endif
bogdanm 82:6473597d706e 5743 //@}
bogdanm 82:6473597d706e 5744
bogdanm 82:6473597d706e 5745 /*!
bogdanm 82:6473597d706e 5746 * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
bogdanm 82:6473597d706e 5747 *
bogdanm 82:6473597d706e 5748 * Values:
bogdanm 82:6473597d706e 5749 * - 0 - Inverting is disabled.
bogdanm 82:6473597d706e 5750 * - 1 - Inverting is enabled.
bogdanm 82:6473597d706e 5751 */
bogdanm 82:6473597d706e 5752 //@{
bogdanm 82:6473597d706e 5753 #define BP_FTM_INVCTRL_INV2EN (2U) //!< Bit position for FTM_INVCTRL_INV2EN.
bogdanm 82:6473597d706e 5754 #define BM_FTM_INVCTRL_INV2EN (0x00000004U) //!< Bit mask for FTM_INVCTRL_INV2EN.
bogdanm 82:6473597d706e 5755 #define BS_FTM_INVCTRL_INV2EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV2EN.
bogdanm 82:6473597d706e 5756
bogdanm 82:6473597d706e 5757 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5758 //! @brief Read current value of the FTM_INVCTRL_INV2EN field.
bogdanm 82:6473597d706e 5759 #define BR_FTM_INVCTRL_INV2EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN))
bogdanm 82:6473597d706e 5760 #endif
bogdanm 82:6473597d706e 5761
bogdanm 82:6473597d706e 5762 //! @brief Format value for bitfield FTM_INVCTRL_INV2EN.
bogdanm 82:6473597d706e 5763 #define BF_FTM_INVCTRL_INV2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV2EN), uint32_t) & BM_FTM_INVCTRL_INV2EN)
bogdanm 82:6473597d706e 5764
bogdanm 82:6473597d706e 5765 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5766 //! @brief Set the INV2EN field to a new value.
bogdanm 82:6473597d706e 5767 #define BW_FTM_INVCTRL_INV2EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN) = (v))
bogdanm 82:6473597d706e 5768 #endif
bogdanm 82:6473597d706e 5769 //@}
bogdanm 82:6473597d706e 5770
bogdanm 82:6473597d706e 5771 /*!
bogdanm 82:6473597d706e 5772 * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
bogdanm 82:6473597d706e 5773 *
bogdanm 82:6473597d706e 5774 * Values:
bogdanm 82:6473597d706e 5775 * - 0 - Inverting is disabled.
bogdanm 82:6473597d706e 5776 * - 1 - Inverting is enabled.
bogdanm 82:6473597d706e 5777 */
bogdanm 82:6473597d706e 5778 //@{
bogdanm 82:6473597d706e 5779 #define BP_FTM_INVCTRL_INV3EN (3U) //!< Bit position for FTM_INVCTRL_INV3EN.
bogdanm 82:6473597d706e 5780 #define BM_FTM_INVCTRL_INV3EN (0x00000008U) //!< Bit mask for FTM_INVCTRL_INV3EN.
bogdanm 82:6473597d706e 5781 #define BS_FTM_INVCTRL_INV3EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV3EN.
bogdanm 82:6473597d706e 5782
bogdanm 82:6473597d706e 5783 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5784 //! @brief Read current value of the FTM_INVCTRL_INV3EN field.
bogdanm 82:6473597d706e 5785 #define BR_FTM_INVCTRL_INV3EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN))
bogdanm 82:6473597d706e 5786 #endif
bogdanm 82:6473597d706e 5787
bogdanm 82:6473597d706e 5788 //! @brief Format value for bitfield FTM_INVCTRL_INV3EN.
bogdanm 82:6473597d706e 5789 #define BF_FTM_INVCTRL_INV3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV3EN), uint32_t) & BM_FTM_INVCTRL_INV3EN)
bogdanm 82:6473597d706e 5790
bogdanm 82:6473597d706e 5791 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5792 //! @brief Set the INV3EN field to a new value.
bogdanm 82:6473597d706e 5793 #define BW_FTM_INVCTRL_INV3EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN) = (v))
bogdanm 82:6473597d706e 5794 #endif
bogdanm 82:6473597d706e 5795 //@}
bogdanm 82:6473597d706e 5796
bogdanm 82:6473597d706e 5797 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5798 // HW_FTM_SWOCTRL - FTM Software Output Control
bogdanm 82:6473597d706e 5799 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5800
bogdanm 82:6473597d706e 5801 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5802 /*!
bogdanm 82:6473597d706e 5803 * @brief HW_FTM_SWOCTRL - FTM Software Output Control (RW)
bogdanm 82:6473597d706e 5804 *
bogdanm 82:6473597d706e 5805 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 5806 *
bogdanm 82:6473597d706e 5807 * This register enables software control of channel (n) output and defines the
bogdanm 82:6473597d706e 5808 * value forced to the channel (n) output: The CHnOC bits enable the control of
bogdanm 82:6473597d706e 5809 * the corresponding channel (n) output by software. The CHnOCV bits select the
bogdanm 82:6473597d706e 5810 * value that is forced at the corresponding channel (n) output. This register has
bogdanm 82:6473597d706e 5811 * a write buffer. The fields are updated by the SWOCTRL register synchronization.
bogdanm 82:6473597d706e 5812 */
bogdanm 82:6473597d706e 5813 typedef union _hw_ftm_swoctrl
bogdanm 82:6473597d706e 5814 {
bogdanm 82:6473597d706e 5815 uint32_t U;
bogdanm 82:6473597d706e 5816 struct _hw_ftm_swoctrl_bitfields
bogdanm 82:6473597d706e 5817 {
bogdanm 82:6473597d706e 5818 uint32_t CH0OC : 1; //!< [0] Channel 0 Software Output Control Enable
bogdanm 82:6473597d706e 5819 uint32_t CH1OC : 1; //!< [1] Channel 1 Software Output Control Enable
bogdanm 82:6473597d706e 5820 uint32_t CH2OC : 1; //!< [2] Channel 2 Software Output Control Enable
bogdanm 82:6473597d706e 5821 uint32_t CH3OC : 1; //!< [3] Channel 3 Software Output Control Enable
bogdanm 82:6473597d706e 5822 uint32_t CH4OC : 1; //!< [4] Channel 4 Software Output Control Enable
bogdanm 82:6473597d706e 5823 uint32_t CH5OC : 1; //!< [5] Channel 5 Software Output Control Enable
bogdanm 82:6473597d706e 5824 uint32_t CH6OC : 1; //!< [6] Channel 6 Software Output Control Enable
bogdanm 82:6473597d706e 5825 uint32_t CH7OC : 1; //!< [7] Channel 7 Software Output Control Enable
bogdanm 82:6473597d706e 5826 uint32_t CH0OCV : 1; //!< [8] Channel 0 Software Output Control Value
bogdanm 82:6473597d706e 5827 uint32_t CH1OCV : 1; //!< [9] Channel 1 Software Output Control Value
bogdanm 82:6473597d706e 5828 uint32_t CH2OCV : 1; //!< [10] Channel 2 Software Output Control Value
bogdanm 82:6473597d706e 5829 uint32_t CH3OCV : 1; //!< [11] Channel 3 Software Output Control Value
bogdanm 82:6473597d706e 5830 uint32_t CH4OCV : 1; //!< [12] Channel 4 Software Output Control Value
bogdanm 82:6473597d706e 5831 uint32_t CH5OCV : 1; //!< [13] Channel 5 Software Output Control Value
bogdanm 82:6473597d706e 5832 uint32_t CH6OCV : 1; //!< [14] Channel 6 Software Output Control Value
bogdanm 82:6473597d706e 5833 uint32_t CH7OCV : 1; //!< [15] Channel 7 Software Output Control Value
bogdanm 82:6473597d706e 5834 uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm 82:6473597d706e 5835 } B;
bogdanm 82:6473597d706e 5836 } hw_ftm_swoctrl_t;
bogdanm 82:6473597d706e 5837 #endif
bogdanm 82:6473597d706e 5838
bogdanm 82:6473597d706e 5839 /*!
bogdanm 82:6473597d706e 5840 * @name Constants and macros for entire FTM_SWOCTRL register
bogdanm 82:6473597d706e 5841 */
bogdanm 82:6473597d706e 5842 //@{
bogdanm 82:6473597d706e 5843 #define HW_FTM_SWOCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x94U)
bogdanm 82:6473597d706e 5844
bogdanm 82:6473597d706e 5845 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5846 #define HW_FTM_SWOCTRL(x) (*(__IO hw_ftm_swoctrl_t *) HW_FTM_SWOCTRL_ADDR(x))
bogdanm 82:6473597d706e 5847 #define HW_FTM_SWOCTRL_RD(x) (HW_FTM_SWOCTRL(x).U)
bogdanm 82:6473597d706e 5848 #define HW_FTM_SWOCTRL_WR(x, v) (HW_FTM_SWOCTRL(x).U = (v))
bogdanm 82:6473597d706e 5849 #define HW_FTM_SWOCTRL_SET(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) | (v)))
bogdanm 82:6473597d706e 5850 #define HW_FTM_SWOCTRL_CLR(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) & ~(v)))
bogdanm 82:6473597d706e 5851 #define HW_FTM_SWOCTRL_TOG(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) ^ (v)))
bogdanm 82:6473597d706e 5852 #endif
bogdanm 82:6473597d706e 5853 //@}
bogdanm 82:6473597d706e 5854
bogdanm 82:6473597d706e 5855 /*
bogdanm 82:6473597d706e 5856 * Constants & macros for individual FTM_SWOCTRL bitfields
bogdanm 82:6473597d706e 5857 */
bogdanm 82:6473597d706e 5858
bogdanm 82:6473597d706e 5859 /*!
bogdanm 82:6473597d706e 5860 * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
bogdanm 82:6473597d706e 5861 *
bogdanm 82:6473597d706e 5862 * Values:
bogdanm 82:6473597d706e 5863 * - 0 - The channel output is not affected by software output control.
bogdanm 82:6473597d706e 5864 * - 1 - The channel output is affected by software output control.
bogdanm 82:6473597d706e 5865 */
bogdanm 82:6473597d706e 5866 //@{
bogdanm 82:6473597d706e 5867 #define BP_FTM_SWOCTRL_CH0OC (0U) //!< Bit position for FTM_SWOCTRL_CH0OC.
bogdanm 82:6473597d706e 5868 #define BM_FTM_SWOCTRL_CH0OC (0x00000001U) //!< Bit mask for FTM_SWOCTRL_CH0OC.
bogdanm 82:6473597d706e 5869 #define BS_FTM_SWOCTRL_CH0OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH0OC.
bogdanm 82:6473597d706e 5870
bogdanm 82:6473597d706e 5871 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5872 //! @brief Read current value of the FTM_SWOCTRL_CH0OC field.
bogdanm 82:6473597d706e 5873 #define BR_FTM_SWOCTRL_CH0OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC))
bogdanm 82:6473597d706e 5874 #endif
bogdanm 82:6473597d706e 5875
bogdanm 82:6473597d706e 5876 //! @brief Format value for bitfield FTM_SWOCTRL_CH0OC.
bogdanm 82:6473597d706e 5877 #define BF_FTM_SWOCTRL_CH0OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH0OC), uint32_t) & BM_FTM_SWOCTRL_CH0OC)
bogdanm 82:6473597d706e 5878
bogdanm 82:6473597d706e 5879 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5880 //! @brief Set the CH0OC field to a new value.
bogdanm 82:6473597d706e 5881 #define BW_FTM_SWOCTRL_CH0OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC) = (v))
bogdanm 82:6473597d706e 5882 #endif
bogdanm 82:6473597d706e 5883 //@}
bogdanm 82:6473597d706e 5884
bogdanm 82:6473597d706e 5885 /*!
bogdanm 82:6473597d706e 5886 * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
bogdanm 82:6473597d706e 5887 *
bogdanm 82:6473597d706e 5888 * Values:
bogdanm 82:6473597d706e 5889 * - 0 - The channel output is not affected by software output control.
bogdanm 82:6473597d706e 5890 * - 1 - The channel output is affected by software output control.
bogdanm 82:6473597d706e 5891 */
bogdanm 82:6473597d706e 5892 //@{
bogdanm 82:6473597d706e 5893 #define BP_FTM_SWOCTRL_CH1OC (1U) //!< Bit position for FTM_SWOCTRL_CH1OC.
bogdanm 82:6473597d706e 5894 #define BM_FTM_SWOCTRL_CH1OC (0x00000002U) //!< Bit mask for FTM_SWOCTRL_CH1OC.
bogdanm 82:6473597d706e 5895 #define BS_FTM_SWOCTRL_CH1OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH1OC.
bogdanm 82:6473597d706e 5896
bogdanm 82:6473597d706e 5897 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5898 //! @brief Read current value of the FTM_SWOCTRL_CH1OC field.
bogdanm 82:6473597d706e 5899 #define BR_FTM_SWOCTRL_CH1OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC))
bogdanm 82:6473597d706e 5900 #endif
bogdanm 82:6473597d706e 5901
bogdanm 82:6473597d706e 5902 //! @brief Format value for bitfield FTM_SWOCTRL_CH1OC.
bogdanm 82:6473597d706e 5903 #define BF_FTM_SWOCTRL_CH1OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH1OC), uint32_t) & BM_FTM_SWOCTRL_CH1OC)
bogdanm 82:6473597d706e 5904
bogdanm 82:6473597d706e 5905 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5906 //! @brief Set the CH1OC field to a new value.
bogdanm 82:6473597d706e 5907 #define BW_FTM_SWOCTRL_CH1OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC) = (v))
bogdanm 82:6473597d706e 5908 #endif
bogdanm 82:6473597d706e 5909 //@}
bogdanm 82:6473597d706e 5910
bogdanm 82:6473597d706e 5911 /*!
bogdanm 82:6473597d706e 5912 * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
bogdanm 82:6473597d706e 5913 *
bogdanm 82:6473597d706e 5914 * Values:
bogdanm 82:6473597d706e 5915 * - 0 - The channel output is not affected by software output control.
bogdanm 82:6473597d706e 5916 * - 1 - The channel output is affected by software output control.
bogdanm 82:6473597d706e 5917 */
bogdanm 82:6473597d706e 5918 //@{
bogdanm 82:6473597d706e 5919 #define BP_FTM_SWOCTRL_CH2OC (2U) //!< Bit position for FTM_SWOCTRL_CH2OC.
bogdanm 82:6473597d706e 5920 #define BM_FTM_SWOCTRL_CH2OC (0x00000004U) //!< Bit mask for FTM_SWOCTRL_CH2OC.
bogdanm 82:6473597d706e 5921 #define BS_FTM_SWOCTRL_CH2OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH2OC.
bogdanm 82:6473597d706e 5922
bogdanm 82:6473597d706e 5923 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5924 //! @brief Read current value of the FTM_SWOCTRL_CH2OC field.
bogdanm 82:6473597d706e 5925 #define BR_FTM_SWOCTRL_CH2OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC))
bogdanm 82:6473597d706e 5926 #endif
bogdanm 82:6473597d706e 5927
bogdanm 82:6473597d706e 5928 //! @brief Format value for bitfield FTM_SWOCTRL_CH2OC.
bogdanm 82:6473597d706e 5929 #define BF_FTM_SWOCTRL_CH2OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH2OC), uint32_t) & BM_FTM_SWOCTRL_CH2OC)
bogdanm 82:6473597d706e 5930
bogdanm 82:6473597d706e 5931 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5932 //! @brief Set the CH2OC field to a new value.
bogdanm 82:6473597d706e 5933 #define BW_FTM_SWOCTRL_CH2OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC) = (v))
bogdanm 82:6473597d706e 5934 #endif
bogdanm 82:6473597d706e 5935 //@}
bogdanm 82:6473597d706e 5936
bogdanm 82:6473597d706e 5937 /*!
bogdanm 82:6473597d706e 5938 * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
bogdanm 82:6473597d706e 5939 *
bogdanm 82:6473597d706e 5940 * Values:
bogdanm 82:6473597d706e 5941 * - 0 - The channel output is not affected by software output control.
bogdanm 82:6473597d706e 5942 * - 1 - The channel output is affected by software output control.
bogdanm 82:6473597d706e 5943 */
bogdanm 82:6473597d706e 5944 //@{
bogdanm 82:6473597d706e 5945 #define BP_FTM_SWOCTRL_CH3OC (3U) //!< Bit position for FTM_SWOCTRL_CH3OC.
bogdanm 82:6473597d706e 5946 #define BM_FTM_SWOCTRL_CH3OC (0x00000008U) //!< Bit mask for FTM_SWOCTRL_CH3OC.
bogdanm 82:6473597d706e 5947 #define BS_FTM_SWOCTRL_CH3OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH3OC.
bogdanm 82:6473597d706e 5948
bogdanm 82:6473597d706e 5949 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5950 //! @brief Read current value of the FTM_SWOCTRL_CH3OC field.
bogdanm 82:6473597d706e 5951 #define BR_FTM_SWOCTRL_CH3OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC))
bogdanm 82:6473597d706e 5952 #endif
bogdanm 82:6473597d706e 5953
bogdanm 82:6473597d706e 5954 //! @brief Format value for bitfield FTM_SWOCTRL_CH3OC.
bogdanm 82:6473597d706e 5955 #define BF_FTM_SWOCTRL_CH3OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH3OC), uint32_t) & BM_FTM_SWOCTRL_CH3OC)
bogdanm 82:6473597d706e 5956
bogdanm 82:6473597d706e 5957 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5958 //! @brief Set the CH3OC field to a new value.
bogdanm 82:6473597d706e 5959 #define BW_FTM_SWOCTRL_CH3OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC) = (v))
bogdanm 82:6473597d706e 5960 #endif
bogdanm 82:6473597d706e 5961 //@}
bogdanm 82:6473597d706e 5962
bogdanm 82:6473597d706e 5963 /*!
bogdanm 82:6473597d706e 5964 * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
bogdanm 82:6473597d706e 5965 *
bogdanm 82:6473597d706e 5966 * Values:
bogdanm 82:6473597d706e 5967 * - 0 - The channel output is not affected by software output control.
bogdanm 82:6473597d706e 5968 * - 1 - The channel output is affected by software output control.
bogdanm 82:6473597d706e 5969 */
bogdanm 82:6473597d706e 5970 //@{
bogdanm 82:6473597d706e 5971 #define BP_FTM_SWOCTRL_CH4OC (4U) //!< Bit position for FTM_SWOCTRL_CH4OC.
bogdanm 82:6473597d706e 5972 #define BM_FTM_SWOCTRL_CH4OC (0x00000010U) //!< Bit mask for FTM_SWOCTRL_CH4OC.
bogdanm 82:6473597d706e 5973 #define BS_FTM_SWOCTRL_CH4OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH4OC.
bogdanm 82:6473597d706e 5974
bogdanm 82:6473597d706e 5975 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5976 //! @brief Read current value of the FTM_SWOCTRL_CH4OC field.
bogdanm 82:6473597d706e 5977 #define BR_FTM_SWOCTRL_CH4OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC))
bogdanm 82:6473597d706e 5978 #endif
bogdanm 82:6473597d706e 5979
bogdanm 82:6473597d706e 5980 //! @brief Format value for bitfield FTM_SWOCTRL_CH4OC.
bogdanm 82:6473597d706e 5981 #define BF_FTM_SWOCTRL_CH4OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH4OC), uint32_t) & BM_FTM_SWOCTRL_CH4OC)
bogdanm 82:6473597d706e 5982
bogdanm 82:6473597d706e 5983 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5984 //! @brief Set the CH4OC field to a new value.
bogdanm 82:6473597d706e 5985 #define BW_FTM_SWOCTRL_CH4OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC) = (v))
bogdanm 82:6473597d706e 5986 #endif
bogdanm 82:6473597d706e 5987 //@}
bogdanm 82:6473597d706e 5988
bogdanm 82:6473597d706e 5989 /*!
bogdanm 82:6473597d706e 5990 * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
bogdanm 82:6473597d706e 5991 *
bogdanm 82:6473597d706e 5992 * Values:
bogdanm 82:6473597d706e 5993 * - 0 - The channel output is not affected by software output control.
bogdanm 82:6473597d706e 5994 * - 1 - The channel output is affected by software output control.
bogdanm 82:6473597d706e 5995 */
bogdanm 82:6473597d706e 5996 //@{
bogdanm 82:6473597d706e 5997 #define BP_FTM_SWOCTRL_CH5OC (5U) //!< Bit position for FTM_SWOCTRL_CH5OC.
bogdanm 82:6473597d706e 5998 #define BM_FTM_SWOCTRL_CH5OC (0x00000020U) //!< Bit mask for FTM_SWOCTRL_CH5OC.
bogdanm 82:6473597d706e 5999 #define BS_FTM_SWOCTRL_CH5OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH5OC.
bogdanm 82:6473597d706e 6000
bogdanm 82:6473597d706e 6001 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6002 //! @brief Read current value of the FTM_SWOCTRL_CH5OC field.
bogdanm 82:6473597d706e 6003 #define BR_FTM_SWOCTRL_CH5OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC))
bogdanm 82:6473597d706e 6004 #endif
bogdanm 82:6473597d706e 6005
bogdanm 82:6473597d706e 6006 //! @brief Format value for bitfield FTM_SWOCTRL_CH5OC.
bogdanm 82:6473597d706e 6007 #define BF_FTM_SWOCTRL_CH5OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH5OC), uint32_t) & BM_FTM_SWOCTRL_CH5OC)
bogdanm 82:6473597d706e 6008
bogdanm 82:6473597d706e 6009 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6010 //! @brief Set the CH5OC field to a new value.
bogdanm 82:6473597d706e 6011 #define BW_FTM_SWOCTRL_CH5OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC) = (v))
bogdanm 82:6473597d706e 6012 #endif
bogdanm 82:6473597d706e 6013 //@}
bogdanm 82:6473597d706e 6014
bogdanm 82:6473597d706e 6015 /*!
bogdanm 82:6473597d706e 6016 * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
bogdanm 82:6473597d706e 6017 *
bogdanm 82:6473597d706e 6018 * Values:
bogdanm 82:6473597d706e 6019 * - 0 - The channel output is not affected by software output control.
bogdanm 82:6473597d706e 6020 * - 1 - The channel output is affected by software output control.
bogdanm 82:6473597d706e 6021 */
bogdanm 82:6473597d706e 6022 //@{
bogdanm 82:6473597d706e 6023 #define BP_FTM_SWOCTRL_CH6OC (6U) //!< Bit position for FTM_SWOCTRL_CH6OC.
bogdanm 82:6473597d706e 6024 #define BM_FTM_SWOCTRL_CH6OC (0x00000040U) //!< Bit mask for FTM_SWOCTRL_CH6OC.
bogdanm 82:6473597d706e 6025 #define BS_FTM_SWOCTRL_CH6OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH6OC.
bogdanm 82:6473597d706e 6026
bogdanm 82:6473597d706e 6027 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6028 //! @brief Read current value of the FTM_SWOCTRL_CH6OC field.
bogdanm 82:6473597d706e 6029 #define BR_FTM_SWOCTRL_CH6OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC))
bogdanm 82:6473597d706e 6030 #endif
bogdanm 82:6473597d706e 6031
bogdanm 82:6473597d706e 6032 //! @brief Format value for bitfield FTM_SWOCTRL_CH6OC.
bogdanm 82:6473597d706e 6033 #define BF_FTM_SWOCTRL_CH6OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH6OC), uint32_t) & BM_FTM_SWOCTRL_CH6OC)
bogdanm 82:6473597d706e 6034
bogdanm 82:6473597d706e 6035 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6036 //! @brief Set the CH6OC field to a new value.
bogdanm 82:6473597d706e 6037 #define BW_FTM_SWOCTRL_CH6OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC) = (v))
bogdanm 82:6473597d706e 6038 #endif
bogdanm 82:6473597d706e 6039 //@}
bogdanm 82:6473597d706e 6040
bogdanm 82:6473597d706e 6041 /*!
bogdanm 82:6473597d706e 6042 * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
bogdanm 82:6473597d706e 6043 *
bogdanm 82:6473597d706e 6044 * Values:
bogdanm 82:6473597d706e 6045 * - 0 - The channel output is not affected by software output control.
bogdanm 82:6473597d706e 6046 * - 1 - The channel output is affected by software output control.
bogdanm 82:6473597d706e 6047 */
bogdanm 82:6473597d706e 6048 //@{
bogdanm 82:6473597d706e 6049 #define BP_FTM_SWOCTRL_CH7OC (7U) //!< Bit position for FTM_SWOCTRL_CH7OC.
bogdanm 82:6473597d706e 6050 #define BM_FTM_SWOCTRL_CH7OC (0x00000080U) //!< Bit mask for FTM_SWOCTRL_CH7OC.
bogdanm 82:6473597d706e 6051 #define BS_FTM_SWOCTRL_CH7OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH7OC.
bogdanm 82:6473597d706e 6052
bogdanm 82:6473597d706e 6053 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6054 //! @brief Read current value of the FTM_SWOCTRL_CH7OC field.
bogdanm 82:6473597d706e 6055 #define BR_FTM_SWOCTRL_CH7OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC))
bogdanm 82:6473597d706e 6056 #endif
bogdanm 82:6473597d706e 6057
bogdanm 82:6473597d706e 6058 //! @brief Format value for bitfield FTM_SWOCTRL_CH7OC.
bogdanm 82:6473597d706e 6059 #define BF_FTM_SWOCTRL_CH7OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH7OC), uint32_t) & BM_FTM_SWOCTRL_CH7OC)
bogdanm 82:6473597d706e 6060
bogdanm 82:6473597d706e 6061 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6062 //! @brief Set the CH7OC field to a new value.
bogdanm 82:6473597d706e 6063 #define BW_FTM_SWOCTRL_CH7OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC) = (v))
bogdanm 82:6473597d706e 6064 #endif
bogdanm 82:6473597d706e 6065 //@}
bogdanm 82:6473597d706e 6066
bogdanm 82:6473597d706e 6067 /*!
bogdanm 82:6473597d706e 6068 * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
bogdanm 82:6473597d706e 6069 *
bogdanm 82:6473597d706e 6070 * Values:
bogdanm 82:6473597d706e 6071 * - 0 - The software output control forces 0 to the channel output.
bogdanm 82:6473597d706e 6072 * - 1 - The software output control forces 1 to the channel output.
bogdanm 82:6473597d706e 6073 */
bogdanm 82:6473597d706e 6074 //@{
bogdanm 82:6473597d706e 6075 #define BP_FTM_SWOCTRL_CH0OCV (8U) //!< Bit position for FTM_SWOCTRL_CH0OCV.
bogdanm 82:6473597d706e 6076 #define BM_FTM_SWOCTRL_CH0OCV (0x00000100U) //!< Bit mask for FTM_SWOCTRL_CH0OCV.
bogdanm 82:6473597d706e 6077 #define BS_FTM_SWOCTRL_CH0OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH0OCV.
bogdanm 82:6473597d706e 6078
bogdanm 82:6473597d706e 6079 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6080 //! @brief Read current value of the FTM_SWOCTRL_CH0OCV field.
bogdanm 82:6473597d706e 6081 #define BR_FTM_SWOCTRL_CH0OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV))
bogdanm 82:6473597d706e 6082 #endif
bogdanm 82:6473597d706e 6083
bogdanm 82:6473597d706e 6084 //! @brief Format value for bitfield FTM_SWOCTRL_CH0OCV.
bogdanm 82:6473597d706e 6085 #define BF_FTM_SWOCTRL_CH0OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH0OCV), uint32_t) & BM_FTM_SWOCTRL_CH0OCV)
bogdanm 82:6473597d706e 6086
bogdanm 82:6473597d706e 6087 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6088 //! @brief Set the CH0OCV field to a new value.
bogdanm 82:6473597d706e 6089 #define BW_FTM_SWOCTRL_CH0OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV) = (v))
bogdanm 82:6473597d706e 6090 #endif
bogdanm 82:6473597d706e 6091 //@}
bogdanm 82:6473597d706e 6092
bogdanm 82:6473597d706e 6093 /*!
bogdanm 82:6473597d706e 6094 * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
bogdanm 82:6473597d706e 6095 *
bogdanm 82:6473597d706e 6096 * Values:
bogdanm 82:6473597d706e 6097 * - 0 - The software output control forces 0 to the channel output.
bogdanm 82:6473597d706e 6098 * - 1 - The software output control forces 1 to the channel output.
bogdanm 82:6473597d706e 6099 */
bogdanm 82:6473597d706e 6100 //@{
bogdanm 82:6473597d706e 6101 #define BP_FTM_SWOCTRL_CH1OCV (9U) //!< Bit position for FTM_SWOCTRL_CH1OCV.
bogdanm 82:6473597d706e 6102 #define BM_FTM_SWOCTRL_CH1OCV (0x00000200U) //!< Bit mask for FTM_SWOCTRL_CH1OCV.
bogdanm 82:6473597d706e 6103 #define BS_FTM_SWOCTRL_CH1OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH1OCV.
bogdanm 82:6473597d706e 6104
bogdanm 82:6473597d706e 6105 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6106 //! @brief Read current value of the FTM_SWOCTRL_CH1OCV field.
bogdanm 82:6473597d706e 6107 #define BR_FTM_SWOCTRL_CH1OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV))
bogdanm 82:6473597d706e 6108 #endif
bogdanm 82:6473597d706e 6109
bogdanm 82:6473597d706e 6110 //! @brief Format value for bitfield FTM_SWOCTRL_CH1OCV.
bogdanm 82:6473597d706e 6111 #define BF_FTM_SWOCTRL_CH1OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH1OCV), uint32_t) & BM_FTM_SWOCTRL_CH1OCV)
bogdanm 82:6473597d706e 6112
bogdanm 82:6473597d706e 6113 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6114 //! @brief Set the CH1OCV field to a new value.
bogdanm 82:6473597d706e 6115 #define BW_FTM_SWOCTRL_CH1OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV) = (v))
bogdanm 82:6473597d706e 6116 #endif
bogdanm 82:6473597d706e 6117 //@}
bogdanm 82:6473597d706e 6118
bogdanm 82:6473597d706e 6119 /*!
bogdanm 82:6473597d706e 6120 * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
bogdanm 82:6473597d706e 6121 *
bogdanm 82:6473597d706e 6122 * Values:
bogdanm 82:6473597d706e 6123 * - 0 - The software output control forces 0 to the channel output.
bogdanm 82:6473597d706e 6124 * - 1 - The software output control forces 1 to the channel output.
bogdanm 82:6473597d706e 6125 */
bogdanm 82:6473597d706e 6126 //@{
bogdanm 82:6473597d706e 6127 #define BP_FTM_SWOCTRL_CH2OCV (10U) //!< Bit position for FTM_SWOCTRL_CH2OCV.
bogdanm 82:6473597d706e 6128 #define BM_FTM_SWOCTRL_CH2OCV (0x00000400U) //!< Bit mask for FTM_SWOCTRL_CH2OCV.
bogdanm 82:6473597d706e 6129 #define BS_FTM_SWOCTRL_CH2OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH2OCV.
bogdanm 82:6473597d706e 6130
bogdanm 82:6473597d706e 6131 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6132 //! @brief Read current value of the FTM_SWOCTRL_CH2OCV field.
bogdanm 82:6473597d706e 6133 #define BR_FTM_SWOCTRL_CH2OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV))
bogdanm 82:6473597d706e 6134 #endif
bogdanm 82:6473597d706e 6135
bogdanm 82:6473597d706e 6136 //! @brief Format value for bitfield FTM_SWOCTRL_CH2OCV.
bogdanm 82:6473597d706e 6137 #define BF_FTM_SWOCTRL_CH2OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH2OCV), uint32_t) & BM_FTM_SWOCTRL_CH2OCV)
bogdanm 82:6473597d706e 6138
bogdanm 82:6473597d706e 6139 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6140 //! @brief Set the CH2OCV field to a new value.
bogdanm 82:6473597d706e 6141 #define BW_FTM_SWOCTRL_CH2OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV) = (v))
bogdanm 82:6473597d706e 6142 #endif
bogdanm 82:6473597d706e 6143 //@}
bogdanm 82:6473597d706e 6144
bogdanm 82:6473597d706e 6145 /*!
bogdanm 82:6473597d706e 6146 * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
bogdanm 82:6473597d706e 6147 *
bogdanm 82:6473597d706e 6148 * Values:
bogdanm 82:6473597d706e 6149 * - 0 - The software output control forces 0 to the channel output.
bogdanm 82:6473597d706e 6150 * - 1 - The software output control forces 1 to the channel output.
bogdanm 82:6473597d706e 6151 */
bogdanm 82:6473597d706e 6152 //@{
bogdanm 82:6473597d706e 6153 #define BP_FTM_SWOCTRL_CH3OCV (11U) //!< Bit position for FTM_SWOCTRL_CH3OCV.
bogdanm 82:6473597d706e 6154 #define BM_FTM_SWOCTRL_CH3OCV (0x00000800U) //!< Bit mask for FTM_SWOCTRL_CH3OCV.
bogdanm 82:6473597d706e 6155 #define BS_FTM_SWOCTRL_CH3OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH3OCV.
bogdanm 82:6473597d706e 6156
bogdanm 82:6473597d706e 6157 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6158 //! @brief Read current value of the FTM_SWOCTRL_CH3OCV field.
bogdanm 82:6473597d706e 6159 #define BR_FTM_SWOCTRL_CH3OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV))
bogdanm 82:6473597d706e 6160 #endif
bogdanm 82:6473597d706e 6161
bogdanm 82:6473597d706e 6162 //! @brief Format value for bitfield FTM_SWOCTRL_CH3OCV.
bogdanm 82:6473597d706e 6163 #define BF_FTM_SWOCTRL_CH3OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH3OCV), uint32_t) & BM_FTM_SWOCTRL_CH3OCV)
bogdanm 82:6473597d706e 6164
bogdanm 82:6473597d706e 6165 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6166 //! @brief Set the CH3OCV field to a new value.
bogdanm 82:6473597d706e 6167 #define BW_FTM_SWOCTRL_CH3OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV) = (v))
bogdanm 82:6473597d706e 6168 #endif
bogdanm 82:6473597d706e 6169 //@}
bogdanm 82:6473597d706e 6170
bogdanm 82:6473597d706e 6171 /*!
bogdanm 82:6473597d706e 6172 * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
bogdanm 82:6473597d706e 6173 *
bogdanm 82:6473597d706e 6174 * Values:
bogdanm 82:6473597d706e 6175 * - 0 - The software output control forces 0 to the channel output.
bogdanm 82:6473597d706e 6176 * - 1 - The software output control forces 1 to the channel output.
bogdanm 82:6473597d706e 6177 */
bogdanm 82:6473597d706e 6178 //@{
bogdanm 82:6473597d706e 6179 #define BP_FTM_SWOCTRL_CH4OCV (12U) //!< Bit position for FTM_SWOCTRL_CH4OCV.
bogdanm 82:6473597d706e 6180 #define BM_FTM_SWOCTRL_CH4OCV (0x00001000U) //!< Bit mask for FTM_SWOCTRL_CH4OCV.
bogdanm 82:6473597d706e 6181 #define BS_FTM_SWOCTRL_CH4OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH4OCV.
bogdanm 82:6473597d706e 6182
bogdanm 82:6473597d706e 6183 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6184 //! @brief Read current value of the FTM_SWOCTRL_CH4OCV field.
bogdanm 82:6473597d706e 6185 #define BR_FTM_SWOCTRL_CH4OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV))
bogdanm 82:6473597d706e 6186 #endif
bogdanm 82:6473597d706e 6187
bogdanm 82:6473597d706e 6188 //! @brief Format value for bitfield FTM_SWOCTRL_CH4OCV.
bogdanm 82:6473597d706e 6189 #define BF_FTM_SWOCTRL_CH4OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH4OCV), uint32_t) & BM_FTM_SWOCTRL_CH4OCV)
bogdanm 82:6473597d706e 6190
bogdanm 82:6473597d706e 6191 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6192 //! @brief Set the CH4OCV field to a new value.
bogdanm 82:6473597d706e 6193 #define BW_FTM_SWOCTRL_CH4OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV) = (v))
bogdanm 82:6473597d706e 6194 #endif
bogdanm 82:6473597d706e 6195 //@}
bogdanm 82:6473597d706e 6196
bogdanm 82:6473597d706e 6197 /*!
bogdanm 82:6473597d706e 6198 * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
bogdanm 82:6473597d706e 6199 *
bogdanm 82:6473597d706e 6200 * Values:
bogdanm 82:6473597d706e 6201 * - 0 - The software output control forces 0 to the channel output.
bogdanm 82:6473597d706e 6202 * - 1 - The software output control forces 1 to the channel output.
bogdanm 82:6473597d706e 6203 */
bogdanm 82:6473597d706e 6204 //@{
bogdanm 82:6473597d706e 6205 #define BP_FTM_SWOCTRL_CH5OCV (13U) //!< Bit position for FTM_SWOCTRL_CH5OCV.
bogdanm 82:6473597d706e 6206 #define BM_FTM_SWOCTRL_CH5OCV (0x00002000U) //!< Bit mask for FTM_SWOCTRL_CH5OCV.
bogdanm 82:6473597d706e 6207 #define BS_FTM_SWOCTRL_CH5OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH5OCV.
bogdanm 82:6473597d706e 6208
bogdanm 82:6473597d706e 6209 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6210 //! @brief Read current value of the FTM_SWOCTRL_CH5OCV field.
bogdanm 82:6473597d706e 6211 #define BR_FTM_SWOCTRL_CH5OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV))
bogdanm 82:6473597d706e 6212 #endif
bogdanm 82:6473597d706e 6213
bogdanm 82:6473597d706e 6214 //! @brief Format value for bitfield FTM_SWOCTRL_CH5OCV.
bogdanm 82:6473597d706e 6215 #define BF_FTM_SWOCTRL_CH5OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH5OCV), uint32_t) & BM_FTM_SWOCTRL_CH5OCV)
bogdanm 82:6473597d706e 6216
bogdanm 82:6473597d706e 6217 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6218 //! @brief Set the CH5OCV field to a new value.
bogdanm 82:6473597d706e 6219 #define BW_FTM_SWOCTRL_CH5OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV) = (v))
bogdanm 82:6473597d706e 6220 #endif
bogdanm 82:6473597d706e 6221 //@}
bogdanm 82:6473597d706e 6222
bogdanm 82:6473597d706e 6223 /*!
bogdanm 82:6473597d706e 6224 * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
bogdanm 82:6473597d706e 6225 *
bogdanm 82:6473597d706e 6226 * Values:
bogdanm 82:6473597d706e 6227 * - 0 - The software output control forces 0 to the channel output.
bogdanm 82:6473597d706e 6228 * - 1 - The software output control forces 1 to the channel output.
bogdanm 82:6473597d706e 6229 */
bogdanm 82:6473597d706e 6230 //@{
bogdanm 82:6473597d706e 6231 #define BP_FTM_SWOCTRL_CH6OCV (14U) //!< Bit position for FTM_SWOCTRL_CH6OCV.
bogdanm 82:6473597d706e 6232 #define BM_FTM_SWOCTRL_CH6OCV (0x00004000U) //!< Bit mask for FTM_SWOCTRL_CH6OCV.
bogdanm 82:6473597d706e 6233 #define BS_FTM_SWOCTRL_CH6OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH6OCV.
bogdanm 82:6473597d706e 6234
bogdanm 82:6473597d706e 6235 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6236 //! @brief Read current value of the FTM_SWOCTRL_CH6OCV field.
bogdanm 82:6473597d706e 6237 #define BR_FTM_SWOCTRL_CH6OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV))
bogdanm 82:6473597d706e 6238 #endif
bogdanm 82:6473597d706e 6239
bogdanm 82:6473597d706e 6240 //! @brief Format value for bitfield FTM_SWOCTRL_CH6OCV.
bogdanm 82:6473597d706e 6241 #define BF_FTM_SWOCTRL_CH6OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH6OCV), uint32_t) & BM_FTM_SWOCTRL_CH6OCV)
bogdanm 82:6473597d706e 6242
bogdanm 82:6473597d706e 6243 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6244 //! @brief Set the CH6OCV field to a new value.
bogdanm 82:6473597d706e 6245 #define BW_FTM_SWOCTRL_CH6OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV) = (v))
bogdanm 82:6473597d706e 6246 #endif
bogdanm 82:6473597d706e 6247 //@}
bogdanm 82:6473597d706e 6248
bogdanm 82:6473597d706e 6249 /*!
bogdanm 82:6473597d706e 6250 * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
bogdanm 82:6473597d706e 6251 *
bogdanm 82:6473597d706e 6252 * Values:
bogdanm 82:6473597d706e 6253 * - 0 - The software output control forces 0 to the channel output.
bogdanm 82:6473597d706e 6254 * - 1 - The software output control forces 1 to the channel output.
bogdanm 82:6473597d706e 6255 */
bogdanm 82:6473597d706e 6256 //@{
bogdanm 82:6473597d706e 6257 #define BP_FTM_SWOCTRL_CH7OCV (15U) //!< Bit position for FTM_SWOCTRL_CH7OCV.
bogdanm 82:6473597d706e 6258 #define BM_FTM_SWOCTRL_CH7OCV (0x00008000U) //!< Bit mask for FTM_SWOCTRL_CH7OCV.
bogdanm 82:6473597d706e 6259 #define BS_FTM_SWOCTRL_CH7OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH7OCV.
bogdanm 82:6473597d706e 6260
bogdanm 82:6473597d706e 6261 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6262 //! @brief Read current value of the FTM_SWOCTRL_CH7OCV field.
bogdanm 82:6473597d706e 6263 #define BR_FTM_SWOCTRL_CH7OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV))
bogdanm 82:6473597d706e 6264 #endif
bogdanm 82:6473597d706e 6265
bogdanm 82:6473597d706e 6266 //! @brief Format value for bitfield FTM_SWOCTRL_CH7OCV.
bogdanm 82:6473597d706e 6267 #define BF_FTM_SWOCTRL_CH7OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH7OCV), uint32_t) & BM_FTM_SWOCTRL_CH7OCV)
bogdanm 82:6473597d706e 6268
bogdanm 82:6473597d706e 6269 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6270 //! @brief Set the CH7OCV field to a new value.
bogdanm 82:6473597d706e 6271 #define BW_FTM_SWOCTRL_CH7OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV) = (v))
bogdanm 82:6473597d706e 6272 #endif
bogdanm 82:6473597d706e 6273 //@}
bogdanm 82:6473597d706e 6274
bogdanm 82:6473597d706e 6275 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 6276 // HW_FTM_PWMLOAD - FTM PWM Load
bogdanm 82:6473597d706e 6277 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 6278
bogdanm 82:6473597d706e 6279 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6280 /*!
bogdanm 82:6473597d706e 6281 * @brief HW_FTM_PWMLOAD - FTM PWM Load (RW)
bogdanm 82:6473597d706e 6282 *
bogdanm 82:6473597d706e 6283 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 6284 *
bogdanm 82:6473597d706e 6285 * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
bogdanm 82:6473597d706e 6286 * values of their write buffers when the FTM counter changes from the MOD
bogdanm 82:6473597d706e 6287 * register value to its next value or when a channel (j) match occurs. A match occurs
bogdanm 82:6473597d706e 6288 * for the channel (j) when FTM counter = C(j)V.
bogdanm 82:6473597d706e 6289 */
bogdanm 82:6473597d706e 6290 typedef union _hw_ftm_pwmload
bogdanm 82:6473597d706e 6291 {
bogdanm 82:6473597d706e 6292 uint32_t U;
bogdanm 82:6473597d706e 6293 struct _hw_ftm_pwmload_bitfields
bogdanm 82:6473597d706e 6294 {
bogdanm 82:6473597d706e 6295 uint32_t CH0SEL : 1; //!< [0] Channel 0 Select
bogdanm 82:6473597d706e 6296 uint32_t CH1SEL : 1; //!< [1] Channel 1 Select
bogdanm 82:6473597d706e 6297 uint32_t CH2SEL : 1; //!< [2] Channel 2 Select
bogdanm 82:6473597d706e 6298 uint32_t CH3SEL : 1; //!< [3] Channel 3 Select
bogdanm 82:6473597d706e 6299 uint32_t CH4SEL : 1; //!< [4] Channel 4 Select
bogdanm 82:6473597d706e 6300 uint32_t CH5SEL : 1; //!< [5] Channel 5 Select
bogdanm 82:6473597d706e 6301 uint32_t CH6SEL : 1; //!< [6] Channel 6 Select
bogdanm 82:6473597d706e 6302 uint32_t CH7SEL : 1; //!< [7] Channel 7 Select
bogdanm 82:6473597d706e 6303 uint32_t RESERVED0 : 1; //!< [8]
bogdanm 82:6473597d706e 6304 uint32_t LDOK : 1; //!< [9] Load Enable
bogdanm 82:6473597d706e 6305 uint32_t RESERVED1 : 22; //!< [31:10]
bogdanm 82:6473597d706e 6306 } B;
bogdanm 82:6473597d706e 6307 } hw_ftm_pwmload_t;
bogdanm 82:6473597d706e 6308 #endif
bogdanm 82:6473597d706e 6309
bogdanm 82:6473597d706e 6310 /*!
bogdanm 82:6473597d706e 6311 * @name Constants and macros for entire FTM_PWMLOAD register
bogdanm 82:6473597d706e 6312 */
bogdanm 82:6473597d706e 6313 //@{
bogdanm 82:6473597d706e 6314 #define HW_FTM_PWMLOAD_ADDR(x) (REGS_FTM_BASE(x) + 0x98U)
bogdanm 82:6473597d706e 6315
bogdanm 82:6473597d706e 6316 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6317 #define HW_FTM_PWMLOAD(x) (*(__IO hw_ftm_pwmload_t *) HW_FTM_PWMLOAD_ADDR(x))
bogdanm 82:6473597d706e 6318 #define HW_FTM_PWMLOAD_RD(x) (HW_FTM_PWMLOAD(x).U)
bogdanm 82:6473597d706e 6319 #define HW_FTM_PWMLOAD_WR(x, v) (HW_FTM_PWMLOAD(x).U = (v))
bogdanm 82:6473597d706e 6320 #define HW_FTM_PWMLOAD_SET(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) | (v)))
bogdanm 82:6473597d706e 6321 #define HW_FTM_PWMLOAD_CLR(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) & ~(v)))
bogdanm 82:6473597d706e 6322 #define HW_FTM_PWMLOAD_TOG(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) ^ (v)))
bogdanm 82:6473597d706e 6323 #endif
bogdanm 82:6473597d706e 6324 //@}
bogdanm 82:6473597d706e 6325
bogdanm 82:6473597d706e 6326 /*
bogdanm 82:6473597d706e 6327 * Constants & macros for individual FTM_PWMLOAD bitfields
bogdanm 82:6473597d706e 6328 */
bogdanm 82:6473597d706e 6329
bogdanm 82:6473597d706e 6330 /*!
bogdanm 82:6473597d706e 6331 * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
bogdanm 82:6473597d706e 6332 *
bogdanm 82:6473597d706e 6333 * Values:
bogdanm 82:6473597d706e 6334 * - 0 - Do not include the channel in the matching process.
bogdanm 82:6473597d706e 6335 * - 1 - Include the channel in the matching process.
bogdanm 82:6473597d706e 6336 */
bogdanm 82:6473597d706e 6337 //@{
bogdanm 82:6473597d706e 6338 #define BP_FTM_PWMLOAD_CH0SEL (0U) //!< Bit position for FTM_PWMLOAD_CH0SEL.
bogdanm 82:6473597d706e 6339 #define BM_FTM_PWMLOAD_CH0SEL (0x00000001U) //!< Bit mask for FTM_PWMLOAD_CH0SEL.
bogdanm 82:6473597d706e 6340 #define BS_FTM_PWMLOAD_CH0SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH0SEL.
bogdanm 82:6473597d706e 6341
bogdanm 82:6473597d706e 6342 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6343 //! @brief Read current value of the FTM_PWMLOAD_CH0SEL field.
bogdanm 82:6473597d706e 6344 #define BR_FTM_PWMLOAD_CH0SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL))
bogdanm 82:6473597d706e 6345 #endif
bogdanm 82:6473597d706e 6346
bogdanm 82:6473597d706e 6347 //! @brief Format value for bitfield FTM_PWMLOAD_CH0SEL.
bogdanm 82:6473597d706e 6348 #define BF_FTM_PWMLOAD_CH0SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH0SEL), uint32_t) & BM_FTM_PWMLOAD_CH0SEL)
bogdanm 82:6473597d706e 6349
bogdanm 82:6473597d706e 6350 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6351 //! @brief Set the CH0SEL field to a new value.
bogdanm 82:6473597d706e 6352 #define BW_FTM_PWMLOAD_CH0SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL) = (v))
bogdanm 82:6473597d706e 6353 #endif
bogdanm 82:6473597d706e 6354 //@}
bogdanm 82:6473597d706e 6355
bogdanm 82:6473597d706e 6356 /*!
bogdanm 82:6473597d706e 6357 * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
bogdanm 82:6473597d706e 6358 *
bogdanm 82:6473597d706e 6359 * Values:
bogdanm 82:6473597d706e 6360 * - 0 - Do not include the channel in the matching process.
bogdanm 82:6473597d706e 6361 * - 1 - Include the channel in the matching process.
bogdanm 82:6473597d706e 6362 */
bogdanm 82:6473597d706e 6363 //@{
bogdanm 82:6473597d706e 6364 #define BP_FTM_PWMLOAD_CH1SEL (1U) //!< Bit position for FTM_PWMLOAD_CH1SEL.
bogdanm 82:6473597d706e 6365 #define BM_FTM_PWMLOAD_CH1SEL (0x00000002U) //!< Bit mask for FTM_PWMLOAD_CH1SEL.
bogdanm 82:6473597d706e 6366 #define BS_FTM_PWMLOAD_CH1SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH1SEL.
bogdanm 82:6473597d706e 6367
bogdanm 82:6473597d706e 6368 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6369 //! @brief Read current value of the FTM_PWMLOAD_CH1SEL field.
bogdanm 82:6473597d706e 6370 #define BR_FTM_PWMLOAD_CH1SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL))
bogdanm 82:6473597d706e 6371 #endif
bogdanm 82:6473597d706e 6372
bogdanm 82:6473597d706e 6373 //! @brief Format value for bitfield FTM_PWMLOAD_CH1SEL.
bogdanm 82:6473597d706e 6374 #define BF_FTM_PWMLOAD_CH1SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH1SEL), uint32_t) & BM_FTM_PWMLOAD_CH1SEL)
bogdanm 82:6473597d706e 6375
bogdanm 82:6473597d706e 6376 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6377 //! @brief Set the CH1SEL field to a new value.
bogdanm 82:6473597d706e 6378 #define BW_FTM_PWMLOAD_CH1SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL) = (v))
bogdanm 82:6473597d706e 6379 #endif
bogdanm 82:6473597d706e 6380 //@}
bogdanm 82:6473597d706e 6381
bogdanm 82:6473597d706e 6382 /*!
bogdanm 82:6473597d706e 6383 * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
bogdanm 82:6473597d706e 6384 *
bogdanm 82:6473597d706e 6385 * Values:
bogdanm 82:6473597d706e 6386 * - 0 - Do not include the channel in the matching process.
bogdanm 82:6473597d706e 6387 * - 1 - Include the channel in the matching process.
bogdanm 82:6473597d706e 6388 */
bogdanm 82:6473597d706e 6389 //@{
bogdanm 82:6473597d706e 6390 #define BP_FTM_PWMLOAD_CH2SEL (2U) //!< Bit position for FTM_PWMLOAD_CH2SEL.
bogdanm 82:6473597d706e 6391 #define BM_FTM_PWMLOAD_CH2SEL (0x00000004U) //!< Bit mask for FTM_PWMLOAD_CH2SEL.
bogdanm 82:6473597d706e 6392 #define BS_FTM_PWMLOAD_CH2SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH2SEL.
bogdanm 82:6473597d706e 6393
bogdanm 82:6473597d706e 6394 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6395 //! @brief Read current value of the FTM_PWMLOAD_CH2SEL field.
bogdanm 82:6473597d706e 6396 #define BR_FTM_PWMLOAD_CH2SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL))
bogdanm 82:6473597d706e 6397 #endif
bogdanm 82:6473597d706e 6398
bogdanm 82:6473597d706e 6399 //! @brief Format value for bitfield FTM_PWMLOAD_CH2SEL.
bogdanm 82:6473597d706e 6400 #define BF_FTM_PWMLOAD_CH2SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH2SEL), uint32_t) & BM_FTM_PWMLOAD_CH2SEL)
bogdanm 82:6473597d706e 6401
bogdanm 82:6473597d706e 6402 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6403 //! @brief Set the CH2SEL field to a new value.
bogdanm 82:6473597d706e 6404 #define BW_FTM_PWMLOAD_CH2SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL) = (v))
bogdanm 82:6473597d706e 6405 #endif
bogdanm 82:6473597d706e 6406 //@}
bogdanm 82:6473597d706e 6407
bogdanm 82:6473597d706e 6408 /*!
bogdanm 82:6473597d706e 6409 * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
bogdanm 82:6473597d706e 6410 *
bogdanm 82:6473597d706e 6411 * Values:
bogdanm 82:6473597d706e 6412 * - 0 - Do not include the channel in the matching process.
bogdanm 82:6473597d706e 6413 * - 1 - Include the channel in the matching process.
bogdanm 82:6473597d706e 6414 */
bogdanm 82:6473597d706e 6415 //@{
bogdanm 82:6473597d706e 6416 #define BP_FTM_PWMLOAD_CH3SEL (3U) //!< Bit position for FTM_PWMLOAD_CH3SEL.
bogdanm 82:6473597d706e 6417 #define BM_FTM_PWMLOAD_CH3SEL (0x00000008U) //!< Bit mask for FTM_PWMLOAD_CH3SEL.
bogdanm 82:6473597d706e 6418 #define BS_FTM_PWMLOAD_CH3SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH3SEL.
bogdanm 82:6473597d706e 6419
bogdanm 82:6473597d706e 6420 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6421 //! @brief Read current value of the FTM_PWMLOAD_CH3SEL field.
bogdanm 82:6473597d706e 6422 #define BR_FTM_PWMLOAD_CH3SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL))
bogdanm 82:6473597d706e 6423 #endif
bogdanm 82:6473597d706e 6424
bogdanm 82:6473597d706e 6425 //! @brief Format value for bitfield FTM_PWMLOAD_CH3SEL.
bogdanm 82:6473597d706e 6426 #define BF_FTM_PWMLOAD_CH3SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH3SEL), uint32_t) & BM_FTM_PWMLOAD_CH3SEL)
bogdanm 82:6473597d706e 6427
bogdanm 82:6473597d706e 6428 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6429 //! @brief Set the CH3SEL field to a new value.
bogdanm 82:6473597d706e 6430 #define BW_FTM_PWMLOAD_CH3SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL) = (v))
bogdanm 82:6473597d706e 6431 #endif
bogdanm 82:6473597d706e 6432 //@}
bogdanm 82:6473597d706e 6433
bogdanm 82:6473597d706e 6434 /*!
bogdanm 82:6473597d706e 6435 * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
bogdanm 82:6473597d706e 6436 *
bogdanm 82:6473597d706e 6437 * Values:
bogdanm 82:6473597d706e 6438 * - 0 - Do not include the channel in the matching process.
bogdanm 82:6473597d706e 6439 * - 1 - Include the channel in the matching process.
bogdanm 82:6473597d706e 6440 */
bogdanm 82:6473597d706e 6441 //@{
bogdanm 82:6473597d706e 6442 #define BP_FTM_PWMLOAD_CH4SEL (4U) //!< Bit position for FTM_PWMLOAD_CH4SEL.
bogdanm 82:6473597d706e 6443 #define BM_FTM_PWMLOAD_CH4SEL (0x00000010U) //!< Bit mask for FTM_PWMLOAD_CH4SEL.
bogdanm 82:6473597d706e 6444 #define BS_FTM_PWMLOAD_CH4SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH4SEL.
bogdanm 82:6473597d706e 6445
bogdanm 82:6473597d706e 6446 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6447 //! @brief Read current value of the FTM_PWMLOAD_CH4SEL field.
bogdanm 82:6473597d706e 6448 #define BR_FTM_PWMLOAD_CH4SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL))
bogdanm 82:6473597d706e 6449 #endif
bogdanm 82:6473597d706e 6450
bogdanm 82:6473597d706e 6451 //! @brief Format value for bitfield FTM_PWMLOAD_CH4SEL.
bogdanm 82:6473597d706e 6452 #define BF_FTM_PWMLOAD_CH4SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH4SEL), uint32_t) & BM_FTM_PWMLOAD_CH4SEL)
bogdanm 82:6473597d706e 6453
bogdanm 82:6473597d706e 6454 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6455 //! @brief Set the CH4SEL field to a new value.
bogdanm 82:6473597d706e 6456 #define BW_FTM_PWMLOAD_CH4SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL) = (v))
bogdanm 82:6473597d706e 6457 #endif
bogdanm 82:6473597d706e 6458 //@}
bogdanm 82:6473597d706e 6459
bogdanm 82:6473597d706e 6460 /*!
bogdanm 82:6473597d706e 6461 * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
bogdanm 82:6473597d706e 6462 *
bogdanm 82:6473597d706e 6463 * Values:
bogdanm 82:6473597d706e 6464 * - 0 - Do not include the channel in the matching process.
bogdanm 82:6473597d706e 6465 * - 1 - Include the channel in the matching process.
bogdanm 82:6473597d706e 6466 */
bogdanm 82:6473597d706e 6467 //@{
bogdanm 82:6473597d706e 6468 #define BP_FTM_PWMLOAD_CH5SEL (5U) //!< Bit position for FTM_PWMLOAD_CH5SEL.
bogdanm 82:6473597d706e 6469 #define BM_FTM_PWMLOAD_CH5SEL (0x00000020U) //!< Bit mask for FTM_PWMLOAD_CH5SEL.
bogdanm 82:6473597d706e 6470 #define BS_FTM_PWMLOAD_CH5SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH5SEL.
bogdanm 82:6473597d706e 6471
bogdanm 82:6473597d706e 6472 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6473 //! @brief Read current value of the FTM_PWMLOAD_CH5SEL field.
bogdanm 82:6473597d706e 6474 #define BR_FTM_PWMLOAD_CH5SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL))
bogdanm 82:6473597d706e 6475 #endif
bogdanm 82:6473597d706e 6476
bogdanm 82:6473597d706e 6477 //! @brief Format value for bitfield FTM_PWMLOAD_CH5SEL.
bogdanm 82:6473597d706e 6478 #define BF_FTM_PWMLOAD_CH5SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH5SEL), uint32_t) & BM_FTM_PWMLOAD_CH5SEL)
bogdanm 82:6473597d706e 6479
bogdanm 82:6473597d706e 6480 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6481 //! @brief Set the CH5SEL field to a new value.
bogdanm 82:6473597d706e 6482 #define BW_FTM_PWMLOAD_CH5SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL) = (v))
bogdanm 82:6473597d706e 6483 #endif
bogdanm 82:6473597d706e 6484 //@}
bogdanm 82:6473597d706e 6485
bogdanm 82:6473597d706e 6486 /*!
bogdanm 82:6473597d706e 6487 * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
bogdanm 82:6473597d706e 6488 *
bogdanm 82:6473597d706e 6489 * Values:
bogdanm 82:6473597d706e 6490 * - 0 - Do not include the channel in the matching process.
bogdanm 82:6473597d706e 6491 * - 1 - Include the channel in the matching process.
bogdanm 82:6473597d706e 6492 */
bogdanm 82:6473597d706e 6493 //@{
bogdanm 82:6473597d706e 6494 #define BP_FTM_PWMLOAD_CH6SEL (6U) //!< Bit position for FTM_PWMLOAD_CH6SEL.
bogdanm 82:6473597d706e 6495 #define BM_FTM_PWMLOAD_CH6SEL (0x00000040U) //!< Bit mask for FTM_PWMLOAD_CH6SEL.
bogdanm 82:6473597d706e 6496 #define BS_FTM_PWMLOAD_CH6SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH6SEL.
bogdanm 82:6473597d706e 6497
bogdanm 82:6473597d706e 6498 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6499 //! @brief Read current value of the FTM_PWMLOAD_CH6SEL field.
bogdanm 82:6473597d706e 6500 #define BR_FTM_PWMLOAD_CH6SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL))
bogdanm 82:6473597d706e 6501 #endif
bogdanm 82:6473597d706e 6502
bogdanm 82:6473597d706e 6503 //! @brief Format value for bitfield FTM_PWMLOAD_CH6SEL.
bogdanm 82:6473597d706e 6504 #define BF_FTM_PWMLOAD_CH6SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH6SEL), uint32_t) & BM_FTM_PWMLOAD_CH6SEL)
bogdanm 82:6473597d706e 6505
bogdanm 82:6473597d706e 6506 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6507 //! @brief Set the CH6SEL field to a new value.
bogdanm 82:6473597d706e 6508 #define BW_FTM_PWMLOAD_CH6SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL) = (v))
bogdanm 82:6473597d706e 6509 #endif
bogdanm 82:6473597d706e 6510 //@}
bogdanm 82:6473597d706e 6511
bogdanm 82:6473597d706e 6512 /*!
bogdanm 82:6473597d706e 6513 * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
bogdanm 82:6473597d706e 6514 *
bogdanm 82:6473597d706e 6515 * Values:
bogdanm 82:6473597d706e 6516 * - 0 - Do not include the channel in the matching process.
bogdanm 82:6473597d706e 6517 * - 1 - Include the channel in the matching process.
bogdanm 82:6473597d706e 6518 */
bogdanm 82:6473597d706e 6519 //@{
bogdanm 82:6473597d706e 6520 #define BP_FTM_PWMLOAD_CH7SEL (7U) //!< Bit position for FTM_PWMLOAD_CH7SEL.
bogdanm 82:6473597d706e 6521 #define BM_FTM_PWMLOAD_CH7SEL (0x00000080U) //!< Bit mask for FTM_PWMLOAD_CH7SEL.
bogdanm 82:6473597d706e 6522 #define BS_FTM_PWMLOAD_CH7SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH7SEL.
bogdanm 82:6473597d706e 6523
bogdanm 82:6473597d706e 6524 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6525 //! @brief Read current value of the FTM_PWMLOAD_CH7SEL field.
bogdanm 82:6473597d706e 6526 #define BR_FTM_PWMLOAD_CH7SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL))
bogdanm 82:6473597d706e 6527 #endif
bogdanm 82:6473597d706e 6528
bogdanm 82:6473597d706e 6529 //! @brief Format value for bitfield FTM_PWMLOAD_CH7SEL.
bogdanm 82:6473597d706e 6530 #define BF_FTM_PWMLOAD_CH7SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH7SEL), uint32_t) & BM_FTM_PWMLOAD_CH7SEL)
bogdanm 82:6473597d706e 6531
bogdanm 82:6473597d706e 6532 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6533 //! @brief Set the CH7SEL field to a new value.
bogdanm 82:6473597d706e 6534 #define BW_FTM_PWMLOAD_CH7SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL) = (v))
bogdanm 82:6473597d706e 6535 #endif
bogdanm 82:6473597d706e 6536 //@}
bogdanm 82:6473597d706e 6537
bogdanm 82:6473597d706e 6538 /*!
bogdanm 82:6473597d706e 6539 * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
bogdanm 82:6473597d706e 6540 *
bogdanm 82:6473597d706e 6541 * Enables the loading of the MOD, CNTIN, and CV registers with the values of
bogdanm 82:6473597d706e 6542 * their write buffers.
bogdanm 82:6473597d706e 6543 *
bogdanm 82:6473597d706e 6544 * Values:
bogdanm 82:6473597d706e 6545 * - 0 - Loading updated values is disabled.
bogdanm 82:6473597d706e 6546 * - 1 - Loading updated values is enabled.
bogdanm 82:6473597d706e 6547 */
bogdanm 82:6473597d706e 6548 //@{
bogdanm 82:6473597d706e 6549 #define BP_FTM_PWMLOAD_LDOK (9U) //!< Bit position for FTM_PWMLOAD_LDOK.
bogdanm 82:6473597d706e 6550 #define BM_FTM_PWMLOAD_LDOK (0x00000200U) //!< Bit mask for FTM_PWMLOAD_LDOK.
bogdanm 82:6473597d706e 6551 #define BS_FTM_PWMLOAD_LDOK (1U) //!< Bit field size in bits for FTM_PWMLOAD_LDOK.
bogdanm 82:6473597d706e 6552
bogdanm 82:6473597d706e 6553 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6554 //! @brief Read current value of the FTM_PWMLOAD_LDOK field.
bogdanm 82:6473597d706e 6555 #define BR_FTM_PWMLOAD_LDOK(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK))
bogdanm 82:6473597d706e 6556 #endif
bogdanm 82:6473597d706e 6557
bogdanm 82:6473597d706e 6558 //! @brief Format value for bitfield FTM_PWMLOAD_LDOK.
bogdanm 82:6473597d706e 6559 #define BF_FTM_PWMLOAD_LDOK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_LDOK), uint32_t) & BM_FTM_PWMLOAD_LDOK)
bogdanm 82:6473597d706e 6560
bogdanm 82:6473597d706e 6561 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6562 //! @brief Set the LDOK field to a new value.
bogdanm 82:6473597d706e 6563 #define BW_FTM_PWMLOAD_LDOK(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK) = (v))
bogdanm 82:6473597d706e 6564 #endif
bogdanm 82:6473597d706e 6565 //@}
bogdanm 82:6473597d706e 6566
bogdanm 82:6473597d706e 6567 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 6568 // hw_ftm_t - module struct
bogdanm 82:6473597d706e 6569 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 6570 /*!
bogdanm 82:6473597d706e 6571 * @brief All FTM module registers.
bogdanm 82:6473597d706e 6572 */
bogdanm 82:6473597d706e 6573 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 6574 #pragma pack(1)
bogdanm 82:6473597d706e 6575 typedef struct _hw_ftm
bogdanm 82:6473597d706e 6576 {
bogdanm 82:6473597d706e 6577 __IO hw_ftm_sc_t SC; //!< [0x0] Status And Control
bogdanm 82:6473597d706e 6578 __IO hw_ftm_cnt_t CNT; //!< [0x4] Counter
bogdanm 82:6473597d706e 6579 __IO hw_ftm_mod_t MOD; //!< [0x8] Modulo
bogdanm 82:6473597d706e 6580 struct {
bogdanm 82:6473597d706e 6581 __IO hw_ftm_cnsc_t CnSC; //!< [0xC] Channel (n) Status And Control
bogdanm 82:6473597d706e 6582 __IO hw_ftm_cnv_t CnV; //!< [0x10] Channel (n) Value
bogdanm 82:6473597d706e 6583 } CONTROLS[8];
bogdanm 82:6473597d706e 6584 __IO hw_ftm_cntin_t CNTIN; //!< [0x4C] Counter Initial Value
bogdanm 82:6473597d706e 6585 __IO hw_ftm_status_t STATUS; //!< [0x50] Capture And Compare Status
bogdanm 82:6473597d706e 6586 __IO hw_ftm_mode_t MODE; //!< [0x54] Features Mode Selection
bogdanm 82:6473597d706e 6587 __IO hw_ftm_sync_t SYNC; //!< [0x58] Synchronization
bogdanm 82:6473597d706e 6588 __IO hw_ftm_outinit_t OUTINIT; //!< [0x5C] Initial State For Channels Output
bogdanm 82:6473597d706e 6589 __IO hw_ftm_outmask_t OUTMASK; //!< [0x60] Output Mask
bogdanm 82:6473597d706e 6590 __IO hw_ftm_combine_t COMBINE; //!< [0x64] Function For Linked Channels
bogdanm 82:6473597d706e 6591 __IO hw_ftm_deadtime_t DEADTIME; //!< [0x68] Deadtime Insertion Control
bogdanm 82:6473597d706e 6592 __IO hw_ftm_exttrig_t EXTTRIG; //!< [0x6C] FTM External Trigger
bogdanm 82:6473597d706e 6593 __IO hw_ftm_pol_t POL; //!< [0x70] Channels Polarity
bogdanm 82:6473597d706e 6594 __IO hw_ftm_fms_t FMS; //!< [0x74] Fault Mode Status
bogdanm 82:6473597d706e 6595 __IO hw_ftm_filter_t FILTER; //!< [0x78] Input Capture Filter Control
bogdanm 82:6473597d706e 6596 __IO hw_ftm_fltctrl_t FLTCTRL; //!< [0x7C] Fault Control
bogdanm 82:6473597d706e 6597 __IO hw_ftm_qdctrl_t QDCTRL; //!< [0x80] Quadrature Decoder Control And Status
bogdanm 82:6473597d706e 6598 __IO hw_ftm_conf_t CONF; //!< [0x84] Configuration
bogdanm 82:6473597d706e 6599 __IO hw_ftm_fltpol_t FLTPOL; //!< [0x88] FTM Fault Input Polarity
bogdanm 82:6473597d706e 6600 __IO hw_ftm_synconf_t SYNCONF; //!< [0x8C] Synchronization Configuration
bogdanm 82:6473597d706e 6601 __IO hw_ftm_invctrl_t INVCTRL; //!< [0x90] FTM Inverting Control
bogdanm 82:6473597d706e 6602 __IO hw_ftm_swoctrl_t SWOCTRL; //!< [0x94] FTM Software Output Control
bogdanm 82:6473597d706e 6603 __IO hw_ftm_pwmload_t PWMLOAD; //!< [0x98] FTM PWM Load
bogdanm 82:6473597d706e 6604 } hw_ftm_t;
bogdanm 82:6473597d706e 6605 #pragma pack()
bogdanm 82:6473597d706e 6606
bogdanm 82:6473597d706e 6607 //! @brief Macro to access all FTM registers.
bogdanm 82:6473597d706e 6608 //! @param x FTM instance number.
bogdanm 82:6473597d706e 6609 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 6610 //! use the '&' operator, like <code>&HW_FTM(0)</code>.
bogdanm 82:6473597d706e 6611 #define HW_FTM(x) (*(hw_ftm_t *) REGS_FTM_BASE(x))
bogdanm 82:6473597d706e 6612 #endif
bogdanm 82:6473597d706e 6613
bogdanm 82:6473597d706e 6614 #endif // __HW_FTM_REGISTERS_H__
bogdanm 82:6473597d706e 6615 // v22/130726/0.9
bogdanm 82:6473597d706e 6616 // EOF