Ken Todotani / Mbed 2 deprecated DMA_M2M

Memory to Memory DMA demo from CMSIS example. This demo execute 1000 times of 32 word memory to memory DMA (copy), and also measures number of dummy loop execution during DMA cylcles. Line 56 of "DMA_M2M.c" can change DMA source. where; 1)static : source is SRAM 2)const : source is Flash ROM

Dependencies:   mbed

CMSIS_Lib/lpc17xx_clkpwr.h@0:692bf16d1455, 2010-11-14 (annotated)

Committer:
todotani
Date:
Sun Nov 14 03:26:04 2010 +0000
Revision:
0:692bf16d1455
2010/11/14

Who changed what in which revision?

UserRevisionLine numberNew contents of line
todotani 0:692bf16d1455 1 /***********************************************************************//**
todotani 0:692bf16d1455 2 * @file lpc17xx_clkpwr.h
todotani 0:692bf16d1455 3 * @brief Contains all macro definitions and function prototypes
todotani 0:692bf16d1455 4 * support for Clock and Power Control firmware library on LPC17xx
todotani 0:692bf16d1455 5 * @version 2.0
todotani 0:692bf16d1455 6 * @date 21. May. 2010
todotani 0:692bf16d1455 7 * @author NXP MCU SW Application Team
todotani 0:692bf16d1455 8 **************************************************************************
todotani 0:692bf16d1455 9 * Software that is described herein is for illustrative purposes only
todotani 0:692bf16d1455 10 * which provides customers with programming information regarding the
todotani 0:692bf16d1455 11 * products. This software is supplied "AS IS" without any warranties.
todotani 0:692bf16d1455 12 * NXP Semiconductors assumes no responsibility or liability for the
todotani 0:692bf16d1455 13 * use of the software, conveys no license or title under any patent,
todotani 0:692bf16d1455 14 * copyright, or mask work right to the product. NXP Semiconductors
todotani 0:692bf16d1455 15 * reserves the right to make changes in the software without
todotani 0:692bf16d1455 16 * notification. NXP Semiconductors also make no representation or
todotani 0:692bf16d1455 17 * warranty that such application will be suitable for the specified
todotani 0:692bf16d1455 18 * use without further testing or modification.
todotani 0:692bf16d1455 19 **************************************************************************/
todotani 0:692bf16d1455 20
todotani 0:692bf16d1455 21 /* Peripheral group ----------------------------------------------------------- */
todotani 0:692bf16d1455 22 /** @defgroup CLKPWR CLKPWR
todotani 0:692bf16d1455 23 * @ingroup LPC1700CMSIS_FwLib_Drivers
todotani 0:692bf16d1455 24 * @{
todotani 0:692bf16d1455 25 */
todotani 0:692bf16d1455 26
todotani 0:692bf16d1455 27 #ifndef LPC17XX_CLKPWR_H_
todotani 0:692bf16d1455 28 #define LPC17XX_CLKPWR_H_
todotani 0:692bf16d1455 29
todotani 0:692bf16d1455 30 /* Includes ------------------------------------------------------------------- */
todotani 0:692bf16d1455 31 #include "LPC17xx.h"
todotani 0:692bf16d1455 32 #include "lpc_types.h"
todotani 0:692bf16d1455 33
todotani 0:692bf16d1455 34 #ifdef __cplusplus
todotani 0:692bf16d1455 35 extern "C"
todotani 0:692bf16d1455 36 {
todotani 0:692bf16d1455 37 #endif
todotani 0:692bf16d1455 38
todotani 0:692bf16d1455 39 /* Public Macros -------------------------------------------------------------- */
todotani 0:692bf16d1455 40 /** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
todotani 0:692bf16d1455 41 * @{
todotani 0:692bf16d1455 42 */
todotani 0:692bf16d1455 43
todotani 0:692bf16d1455 44 /**********************************************************************
todotani 0:692bf16d1455 45 * Peripheral Clock Selection Definitions
todotani 0:692bf16d1455 46 **********************************************************************/
todotani 0:692bf16d1455 47 /** Peripheral clock divider bit position for WDT */
todotani 0:692bf16d1455 48 #define CLKPWR_PCLKSEL_WDT ((uint32_t)(0))
todotani 0:692bf16d1455 49 /** Peripheral clock divider bit position for TIMER0 */
todotani 0:692bf16d1455 50 #define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2))
todotani 0:692bf16d1455 51 /** Peripheral clock divider bit position for TIMER1 */
todotani 0:692bf16d1455 52 #define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4))
todotani 0:692bf16d1455 53 /** Peripheral clock divider bit position for UART0 */
todotani 0:692bf16d1455 54 #define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6))
todotani 0:692bf16d1455 55 /** Peripheral clock divider bit position for UART1 */
todotani 0:692bf16d1455 56 #define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8))
todotani 0:692bf16d1455 57 /** Peripheral clock divider bit position for PWM1 */
todotani 0:692bf16d1455 58 #define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12))
todotani 0:692bf16d1455 59 /** Peripheral clock divider bit position for I2C0 */
todotani 0:692bf16d1455 60 #define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14))
todotani 0:692bf16d1455 61 /** Peripheral clock divider bit position for SPI */
todotani 0:692bf16d1455 62 #define CLKPWR_PCLKSEL_SPI ((uint32_t)(16))
todotani 0:692bf16d1455 63 /** Peripheral clock divider bit position for SSP1 */
todotani 0:692bf16d1455 64 #define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20))
todotani 0:692bf16d1455 65 /** Peripheral clock divider bit position for DAC */
todotani 0:692bf16d1455 66 #define CLKPWR_PCLKSEL_DAC ((uint32_t)(22))
todotani 0:692bf16d1455 67 /** Peripheral clock divider bit position for ADC */
todotani 0:692bf16d1455 68 #define CLKPWR_PCLKSEL_ADC ((uint32_t)(24))
todotani 0:692bf16d1455 69 /** Peripheral clock divider bit position for CAN1 */
todotani 0:692bf16d1455 70 #define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26))
todotani 0:692bf16d1455 71 /** Peripheral clock divider bit position for CAN2 */
todotani 0:692bf16d1455 72 #define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28))
todotani 0:692bf16d1455 73 /** Peripheral clock divider bit position for ACF */
todotani 0:692bf16d1455 74 #define CLKPWR_PCLKSEL_ACF ((uint32_t)(30))
todotani 0:692bf16d1455 75 /** Peripheral clock divider bit position for QEI */
todotani 0:692bf16d1455 76 #define CLKPWR_PCLKSEL_QEI ((uint32_t)(32))
todotani 0:692bf16d1455 77 /** Peripheral clock divider bit position for PCB */
todotani 0:692bf16d1455 78 #define CLKPWR_PCLKSEL_PCB ((uint32_t)(36))
todotani 0:692bf16d1455 79 /** Peripheral clock divider bit position for I2C1 */
todotani 0:692bf16d1455 80 #define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38))
todotani 0:692bf16d1455 81 /** Peripheral clock divider bit position for SSP0 */
todotani 0:692bf16d1455 82 #define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42))
todotani 0:692bf16d1455 83 /** Peripheral clock divider bit position for TIMER2 */
todotani 0:692bf16d1455 84 #define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44))
todotani 0:692bf16d1455 85 /** Peripheral clock divider bit position for TIMER3 */
todotani 0:692bf16d1455 86 #define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46))
todotani 0:692bf16d1455 87 /** Peripheral clock divider bit position for UART2 */
todotani 0:692bf16d1455 88 #define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48))
todotani 0:692bf16d1455 89 /** Peripheral clock divider bit position for UART3 */
todotani 0:692bf16d1455 90 #define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50))
todotani 0:692bf16d1455 91 /** Peripheral clock divider bit position for I2C2 */
todotani 0:692bf16d1455 92 #define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52))
todotani 0:692bf16d1455 93 /** Peripheral clock divider bit position for I2S */
todotani 0:692bf16d1455 94 #define CLKPWR_PCLKSEL_I2S ((uint32_t)(54))
todotani 0:692bf16d1455 95 /** Peripheral clock divider bit position for RIT */
todotani 0:692bf16d1455 96 #define CLKPWR_PCLKSEL_RIT ((uint32_t)(58))
todotani 0:692bf16d1455 97 /** Peripheral clock divider bit position for SYSCON */
todotani 0:692bf16d1455 98 #define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60))
todotani 0:692bf16d1455 99 /** Peripheral clock divider bit position for MC */
todotani 0:692bf16d1455 100 #define CLKPWR_PCLKSEL_MC ((uint32_t)(62))
todotani 0:692bf16d1455 101
todotani 0:692bf16d1455 102 /** Macro for Peripheral Clock Selection register bit values
todotani 0:692bf16d1455 103 * Note: When CCLK_DIV_8, Peripheral�s clock is selected to
todotani 0:692bf16d1455 104 * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
todotani 0:692bf16d1455 105 * when �11�selects PCLK_xyz = CCLK/6 */
todotani 0:692bf16d1455 106 /* Peripheral clock divider is set to 4 from CCLK */
todotani 0:692bf16d1455 107 #define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0))
todotani 0:692bf16d1455 108 /** Peripheral clock divider is the same with CCLK */
todotani 0:692bf16d1455 109 #define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1))
todotani 0:692bf16d1455 110 /** Peripheral clock divider is set to 2 from CCLK */
todotani 0:692bf16d1455 111 #define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2))
todotani 0:692bf16d1455 112
todotani 0:692bf16d1455 113
todotani 0:692bf16d1455 114 /********************************************************************
todotani 0:692bf16d1455 115 * Power Control for Peripherals Definitions
todotani 0:692bf16d1455 116 **********************************************************************/
todotani 0:692bf16d1455 117 /** Timer/Counter 0 power/clock control bit */
todotani 0:692bf16d1455 118 #define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
todotani 0:692bf16d1455 119 /* Timer/Counter 1 power/clock control bit */
todotani 0:692bf16d1455 120 #define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
todotani 0:692bf16d1455 121 /** UART0 power/clock control bit */
todotani 0:692bf16d1455 122 #define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
todotani 0:692bf16d1455 123 /** UART1 power/clock control bit */
todotani 0:692bf16d1455 124 #define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
todotani 0:692bf16d1455 125 /** PWM1 power/clock control bit */
todotani 0:692bf16d1455 126 #define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
todotani 0:692bf16d1455 127 /** The I2C0 interface power/clock control bit */
todotani 0:692bf16d1455 128 #define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
todotani 0:692bf16d1455 129 /** The SPI interface power/clock control bit */
todotani 0:692bf16d1455 130 #define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8))
todotani 0:692bf16d1455 131 /** The RTC power/clock control bit */
todotani 0:692bf16d1455 132 #define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
todotani 0:692bf16d1455 133 /** The SSP1 interface power/clock control bit */
todotani 0:692bf16d1455 134 #define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
todotani 0:692bf16d1455 135 /** A/D converter 0 (ADC0) power/clock control bit */
todotani 0:692bf16d1455 136 #define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12))
todotani 0:692bf16d1455 137 /** CAN Controller 1 power/clock control bit */
todotani 0:692bf16d1455 138 #define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
todotani 0:692bf16d1455 139 /** CAN Controller 2 power/clock control bit */
todotani 0:692bf16d1455 140 #define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
todotani 0:692bf16d1455 141 /** GPIO power/clock control bit */
todotani 0:692bf16d1455 142 #define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
todotani 0:692bf16d1455 143 /** Repetitive Interrupt Timer power/clock control bit */
todotani 0:692bf16d1455 144 #define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16))
todotani 0:692bf16d1455 145 /** Motor Control PWM */
todotani 0:692bf16d1455 146 #define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17))
todotani 0:692bf16d1455 147 /** Quadrature Encoder Interface power/clock control bit */
todotani 0:692bf16d1455 148 #define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
todotani 0:692bf16d1455 149 /** The I2C1 interface power/clock control bit */
todotani 0:692bf16d1455 150 #define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
todotani 0:692bf16d1455 151 /** The SSP0 interface power/clock control bit */
todotani 0:692bf16d1455 152 #define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
todotani 0:692bf16d1455 153 /** Timer 2 power/clock control bit */
todotani 0:692bf16d1455 154 #define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
todotani 0:692bf16d1455 155 /** Timer 3 power/clock control bit */
todotani 0:692bf16d1455 156 #define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
todotani 0:692bf16d1455 157 /** UART 2 power/clock control bit */
todotani 0:692bf16d1455 158 #define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
todotani 0:692bf16d1455 159 /** UART 3 power/clock control bit */
todotani 0:692bf16d1455 160 #define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
todotani 0:692bf16d1455 161 /** I2C interface 2 power/clock control bit */
todotani 0:692bf16d1455 162 #define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
todotani 0:692bf16d1455 163 /** I2S interface power/clock control bit*/
todotani 0:692bf16d1455 164 #define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
todotani 0:692bf16d1455 165 /** GP DMA function power/clock control bit*/
todotani 0:692bf16d1455 166 #define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
todotani 0:692bf16d1455 167 /** Ethernet block power/clock control bit*/
todotani 0:692bf16d1455 168 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
todotani 0:692bf16d1455 169 /** USB interface power/clock control bit*/
todotani 0:692bf16d1455 170 #define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
todotani 0:692bf16d1455 171
todotani 0:692bf16d1455 172
todotani 0:692bf16d1455 173 /**
todotani 0:692bf16d1455 174 * @}
todotani 0:692bf16d1455 175 */
todotani 0:692bf16d1455 176 /* Private Macros ------------------------------------------------------------- */
todotani 0:692bf16d1455 177 /** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros
todotani 0:692bf16d1455 178 * @{
todotani 0:692bf16d1455 179 */
todotani 0:692bf16d1455 180
todotani 0:692bf16d1455 181 /* --------------------- BIT DEFINITIONS -------------------------------------- */
todotani 0:692bf16d1455 182 /*********************************************************************//**
todotani 0:692bf16d1455 183 * Macro defines for Clock Source Select Register
todotani 0:692bf16d1455 184 **********************************************************************/
todotani 0:692bf16d1455 185 /** Internal RC oscillator */
todotani 0:692bf16d1455 186 #define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00))
todotani 0:692bf16d1455 187 /** Main oscillator */
todotani 0:692bf16d1455 188 #define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01))
todotani 0:692bf16d1455 189 /** RTC oscillator */
todotani 0:692bf16d1455 190 #define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02))
todotani 0:692bf16d1455 191 /** Clock source selection bit mask */
todotani 0:692bf16d1455 192 #define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03))
todotani 0:692bf16d1455 193
todotani 0:692bf16d1455 194 /*********************************************************************//**
todotani 0:692bf16d1455 195 * Macro defines for Clock Output Configuration Register
todotani 0:692bf16d1455 196 **********************************************************************/
todotani 0:692bf16d1455 197 /* Clock Output Configuration register definition */
todotani 0:692bf16d1455 198 /** Selects the CPU clock as the CLKOUT source */
todotani 0:692bf16d1455 199 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00))
todotani 0:692bf16d1455 200 /** Selects the main oscillator as the CLKOUT source */
todotani 0:692bf16d1455 201 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01))
todotani 0:692bf16d1455 202 /** Selects the Internal RC oscillator as the CLKOUT source */
todotani 0:692bf16d1455 203 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02))
todotani 0:692bf16d1455 204 /** Selects the USB clock as the CLKOUT source */
todotani 0:692bf16d1455 205 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03))
todotani 0:692bf16d1455 206 /** Selects the RTC oscillator as the CLKOUT source */
todotani 0:692bf16d1455 207 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04))
todotani 0:692bf16d1455 208 /** Integer value to divide the output clock by, minus one */
todotani 0:692bf16d1455 209 #define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4))
todotani 0:692bf16d1455 210 /** CLKOUT enable control */
todotani 0:692bf16d1455 211 #define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8))
todotani 0:692bf16d1455 212 /** CLKOUT activity indication */
todotani 0:692bf16d1455 213 #define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9))
todotani 0:692bf16d1455 214 /** Clock source selection bit mask */
todotani 0:692bf16d1455 215 #define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF))
todotani 0:692bf16d1455 216
todotani 0:692bf16d1455 217 /*********************************************************************//**
todotani 0:692bf16d1455 218 * Macro defines for PPL0 Control Register
todotani 0:692bf16d1455 219 **********************************************************************/
todotani 0:692bf16d1455 220 /** PLL 0 control enable */
todotani 0:692bf16d1455 221 #define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01))
todotani 0:692bf16d1455 222 /** PLL 0 control connect */
todotani 0:692bf16d1455 223 #define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02))
todotani 0:692bf16d1455 224 /** PLL 0 control bit mask */
todotani 0:692bf16d1455 225 #define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03))
todotani 0:692bf16d1455 226
todotani 0:692bf16d1455 227 /*********************************************************************//**
todotani 0:692bf16d1455 228 * Macro defines for PPL0 Configuration Register
todotani 0:692bf16d1455 229 **********************************************************************/
todotani 0:692bf16d1455 230 /** PLL 0 Configuration MSEL field */
todotani 0:692bf16d1455 231 #define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF))
todotani 0:692bf16d1455 232 /** PLL 0 Configuration NSEL field */
todotani 0:692bf16d1455 233 #define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000))
todotani 0:692bf16d1455 234 /** PLL 0 Configuration bit mask */
todotani 0:692bf16d1455 235 #define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF))
todotani 0:692bf16d1455 236
todotani 0:692bf16d1455 237
todotani 0:692bf16d1455 238 /*********************************************************************//**
todotani 0:692bf16d1455 239 * Macro defines for PPL0 Status Register
todotani 0:692bf16d1455 240 **********************************************************************/
todotani 0:692bf16d1455 241 /** PLL 0 MSEL value */
todotani 0:692bf16d1455 242 #define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF))
todotani 0:692bf16d1455 243 /** PLL NSEL get value */
todotani 0:692bf16d1455 244 #define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF))
todotani 0:692bf16d1455 245 /** PLL status enable bit */
todotani 0:692bf16d1455 246 #define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24))
todotani 0:692bf16d1455 247 /** PLL status Connect bit */
todotani 0:692bf16d1455 248 #define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25))
todotani 0:692bf16d1455 249 /** PLL status lock */
todotani 0:692bf16d1455 250 #define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26))
todotani 0:692bf16d1455 251
todotani 0:692bf16d1455 252 /*********************************************************************//**
todotani 0:692bf16d1455 253 * Macro defines for PPL0 Feed Register
todotani 0:692bf16d1455 254 **********************************************************************/
todotani 0:692bf16d1455 255 /** PLL0 Feed bit mask */
todotani 0:692bf16d1455 256 #define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF)
todotani 0:692bf16d1455 257
todotani 0:692bf16d1455 258 /*********************************************************************//**
todotani 0:692bf16d1455 259 * Macro defines for PLL1 Control Register
todotani 0:692bf16d1455 260 **********************************************************************/
todotani 0:692bf16d1455 261 /** USB PLL control enable */
todotani 0:692bf16d1455 262 #define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01))
todotani 0:692bf16d1455 263 /** USB PLL control connect */
todotani 0:692bf16d1455 264 #define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02))
todotani 0:692bf16d1455 265 /** USB PLL control bit mask */
todotani 0:692bf16d1455 266 #define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03))
todotani 0:692bf16d1455 267
todotani 0:692bf16d1455 268 /*********************************************************************//**
todotani 0:692bf16d1455 269 * Macro defines for PLL1 Configuration Register
todotani 0:692bf16d1455 270 **********************************************************************/
todotani 0:692bf16d1455 271 /** USB PLL MSEL set value */
todotani 0:692bf16d1455 272 #define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F))
todotani 0:692bf16d1455 273 /** USB PLL PSEL set value */
todotani 0:692bf16d1455 274 #define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5))
todotani 0:692bf16d1455 275 /** USB PLL configuration bit mask */
todotani 0:692bf16d1455 276 #define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F))
todotani 0:692bf16d1455 277
todotani 0:692bf16d1455 278 /*********************************************************************//**
todotani 0:692bf16d1455 279 * Macro defines for PLL1 Status Register
todotani 0:692bf16d1455 280 **********************************************************************/
todotani 0:692bf16d1455 281 /** USB PLL MSEL get value */
todotani 0:692bf16d1455 282 #define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F))
todotani 0:692bf16d1455 283 /** USB PLL PSEL get value */
todotani 0:692bf16d1455 284 #define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03))
todotani 0:692bf16d1455 285 /** USB PLL status enable bit */
todotani 0:692bf16d1455 286 #define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8))
todotani 0:692bf16d1455 287 /** USB PLL status Connect bit */
todotani 0:692bf16d1455 288 #define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9))
todotani 0:692bf16d1455 289 /** USB PLL status lock */
todotani 0:692bf16d1455 290 #define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10))
todotani 0:692bf16d1455 291
todotani 0:692bf16d1455 292 /*********************************************************************//**
todotani 0:692bf16d1455 293 * Macro defines for PLL1 Feed Register
todotani 0:692bf16d1455 294 **********************************************************************/
todotani 0:692bf16d1455 295 /** PLL1 Feed bit mask */
todotani 0:692bf16d1455 296 #define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF)
todotani 0:692bf16d1455 297
todotani 0:692bf16d1455 298 /*********************************************************************//**
todotani 0:692bf16d1455 299 * Macro defines for CPU Clock Configuration Register
todotani 0:692bf16d1455 300 **********************************************************************/
todotani 0:692bf16d1455 301 /** CPU Clock configuration bit mask */
todotani 0:692bf16d1455 302 #define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF))
todotani 0:692bf16d1455 303
todotani 0:692bf16d1455 304 /*********************************************************************//**
todotani 0:692bf16d1455 305 * Macro defines for USB Clock Configuration Register
todotani 0:692bf16d1455 306 **********************************************************************/
todotani 0:692bf16d1455 307 /** USB Clock Configuration bit mask */
todotani 0:692bf16d1455 308 #define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F))
todotani 0:692bf16d1455 309
todotani 0:692bf16d1455 310 /*********************************************************************//**
todotani 0:692bf16d1455 311 * Macro defines for IRC Trim Register
todotani 0:692bf16d1455 312 **********************************************************************/
todotani 0:692bf16d1455 313 /** IRC Trim bit mask */
todotani 0:692bf16d1455 314 #define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F))
todotani 0:692bf16d1455 315
todotani 0:692bf16d1455 316 /*********************************************************************//**
todotani 0:692bf16d1455 317 * Macro defines for Peripheral Clock Selection Register 0 and 1
todotani 0:692bf16d1455 318 **********************************************************************/
todotani 0:692bf16d1455 319 /** Peripheral Clock Selection 0 mask bit */
todotani 0:692bf16d1455 320 #define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF))
todotani 0:692bf16d1455 321 /** Peripheral Clock Selection 1 mask bit */
todotani 0:692bf16d1455 322 #define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3))
todotani 0:692bf16d1455 323 /** Macro to set peripheral clock of each type
todotani 0:692bf16d1455 324 * p: position of two bits that hold divider of peripheral clock
todotani 0:692bf16d1455 325 * n: value of divider of peripheral clock to be set */
todotani 0:692bf16d1455 326 #define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n)
todotani 0:692bf16d1455 327 /** Macro to mask peripheral clock of each type */
todotani 0:692bf16d1455 328 #define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03)
todotani 0:692bf16d1455 329 /** Macro to get peripheral clock of each type */
todotani 0:692bf16d1455 330 #define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03))
todotani 0:692bf16d1455 331
todotani 0:692bf16d1455 332 /*********************************************************************//**
todotani 0:692bf16d1455 333 * Macro defines for Power Mode Control Register
todotani 0:692bf16d1455 334 **********************************************************************/
todotani 0:692bf16d1455 335 /** Power mode control bit 0 */
todotani 0:692bf16d1455 336 #define CLKPWR_PCON_PM0 ((uint32_t)(1<<0))
todotani 0:692bf16d1455 337 /** Power mode control bit 1 */
todotani 0:692bf16d1455 338 #define CLKPWR_PCON_PM1 ((uint32_t)(1<<1))
todotani 0:692bf16d1455 339 /** Brown-Out Reduced Power Mode */
todotani 0:692bf16d1455 340 #define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2))
todotani 0:692bf16d1455 341 /** Brown-Out Global Disable */
todotani 0:692bf16d1455 342 #define CLKPWR_PCON_BOGD ((uint32_t)(1<<3))
todotani 0:692bf16d1455 343 /** Brown Out Reset Disable */
todotani 0:692bf16d1455 344 #define CLKPWR_PCON_BORD ((uint32_t)(1<<4))
todotani 0:692bf16d1455 345 /** Sleep Mode entry flag */
todotani 0:692bf16d1455 346 #define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8))
todotani 0:692bf16d1455 347 /** Deep Sleep entry flag */
todotani 0:692bf16d1455 348 #define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9))
todotani 0:692bf16d1455 349 /** Power-down entry flag */
todotani 0:692bf16d1455 350 #define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10))
todotani 0:692bf16d1455 351 /** Deep Power-down entry flag */
todotani 0:692bf16d1455 352 #define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11))
todotani 0:692bf16d1455 353
todotani 0:692bf16d1455 354 /*********************************************************************//**
todotani 0:692bf16d1455 355 * Macro defines for Power Control for Peripheral Register
todotani 0:692bf16d1455 356 **********************************************************************/
todotani 0:692bf16d1455 357 /** Power Control for Peripherals bit mask */
todotani 0:692bf16d1455 358 #define CLKPWR_PCONP_BITMASK 0xEFEFF7DE
todotani 0:692bf16d1455 359
todotani 0:692bf16d1455 360 /**
todotani 0:692bf16d1455 361 * @}
todotani 0:692bf16d1455 362 */
todotani 0:692bf16d1455 363
todotani 0:692bf16d1455 364
todotani 0:692bf16d1455 365 /* Public Functions ----------------------------------------------------------- */
todotani 0:692bf16d1455 366 /** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
todotani 0:692bf16d1455 367 * @{
todotani 0:692bf16d1455 368 */
todotani 0:692bf16d1455 369
todotani 0:692bf16d1455 370 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
todotani 0:692bf16d1455 371 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
todotani 0:692bf16d1455 372 uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
todotani 0:692bf16d1455 373 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
todotani 0:692bf16d1455 374 void CLKPWR_Sleep(void);
todotani 0:692bf16d1455 375 void CLKPWR_DeepSleep(void);
todotani 0:692bf16d1455 376 void CLKPWR_PowerDown(void);
todotani 0:692bf16d1455 377 void CLKPWR_DeepPowerDown(void);
todotani 0:692bf16d1455 378
todotani 0:692bf16d1455 379 /**
todotani 0:692bf16d1455 380 * @}
todotani 0:692bf16d1455 381 */
todotani 0:692bf16d1455 382
todotani 0:692bf16d1455 383
todotani 0:692bf16d1455 384 #ifdef __cplusplus
todotani 0:692bf16d1455 385 }
todotani 0:692bf16d1455 386 #endif
todotani 0:692bf16d1455 387
todotani 0:692bf16d1455 388 #endif /* LPC17XX_CLKPWR_H_ */
todotani 0:692bf16d1455 389
todotani 0:692bf16d1455 390 /**
todotani 0:692bf16d1455 391 * @}
todotani 0:692bf16d1455 392 */
todotani 0:692bf16d1455 393
todotani 0:692bf16d1455 394 /* --------------------------------- End Of File ------------------------------ */