Ricardo Benitez / mbed

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Fork of mbed by mbed official

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal_access_control.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 82:6473597d706e 6 * are permitted provided that the following conditions are met:
bogdanm 82:6473597d706e 7 *
bogdanm 82:6473597d706e 8 * o Redistributions of source code must retain the above copyright notice, this list
bogdanm 82:6473597d706e 9 * of conditions and the following disclaimer.
bogdanm 82:6473597d706e 10 *
bogdanm 82:6473597d706e 11 * o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 82:6473597d706e 12 * list of conditions and the following disclaimer in the documentation and/or
bogdanm 82:6473597d706e 13 * other materials provided with the distribution.
bogdanm 82:6473597d706e 14 *
bogdanm 82:6473597d706e 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 82:6473597d706e 16 * contributors may be used to endorse or promote products derived from this
bogdanm 82:6473597d706e 17 * software without specific prior written permission.
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 82:6473597d706e 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 82:6473597d706e 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 82:6473597d706e 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 82:6473597d706e 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 82:6473597d706e 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 82:6473597d706e 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 82:6473597d706e 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 82:6473597d706e 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 82:6473597d706e 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 82:6473597d706e 29 */
bogdanm 82:6473597d706e 30 #if !defined(__FSL_RTC_HAL_ACCESS_CONTROL_H__)
bogdanm 82:6473597d706e 31 #define __FSL_RTC_HAL_ACCESS_CONTROL_H__
bogdanm 82:6473597d706e 32
bogdanm 82:6473597d706e 33
bogdanm 82:6473597d706e 34 #include "fsl_rtc_features.h"
bogdanm 82:6473597d706e 35 #include "fsl_device_registers.h"
bogdanm 82:6473597d706e 36 #include <stdint.h>
bogdanm 82:6473597d706e 37 #include <stdbool.h>
bogdanm 82:6473597d706e 38
bogdanm 82:6473597d706e 39
bogdanm 82:6473597d706e 40
bogdanm 82:6473597d706e 41 /*! @addtogroup rtc_hal*/
bogdanm 82:6473597d706e 42 /*! @{*/
bogdanm 82:6473597d706e 43
bogdanm 82:6473597d706e 44
bogdanm 82:6473597d706e 45 /*******************************************************************************
bogdanm 82:6473597d706e 46 * Definitions
bogdanm 82:6473597d706e 47 ******************************************************************************/
bogdanm 82:6473597d706e 48
bogdanm 82:6473597d706e 49 typedef struct rtc_hal_access_control_config
bogdanm 82:6473597d706e 50 {
bogdanm 82:6473597d706e 51 /*! Set/clear any of the following bitfields to enable/disable the
bogdanm 82:6473597d706e 52 * respective interrupts.\n\n
bogdanm 82:6473597d706e 53 * IERW: Interrupt Enable Register Write \n
bogdanm 82:6473597d706e 54 * LRW: Lock Register Write \n
bogdanm 82:6473597d706e 55 * SRW: Status Register Write \n
bogdanm 82:6473597d706e 56 * CRW: Control Register Write \n
bogdanm 82:6473597d706e 57 * TCRW: Time Compensation Register Write \n
bogdanm 82:6473597d706e 58 * TARW: Time Alarm Register Write \n
bogdanm 82:6473597d706e 59 * TPRW: Time Prescaler Register Write \n
bogdanm 82:6473597d706e 60 * TSRW: Time Seconds Register Write \n
bogdanm 82:6473597d706e 61 * \n
bogdanm 82:6473597d706e 62 * For MCUs that have Tamper feature: \n
bogdanm 82:6473597d706e 63 * TIRW: Tamper Interrupt Register Write \n
bogdanm 82:6473597d706e 64 * TTRW: Tamper Trim Register Write \n
bogdanm 82:6473597d706e 65 * TDRW: Tamper Detect Register Write \n
bogdanm 82:6473597d706e 66 * TERW: Tamper Enable Register Write \n
bogdanm 82:6473597d706e 67 * TTSW: Tamper Time Seconds Write \n
bogdanm 82:6473597d706e 68 * \n
bogdanm 82:6473597d706e 69 * For MCUs that have Monotonic Counter: \n
bogdanm 82:6473597d706e 70 * MCHW: Monotonic Counter High Write \n
bogdanm 82:6473597d706e 71 * MCLW: Monotonic Counter Low Write \n
bogdanm 82:6473597d706e 72 * MERW: Monotonic Enable Register Write \n
bogdanm 82:6473597d706e 73 */
bogdanm 82:6473597d706e 74 hw_rtc_war_t writeFlags;
bogdanm 82:6473597d706e 75
bogdanm 82:6473597d706e 76 /*! Set/clear any of the following bitfields to enable/disable the
bogdanm 82:6473597d706e 77 * respective interrupts.\n\n
bogdanm 82:6473597d706e 78 * IERR: Interrupt Enable Register Read \n
bogdanm 82:6473597d706e 79 * LRR: Lock Register Read \n
bogdanm 82:6473597d706e 80 * SRR: Status Register Read \n
bogdanm 82:6473597d706e 81 * CRR: Control Register Read \n
bogdanm 82:6473597d706e 82 * TCRR: Time Compensation Register Read \n
bogdanm 82:6473597d706e 83 * TARR: Time Alarm Register Read \n
bogdanm 82:6473597d706e 84 * TPRR: Time Prescaler Register Read \n
bogdanm 82:6473597d706e 85 * TSRR: Time Seconds Register Read \n
bogdanm 82:6473597d706e 86 * \n
bogdanm 82:6473597d706e 87 * For MCUs that have Tamper feature: \n
bogdanm 82:6473597d706e 88 * TIRR: Tamper Interrupt Register Read \n
bogdanm 82:6473597d706e 89 * TTRR: Tamper Trim Register Read \n
bogdanm 82:6473597d706e 90 * TDRR: Tamper Detect Register Read \n
bogdanm 82:6473597d706e 91 * TERR: Tamper Enable Register Read \n
bogdanm 82:6473597d706e 92 * TTSR: Tamper Time Seconds Read \n
bogdanm 82:6473597d706e 93 * \n
bogdanm 82:6473597d706e 94 * For MCUs that have Monotonic Counter: \n
bogdanm 82:6473597d706e 95 * MCHR: Monotonic Counter High Read \n
bogdanm 82:6473597d706e 96 * MCLR: Monotonic Counter Low Read \n
bogdanm 82:6473597d706e 97 * MERR: Monotonic Enable Register Read \n
bogdanm 82:6473597d706e 98 */
bogdanm 82:6473597d706e 99 hw_rtc_rar_t readFlags;
bogdanm 82:6473597d706e 100
bogdanm 82:6473597d706e 101 } rtc_hal_access_control_config_t;
bogdanm 82:6473597d706e 102
bogdanm 82:6473597d706e 103
bogdanm 82:6473597d706e 104 /*******************************************************************************
bogdanm 82:6473597d706e 105 * API
bogdanm 82:6473597d706e 106 ******************************************************************************/
bogdanm 82:6473597d706e 107
bogdanm 82:6473597d706e 108 #if FSL_FEATURE_RTC_HAS_ACCESS_CONTROL
bogdanm 82:6473597d706e 109
bogdanm 82:6473597d706e 110 #if defined(__cplusplus)
bogdanm 82:6473597d706e 111 extern "C" {
bogdanm 82:6473597d706e 112 #endif
bogdanm 82:6473597d706e 113
bogdanm 82:6473597d706e 114
bogdanm 82:6473597d706e 115 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 116 /* RTC Access Control Register Reset Functions*/
bogdanm 82:6473597d706e 117 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 118
bogdanm 82:6473597d706e 119 /*! @brief Resets the RTC Write Access Register (RTC_WAR).*/
bogdanm 82:6473597d706e 120 static inline void rtc_hal_reset_reg_WAR(void)
bogdanm 82:6473597d706e 121 {
bogdanm 82:6473597d706e 122 HW_RTC_WAR_WR((uint32_t)0x0000FFFFU);
bogdanm 82:6473597d706e 123 }
bogdanm 82:6473597d706e 124
bogdanm 82:6473597d706e 125 /*! @brief Resets the RTC Read Access Register (RTC_RAR).*/
bogdanm 82:6473597d706e 126 static inline void rtc_hal_reset_reg_RAR(void)
bogdanm 82:6473597d706e 127 {
bogdanm 82:6473597d706e 128 HW_RTC_RAR_WR((uint32_t)0x0000FFFFU);
bogdanm 82:6473597d706e 129 }
bogdanm 82:6473597d706e 130
bogdanm 82:6473597d706e 131 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 132 /* RTC Access Control Configuration*/
bogdanm 82:6473597d706e 133 /*-------------------------------------------------------------------------------------------*/
bogdanm 82:6473597d706e 134
bogdanm 82:6473597d706e 135 /*! @brief Configures the read and write access controls to other module fields
bogdanm 82:6473597d706e 136 * @param flags [in] pointer to structure where configuration flags are
bogdanm 82:6473597d706e 137 * found. See the related structure for details.
bogdanm 82:6473597d706e 138 */
bogdanm 82:6473597d706e 139 static inline void rtc_hal_access_control_configuration(const rtc_hal_access_control_config_t * flags)
bogdanm 82:6473597d706e 140 {
bogdanm 82:6473597d706e 141 /* check for null pointer*/
bogdanm 82:6473597d706e 142 if(NULL == flags)
bogdanm 82:6473597d706e 143 {
bogdanm 82:6473597d706e 144 return;
bogdanm 82:6473597d706e 145 }
bogdanm 82:6473597d706e 146
bogdanm 82:6473597d706e 147 uint32_t valid_flags;
bogdanm 82:6473597d706e 148
bogdanm 82:6473597d706e 149 /* Set/clear any of the following bitfields to enable/disable the
bogdanm 82:6473597d706e 150 * respective interrupts.\n\n
bogdanm 82:6473597d706e 151 * IERW: Interrupt Enable Register Write \n
bogdanm 82:6473597d706e 152 * LRW: Lock Register Write \n
bogdanm 82:6473597d706e 153 * SRW: Status Register Write \n
bogdanm 82:6473597d706e 154 * CRW: Control Register Write \n
bogdanm 82:6473597d706e 155 * TCRW: Time Compensation Register Write \n
bogdanm 82:6473597d706e 156 * TARW: Time Alarm Register Write \n
bogdanm 82:6473597d706e 157 * TPRW: Time Prescaler Register Write \n
bogdanm 82:6473597d706e 158 * TSRW: Time Seconds Register Write \n
bogdanm 82:6473597d706e 159 * \n
bogdanm 82:6473597d706e 160 * For MCUs that have Tamper feature: \n
bogdanm 82:6473597d706e 161 * TIRW: Tamper Interrupt Register Write \n
bogdanm 82:6473597d706e 162 * TTRW: Tamper Trim Register Write \n
bogdanm 82:6473597d706e 163 * TDRW: Tamper Detect Register Write \n
bogdanm 82:6473597d706e 164 * TERW: Tamper Enable Register Write \n
bogdanm 82:6473597d706e 165 * TTSW: Tamper Time Seconds Write \n
bogdanm 82:6473597d706e 166 * \n
bogdanm 82:6473597d706e 167 * For MCUs that have Monotonic Counter: \n
bogdanm 82:6473597d706e 168 * MCHW: Monotonic Counter High Write \n
bogdanm 82:6473597d706e 169 * MCLW: Monotonic Counter Low Write \n
bogdanm 82:6473597d706e 170 * MERW: Monotonic Enable Register Write \n
bogdanm 82:6473597d706e 171 */
bogdanm 82:6473597d706e 172 valid_flags = 0;
bogdanm 82:6473597d706e 173
bogdanm 82:6473597d706e 174 #if FSL_FEATURE_RTC_HAS_MONOTONIC
bogdanm 82:6473597d706e 175 valid_flags |= (BM_RTC_WAR_MCHW | BM_RTC_WAR_MCLW | BM_RTC_WAR_MERW);
bogdanm 82:6473597d706e 176 #endif
bogdanm 82:6473597d706e 177 valid_flags |= (BM_RTC_WAR_IERW | BM_RTC_WAR_LRW | BM_RTC_WAR_SRW |
bogdanm 82:6473597d706e 178 BM_RTC_WAR_CRW | BM_RTC_WAR_TCRW | BM_RTC_WAR_TARW | BM_RTC_WAR_TPRW |
bogdanm 82:6473597d706e 179 BM_RTC_WAR_TSRW);
bogdanm 82:6473597d706e 180
bogdanm 82:6473597d706e 181 HW_RTC_WAR_WR((flags->writeFlags.U) & valid_flags);
bogdanm 82:6473597d706e 182
bogdanm 82:6473597d706e 183 /* Set/clear any of the following bitfields to enable/disable the
bogdanm 82:6473597d706e 184 * respective interrupts.\n\n
bogdanm 82:6473597d706e 185 * IERR: Interrupt Enable Register Read \n
bogdanm 82:6473597d706e 186 * LRR: Lock Register Read \n
bogdanm 82:6473597d706e 187 * SRR: Status Register Read \n
bogdanm 82:6473597d706e 188 * CRR: Control Register Read \n
bogdanm 82:6473597d706e 189 * TCRR: Time Compensation Register Read \n
bogdanm 82:6473597d706e 190 * TARR: Time Alarm Register Read \n
bogdanm 82:6473597d706e 191 * TPRR: Time Prescaler Register Read \n
bogdanm 82:6473597d706e 192 * TSRR: Time Seconds Register Read \n
bogdanm 82:6473597d706e 193 * \n
bogdanm 82:6473597d706e 194 * For MCUs that have Tamper feature: \n
bogdanm 82:6473597d706e 195 * TIRR: Tamper Interrupt Register Read \n
bogdanm 82:6473597d706e 196 * TTRR: Tamper Trim Register Read \n
bogdanm 82:6473597d706e 197 * TDRR: Tamper Detect Register Read \n
bogdanm 82:6473597d706e 198 * TERR: Tamper Enable Register Read \n
bogdanm 82:6473597d706e 199 * TTSR: Tamper Time Seconds Read \n
bogdanm 82:6473597d706e 200 * \n
bogdanm 82:6473597d706e 201 * For MCUs that have Monotonic Counter: \n
bogdanm 82:6473597d706e 202 * MCHR: Monotonic Counter High Read \n
bogdanm 82:6473597d706e 203 * MCLR: Monotonic Counter Low Read \n
bogdanm 82:6473597d706e 204 * MERR: Monotonic Enable Register Read \n
bogdanm 82:6473597d706e 205 */
bogdanm 82:6473597d706e 206 valid_flags = 0;
bogdanm 82:6473597d706e 207
bogdanm 82:6473597d706e 208 #if FSL_FEATURE_RTC_HAS_MONOTONIC
bogdanm 82:6473597d706e 209 valid_flags |= (BM_RTC_RAR_MCHR | BM_RTC_RAR_MCLR | BM_RTC_RAR_MERR);
bogdanm 82:6473597d706e 210 #endif
bogdanm 82:6473597d706e 211 valid_flags |= (BM_RTC_RAR_IERR | BM_RTC_RAR_LRR | BM_RTC_RAR_SRR |
bogdanm 82:6473597d706e 212 BM_RTC_RAR_CRR | BM_RTC_RAR_TCRR | BM_RTC_RAR_TARR | BM_RTC_RAR_TPRR |
bogdanm 82:6473597d706e 213 BM_RTC_RAR_TSRR);
bogdanm 82:6473597d706e 214
bogdanm 82:6473597d706e 215 HW_RTC_RAR_WR((flags->readFlags.U) & valid_flags);
bogdanm 82:6473597d706e 216
bogdanm 82:6473597d706e 217 }
bogdanm 82:6473597d706e 218
bogdanm 82:6473597d706e 219
bogdanm 82:6473597d706e 220 #if FSL_FEATURE_RTC_HAS_MONOTONIC
bogdanm 82:6473597d706e 221 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 222 * field Monotonic Counter High Write (MCHW). Once cleared,
bogdanm 82:6473597d706e 223 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 224 * VBAT POR or by the software reset.
bogdanm 82:6473597d706e 225 * @return true: Writes to the monotonic counter high register complete normally.
bogdanm 82:6473597d706e 226 * false: Writes to the monotonic counter high register are ignored.
bogdanm 82:6473597d706e 227 */
bogdanm 82:6473597d706e 228 static inline bool rtc_hal_get_monotonic_hcount_wreg(void)
bogdanm 82:6473597d706e 229 {
bogdanm 82:6473597d706e 230 return (bool)BR_RTC_WAR_MCHW;
bogdanm 82:6473597d706e 231 }
bogdanm 82:6473597d706e 232
bogdanm 82:6473597d706e 233 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 234 * field Monotonic Counter High Write (MCHW). Once cleared,
bogdanm 82:6473597d706e 235 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 236 * VBAT POR or software reset.
bogdanm 82:6473597d706e 237 * @param enable true: Writes to the monotonic counter high register complete normally.
bogdanm 82:6473597d706e 238 * false: Writes to the monotonic counter high register are ignored.
bogdanm 82:6473597d706e 239 */
bogdanm 82:6473597d706e 240 static inline void rtc_hal_set_monotonic_hcount_wreg(bool enable)
bogdanm 82:6473597d706e 241 {
bogdanm 82:6473597d706e 242 BW_RTC_WAR_MCHW((uint32_t) enable);
bogdanm 82:6473597d706e 243 }
bogdanm 82:6473597d706e 244
bogdanm 82:6473597d706e 245 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 246 * field Monotonic Counter Low Write (MCLW). Once cleared,
bogdanm 82:6473597d706e 247 * this bit is only set by system reset. It is not affected by the
bogdanm 82:6473597d706e 248 * VBAT POR or software reset.
bogdanm 82:6473597d706e 249 * @return true: Writes to the monotonic counter low register complete normally.
bogdanm 82:6473597d706e 250 * false: Writes to the monotonic counter low register are ignored.
bogdanm 82:6473597d706e 251 */
bogdanm 82:6473597d706e 252 static inline bool rtc_hal_get_monotonic_lcount_wreg(void)
bogdanm 82:6473597d706e 253 {
bogdanm 82:6473597d706e 254 return (bool)BR_RTC_WAR_MCLW;
bogdanm 82:6473597d706e 255 }
bogdanm 82:6473597d706e 256
bogdanm 82:6473597d706e 257 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 258 * field Monotonic Counter Low Write (MCLW). Once cleared,
bogdanm 82:6473597d706e 259 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 260 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 261 * @param enable true: Writes to the monotonic counter low register complete normally.
bogdanm 82:6473597d706e 262 * false: Writes to the monotonic counter low register are ignored.
bogdanm 82:6473597d706e 263 */
bogdanm 82:6473597d706e 264 static inline void rtc_hal_set_monotonic_lcount_wreg(bool enable)
bogdanm 82:6473597d706e 265 {
bogdanm 82:6473597d706e 266 BW_RTC_WAR_MCLW((uint32_t) enable);
bogdanm 82:6473597d706e 267 }
bogdanm 82:6473597d706e 268
bogdanm 82:6473597d706e 269 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 270 * field Monotonic Enable Register Write (MERW). Once cleared,
bogdanm 82:6473597d706e 271 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 272 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 273 * @return true: Writes to the monotonic enable register complete normally.
bogdanm 82:6473597d706e 274 * false: Writes to the monotonic enable register are ignored.
bogdanm 82:6473597d706e 275 */
bogdanm 82:6473597d706e 276 static inline bool rtc_hal_get_monotonic_enable_wreg(void)
bogdanm 82:6473597d706e 277 {
bogdanm 82:6473597d706e 278 return (bool)BR_RTC_WAR_MERW;
bogdanm 82:6473597d706e 279 }
bogdanm 82:6473597d706e 280
bogdanm 82:6473597d706e 281 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 282 * field Monotonic Enable Register Write (MERW). Once cleared,
bogdanm 82:6473597d706e 283 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 284 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 285 * @param enable true: Writes to the monotonic enable register complete normally.
bogdanm 82:6473597d706e 286 * false: Writes to the monotonic enable register are ignored.
bogdanm 82:6473597d706e 287 */
bogdanm 82:6473597d706e 288 static inline void rtc_hal_set_monotonic_enable_wreg(bool enable)
bogdanm 82:6473597d706e 289 {
bogdanm 82:6473597d706e 290 BW_RTC_WAR_MERW((uint32_t) enable);
bogdanm 82:6473597d706e 291 }
bogdanm 82:6473597d706e 292 #endif
bogdanm 82:6473597d706e 293
bogdanm 82:6473597d706e 294 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 295 * field Interrupt Enable Register Write (IERW). Once cleared,
bogdanm 82:6473597d706e 296 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 297 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 298 * @return true: Writes to the interrupt enable register complete normally.
bogdanm 82:6473597d706e 299 * false: Writes to the interrupt enable register are ignored.
bogdanm 82:6473597d706e 300 */
bogdanm 82:6473597d706e 301 static inline bool rtc_hal_get_interrupt_enable_wreg(void)
bogdanm 82:6473597d706e 302 {
bogdanm 82:6473597d706e 303 return (bool)BR_RTC_WAR_IERW;
bogdanm 82:6473597d706e 304 }
bogdanm 82:6473597d706e 305
bogdanm 82:6473597d706e 306 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 307 * field Interrupt Enable Register Write (IERW). Once cleared,
bogdanm 82:6473597d706e 308 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 309 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 310 * @param enable true: Writes to the interrupt enable register complete normally.
bogdanm 82:6473597d706e 311 * false: Writes to the interrupt enable register are ignored.
bogdanm 82:6473597d706e 312 */
bogdanm 82:6473597d706e 313 static inline void rtc_hal_set_interrupt_enable_wreg(bool enable)
bogdanm 82:6473597d706e 314 {
bogdanm 82:6473597d706e 315 BW_RTC_WAR_IERW((uint32_t) enable);
bogdanm 82:6473597d706e 316 }
bogdanm 82:6473597d706e 317
bogdanm 82:6473597d706e 318 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 319 * field Lock Register Write (LRW).
bogdanm 82:6473597d706e 320 * @return true: Writes to the lock register complete normally.
bogdanm 82:6473597d706e 321 * false: Writes to the lock register are ignored.
bogdanm 82:6473597d706e 322 */
bogdanm 82:6473597d706e 323 static inline bool rtc_hal_get_lock_wreg(void)
bogdanm 82:6473597d706e 324 {
bogdanm 82:6473597d706e 325 return (bool)BR_RTC_WAR_LRW;
bogdanm 82:6473597d706e 326 }
bogdanm 82:6473597d706e 327
bogdanm 82:6473597d706e 328 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 329 * field Lock Register Write (LRW). Once cleared,
bogdanm 82:6473597d706e 330 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 331 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 332 * @param enable true: Writes to the lock register complete normally.
bogdanm 82:6473597d706e 333 * false: Writes to the lock register are ignored.
bogdanm 82:6473597d706e 334 */
bogdanm 82:6473597d706e 335 static inline void rtc_hal_set_lock_wreg(bool enable)
bogdanm 82:6473597d706e 336 {
bogdanm 82:6473597d706e 337 BW_RTC_WAR_LRW((uint32_t) enable);
bogdanm 82:6473597d706e 338 }
bogdanm 82:6473597d706e 339
bogdanm 82:6473597d706e 340 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 341 * field Status Register Write (SRW). Once cleared,
bogdanm 82:6473597d706e 342 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 343 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 344 * @return true: Writes to the status register complete normally.
bogdanm 82:6473597d706e 345 * false: Writes to the status register are ignored.
bogdanm 82:6473597d706e 346 */
bogdanm 82:6473597d706e 347 static inline bool rtc_hal_get_status_wreg(void)
bogdanm 82:6473597d706e 348 {
bogdanm 82:6473597d706e 349 return (bool)BR_RTC_WAR_SRW;
bogdanm 82:6473597d706e 350 }
bogdanm 82:6473597d706e 351
bogdanm 82:6473597d706e 352 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 353 * field Status Register Write (SRW). Once cleared,
bogdanm 82:6473597d706e 354 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 355 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 356 * @param enable true: Writes to the status register complete normally.
bogdanm 82:6473597d706e 357 * false: Writes to the status register are ignored.
bogdanm 82:6473597d706e 358 */
bogdanm 82:6473597d706e 359 static inline void rtc_hal_set_status_wreg(bool enable)
bogdanm 82:6473597d706e 360 {
bogdanm 82:6473597d706e 361 BW_RTC_WAR_SRW((uint32_t) enable);
bogdanm 82:6473597d706e 362 }
bogdanm 82:6473597d706e 363
bogdanm 82:6473597d706e 364 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 365 * field Control Register Write (CRW). Once cleared,
bogdanm 82:6473597d706e 366 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 367 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 368 * @return true: Writes to the control register complete normally.
bogdanm 82:6473597d706e 369 * false: Writes to the control register are ignored.
bogdanm 82:6473597d706e 370 */
bogdanm 82:6473597d706e 371 static inline bool rtc_hal_get_control_wreg(void)
bogdanm 82:6473597d706e 372 {
bogdanm 82:6473597d706e 373 return (bool)BR_RTC_WAR_CRW;
bogdanm 82:6473597d706e 374 }
bogdanm 82:6473597d706e 375
bogdanm 82:6473597d706e 376 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 377 * field Control Register Write (CRW). Once cleared,
bogdanm 82:6473597d706e 378 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 379 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 380 * @param enable true: Writes to the control register complete normally.
bogdanm 82:6473597d706e 381 * false: Writes to the control register are ignored.
bogdanm 82:6473597d706e 382 */
bogdanm 82:6473597d706e 383 static inline void rtc_hal_set_control_wreg(bool enable)
bogdanm 82:6473597d706e 384 {
bogdanm 82:6473597d706e 385 BW_RTC_WAR_CRW((uint32_t) enable);
bogdanm 82:6473597d706e 386 }
bogdanm 82:6473597d706e 387
bogdanm 82:6473597d706e 388 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 389 * field Time Compensation Register Write (TCRW).
bogdanm 82:6473597d706e 390 * @return true: Writes to the time compensation register complete normally.
bogdanm 82:6473597d706e 391 * false: Writes to the time compensation register are ignored.
bogdanm 82:6473597d706e 392 */
bogdanm 82:6473597d706e 393 static inline bool rtc_hal_get_compensation_wreg(void)
bogdanm 82:6473597d706e 394 {
bogdanm 82:6473597d706e 395 return (bool)BR_RTC_WAR_TCRW;
bogdanm 82:6473597d706e 396 }
bogdanm 82:6473597d706e 397
bogdanm 82:6473597d706e 398 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 399 * field Time Compensation Register Write (TCRW). Once cleared,
bogdanm 82:6473597d706e 400 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 401 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 402 * @param enable true: Writes to the time compensation register complete normally.
bogdanm 82:6473597d706e 403 * false: Writes to the time compensation register are ignored.
bogdanm 82:6473597d706e 404 */
bogdanm 82:6473597d706e 405 static inline void rtc_hal_set_compensation_wreg(bool enable)
bogdanm 82:6473597d706e 406 {
bogdanm 82:6473597d706e 407 BW_RTC_WAR_TCRW((uint32_t) enable);
bogdanm 82:6473597d706e 408 }
bogdanm 82:6473597d706e 409
bogdanm 82:6473597d706e 410 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 411 * field Time Alarm Register Write (TARW). Once cleared,
bogdanm 82:6473597d706e 412 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 413 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 414 * @return true: Writes to the time alarm register complete normally.
bogdanm 82:6473597d706e 415 * false: Writes to the time alarm register are ignored.
bogdanm 82:6473597d706e 416 */
bogdanm 82:6473597d706e 417 static inline bool rtc_hal_get_alarm_wreg(void)
bogdanm 82:6473597d706e 418 {
bogdanm 82:6473597d706e 419 return (bool)BR_RTC_WAR_TARW;
bogdanm 82:6473597d706e 420 }
bogdanm 82:6473597d706e 421
bogdanm 82:6473597d706e 422 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 423 * field Time Alarm Register Write (TARW). Once cleared,
bogdanm 82:6473597d706e 424 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 425 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 426 * @param enable true: Writes to the time alarm register complete normally.
bogdanm 82:6473597d706e 427 * false: Writes to the time alarm register are ignored.
bogdanm 82:6473597d706e 428 */
bogdanm 82:6473597d706e 429 static inline void rtc_hal_set_alarm_wreg(bool enable)
bogdanm 82:6473597d706e 430 {
bogdanm 82:6473597d706e 431 BW_RTC_WAR_TARW((uint32_t) enable);
bogdanm 82:6473597d706e 432 }
bogdanm 82:6473597d706e 433
bogdanm 82:6473597d706e 434 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 435 * field Time Prescaler Register Write (TPRW).
bogdanm 82:6473597d706e 436 * @return true: Writes to the time prescaler register complete normally.
bogdanm 82:6473597d706e 437 * false: Writes to the time prescaler register are ignored.
bogdanm 82:6473597d706e 438 */
bogdanm 82:6473597d706e 439 static inline bool rtc_hal_get_prescaler_wreg(void)
bogdanm 82:6473597d706e 440 {
bogdanm 82:6473597d706e 441 return (bool)BR_RTC_WAR_TPRW;
bogdanm 82:6473597d706e 442 }
bogdanm 82:6473597d706e 443
bogdanm 82:6473597d706e 444 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 445 * field Time Prescaler Register Write (TPRW). Once cleared,
bogdanm 82:6473597d706e 446 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 447 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 448 * @param enable true: Writes to the time prescaler register complete normally.
bogdanm 82:6473597d706e 449 * false: Writes to the time prescaler register are ignored.
bogdanm 82:6473597d706e 450 */
bogdanm 82:6473597d706e 451 static inline void rtc_hal_set_prescaler_wreg(bool enable)
bogdanm 82:6473597d706e 452 {
bogdanm 82:6473597d706e 453 BW_RTC_WAR_TPRW((uint32_t) enable);
bogdanm 82:6473597d706e 454 }
bogdanm 82:6473597d706e 455
bogdanm 82:6473597d706e 456 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 457 * field Time Seconds Register Write (TSRW). Once cleared,
bogdanm 82:6473597d706e 458 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 459 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 460 * @return true: Writes to the time seconds register complete normally.
bogdanm 82:6473597d706e 461 * false: Writes to the time seconds register are ignored.
bogdanm 82:6473597d706e 462 */
bogdanm 82:6473597d706e 463 static inline bool rtc_hal_get_seconds_wreg(void)
bogdanm 82:6473597d706e 464 {
bogdanm 82:6473597d706e 465 return (bool)BR_RTC_WAR_TSRW;
bogdanm 82:6473597d706e 466 }
bogdanm 82:6473597d706e 467
bogdanm 82:6473597d706e 468 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
bogdanm 82:6473597d706e 469 * field Time Seconds Register Write (TSRW). Once cleared,
bogdanm 82:6473597d706e 470 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 471 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 472 * @param enable true: Writes to the time seconds register complete normally.
bogdanm 82:6473597d706e 473 * false: Writes to the time seconds register are ignored.
bogdanm 82:6473597d706e 474 */
bogdanm 82:6473597d706e 475 static inline void rtc_hal_set_seconds_wreg(bool enable)
bogdanm 82:6473597d706e 476 {
bogdanm 82:6473597d706e 477 BW_RTC_WAR_TSRW((uint32_t) enable);
bogdanm 82:6473597d706e 478 }
bogdanm 82:6473597d706e 479
bogdanm 82:6473597d706e 480 #if (FSL_FEATURE_RTC_HAS_MONOTONIC == 1)
bogdanm 82:6473597d706e 481 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 482 * field Monotonic Counter High Read (MCHR). Once cleared,
bogdanm 82:6473597d706e 483 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 484 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 485 * @return true: Reads to the monotonic counter high register complete normally.
bogdanm 82:6473597d706e 486 * false: Reads to the monotonic counter high register are ignored.
bogdanm 82:6473597d706e 487 */
bogdanm 82:6473597d706e 488 static inline bool rtc_hal_get_monotonic_hcount_rreg(void)
bogdanm 82:6473597d706e 489 {
bogdanm 82:6473597d706e 490 return (bool)BR_RTC_RAR_MCHR;
bogdanm 82:6473597d706e 491 }
bogdanm 82:6473597d706e 492
bogdanm 82:6473597d706e 493 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 494 * field Monotonic Counter High Read (MCHR). Once cleared,
bogdanm 82:6473597d706e 495 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 496 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 497 * @param enable true: Reads to the monotonic counter high register complete normally.
bogdanm 82:6473597d706e 498 * false: Reads to the monotonic counter high register are ignored.
bogdanm 82:6473597d706e 499 */
bogdanm 82:6473597d706e 500 static inline void rtc_hal_set_monotonic_hcount_rreg(bool enable)
bogdanm 82:6473597d706e 501 {
bogdanm 82:6473597d706e 502 BW_RTC_RAR_MCHR((uint32_t) enable);
bogdanm 82:6473597d706e 503 }
bogdanm 82:6473597d706e 504
bogdanm 82:6473597d706e 505 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 506 * field Monotonic Counter Low Read (MCLR). Once cleared,
bogdanm 82:6473597d706e 507 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 508 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 509 * @return true: Reads to the monotonic counter low register complete normally.
bogdanm 82:6473597d706e 510 * false: Reads to the monotonic counter low register are ignored.
bogdanm 82:6473597d706e 511 */
bogdanm 82:6473597d706e 512 static inline bool rtc_hal_get_monotonic_lcount_rreg(void)
bogdanm 82:6473597d706e 513 {
bogdanm 82:6473597d706e 514 return (bool)BR_RTC_RAR_MCLR;
bogdanm 82:6473597d706e 515 }
bogdanm 82:6473597d706e 516
bogdanm 82:6473597d706e 517 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 518 * field Monotonic Counter Low Read (MCLR). Once cleared,
bogdanm 82:6473597d706e 519 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 520 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 521 * @param enable true: Reads to the monotonic counter low register complete normally.
bogdanm 82:6473597d706e 522 * false: Reads to the monotonic counter low register are ignored.
bogdanm 82:6473597d706e 523 */
bogdanm 82:6473597d706e 524 static inline void rtc_hal_set_monotonic_lcount_rreg(bool enable)
bogdanm 82:6473597d706e 525 {
bogdanm 82:6473597d706e 526 BW_RTC_RAR_MCLR((uint32_t) enable);
bogdanm 82:6473597d706e 527 }
bogdanm 82:6473597d706e 528
bogdanm 82:6473597d706e 529 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 530 * field Monotonic Enable Register Read (MERR). Once cleared,
bogdanm 82:6473597d706e 531 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 532 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 533 * @return true: Reads to the monotonic enable register complete normally.
bogdanm 82:6473597d706e 534 * false: Reads to the monotonic enable register are ignored.
bogdanm 82:6473597d706e 535 */
bogdanm 82:6473597d706e 536 static inline bool rtc_hal_get_monotonic_enable_rreg(void)
bogdanm 82:6473597d706e 537 {
bogdanm 82:6473597d706e 538 return (bool)BR_RTC_RAR_MERR;
bogdanm 82:6473597d706e 539 }
bogdanm 82:6473597d706e 540
bogdanm 82:6473597d706e 541 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 542 * field Monotonic Enable Register Read (MERR). Once cleared,
bogdanm 82:6473597d706e 543 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 544 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 545 * @param enable true: Reads to the monotonic enable register complete normally.
bogdanm 82:6473597d706e 546 * false: Reads to the monotonic enable register are ignored.
bogdanm 82:6473597d706e 547 */
bogdanm 82:6473597d706e 548 static inline void rtc_hal_set_monotonic_enable_rreg(bool enable)
bogdanm 82:6473597d706e 549 {
bogdanm 82:6473597d706e 550 BW_RTC_RAR_MERR((uint32_t) enable);
bogdanm 82:6473597d706e 551 }
bogdanm 82:6473597d706e 552 #endif
bogdanm 82:6473597d706e 553
bogdanm 82:6473597d706e 554 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 555 * field Interrupt Enable Register Read (IERR). Once cleared,
bogdanm 82:6473597d706e 556 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 557 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 558 * @return true: Reads to the interrupt enable register complete normally.
bogdanm 82:6473597d706e 559 * false: Reads to the interrupt enable register are ignored.
bogdanm 82:6473597d706e 560 */
bogdanm 82:6473597d706e 561 static inline bool rtc_hal_get_interrupt_enable_rreg(void)
bogdanm 82:6473597d706e 562 {
bogdanm 82:6473597d706e 563 return (bool)BR_RTC_RAR_IERR;
bogdanm 82:6473597d706e 564 }
bogdanm 82:6473597d706e 565
bogdanm 82:6473597d706e 566 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 567 * field Interrupt Enable Register Read (IERR). Once cleared,
bogdanm 82:6473597d706e 568 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 569 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 570 * @param enable true: Reads to the interrupt enable register complete normally.
bogdanm 82:6473597d706e 571 * false: Reads to the interrupt enable register are ignored.
bogdanm 82:6473597d706e 572 */
bogdanm 82:6473597d706e 573 static inline void rtc_hal_set_interrupt_enable_rreg(bool enable)
bogdanm 82:6473597d706e 574 {
bogdanm 82:6473597d706e 575 BW_RTC_RAR_IERR((uint32_t) enable);
bogdanm 82:6473597d706e 576 }
bogdanm 82:6473597d706e 577
bogdanm 82:6473597d706e 578 /*! @brief reads the value of the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 579 * field Lock Register Read (LRR). Once cleared,
bogdanm 82:6473597d706e 580 * this bit is only set by system reset. It is not affected by
bogdanm 82:6473597d706e 581 * VBAT POR or software reset.
bogdanm 82:6473597d706e 582 * @return true: Reads to the lock register complete as normal.
bogdanm 82:6473597d706e 583 * false: Reads to the lock register are ignored.
bogdanm 82:6473597d706e 584 */
bogdanm 82:6473597d706e 585 static inline bool rtc_hal_get_lock_rreg(void)
bogdanm 82:6473597d706e 586 {
bogdanm 82:6473597d706e 587 return (bool)BR_RTC_RAR_LRR;
bogdanm 82:6473597d706e 588 }
bogdanm 82:6473597d706e 589
bogdanm 82:6473597d706e 590 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 591 * field Lock Register Read (LRR). Once cleared,
bogdanm 82:6473597d706e 592 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 593 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 594 * @param enable true: Reads to the lock register complete normally.
bogdanm 82:6473597d706e 595 * false: Reads to the lock register are ignored.
bogdanm 82:6473597d706e 596 */
bogdanm 82:6473597d706e 597 static inline void rtc_hal_set_lock_rreg(bool enable)
bogdanm 82:6473597d706e 598 {
bogdanm 82:6473597d706e 599 BW_RTC_RAR_LRR((uint32_t) enable);
bogdanm 82:6473597d706e 600 }
bogdanm 82:6473597d706e 601
bogdanm 82:6473597d706e 602 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 603 * field Status Register Read (SRR). Once cleared,
bogdanm 82:6473597d706e 604 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 605 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 606 * @return true: Reads to the status register complete normally.
bogdanm 82:6473597d706e 607 * false: Reads to the status register are ignored.
bogdanm 82:6473597d706e 608 */
bogdanm 82:6473597d706e 609 static inline bool rtc_hal_get_status_rreg(void)
bogdanm 82:6473597d706e 610 {
bogdanm 82:6473597d706e 611 return (bool)BR_RTC_RAR_SRR;
bogdanm 82:6473597d706e 612 }
bogdanm 82:6473597d706e 613
bogdanm 82:6473597d706e 614 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 615 * field Status Register Read (SRR). Once cleared,
bogdanm 82:6473597d706e 616 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 617 * VBAT POR or software reset.
bogdanm 82:6473597d706e 618 * @param enable true: Reads to the status register complete normally.
bogdanm 82:6473597d706e 619 * false: Reads to the status register are ignored.
bogdanm 82:6473597d706e 620 */
bogdanm 82:6473597d706e 621 static inline void rtc_hal_set_status_rreg(bool enable)
bogdanm 82:6473597d706e 622 {
bogdanm 82:6473597d706e 623 BW_RTC_RAR_SRR((uint32_t) enable);
bogdanm 82:6473597d706e 624 }
bogdanm 82:6473597d706e 625
bogdanm 82:6473597d706e 626 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 627 * field Control Register Read (CRR). Once cleared,
bogdanm 82:6473597d706e 628 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 629 * VBAT POR or software reset.
bogdanm 82:6473597d706e 630 * @return true: Reads to the control register complete normally.
bogdanm 82:6473597d706e 631 * false: Reads to the control register are ignored.
bogdanm 82:6473597d706e 632 */
bogdanm 82:6473597d706e 633 static inline bool rtc_hal_get_control_rreg(void)
bogdanm 82:6473597d706e 634 {
bogdanm 82:6473597d706e 635 return (bool)BR_RTC_RAR_CRR;
bogdanm 82:6473597d706e 636 }
bogdanm 82:6473597d706e 637
bogdanm 82:6473597d706e 638 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 639 * field Control Register Read (CRR). Once cleared,
bogdanm 82:6473597d706e 640 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 641 * VBAT POR or software reset.
bogdanm 82:6473597d706e 642 * @param enable true: Reads to the control register complete normally.
bogdanm 82:6473597d706e 643 * false: Reads to the control register are ignored.
bogdanm 82:6473597d706e 644 */
bogdanm 82:6473597d706e 645 static inline void rtc_hal_set_control_rreg(bool enable)
bogdanm 82:6473597d706e 646 {
bogdanm 82:6473597d706e 647 BW_RTC_RAR_CRR((uint32_t) enable);
bogdanm 82:6473597d706e 648 }
bogdanm 82:6473597d706e 649
bogdanm 82:6473597d706e 650 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 651 * field Time Compensation Register Read (TCRR). Once cleared,
bogdanm 82:6473597d706e 652 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 653 * VBAT POR or software reset.
bogdanm 82:6473597d706e 654 * @return true: Reads to the time compensation register complete normally.
bogdanm 82:6473597d706e 655 * false: Reads to the time compensation register are ignored.
bogdanm 82:6473597d706e 656 */
bogdanm 82:6473597d706e 657 static inline bool rtc_hal_get_compensation_rreg(void)
bogdanm 82:6473597d706e 658 {
bogdanm 82:6473597d706e 659 return (bool)BR_RTC_RAR_TCRR;
bogdanm 82:6473597d706e 660 }
bogdanm 82:6473597d706e 661
bogdanm 82:6473597d706e 662 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 663 * field Time Compensation Register Read (TCRR). Once cleared,
bogdanm 82:6473597d706e 664 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 665 * VBAT POR or software reset.
bogdanm 82:6473597d706e 666 * @param enable true: Reads to the time compensation register complete normally.
bogdanm 82:6473597d706e 667 * false: Reads to the time compensation register are ignored.
bogdanm 82:6473597d706e 668 */
bogdanm 82:6473597d706e 669 static inline void rtc_hal_set_compensation_rreg(bool enable)
bogdanm 82:6473597d706e 670 {
bogdanm 82:6473597d706e 671 BW_RTC_RAR_TCRR((uint32_t) enable);
bogdanm 82:6473597d706e 672 }
bogdanm 82:6473597d706e 673
bogdanm 82:6473597d706e 674 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 675 * field Time Alarm Register Read (TARR). Once cleared,
bogdanm 82:6473597d706e 676 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 677 * VBAT POR or software reset.
bogdanm 82:6473597d706e 678 * @return true: Reads to the time alarm register complete normally.
bogdanm 82:6473597d706e 679 * false: Reads to the time alarm register are ignored.
bogdanm 82:6473597d706e 680 */
bogdanm 82:6473597d706e 681 static inline bool rtc_hal_get_alarm_rreg(void)
bogdanm 82:6473597d706e 682 {
bogdanm 82:6473597d706e 683 return (bool)BR_RTC_RAR_TARR;
bogdanm 82:6473597d706e 684 }
bogdanm 82:6473597d706e 685
bogdanm 82:6473597d706e 686 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 687 * field Time Alarm Register Read (TARR). Once cleared,
bogdanm 82:6473597d706e 688 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 689 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 690 * @param enable true: Reads to the time alarm register complete normally.
bogdanm 82:6473597d706e 691 * false: Reads to the time alarm register are ignored.
bogdanm 82:6473597d706e 692 */
bogdanm 82:6473597d706e 693 static inline void rtc_hal_set_alarm_rreg(bool enable)
bogdanm 82:6473597d706e 694 {
bogdanm 82:6473597d706e 695 BW_RTC_RAR_TARR((uint32_t) enable);
bogdanm 82:6473597d706e 696 }
bogdanm 82:6473597d706e 697
bogdanm 82:6473597d706e 698 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 699 * field Time Prescaler Register Read (TPRR). Once cleared,
bogdanm 82:6473597d706e 700 * this bit is only set by the system reset. It is not affected by
bogdanm 82:6473597d706e 701 * VBAT POR or software reset.
bogdanm 82:6473597d706e 702 * @return true: Reads to the time prescaler register complete normally.
bogdanm 82:6473597d706e 703 * false: Reads to the time prescaler register are ignored.
bogdanm 82:6473597d706e 704 */
bogdanm 82:6473597d706e 705 static inline bool rtc_hal_get_prescaler_rreg(void)
bogdanm 82:6473597d706e 706 {
bogdanm 82:6473597d706e 707 return (bool)BR_RTC_RAR_TPRR;
bogdanm 82:6473597d706e 708 }
bogdanm 82:6473597d706e 709
bogdanm 82:6473597d706e 710 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 711 * field Time Prescaler Register Read (TPRR). Once cleared,
bogdanm 82:6473597d706e 712 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 713 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 714 * @param enable true: Reads to the time prescaler register complete normally.
bogdanm 82:6473597d706e 715 * false: Reads to the time prescaler register are ignored.
bogdanm 82:6473597d706e 716 */
bogdanm 82:6473597d706e 717 static inline void rtc_hal_set_prescaler_rreg(bool enable)
bogdanm 82:6473597d706e 718 {
bogdanm 82:6473597d706e 719
bogdanm 82:6473597d706e 720 BW_RTC_RAR_TPRR((uint32_t) enable);
bogdanm 82:6473597d706e 721 }
bogdanm 82:6473597d706e 722
bogdanm 82:6473597d706e 723 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 724 * field Time Seconds Register Read (TSRR). Once cleared,
bogdanm 82:6473597d706e 725 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 726 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 727 * @return true: Reads to the time seconds register complete normally.
bogdanm 82:6473597d706e 728 * false: Reads to the time seconds register are ignored.
bogdanm 82:6473597d706e 729 */
bogdanm 82:6473597d706e 730 static inline bool rtc_hal_get_seconds_rreg(void)
bogdanm 82:6473597d706e 731 {
bogdanm 82:6473597d706e 732 return (bool)BR_RTC_RAR_TSRR;
bogdanm 82:6473597d706e 733 }
bogdanm 82:6473597d706e 734
bogdanm 82:6473597d706e 735 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
bogdanm 82:6473597d706e 736 * field Time Seconds Register Read (TSRR). Once cleared,
bogdanm 82:6473597d706e 737 * this bit is only set by the system reset. It is not affected by the
bogdanm 82:6473597d706e 738 * VBAT POR or the software reset.
bogdanm 82:6473597d706e 739 * @param enable true: Reads to the time seconds register complete normally.
bogdanm 82:6473597d706e 740 * false: Reads to the time seconds register are ignored.
bogdanm 82:6473597d706e 741 */
bogdanm 82:6473597d706e 742 static inline void rtc_hal_set_seconds_rreg(bool enable)
bogdanm 82:6473597d706e 743 {
bogdanm 82:6473597d706e 744 BW_RTC_RAR_TSRR((uint32_t) enable);
bogdanm 82:6473597d706e 745 }
bogdanm 82:6473597d706e 746
bogdanm 82:6473597d706e 747
bogdanm 82:6473597d706e 748 #if defined(__cplusplus)
bogdanm 82:6473597d706e 749 }
bogdanm 82:6473597d706e 750 #endif
bogdanm 82:6473597d706e 751
bogdanm 82:6473597d706e 752 #endif
bogdanm 82:6473597d706e 753
bogdanm 82:6473597d706e 754 /*! @}*/
bogdanm 82:6473597d706e 755
bogdanm 82:6473597d706e 756 #endif /* __FSL_RTC_HAL_MONOTONIC_H__*/
bogdanm 82:6473597d706e 757
bogdanm 82:6473597d706e 758 /*******************************************************************************
bogdanm 82:6473597d706e 759 * EOF
bogdanm 82:6473597d706e 760 ******************************************************************************/