Ricardo Benitez / mbed

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Fork of mbed by mbed official

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_features.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Child:
90:cb3d968589d8
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 82:6473597d706e 6 * are permitted provided that the following conditions are met:
bogdanm 82:6473597d706e 7 *
bogdanm 82:6473597d706e 8 * o Redistributions of source code must retain the above copyright notice, this list
bogdanm 82:6473597d706e 9 * of conditions and the following disclaimer.
bogdanm 82:6473597d706e 10 *
bogdanm 82:6473597d706e 11 * o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 82:6473597d706e 12 * list of conditions and the following disclaimer in the documentation and/or
bogdanm 82:6473597d706e 13 * other materials provided with the distribution.
bogdanm 82:6473597d706e 14 *
bogdanm 82:6473597d706e 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 82:6473597d706e 16 * contributors may be used to endorse or promote products derived from this
bogdanm 82:6473597d706e 17 * software without specific prior written permission.
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 82:6473597d706e 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 82:6473597d706e 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 82:6473597d706e 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 82:6473597d706e 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 82:6473597d706e 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 82:6473597d706e 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 82:6473597d706e 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 82:6473597d706e 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 82:6473597d706e 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 82:6473597d706e 29 */
bogdanm 82:6473597d706e 30 #if !defined(__FSL_PORT_FEATURES_H__)
bogdanm 82:6473597d706e 31 #define __FSL_PORT_FEATURES_H__
bogdanm 82:6473597d706e 32
bogdanm 82:6473597d706e 33 #if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
bogdanm 82:6473597d706e 34 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
bogdanm 82:6473597d706e 35 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
bogdanm 82:6473597d706e 36 defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
bogdanm 82:6473597d706e 37 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
bogdanm 82:6473597d706e 38 defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
bogdanm 82:6473597d706e 39 defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
bogdanm 82:6473597d706e 40 defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \
bogdanm 82:6473597d706e 41 defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
bogdanm 82:6473597d706e 42 defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || \
bogdanm 82:6473597d706e 43 defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || \
bogdanm 82:6473597d706e 44 defined(CPU_MK64FX512VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
bogdanm 82:6473597d706e 45 defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
bogdanm 82:6473597d706e 46 defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31FN512VLH12) || \
bogdanm 82:6473597d706e 47 defined(CPU_MKV31F512VLL12)
bogdanm 82:6473597d706e 48 /* @brief Has control lock (register bit PCR[LK]).*/
bogdanm 82:6473597d706e 49 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
bogdanm 82:6473597d706e 50 /* @brief Has open drain control (register bit PCR[ODE]).*/
bogdanm 82:6473597d706e 51 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
bogdanm 82:6473597d706e 52 /* @brief Has digital filter (registers DFER, DFCR and DFWR).*/
bogdanm 82:6473597d706e 53 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
bogdanm 82:6473597d706e 54 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
bogdanm 82:6473597d706e 55 ((x) == 0 ? (0) : \
bogdanm 82:6473597d706e 56 ((x) == 1 ? (0) : \
bogdanm 82:6473597d706e 57 ((x) == 2 ? (0) : \
bogdanm 82:6473597d706e 58 ((x) == 3 ? (1) : \
bogdanm 82:6473597d706e 59 ((x) == 4 ? (0) : (-1))))))
bogdanm 82:6473597d706e 60 /* @brief Has DMA request (register bit field PCR[IRQC] values).*/
bogdanm 82:6473597d706e 61 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
bogdanm 82:6473597d706e 62 /* @brief Has pull resistor selection (register bit PCR[PS]).*/
bogdanm 82:6473597d706e 63 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
bogdanm 82:6473597d706e 64 /* @brief Has separate pull resistor enable registers (PUEL and PUEH).*/
bogdanm 82:6473597d706e 65 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
bogdanm 82:6473597d706e 66 /* @brief Has slew rate control (register bit PCR[SRE]).*/
bogdanm 82:6473597d706e 67 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
bogdanm 82:6473597d706e 68 /* @brief Has passive filter (register bit field PCR[PFE]).*/
bogdanm 82:6473597d706e 69 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
bogdanm 82:6473597d706e 70 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
bogdanm 82:6473597d706e 71 ((x) == 0 ? (1) : \
bogdanm 82:6473597d706e 72 ((x) == 1 ? (1) : \
bogdanm 82:6473597d706e 73 ((x) == 2 ? (1) : \
bogdanm 82:6473597d706e 74 ((x) == 3 ? (1) : \
bogdanm 82:6473597d706e 75 ((x) == 4 ? (1) : (-1))))))
bogdanm 82:6473597d706e 76 /* @brief Has drive strength control (register bit PCR[DSE]).*/
bogdanm 82:6473597d706e 77 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
bogdanm 82:6473597d706e 78 /* @brief Has separate drive strength register (HDRVE).*/
bogdanm 82:6473597d706e 79 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
bogdanm 82:6473597d706e 80 /* @brief Has glitch filter (register IOFLT).*/
bogdanm 82:6473597d706e 81 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
bogdanm 82:6473597d706e 82 #elif defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VMD12)
bogdanm 82:6473597d706e 83 /* @brief Has control lock (register bit PCR[LK]).*/
bogdanm 82:6473597d706e 84 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
bogdanm 82:6473597d706e 85 /* @brief Has open drain control (register bit PCR[ODE]).*/
bogdanm 82:6473597d706e 86 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
bogdanm 82:6473597d706e 87 /* @brief Has digital filter (registers DFER, DFCR and DFWR).*/
bogdanm 82:6473597d706e 88 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
bogdanm 82:6473597d706e 89 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
bogdanm 82:6473597d706e 90 ((x) == 0 ? (0) : \
bogdanm 82:6473597d706e 91 ((x) == 1 ? (0) : \
bogdanm 82:6473597d706e 92 ((x) == 2 ? (0) : \
bogdanm 82:6473597d706e 93 ((x) == 3 ? (1) : \
bogdanm 82:6473597d706e 94 ((x) == 4 ? (0) : (-1))))))
bogdanm 82:6473597d706e 95 /* @brief Has DMA request (register bit field PCR[IRQC] values).*/
bogdanm 82:6473597d706e 96 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
bogdanm 82:6473597d706e 97 /* @brief Has pull resistor selection (register bit PCR[PS]).*/
bogdanm 82:6473597d706e 98 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
bogdanm 82:6473597d706e 99 /* @brief Has separate pull resistor enable registers (PUEL and PUEH).*/
bogdanm 82:6473597d706e 100 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
bogdanm 82:6473597d706e 101 /* @brief Has slew rate control (register bit PCR[SRE]).*/
bogdanm 82:6473597d706e 102 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
bogdanm 82:6473597d706e 103 /* @brief Has passive filter (register bit field PCR[PFE]).*/
bogdanm 82:6473597d706e 104 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
bogdanm 82:6473597d706e 105 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
bogdanm 82:6473597d706e 106 ((x) == 0 ? (1) : \
bogdanm 82:6473597d706e 107 ((x) == 1 ? (1) : \
bogdanm 82:6473597d706e 108 ((x) == 2 ? (1) : \
bogdanm 82:6473597d706e 109 ((x) == 3 ? (1) : \
bogdanm 82:6473597d706e 110 ((x) == 4 ? (1) : (-1))))))
bogdanm 82:6473597d706e 111 /* @brief Has drive strength control (register bit PCR[DSE]).*/
bogdanm 82:6473597d706e 112 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
bogdanm 82:6473597d706e 113 /* @brief Has separate drive strength register (HDRVE).*/
bogdanm 82:6473597d706e 114 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
bogdanm 82:6473597d706e 115 /* @brief Has glitch filter (register IOFLT).*/
bogdanm 82:6473597d706e 116 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
bogdanm 82:6473597d706e 117 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
bogdanm 82:6473597d706e 118 defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
bogdanm 82:6473597d706e 119 /* @brief Has control lock (register bit PCR[LK]).*/
bogdanm 82:6473597d706e 120 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
bogdanm 82:6473597d706e 121 /* @brief Has open drain control (register bit PCR[ODE]).*/
bogdanm 82:6473597d706e 122 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
bogdanm 82:6473597d706e 123 /* @brief Has digital filter (registers DFER, DFCR and DFWR).*/
bogdanm 82:6473597d706e 124 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
bogdanm 82:6473597d706e 125 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
bogdanm 82:6473597d706e 126 ((x) == 0 ? (1) : \
bogdanm 82:6473597d706e 127 ((x) == 1 ? (1) : \
bogdanm 82:6473597d706e 128 ((x) == 2 ? (1) : \
bogdanm 82:6473597d706e 129 ((x) == 3 ? (1) : \
bogdanm 82:6473597d706e 130 ((x) == 4 ? (1) : \
bogdanm 82:6473597d706e 131 ((x) == 5 ? (1) : (-1)))))))
bogdanm 82:6473597d706e 132 /* @brief Has DMA request (register bit field PCR[IRQC] values).*/
bogdanm 82:6473597d706e 133 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
bogdanm 82:6473597d706e 134 /* @brief Has pull resistor selection (register bit PCR[PS]).*/
bogdanm 82:6473597d706e 135 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
bogdanm 82:6473597d706e 136 /* @brief Has separate pull resistor enable registers (PUEL and PUEH).*/
bogdanm 82:6473597d706e 137 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
bogdanm 82:6473597d706e 138 /* @brief Has slew rate control (register bit PCR[SRE]).*/
bogdanm 82:6473597d706e 139 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
bogdanm 82:6473597d706e 140 /* @brief Has passive filter (register bit field PCR[PFE]).*/
bogdanm 82:6473597d706e 141 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
bogdanm 82:6473597d706e 142 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
bogdanm 82:6473597d706e 143 ((x) == 0 ? (1) : \
bogdanm 82:6473597d706e 144 ((x) == 1 ? (1) : \
bogdanm 82:6473597d706e 145 ((x) == 2 ? (1) : \
bogdanm 82:6473597d706e 146 ((x) == 3 ? (1) : \
bogdanm 82:6473597d706e 147 ((x) == 4 ? (1) : \
bogdanm 82:6473597d706e 148 ((x) == 5 ? (1) : (-1)))))))
bogdanm 82:6473597d706e 149 /* @brief Has drive strength control (register bit PCR[DSE]).*/
bogdanm 82:6473597d706e 150 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
bogdanm 82:6473597d706e 151 /* @brief Has separate drive strength register (HDRVE).*/
bogdanm 82:6473597d706e 152 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
bogdanm 82:6473597d706e 153 /* @brief Has glitch filter (register IOFLT).*/
bogdanm 82:6473597d706e 154 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
bogdanm 82:6473597d706e 155 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
bogdanm 82:6473597d706e 156 defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
bogdanm 82:6473597d706e 157 defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)
bogdanm 82:6473597d706e 158 /* @brief Has control lock (register bit PCR[LK]).*/
bogdanm 82:6473597d706e 159 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
bogdanm 82:6473597d706e 160 /* @brief Has open drain control (register bit PCR[ODE]).*/
bogdanm 82:6473597d706e 161 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
bogdanm 82:6473597d706e 162 /* @brief Has digital filter (registers DFER, DFCR and DFWR).*/
bogdanm 82:6473597d706e 163 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
bogdanm 82:6473597d706e 164 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
bogdanm 82:6473597d706e 165 ((x) == 0 ? (0) : \
bogdanm 82:6473597d706e 166 ((x) == 1 ? (0) : (-1)))
bogdanm 82:6473597d706e 167 /* @brief Has DMA request (register bit field PCR[IRQC] values).*/
bogdanm 82:6473597d706e 168 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
bogdanm 82:6473597d706e 169 /* @brief Has pull resistor selection (register bit PCR[PS]).*/
bogdanm 82:6473597d706e 170 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
bogdanm 82:6473597d706e 171 /* @brief Has separate pull resistor enable registers (PUEL and PUEH).*/
bogdanm 82:6473597d706e 172 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
bogdanm 82:6473597d706e 173 /* @brief Has slew rate control (register bit PCR[SRE]).*/
bogdanm 82:6473597d706e 174 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
bogdanm 82:6473597d706e 175 /* @brief Has passive filter (register bit field PCR[PFE]).*/
bogdanm 82:6473597d706e 176 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
bogdanm 82:6473597d706e 177 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
bogdanm 82:6473597d706e 178 ((x) == 0 ? (1) : \
bogdanm 82:6473597d706e 179 ((x) == 1 ? (1) : (-1)))
bogdanm 82:6473597d706e 180 /* @brief Has drive strength control (register bit PCR[DSE]).*/
bogdanm 82:6473597d706e 181 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
bogdanm 82:6473597d706e 182 /* @brief Has separate drive strength register (HDRVE).*/
bogdanm 82:6473597d706e 183 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
bogdanm 82:6473597d706e 184 /* @brief Has glitch filter (register IOFLT).*/
bogdanm 82:6473597d706e 185 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
bogdanm 82:6473597d706e 186 #elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \
bogdanm 82:6473597d706e 187 defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \
bogdanm 82:6473597d706e 188 defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)
bogdanm 82:6473597d706e 189 /* @brief Has control lock (register bit PCR[LK]).*/
bogdanm 82:6473597d706e 190 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
bogdanm 82:6473597d706e 191 /* @brief Has open drain control (register bit PCR[ODE]).*/
bogdanm 82:6473597d706e 192 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
bogdanm 82:6473597d706e 193 /* @brief Has digital filter (registers DFER, DFCR and DFWR).*/
bogdanm 82:6473597d706e 194 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
bogdanm 82:6473597d706e 195 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
bogdanm 82:6473597d706e 196 ((x) == 0 ? (0) : \
bogdanm 82:6473597d706e 197 ((x) == 1 ? (0) : \
bogdanm 82:6473597d706e 198 ((x) == 2 ? (0) : \
bogdanm 82:6473597d706e 199 ((x) == 3 ? (0) : \
bogdanm 82:6473597d706e 200 ((x) == 4 ? (0) : (-1))))))
bogdanm 82:6473597d706e 201 /* @brief Has DMA request (register bit field PCR[IRQC] values).*/
bogdanm 82:6473597d706e 202 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
bogdanm 82:6473597d706e 203 /* @brief Has pull resistor selection (register bit PCR[PS]).*/
bogdanm 82:6473597d706e 204 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (0)
bogdanm 82:6473597d706e 205 /* @brief Has separate pull resistor enable registers (PUEL and PUEH).*/
bogdanm 82:6473597d706e 206 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
bogdanm 82:6473597d706e 207 /* @brief Has slew rate control (register bit PCR[SRE]).*/
bogdanm 82:6473597d706e 208 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
bogdanm 82:6473597d706e 209 /* @brief Has passive filter (register bit field PCR[PFE]).*/
bogdanm 82:6473597d706e 210 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
bogdanm 82:6473597d706e 211 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
bogdanm 82:6473597d706e 212 ((x) == 0 ? (1) : \
bogdanm 82:6473597d706e 213 ((x) == 1 ? (0) : \
bogdanm 82:6473597d706e 214 ((x) == 2 ? (0) : \
bogdanm 82:6473597d706e 215 ((x) == 3 ? (0) : \
bogdanm 82:6473597d706e 216 ((x) == 4 ? (0) : (-1))))))
bogdanm 82:6473597d706e 217 /* @brief Has drive strength control (register bit PCR[DSE]).*/
bogdanm 82:6473597d706e 218 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
bogdanm 82:6473597d706e 219 /* @brief Has separate drive strength register (HDRVE).*/
bogdanm 82:6473597d706e 220 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
bogdanm 82:6473597d706e 221 /* @brief Has glitch filter (register IOFLT).*/
bogdanm 82:6473597d706e 222 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
bogdanm 82:6473597d706e 223 #elif defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || \
bogdanm 82:6473597d706e 224 defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
bogdanm 82:6473597d706e 225 /* @brief Has control lock (register bit PCR[LK]).*/
bogdanm 82:6473597d706e 226 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
bogdanm 82:6473597d706e 227 /* @brief Has open drain control (register bit PCR[ODE]).*/
bogdanm 82:6473597d706e 228 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
bogdanm 82:6473597d706e 229 /* @brief Has digital filter (registers DFER, DFCR and DFWR).*/
bogdanm 82:6473597d706e 230 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
bogdanm 82:6473597d706e 231 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTERn(x) \
bogdanm 82:6473597d706e 232 ((x) == 0 ? (0) : \
bogdanm 82:6473597d706e 233 ((x) == 1 ? (0) : \
bogdanm 82:6473597d706e 234 ((x) == 2 ? (0) : \
bogdanm 82:6473597d706e 235 ((x) == 3 ? (0) : \
bogdanm 82:6473597d706e 236 ((x) == 4 ? (0) : (-1))))))
bogdanm 82:6473597d706e 237 /* @brief Has DMA request (register bit field PCR[IRQC] values).*/
bogdanm 82:6473597d706e 238 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
bogdanm 82:6473597d706e 239 /* @brief Has pull resistor selection (register bit PCR[PS]).*/
bogdanm 82:6473597d706e 240 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
bogdanm 82:6473597d706e 241 /* @brief Has separate pull resistor enable registers (PUEL and PUEH).*/
bogdanm 82:6473597d706e 242 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE_REGISTER (0)
bogdanm 82:6473597d706e 243 /* @brief Has slew rate control (register bit PCR[SRE]).*/
bogdanm 82:6473597d706e 244 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
bogdanm 82:6473597d706e 245 /* @brief Has passive filter (register bit field PCR[PFE]).*/
bogdanm 82:6473597d706e 246 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
bogdanm 82:6473597d706e 247 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTERn(x) \
bogdanm 82:6473597d706e 248 ((x) == 0 ? (1) : \
bogdanm 82:6473597d706e 249 ((x) == 1 ? (0) : \
bogdanm 82:6473597d706e 250 ((x) == 2 ? (0) : \
bogdanm 82:6473597d706e 251 ((x) == 3 ? (0) : \
bogdanm 82:6473597d706e 252 ((x) == 4 ? (0) : (-1))))))
bogdanm 82:6473597d706e 253 /* @brief Has drive strength control (register bit PCR[DSE]).*/
bogdanm 82:6473597d706e 254 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
bogdanm 82:6473597d706e 255 /* @brief Has separate drive strength register (HDRVE).*/
bogdanm 82:6473597d706e 256 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
bogdanm 82:6473597d706e 257 /* @brief Has glitch filter (register IOFLT).*/
bogdanm 82:6473597d706e 258 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
bogdanm 82:6473597d706e 259 #else
bogdanm 82:6473597d706e 260 #error "No valid CPU defined!"
bogdanm 82:6473597d706e 261 #endif
bogdanm 82:6473597d706e 262
bogdanm 82:6473597d706e 263 #endif /* __FSL_PORT_FEATURES_H__*/
bogdanm 82:6473597d706e 264 /*******************************************************************************
bogdanm 82:6473597d706e 265 * EOF
bogdanm 82:6473597d706e 266 ******************************************************************************/
bogdanm 82:6473597d706e 267