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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_rcm.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_RCM_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_RCM_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 RCM
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * Reset Control Module
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_RCM_SRS0 - System Reset Status Register 0
bogdanm 82:6473597d706e 33 * - HW_RCM_SRS1 - System Reset Status Register 1
bogdanm 82:6473597d706e 34 * - HW_RCM_RPFC - Reset Pin Filter Control register
bogdanm 82:6473597d706e 35 * - HW_RCM_RPFW - Reset Pin Filter Width register
bogdanm 82:6473597d706e 36 * - HW_RCM_MR - Mode Register
bogdanm 82:6473597d706e 37 *
bogdanm 82:6473597d706e 38 * - hw_rcm_t - Struct containing all module registers.
bogdanm 82:6473597d706e 39 */
bogdanm 82:6473597d706e 40
bogdanm 82:6473597d706e 41 //! @name Module base addresses
bogdanm 82:6473597d706e 42 //@{
bogdanm 82:6473597d706e 43 #ifndef REGS_RCM_BASE
bogdanm 82:6473597d706e 44 #define HW_RCM_INSTANCE_COUNT (1U) //!< Number of instances of the RCM module.
bogdanm 82:6473597d706e 45 #define REGS_RCM_BASE (0x4007F000U) //!< Base address for RCM.
bogdanm 82:6473597d706e 46 #endif
bogdanm 82:6473597d706e 47 //@}
bogdanm 82:6473597d706e 48
bogdanm 82:6473597d706e 49 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 50 // HW_RCM_SRS0 - System Reset Status Register 0
bogdanm 82:6473597d706e 51 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 52
bogdanm 82:6473597d706e 53 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 54 /*!
bogdanm 82:6473597d706e 55 * @brief HW_RCM_SRS0 - System Reset Status Register 0 (RO)
bogdanm 82:6473597d706e 56 *
bogdanm 82:6473597d706e 57 * Reset value: 0x82U
bogdanm 82:6473597d706e 58 *
bogdanm 82:6473597d706e 59 * This register includes read-only status flags to indicate the source of the
bogdanm 82:6473597d706e 60 * most recent reset. The reset state of these bits depends on what caused the MCU
bogdanm 82:6473597d706e 61 * to reset. The reset value of this register depends on the reset source: POR
bogdanm 82:6473597d706e 62 * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
bogdanm 82:6473597d706e 63 * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
bogdanm 82:6473597d706e 64 * reset - a bit is set if its corresponding reset source caused the reset
bogdanm 82:6473597d706e 65 */
bogdanm 82:6473597d706e 66 typedef union _hw_rcm_srs0
bogdanm 82:6473597d706e 67 {
bogdanm 82:6473597d706e 68 uint8_t U;
bogdanm 82:6473597d706e 69 struct _hw_rcm_srs0_bitfields
bogdanm 82:6473597d706e 70 {
bogdanm 82:6473597d706e 71 uint8_t WAKEUP : 1; //!< [0] Low Leakage Wakeup Reset
bogdanm 82:6473597d706e 72 uint8_t LVD : 1; //!< [1] Low-Voltage Detect Reset
bogdanm 82:6473597d706e 73 uint8_t LOC : 1; //!< [2] Loss-of-Clock Reset
bogdanm 82:6473597d706e 74 uint8_t LOL : 1; //!< [3] Loss-of-Lock Reset
bogdanm 82:6473597d706e 75 uint8_t RESERVED0 : 1; //!< [4]
bogdanm 82:6473597d706e 76 uint8_t WDOGb : 1; //!< [5] Watchdog
bogdanm 82:6473597d706e 77 uint8_t PIN : 1; //!< [6] External Reset Pin
bogdanm 82:6473597d706e 78 uint8_t POR : 1; //!< [7] Power-On Reset
bogdanm 82:6473597d706e 79 } B;
bogdanm 82:6473597d706e 80 } hw_rcm_srs0_t;
bogdanm 82:6473597d706e 81 #endif
bogdanm 82:6473597d706e 82
bogdanm 82:6473597d706e 83 /*!
bogdanm 82:6473597d706e 84 * @name Constants and macros for entire RCM_SRS0 register
bogdanm 82:6473597d706e 85 */
bogdanm 82:6473597d706e 86 //@{
bogdanm 82:6473597d706e 87 #define HW_RCM_SRS0_ADDR (REGS_RCM_BASE + 0x0U)
bogdanm 82:6473597d706e 88
bogdanm 82:6473597d706e 89 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 90 #define HW_RCM_SRS0 (*(__I hw_rcm_srs0_t *) HW_RCM_SRS0_ADDR)
bogdanm 82:6473597d706e 91 #define HW_RCM_SRS0_RD() (HW_RCM_SRS0.U)
bogdanm 82:6473597d706e 92 #endif
bogdanm 82:6473597d706e 93 //@}
bogdanm 82:6473597d706e 94
bogdanm 82:6473597d706e 95 /*
bogdanm 82:6473597d706e 96 * Constants & macros for individual RCM_SRS0 bitfields
bogdanm 82:6473597d706e 97 */
bogdanm 82:6473597d706e 98
bogdanm 82:6473597d706e 99 /*!
bogdanm 82:6473597d706e 100 * @name Register RCM_SRS0, field WAKEUP[0] (RO)
bogdanm 82:6473597d706e 101 *
bogdanm 82:6473597d706e 102 * Indicates a reset has been caused by an enabled LLWU module wakeup source
bogdanm 82:6473597d706e 103 * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
bogdanm 82:6473597d706e 104 * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
bogdanm 82:6473597d706e 105 * mode causes a reset. This bit is cleared by any reset except WAKEUP.
bogdanm 82:6473597d706e 106 *
bogdanm 82:6473597d706e 107 * Values:
bogdanm 82:6473597d706e 108 * - 0 - Reset not caused by LLWU module wakeup source
bogdanm 82:6473597d706e 109 * - 1 - Reset caused by LLWU module wakeup source
bogdanm 82:6473597d706e 110 */
bogdanm 82:6473597d706e 111 //@{
bogdanm 82:6473597d706e 112 #define BP_RCM_SRS0_WAKEUP (0U) //!< Bit position for RCM_SRS0_WAKEUP.
bogdanm 82:6473597d706e 113 #define BM_RCM_SRS0_WAKEUP (0x01U) //!< Bit mask for RCM_SRS0_WAKEUP.
bogdanm 82:6473597d706e 114 #define BS_RCM_SRS0_WAKEUP (1U) //!< Bit field size in bits for RCM_SRS0_WAKEUP.
bogdanm 82:6473597d706e 115
bogdanm 82:6473597d706e 116 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 117 //! @brief Read current value of the RCM_SRS0_WAKEUP field.
bogdanm 82:6473597d706e 118 #define BR_RCM_SRS0_WAKEUP (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_WAKEUP))
bogdanm 82:6473597d706e 119 #endif
bogdanm 82:6473597d706e 120 //@}
bogdanm 82:6473597d706e 121
bogdanm 82:6473597d706e 122 /*!
bogdanm 82:6473597d706e 123 * @name Register RCM_SRS0, field LVD[1] (RO)
bogdanm 82:6473597d706e 124 *
bogdanm 82:6473597d706e 125 * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
bogdanm 82:6473597d706e 126 * an LVD reset occurs. This field is also set by POR.
bogdanm 82:6473597d706e 127 *
bogdanm 82:6473597d706e 128 * Values:
bogdanm 82:6473597d706e 129 * - 0 - Reset not caused by LVD trip or POR
bogdanm 82:6473597d706e 130 * - 1 - Reset caused by LVD trip or POR
bogdanm 82:6473597d706e 131 */
bogdanm 82:6473597d706e 132 //@{
bogdanm 82:6473597d706e 133 #define BP_RCM_SRS0_LVD (1U) //!< Bit position for RCM_SRS0_LVD.
bogdanm 82:6473597d706e 134 #define BM_RCM_SRS0_LVD (0x02U) //!< Bit mask for RCM_SRS0_LVD.
bogdanm 82:6473597d706e 135 #define BS_RCM_SRS0_LVD (1U) //!< Bit field size in bits for RCM_SRS0_LVD.
bogdanm 82:6473597d706e 136
bogdanm 82:6473597d706e 137 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 138 //! @brief Read current value of the RCM_SRS0_LVD field.
bogdanm 82:6473597d706e 139 #define BR_RCM_SRS0_LVD (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LVD))
bogdanm 82:6473597d706e 140 #endif
bogdanm 82:6473597d706e 141 //@}
bogdanm 82:6473597d706e 142
bogdanm 82:6473597d706e 143 /*!
bogdanm 82:6473597d706e 144 * @name Register RCM_SRS0, field LOC[2] (RO)
bogdanm 82:6473597d706e 145 *
bogdanm 82:6473597d706e 146 * Indicates a reset has been caused by a loss of external clock. The MCG clock
bogdanm 82:6473597d706e 147 * monitor must be enabled for a loss of clock to be detected. Refer to the
bogdanm 82:6473597d706e 148 * detailed MCG description for information on enabling the clock monitor.
bogdanm 82:6473597d706e 149 *
bogdanm 82:6473597d706e 150 * Values:
bogdanm 82:6473597d706e 151 * - 0 - Reset not caused by a loss of external clock.
bogdanm 82:6473597d706e 152 * - 1 - Reset caused by a loss of external clock.
bogdanm 82:6473597d706e 153 */
bogdanm 82:6473597d706e 154 //@{
bogdanm 82:6473597d706e 155 #define BP_RCM_SRS0_LOC (2U) //!< Bit position for RCM_SRS0_LOC.
bogdanm 82:6473597d706e 156 #define BM_RCM_SRS0_LOC (0x04U) //!< Bit mask for RCM_SRS0_LOC.
bogdanm 82:6473597d706e 157 #define BS_RCM_SRS0_LOC (1U) //!< Bit field size in bits for RCM_SRS0_LOC.
bogdanm 82:6473597d706e 158
bogdanm 82:6473597d706e 159 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 160 //! @brief Read current value of the RCM_SRS0_LOC field.
bogdanm 82:6473597d706e 161 #define BR_RCM_SRS0_LOC (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LOC))
bogdanm 82:6473597d706e 162 #endif
bogdanm 82:6473597d706e 163 //@}
bogdanm 82:6473597d706e 164
bogdanm 82:6473597d706e 165 /*!
bogdanm 82:6473597d706e 166 * @name Register RCM_SRS0, field LOL[3] (RO)
bogdanm 82:6473597d706e 167 *
bogdanm 82:6473597d706e 168 * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
bogdanm 82:6473597d706e 169 * MCG description for information on the loss-of-clock event.
bogdanm 82:6473597d706e 170 *
bogdanm 82:6473597d706e 171 * Values:
bogdanm 82:6473597d706e 172 * - 0 - Reset not caused by a loss of lock in the PLL
bogdanm 82:6473597d706e 173 * - 1 - Reset caused by a loss of lock in the PLL
bogdanm 82:6473597d706e 174 */
bogdanm 82:6473597d706e 175 //@{
bogdanm 82:6473597d706e 176 #define BP_RCM_SRS0_LOL (3U) //!< Bit position for RCM_SRS0_LOL.
bogdanm 82:6473597d706e 177 #define BM_RCM_SRS0_LOL (0x08U) //!< Bit mask for RCM_SRS0_LOL.
bogdanm 82:6473597d706e 178 #define BS_RCM_SRS0_LOL (1U) //!< Bit field size in bits for RCM_SRS0_LOL.
bogdanm 82:6473597d706e 179
bogdanm 82:6473597d706e 180 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 181 //! @brief Read current value of the RCM_SRS0_LOL field.
bogdanm 82:6473597d706e 182 #define BR_RCM_SRS0_LOL (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LOL))
bogdanm 82:6473597d706e 183 #endif
bogdanm 82:6473597d706e 184 //@}
bogdanm 82:6473597d706e 185
bogdanm 82:6473597d706e 186 /*!
bogdanm 82:6473597d706e 187 * @name Register RCM_SRS0, field WDOG[5] (RO)
bogdanm 82:6473597d706e 188 *
bogdanm 82:6473597d706e 189 * Indicates a reset has been caused by the watchdog timer Computer Operating
bogdanm 82:6473597d706e 190 * Properly (COP) timing out. This reset source can be blocked by disabling the COP
bogdanm 82:6473597d706e 191 * watchdog: write 00 to SIM_COPCTRL[COPT].
bogdanm 82:6473597d706e 192 *
bogdanm 82:6473597d706e 193 * Values:
bogdanm 82:6473597d706e 194 * - 0 - Reset not caused by watchdog timeout
bogdanm 82:6473597d706e 195 * - 1 - Reset caused by watchdog timeout
bogdanm 82:6473597d706e 196 */
bogdanm 82:6473597d706e 197 //@{
bogdanm 82:6473597d706e 198 #define BP_RCM_SRS0_WDOG (5U) //!< Bit position for RCM_SRS0_WDOG.
bogdanm 82:6473597d706e 199 #define BM_RCM_SRS0_WDOG (0x20U) //!< Bit mask for RCM_SRS0_WDOG.
bogdanm 82:6473597d706e 200 #define BS_RCM_SRS0_WDOG (1U) //!< Bit field size in bits for RCM_SRS0_WDOG.
bogdanm 82:6473597d706e 201
bogdanm 82:6473597d706e 202 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 203 //! @brief Read current value of the RCM_SRS0_WDOG field.
bogdanm 82:6473597d706e 204 #define BR_RCM_SRS0_WDOG (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_WDOG))
bogdanm 82:6473597d706e 205 #endif
bogdanm 82:6473597d706e 206 //@}
bogdanm 82:6473597d706e 207
bogdanm 82:6473597d706e 208 /*!
bogdanm 82:6473597d706e 209 * @name Register RCM_SRS0, field PIN[6] (RO)
bogdanm 82:6473597d706e 210 *
bogdanm 82:6473597d706e 211 * Indicates a reset has been caused by an active-low level on the external
bogdanm 82:6473597d706e 212 * RESET pin.
bogdanm 82:6473597d706e 213 *
bogdanm 82:6473597d706e 214 * Values:
bogdanm 82:6473597d706e 215 * - 0 - Reset not caused by external reset pin
bogdanm 82:6473597d706e 216 * - 1 - Reset caused by external reset pin
bogdanm 82:6473597d706e 217 */
bogdanm 82:6473597d706e 218 //@{
bogdanm 82:6473597d706e 219 #define BP_RCM_SRS0_PIN (6U) //!< Bit position for RCM_SRS0_PIN.
bogdanm 82:6473597d706e 220 #define BM_RCM_SRS0_PIN (0x40U) //!< Bit mask for RCM_SRS0_PIN.
bogdanm 82:6473597d706e 221 #define BS_RCM_SRS0_PIN (1U) //!< Bit field size in bits for RCM_SRS0_PIN.
bogdanm 82:6473597d706e 222
bogdanm 82:6473597d706e 223 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 224 //! @brief Read current value of the RCM_SRS0_PIN field.
bogdanm 82:6473597d706e 225 #define BR_RCM_SRS0_PIN (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_PIN))
bogdanm 82:6473597d706e 226 #endif
bogdanm 82:6473597d706e 227 //@}
bogdanm 82:6473597d706e 228
bogdanm 82:6473597d706e 229 /*!
bogdanm 82:6473597d706e 230 * @name Register RCM_SRS0, field POR[7] (RO)
bogdanm 82:6473597d706e 231 *
bogdanm 82:6473597d706e 232 * Indicates a reset has been caused by the power-on detection logic. Because
bogdanm 82:6473597d706e 233 * the internal supply voltage was ramping up at the time, the low-voltage reset
bogdanm 82:6473597d706e 234 * (LVD) status bit is also set to indicate that the reset occurred while the
bogdanm 82:6473597d706e 235 * internal supply was below the LVD threshold.
bogdanm 82:6473597d706e 236 *
bogdanm 82:6473597d706e 237 * Values:
bogdanm 82:6473597d706e 238 * - 0 - Reset not caused by POR
bogdanm 82:6473597d706e 239 * - 1 - Reset caused by POR
bogdanm 82:6473597d706e 240 */
bogdanm 82:6473597d706e 241 //@{
bogdanm 82:6473597d706e 242 #define BP_RCM_SRS0_POR (7U) //!< Bit position for RCM_SRS0_POR.
bogdanm 82:6473597d706e 243 #define BM_RCM_SRS0_POR (0x80U) //!< Bit mask for RCM_SRS0_POR.
bogdanm 82:6473597d706e 244 #define BS_RCM_SRS0_POR (1U) //!< Bit field size in bits for RCM_SRS0_POR.
bogdanm 82:6473597d706e 245
bogdanm 82:6473597d706e 246 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 247 //! @brief Read current value of the RCM_SRS0_POR field.
bogdanm 82:6473597d706e 248 #define BR_RCM_SRS0_POR (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_POR))
bogdanm 82:6473597d706e 249 #endif
bogdanm 82:6473597d706e 250 //@}
bogdanm 82:6473597d706e 251
bogdanm 82:6473597d706e 252 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 253 // HW_RCM_SRS1 - System Reset Status Register 1
bogdanm 82:6473597d706e 254 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 255
bogdanm 82:6473597d706e 256 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 257 /*!
bogdanm 82:6473597d706e 258 * @brief HW_RCM_SRS1 - System Reset Status Register 1 (RO)
bogdanm 82:6473597d706e 259 *
bogdanm 82:6473597d706e 260 * Reset value: 0x00U
bogdanm 82:6473597d706e 261 *
bogdanm 82:6473597d706e 262 * This register includes read-only status flags to indicate the source of the
bogdanm 82:6473597d706e 263 * most recent reset. The reset state of these bits depends on what caused the MCU
bogdanm 82:6473597d706e 264 * to reset. The reset value of this register depends on the reset source: POR
bogdanm 82:6473597d706e 265 * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
bogdanm 82:6473597d706e 266 * reset - a bit is set if its corresponding reset source caused the reset
bogdanm 82:6473597d706e 267 */
bogdanm 82:6473597d706e 268 typedef union _hw_rcm_srs1
bogdanm 82:6473597d706e 269 {
bogdanm 82:6473597d706e 270 uint8_t U;
bogdanm 82:6473597d706e 271 struct _hw_rcm_srs1_bitfields
bogdanm 82:6473597d706e 272 {
bogdanm 82:6473597d706e 273 uint8_t JTAG : 1; //!< [0] JTAG Generated Reset
bogdanm 82:6473597d706e 274 uint8_t LOCKUP : 1; //!< [1] Core Lockup
bogdanm 82:6473597d706e 275 uint8_t SW : 1; //!< [2] Software
bogdanm 82:6473597d706e 276 uint8_t MDM_AP : 1; //!< [3] MDM-AP System Reset Request
bogdanm 82:6473597d706e 277 uint8_t EZPT : 1; //!< [4] EzPort Reset
bogdanm 82:6473597d706e 278 uint8_t SACKERR : 1; //!< [5] Stop Mode Acknowledge Error Reset
bogdanm 82:6473597d706e 279 uint8_t RESERVED0 : 2; //!< [7:6]
bogdanm 82:6473597d706e 280 } B;
bogdanm 82:6473597d706e 281 } hw_rcm_srs1_t;
bogdanm 82:6473597d706e 282 #endif
bogdanm 82:6473597d706e 283
bogdanm 82:6473597d706e 284 /*!
bogdanm 82:6473597d706e 285 * @name Constants and macros for entire RCM_SRS1 register
bogdanm 82:6473597d706e 286 */
bogdanm 82:6473597d706e 287 //@{
bogdanm 82:6473597d706e 288 #define HW_RCM_SRS1_ADDR (REGS_RCM_BASE + 0x1U)
bogdanm 82:6473597d706e 289
bogdanm 82:6473597d706e 290 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 291 #define HW_RCM_SRS1 (*(__I hw_rcm_srs1_t *) HW_RCM_SRS1_ADDR)
bogdanm 82:6473597d706e 292 #define HW_RCM_SRS1_RD() (HW_RCM_SRS1.U)
bogdanm 82:6473597d706e 293 #endif
bogdanm 82:6473597d706e 294 //@}
bogdanm 82:6473597d706e 295
bogdanm 82:6473597d706e 296 /*
bogdanm 82:6473597d706e 297 * Constants & macros for individual RCM_SRS1 bitfields
bogdanm 82:6473597d706e 298 */
bogdanm 82:6473597d706e 299
bogdanm 82:6473597d706e 300 /*!
bogdanm 82:6473597d706e 301 * @name Register RCM_SRS1, field JTAG[0] (RO)
bogdanm 82:6473597d706e 302 *
bogdanm 82:6473597d706e 303 * Indicates a reset has been caused by JTAG selection of certain IR codes:
bogdanm 82:6473597d706e 304 * EZPORT, EXTEST, HIGHZ, and CLAMP.
bogdanm 82:6473597d706e 305 *
bogdanm 82:6473597d706e 306 * Values:
bogdanm 82:6473597d706e 307 * - 0 - Reset not caused by JTAG
bogdanm 82:6473597d706e 308 * - 1 - Reset caused by JTAG
bogdanm 82:6473597d706e 309 */
bogdanm 82:6473597d706e 310 //@{
bogdanm 82:6473597d706e 311 #define BP_RCM_SRS1_JTAG (0U) //!< Bit position for RCM_SRS1_JTAG.
bogdanm 82:6473597d706e 312 #define BM_RCM_SRS1_JTAG (0x01U) //!< Bit mask for RCM_SRS1_JTAG.
bogdanm 82:6473597d706e 313 #define BS_RCM_SRS1_JTAG (1U) //!< Bit field size in bits for RCM_SRS1_JTAG.
bogdanm 82:6473597d706e 314
bogdanm 82:6473597d706e 315 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 316 //! @brief Read current value of the RCM_SRS1_JTAG field.
bogdanm 82:6473597d706e 317 #define BR_RCM_SRS1_JTAG (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_JTAG))
bogdanm 82:6473597d706e 318 #endif
bogdanm 82:6473597d706e 319 //@}
bogdanm 82:6473597d706e 320
bogdanm 82:6473597d706e 321 /*!
bogdanm 82:6473597d706e 322 * @name Register RCM_SRS1, field LOCKUP[1] (RO)
bogdanm 82:6473597d706e 323 *
bogdanm 82:6473597d706e 324 * Indicates a reset has been caused by the ARM core indication of a LOCKUP
bogdanm 82:6473597d706e 325 * event.
bogdanm 82:6473597d706e 326 *
bogdanm 82:6473597d706e 327 * Values:
bogdanm 82:6473597d706e 328 * - 0 - Reset not caused by core LOCKUP event
bogdanm 82:6473597d706e 329 * - 1 - Reset caused by core LOCKUP event
bogdanm 82:6473597d706e 330 */
bogdanm 82:6473597d706e 331 //@{
bogdanm 82:6473597d706e 332 #define BP_RCM_SRS1_LOCKUP (1U) //!< Bit position for RCM_SRS1_LOCKUP.
bogdanm 82:6473597d706e 333 #define BM_RCM_SRS1_LOCKUP (0x02U) //!< Bit mask for RCM_SRS1_LOCKUP.
bogdanm 82:6473597d706e 334 #define BS_RCM_SRS1_LOCKUP (1U) //!< Bit field size in bits for RCM_SRS1_LOCKUP.
bogdanm 82:6473597d706e 335
bogdanm 82:6473597d706e 336 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 337 //! @brief Read current value of the RCM_SRS1_LOCKUP field.
bogdanm 82:6473597d706e 338 #define BR_RCM_SRS1_LOCKUP (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_LOCKUP))
bogdanm 82:6473597d706e 339 #endif
bogdanm 82:6473597d706e 340 //@}
bogdanm 82:6473597d706e 341
bogdanm 82:6473597d706e 342 /*!
bogdanm 82:6473597d706e 343 * @name Register RCM_SRS1, field SW[2] (RO)
bogdanm 82:6473597d706e 344 *
bogdanm 82:6473597d706e 345 * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
bogdanm 82:6473597d706e 346 * Application Interrupt and Reset Control Register in the ARM core.
bogdanm 82:6473597d706e 347 *
bogdanm 82:6473597d706e 348 * Values:
bogdanm 82:6473597d706e 349 * - 0 - Reset not caused by software setting of SYSRESETREQ bit
bogdanm 82:6473597d706e 350 * - 1 - Reset caused by software setting of SYSRESETREQ bit
bogdanm 82:6473597d706e 351 */
bogdanm 82:6473597d706e 352 //@{
bogdanm 82:6473597d706e 353 #define BP_RCM_SRS1_SW (2U) //!< Bit position for RCM_SRS1_SW.
bogdanm 82:6473597d706e 354 #define BM_RCM_SRS1_SW (0x04U) //!< Bit mask for RCM_SRS1_SW.
bogdanm 82:6473597d706e 355 #define BS_RCM_SRS1_SW (1U) //!< Bit field size in bits for RCM_SRS1_SW.
bogdanm 82:6473597d706e 356
bogdanm 82:6473597d706e 357 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 358 //! @brief Read current value of the RCM_SRS1_SW field.
bogdanm 82:6473597d706e 359 #define BR_RCM_SRS1_SW (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_SW))
bogdanm 82:6473597d706e 360 #endif
bogdanm 82:6473597d706e 361 //@}
bogdanm 82:6473597d706e 362
bogdanm 82:6473597d706e 363 /*!
bogdanm 82:6473597d706e 364 * @name Register RCM_SRS1, field MDM_AP[3] (RO)
bogdanm 82:6473597d706e 365 *
bogdanm 82:6473597d706e 366 * Indicates a reset has been caused by the host debugger system setting of the
bogdanm 82:6473597d706e 367 * System Reset Request bit in the MDM-AP Control Register.
bogdanm 82:6473597d706e 368 *
bogdanm 82:6473597d706e 369 * Values:
bogdanm 82:6473597d706e 370 * - 0 - Reset not caused by host debugger system setting of the System Reset
bogdanm 82:6473597d706e 371 * Request bit
bogdanm 82:6473597d706e 372 * - 1 - Reset caused by host debugger system setting of the System Reset
bogdanm 82:6473597d706e 373 * Request bit
bogdanm 82:6473597d706e 374 */
bogdanm 82:6473597d706e 375 //@{
bogdanm 82:6473597d706e 376 #define BP_RCM_SRS1_MDM_AP (3U) //!< Bit position for RCM_SRS1_MDM_AP.
bogdanm 82:6473597d706e 377 #define BM_RCM_SRS1_MDM_AP (0x08U) //!< Bit mask for RCM_SRS1_MDM_AP.
bogdanm 82:6473597d706e 378 #define BS_RCM_SRS1_MDM_AP (1U) //!< Bit field size in bits for RCM_SRS1_MDM_AP.
bogdanm 82:6473597d706e 379
bogdanm 82:6473597d706e 380 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 381 //! @brief Read current value of the RCM_SRS1_MDM_AP field.
bogdanm 82:6473597d706e 382 #define BR_RCM_SRS1_MDM_AP (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_MDM_AP))
bogdanm 82:6473597d706e 383 #endif
bogdanm 82:6473597d706e 384 //@}
bogdanm 82:6473597d706e 385
bogdanm 82:6473597d706e 386 /*!
bogdanm 82:6473597d706e 387 * @name Register RCM_SRS1, field EZPT[4] (RO)
bogdanm 82:6473597d706e 388 *
bogdanm 82:6473597d706e 389 * Indicates a reset has been caused by EzPort receiving the RESET command while
bogdanm 82:6473597d706e 390 * the device is in EzPort mode.
bogdanm 82:6473597d706e 391 *
bogdanm 82:6473597d706e 392 * Values:
bogdanm 82:6473597d706e 393 * - 0 - Reset not caused by EzPort receiving the RESET command while the device
bogdanm 82:6473597d706e 394 * is in EzPort mode
bogdanm 82:6473597d706e 395 * - 1 - Reset caused by EzPort receiving the RESET command while the device is
bogdanm 82:6473597d706e 396 * in EzPort mode
bogdanm 82:6473597d706e 397 */
bogdanm 82:6473597d706e 398 //@{
bogdanm 82:6473597d706e 399 #define BP_RCM_SRS1_EZPT (4U) //!< Bit position for RCM_SRS1_EZPT.
bogdanm 82:6473597d706e 400 #define BM_RCM_SRS1_EZPT (0x10U) //!< Bit mask for RCM_SRS1_EZPT.
bogdanm 82:6473597d706e 401 #define BS_RCM_SRS1_EZPT (1U) //!< Bit field size in bits for RCM_SRS1_EZPT.
bogdanm 82:6473597d706e 402
bogdanm 82:6473597d706e 403 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 404 //! @brief Read current value of the RCM_SRS1_EZPT field.
bogdanm 82:6473597d706e 405 #define BR_RCM_SRS1_EZPT (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_EZPT))
bogdanm 82:6473597d706e 406 #endif
bogdanm 82:6473597d706e 407 //@}
bogdanm 82:6473597d706e 408
bogdanm 82:6473597d706e 409 /*!
bogdanm 82:6473597d706e 410 * @name Register RCM_SRS1, field SACKERR[5] (RO)
bogdanm 82:6473597d706e 411 *
bogdanm 82:6473597d706e 412 * Indicates that after an attempt to enter Stop mode, a reset has been caused
bogdanm 82:6473597d706e 413 * by a failure of one or more peripherals to acknowledge within approximately one
bogdanm 82:6473597d706e 414 * second to enter stop mode.
bogdanm 82:6473597d706e 415 *
bogdanm 82:6473597d706e 416 * Values:
bogdanm 82:6473597d706e 417 * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter
bogdanm 82:6473597d706e 418 * stop mode
bogdanm 82:6473597d706e 419 * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop
bogdanm 82:6473597d706e 420 * mode
bogdanm 82:6473597d706e 421 */
bogdanm 82:6473597d706e 422 //@{
bogdanm 82:6473597d706e 423 #define BP_RCM_SRS1_SACKERR (5U) //!< Bit position for RCM_SRS1_SACKERR.
bogdanm 82:6473597d706e 424 #define BM_RCM_SRS1_SACKERR (0x20U) //!< Bit mask for RCM_SRS1_SACKERR.
bogdanm 82:6473597d706e 425 #define BS_RCM_SRS1_SACKERR (1U) //!< Bit field size in bits for RCM_SRS1_SACKERR.
bogdanm 82:6473597d706e 426
bogdanm 82:6473597d706e 427 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 428 //! @brief Read current value of the RCM_SRS1_SACKERR field.
bogdanm 82:6473597d706e 429 #define BR_RCM_SRS1_SACKERR (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_SACKERR))
bogdanm 82:6473597d706e 430 #endif
bogdanm 82:6473597d706e 431 //@}
bogdanm 82:6473597d706e 432
bogdanm 82:6473597d706e 433 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 434 // HW_RCM_RPFC - Reset Pin Filter Control register
bogdanm 82:6473597d706e 435 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 436
bogdanm 82:6473597d706e 437 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 438 /*!
bogdanm 82:6473597d706e 439 * @brief HW_RCM_RPFC - Reset Pin Filter Control register (RW)
bogdanm 82:6473597d706e 440 *
bogdanm 82:6473597d706e 441 * Reset value: 0x00U
bogdanm 82:6473597d706e 442 *
bogdanm 82:6473597d706e 443 * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
bogdanm 82:6473597d706e 444 * other reset types. The bus clock filter is reset when disabled or when entering
bogdanm 82:6473597d706e 445 * stop mode. The LPO filter is reset when disabled or when entering any low
bogdanm 82:6473597d706e 446 * leakage stop mode .
bogdanm 82:6473597d706e 447 */
bogdanm 82:6473597d706e 448 typedef union _hw_rcm_rpfc
bogdanm 82:6473597d706e 449 {
bogdanm 82:6473597d706e 450 uint8_t U;
bogdanm 82:6473597d706e 451 struct _hw_rcm_rpfc_bitfields
bogdanm 82:6473597d706e 452 {
bogdanm 82:6473597d706e 453 uint8_t RSTFLTSRW : 2; //!< [1:0] Reset Pin Filter Select in Run and
bogdanm 82:6473597d706e 454 //! Wait Modes
bogdanm 82:6473597d706e 455 uint8_t RSTFLTSS : 1; //!< [2] Reset Pin Filter Select in Stop Mode
bogdanm 82:6473597d706e 456 uint8_t RESERVED0 : 5; //!< [7:3]
bogdanm 82:6473597d706e 457 } B;
bogdanm 82:6473597d706e 458 } hw_rcm_rpfc_t;
bogdanm 82:6473597d706e 459 #endif
bogdanm 82:6473597d706e 460
bogdanm 82:6473597d706e 461 /*!
bogdanm 82:6473597d706e 462 * @name Constants and macros for entire RCM_RPFC register
bogdanm 82:6473597d706e 463 */
bogdanm 82:6473597d706e 464 //@{
bogdanm 82:6473597d706e 465 #define HW_RCM_RPFC_ADDR (REGS_RCM_BASE + 0x4U)
bogdanm 82:6473597d706e 466
bogdanm 82:6473597d706e 467 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 468 #define HW_RCM_RPFC (*(__IO hw_rcm_rpfc_t *) HW_RCM_RPFC_ADDR)
bogdanm 82:6473597d706e 469 #define HW_RCM_RPFC_RD() (HW_RCM_RPFC.U)
bogdanm 82:6473597d706e 470 #define HW_RCM_RPFC_WR(v) (HW_RCM_RPFC.U = (v))
bogdanm 82:6473597d706e 471 #define HW_RCM_RPFC_SET(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() | (v)))
bogdanm 82:6473597d706e 472 #define HW_RCM_RPFC_CLR(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() & ~(v)))
bogdanm 82:6473597d706e 473 #define HW_RCM_RPFC_TOG(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() ^ (v)))
bogdanm 82:6473597d706e 474 #endif
bogdanm 82:6473597d706e 475 //@}
bogdanm 82:6473597d706e 476
bogdanm 82:6473597d706e 477 /*
bogdanm 82:6473597d706e 478 * Constants & macros for individual RCM_RPFC bitfields
bogdanm 82:6473597d706e 479 */
bogdanm 82:6473597d706e 480
bogdanm 82:6473597d706e 481 /*!
bogdanm 82:6473597d706e 482 * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
bogdanm 82:6473597d706e 483 *
bogdanm 82:6473597d706e 484 * Selects how the reset pin filter is enabled in run and wait modes.
bogdanm 82:6473597d706e 485 *
bogdanm 82:6473597d706e 486 * Values:
bogdanm 82:6473597d706e 487 * - 00 - All filtering disabled
bogdanm 82:6473597d706e 488 * - 01 - Bus clock filter enabled for normal operation
bogdanm 82:6473597d706e 489 * - 10 - LPO clock filter enabled for normal operation
bogdanm 82:6473597d706e 490 * - 11 - Reserved
bogdanm 82:6473597d706e 491 */
bogdanm 82:6473597d706e 492 //@{
bogdanm 82:6473597d706e 493 #define BP_RCM_RPFC_RSTFLTSRW (0U) //!< Bit position for RCM_RPFC_RSTFLTSRW.
bogdanm 82:6473597d706e 494 #define BM_RCM_RPFC_RSTFLTSRW (0x03U) //!< Bit mask for RCM_RPFC_RSTFLTSRW.
bogdanm 82:6473597d706e 495 #define BS_RCM_RPFC_RSTFLTSRW (2U) //!< Bit field size in bits for RCM_RPFC_RSTFLTSRW.
bogdanm 82:6473597d706e 496
bogdanm 82:6473597d706e 497 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 498 //! @brief Read current value of the RCM_RPFC_RSTFLTSRW field.
bogdanm 82:6473597d706e 499 #define BR_RCM_RPFC_RSTFLTSRW (HW_RCM_RPFC.B.RSTFLTSRW)
bogdanm 82:6473597d706e 500 #endif
bogdanm 82:6473597d706e 501
bogdanm 82:6473597d706e 502 //! @brief Format value for bitfield RCM_RPFC_RSTFLTSRW.
bogdanm 82:6473597d706e 503 #define BF_RCM_RPFC_RSTFLTSRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFC_RSTFLTSRW), uint8_t) & BM_RCM_RPFC_RSTFLTSRW)
bogdanm 82:6473597d706e 504
bogdanm 82:6473597d706e 505 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 506 //! @brief Set the RSTFLTSRW field to a new value.
bogdanm 82:6473597d706e 507 #define BW_RCM_RPFC_RSTFLTSRW(v) (HW_RCM_RPFC_WR((HW_RCM_RPFC_RD() & ~BM_RCM_RPFC_RSTFLTSRW) | BF_RCM_RPFC_RSTFLTSRW(v)))
bogdanm 82:6473597d706e 508 #endif
bogdanm 82:6473597d706e 509 //@}
bogdanm 82:6473597d706e 510
bogdanm 82:6473597d706e 511 /*!
bogdanm 82:6473597d706e 512 * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
bogdanm 82:6473597d706e 513 *
bogdanm 82:6473597d706e 514 * Selects how the reset pin filter is enabled in Stop and VLPS modes
bogdanm 82:6473597d706e 515 *
bogdanm 82:6473597d706e 516 * Values:
bogdanm 82:6473597d706e 517 * - 0 - All filtering disabled
bogdanm 82:6473597d706e 518 * - 1 - LPO clock filter enabled
bogdanm 82:6473597d706e 519 */
bogdanm 82:6473597d706e 520 //@{
bogdanm 82:6473597d706e 521 #define BP_RCM_RPFC_RSTFLTSS (2U) //!< Bit position for RCM_RPFC_RSTFLTSS.
bogdanm 82:6473597d706e 522 #define BM_RCM_RPFC_RSTFLTSS (0x04U) //!< Bit mask for RCM_RPFC_RSTFLTSS.
bogdanm 82:6473597d706e 523 #define BS_RCM_RPFC_RSTFLTSS (1U) //!< Bit field size in bits for RCM_RPFC_RSTFLTSS.
bogdanm 82:6473597d706e 524
bogdanm 82:6473597d706e 525 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 526 //! @brief Read current value of the RCM_RPFC_RSTFLTSS field.
bogdanm 82:6473597d706e 527 #define BR_RCM_RPFC_RSTFLTSS (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR, BP_RCM_RPFC_RSTFLTSS))
bogdanm 82:6473597d706e 528 #endif
bogdanm 82:6473597d706e 529
bogdanm 82:6473597d706e 530 //! @brief Format value for bitfield RCM_RPFC_RSTFLTSS.
bogdanm 82:6473597d706e 531 #define BF_RCM_RPFC_RSTFLTSS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFC_RSTFLTSS), uint8_t) & BM_RCM_RPFC_RSTFLTSS)
bogdanm 82:6473597d706e 532
bogdanm 82:6473597d706e 533 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 534 //! @brief Set the RSTFLTSS field to a new value.
bogdanm 82:6473597d706e 535 #define BW_RCM_RPFC_RSTFLTSS(v) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR, BP_RCM_RPFC_RSTFLTSS) = (v))
bogdanm 82:6473597d706e 536 #endif
bogdanm 82:6473597d706e 537 //@}
bogdanm 82:6473597d706e 538
bogdanm 82:6473597d706e 539 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 540 // HW_RCM_RPFW - Reset Pin Filter Width register
bogdanm 82:6473597d706e 541 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 542
bogdanm 82:6473597d706e 543 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 544 /*!
bogdanm 82:6473597d706e 545 * @brief HW_RCM_RPFW - Reset Pin Filter Width register (RW)
bogdanm 82:6473597d706e 546 *
bogdanm 82:6473597d706e 547 * Reset value: 0x00U
bogdanm 82:6473597d706e 548 *
bogdanm 82:6473597d706e 549 * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
bogdanm 82:6473597d706e 550 * They are unaffected by other reset types.
bogdanm 82:6473597d706e 551 */
bogdanm 82:6473597d706e 552 typedef union _hw_rcm_rpfw
bogdanm 82:6473597d706e 553 {
bogdanm 82:6473597d706e 554 uint8_t U;
bogdanm 82:6473597d706e 555 struct _hw_rcm_rpfw_bitfields
bogdanm 82:6473597d706e 556 {
bogdanm 82:6473597d706e 557 uint8_t RSTFLTSEL : 5; //!< [4:0] Reset Pin Filter Bus Clock Select
bogdanm 82:6473597d706e 558 uint8_t RESERVED0 : 3; //!< [7:5]
bogdanm 82:6473597d706e 559 } B;
bogdanm 82:6473597d706e 560 } hw_rcm_rpfw_t;
bogdanm 82:6473597d706e 561 #endif
bogdanm 82:6473597d706e 562
bogdanm 82:6473597d706e 563 /*!
bogdanm 82:6473597d706e 564 * @name Constants and macros for entire RCM_RPFW register
bogdanm 82:6473597d706e 565 */
bogdanm 82:6473597d706e 566 //@{
bogdanm 82:6473597d706e 567 #define HW_RCM_RPFW_ADDR (REGS_RCM_BASE + 0x5U)
bogdanm 82:6473597d706e 568
bogdanm 82:6473597d706e 569 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 570 #define HW_RCM_RPFW (*(__IO hw_rcm_rpfw_t *) HW_RCM_RPFW_ADDR)
bogdanm 82:6473597d706e 571 #define HW_RCM_RPFW_RD() (HW_RCM_RPFW.U)
bogdanm 82:6473597d706e 572 #define HW_RCM_RPFW_WR(v) (HW_RCM_RPFW.U = (v))
bogdanm 82:6473597d706e 573 #define HW_RCM_RPFW_SET(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() | (v)))
bogdanm 82:6473597d706e 574 #define HW_RCM_RPFW_CLR(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() & ~(v)))
bogdanm 82:6473597d706e 575 #define HW_RCM_RPFW_TOG(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() ^ (v)))
bogdanm 82:6473597d706e 576 #endif
bogdanm 82:6473597d706e 577 //@}
bogdanm 82:6473597d706e 578
bogdanm 82:6473597d706e 579 /*
bogdanm 82:6473597d706e 580 * Constants & macros for individual RCM_RPFW bitfields
bogdanm 82:6473597d706e 581 */
bogdanm 82:6473597d706e 582
bogdanm 82:6473597d706e 583 /*!
bogdanm 82:6473597d706e 584 * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
bogdanm 82:6473597d706e 585 *
bogdanm 82:6473597d706e 586 * Selects the reset pin bus clock filter width.
bogdanm 82:6473597d706e 587 *
bogdanm 82:6473597d706e 588 * Values:
bogdanm 82:6473597d706e 589 * - 00000 - Bus clock filter count is 1
bogdanm 82:6473597d706e 590 * - 00001 - Bus clock filter count is 2
bogdanm 82:6473597d706e 591 * - 00010 - Bus clock filter count is 3
bogdanm 82:6473597d706e 592 * - 00011 - Bus clock filter count is 4
bogdanm 82:6473597d706e 593 * - 00100 - Bus clock filter count is 5
bogdanm 82:6473597d706e 594 * - 00101 - Bus clock filter count is 6
bogdanm 82:6473597d706e 595 * - 00110 - Bus clock filter count is 7
bogdanm 82:6473597d706e 596 * - 00111 - Bus clock filter count is 8
bogdanm 82:6473597d706e 597 * - 01000 - Bus clock filter count is 9
bogdanm 82:6473597d706e 598 * - 01001 - Bus clock filter count is 10
bogdanm 82:6473597d706e 599 * - 01010 - Bus clock filter count is 11
bogdanm 82:6473597d706e 600 * - 01011 - Bus clock filter count is 12
bogdanm 82:6473597d706e 601 * - 01100 - Bus clock filter count is 13
bogdanm 82:6473597d706e 602 * - 01101 - Bus clock filter count is 14
bogdanm 82:6473597d706e 603 * - 01110 - Bus clock filter count is 15
bogdanm 82:6473597d706e 604 * - 01111 - Bus clock filter count is 16
bogdanm 82:6473597d706e 605 * - 10000 - Bus clock filter count is 17
bogdanm 82:6473597d706e 606 * - 10001 - Bus clock filter count is 18
bogdanm 82:6473597d706e 607 * - 10010 - Bus clock filter count is 19
bogdanm 82:6473597d706e 608 * - 10011 - Bus clock filter count is 20
bogdanm 82:6473597d706e 609 * - 10100 - Bus clock filter count is 21
bogdanm 82:6473597d706e 610 * - 10101 - Bus clock filter count is 22
bogdanm 82:6473597d706e 611 * - 10110 - Bus clock filter count is 23
bogdanm 82:6473597d706e 612 * - 10111 - Bus clock filter count is 24
bogdanm 82:6473597d706e 613 * - 11000 - Bus clock filter count is 25
bogdanm 82:6473597d706e 614 * - 11001 - Bus clock filter count is 26
bogdanm 82:6473597d706e 615 * - 11010 - Bus clock filter count is 27
bogdanm 82:6473597d706e 616 * - 11011 - Bus clock filter count is 28
bogdanm 82:6473597d706e 617 * - 11100 - Bus clock filter count is 29
bogdanm 82:6473597d706e 618 * - 11101 - Bus clock filter count is 30
bogdanm 82:6473597d706e 619 * - 11110 - Bus clock filter count is 31
bogdanm 82:6473597d706e 620 * - 11111 - Bus clock filter count is 32
bogdanm 82:6473597d706e 621 */
bogdanm 82:6473597d706e 622 //@{
bogdanm 82:6473597d706e 623 #define BP_RCM_RPFW_RSTFLTSEL (0U) //!< Bit position for RCM_RPFW_RSTFLTSEL.
bogdanm 82:6473597d706e 624 #define BM_RCM_RPFW_RSTFLTSEL (0x1FU) //!< Bit mask for RCM_RPFW_RSTFLTSEL.
bogdanm 82:6473597d706e 625 #define BS_RCM_RPFW_RSTFLTSEL (5U) //!< Bit field size in bits for RCM_RPFW_RSTFLTSEL.
bogdanm 82:6473597d706e 626
bogdanm 82:6473597d706e 627 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 628 //! @brief Read current value of the RCM_RPFW_RSTFLTSEL field.
bogdanm 82:6473597d706e 629 #define BR_RCM_RPFW_RSTFLTSEL (HW_RCM_RPFW.B.RSTFLTSEL)
bogdanm 82:6473597d706e 630 #endif
bogdanm 82:6473597d706e 631
bogdanm 82:6473597d706e 632 //! @brief Format value for bitfield RCM_RPFW_RSTFLTSEL.
bogdanm 82:6473597d706e 633 #define BF_RCM_RPFW_RSTFLTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFW_RSTFLTSEL), uint8_t) & BM_RCM_RPFW_RSTFLTSEL)
bogdanm 82:6473597d706e 634
bogdanm 82:6473597d706e 635 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 636 //! @brief Set the RSTFLTSEL field to a new value.
bogdanm 82:6473597d706e 637 #define BW_RCM_RPFW_RSTFLTSEL(v) (HW_RCM_RPFW_WR((HW_RCM_RPFW_RD() & ~BM_RCM_RPFW_RSTFLTSEL) | BF_RCM_RPFW_RSTFLTSEL(v)))
bogdanm 82:6473597d706e 638 #endif
bogdanm 82:6473597d706e 639 //@}
bogdanm 82:6473597d706e 640
bogdanm 82:6473597d706e 641 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 642 // HW_RCM_MR - Mode Register
bogdanm 82:6473597d706e 643 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 644
bogdanm 82:6473597d706e 645 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 646 /*!
bogdanm 82:6473597d706e 647 * @brief HW_RCM_MR - Mode Register (RO)
bogdanm 82:6473597d706e 648 *
bogdanm 82:6473597d706e 649 * Reset value: 0x00U
bogdanm 82:6473597d706e 650 *
bogdanm 82:6473597d706e 651 * This register includes read-only status flags to indicate the state of the
bogdanm 82:6473597d706e 652 * mode pins during the last Chip Reset.
bogdanm 82:6473597d706e 653 */
bogdanm 82:6473597d706e 654 typedef union _hw_rcm_mr
bogdanm 82:6473597d706e 655 {
bogdanm 82:6473597d706e 656 uint8_t U;
bogdanm 82:6473597d706e 657 struct _hw_rcm_mr_bitfields
bogdanm 82:6473597d706e 658 {
bogdanm 82:6473597d706e 659 uint8_t RESERVED0 : 1; //!< [0]
bogdanm 82:6473597d706e 660 uint8_t EZP_MS : 1; //!< [1] EZP_MS_B pin state
bogdanm 82:6473597d706e 661 uint8_t RESERVED1 : 6; //!< [7:2]
bogdanm 82:6473597d706e 662 } B;
bogdanm 82:6473597d706e 663 } hw_rcm_mr_t;
bogdanm 82:6473597d706e 664 #endif
bogdanm 82:6473597d706e 665
bogdanm 82:6473597d706e 666 /*!
bogdanm 82:6473597d706e 667 * @name Constants and macros for entire RCM_MR register
bogdanm 82:6473597d706e 668 */
bogdanm 82:6473597d706e 669 //@{
bogdanm 82:6473597d706e 670 #define HW_RCM_MR_ADDR (REGS_RCM_BASE + 0x7U)
bogdanm 82:6473597d706e 671
bogdanm 82:6473597d706e 672 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 673 #define HW_RCM_MR (*(__I hw_rcm_mr_t *) HW_RCM_MR_ADDR)
bogdanm 82:6473597d706e 674 #define HW_RCM_MR_RD() (HW_RCM_MR.U)
bogdanm 82:6473597d706e 675 #endif
bogdanm 82:6473597d706e 676 //@}
bogdanm 82:6473597d706e 677
bogdanm 82:6473597d706e 678 /*
bogdanm 82:6473597d706e 679 * Constants & macros for individual RCM_MR bitfields
bogdanm 82:6473597d706e 680 */
bogdanm 82:6473597d706e 681
bogdanm 82:6473597d706e 682 /*!
bogdanm 82:6473597d706e 683 * @name Register RCM_MR, field EZP_MS[1] (RO)
bogdanm 82:6473597d706e 684 *
bogdanm 82:6473597d706e 685 * Reflects the state of the EZP_MS pin during the last Chip Reset
bogdanm 82:6473597d706e 686 *
bogdanm 82:6473597d706e 687 * Values:
bogdanm 82:6473597d706e 688 * - 0 - Pin deasserted (logic 1)
bogdanm 82:6473597d706e 689 * - 1 - Pin asserted (logic 0)
bogdanm 82:6473597d706e 690 */
bogdanm 82:6473597d706e 691 //@{
bogdanm 82:6473597d706e 692 #define BP_RCM_MR_EZP_MS (1U) //!< Bit position for RCM_MR_EZP_MS.
bogdanm 82:6473597d706e 693 #define BM_RCM_MR_EZP_MS (0x02U) //!< Bit mask for RCM_MR_EZP_MS.
bogdanm 82:6473597d706e 694 #define BS_RCM_MR_EZP_MS (1U) //!< Bit field size in bits for RCM_MR_EZP_MS.
bogdanm 82:6473597d706e 695
bogdanm 82:6473597d706e 696 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 697 //! @brief Read current value of the RCM_MR_EZP_MS field.
bogdanm 82:6473597d706e 698 #define BR_RCM_MR_EZP_MS (BITBAND_ACCESS8(HW_RCM_MR_ADDR, BP_RCM_MR_EZP_MS))
bogdanm 82:6473597d706e 699 #endif
bogdanm 82:6473597d706e 700 //@}
bogdanm 82:6473597d706e 701
bogdanm 82:6473597d706e 702 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 703 // hw_rcm_t - module struct
bogdanm 82:6473597d706e 704 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 705 /*!
bogdanm 82:6473597d706e 706 * @brief All RCM module registers.
bogdanm 82:6473597d706e 707 */
bogdanm 82:6473597d706e 708 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 709 #pragma pack(1)
bogdanm 82:6473597d706e 710 typedef struct _hw_rcm
bogdanm 82:6473597d706e 711 {
bogdanm 82:6473597d706e 712 __I hw_rcm_srs0_t SRS0; //!< [0x0] System Reset Status Register 0
bogdanm 82:6473597d706e 713 __I hw_rcm_srs1_t SRS1; //!< [0x1] System Reset Status Register 1
bogdanm 82:6473597d706e 714 uint8_t _reserved0[2];
bogdanm 82:6473597d706e 715 __IO hw_rcm_rpfc_t RPFC; //!< [0x4] Reset Pin Filter Control register
bogdanm 82:6473597d706e 716 __IO hw_rcm_rpfw_t RPFW; //!< [0x5] Reset Pin Filter Width register
bogdanm 82:6473597d706e 717 uint8_t _reserved1[1];
bogdanm 82:6473597d706e 718 __I hw_rcm_mr_t MR; //!< [0x7] Mode Register
bogdanm 82:6473597d706e 719 } hw_rcm_t;
bogdanm 82:6473597d706e 720 #pragma pack()
bogdanm 82:6473597d706e 721
bogdanm 82:6473597d706e 722 //! @brief Macro to access all RCM registers.
bogdanm 82:6473597d706e 723 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 724 //! use the '&' operator, like <code>&HW_RCM</code>.
bogdanm 82:6473597d706e 725 #define HW_RCM (*(hw_rcm_t *) REGS_RCM_BASE)
bogdanm 82:6473597d706e 726 #endif
bogdanm 82:6473597d706e 727
bogdanm 82:6473597d706e 728 #endif // __HW_RCM_REGISTERS_H__
bogdanm 82:6473597d706e 729 // v22/130726/0.9
bogdanm 82:6473597d706e 730 // EOF