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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_i2s.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:: bogdanm
Date:: Mon Apr 07 18:28:36 2014 +0100
Revision:: 82:6473597d706e

Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_I2S_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_I2S_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 I2S
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Inter-IC Sound / Synchronous Audio Interface
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_I2S_TCSR - SAI Transmit Control Register
bogdanm	82:6473597d706e	33	* - HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
bogdanm	82:6473597d706e	34	* - HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
bogdanm	82:6473597d706e	35	* - HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
bogdanm	82:6473597d706e	36	* - HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
bogdanm	82:6473597d706e	37	* - HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
bogdanm	82:6473597d706e	38	* - HW_I2S_TDRn - SAI Transmit Data Register
bogdanm	82:6473597d706e	39	* - HW_I2S_TFRn - SAI Transmit FIFO Register
bogdanm	82:6473597d706e	40	* - HW_I2S_TMR - SAI Transmit Mask Register
bogdanm	82:6473597d706e	41	* - HW_I2S_RCSR - SAI Receive Control Register
bogdanm	82:6473597d706e	42	* - HW_I2S_RCR1 - SAI Receive Configuration 1 Register
bogdanm	82:6473597d706e	43	* - HW_I2S_RCR2 - SAI Receive Configuration 2 Register
bogdanm	82:6473597d706e	44	* - HW_I2S_RCR3 - SAI Receive Configuration 3 Register
bogdanm	82:6473597d706e	45	* - HW_I2S_RCR4 - SAI Receive Configuration 4 Register
bogdanm	82:6473597d706e	46	* - HW_I2S_RCR5 - SAI Receive Configuration 5 Register
bogdanm	82:6473597d706e	47	* - HW_I2S_RDRn - SAI Receive Data Register
bogdanm	82:6473597d706e	48	* - HW_I2S_RFRn - SAI Receive FIFO Register
bogdanm	82:6473597d706e	49	* - HW_I2S_RMR - SAI Receive Mask Register
bogdanm	82:6473597d706e	50	* - HW_I2S_MCR - SAI MCLK Control Register
bogdanm	82:6473597d706e	51	* - HW_I2S_MDR - SAI MCLK Divide Register
bogdanm	82:6473597d706e	52	*
bogdanm	82:6473597d706e	53	* - hw_i2s_t - Struct containing all module registers.
bogdanm	82:6473597d706e	54	*/
bogdanm	82:6473597d706e	55
bogdanm	82:6473597d706e	56	//! @name Module base addresses
bogdanm	82:6473597d706e	57	//@{
bogdanm	82:6473597d706e	58	#ifndef REGS_I2S_BASE
bogdanm	82:6473597d706e	59	#define HW_I2S_INSTANCE_COUNT (1U) //!< Number of instances of the I2S module.
bogdanm	82:6473597d706e	60	#define HW_I2S0 (0U) //!< Instance number for I2S0.
bogdanm	82:6473597d706e	61	#define REGS_I2S0_BASE (0x4002F000U) //!< Base address for I2S0.
bogdanm	82:6473597d706e	62
bogdanm	82:6473597d706e	63	//! @brief Table of base addresses for I2S instances.
bogdanm	82:6473597d706e	64	static const uint32_t __g_regs_I2S_base_addresses[] = {
bogdanm	82:6473597d706e	65	REGS_I2S0_BASE,
bogdanm	82:6473597d706e	66	};
bogdanm	82:6473597d706e	67
bogdanm	82:6473597d706e	68	//! @brief Get the base address of I2S by instance number.
bogdanm	82:6473597d706e	69	//! @param x I2S instance number, from 0 through 0.
bogdanm	82:6473597d706e	70	#define REGS_I2S_BASE(x) (__g_regs_I2S_base_addresses[(x)])
bogdanm	82:6473597d706e	71
bogdanm	82:6473597d706e	72	//! @brief Get the instance number given a base address.
bogdanm	82:6473597d706e	73	//! @param b Base address for an instance of I2S.
bogdanm	82:6473597d706e	74	#define REGS_I2S_INSTANCE(b) ((b) == REGS_I2S0_BASE ? HW_I2S0 : 0)
bogdanm	82:6473597d706e	75	#endif
bogdanm	82:6473597d706e	76	//@}
bogdanm	82:6473597d706e	77
bogdanm	82:6473597d706e	78	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	79	// HW_I2S_TCSR - SAI Transmit Control Register
bogdanm	82:6473597d706e	80	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	81
bogdanm	82:6473597d706e	82	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	83	/*!
bogdanm	82:6473597d706e	84	* @brief HW_I2S_TCSR - SAI Transmit Control Register (RW)
bogdanm	82:6473597d706e	85	*
bogdanm	82:6473597d706e	86	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	87	*/
bogdanm	82:6473597d706e	88	typedef union _hw_i2s_tcsr
bogdanm	82:6473597d706e	89	{
bogdanm	82:6473597d706e	90	uint32_t U;
bogdanm	82:6473597d706e	91	struct _hw_i2s_tcsr_bitfields
bogdanm	82:6473597d706e	92	{
bogdanm	82:6473597d706e	93	uint32_t FRDE : 1; //!< [0] FIFO Request DMA Enable
bogdanm	82:6473597d706e	94	uint32_t FWDE : 1; //!< [1] FIFO Warning DMA Enable
bogdanm	82:6473597d706e	95	uint32_t RESERVED0 : 6; //!< [7:2]
bogdanm	82:6473597d706e	96	uint32_t FRIE : 1; //!< [8] FIFO Request Interrupt Enable
bogdanm	82:6473597d706e	97	uint32_t FWIE : 1; //!< [9] FIFO Warning Interrupt Enable
bogdanm	82:6473597d706e	98	uint32_t FEIE : 1; //!< [10] FIFO Error Interrupt Enable
bogdanm	82:6473597d706e	99	uint32_t SEIE : 1; //!< [11] Sync Error Interrupt Enable
bogdanm	82:6473597d706e	100	uint32_t WSIE : 1; //!< [12] Word Start Interrupt Enable
bogdanm	82:6473597d706e	101	uint32_t RESERVED1 : 3; //!< [15:13]
bogdanm	82:6473597d706e	102	uint32_t FRF : 1; //!< [16] FIFO Request Flag
bogdanm	82:6473597d706e	103	uint32_t FWF : 1; //!< [17] FIFO Warning Flag
bogdanm	82:6473597d706e	104	uint32_t FEF : 1; //!< [18] FIFO Error Flag
bogdanm	82:6473597d706e	105	uint32_t SEF : 1; //!< [19] Sync Error Flag
bogdanm	82:6473597d706e	106	uint32_t WSF : 1; //!< [20] Word Start Flag
bogdanm	82:6473597d706e	107	uint32_t RESERVED2 : 3; //!< [23:21]
bogdanm	82:6473597d706e	108	uint32_t SR : 1; //!< [24] Software Reset
bogdanm	82:6473597d706e	109	uint32_t FR : 1; //!< [25] FIFO Reset
bogdanm	82:6473597d706e	110	uint32_t RESERVED3 : 2; //!< [27:26]
bogdanm	82:6473597d706e	111	uint32_t BCE : 1; //!< [28] Bit Clock Enable
bogdanm	82:6473597d706e	112	uint32_t DBGE : 1; //!< [29] Debug Enable
bogdanm	82:6473597d706e	113	uint32_t STOPE : 1; //!< [30] Stop Enable
bogdanm	82:6473597d706e	114	uint32_t TE : 1; //!< [31] Transmitter Enable
bogdanm	82:6473597d706e	115	} B;
bogdanm	82:6473597d706e	116	} hw_i2s_tcsr_t;
bogdanm	82:6473597d706e	117	#endif
bogdanm	82:6473597d706e	118
bogdanm	82:6473597d706e	119	/*!
bogdanm	82:6473597d706e	120	* @name Constants and macros for entire I2S_TCSR register
bogdanm	82:6473597d706e	121	*/
bogdanm	82:6473597d706e	122	//@{
bogdanm	82:6473597d706e	123	#define HW_I2S_TCSR_ADDR(x) (REGS_I2S_BASE(x) + 0x0U)
bogdanm	82:6473597d706e	124
bogdanm	82:6473597d706e	125	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	126	#define HW_I2S_TCSR(x) ((__IO hw_i2s_tcsr_t ) HW_I2S_TCSR_ADDR(x))
bogdanm	82:6473597d706e	127	#define HW_I2S_TCSR_RD(x) (HW_I2S_TCSR(x).U)
bogdanm	82:6473597d706e	128	#define HW_I2S_TCSR_WR(x, v) (HW_I2S_TCSR(x).U = (v))
bogdanm	82:6473597d706e	129	#define HW_I2S_TCSR_SET(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) \| (v)))
bogdanm	82:6473597d706e	130	#define HW_I2S_TCSR_CLR(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	131	#define HW_I2S_TCSR_TOG(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	132	#endif
bogdanm	82:6473597d706e	133	//@}
bogdanm	82:6473597d706e	134
bogdanm	82:6473597d706e	135	/*
bogdanm	82:6473597d706e	136	* Constants & macros for individual I2S_TCSR bitfields
bogdanm	82:6473597d706e	137	*/
bogdanm	82:6473597d706e	138
bogdanm	82:6473597d706e	139	/*!
bogdanm	82:6473597d706e	140	* @name Register I2S_TCSR, field FRDE[0] (RW)
bogdanm	82:6473597d706e	141	*
bogdanm	82:6473597d706e	142	* Enables/disables DMA requests.
bogdanm	82:6473597d706e	143	*
bogdanm	82:6473597d706e	144	* Values:
bogdanm	82:6473597d706e	145	* - 0 - Disables the DMA request.
bogdanm	82:6473597d706e	146	* - 1 - Enables the DMA request.
bogdanm	82:6473597d706e	147	*/
bogdanm	82:6473597d706e	148	//@{
bogdanm	82:6473597d706e	149	#define BP_I2S_TCSR_FRDE (0U) //!< Bit position for I2S_TCSR_FRDE.
bogdanm	82:6473597d706e	150	#define BM_I2S_TCSR_FRDE (0x00000001U) //!< Bit mask for I2S_TCSR_FRDE.
bogdanm	82:6473597d706e	151	#define BS_I2S_TCSR_FRDE (1U) //!< Bit field size in bits for I2S_TCSR_FRDE.
bogdanm	82:6473597d706e	152
bogdanm	82:6473597d706e	153	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	154	//! @brief Read current value of the I2S_TCSR_FRDE field.
bogdanm	82:6473597d706e	155	#define BR_I2S_TCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE))
bogdanm	82:6473597d706e	156	#endif
bogdanm	82:6473597d706e	157
bogdanm	82:6473597d706e	158	//! @brief Format value for bitfield I2S_TCSR_FRDE.
bogdanm	82:6473597d706e	159	#define BF_I2S_TCSR_FRDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FRDE), uint32_t) & BM_I2S_TCSR_FRDE)
bogdanm	82:6473597d706e	160
bogdanm	82:6473597d706e	161	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	162	//! @brief Set the FRDE field to a new value.
bogdanm	82:6473597d706e	163	#define BW_I2S_TCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE) = (v))
bogdanm	82:6473597d706e	164	#endif
bogdanm	82:6473597d706e	165	//@}
bogdanm	82:6473597d706e	166
bogdanm	82:6473597d706e	167	/*!
bogdanm	82:6473597d706e	168	* @name Register I2S_TCSR, field FWDE[1] (RW)
bogdanm	82:6473597d706e	169	*
bogdanm	82:6473597d706e	170	* Enables/disables DMA requests.
bogdanm	82:6473597d706e	171	*
bogdanm	82:6473597d706e	172	* Values:
bogdanm	82:6473597d706e	173	* - 0 - Disables the DMA request.
bogdanm	82:6473597d706e	174	* - 1 - Enables the DMA request.
bogdanm	82:6473597d706e	175	*/
bogdanm	82:6473597d706e	176	//@{
bogdanm	82:6473597d706e	177	#define BP_I2S_TCSR_FWDE (1U) //!< Bit position for I2S_TCSR_FWDE.
bogdanm	82:6473597d706e	178	#define BM_I2S_TCSR_FWDE (0x00000002U) //!< Bit mask for I2S_TCSR_FWDE.
bogdanm	82:6473597d706e	179	#define BS_I2S_TCSR_FWDE (1U) //!< Bit field size in bits for I2S_TCSR_FWDE.
bogdanm	82:6473597d706e	180
bogdanm	82:6473597d706e	181	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	182	//! @brief Read current value of the I2S_TCSR_FWDE field.
bogdanm	82:6473597d706e	183	#define BR_I2S_TCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE))
bogdanm	82:6473597d706e	184	#endif
bogdanm	82:6473597d706e	185
bogdanm	82:6473597d706e	186	//! @brief Format value for bitfield I2S_TCSR_FWDE.
bogdanm	82:6473597d706e	187	#define BF_I2S_TCSR_FWDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FWDE), uint32_t) & BM_I2S_TCSR_FWDE)
bogdanm	82:6473597d706e	188
bogdanm	82:6473597d706e	189	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	190	//! @brief Set the FWDE field to a new value.
bogdanm	82:6473597d706e	191	#define BW_I2S_TCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE) = (v))
bogdanm	82:6473597d706e	192	#endif
bogdanm	82:6473597d706e	193	//@}
bogdanm	82:6473597d706e	194
bogdanm	82:6473597d706e	195	/*!
bogdanm	82:6473597d706e	196	* @name Register I2S_TCSR, field FRIE[8] (RW)
bogdanm	82:6473597d706e	197	*
bogdanm	82:6473597d706e	198	* Enables/disables FIFO request interrupts.
bogdanm	82:6473597d706e	199	*
bogdanm	82:6473597d706e	200	* Values:
bogdanm	82:6473597d706e	201	* - 0 - Disables the interrupt.
bogdanm	82:6473597d706e	202	* - 1 - Enables the interrupt.
bogdanm	82:6473597d706e	203	*/
bogdanm	82:6473597d706e	204	//@{
bogdanm	82:6473597d706e	205	#define BP_I2S_TCSR_FRIE (8U) //!< Bit position for I2S_TCSR_FRIE.
bogdanm	82:6473597d706e	206	#define BM_I2S_TCSR_FRIE (0x00000100U) //!< Bit mask for I2S_TCSR_FRIE.
bogdanm	82:6473597d706e	207	#define BS_I2S_TCSR_FRIE (1U) //!< Bit field size in bits for I2S_TCSR_FRIE.
bogdanm	82:6473597d706e	208
bogdanm	82:6473597d706e	209	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	210	//! @brief Read current value of the I2S_TCSR_FRIE field.
bogdanm	82:6473597d706e	211	#define BR_I2S_TCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE))
bogdanm	82:6473597d706e	212	#endif
bogdanm	82:6473597d706e	213
bogdanm	82:6473597d706e	214	//! @brief Format value for bitfield I2S_TCSR_FRIE.
bogdanm	82:6473597d706e	215	#define BF_I2S_TCSR_FRIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FRIE), uint32_t) & BM_I2S_TCSR_FRIE)
bogdanm	82:6473597d706e	216
bogdanm	82:6473597d706e	217	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	218	//! @brief Set the FRIE field to a new value.
bogdanm	82:6473597d706e	219	#define BW_I2S_TCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE) = (v))
bogdanm	82:6473597d706e	220	#endif
bogdanm	82:6473597d706e	221	//@}
bogdanm	82:6473597d706e	222
bogdanm	82:6473597d706e	223	/*!
bogdanm	82:6473597d706e	224	* @name Register I2S_TCSR, field FWIE[9] (RW)
bogdanm	82:6473597d706e	225	*
bogdanm	82:6473597d706e	226	* Enables/disables FIFO warning interrupts.
bogdanm	82:6473597d706e	227	*
bogdanm	82:6473597d706e	228	* Values:
bogdanm	82:6473597d706e	229	* - 0 - Disables the interrupt.
bogdanm	82:6473597d706e	230	* - 1 - Enables the interrupt.
bogdanm	82:6473597d706e	231	*/
bogdanm	82:6473597d706e	232	//@{
bogdanm	82:6473597d706e	233	#define BP_I2S_TCSR_FWIE (9U) //!< Bit position for I2S_TCSR_FWIE.
bogdanm	82:6473597d706e	234	#define BM_I2S_TCSR_FWIE (0x00000200U) //!< Bit mask for I2S_TCSR_FWIE.
bogdanm	82:6473597d706e	235	#define BS_I2S_TCSR_FWIE (1U) //!< Bit field size in bits for I2S_TCSR_FWIE.
bogdanm	82:6473597d706e	236
bogdanm	82:6473597d706e	237	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	238	//! @brief Read current value of the I2S_TCSR_FWIE field.
bogdanm	82:6473597d706e	239	#define BR_I2S_TCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE))
bogdanm	82:6473597d706e	240	#endif
bogdanm	82:6473597d706e	241
bogdanm	82:6473597d706e	242	//! @brief Format value for bitfield I2S_TCSR_FWIE.
bogdanm	82:6473597d706e	243	#define BF_I2S_TCSR_FWIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FWIE), uint32_t) & BM_I2S_TCSR_FWIE)
bogdanm	82:6473597d706e	244
bogdanm	82:6473597d706e	245	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	246	//! @brief Set the FWIE field to a new value.
bogdanm	82:6473597d706e	247	#define BW_I2S_TCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE) = (v))
bogdanm	82:6473597d706e	248	#endif
bogdanm	82:6473597d706e	249	//@}
bogdanm	82:6473597d706e	250
bogdanm	82:6473597d706e	251	/*!
bogdanm	82:6473597d706e	252	* @name Register I2S_TCSR, field FEIE[10] (RW)
bogdanm	82:6473597d706e	253	*
bogdanm	82:6473597d706e	254	* Enables/disables FIFO error interrupts.
bogdanm	82:6473597d706e	255	*
bogdanm	82:6473597d706e	256	* Values:
bogdanm	82:6473597d706e	257	* - 0 - Disables the interrupt.
bogdanm	82:6473597d706e	258	* - 1 - Enables the interrupt.
bogdanm	82:6473597d706e	259	*/
bogdanm	82:6473597d706e	260	//@{
bogdanm	82:6473597d706e	261	#define BP_I2S_TCSR_FEIE (10U) //!< Bit position for I2S_TCSR_FEIE.
bogdanm	82:6473597d706e	262	#define BM_I2S_TCSR_FEIE (0x00000400U) //!< Bit mask for I2S_TCSR_FEIE.
bogdanm	82:6473597d706e	263	#define BS_I2S_TCSR_FEIE (1U) //!< Bit field size in bits for I2S_TCSR_FEIE.
bogdanm	82:6473597d706e	264
bogdanm	82:6473597d706e	265	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	266	//! @brief Read current value of the I2S_TCSR_FEIE field.
bogdanm	82:6473597d706e	267	#define BR_I2S_TCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE))
bogdanm	82:6473597d706e	268	#endif
bogdanm	82:6473597d706e	269
bogdanm	82:6473597d706e	270	//! @brief Format value for bitfield I2S_TCSR_FEIE.
bogdanm	82:6473597d706e	271	#define BF_I2S_TCSR_FEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FEIE), uint32_t) & BM_I2S_TCSR_FEIE)
bogdanm	82:6473597d706e	272
bogdanm	82:6473597d706e	273	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	274	//! @brief Set the FEIE field to a new value.
bogdanm	82:6473597d706e	275	#define BW_I2S_TCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE) = (v))
bogdanm	82:6473597d706e	276	#endif
bogdanm	82:6473597d706e	277	//@}
bogdanm	82:6473597d706e	278
bogdanm	82:6473597d706e	279	/*!
bogdanm	82:6473597d706e	280	* @name Register I2S_TCSR, field SEIE[11] (RW)
bogdanm	82:6473597d706e	281	*
bogdanm	82:6473597d706e	282	* Enables/disables sync error interrupts.
bogdanm	82:6473597d706e	283	*
bogdanm	82:6473597d706e	284	* Values:
bogdanm	82:6473597d706e	285	* - 0 - Disables interrupt.
bogdanm	82:6473597d706e	286	* - 1 - Enables interrupt.
bogdanm	82:6473597d706e	287	*/
bogdanm	82:6473597d706e	288	//@{
bogdanm	82:6473597d706e	289	#define BP_I2S_TCSR_SEIE (11U) //!< Bit position for I2S_TCSR_SEIE.
bogdanm	82:6473597d706e	290	#define BM_I2S_TCSR_SEIE (0x00000800U) //!< Bit mask for I2S_TCSR_SEIE.
bogdanm	82:6473597d706e	291	#define BS_I2S_TCSR_SEIE (1U) //!< Bit field size in bits for I2S_TCSR_SEIE.
bogdanm	82:6473597d706e	292
bogdanm	82:6473597d706e	293	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	294	//! @brief Read current value of the I2S_TCSR_SEIE field.
bogdanm	82:6473597d706e	295	#define BR_I2S_TCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE))
bogdanm	82:6473597d706e	296	#endif
bogdanm	82:6473597d706e	297
bogdanm	82:6473597d706e	298	//! @brief Format value for bitfield I2S_TCSR_SEIE.
bogdanm	82:6473597d706e	299	#define BF_I2S_TCSR_SEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SEIE), uint32_t) & BM_I2S_TCSR_SEIE)
bogdanm	82:6473597d706e	300
bogdanm	82:6473597d706e	301	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	302	//! @brief Set the SEIE field to a new value.
bogdanm	82:6473597d706e	303	#define BW_I2S_TCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE) = (v))
bogdanm	82:6473597d706e	304	#endif
bogdanm	82:6473597d706e	305	//@}
bogdanm	82:6473597d706e	306
bogdanm	82:6473597d706e	307	/*!
bogdanm	82:6473597d706e	308	* @name Register I2S_TCSR, field WSIE[12] (RW)
bogdanm	82:6473597d706e	309	*
bogdanm	82:6473597d706e	310	* Enables/disables word start interrupts.
bogdanm	82:6473597d706e	311	*
bogdanm	82:6473597d706e	312	* Values:
bogdanm	82:6473597d706e	313	* - 0 - Disables interrupt.
bogdanm	82:6473597d706e	314	* - 1 - Enables interrupt.
bogdanm	82:6473597d706e	315	*/
bogdanm	82:6473597d706e	316	//@{
bogdanm	82:6473597d706e	317	#define BP_I2S_TCSR_WSIE (12U) //!< Bit position for I2S_TCSR_WSIE.
bogdanm	82:6473597d706e	318	#define BM_I2S_TCSR_WSIE (0x00001000U) //!< Bit mask for I2S_TCSR_WSIE.
bogdanm	82:6473597d706e	319	#define BS_I2S_TCSR_WSIE (1U) //!< Bit field size in bits for I2S_TCSR_WSIE.
bogdanm	82:6473597d706e	320
bogdanm	82:6473597d706e	321	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	322	//! @brief Read current value of the I2S_TCSR_WSIE field.
bogdanm	82:6473597d706e	323	#define BR_I2S_TCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE))
bogdanm	82:6473597d706e	324	#endif
bogdanm	82:6473597d706e	325
bogdanm	82:6473597d706e	326	//! @brief Format value for bitfield I2S_TCSR_WSIE.
bogdanm	82:6473597d706e	327	#define BF_I2S_TCSR_WSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_WSIE), uint32_t) & BM_I2S_TCSR_WSIE)
bogdanm	82:6473597d706e	328
bogdanm	82:6473597d706e	329	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	330	//! @brief Set the WSIE field to a new value.
bogdanm	82:6473597d706e	331	#define BW_I2S_TCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE) = (v))
bogdanm	82:6473597d706e	332	#endif
bogdanm	82:6473597d706e	333	//@}
bogdanm	82:6473597d706e	334
bogdanm	82:6473597d706e	335	/*!
bogdanm	82:6473597d706e	336	* @name Register I2S_TCSR, field FRF[16] (RO)
bogdanm	82:6473597d706e	337	*
bogdanm	82:6473597d706e	338	* Indicates that the number of words in an enabled transmit channel FIFO is
bogdanm	82:6473597d706e	339	* less than or equal to the transmit FIFO watermark.
bogdanm	82:6473597d706e	340	*
bogdanm	82:6473597d706e	341	* Values:
bogdanm	82:6473597d706e	342	* - 0 - Transmit FIFO watermark has not been reached.
bogdanm	82:6473597d706e	343	* - 1 - Transmit FIFO watermark has been reached.
bogdanm	82:6473597d706e	344	*/
bogdanm	82:6473597d706e	345	//@{
bogdanm	82:6473597d706e	346	#define BP_I2S_TCSR_FRF (16U) //!< Bit position for I2S_TCSR_FRF.
bogdanm	82:6473597d706e	347	#define BM_I2S_TCSR_FRF (0x00010000U) //!< Bit mask for I2S_TCSR_FRF.
bogdanm	82:6473597d706e	348	#define BS_I2S_TCSR_FRF (1U) //!< Bit field size in bits for I2S_TCSR_FRF.
bogdanm	82:6473597d706e	349
bogdanm	82:6473597d706e	350	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	351	//! @brief Read current value of the I2S_TCSR_FRF field.
bogdanm	82:6473597d706e	352	#define BR_I2S_TCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRF))
bogdanm	82:6473597d706e	353	#endif
bogdanm	82:6473597d706e	354	//@}
bogdanm	82:6473597d706e	355
bogdanm	82:6473597d706e	356	/*!
bogdanm	82:6473597d706e	357	* @name Register I2S_TCSR, field FWF[17] (RO)
bogdanm	82:6473597d706e	358	*
bogdanm	82:6473597d706e	359	* Indicates that an enabled transmit FIFO is empty.
bogdanm	82:6473597d706e	360	*
bogdanm	82:6473597d706e	361	* Values:
bogdanm	82:6473597d706e	362	* - 0 - No enabled transmit FIFO is empty.
bogdanm	82:6473597d706e	363	* - 1 - Enabled transmit FIFO is empty.
bogdanm	82:6473597d706e	364	*/
bogdanm	82:6473597d706e	365	//@{
bogdanm	82:6473597d706e	366	#define BP_I2S_TCSR_FWF (17U) //!< Bit position for I2S_TCSR_FWF.
bogdanm	82:6473597d706e	367	#define BM_I2S_TCSR_FWF (0x00020000U) //!< Bit mask for I2S_TCSR_FWF.
bogdanm	82:6473597d706e	368	#define BS_I2S_TCSR_FWF (1U) //!< Bit field size in bits for I2S_TCSR_FWF.
bogdanm	82:6473597d706e	369
bogdanm	82:6473597d706e	370	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	371	//! @brief Read current value of the I2S_TCSR_FWF field.
bogdanm	82:6473597d706e	372	#define BR_I2S_TCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWF))
bogdanm	82:6473597d706e	373	#endif
bogdanm	82:6473597d706e	374	//@}
bogdanm	82:6473597d706e	375
bogdanm	82:6473597d706e	376	/*!
bogdanm	82:6473597d706e	377	* @name Register I2S_TCSR, field FEF[18] (W1C)
bogdanm	82:6473597d706e	378	*
bogdanm	82:6473597d706e	379	* Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
bogdanm	82:6473597d706e	380	* field to clear this flag.
bogdanm	82:6473597d706e	381	*
bogdanm	82:6473597d706e	382	* Values:
bogdanm	82:6473597d706e	383	* - 0 - Transmit underrun not detected.
bogdanm	82:6473597d706e	384	* - 1 - Transmit underrun detected.
bogdanm	82:6473597d706e	385	*/
bogdanm	82:6473597d706e	386	//@{
bogdanm	82:6473597d706e	387	#define BP_I2S_TCSR_FEF (18U) //!< Bit position for I2S_TCSR_FEF.
bogdanm	82:6473597d706e	388	#define BM_I2S_TCSR_FEF (0x00040000U) //!< Bit mask for I2S_TCSR_FEF.
bogdanm	82:6473597d706e	389	#define BS_I2S_TCSR_FEF (1U) //!< Bit field size in bits for I2S_TCSR_FEF.
bogdanm	82:6473597d706e	390
bogdanm	82:6473597d706e	391	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	392	//! @brief Read current value of the I2S_TCSR_FEF field.
bogdanm	82:6473597d706e	393	#define BR_I2S_TCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF))
bogdanm	82:6473597d706e	394	#endif
bogdanm	82:6473597d706e	395
bogdanm	82:6473597d706e	396	//! @brief Format value for bitfield I2S_TCSR_FEF.
bogdanm	82:6473597d706e	397	#define BF_I2S_TCSR_FEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FEF), uint32_t) & BM_I2S_TCSR_FEF)
bogdanm	82:6473597d706e	398
bogdanm	82:6473597d706e	399	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	400	//! @brief Set the FEF field to a new value.
bogdanm	82:6473597d706e	401	#define BW_I2S_TCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF) = (v))
bogdanm	82:6473597d706e	402	#endif
bogdanm	82:6473597d706e	403	//@}
bogdanm	82:6473597d706e	404
bogdanm	82:6473597d706e	405	/*!
bogdanm	82:6473597d706e	406	* @name Register I2S_TCSR, field SEF[19] (W1C)
bogdanm	82:6473597d706e	407	*
bogdanm	82:6473597d706e	408	* Indicates that an error in the externally-generated frame sync has been
bogdanm	82:6473597d706e	409	* detected. Write a logic 1 to this field to clear this flag.
bogdanm	82:6473597d706e	410	*
bogdanm	82:6473597d706e	411	* Values:
bogdanm	82:6473597d706e	412	* - 0 - Sync error not detected.
bogdanm	82:6473597d706e	413	* - 1 - Frame sync error detected.
bogdanm	82:6473597d706e	414	*/
bogdanm	82:6473597d706e	415	//@{
bogdanm	82:6473597d706e	416	#define BP_I2S_TCSR_SEF (19U) //!< Bit position for I2S_TCSR_SEF.
bogdanm	82:6473597d706e	417	#define BM_I2S_TCSR_SEF (0x00080000U) //!< Bit mask for I2S_TCSR_SEF.
bogdanm	82:6473597d706e	418	#define BS_I2S_TCSR_SEF (1U) //!< Bit field size in bits for I2S_TCSR_SEF.
bogdanm	82:6473597d706e	419
bogdanm	82:6473597d706e	420	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	421	//! @brief Read current value of the I2S_TCSR_SEF field.
bogdanm	82:6473597d706e	422	#define BR_I2S_TCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF))
bogdanm	82:6473597d706e	423	#endif
bogdanm	82:6473597d706e	424
bogdanm	82:6473597d706e	425	//! @brief Format value for bitfield I2S_TCSR_SEF.
bogdanm	82:6473597d706e	426	#define BF_I2S_TCSR_SEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SEF), uint32_t) & BM_I2S_TCSR_SEF)
bogdanm	82:6473597d706e	427
bogdanm	82:6473597d706e	428	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	429	//! @brief Set the SEF field to a new value.
bogdanm	82:6473597d706e	430	#define BW_I2S_TCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF) = (v))
bogdanm	82:6473597d706e	431	#endif
bogdanm	82:6473597d706e	432	//@}
bogdanm	82:6473597d706e	433
bogdanm	82:6473597d706e	434	/*!
bogdanm	82:6473597d706e	435	* @name Register I2S_TCSR, field WSF[20] (W1C)
bogdanm	82:6473597d706e	436	*
bogdanm	82:6473597d706e	437	* Indicates that the start of the configured word has been detected. Write a
bogdanm	82:6473597d706e	438	* logic 1 to this field to clear this flag.
bogdanm	82:6473597d706e	439	*
bogdanm	82:6473597d706e	440	* Values:
bogdanm	82:6473597d706e	441	* - 0 - Start of word not detected.
bogdanm	82:6473597d706e	442	* - 1 - Start of word detected.
bogdanm	82:6473597d706e	443	*/
bogdanm	82:6473597d706e	444	//@{
bogdanm	82:6473597d706e	445	#define BP_I2S_TCSR_WSF (20U) //!< Bit position for I2S_TCSR_WSF.
bogdanm	82:6473597d706e	446	#define BM_I2S_TCSR_WSF (0x00100000U) //!< Bit mask for I2S_TCSR_WSF.
bogdanm	82:6473597d706e	447	#define BS_I2S_TCSR_WSF (1U) //!< Bit field size in bits for I2S_TCSR_WSF.
bogdanm	82:6473597d706e	448
bogdanm	82:6473597d706e	449	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	450	//! @brief Read current value of the I2S_TCSR_WSF field.
bogdanm	82:6473597d706e	451	#define BR_I2S_TCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF))
bogdanm	82:6473597d706e	452	#endif
bogdanm	82:6473597d706e	453
bogdanm	82:6473597d706e	454	//! @brief Format value for bitfield I2S_TCSR_WSF.
bogdanm	82:6473597d706e	455	#define BF_I2S_TCSR_WSF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_WSF), uint32_t) & BM_I2S_TCSR_WSF)
bogdanm	82:6473597d706e	456
bogdanm	82:6473597d706e	457	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	458	//! @brief Set the WSF field to a new value.
bogdanm	82:6473597d706e	459	#define BW_I2S_TCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF) = (v))
bogdanm	82:6473597d706e	460	#endif
bogdanm	82:6473597d706e	461	//@}
bogdanm	82:6473597d706e	462
bogdanm	82:6473597d706e	463	/*!
bogdanm	82:6473597d706e	464	* @name Register I2S_TCSR, field SR[24] (RW)
bogdanm	82:6473597d706e	465	*
bogdanm	82:6473597d706e	466	* When set, resets the internal transmitter logic including the FIFO pointers.
bogdanm	82:6473597d706e	467	* Software-visible registers are not affected, except for the status registers.
bogdanm	82:6473597d706e	468	*
bogdanm	82:6473597d706e	469	* Values:
bogdanm	82:6473597d706e	470	* - 0 - No effect.
bogdanm	82:6473597d706e	471	* - 1 - Software reset.
bogdanm	82:6473597d706e	472	*/
bogdanm	82:6473597d706e	473	//@{
bogdanm	82:6473597d706e	474	#define BP_I2S_TCSR_SR (24U) //!< Bit position for I2S_TCSR_SR.
bogdanm	82:6473597d706e	475	#define BM_I2S_TCSR_SR (0x01000000U) //!< Bit mask for I2S_TCSR_SR.
bogdanm	82:6473597d706e	476	#define BS_I2S_TCSR_SR (1U) //!< Bit field size in bits for I2S_TCSR_SR.
bogdanm	82:6473597d706e	477
bogdanm	82:6473597d706e	478	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	479	//! @brief Read current value of the I2S_TCSR_SR field.
bogdanm	82:6473597d706e	480	#define BR_I2S_TCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR))
bogdanm	82:6473597d706e	481	#endif
bogdanm	82:6473597d706e	482
bogdanm	82:6473597d706e	483	//! @brief Format value for bitfield I2S_TCSR_SR.
bogdanm	82:6473597d706e	484	#define BF_I2S_TCSR_SR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SR), uint32_t) & BM_I2S_TCSR_SR)
bogdanm	82:6473597d706e	485
bogdanm	82:6473597d706e	486	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	487	//! @brief Set the SR field to a new value.
bogdanm	82:6473597d706e	488	#define BW_I2S_TCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR) = (v))
bogdanm	82:6473597d706e	489	#endif
bogdanm	82:6473597d706e	490	//@}
bogdanm	82:6473597d706e	491
bogdanm	82:6473597d706e	492	/*!
bogdanm	82:6473597d706e	493	* @name Register I2S_TCSR, field FR[25] (WORZ)
bogdanm	82:6473597d706e	494	*
bogdanm	82:6473597d706e	495	* Resets the FIFO pointers. Reading this field will always return zero. FIFO
bogdanm	82:6473597d706e	496	* pointers should only be reset when the transmitter is disabled or the FIFO error
bogdanm	82:6473597d706e	497	* flag is set.
bogdanm	82:6473597d706e	498	*
bogdanm	82:6473597d706e	499	* Values:
bogdanm	82:6473597d706e	500	* - 0 - No effect.
bogdanm	82:6473597d706e	501	* - 1 - FIFO reset.
bogdanm	82:6473597d706e	502	*/
bogdanm	82:6473597d706e	503	//@{
bogdanm	82:6473597d706e	504	#define BP_I2S_TCSR_FR (25U) //!< Bit position for I2S_TCSR_FR.
bogdanm	82:6473597d706e	505	#define BM_I2S_TCSR_FR (0x02000000U) //!< Bit mask for I2S_TCSR_FR.
bogdanm	82:6473597d706e	506	#define BS_I2S_TCSR_FR (1U) //!< Bit field size in bits for I2S_TCSR_FR.
bogdanm	82:6473597d706e	507
bogdanm	82:6473597d706e	508	//! @brief Format value for bitfield I2S_TCSR_FR.
bogdanm	82:6473597d706e	509	#define BF_I2S_TCSR_FR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FR), uint32_t) & BM_I2S_TCSR_FR)
bogdanm	82:6473597d706e	510
bogdanm	82:6473597d706e	511	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	512	//! @brief Set the FR field to a new value.
bogdanm	82:6473597d706e	513	#define BW_I2S_TCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FR) = (v))
bogdanm	82:6473597d706e	514	#endif
bogdanm	82:6473597d706e	515	//@}
bogdanm	82:6473597d706e	516
bogdanm	82:6473597d706e	517	/*!
bogdanm	82:6473597d706e	518	* @name Register I2S_TCSR, field BCE[28] (RW)
bogdanm	82:6473597d706e	519	*
bogdanm	82:6473597d706e	520	* Enables the transmit bit clock, separately from the TE. This field is
bogdanm	82:6473597d706e	521	* automatically set whenever TE is set. When software clears this field, the transmit
bogdanm	82:6473597d706e	522	* bit clock remains enabled, and this bit remains set, until the end of the
bogdanm	82:6473597d706e	523	* current frame.
bogdanm	82:6473597d706e	524	*
bogdanm	82:6473597d706e	525	* Values:
bogdanm	82:6473597d706e	526	* - 0 - Transmit bit clock is disabled.
bogdanm	82:6473597d706e	527	* - 1 - Transmit bit clock is enabled.
bogdanm	82:6473597d706e	528	*/
bogdanm	82:6473597d706e	529	//@{
bogdanm	82:6473597d706e	530	#define BP_I2S_TCSR_BCE (28U) //!< Bit position for I2S_TCSR_BCE.
bogdanm	82:6473597d706e	531	#define BM_I2S_TCSR_BCE (0x10000000U) //!< Bit mask for I2S_TCSR_BCE.
bogdanm	82:6473597d706e	532	#define BS_I2S_TCSR_BCE (1U) //!< Bit field size in bits for I2S_TCSR_BCE.
bogdanm	82:6473597d706e	533
bogdanm	82:6473597d706e	534	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	535	//! @brief Read current value of the I2S_TCSR_BCE field.
bogdanm	82:6473597d706e	536	#define BR_I2S_TCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE))
bogdanm	82:6473597d706e	537	#endif
bogdanm	82:6473597d706e	538
bogdanm	82:6473597d706e	539	//! @brief Format value for bitfield I2S_TCSR_BCE.
bogdanm	82:6473597d706e	540	#define BF_I2S_TCSR_BCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_BCE), uint32_t) & BM_I2S_TCSR_BCE)
bogdanm	82:6473597d706e	541
bogdanm	82:6473597d706e	542	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	543	//! @brief Set the BCE field to a new value.
bogdanm	82:6473597d706e	544	#define BW_I2S_TCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE) = (v))
bogdanm	82:6473597d706e	545	#endif
bogdanm	82:6473597d706e	546	//@}
bogdanm	82:6473597d706e	547
bogdanm	82:6473597d706e	548	/*!
bogdanm	82:6473597d706e	549	* @name Register I2S_TCSR, field DBGE[29] (RW)
bogdanm	82:6473597d706e	550	*
bogdanm	82:6473597d706e	551	* Enables/disables transmitter operation in Debug mode. The transmit bit clock
bogdanm	82:6473597d706e	552	* is not affected by debug mode.
bogdanm	82:6473597d706e	553	*
bogdanm	82:6473597d706e	554	* Values:
bogdanm	82:6473597d706e	555	* - 0 - Transmitter is disabled in Debug mode, after completing the current
bogdanm	82:6473597d706e	556	* frame.
bogdanm	82:6473597d706e	557	* - 1 - Transmitter is enabled in Debug mode.
bogdanm	82:6473597d706e	558	*/
bogdanm	82:6473597d706e	559	//@{
bogdanm	82:6473597d706e	560	#define BP_I2S_TCSR_DBGE (29U) //!< Bit position for I2S_TCSR_DBGE.
bogdanm	82:6473597d706e	561	#define BM_I2S_TCSR_DBGE (0x20000000U) //!< Bit mask for I2S_TCSR_DBGE.
bogdanm	82:6473597d706e	562	#define BS_I2S_TCSR_DBGE (1U) //!< Bit field size in bits for I2S_TCSR_DBGE.
bogdanm	82:6473597d706e	563
bogdanm	82:6473597d706e	564	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	565	//! @brief Read current value of the I2S_TCSR_DBGE field.
bogdanm	82:6473597d706e	566	#define BR_I2S_TCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE))
bogdanm	82:6473597d706e	567	#endif
bogdanm	82:6473597d706e	568
bogdanm	82:6473597d706e	569	//! @brief Format value for bitfield I2S_TCSR_DBGE.
bogdanm	82:6473597d706e	570	#define BF_I2S_TCSR_DBGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_DBGE), uint32_t) & BM_I2S_TCSR_DBGE)
bogdanm	82:6473597d706e	571
bogdanm	82:6473597d706e	572	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	573	//! @brief Set the DBGE field to a new value.
bogdanm	82:6473597d706e	574	#define BW_I2S_TCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE) = (v))
bogdanm	82:6473597d706e	575	#endif
bogdanm	82:6473597d706e	576	//@}
bogdanm	82:6473597d706e	577
bogdanm	82:6473597d706e	578	/*!
bogdanm	82:6473597d706e	579	* @name Register I2S_TCSR, field STOPE[30] (RW)
bogdanm	82:6473597d706e	580	*
bogdanm	82:6473597d706e	581	* Configures transmitter operation in Stop mode. This field is ignored and the
bogdanm	82:6473597d706e	582	* transmitter is disabled in all low-leakage stop modes.
bogdanm	82:6473597d706e	583	*
bogdanm	82:6473597d706e	584	* Values:
bogdanm	82:6473597d706e	585	* - 0 - Transmitter disabled in Stop mode.
bogdanm	82:6473597d706e	586	* - 1 - Transmitter enabled in Stop mode.
bogdanm	82:6473597d706e	587	*/
bogdanm	82:6473597d706e	588	//@{
bogdanm	82:6473597d706e	589	#define BP_I2S_TCSR_STOPE (30U) //!< Bit position for I2S_TCSR_STOPE.
bogdanm	82:6473597d706e	590	#define BM_I2S_TCSR_STOPE (0x40000000U) //!< Bit mask for I2S_TCSR_STOPE.
bogdanm	82:6473597d706e	591	#define BS_I2S_TCSR_STOPE (1U) //!< Bit field size in bits for I2S_TCSR_STOPE.
bogdanm	82:6473597d706e	592
bogdanm	82:6473597d706e	593	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	594	//! @brief Read current value of the I2S_TCSR_STOPE field.
bogdanm	82:6473597d706e	595	#define BR_I2S_TCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE))
bogdanm	82:6473597d706e	596	#endif
bogdanm	82:6473597d706e	597
bogdanm	82:6473597d706e	598	//! @brief Format value for bitfield I2S_TCSR_STOPE.
bogdanm	82:6473597d706e	599	#define BF_I2S_TCSR_STOPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_STOPE), uint32_t) & BM_I2S_TCSR_STOPE)
bogdanm	82:6473597d706e	600
bogdanm	82:6473597d706e	601	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	602	//! @brief Set the STOPE field to a new value.
bogdanm	82:6473597d706e	603	#define BW_I2S_TCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE) = (v))
bogdanm	82:6473597d706e	604	#endif
bogdanm	82:6473597d706e	605	//@}
bogdanm	82:6473597d706e	606
bogdanm	82:6473597d706e	607	/*!
bogdanm	82:6473597d706e	608	* @name Register I2S_TCSR, field TE[31] (RW)
bogdanm	82:6473597d706e	609	*
bogdanm	82:6473597d706e	610	* Enables/disables the transmitter. When software clears this field, the
bogdanm	82:6473597d706e	611	* transmitter remains enabled, and this bit remains set, until the end of the current
bogdanm	82:6473597d706e	612	* frame.
bogdanm	82:6473597d706e	613	*
bogdanm	82:6473597d706e	614	* Values:
bogdanm	82:6473597d706e	615	* - 0 - Transmitter is disabled.
bogdanm	82:6473597d706e	616	* - 1 - Transmitter is enabled, or transmitter has been disabled and has not
bogdanm	82:6473597d706e	617	* yet reached end of frame.
bogdanm	82:6473597d706e	618	*/
bogdanm	82:6473597d706e	619	//@{
bogdanm	82:6473597d706e	620	#define BP_I2S_TCSR_TE (31U) //!< Bit position for I2S_TCSR_TE.
bogdanm	82:6473597d706e	621	#define BM_I2S_TCSR_TE (0x80000000U) //!< Bit mask for I2S_TCSR_TE.
bogdanm	82:6473597d706e	622	#define BS_I2S_TCSR_TE (1U) //!< Bit field size in bits for I2S_TCSR_TE.
bogdanm	82:6473597d706e	623
bogdanm	82:6473597d706e	624	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	625	//! @brief Read current value of the I2S_TCSR_TE field.
bogdanm	82:6473597d706e	626	#define BR_I2S_TCSR_TE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE))
bogdanm	82:6473597d706e	627	#endif
bogdanm	82:6473597d706e	628
bogdanm	82:6473597d706e	629	//! @brief Format value for bitfield I2S_TCSR_TE.
bogdanm	82:6473597d706e	630	#define BF_I2S_TCSR_TE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_TE), uint32_t) & BM_I2S_TCSR_TE)
bogdanm	82:6473597d706e	631
bogdanm	82:6473597d706e	632	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	633	//! @brief Set the TE field to a new value.
bogdanm	82:6473597d706e	634	#define BW_I2S_TCSR_TE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE) = (v))
bogdanm	82:6473597d706e	635	#endif
bogdanm	82:6473597d706e	636	//@}
bogdanm	82:6473597d706e	637
bogdanm	82:6473597d706e	638	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	639	// HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
bogdanm	82:6473597d706e	640	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	641
bogdanm	82:6473597d706e	642	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	643	/*!
bogdanm	82:6473597d706e	644	* @brief HW_I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
bogdanm	82:6473597d706e	645	*
bogdanm	82:6473597d706e	646	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	647	*/
bogdanm	82:6473597d706e	648	typedef union _hw_i2s_tcr1
bogdanm	82:6473597d706e	649	{
bogdanm	82:6473597d706e	650	uint32_t U;
bogdanm	82:6473597d706e	651	struct _hw_i2s_tcr1_bitfields
bogdanm	82:6473597d706e	652	{
bogdanm	82:6473597d706e	653	uint32_t TFW : 3; //!< [2:0] Transmit FIFO Watermark
bogdanm	82:6473597d706e	654	uint32_t RESERVED0 : 29; //!< [31:3]
bogdanm	82:6473597d706e	655	} B;
bogdanm	82:6473597d706e	656	} hw_i2s_tcr1_t;
bogdanm	82:6473597d706e	657	#endif
bogdanm	82:6473597d706e	658
bogdanm	82:6473597d706e	659	/*!
bogdanm	82:6473597d706e	660	* @name Constants and macros for entire I2S_TCR1 register
bogdanm	82:6473597d706e	661	*/
bogdanm	82:6473597d706e	662	//@{
bogdanm	82:6473597d706e	663	#define HW_I2S_TCR1_ADDR(x) (REGS_I2S_BASE(x) + 0x4U)
bogdanm	82:6473597d706e	664
bogdanm	82:6473597d706e	665	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	666	#define HW_I2S_TCR1(x) ((__IO hw_i2s_tcr1_t ) HW_I2S_TCR1_ADDR(x))
bogdanm	82:6473597d706e	667	#define HW_I2S_TCR1_RD(x) (HW_I2S_TCR1(x).U)
bogdanm	82:6473597d706e	668	#define HW_I2S_TCR1_WR(x, v) (HW_I2S_TCR1(x).U = (v))
bogdanm	82:6473597d706e	669	#define HW_I2S_TCR1_SET(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) \| (v)))
bogdanm	82:6473597d706e	670	#define HW_I2S_TCR1_CLR(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	671	#define HW_I2S_TCR1_TOG(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	672	#endif
bogdanm	82:6473597d706e	673	//@}
bogdanm	82:6473597d706e	674
bogdanm	82:6473597d706e	675	/*
bogdanm	82:6473597d706e	676	* Constants & macros for individual I2S_TCR1 bitfields
bogdanm	82:6473597d706e	677	*/
bogdanm	82:6473597d706e	678
bogdanm	82:6473597d706e	679	/*!
bogdanm	82:6473597d706e	680	* @name Register I2S_TCR1, field TFW[2:0] (RW)
bogdanm	82:6473597d706e	681	*
bogdanm	82:6473597d706e	682	* Configures the watermark level for all enabled transmit channels.
bogdanm	82:6473597d706e	683	*/
bogdanm	82:6473597d706e	684	//@{
bogdanm	82:6473597d706e	685	#define BP_I2S_TCR1_TFW (0U) //!< Bit position for I2S_TCR1_TFW.
bogdanm	82:6473597d706e	686	#define BM_I2S_TCR1_TFW (0x00000007U) //!< Bit mask for I2S_TCR1_TFW.
bogdanm	82:6473597d706e	687	#define BS_I2S_TCR1_TFW (3U) //!< Bit field size in bits for I2S_TCR1_TFW.
bogdanm	82:6473597d706e	688
bogdanm	82:6473597d706e	689	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	690	//! @brief Read current value of the I2S_TCR1_TFW field.
bogdanm	82:6473597d706e	691	#define BR_I2S_TCR1_TFW(x) (HW_I2S_TCR1(x).B.TFW)
bogdanm	82:6473597d706e	692	#endif
bogdanm	82:6473597d706e	693
bogdanm	82:6473597d706e	694	//! @brief Format value for bitfield I2S_TCR1_TFW.
bogdanm	82:6473597d706e	695	#define BF_I2S_TCR1_TFW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR1_TFW), uint32_t) & BM_I2S_TCR1_TFW)
bogdanm	82:6473597d706e	696
bogdanm	82:6473597d706e	697	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	698	//! @brief Set the TFW field to a new value.
bogdanm	82:6473597d706e	699	#define BW_I2S_TCR1_TFW(x, v) (HW_I2S_TCR1_WR(x, (HW_I2S_TCR1_RD(x) & ~BM_I2S_TCR1_TFW) \| BF_I2S_TCR1_TFW(v)))
bogdanm	82:6473597d706e	700	#endif
bogdanm	82:6473597d706e	701	//@}
bogdanm	82:6473597d706e	702
bogdanm	82:6473597d706e	703	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	704	// HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
bogdanm	82:6473597d706e	705	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	706
bogdanm	82:6473597d706e	707	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	708	/*!
bogdanm	82:6473597d706e	709	* @brief HW_I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
bogdanm	82:6473597d706e	710	*
bogdanm	82:6473597d706e	711	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	712	*
bogdanm	82:6473597d706e	713	* This register must not be altered when TCSR[TE] is set.
bogdanm	82:6473597d706e	714	*/
bogdanm	82:6473597d706e	715	typedef union _hw_i2s_tcr2
bogdanm	82:6473597d706e	716	{
bogdanm	82:6473597d706e	717	uint32_t U;
bogdanm	82:6473597d706e	718	struct _hw_i2s_tcr2_bitfields
bogdanm	82:6473597d706e	719	{
bogdanm	82:6473597d706e	720	uint32_t DIV : 8; //!< [7:0] Bit Clock Divide
bogdanm	82:6473597d706e	721	uint32_t RESERVED0 : 16; //!< [23:8]
bogdanm	82:6473597d706e	722	uint32_t BCD : 1; //!< [24] Bit Clock Direction
bogdanm	82:6473597d706e	723	uint32_t BCP : 1; //!< [25] Bit Clock Polarity
bogdanm	82:6473597d706e	724	uint32_t MSEL : 2; //!< [27:26] MCLK Select
bogdanm	82:6473597d706e	725	uint32_t BCI : 1; //!< [28] Bit Clock Input
bogdanm	82:6473597d706e	726	uint32_t BCS : 1; //!< [29] Bit Clock Swap
bogdanm	82:6473597d706e	727	uint32_t SYNC : 2; //!< [31:30] Synchronous Mode
bogdanm	82:6473597d706e	728	} B;
bogdanm	82:6473597d706e	729	} hw_i2s_tcr2_t;
bogdanm	82:6473597d706e	730	#endif
bogdanm	82:6473597d706e	731
bogdanm	82:6473597d706e	732	/*!
bogdanm	82:6473597d706e	733	* @name Constants and macros for entire I2S_TCR2 register
bogdanm	82:6473597d706e	734	*/
bogdanm	82:6473597d706e	735	//@{
bogdanm	82:6473597d706e	736	#define HW_I2S_TCR2_ADDR(x) (REGS_I2S_BASE(x) + 0x8U)
bogdanm	82:6473597d706e	737
bogdanm	82:6473597d706e	738	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	739	#define HW_I2S_TCR2(x) ((__IO hw_i2s_tcr2_t ) HW_I2S_TCR2_ADDR(x))
bogdanm	82:6473597d706e	740	#define HW_I2S_TCR2_RD(x) (HW_I2S_TCR2(x).U)
bogdanm	82:6473597d706e	741	#define HW_I2S_TCR2_WR(x, v) (HW_I2S_TCR2(x).U = (v))
bogdanm	82:6473597d706e	742	#define HW_I2S_TCR2_SET(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) \| (v)))
bogdanm	82:6473597d706e	743	#define HW_I2S_TCR2_CLR(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) & ~(v)))
bogdanm	82:6473597d706e	744	#define HW_I2S_TCR2_TOG(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) ^ (v)))
bogdanm	82:6473597d706e	745	#endif
bogdanm	82:6473597d706e	746	//@}
bogdanm	82:6473597d706e	747
bogdanm	82:6473597d706e	748	/*
bogdanm	82:6473597d706e	749	* Constants & macros for individual I2S_TCR2 bitfields
bogdanm	82:6473597d706e	750	*/
bogdanm	82:6473597d706e	751
bogdanm	82:6473597d706e	752	/*!
bogdanm	82:6473597d706e	753	* @name Register I2S_TCR2, field DIV[7:0] (RW)
bogdanm	82:6473597d706e	754	*
bogdanm	82:6473597d706e	755	* Divides down the audio master clock to generate the bit clock when configured
bogdanm	82:6473597d706e	756	* for an internal bit clock. The division value is (DIV + 1) * 2.
bogdanm	82:6473597d706e	757	*/
bogdanm	82:6473597d706e	758	//@{
bogdanm	82:6473597d706e	759	#define BP_I2S_TCR2_DIV (0U) //!< Bit position for I2S_TCR2_DIV.
bogdanm	82:6473597d706e	760	#define BM_I2S_TCR2_DIV (0x000000FFU) //!< Bit mask for I2S_TCR2_DIV.
bogdanm	82:6473597d706e	761	#define BS_I2S_TCR2_DIV (8U) //!< Bit field size in bits for I2S_TCR2_DIV.
bogdanm	82:6473597d706e	762
bogdanm	82:6473597d706e	763	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	764	//! @brief Read current value of the I2S_TCR2_DIV field.
bogdanm	82:6473597d706e	765	#define BR_I2S_TCR2_DIV(x) (HW_I2S_TCR2(x).B.DIV)
bogdanm	82:6473597d706e	766	#endif
bogdanm	82:6473597d706e	767
bogdanm	82:6473597d706e	768	//! @brief Format value for bitfield I2S_TCR2_DIV.
bogdanm	82:6473597d706e	769	#define BF_I2S_TCR2_DIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_DIV), uint32_t) & BM_I2S_TCR2_DIV)
bogdanm	82:6473597d706e	770
bogdanm	82:6473597d706e	771	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	772	//! @brief Set the DIV field to a new value.
bogdanm	82:6473597d706e	773	#define BW_I2S_TCR2_DIV(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_DIV) \| BF_I2S_TCR2_DIV(v)))
bogdanm	82:6473597d706e	774	#endif
bogdanm	82:6473597d706e	775	//@}
bogdanm	82:6473597d706e	776
bogdanm	82:6473597d706e	777	/*!
bogdanm	82:6473597d706e	778	* @name Register I2S_TCR2, field BCD[24] (RW)
bogdanm	82:6473597d706e	779	*
bogdanm	82:6473597d706e	780	* Configures the direction of the bit clock.
bogdanm	82:6473597d706e	781	*
bogdanm	82:6473597d706e	782	* Values:
bogdanm	82:6473597d706e	783	* - 0 - Bit clock is generated externally in Slave mode.
bogdanm	82:6473597d706e	784	* - 1 - Bit clock is generated internally in Master mode.
bogdanm	82:6473597d706e	785	*/
bogdanm	82:6473597d706e	786	//@{
bogdanm	82:6473597d706e	787	#define BP_I2S_TCR2_BCD (24U) //!< Bit position for I2S_TCR2_BCD.
bogdanm	82:6473597d706e	788	#define BM_I2S_TCR2_BCD (0x01000000U) //!< Bit mask for I2S_TCR2_BCD.
bogdanm	82:6473597d706e	789	#define BS_I2S_TCR2_BCD (1U) //!< Bit field size in bits for I2S_TCR2_BCD.
bogdanm	82:6473597d706e	790
bogdanm	82:6473597d706e	791	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	792	//! @brief Read current value of the I2S_TCR2_BCD field.
bogdanm	82:6473597d706e	793	#define BR_I2S_TCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD))
bogdanm	82:6473597d706e	794	#endif
bogdanm	82:6473597d706e	795
bogdanm	82:6473597d706e	796	//! @brief Format value for bitfield I2S_TCR2_BCD.
bogdanm	82:6473597d706e	797	#define BF_I2S_TCR2_BCD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCD), uint32_t) & BM_I2S_TCR2_BCD)
bogdanm	82:6473597d706e	798
bogdanm	82:6473597d706e	799	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	800	//! @brief Set the BCD field to a new value.
bogdanm	82:6473597d706e	801	#define BW_I2S_TCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD) = (v))
bogdanm	82:6473597d706e	802	#endif
bogdanm	82:6473597d706e	803	//@}
bogdanm	82:6473597d706e	804
bogdanm	82:6473597d706e	805	/*!
bogdanm	82:6473597d706e	806	* @name Register I2S_TCR2, field BCP[25] (RW)
bogdanm	82:6473597d706e	807	*
bogdanm	82:6473597d706e	808	* Configures the polarity of the bit clock.
bogdanm	82:6473597d706e	809	*
bogdanm	82:6473597d706e	810	* Values:
bogdanm	82:6473597d706e	811	* - 0 - Bit clock is active high with drive outputs on rising edge and sample
bogdanm	82:6473597d706e	812	* inputs on falling edge.
bogdanm	82:6473597d706e	813	* - 1 - Bit clock is active low with drive outputs on falling edge and sample
bogdanm	82:6473597d706e	814	* inputs on rising edge.
bogdanm	82:6473597d706e	815	*/
bogdanm	82:6473597d706e	816	//@{
bogdanm	82:6473597d706e	817	#define BP_I2S_TCR2_BCP (25U) //!< Bit position for I2S_TCR2_BCP.
bogdanm	82:6473597d706e	818	#define BM_I2S_TCR2_BCP (0x02000000U) //!< Bit mask for I2S_TCR2_BCP.
bogdanm	82:6473597d706e	819	#define BS_I2S_TCR2_BCP (1U) //!< Bit field size in bits for I2S_TCR2_BCP.
bogdanm	82:6473597d706e	820
bogdanm	82:6473597d706e	821	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	822	//! @brief Read current value of the I2S_TCR2_BCP field.
bogdanm	82:6473597d706e	823	#define BR_I2S_TCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP))
bogdanm	82:6473597d706e	824	#endif
bogdanm	82:6473597d706e	825
bogdanm	82:6473597d706e	826	//! @brief Format value for bitfield I2S_TCR2_BCP.
bogdanm	82:6473597d706e	827	#define BF_I2S_TCR2_BCP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCP), uint32_t) & BM_I2S_TCR2_BCP)
bogdanm	82:6473597d706e	828
bogdanm	82:6473597d706e	829	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	830	//! @brief Set the BCP field to a new value.
bogdanm	82:6473597d706e	831	#define BW_I2S_TCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP) = (v))
bogdanm	82:6473597d706e	832	#endif
bogdanm	82:6473597d706e	833	//@}
bogdanm	82:6473597d706e	834
bogdanm	82:6473597d706e	835	/*!
bogdanm	82:6473597d706e	836	* @name Register I2S_TCR2, field MSEL[27:26] (RW)
bogdanm	82:6473597d706e	837	*
bogdanm	82:6473597d706e	838	* Selects the audio Master Clock option used to generate an internally
bogdanm	82:6473597d706e	839	* generated bit clock. This field has no effect when configured for an externally
bogdanm	82:6473597d706e	840	* generated bit clock. Depending on the device, some Master Clock options might not be
bogdanm	82:6473597d706e	841	* available. See the chip configuration details for the availability and
bogdanm	82:6473597d706e	842	* chip-specific meaning of each option.
bogdanm	82:6473597d706e	843	*
bogdanm	82:6473597d706e	844	* Values:
bogdanm	82:6473597d706e	845	* - 00 - Bus Clock selected.
bogdanm	82:6473597d706e	846	* - 01 - Master Clock (MCLK) 1 option selected.
bogdanm	82:6473597d706e	847	* - 10 - Master Clock (MCLK) 2 option selected.
bogdanm	82:6473597d706e	848	* - 11 - Master Clock (MCLK) 3 option selected.
bogdanm	82:6473597d706e	849	*/
bogdanm	82:6473597d706e	850	//@{
bogdanm	82:6473597d706e	851	#define BP_I2S_TCR2_MSEL (26U) //!< Bit position for I2S_TCR2_MSEL.
bogdanm	82:6473597d706e	852	#define BM_I2S_TCR2_MSEL (0x0C000000U) //!< Bit mask for I2S_TCR2_MSEL.
bogdanm	82:6473597d706e	853	#define BS_I2S_TCR2_MSEL (2U) //!< Bit field size in bits for I2S_TCR2_MSEL.
bogdanm	82:6473597d706e	854
bogdanm	82:6473597d706e	855	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	856	//! @brief Read current value of the I2S_TCR2_MSEL field.
bogdanm	82:6473597d706e	857	#define BR_I2S_TCR2_MSEL(x) (HW_I2S_TCR2(x).B.MSEL)
bogdanm	82:6473597d706e	858	#endif
bogdanm	82:6473597d706e	859
bogdanm	82:6473597d706e	860	//! @brief Format value for bitfield I2S_TCR2_MSEL.
bogdanm	82:6473597d706e	861	#define BF_I2S_TCR2_MSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_MSEL), uint32_t) & BM_I2S_TCR2_MSEL)
bogdanm	82:6473597d706e	862
bogdanm	82:6473597d706e	863	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	864	//! @brief Set the MSEL field to a new value.
bogdanm	82:6473597d706e	865	#define BW_I2S_TCR2_MSEL(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_MSEL) \| BF_I2S_TCR2_MSEL(v)))
bogdanm	82:6473597d706e	866	#endif
bogdanm	82:6473597d706e	867	//@}
bogdanm	82:6473597d706e	868
bogdanm	82:6473597d706e	869	/*!
bogdanm	82:6473597d706e	870	* @name Register I2S_TCR2, field BCI[28] (RW)
bogdanm	82:6473597d706e	871	*
bogdanm	82:6473597d706e	872	* When this field is set and using an internally generated bit clock in either
bogdanm	82:6473597d706e	873	* synchronous or asynchronous mode, the bit clock actually used by the
bogdanm	82:6473597d706e	874	* transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
bogdanm	82:6473597d706e	875	* input as if the clock was externally generated). This has the effect of
bogdanm	82:6473597d706e	876	* decreasing the data input setup time, but increasing the data output valid time. The
bogdanm	82:6473597d706e	877	* slave mode timing from the datasheet should be used for the transmitter when
bogdanm	82:6473597d706e	878	* this bit is set. In synchronous mode, this bit allows the transmitter to use
bogdanm	82:6473597d706e	879	* the slave mode timing from the datasheet, while the receiver uses the master
bogdanm	82:6473597d706e	880	* mode timing. This field has no effect when configured for an externally generated
bogdanm	82:6473597d706e	881	* bit clock or when synchronous to another SAI peripheral .
bogdanm	82:6473597d706e	882	*
bogdanm	82:6473597d706e	883	* Values:
bogdanm	82:6473597d706e	884	* - 0 - No effect.
bogdanm	82:6473597d706e	885	* - 1 - Internal logic is clocked as if bit clock was externally generated.
bogdanm	82:6473597d706e	886	*/
bogdanm	82:6473597d706e	887	//@{
bogdanm	82:6473597d706e	888	#define BP_I2S_TCR2_BCI (28U) //!< Bit position for I2S_TCR2_BCI.
bogdanm	82:6473597d706e	889	#define BM_I2S_TCR2_BCI (0x10000000U) //!< Bit mask for I2S_TCR2_BCI.
bogdanm	82:6473597d706e	890	#define BS_I2S_TCR2_BCI (1U) //!< Bit field size in bits for I2S_TCR2_BCI.
bogdanm	82:6473597d706e	891
bogdanm	82:6473597d706e	892	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	893	//! @brief Read current value of the I2S_TCR2_BCI field.
bogdanm	82:6473597d706e	894	#define BR_I2S_TCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI))
bogdanm	82:6473597d706e	895	#endif
bogdanm	82:6473597d706e	896
bogdanm	82:6473597d706e	897	//! @brief Format value for bitfield I2S_TCR2_BCI.
bogdanm	82:6473597d706e	898	#define BF_I2S_TCR2_BCI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCI), uint32_t) & BM_I2S_TCR2_BCI)
bogdanm	82:6473597d706e	899
bogdanm	82:6473597d706e	900	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	901	//! @brief Set the BCI field to a new value.
bogdanm	82:6473597d706e	902	#define BW_I2S_TCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI) = (v))
bogdanm	82:6473597d706e	903	#endif
bogdanm	82:6473597d706e	904	//@}
bogdanm	82:6473597d706e	905
bogdanm	82:6473597d706e	906	/*!
bogdanm	82:6473597d706e	907	* @name Register I2S_TCR2, field BCS[29] (RW)
bogdanm	82:6473597d706e	908	*
bogdanm	82:6473597d706e	909	* This field swaps the bit clock used by the transmitter. When the transmitter
bogdanm	82:6473597d706e	910	* is configured in asynchronous mode and this bit is set, the transmitter is
bogdanm	82:6473597d706e	911	* clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
bogdanm	82:6473597d706e	912	* receiver to share the same bit clock, but the transmitter continues to use the
bogdanm	82:6473597d706e	913	* transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
bogdanm	82:6473597d706e	914	* synchronous mode, the transmitter BCS field and receiver BCS field must be set to
bogdanm	82:6473597d706e	915	* the same value. When both are set, the transmitter and receiver are both
bogdanm	82:6473597d706e	916	* clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
bogdanm	82:6473597d706e	917	* (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
bogdanm	82:6473597d706e	918	* peripheral.
bogdanm	82:6473597d706e	919	*
bogdanm	82:6473597d706e	920	* Values:
bogdanm	82:6473597d706e	921	* - 0 - Use the normal bit clock source.
bogdanm	82:6473597d706e	922	* - 1 - Swap the bit clock source.
bogdanm	82:6473597d706e	923	*/
bogdanm	82:6473597d706e	924	//@{
bogdanm	82:6473597d706e	925	#define BP_I2S_TCR2_BCS (29U) //!< Bit position for I2S_TCR2_BCS.
bogdanm	82:6473597d706e	926	#define BM_I2S_TCR2_BCS (0x20000000U) //!< Bit mask for I2S_TCR2_BCS.
bogdanm	82:6473597d706e	927	#define BS_I2S_TCR2_BCS (1U) //!< Bit field size in bits for I2S_TCR2_BCS.
bogdanm	82:6473597d706e	928
bogdanm	82:6473597d706e	929	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	930	//! @brief Read current value of the I2S_TCR2_BCS field.
bogdanm	82:6473597d706e	931	#define BR_I2S_TCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS))
bogdanm	82:6473597d706e	932	#endif
bogdanm	82:6473597d706e	933
bogdanm	82:6473597d706e	934	//! @brief Format value for bitfield I2S_TCR2_BCS.
bogdanm	82:6473597d706e	935	#define BF_I2S_TCR2_BCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCS), uint32_t) & BM_I2S_TCR2_BCS)
bogdanm	82:6473597d706e	936
bogdanm	82:6473597d706e	937	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	938	//! @brief Set the BCS field to a new value.
bogdanm	82:6473597d706e	939	#define BW_I2S_TCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS) = (v))
bogdanm	82:6473597d706e	940	#endif
bogdanm	82:6473597d706e	941	//@}
bogdanm	82:6473597d706e	942
bogdanm	82:6473597d706e	943	/*!
bogdanm	82:6473597d706e	944	* @name Register I2S_TCR2, field SYNC[31:30] (RW)
bogdanm	82:6473597d706e	945	*
bogdanm	82:6473597d706e	946	* Configures between asynchronous and synchronous modes of operation. When
bogdanm	82:6473597d706e	947	* configured for a synchronous mode of operation, the receiver or other SAI
bogdanm	82:6473597d706e	948	* peripheral must be configured for asynchronous operation.
bogdanm	82:6473597d706e	949	*
bogdanm	82:6473597d706e	950	* Values:
bogdanm	82:6473597d706e	951	* - 00 - Asynchronous mode.
bogdanm	82:6473597d706e	952	* - 01 - Synchronous with receiver.
bogdanm	82:6473597d706e	953	* - 10 - Synchronous with another SAI transmitter.
bogdanm	82:6473597d706e	954	* - 11 - Synchronous with another SAI receiver.
bogdanm	82:6473597d706e	955	*/
bogdanm	82:6473597d706e	956	//@{
bogdanm	82:6473597d706e	957	#define BP_I2S_TCR2_SYNC (30U) //!< Bit position for I2S_TCR2_SYNC.
bogdanm	82:6473597d706e	958	#define BM_I2S_TCR2_SYNC (0xC0000000U) //!< Bit mask for I2S_TCR2_SYNC.
bogdanm	82:6473597d706e	959	#define BS_I2S_TCR2_SYNC (2U) //!< Bit field size in bits for I2S_TCR2_SYNC.
bogdanm	82:6473597d706e	960
bogdanm	82:6473597d706e	961	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	962	//! @brief Read current value of the I2S_TCR2_SYNC field.
bogdanm	82:6473597d706e	963	#define BR_I2S_TCR2_SYNC(x) (HW_I2S_TCR2(x).B.SYNC)
bogdanm	82:6473597d706e	964	#endif
bogdanm	82:6473597d706e	965
bogdanm	82:6473597d706e	966	//! @brief Format value for bitfield I2S_TCR2_SYNC.
bogdanm	82:6473597d706e	967	#define BF_I2S_TCR2_SYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_SYNC), uint32_t) & BM_I2S_TCR2_SYNC)
bogdanm	82:6473597d706e	968
bogdanm	82:6473597d706e	969	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	970	//! @brief Set the SYNC field to a new value.
bogdanm	82:6473597d706e	971	#define BW_I2S_TCR2_SYNC(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_SYNC) \| BF_I2S_TCR2_SYNC(v)))
bogdanm	82:6473597d706e	972	#endif
bogdanm	82:6473597d706e	973	//@}
bogdanm	82:6473597d706e	974
bogdanm	82:6473597d706e	975	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	976	// HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
bogdanm	82:6473597d706e	977	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	978
bogdanm	82:6473597d706e	979	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	980	/*!
bogdanm	82:6473597d706e	981	* @brief HW_I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
bogdanm	82:6473597d706e	982	*
bogdanm	82:6473597d706e	983	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	984	*
bogdanm	82:6473597d706e	985	* This register must not be altered when TCSR[TE] is set.
bogdanm	82:6473597d706e	986	*/
bogdanm	82:6473597d706e	987	typedef union _hw_i2s_tcr3
bogdanm	82:6473597d706e	988	{
bogdanm	82:6473597d706e	989	uint32_t U;
bogdanm	82:6473597d706e	990	struct _hw_i2s_tcr3_bitfields
bogdanm	82:6473597d706e	991	{
bogdanm	82:6473597d706e	992	uint32_t WDFL : 5; //!< [4:0] Word Flag Configuration
bogdanm	82:6473597d706e	993	uint32_t RESERVED0 : 11; //!< [15:5]
bogdanm	82:6473597d706e	994	uint32_t TCE : 2; //!< [17:16] Transmit Channel Enable
bogdanm	82:6473597d706e	995	uint32_t RESERVED1 : 14; //!< [31:18]
bogdanm	82:6473597d706e	996	} B;
bogdanm	82:6473597d706e	997	} hw_i2s_tcr3_t;
bogdanm	82:6473597d706e	998	#endif
bogdanm	82:6473597d706e	999
bogdanm	82:6473597d706e	1000	/*!
bogdanm	82:6473597d706e	1001	* @name Constants and macros for entire I2S_TCR3 register
bogdanm	82:6473597d706e	1002	*/
bogdanm	82:6473597d706e	1003	//@{
bogdanm	82:6473597d706e	1004	#define HW_I2S_TCR3_ADDR(x) (REGS_I2S_BASE(x) + 0xCU)
bogdanm	82:6473597d706e	1005
bogdanm	82:6473597d706e	1006	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1007	#define HW_I2S_TCR3(x) ((__IO hw_i2s_tcr3_t ) HW_I2S_TCR3_ADDR(x))
bogdanm	82:6473597d706e	1008	#define HW_I2S_TCR3_RD(x) (HW_I2S_TCR3(x).U)
bogdanm	82:6473597d706e	1009	#define HW_I2S_TCR3_WR(x, v) (HW_I2S_TCR3(x).U = (v))
bogdanm	82:6473597d706e	1010	#define HW_I2S_TCR3_SET(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) \| (v)))
bogdanm	82:6473597d706e	1011	#define HW_I2S_TCR3_CLR(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1012	#define HW_I2S_TCR3_TOG(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1013	#endif
bogdanm	82:6473597d706e	1014	//@}
bogdanm	82:6473597d706e	1015
bogdanm	82:6473597d706e	1016	/*
bogdanm	82:6473597d706e	1017	* Constants & macros for individual I2S_TCR3 bitfields
bogdanm	82:6473597d706e	1018	*/
bogdanm	82:6473597d706e	1019
bogdanm	82:6473597d706e	1020	/*!
bogdanm	82:6473597d706e	1021	* @name Register I2S_TCR3, field WDFL[4:0] (RW)
bogdanm	82:6473597d706e	1022	*
bogdanm	82:6473597d706e	1023	* Configures which word sets the start of word flag. The value written must be
bogdanm	82:6473597d706e	1024	* one less than the word number. For example, writing 0 configures the first
bogdanm	82:6473597d706e	1025	* word in the frame. When configured to a value greater than TCR4[FRSZ], then the
bogdanm	82:6473597d706e	1026	* start of word flag is never set.
bogdanm	82:6473597d706e	1027	*/
bogdanm	82:6473597d706e	1028	//@{
bogdanm	82:6473597d706e	1029	#define BP_I2S_TCR3_WDFL (0U) //!< Bit position for I2S_TCR3_WDFL.
bogdanm	82:6473597d706e	1030	#define BM_I2S_TCR3_WDFL (0x0000001FU) //!< Bit mask for I2S_TCR3_WDFL.
bogdanm	82:6473597d706e	1031	#define BS_I2S_TCR3_WDFL (5U) //!< Bit field size in bits for I2S_TCR3_WDFL.
bogdanm	82:6473597d706e	1032
bogdanm	82:6473597d706e	1033	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1034	//! @brief Read current value of the I2S_TCR3_WDFL field.
bogdanm	82:6473597d706e	1035	#define BR_I2S_TCR3_WDFL(x) (HW_I2S_TCR3(x).B.WDFL)
bogdanm	82:6473597d706e	1036	#endif
bogdanm	82:6473597d706e	1037
bogdanm	82:6473597d706e	1038	//! @brief Format value for bitfield I2S_TCR3_WDFL.
bogdanm	82:6473597d706e	1039	#define BF_I2S_TCR3_WDFL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR3_WDFL), uint32_t) & BM_I2S_TCR3_WDFL)
bogdanm	82:6473597d706e	1040
bogdanm	82:6473597d706e	1041	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1042	//! @brief Set the WDFL field to a new value.
bogdanm	82:6473597d706e	1043	#define BW_I2S_TCR3_WDFL(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_WDFL) \| BF_I2S_TCR3_WDFL(v)))
bogdanm	82:6473597d706e	1044	#endif
bogdanm	82:6473597d706e	1045	//@}
bogdanm	82:6473597d706e	1046
bogdanm	82:6473597d706e	1047	/*!
bogdanm	82:6473597d706e	1048	* @name Register I2S_TCR3, field TCE[17:16] (RW)
bogdanm	82:6473597d706e	1049	*
bogdanm	82:6473597d706e	1050	* Enables the corresponding data channel for transmit operation. A channel must
bogdanm	82:6473597d706e	1051	* be enabled before its FIFO is accessed.
bogdanm	82:6473597d706e	1052	*
bogdanm	82:6473597d706e	1053	* Values:
bogdanm	82:6473597d706e	1054	* - 0 - Transmit data channel N is disabled.
bogdanm	82:6473597d706e	1055	* - 1 - Transmit data channel N is enabled.
bogdanm	82:6473597d706e	1056	*/
bogdanm	82:6473597d706e	1057	//@{
bogdanm	82:6473597d706e	1058	#define BP_I2S_TCR3_TCE (16U) //!< Bit position for I2S_TCR3_TCE.
bogdanm	82:6473597d706e	1059	#define BM_I2S_TCR3_TCE (0x00030000U) //!< Bit mask for I2S_TCR3_TCE.
bogdanm	82:6473597d706e	1060	#define BS_I2S_TCR3_TCE (2U) //!< Bit field size in bits for I2S_TCR3_TCE.
bogdanm	82:6473597d706e	1061
bogdanm	82:6473597d706e	1062	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1063	//! @brief Read current value of the I2S_TCR3_TCE field.
bogdanm	82:6473597d706e	1064	#define BR_I2S_TCR3_TCE(x) (HW_I2S_TCR3(x).B.TCE)
bogdanm	82:6473597d706e	1065	#endif
bogdanm	82:6473597d706e	1066
bogdanm	82:6473597d706e	1067	//! @brief Format value for bitfield I2S_TCR3_TCE.
bogdanm	82:6473597d706e	1068	#define BF_I2S_TCR3_TCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR3_TCE), uint32_t) & BM_I2S_TCR3_TCE)
bogdanm	82:6473597d706e	1069
bogdanm	82:6473597d706e	1070	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1071	//! @brief Set the TCE field to a new value.
bogdanm	82:6473597d706e	1072	#define BW_I2S_TCR3_TCE(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_TCE) \| BF_I2S_TCR3_TCE(v)))
bogdanm	82:6473597d706e	1073	#endif
bogdanm	82:6473597d706e	1074	//@}
bogdanm	82:6473597d706e	1075
bogdanm	82:6473597d706e	1076	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1077	// HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
bogdanm	82:6473597d706e	1078	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1079
bogdanm	82:6473597d706e	1080	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1081	/*!
bogdanm	82:6473597d706e	1082	* @brief HW_I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
bogdanm	82:6473597d706e	1083	*
bogdanm	82:6473597d706e	1084	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1085	*
bogdanm	82:6473597d706e	1086	* This register must not be altered when TCSR[TE] is set.
bogdanm	82:6473597d706e	1087	*/
bogdanm	82:6473597d706e	1088	typedef union _hw_i2s_tcr4
bogdanm	82:6473597d706e	1089	{
bogdanm	82:6473597d706e	1090	uint32_t U;
bogdanm	82:6473597d706e	1091	struct _hw_i2s_tcr4_bitfields
bogdanm	82:6473597d706e	1092	{
bogdanm	82:6473597d706e	1093	uint32_t FSD : 1; //!< [0] Frame Sync Direction
bogdanm	82:6473597d706e	1094	uint32_t FSP : 1; //!< [1] Frame Sync Polarity
bogdanm	82:6473597d706e	1095	uint32_t RESERVED0 : 1; //!< [2]
bogdanm	82:6473597d706e	1096	uint32_t FSE : 1; //!< [3] Frame Sync Early
bogdanm	82:6473597d706e	1097	uint32_t MF : 1; //!< [4] MSB First
bogdanm	82:6473597d706e	1098	uint32_t RESERVED1 : 3; //!< [7:5]
bogdanm	82:6473597d706e	1099	uint32_t SYWD : 5; //!< [12:8] Sync Width
bogdanm	82:6473597d706e	1100	uint32_t RESERVED2 : 3; //!< [15:13]
bogdanm	82:6473597d706e	1101	uint32_t FRSZ : 5; //!< [20:16] Frame size
bogdanm	82:6473597d706e	1102	uint32_t RESERVED3 : 11; //!< [31:21]
bogdanm	82:6473597d706e	1103	} B;
bogdanm	82:6473597d706e	1104	} hw_i2s_tcr4_t;
bogdanm	82:6473597d706e	1105	#endif
bogdanm	82:6473597d706e	1106
bogdanm	82:6473597d706e	1107	/*!
bogdanm	82:6473597d706e	1108	* @name Constants and macros for entire I2S_TCR4 register
bogdanm	82:6473597d706e	1109	*/
bogdanm	82:6473597d706e	1110	//@{
bogdanm	82:6473597d706e	1111	#define HW_I2S_TCR4_ADDR(x) (REGS_I2S_BASE(x) + 0x10U)
bogdanm	82:6473597d706e	1112
bogdanm	82:6473597d706e	1113	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1114	#define HW_I2S_TCR4(x) ((__IO hw_i2s_tcr4_t ) HW_I2S_TCR4_ADDR(x))
bogdanm	82:6473597d706e	1115	#define HW_I2S_TCR4_RD(x) (HW_I2S_TCR4(x).U)
bogdanm	82:6473597d706e	1116	#define HW_I2S_TCR4_WR(x, v) (HW_I2S_TCR4(x).U = (v))
bogdanm	82:6473597d706e	1117	#define HW_I2S_TCR4_SET(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) \| (v)))
bogdanm	82:6473597d706e	1118	#define HW_I2S_TCR4_CLR(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1119	#define HW_I2S_TCR4_TOG(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1120	#endif
bogdanm	82:6473597d706e	1121	//@}
bogdanm	82:6473597d706e	1122
bogdanm	82:6473597d706e	1123	/*
bogdanm	82:6473597d706e	1124	* Constants & macros for individual I2S_TCR4 bitfields
bogdanm	82:6473597d706e	1125	*/
bogdanm	82:6473597d706e	1126
bogdanm	82:6473597d706e	1127	/*!
bogdanm	82:6473597d706e	1128	* @name Register I2S_TCR4, field FSD[0] (RW)
bogdanm	82:6473597d706e	1129	*
bogdanm	82:6473597d706e	1130	* Configures the direction of the frame sync.
bogdanm	82:6473597d706e	1131	*
bogdanm	82:6473597d706e	1132	* Values:
bogdanm	82:6473597d706e	1133	* - 0 - Frame sync is generated externally in Slave mode.
bogdanm	82:6473597d706e	1134	* - 1 - Frame sync is generated internally in Master mode.
bogdanm	82:6473597d706e	1135	*/
bogdanm	82:6473597d706e	1136	//@{
bogdanm	82:6473597d706e	1137	#define BP_I2S_TCR4_FSD (0U) //!< Bit position for I2S_TCR4_FSD.
bogdanm	82:6473597d706e	1138	#define BM_I2S_TCR4_FSD (0x00000001U) //!< Bit mask for I2S_TCR4_FSD.
bogdanm	82:6473597d706e	1139	#define BS_I2S_TCR4_FSD (1U) //!< Bit field size in bits for I2S_TCR4_FSD.
bogdanm	82:6473597d706e	1140
bogdanm	82:6473597d706e	1141	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1142	//! @brief Read current value of the I2S_TCR4_FSD field.
bogdanm	82:6473597d706e	1143	#define BR_I2S_TCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD))
bogdanm	82:6473597d706e	1144	#endif
bogdanm	82:6473597d706e	1145
bogdanm	82:6473597d706e	1146	//! @brief Format value for bitfield I2S_TCR4_FSD.
bogdanm	82:6473597d706e	1147	#define BF_I2S_TCR4_FSD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSD), uint32_t) & BM_I2S_TCR4_FSD)
bogdanm	82:6473597d706e	1148
bogdanm	82:6473597d706e	1149	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1150	//! @brief Set the FSD field to a new value.
bogdanm	82:6473597d706e	1151	#define BW_I2S_TCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD) = (v))
bogdanm	82:6473597d706e	1152	#endif
bogdanm	82:6473597d706e	1153	//@}
bogdanm	82:6473597d706e	1154
bogdanm	82:6473597d706e	1155	/*!
bogdanm	82:6473597d706e	1156	* @name Register I2S_TCR4, field FSP[1] (RW)
bogdanm	82:6473597d706e	1157	*
bogdanm	82:6473597d706e	1158	* Configures the polarity of the frame sync.
bogdanm	82:6473597d706e	1159	*
bogdanm	82:6473597d706e	1160	* Values:
bogdanm	82:6473597d706e	1161	* - 0 - Frame sync is active high.
bogdanm	82:6473597d706e	1162	* - 1 - Frame sync is active low.
bogdanm	82:6473597d706e	1163	*/
bogdanm	82:6473597d706e	1164	//@{
bogdanm	82:6473597d706e	1165	#define BP_I2S_TCR4_FSP (1U) //!< Bit position for I2S_TCR4_FSP.
bogdanm	82:6473597d706e	1166	#define BM_I2S_TCR4_FSP (0x00000002U) //!< Bit mask for I2S_TCR4_FSP.
bogdanm	82:6473597d706e	1167	#define BS_I2S_TCR4_FSP (1U) //!< Bit field size in bits for I2S_TCR4_FSP.
bogdanm	82:6473597d706e	1168
bogdanm	82:6473597d706e	1169	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1170	//! @brief Read current value of the I2S_TCR4_FSP field.
bogdanm	82:6473597d706e	1171	#define BR_I2S_TCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP))
bogdanm	82:6473597d706e	1172	#endif
bogdanm	82:6473597d706e	1173
bogdanm	82:6473597d706e	1174	//! @brief Format value for bitfield I2S_TCR4_FSP.
bogdanm	82:6473597d706e	1175	#define BF_I2S_TCR4_FSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSP), uint32_t) & BM_I2S_TCR4_FSP)
bogdanm	82:6473597d706e	1176
bogdanm	82:6473597d706e	1177	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1178	//! @brief Set the FSP field to a new value.
bogdanm	82:6473597d706e	1179	#define BW_I2S_TCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP) = (v))
bogdanm	82:6473597d706e	1180	#endif
bogdanm	82:6473597d706e	1181	//@}
bogdanm	82:6473597d706e	1182
bogdanm	82:6473597d706e	1183	/*!
bogdanm	82:6473597d706e	1184	* @name Register I2S_TCR4, field FSE[3] (RW)
bogdanm	82:6473597d706e	1185	*
bogdanm	82:6473597d706e	1186	* Values:
bogdanm	82:6473597d706e	1187	* - 0 - Frame sync asserts with the first bit of the frame.
bogdanm	82:6473597d706e	1188	* - 1 - Frame sync asserts one bit before the first bit of the frame.
bogdanm	82:6473597d706e	1189	*/
bogdanm	82:6473597d706e	1190	//@{
bogdanm	82:6473597d706e	1191	#define BP_I2S_TCR4_FSE (3U) //!< Bit position for I2S_TCR4_FSE.
bogdanm	82:6473597d706e	1192	#define BM_I2S_TCR4_FSE (0x00000008U) //!< Bit mask for I2S_TCR4_FSE.
bogdanm	82:6473597d706e	1193	#define BS_I2S_TCR4_FSE (1U) //!< Bit field size in bits for I2S_TCR4_FSE.
bogdanm	82:6473597d706e	1194
bogdanm	82:6473597d706e	1195	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1196	//! @brief Read current value of the I2S_TCR4_FSE field.
bogdanm	82:6473597d706e	1197	#define BR_I2S_TCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE))
bogdanm	82:6473597d706e	1198	#endif
bogdanm	82:6473597d706e	1199
bogdanm	82:6473597d706e	1200	//! @brief Format value for bitfield I2S_TCR4_FSE.
bogdanm	82:6473597d706e	1201	#define BF_I2S_TCR4_FSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSE), uint32_t) & BM_I2S_TCR4_FSE)
bogdanm	82:6473597d706e	1202
bogdanm	82:6473597d706e	1203	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1204	//! @brief Set the FSE field to a new value.
bogdanm	82:6473597d706e	1205	#define BW_I2S_TCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE) = (v))
bogdanm	82:6473597d706e	1206	#endif
bogdanm	82:6473597d706e	1207	//@}
bogdanm	82:6473597d706e	1208
bogdanm	82:6473597d706e	1209	/*!
bogdanm	82:6473597d706e	1210	* @name Register I2S_TCR4, field MF[4] (RW)
bogdanm	82:6473597d706e	1211	*
bogdanm	82:6473597d706e	1212	* Configures whether the LSB or the MSB is transmitted first.
bogdanm	82:6473597d706e	1213	*
bogdanm	82:6473597d706e	1214	* Values:
bogdanm	82:6473597d706e	1215	* - 0 - LSB is transmitted first.
bogdanm	82:6473597d706e	1216	* - 1 - MSB is transmitted first.
bogdanm	82:6473597d706e	1217	*/
bogdanm	82:6473597d706e	1218	//@{
bogdanm	82:6473597d706e	1219	#define BP_I2S_TCR4_MF (4U) //!< Bit position for I2S_TCR4_MF.
bogdanm	82:6473597d706e	1220	#define BM_I2S_TCR4_MF (0x00000010U) //!< Bit mask for I2S_TCR4_MF.
bogdanm	82:6473597d706e	1221	#define BS_I2S_TCR4_MF (1U) //!< Bit field size in bits for I2S_TCR4_MF.
bogdanm	82:6473597d706e	1222
bogdanm	82:6473597d706e	1223	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1224	//! @brief Read current value of the I2S_TCR4_MF field.
bogdanm	82:6473597d706e	1225	#define BR_I2S_TCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF))
bogdanm	82:6473597d706e	1226	#endif
bogdanm	82:6473597d706e	1227
bogdanm	82:6473597d706e	1228	//! @brief Format value for bitfield I2S_TCR4_MF.
bogdanm	82:6473597d706e	1229	#define BF_I2S_TCR4_MF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_MF), uint32_t) & BM_I2S_TCR4_MF)
bogdanm	82:6473597d706e	1230
bogdanm	82:6473597d706e	1231	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1232	//! @brief Set the MF field to a new value.
bogdanm	82:6473597d706e	1233	#define BW_I2S_TCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF) = (v))
bogdanm	82:6473597d706e	1234	#endif
bogdanm	82:6473597d706e	1235	//@}
bogdanm	82:6473597d706e	1236
bogdanm	82:6473597d706e	1237	/*!
bogdanm	82:6473597d706e	1238	* @name Register I2S_TCR4, field SYWD[12:8] (RW)
bogdanm	82:6473597d706e	1239	*
bogdanm	82:6473597d706e	1240	* Configures the length of the frame sync in number of bit clocks. The value
bogdanm	82:6473597d706e	1241	* written must be one less than the number of bit clocks. For example, write 0 for
bogdanm	82:6473597d706e	1242	* the frame sync to assert for one bit clock only. The sync width cannot be
bogdanm	82:6473597d706e	1243	* configured longer than the first word of the frame.
bogdanm	82:6473597d706e	1244	*/
bogdanm	82:6473597d706e	1245	//@{
bogdanm	82:6473597d706e	1246	#define BP_I2S_TCR4_SYWD (8U) //!< Bit position for I2S_TCR4_SYWD.
bogdanm	82:6473597d706e	1247	#define BM_I2S_TCR4_SYWD (0x00001F00U) //!< Bit mask for I2S_TCR4_SYWD.
bogdanm	82:6473597d706e	1248	#define BS_I2S_TCR4_SYWD (5U) //!< Bit field size in bits for I2S_TCR4_SYWD.
bogdanm	82:6473597d706e	1249
bogdanm	82:6473597d706e	1250	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1251	//! @brief Read current value of the I2S_TCR4_SYWD field.
bogdanm	82:6473597d706e	1252	#define BR_I2S_TCR4_SYWD(x) (HW_I2S_TCR4(x).B.SYWD)
bogdanm	82:6473597d706e	1253	#endif
bogdanm	82:6473597d706e	1254
bogdanm	82:6473597d706e	1255	//! @brief Format value for bitfield I2S_TCR4_SYWD.
bogdanm	82:6473597d706e	1256	#define BF_I2S_TCR4_SYWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_SYWD), uint32_t) & BM_I2S_TCR4_SYWD)
bogdanm	82:6473597d706e	1257
bogdanm	82:6473597d706e	1258	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1259	//! @brief Set the SYWD field to a new value.
bogdanm	82:6473597d706e	1260	#define BW_I2S_TCR4_SYWD(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_SYWD) \| BF_I2S_TCR4_SYWD(v)))
bogdanm	82:6473597d706e	1261	#endif
bogdanm	82:6473597d706e	1262	//@}
bogdanm	82:6473597d706e	1263
bogdanm	82:6473597d706e	1264	/*!
bogdanm	82:6473597d706e	1265	* @name Register I2S_TCR4, field FRSZ[20:16] (RW)
bogdanm	82:6473597d706e	1266	*
bogdanm	82:6473597d706e	1267	* Configures the number of words in each frame. The value written must be one
bogdanm	82:6473597d706e	1268	* less than the number of words in the frame. For example, write 0 for one word
bogdanm	82:6473597d706e	1269	* per frame. The maximum supported frame size is 32 words.
bogdanm	82:6473597d706e	1270	*/
bogdanm	82:6473597d706e	1271	//@{
bogdanm	82:6473597d706e	1272	#define BP_I2S_TCR4_FRSZ (16U) //!< Bit position for I2S_TCR4_FRSZ.
bogdanm	82:6473597d706e	1273	#define BM_I2S_TCR4_FRSZ (0x001F0000U) //!< Bit mask for I2S_TCR4_FRSZ.
bogdanm	82:6473597d706e	1274	#define BS_I2S_TCR4_FRSZ (5U) //!< Bit field size in bits for I2S_TCR4_FRSZ.
bogdanm	82:6473597d706e	1275
bogdanm	82:6473597d706e	1276	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1277	//! @brief Read current value of the I2S_TCR4_FRSZ field.
bogdanm	82:6473597d706e	1278	#define BR_I2S_TCR4_FRSZ(x) (HW_I2S_TCR4(x).B.FRSZ)
bogdanm	82:6473597d706e	1279	#endif
bogdanm	82:6473597d706e	1280
bogdanm	82:6473597d706e	1281	//! @brief Format value for bitfield I2S_TCR4_FRSZ.
bogdanm	82:6473597d706e	1282	#define BF_I2S_TCR4_FRSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FRSZ), uint32_t) & BM_I2S_TCR4_FRSZ)
bogdanm	82:6473597d706e	1283
bogdanm	82:6473597d706e	1284	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1285	//! @brief Set the FRSZ field to a new value.
bogdanm	82:6473597d706e	1286	#define BW_I2S_TCR4_FRSZ(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FRSZ) \| BF_I2S_TCR4_FRSZ(v)))
bogdanm	82:6473597d706e	1287	#endif
bogdanm	82:6473597d706e	1288	//@}
bogdanm	82:6473597d706e	1289
bogdanm	82:6473597d706e	1290	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1291	// HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
bogdanm	82:6473597d706e	1292	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1293
bogdanm	82:6473597d706e	1294	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1295	/*!
bogdanm	82:6473597d706e	1296	* @brief HW_I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
bogdanm	82:6473597d706e	1297	*
bogdanm	82:6473597d706e	1298	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1299	*
bogdanm	82:6473597d706e	1300	* This register must not be altered when TCSR[TE] is set.
bogdanm	82:6473597d706e	1301	*/
bogdanm	82:6473597d706e	1302	typedef union _hw_i2s_tcr5
bogdanm	82:6473597d706e	1303	{
bogdanm	82:6473597d706e	1304	uint32_t U;
bogdanm	82:6473597d706e	1305	struct _hw_i2s_tcr5_bitfields
bogdanm	82:6473597d706e	1306	{
bogdanm	82:6473597d706e	1307	uint32_t RESERVED0 : 8; //!< [7:0]
bogdanm	82:6473597d706e	1308	uint32_t FBT : 5; //!< [12:8] First Bit Shifted
bogdanm	82:6473597d706e	1309	uint32_t RESERVED1 : 3; //!< [15:13]
bogdanm	82:6473597d706e	1310	uint32_t W0W : 5; //!< [20:16] Word 0 Width
bogdanm	82:6473597d706e	1311	uint32_t RESERVED2 : 3; //!< [23:21]
bogdanm	82:6473597d706e	1312	uint32_t WNW : 5; //!< [28:24] Word N Width
bogdanm	82:6473597d706e	1313	uint32_t RESERVED3 : 3; //!< [31:29]
bogdanm	82:6473597d706e	1314	} B;
bogdanm	82:6473597d706e	1315	} hw_i2s_tcr5_t;
bogdanm	82:6473597d706e	1316	#endif
bogdanm	82:6473597d706e	1317
bogdanm	82:6473597d706e	1318	/*!
bogdanm	82:6473597d706e	1319	* @name Constants and macros for entire I2S_TCR5 register
bogdanm	82:6473597d706e	1320	*/
bogdanm	82:6473597d706e	1321	//@{
bogdanm	82:6473597d706e	1322	#define HW_I2S_TCR5_ADDR(x) (REGS_I2S_BASE(x) + 0x14U)
bogdanm	82:6473597d706e	1323
bogdanm	82:6473597d706e	1324	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1325	#define HW_I2S_TCR5(x) ((__IO hw_i2s_tcr5_t ) HW_I2S_TCR5_ADDR(x))
bogdanm	82:6473597d706e	1326	#define HW_I2S_TCR5_RD(x) (HW_I2S_TCR5(x).U)
bogdanm	82:6473597d706e	1327	#define HW_I2S_TCR5_WR(x, v) (HW_I2S_TCR5(x).U = (v))
bogdanm	82:6473597d706e	1328	#define HW_I2S_TCR5_SET(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) \| (v)))
bogdanm	82:6473597d706e	1329	#define HW_I2S_TCR5_CLR(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1330	#define HW_I2S_TCR5_TOG(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1331	#endif
bogdanm	82:6473597d706e	1332	//@}
bogdanm	82:6473597d706e	1333
bogdanm	82:6473597d706e	1334	/*
bogdanm	82:6473597d706e	1335	* Constants & macros for individual I2S_TCR5 bitfields
bogdanm	82:6473597d706e	1336	*/
bogdanm	82:6473597d706e	1337
bogdanm	82:6473597d706e	1338	/*!
bogdanm	82:6473597d706e	1339	* @name Register I2S_TCR5, field FBT[12:8] (RW)
bogdanm	82:6473597d706e	1340	*
bogdanm	82:6473597d706e	1341	* Configures the bit index for the first bit transmitted for each word in the
bogdanm	82:6473597d706e	1342	* frame. If configured for MSB First, the index of the next bit transmitted is
bogdanm	82:6473597d706e	1343	* one less than the current bit transmitted. If configured for LSB First, the
bogdanm	82:6473597d706e	1344	* index of the next bit transmitted is one more than the current bit transmitted.
bogdanm	82:6473597d706e	1345	* The value written must be greater than or equal to the word width when
bogdanm	82:6473597d706e	1346	* configured for MSB First. The value written must be less than or equal to 31-word width
bogdanm	82:6473597d706e	1347	* when configured for LSB First.
bogdanm	82:6473597d706e	1348	*/
bogdanm	82:6473597d706e	1349	//@{
bogdanm	82:6473597d706e	1350	#define BP_I2S_TCR5_FBT (8U) //!< Bit position for I2S_TCR5_FBT.
bogdanm	82:6473597d706e	1351	#define BM_I2S_TCR5_FBT (0x00001F00U) //!< Bit mask for I2S_TCR5_FBT.
bogdanm	82:6473597d706e	1352	#define BS_I2S_TCR5_FBT (5U) //!< Bit field size in bits for I2S_TCR5_FBT.
bogdanm	82:6473597d706e	1353
bogdanm	82:6473597d706e	1354	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1355	//! @brief Read current value of the I2S_TCR5_FBT field.
bogdanm	82:6473597d706e	1356	#define BR_I2S_TCR5_FBT(x) (HW_I2S_TCR5(x).B.FBT)
bogdanm	82:6473597d706e	1357	#endif
bogdanm	82:6473597d706e	1358
bogdanm	82:6473597d706e	1359	//! @brief Format value for bitfield I2S_TCR5_FBT.
bogdanm	82:6473597d706e	1360	#define BF_I2S_TCR5_FBT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_FBT), uint32_t) & BM_I2S_TCR5_FBT)
bogdanm	82:6473597d706e	1361
bogdanm	82:6473597d706e	1362	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1363	//! @brief Set the FBT field to a new value.
bogdanm	82:6473597d706e	1364	#define BW_I2S_TCR5_FBT(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_FBT) \| BF_I2S_TCR5_FBT(v)))
bogdanm	82:6473597d706e	1365	#endif
bogdanm	82:6473597d706e	1366	//@}
bogdanm	82:6473597d706e	1367
bogdanm	82:6473597d706e	1368	/*!
bogdanm	82:6473597d706e	1369	* @name Register I2S_TCR5, field W0W[20:16] (RW)
bogdanm	82:6473597d706e	1370	*
bogdanm	82:6473597d706e	1371	* Configures the number of bits in the first word in each frame. The value
bogdanm	82:6473597d706e	1372	* written must be one less than the number of bits in the first word. Word width of
bogdanm	82:6473597d706e	1373	* less than 8 bits is not supported if there is only one word per frame.
bogdanm	82:6473597d706e	1374	*/
bogdanm	82:6473597d706e	1375	//@{
bogdanm	82:6473597d706e	1376	#define BP_I2S_TCR5_W0W (16U) //!< Bit position for I2S_TCR5_W0W.
bogdanm	82:6473597d706e	1377	#define BM_I2S_TCR5_W0W (0x001F0000U) //!< Bit mask for I2S_TCR5_W0W.
bogdanm	82:6473597d706e	1378	#define BS_I2S_TCR5_W0W (5U) //!< Bit field size in bits for I2S_TCR5_W0W.
bogdanm	82:6473597d706e	1379
bogdanm	82:6473597d706e	1380	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1381	//! @brief Read current value of the I2S_TCR5_W0W field.
bogdanm	82:6473597d706e	1382	#define BR_I2S_TCR5_W0W(x) (HW_I2S_TCR5(x).B.W0W)
bogdanm	82:6473597d706e	1383	#endif
bogdanm	82:6473597d706e	1384
bogdanm	82:6473597d706e	1385	//! @brief Format value for bitfield I2S_TCR5_W0W.
bogdanm	82:6473597d706e	1386	#define BF_I2S_TCR5_W0W(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_W0W), uint32_t) & BM_I2S_TCR5_W0W)
bogdanm	82:6473597d706e	1387
bogdanm	82:6473597d706e	1388	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1389	//! @brief Set the W0W field to a new value.
bogdanm	82:6473597d706e	1390	#define BW_I2S_TCR5_W0W(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_W0W) \| BF_I2S_TCR5_W0W(v)))
bogdanm	82:6473597d706e	1391	#endif
bogdanm	82:6473597d706e	1392	//@}
bogdanm	82:6473597d706e	1393
bogdanm	82:6473597d706e	1394	/*!
bogdanm	82:6473597d706e	1395	* @name Register I2S_TCR5, field WNW[28:24] (RW)
bogdanm	82:6473597d706e	1396	*
bogdanm	82:6473597d706e	1397	* Configures the number of bits in each word, for each word except the first in
bogdanm	82:6473597d706e	1398	* the frame. The value written must be one less than the number of bits per
bogdanm	82:6473597d706e	1399	* word. Word width of less than 8 bits is not supported.
bogdanm	82:6473597d706e	1400	*/
bogdanm	82:6473597d706e	1401	//@{
bogdanm	82:6473597d706e	1402	#define BP_I2S_TCR5_WNW (24U) //!< Bit position for I2S_TCR5_WNW.
bogdanm	82:6473597d706e	1403	#define BM_I2S_TCR5_WNW (0x1F000000U) //!< Bit mask for I2S_TCR5_WNW.
bogdanm	82:6473597d706e	1404	#define BS_I2S_TCR5_WNW (5U) //!< Bit field size in bits for I2S_TCR5_WNW.
bogdanm	82:6473597d706e	1405
bogdanm	82:6473597d706e	1406	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1407	//! @brief Read current value of the I2S_TCR5_WNW field.
bogdanm	82:6473597d706e	1408	#define BR_I2S_TCR5_WNW(x) (HW_I2S_TCR5(x).B.WNW)
bogdanm	82:6473597d706e	1409	#endif
bogdanm	82:6473597d706e	1410
bogdanm	82:6473597d706e	1411	//! @brief Format value for bitfield I2S_TCR5_WNW.
bogdanm	82:6473597d706e	1412	#define BF_I2S_TCR5_WNW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_WNW), uint32_t) & BM_I2S_TCR5_WNW)
bogdanm	82:6473597d706e	1413
bogdanm	82:6473597d706e	1414	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1415	//! @brief Set the WNW field to a new value.
bogdanm	82:6473597d706e	1416	#define BW_I2S_TCR5_WNW(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_WNW) \| BF_I2S_TCR5_WNW(v)))
bogdanm	82:6473597d706e	1417	#endif
bogdanm	82:6473597d706e	1418	//@}
bogdanm	82:6473597d706e	1419
bogdanm	82:6473597d706e	1420	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1421	// HW_I2S_TDRn - SAI Transmit Data Register
bogdanm	82:6473597d706e	1422	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1423
bogdanm	82:6473597d706e	1424	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1425	/*!
bogdanm	82:6473597d706e	1426	* @brief HW_I2S_TDRn - SAI Transmit Data Register (WORZ)
bogdanm	82:6473597d706e	1427	*
bogdanm	82:6473597d706e	1428	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1429	*/
bogdanm	82:6473597d706e	1430	typedef union _hw_i2s_tdrn
bogdanm	82:6473597d706e	1431	{
bogdanm	82:6473597d706e	1432	uint32_t U;
bogdanm	82:6473597d706e	1433	struct _hw_i2s_tdrn_bitfields
bogdanm	82:6473597d706e	1434	{
bogdanm	82:6473597d706e	1435	uint32_t TDR : 32; //!< [31:0] Transmit Data Register
bogdanm	82:6473597d706e	1436	} B;
bogdanm	82:6473597d706e	1437	} hw_i2s_tdrn_t;
bogdanm	82:6473597d706e	1438	#endif
bogdanm	82:6473597d706e	1439
bogdanm	82:6473597d706e	1440	/*!
bogdanm	82:6473597d706e	1441	* @name Constants and macros for entire I2S_TDRn register
bogdanm	82:6473597d706e	1442	*/
bogdanm	82:6473597d706e	1443	//@{
bogdanm	82:6473597d706e	1444	#define HW_I2S_TDRn_COUNT (2U)
bogdanm	82:6473597d706e	1445
bogdanm	82:6473597d706e	1446	#define HW_I2S_TDRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0x20U + (0x4U * n))
bogdanm	82:6473597d706e	1447
bogdanm	82:6473597d706e	1448	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1449	#define HW_I2S_TDRn(x, n) ((__O hw_i2s_tdrn_t ) HW_I2S_TDRn_ADDR(x, n))
bogdanm	82:6473597d706e	1450	#define HW_I2S_TDRn_RD(x, n) (HW_I2S_TDRn(x, n).U)
bogdanm	82:6473597d706e	1451	#define HW_I2S_TDRn_WR(x, n, v) (HW_I2S_TDRn(x, n).U = (v))
bogdanm	82:6473597d706e	1452	#endif
bogdanm	82:6473597d706e	1453	//@}
bogdanm	82:6473597d706e	1454
bogdanm	82:6473597d706e	1455	/*
bogdanm	82:6473597d706e	1456	* Constants & macros for individual I2S_TDRn bitfields
bogdanm	82:6473597d706e	1457	*/
bogdanm	82:6473597d706e	1458
bogdanm	82:6473597d706e	1459	/*!
bogdanm	82:6473597d706e	1460	* @name Register I2S_TDRn, field TDR[31:0] (WORZ)
bogdanm	82:6473597d706e	1461	*
bogdanm	82:6473597d706e	1462	* The corresponding TCR3[TCE] bit must be set before accessing the channel's
bogdanm	82:6473597d706e	1463	* transmit data register. Writes to this register when the transmit FIFO is not
bogdanm	82:6473597d706e	1464	* full will push the data written into the transmit data FIFO. Writes to this
bogdanm	82:6473597d706e	1465	* register when the transmit FIFO is full are ignored.
bogdanm	82:6473597d706e	1466	*/
bogdanm	82:6473597d706e	1467	//@{
bogdanm	82:6473597d706e	1468	#define BP_I2S_TDRn_TDR (0U) //!< Bit position for I2S_TDRn_TDR.
bogdanm	82:6473597d706e	1469	#define BM_I2S_TDRn_TDR (0xFFFFFFFFU) //!< Bit mask for I2S_TDRn_TDR.
bogdanm	82:6473597d706e	1470	#define BS_I2S_TDRn_TDR (32U) //!< Bit field size in bits for I2S_TDRn_TDR.
bogdanm	82:6473597d706e	1471
bogdanm	82:6473597d706e	1472	//! @brief Format value for bitfield I2S_TDRn_TDR.
bogdanm	82:6473597d706e	1473	#define BF_I2S_TDRn_TDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TDRn_TDR), uint32_t) & BM_I2S_TDRn_TDR)
bogdanm	82:6473597d706e	1474
bogdanm	82:6473597d706e	1475	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1476	//! @brief Set the TDR field to a new value.
bogdanm	82:6473597d706e	1477	#define BW_I2S_TDRn_TDR(x, n, v) (HW_I2S_TDRn_WR(x, n, v))
bogdanm	82:6473597d706e	1478	#endif
bogdanm	82:6473597d706e	1479	//@}
bogdanm	82:6473597d706e	1480
bogdanm	82:6473597d706e	1481	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1482	// HW_I2S_TFRn - SAI Transmit FIFO Register
bogdanm	82:6473597d706e	1483	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1484
bogdanm	82:6473597d706e	1485	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1486	/*!
bogdanm	82:6473597d706e	1487	* @brief HW_I2S_TFRn - SAI Transmit FIFO Register (RO)
bogdanm	82:6473597d706e	1488	*
bogdanm	82:6473597d706e	1489	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1490	*
bogdanm	82:6473597d706e	1491	* The MSB of the read and write pointers is used to distinguish between FIFO
bogdanm	82:6473597d706e	1492	* full and empty conditions. If the read and write pointers are identical, then
bogdanm	82:6473597d706e	1493	* the FIFO is empty. If the read and write pointers are identical except for the
bogdanm	82:6473597d706e	1494	* MSB, then the FIFO is full.
bogdanm	82:6473597d706e	1495	*/
bogdanm	82:6473597d706e	1496	typedef union _hw_i2s_tfrn
bogdanm	82:6473597d706e	1497	{
bogdanm	82:6473597d706e	1498	uint32_t U;
bogdanm	82:6473597d706e	1499	struct _hw_i2s_tfrn_bitfields
bogdanm	82:6473597d706e	1500	{
bogdanm	82:6473597d706e	1501	uint32_t RFP : 4; //!< [3:0] Read FIFO Pointer
bogdanm	82:6473597d706e	1502	uint32_t RESERVED0 : 12; //!< [15:4]
bogdanm	82:6473597d706e	1503	uint32_t WFP : 4; //!< [19:16] Write FIFO Pointer
bogdanm	82:6473597d706e	1504	uint32_t RESERVED1 : 12; //!< [31:20]
bogdanm	82:6473597d706e	1505	} B;
bogdanm	82:6473597d706e	1506	} hw_i2s_tfrn_t;
bogdanm	82:6473597d706e	1507	#endif
bogdanm	82:6473597d706e	1508
bogdanm	82:6473597d706e	1509	/*!
bogdanm	82:6473597d706e	1510	* @name Constants and macros for entire I2S_TFRn register
bogdanm	82:6473597d706e	1511	*/
bogdanm	82:6473597d706e	1512	//@{
bogdanm	82:6473597d706e	1513	#define HW_I2S_TFRn_COUNT (2U)
bogdanm	82:6473597d706e	1514
bogdanm	82:6473597d706e	1515	#define HW_I2S_TFRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0x40U + (0x4U * n))
bogdanm	82:6473597d706e	1516
bogdanm	82:6473597d706e	1517	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1518	#define HW_I2S_TFRn(x, n) ((__I hw_i2s_tfrn_t ) HW_I2S_TFRn_ADDR(x, n))
bogdanm	82:6473597d706e	1519	#define HW_I2S_TFRn_RD(x, n) (HW_I2S_TFRn(x, n).U)
bogdanm	82:6473597d706e	1520	#endif
bogdanm	82:6473597d706e	1521	//@}
bogdanm	82:6473597d706e	1522
bogdanm	82:6473597d706e	1523	/*
bogdanm	82:6473597d706e	1524	* Constants & macros for individual I2S_TFRn bitfields
bogdanm	82:6473597d706e	1525	*/
bogdanm	82:6473597d706e	1526
bogdanm	82:6473597d706e	1527	/*!
bogdanm	82:6473597d706e	1528	* @name Register I2S_TFRn, field RFP[3:0] (RO)
bogdanm	82:6473597d706e	1529	*
bogdanm	82:6473597d706e	1530	* FIFO read pointer for transmit data channel.
bogdanm	82:6473597d706e	1531	*/
bogdanm	82:6473597d706e	1532	//@{
bogdanm	82:6473597d706e	1533	#define BP_I2S_TFRn_RFP (0U) //!< Bit position for I2S_TFRn_RFP.
bogdanm	82:6473597d706e	1534	#define BM_I2S_TFRn_RFP (0x0000000FU) //!< Bit mask for I2S_TFRn_RFP.
bogdanm	82:6473597d706e	1535	#define BS_I2S_TFRn_RFP (4U) //!< Bit field size in bits for I2S_TFRn_RFP.
bogdanm	82:6473597d706e	1536
bogdanm	82:6473597d706e	1537	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1538	//! @brief Read current value of the I2S_TFRn_RFP field.
bogdanm	82:6473597d706e	1539	#define BR_I2S_TFRn_RFP(x, n) (HW_I2S_TFRn(x, n).B.RFP)
bogdanm	82:6473597d706e	1540	#endif
bogdanm	82:6473597d706e	1541	//@}
bogdanm	82:6473597d706e	1542
bogdanm	82:6473597d706e	1543	/*!
bogdanm	82:6473597d706e	1544	* @name Register I2S_TFRn, field WFP[19:16] (RO)
bogdanm	82:6473597d706e	1545	*
bogdanm	82:6473597d706e	1546	* FIFO write pointer for transmit data channel.
bogdanm	82:6473597d706e	1547	*/
bogdanm	82:6473597d706e	1548	//@{
bogdanm	82:6473597d706e	1549	#define BP_I2S_TFRn_WFP (16U) //!< Bit position for I2S_TFRn_WFP.
bogdanm	82:6473597d706e	1550	#define BM_I2S_TFRn_WFP (0x000F0000U) //!< Bit mask for I2S_TFRn_WFP.
bogdanm	82:6473597d706e	1551	#define BS_I2S_TFRn_WFP (4U) //!< Bit field size in bits for I2S_TFRn_WFP.
bogdanm	82:6473597d706e	1552
bogdanm	82:6473597d706e	1553	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1554	//! @brief Read current value of the I2S_TFRn_WFP field.
bogdanm	82:6473597d706e	1555	#define BR_I2S_TFRn_WFP(x, n) (HW_I2S_TFRn(x, n).B.WFP)
bogdanm	82:6473597d706e	1556	#endif
bogdanm	82:6473597d706e	1557	//@}
bogdanm	82:6473597d706e	1558
bogdanm	82:6473597d706e	1559	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1560	// HW_I2S_TMR - SAI Transmit Mask Register
bogdanm	82:6473597d706e	1561	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1562
bogdanm	82:6473597d706e	1563	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1564	/*!
bogdanm	82:6473597d706e	1565	* @brief HW_I2S_TMR - SAI Transmit Mask Register (RW)
bogdanm	82:6473597d706e	1566	*
bogdanm	82:6473597d706e	1567	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1568	*
bogdanm	82:6473597d706e	1569	* This register is double-buffered and updates: When TCSR[TE] is first set At
bogdanm	82:6473597d706e	1570	* the end of each frame. This allows the masked words in each frame to change
bogdanm	82:6473597d706e	1571	* from frame to frame.
bogdanm	82:6473597d706e	1572	*/
bogdanm	82:6473597d706e	1573	typedef union _hw_i2s_tmr
bogdanm	82:6473597d706e	1574	{
bogdanm	82:6473597d706e	1575	uint32_t U;
bogdanm	82:6473597d706e	1576	struct _hw_i2s_tmr_bitfields
bogdanm	82:6473597d706e	1577	{
bogdanm	82:6473597d706e	1578	uint32_t TWM : 32; //!< [31:0] Transmit Word Mask
bogdanm	82:6473597d706e	1579	} B;
bogdanm	82:6473597d706e	1580	} hw_i2s_tmr_t;
bogdanm	82:6473597d706e	1581	#endif
bogdanm	82:6473597d706e	1582
bogdanm	82:6473597d706e	1583	/*!
bogdanm	82:6473597d706e	1584	* @name Constants and macros for entire I2S_TMR register
bogdanm	82:6473597d706e	1585	*/
bogdanm	82:6473597d706e	1586	//@{
bogdanm	82:6473597d706e	1587	#define HW_I2S_TMR_ADDR(x) (REGS_I2S_BASE(x) + 0x60U)
bogdanm	82:6473597d706e	1588
bogdanm	82:6473597d706e	1589	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1590	#define HW_I2S_TMR(x) ((__IO hw_i2s_tmr_t ) HW_I2S_TMR_ADDR(x))
bogdanm	82:6473597d706e	1591	#define HW_I2S_TMR_RD(x) (HW_I2S_TMR(x).U)
bogdanm	82:6473597d706e	1592	#define HW_I2S_TMR_WR(x, v) (HW_I2S_TMR(x).U = (v))
bogdanm	82:6473597d706e	1593	#define HW_I2S_TMR_SET(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) \| (v)))
bogdanm	82:6473597d706e	1594	#define HW_I2S_TMR_CLR(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1595	#define HW_I2S_TMR_TOG(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1596	#endif
bogdanm	82:6473597d706e	1597	//@}
bogdanm	82:6473597d706e	1598
bogdanm	82:6473597d706e	1599	/*
bogdanm	82:6473597d706e	1600	* Constants & macros for individual I2S_TMR bitfields
bogdanm	82:6473597d706e	1601	*/
bogdanm	82:6473597d706e	1602
bogdanm	82:6473597d706e	1603	/*!
bogdanm	82:6473597d706e	1604	* @name Register I2S_TMR, field TWM[31:0] (RW)
bogdanm	82:6473597d706e	1605	*
bogdanm	82:6473597d706e	1606	* Configures whether the transmit word is masked (transmit data pin tristated
bogdanm	82:6473597d706e	1607	* and transmit data not read from FIFO) for the corresponding word in the frame.
bogdanm	82:6473597d706e	1608	*
bogdanm	82:6473597d706e	1609	* Values:
bogdanm	82:6473597d706e	1610	* - 0 - Word N is enabled.
bogdanm	82:6473597d706e	1611	* - 1 - Word N is masked. The transmit data pins are tri-stated when masked.
bogdanm	82:6473597d706e	1612	*/
bogdanm	82:6473597d706e	1613	//@{
bogdanm	82:6473597d706e	1614	#define BP_I2S_TMR_TWM (0U) //!< Bit position for I2S_TMR_TWM.
bogdanm	82:6473597d706e	1615	#define BM_I2S_TMR_TWM (0xFFFFFFFFU) //!< Bit mask for I2S_TMR_TWM.
bogdanm	82:6473597d706e	1616	#define BS_I2S_TMR_TWM (32U) //!< Bit field size in bits for I2S_TMR_TWM.
bogdanm	82:6473597d706e	1617
bogdanm	82:6473597d706e	1618	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1619	//! @brief Read current value of the I2S_TMR_TWM field.
bogdanm	82:6473597d706e	1620	#define BR_I2S_TMR_TWM(x) (HW_I2S_TMR(x).U)
bogdanm	82:6473597d706e	1621	#endif
bogdanm	82:6473597d706e	1622
bogdanm	82:6473597d706e	1623	//! @brief Format value for bitfield I2S_TMR_TWM.
bogdanm	82:6473597d706e	1624	#define BF_I2S_TMR_TWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TMR_TWM), uint32_t) & BM_I2S_TMR_TWM)
bogdanm	82:6473597d706e	1625
bogdanm	82:6473597d706e	1626	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1627	//! @brief Set the TWM field to a new value.
bogdanm	82:6473597d706e	1628	#define BW_I2S_TMR_TWM(x, v) (HW_I2S_TMR_WR(x, v))
bogdanm	82:6473597d706e	1629	#endif
bogdanm	82:6473597d706e	1630	//@}
bogdanm	82:6473597d706e	1631
bogdanm	82:6473597d706e	1632	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1633	// HW_I2S_RCSR - SAI Receive Control Register
bogdanm	82:6473597d706e	1634	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1635
bogdanm	82:6473597d706e	1636	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1637	/*!
bogdanm	82:6473597d706e	1638	* @brief HW_I2S_RCSR - SAI Receive Control Register (RW)
bogdanm	82:6473597d706e	1639	*
bogdanm	82:6473597d706e	1640	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1641	*/
bogdanm	82:6473597d706e	1642	typedef union _hw_i2s_rcsr
bogdanm	82:6473597d706e	1643	{
bogdanm	82:6473597d706e	1644	uint32_t U;
bogdanm	82:6473597d706e	1645	struct _hw_i2s_rcsr_bitfields
bogdanm	82:6473597d706e	1646	{
bogdanm	82:6473597d706e	1647	uint32_t FRDE : 1; //!< [0] FIFO Request DMA Enable
bogdanm	82:6473597d706e	1648	uint32_t FWDE : 1; //!< [1] FIFO Warning DMA Enable
bogdanm	82:6473597d706e	1649	uint32_t RESERVED0 : 6; //!< [7:2]
bogdanm	82:6473597d706e	1650	uint32_t FRIE : 1; //!< [8] FIFO Request Interrupt Enable
bogdanm	82:6473597d706e	1651	uint32_t FWIE : 1; //!< [9] FIFO Warning Interrupt Enable
bogdanm	82:6473597d706e	1652	uint32_t FEIE : 1; //!< [10] FIFO Error Interrupt Enable
bogdanm	82:6473597d706e	1653	uint32_t SEIE : 1; //!< [11] Sync Error Interrupt Enable
bogdanm	82:6473597d706e	1654	uint32_t WSIE : 1; //!< [12] Word Start Interrupt Enable
bogdanm	82:6473597d706e	1655	uint32_t RESERVED1 : 3; //!< [15:13]
bogdanm	82:6473597d706e	1656	uint32_t FRF : 1; //!< [16] FIFO Request Flag
bogdanm	82:6473597d706e	1657	uint32_t FWF : 1; //!< [17] FIFO Warning Flag
bogdanm	82:6473597d706e	1658	uint32_t FEF : 1; //!< [18] FIFO Error Flag
bogdanm	82:6473597d706e	1659	uint32_t SEF : 1; //!< [19] Sync Error Flag
bogdanm	82:6473597d706e	1660	uint32_t WSF : 1; //!< [20] Word Start Flag
bogdanm	82:6473597d706e	1661	uint32_t RESERVED2 : 3; //!< [23:21]
bogdanm	82:6473597d706e	1662	uint32_t SR : 1; //!< [24] Software Reset
bogdanm	82:6473597d706e	1663	uint32_t FR : 1; //!< [25] FIFO Reset
bogdanm	82:6473597d706e	1664	uint32_t RESERVED3 : 2; //!< [27:26]
bogdanm	82:6473597d706e	1665	uint32_t BCE : 1; //!< [28] Bit Clock Enable
bogdanm	82:6473597d706e	1666	uint32_t DBGE : 1; //!< [29] Debug Enable
bogdanm	82:6473597d706e	1667	uint32_t STOPE : 1; //!< [30] Stop Enable
bogdanm	82:6473597d706e	1668	uint32_t RE : 1; //!< [31] Receiver Enable
bogdanm	82:6473597d706e	1669	} B;
bogdanm	82:6473597d706e	1670	} hw_i2s_rcsr_t;
bogdanm	82:6473597d706e	1671	#endif
bogdanm	82:6473597d706e	1672
bogdanm	82:6473597d706e	1673	/*!
bogdanm	82:6473597d706e	1674	* @name Constants and macros for entire I2S_RCSR register
bogdanm	82:6473597d706e	1675	*/
bogdanm	82:6473597d706e	1676	//@{
bogdanm	82:6473597d706e	1677	#define HW_I2S_RCSR_ADDR(x) (REGS_I2S_BASE(x) + 0x80U)
bogdanm	82:6473597d706e	1678
bogdanm	82:6473597d706e	1679	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1680	#define HW_I2S_RCSR(x) ((__IO hw_i2s_rcsr_t ) HW_I2S_RCSR_ADDR(x))
bogdanm	82:6473597d706e	1681	#define HW_I2S_RCSR_RD(x) (HW_I2S_RCSR(x).U)
bogdanm	82:6473597d706e	1682	#define HW_I2S_RCSR_WR(x, v) (HW_I2S_RCSR(x).U = (v))
bogdanm	82:6473597d706e	1683	#define HW_I2S_RCSR_SET(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) \| (v)))
bogdanm	82:6473597d706e	1684	#define HW_I2S_RCSR_CLR(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1685	#define HW_I2S_RCSR_TOG(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1686	#endif
bogdanm	82:6473597d706e	1687	//@}
bogdanm	82:6473597d706e	1688
bogdanm	82:6473597d706e	1689	/*
bogdanm	82:6473597d706e	1690	* Constants & macros for individual I2S_RCSR bitfields
bogdanm	82:6473597d706e	1691	*/
bogdanm	82:6473597d706e	1692
bogdanm	82:6473597d706e	1693	/*!
bogdanm	82:6473597d706e	1694	* @name Register I2S_RCSR, field FRDE[0] (RW)
bogdanm	82:6473597d706e	1695	*
bogdanm	82:6473597d706e	1696	* Enables/disables DMA requests.
bogdanm	82:6473597d706e	1697	*
bogdanm	82:6473597d706e	1698	* Values:
bogdanm	82:6473597d706e	1699	* - 0 - Disables the DMA request.
bogdanm	82:6473597d706e	1700	* - 1 - Enables the DMA request.
bogdanm	82:6473597d706e	1701	*/
bogdanm	82:6473597d706e	1702	//@{
bogdanm	82:6473597d706e	1703	#define BP_I2S_RCSR_FRDE (0U) //!< Bit position for I2S_RCSR_FRDE.
bogdanm	82:6473597d706e	1704	#define BM_I2S_RCSR_FRDE (0x00000001U) //!< Bit mask for I2S_RCSR_FRDE.
bogdanm	82:6473597d706e	1705	#define BS_I2S_RCSR_FRDE (1U) //!< Bit field size in bits for I2S_RCSR_FRDE.
bogdanm	82:6473597d706e	1706
bogdanm	82:6473597d706e	1707	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1708	//! @brief Read current value of the I2S_RCSR_FRDE field.
bogdanm	82:6473597d706e	1709	#define BR_I2S_RCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE))
bogdanm	82:6473597d706e	1710	#endif
bogdanm	82:6473597d706e	1711
bogdanm	82:6473597d706e	1712	//! @brief Format value for bitfield I2S_RCSR_FRDE.
bogdanm	82:6473597d706e	1713	#define BF_I2S_RCSR_FRDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FRDE), uint32_t) & BM_I2S_RCSR_FRDE)
bogdanm	82:6473597d706e	1714
bogdanm	82:6473597d706e	1715	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1716	//! @brief Set the FRDE field to a new value.
bogdanm	82:6473597d706e	1717	#define BW_I2S_RCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE) = (v))
bogdanm	82:6473597d706e	1718	#endif
bogdanm	82:6473597d706e	1719	//@}
bogdanm	82:6473597d706e	1720
bogdanm	82:6473597d706e	1721	/*!
bogdanm	82:6473597d706e	1722	* @name Register I2S_RCSR, field FWDE[1] (RW)
bogdanm	82:6473597d706e	1723	*
bogdanm	82:6473597d706e	1724	* Enables/disables DMA requests.
bogdanm	82:6473597d706e	1725	*
bogdanm	82:6473597d706e	1726	* Values:
bogdanm	82:6473597d706e	1727	* - 0 - Disables the DMA request.
bogdanm	82:6473597d706e	1728	* - 1 - Enables the DMA request.
bogdanm	82:6473597d706e	1729	*/
bogdanm	82:6473597d706e	1730	//@{
bogdanm	82:6473597d706e	1731	#define BP_I2S_RCSR_FWDE (1U) //!< Bit position for I2S_RCSR_FWDE.
bogdanm	82:6473597d706e	1732	#define BM_I2S_RCSR_FWDE (0x00000002U) //!< Bit mask for I2S_RCSR_FWDE.
bogdanm	82:6473597d706e	1733	#define BS_I2S_RCSR_FWDE (1U) //!< Bit field size in bits for I2S_RCSR_FWDE.
bogdanm	82:6473597d706e	1734
bogdanm	82:6473597d706e	1735	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1736	//! @brief Read current value of the I2S_RCSR_FWDE field.
bogdanm	82:6473597d706e	1737	#define BR_I2S_RCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE))
bogdanm	82:6473597d706e	1738	#endif
bogdanm	82:6473597d706e	1739
bogdanm	82:6473597d706e	1740	//! @brief Format value for bitfield I2S_RCSR_FWDE.
bogdanm	82:6473597d706e	1741	#define BF_I2S_RCSR_FWDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FWDE), uint32_t) & BM_I2S_RCSR_FWDE)
bogdanm	82:6473597d706e	1742
bogdanm	82:6473597d706e	1743	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1744	//! @brief Set the FWDE field to a new value.
bogdanm	82:6473597d706e	1745	#define BW_I2S_RCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE) = (v))
bogdanm	82:6473597d706e	1746	#endif
bogdanm	82:6473597d706e	1747	//@}
bogdanm	82:6473597d706e	1748
bogdanm	82:6473597d706e	1749	/*!
bogdanm	82:6473597d706e	1750	* @name Register I2S_RCSR, field FRIE[8] (RW)
bogdanm	82:6473597d706e	1751	*
bogdanm	82:6473597d706e	1752	* Enables/disables FIFO request interrupts.
bogdanm	82:6473597d706e	1753	*
bogdanm	82:6473597d706e	1754	* Values:
bogdanm	82:6473597d706e	1755	* - 0 - Disables the interrupt.
bogdanm	82:6473597d706e	1756	* - 1 - Enables the interrupt.
bogdanm	82:6473597d706e	1757	*/
bogdanm	82:6473597d706e	1758	//@{
bogdanm	82:6473597d706e	1759	#define BP_I2S_RCSR_FRIE (8U) //!< Bit position for I2S_RCSR_FRIE.
bogdanm	82:6473597d706e	1760	#define BM_I2S_RCSR_FRIE (0x00000100U) //!< Bit mask for I2S_RCSR_FRIE.
bogdanm	82:6473597d706e	1761	#define BS_I2S_RCSR_FRIE (1U) //!< Bit field size in bits for I2S_RCSR_FRIE.
bogdanm	82:6473597d706e	1762
bogdanm	82:6473597d706e	1763	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1764	//! @brief Read current value of the I2S_RCSR_FRIE field.
bogdanm	82:6473597d706e	1765	#define BR_I2S_RCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE))
bogdanm	82:6473597d706e	1766	#endif
bogdanm	82:6473597d706e	1767
bogdanm	82:6473597d706e	1768	//! @brief Format value for bitfield I2S_RCSR_FRIE.
bogdanm	82:6473597d706e	1769	#define BF_I2S_RCSR_FRIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FRIE), uint32_t) & BM_I2S_RCSR_FRIE)
bogdanm	82:6473597d706e	1770
bogdanm	82:6473597d706e	1771	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1772	//! @brief Set the FRIE field to a new value.
bogdanm	82:6473597d706e	1773	#define BW_I2S_RCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE) = (v))
bogdanm	82:6473597d706e	1774	#endif
bogdanm	82:6473597d706e	1775	//@}
bogdanm	82:6473597d706e	1776
bogdanm	82:6473597d706e	1777	/*!
bogdanm	82:6473597d706e	1778	* @name Register I2S_RCSR, field FWIE[9] (RW)
bogdanm	82:6473597d706e	1779	*
bogdanm	82:6473597d706e	1780	* Enables/disables FIFO warning interrupts.
bogdanm	82:6473597d706e	1781	*
bogdanm	82:6473597d706e	1782	* Values:
bogdanm	82:6473597d706e	1783	* - 0 - Disables the interrupt.
bogdanm	82:6473597d706e	1784	* - 1 - Enables the interrupt.
bogdanm	82:6473597d706e	1785	*/
bogdanm	82:6473597d706e	1786	//@{
bogdanm	82:6473597d706e	1787	#define BP_I2S_RCSR_FWIE (9U) //!< Bit position for I2S_RCSR_FWIE.
bogdanm	82:6473597d706e	1788	#define BM_I2S_RCSR_FWIE (0x00000200U) //!< Bit mask for I2S_RCSR_FWIE.
bogdanm	82:6473597d706e	1789	#define BS_I2S_RCSR_FWIE (1U) //!< Bit field size in bits for I2S_RCSR_FWIE.
bogdanm	82:6473597d706e	1790
bogdanm	82:6473597d706e	1791	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1792	//! @brief Read current value of the I2S_RCSR_FWIE field.
bogdanm	82:6473597d706e	1793	#define BR_I2S_RCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE))
bogdanm	82:6473597d706e	1794	#endif
bogdanm	82:6473597d706e	1795
bogdanm	82:6473597d706e	1796	//! @brief Format value for bitfield I2S_RCSR_FWIE.
bogdanm	82:6473597d706e	1797	#define BF_I2S_RCSR_FWIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FWIE), uint32_t) & BM_I2S_RCSR_FWIE)
bogdanm	82:6473597d706e	1798
bogdanm	82:6473597d706e	1799	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1800	//! @brief Set the FWIE field to a new value.
bogdanm	82:6473597d706e	1801	#define BW_I2S_RCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE) = (v))
bogdanm	82:6473597d706e	1802	#endif
bogdanm	82:6473597d706e	1803	//@}
bogdanm	82:6473597d706e	1804
bogdanm	82:6473597d706e	1805	/*!
bogdanm	82:6473597d706e	1806	* @name Register I2S_RCSR, field FEIE[10] (RW)
bogdanm	82:6473597d706e	1807	*
bogdanm	82:6473597d706e	1808	* Enables/disables FIFO error interrupts.
bogdanm	82:6473597d706e	1809	*
bogdanm	82:6473597d706e	1810	* Values:
bogdanm	82:6473597d706e	1811	* - 0 - Disables the interrupt.
bogdanm	82:6473597d706e	1812	* - 1 - Enables the interrupt.
bogdanm	82:6473597d706e	1813	*/
bogdanm	82:6473597d706e	1814	//@{
bogdanm	82:6473597d706e	1815	#define BP_I2S_RCSR_FEIE (10U) //!< Bit position for I2S_RCSR_FEIE.
bogdanm	82:6473597d706e	1816	#define BM_I2S_RCSR_FEIE (0x00000400U) //!< Bit mask for I2S_RCSR_FEIE.
bogdanm	82:6473597d706e	1817	#define BS_I2S_RCSR_FEIE (1U) //!< Bit field size in bits for I2S_RCSR_FEIE.
bogdanm	82:6473597d706e	1818
bogdanm	82:6473597d706e	1819	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1820	//! @brief Read current value of the I2S_RCSR_FEIE field.
bogdanm	82:6473597d706e	1821	#define BR_I2S_RCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE))
bogdanm	82:6473597d706e	1822	#endif
bogdanm	82:6473597d706e	1823
bogdanm	82:6473597d706e	1824	//! @brief Format value for bitfield I2S_RCSR_FEIE.
bogdanm	82:6473597d706e	1825	#define BF_I2S_RCSR_FEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FEIE), uint32_t) & BM_I2S_RCSR_FEIE)
bogdanm	82:6473597d706e	1826
bogdanm	82:6473597d706e	1827	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1828	//! @brief Set the FEIE field to a new value.
bogdanm	82:6473597d706e	1829	#define BW_I2S_RCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE) = (v))
bogdanm	82:6473597d706e	1830	#endif
bogdanm	82:6473597d706e	1831	//@}
bogdanm	82:6473597d706e	1832
bogdanm	82:6473597d706e	1833	/*!
bogdanm	82:6473597d706e	1834	* @name Register I2S_RCSR, field SEIE[11] (RW)
bogdanm	82:6473597d706e	1835	*
bogdanm	82:6473597d706e	1836	* Enables/disables sync error interrupts.
bogdanm	82:6473597d706e	1837	*
bogdanm	82:6473597d706e	1838	* Values:
bogdanm	82:6473597d706e	1839	* - 0 - Disables interrupt.
bogdanm	82:6473597d706e	1840	* - 1 - Enables interrupt.
bogdanm	82:6473597d706e	1841	*/
bogdanm	82:6473597d706e	1842	//@{
bogdanm	82:6473597d706e	1843	#define BP_I2S_RCSR_SEIE (11U) //!< Bit position for I2S_RCSR_SEIE.
bogdanm	82:6473597d706e	1844	#define BM_I2S_RCSR_SEIE (0x00000800U) //!< Bit mask for I2S_RCSR_SEIE.
bogdanm	82:6473597d706e	1845	#define BS_I2S_RCSR_SEIE (1U) //!< Bit field size in bits for I2S_RCSR_SEIE.
bogdanm	82:6473597d706e	1846
bogdanm	82:6473597d706e	1847	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1848	//! @brief Read current value of the I2S_RCSR_SEIE field.
bogdanm	82:6473597d706e	1849	#define BR_I2S_RCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE))
bogdanm	82:6473597d706e	1850	#endif
bogdanm	82:6473597d706e	1851
bogdanm	82:6473597d706e	1852	//! @brief Format value for bitfield I2S_RCSR_SEIE.
bogdanm	82:6473597d706e	1853	#define BF_I2S_RCSR_SEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SEIE), uint32_t) & BM_I2S_RCSR_SEIE)
bogdanm	82:6473597d706e	1854
bogdanm	82:6473597d706e	1855	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1856	//! @brief Set the SEIE field to a new value.
bogdanm	82:6473597d706e	1857	#define BW_I2S_RCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE) = (v))
bogdanm	82:6473597d706e	1858	#endif
bogdanm	82:6473597d706e	1859	//@}
bogdanm	82:6473597d706e	1860
bogdanm	82:6473597d706e	1861	/*!
bogdanm	82:6473597d706e	1862	* @name Register I2S_RCSR, field WSIE[12] (RW)
bogdanm	82:6473597d706e	1863	*
bogdanm	82:6473597d706e	1864	* Enables/disables word start interrupts.
bogdanm	82:6473597d706e	1865	*
bogdanm	82:6473597d706e	1866	* Values:
bogdanm	82:6473597d706e	1867	* - 0 - Disables interrupt.
bogdanm	82:6473597d706e	1868	* - 1 - Enables interrupt.
bogdanm	82:6473597d706e	1869	*/
bogdanm	82:6473597d706e	1870	//@{
bogdanm	82:6473597d706e	1871	#define BP_I2S_RCSR_WSIE (12U) //!< Bit position for I2S_RCSR_WSIE.
bogdanm	82:6473597d706e	1872	#define BM_I2S_RCSR_WSIE (0x00001000U) //!< Bit mask for I2S_RCSR_WSIE.
bogdanm	82:6473597d706e	1873	#define BS_I2S_RCSR_WSIE (1U) //!< Bit field size in bits for I2S_RCSR_WSIE.
bogdanm	82:6473597d706e	1874
bogdanm	82:6473597d706e	1875	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1876	//! @brief Read current value of the I2S_RCSR_WSIE field.
bogdanm	82:6473597d706e	1877	#define BR_I2S_RCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE))
bogdanm	82:6473597d706e	1878	#endif
bogdanm	82:6473597d706e	1879
bogdanm	82:6473597d706e	1880	//! @brief Format value for bitfield I2S_RCSR_WSIE.
bogdanm	82:6473597d706e	1881	#define BF_I2S_RCSR_WSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_WSIE), uint32_t) & BM_I2S_RCSR_WSIE)
bogdanm	82:6473597d706e	1882
bogdanm	82:6473597d706e	1883	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1884	//! @brief Set the WSIE field to a new value.
bogdanm	82:6473597d706e	1885	#define BW_I2S_RCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE) = (v))
bogdanm	82:6473597d706e	1886	#endif
bogdanm	82:6473597d706e	1887	//@}
bogdanm	82:6473597d706e	1888
bogdanm	82:6473597d706e	1889	/*!
bogdanm	82:6473597d706e	1890	* @name Register I2S_RCSR, field FRF[16] (RO)
bogdanm	82:6473597d706e	1891	*
bogdanm	82:6473597d706e	1892	* Indicates that the number of words in an enabled receive channel FIFO is
bogdanm	82:6473597d706e	1893	* greater than the receive FIFO watermark.
bogdanm	82:6473597d706e	1894	*
bogdanm	82:6473597d706e	1895	* Values:
bogdanm	82:6473597d706e	1896	* - 0 - Receive FIFO watermark not reached.
bogdanm	82:6473597d706e	1897	* - 1 - Receive FIFO watermark has been reached.
bogdanm	82:6473597d706e	1898	*/
bogdanm	82:6473597d706e	1899	//@{
bogdanm	82:6473597d706e	1900	#define BP_I2S_RCSR_FRF (16U) //!< Bit position for I2S_RCSR_FRF.
bogdanm	82:6473597d706e	1901	#define BM_I2S_RCSR_FRF (0x00010000U) //!< Bit mask for I2S_RCSR_FRF.
bogdanm	82:6473597d706e	1902	#define BS_I2S_RCSR_FRF (1U) //!< Bit field size in bits for I2S_RCSR_FRF.
bogdanm	82:6473597d706e	1903
bogdanm	82:6473597d706e	1904	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1905	//! @brief Read current value of the I2S_RCSR_FRF field.
bogdanm	82:6473597d706e	1906	#define BR_I2S_RCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRF))
bogdanm	82:6473597d706e	1907	#endif
bogdanm	82:6473597d706e	1908	//@}
bogdanm	82:6473597d706e	1909
bogdanm	82:6473597d706e	1910	/*!
bogdanm	82:6473597d706e	1911	* @name Register I2S_RCSR, field FWF[17] (RO)
bogdanm	82:6473597d706e	1912	*
bogdanm	82:6473597d706e	1913	* Indicates that an enabled receive FIFO is full.
bogdanm	82:6473597d706e	1914	*
bogdanm	82:6473597d706e	1915	* Values:
bogdanm	82:6473597d706e	1916	* - 0 - No enabled receive FIFO is full.
bogdanm	82:6473597d706e	1917	* - 1 - Enabled receive FIFO is full.
bogdanm	82:6473597d706e	1918	*/
bogdanm	82:6473597d706e	1919	//@{
bogdanm	82:6473597d706e	1920	#define BP_I2S_RCSR_FWF (17U) //!< Bit position for I2S_RCSR_FWF.
bogdanm	82:6473597d706e	1921	#define BM_I2S_RCSR_FWF (0x00020000U) //!< Bit mask for I2S_RCSR_FWF.
bogdanm	82:6473597d706e	1922	#define BS_I2S_RCSR_FWF (1U) //!< Bit field size in bits for I2S_RCSR_FWF.
bogdanm	82:6473597d706e	1923
bogdanm	82:6473597d706e	1924	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1925	//! @brief Read current value of the I2S_RCSR_FWF field.
bogdanm	82:6473597d706e	1926	#define BR_I2S_RCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWF))
bogdanm	82:6473597d706e	1927	#endif
bogdanm	82:6473597d706e	1928	//@}
bogdanm	82:6473597d706e	1929
bogdanm	82:6473597d706e	1930	/*!
bogdanm	82:6473597d706e	1931	* @name Register I2S_RCSR, field FEF[18] (W1C)
bogdanm	82:6473597d706e	1932	*
bogdanm	82:6473597d706e	1933	* Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
bogdanm	82:6473597d706e	1934	* this field to clear this flag.
bogdanm	82:6473597d706e	1935	*
bogdanm	82:6473597d706e	1936	* Values:
bogdanm	82:6473597d706e	1937	* - 0 - Receive overflow not detected.
bogdanm	82:6473597d706e	1938	* - 1 - Receive overflow detected.
bogdanm	82:6473597d706e	1939	*/
bogdanm	82:6473597d706e	1940	//@{
bogdanm	82:6473597d706e	1941	#define BP_I2S_RCSR_FEF (18U) //!< Bit position for I2S_RCSR_FEF.
bogdanm	82:6473597d706e	1942	#define BM_I2S_RCSR_FEF (0x00040000U) //!< Bit mask for I2S_RCSR_FEF.
bogdanm	82:6473597d706e	1943	#define BS_I2S_RCSR_FEF (1U) //!< Bit field size in bits for I2S_RCSR_FEF.
bogdanm	82:6473597d706e	1944
bogdanm	82:6473597d706e	1945	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1946	//! @brief Read current value of the I2S_RCSR_FEF field.
bogdanm	82:6473597d706e	1947	#define BR_I2S_RCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF))
bogdanm	82:6473597d706e	1948	#endif
bogdanm	82:6473597d706e	1949
bogdanm	82:6473597d706e	1950	//! @brief Format value for bitfield I2S_RCSR_FEF.
bogdanm	82:6473597d706e	1951	#define BF_I2S_RCSR_FEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FEF), uint32_t) & BM_I2S_RCSR_FEF)
bogdanm	82:6473597d706e	1952
bogdanm	82:6473597d706e	1953	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1954	//! @brief Set the FEF field to a new value.
bogdanm	82:6473597d706e	1955	#define BW_I2S_RCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF) = (v))
bogdanm	82:6473597d706e	1956	#endif
bogdanm	82:6473597d706e	1957	//@}
bogdanm	82:6473597d706e	1958
bogdanm	82:6473597d706e	1959	/*!
bogdanm	82:6473597d706e	1960	* @name Register I2S_RCSR, field SEF[19] (W1C)
bogdanm	82:6473597d706e	1961	*
bogdanm	82:6473597d706e	1962	* Indicates that an error in the externally-generated frame sync has been
bogdanm	82:6473597d706e	1963	* detected. Write a logic 1 to this field to clear this flag.
bogdanm	82:6473597d706e	1964	*
bogdanm	82:6473597d706e	1965	* Values:
bogdanm	82:6473597d706e	1966	* - 0 - Sync error not detected.
bogdanm	82:6473597d706e	1967	* - 1 - Frame sync error detected.
bogdanm	82:6473597d706e	1968	*/
bogdanm	82:6473597d706e	1969	//@{
bogdanm	82:6473597d706e	1970	#define BP_I2S_RCSR_SEF (19U) //!< Bit position for I2S_RCSR_SEF.
bogdanm	82:6473597d706e	1971	#define BM_I2S_RCSR_SEF (0x00080000U) //!< Bit mask for I2S_RCSR_SEF.
bogdanm	82:6473597d706e	1972	#define BS_I2S_RCSR_SEF (1U) //!< Bit field size in bits for I2S_RCSR_SEF.
bogdanm	82:6473597d706e	1973
bogdanm	82:6473597d706e	1974	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1975	//! @brief Read current value of the I2S_RCSR_SEF field.
bogdanm	82:6473597d706e	1976	#define BR_I2S_RCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF))
bogdanm	82:6473597d706e	1977	#endif
bogdanm	82:6473597d706e	1978
bogdanm	82:6473597d706e	1979	//! @brief Format value for bitfield I2S_RCSR_SEF.
bogdanm	82:6473597d706e	1980	#define BF_I2S_RCSR_SEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SEF), uint32_t) & BM_I2S_RCSR_SEF)
bogdanm	82:6473597d706e	1981
bogdanm	82:6473597d706e	1982	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1983	//! @brief Set the SEF field to a new value.
bogdanm	82:6473597d706e	1984	#define BW_I2S_RCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF) = (v))
bogdanm	82:6473597d706e	1985	#endif
bogdanm	82:6473597d706e	1986	//@}
bogdanm	82:6473597d706e	1987
bogdanm	82:6473597d706e	1988	/*!
bogdanm	82:6473597d706e	1989	* @name Register I2S_RCSR, field WSF[20] (W1C)
bogdanm	82:6473597d706e	1990	*
bogdanm	82:6473597d706e	1991	* Indicates that the start of the configured word has been detected. Write a
bogdanm	82:6473597d706e	1992	* logic 1 to this field to clear this flag.
bogdanm	82:6473597d706e	1993	*
bogdanm	82:6473597d706e	1994	* Values:
bogdanm	82:6473597d706e	1995	* - 0 - Start of word not detected.
bogdanm	82:6473597d706e	1996	* - 1 - Start of word detected.
bogdanm	82:6473597d706e	1997	*/
bogdanm	82:6473597d706e	1998	//@{
bogdanm	82:6473597d706e	1999	#define BP_I2S_RCSR_WSF (20U) //!< Bit position for I2S_RCSR_WSF.
bogdanm	82:6473597d706e	2000	#define BM_I2S_RCSR_WSF (0x00100000U) //!< Bit mask for I2S_RCSR_WSF.
bogdanm	82:6473597d706e	2001	#define BS_I2S_RCSR_WSF (1U) //!< Bit field size in bits for I2S_RCSR_WSF.
bogdanm	82:6473597d706e	2002
bogdanm	82:6473597d706e	2003	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2004	//! @brief Read current value of the I2S_RCSR_WSF field.
bogdanm	82:6473597d706e	2005	#define BR_I2S_RCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF))
bogdanm	82:6473597d706e	2006	#endif
bogdanm	82:6473597d706e	2007
bogdanm	82:6473597d706e	2008	//! @brief Format value for bitfield I2S_RCSR_WSF.
bogdanm	82:6473597d706e	2009	#define BF_I2S_RCSR_WSF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_WSF), uint32_t) & BM_I2S_RCSR_WSF)
bogdanm	82:6473597d706e	2010
bogdanm	82:6473597d706e	2011	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2012	//! @brief Set the WSF field to a new value.
bogdanm	82:6473597d706e	2013	#define BW_I2S_RCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF) = (v))
bogdanm	82:6473597d706e	2014	#endif
bogdanm	82:6473597d706e	2015	//@}
bogdanm	82:6473597d706e	2016
bogdanm	82:6473597d706e	2017	/*!
bogdanm	82:6473597d706e	2018	* @name Register I2S_RCSR, field SR[24] (RW)
bogdanm	82:6473597d706e	2019	*
bogdanm	82:6473597d706e	2020	* Resets the internal receiver logic including the FIFO pointers.
bogdanm	82:6473597d706e	2021	* Software-visible registers are not affected, except for the status registers.
bogdanm	82:6473597d706e	2022	*
bogdanm	82:6473597d706e	2023	* Values:
bogdanm	82:6473597d706e	2024	* - 0 - No effect.
bogdanm	82:6473597d706e	2025	* - 1 - Software reset.
bogdanm	82:6473597d706e	2026	*/
bogdanm	82:6473597d706e	2027	//@{
bogdanm	82:6473597d706e	2028	#define BP_I2S_RCSR_SR (24U) //!< Bit position for I2S_RCSR_SR.
bogdanm	82:6473597d706e	2029	#define BM_I2S_RCSR_SR (0x01000000U) //!< Bit mask for I2S_RCSR_SR.
bogdanm	82:6473597d706e	2030	#define BS_I2S_RCSR_SR (1U) //!< Bit field size in bits for I2S_RCSR_SR.
bogdanm	82:6473597d706e	2031
bogdanm	82:6473597d706e	2032	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2033	//! @brief Read current value of the I2S_RCSR_SR field.
bogdanm	82:6473597d706e	2034	#define BR_I2S_RCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR))
bogdanm	82:6473597d706e	2035	#endif
bogdanm	82:6473597d706e	2036
bogdanm	82:6473597d706e	2037	//! @brief Format value for bitfield I2S_RCSR_SR.
bogdanm	82:6473597d706e	2038	#define BF_I2S_RCSR_SR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SR), uint32_t) & BM_I2S_RCSR_SR)
bogdanm	82:6473597d706e	2039
bogdanm	82:6473597d706e	2040	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2041	//! @brief Set the SR field to a new value.
bogdanm	82:6473597d706e	2042	#define BW_I2S_RCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR) = (v))
bogdanm	82:6473597d706e	2043	#endif
bogdanm	82:6473597d706e	2044	//@}
bogdanm	82:6473597d706e	2045
bogdanm	82:6473597d706e	2046	/*!
bogdanm	82:6473597d706e	2047	* @name Register I2S_RCSR, field FR[25] (WORZ)
bogdanm	82:6473597d706e	2048	*
bogdanm	82:6473597d706e	2049	* Resets the FIFO pointers. Reading this field will always return zero. FIFO
bogdanm	82:6473597d706e	2050	* pointers should only be reset when the receiver is disabled or the FIFO error
bogdanm	82:6473597d706e	2051	* flag is set.
bogdanm	82:6473597d706e	2052	*
bogdanm	82:6473597d706e	2053	* Values:
bogdanm	82:6473597d706e	2054	* - 0 - No effect.
bogdanm	82:6473597d706e	2055	* - 1 - FIFO reset.
bogdanm	82:6473597d706e	2056	*/
bogdanm	82:6473597d706e	2057	//@{
bogdanm	82:6473597d706e	2058	#define BP_I2S_RCSR_FR (25U) //!< Bit position for I2S_RCSR_FR.
bogdanm	82:6473597d706e	2059	#define BM_I2S_RCSR_FR (0x02000000U) //!< Bit mask for I2S_RCSR_FR.
bogdanm	82:6473597d706e	2060	#define BS_I2S_RCSR_FR (1U) //!< Bit field size in bits for I2S_RCSR_FR.
bogdanm	82:6473597d706e	2061
bogdanm	82:6473597d706e	2062	//! @brief Format value for bitfield I2S_RCSR_FR.
bogdanm	82:6473597d706e	2063	#define BF_I2S_RCSR_FR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FR), uint32_t) & BM_I2S_RCSR_FR)
bogdanm	82:6473597d706e	2064
bogdanm	82:6473597d706e	2065	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2066	//! @brief Set the FR field to a new value.
bogdanm	82:6473597d706e	2067	#define BW_I2S_RCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FR) = (v))
bogdanm	82:6473597d706e	2068	#endif
bogdanm	82:6473597d706e	2069	//@}
bogdanm	82:6473597d706e	2070
bogdanm	82:6473597d706e	2071	/*!
bogdanm	82:6473597d706e	2072	* @name Register I2S_RCSR, field BCE[28] (RW)
bogdanm	82:6473597d706e	2073	*
bogdanm	82:6473597d706e	2074	* Enables the receive bit clock, separately from RE. This field is
bogdanm	82:6473597d706e	2075	* automatically set whenever RE is set. When software clears this field, the receive bit
bogdanm	82:6473597d706e	2076	* clock remains enabled, and this field remains set, until the end of the current
bogdanm	82:6473597d706e	2077	* frame.
bogdanm	82:6473597d706e	2078	*
bogdanm	82:6473597d706e	2079	* Values:
bogdanm	82:6473597d706e	2080	* - 0 - Receive bit clock is disabled.
bogdanm	82:6473597d706e	2081	* - 1 - Receive bit clock is enabled.
bogdanm	82:6473597d706e	2082	*/
bogdanm	82:6473597d706e	2083	//@{
bogdanm	82:6473597d706e	2084	#define BP_I2S_RCSR_BCE (28U) //!< Bit position for I2S_RCSR_BCE.
bogdanm	82:6473597d706e	2085	#define BM_I2S_RCSR_BCE (0x10000000U) //!< Bit mask for I2S_RCSR_BCE.
bogdanm	82:6473597d706e	2086	#define BS_I2S_RCSR_BCE (1U) //!< Bit field size in bits for I2S_RCSR_BCE.
bogdanm	82:6473597d706e	2087
bogdanm	82:6473597d706e	2088	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2089	//! @brief Read current value of the I2S_RCSR_BCE field.
bogdanm	82:6473597d706e	2090	#define BR_I2S_RCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE))
bogdanm	82:6473597d706e	2091	#endif
bogdanm	82:6473597d706e	2092
bogdanm	82:6473597d706e	2093	//! @brief Format value for bitfield I2S_RCSR_BCE.
bogdanm	82:6473597d706e	2094	#define BF_I2S_RCSR_BCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_BCE), uint32_t) & BM_I2S_RCSR_BCE)
bogdanm	82:6473597d706e	2095
bogdanm	82:6473597d706e	2096	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2097	//! @brief Set the BCE field to a new value.
bogdanm	82:6473597d706e	2098	#define BW_I2S_RCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE) = (v))
bogdanm	82:6473597d706e	2099	#endif
bogdanm	82:6473597d706e	2100	//@}
bogdanm	82:6473597d706e	2101
bogdanm	82:6473597d706e	2102	/*!
bogdanm	82:6473597d706e	2103	* @name Register I2S_RCSR, field DBGE[29] (RW)
bogdanm	82:6473597d706e	2104	*
bogdanm	82:6473597d706e	2105	* Enables/disables receiver operation in Debug mode. The receive bit clock is
bogdanm	82:6473597d706e	2106	* not affected by Debug mode.
bogdanm	82:6473597d706e	2107	*
bogdanm	82:6473597d706e	2108	* Values:
bogdanm	82:6473597d706e	2109	* - 0 - Receiver is disabled in Debug mode, after completing the current frame.
bogdanm	82:6473597d706e	2110	* - 1 - Receiver is enabled in Debug mode.
bogdanm	82:6473597d706e	2111	*/
bogdanm	82:6473597d706e	2112	//@{
bogdanm	82:6473597d706e	2113	#define BP_I2S_RCSR_DBGE (29U) //!< Bit position for I2S_RCSR_DBGE.
bogdanm	82:6473597d706e	2114	#define BM_I2S_RCSR_DBGE (0x20000000U) //!< Bit mask for I2S_RCSR_DBGE.
bogdanm	82:6473597d706e	2115	#define BS_I2S_RCSR_DBGE (1U) //!< Bit field size in bits for I2S_RCSR_DBGE.
bogdanm	82:6473597d706e	2116
bogdanm	82:6473597d706e	2117	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2118	//! @brief Read current value of the I2S_RCSR_DBGE field.
bogdanm	82:6473597d706e	2119	#define BR_I2S_RCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE))
bogdanm	82:6473597d706e	2120	#endif
bogdanm	82:6473597d706e	2121
bogdanm	82:6473597d706e	2122	//! @brief Format value for bitfield I2S_RCSR_DBGE.
bogdanm	82:6473597d706e	2123	#define BF_I2S_RCSR_DBGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_DBGE), uint32_t) & BM_I2S_RCSR_DBGE)
bogdanm	82:6473597d706e	2124
bogdanm	82:6473597d706e	2125	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2126	//! @brief Set the DBGE field to a new value.
bogdanm	82:6473597d706e	2127	#define BW_I2S_RCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE) = (v))
bogdanm	82:6473597d706e	2128	#endif
bogdanm	82:6473597d706e	2129	//@}
bogdanm	82:6473597d706e	2130
bogdanm	82:6473597d706e	2131	/*!
bogdanm	82:6473597d706e	2132	* @name Register I2S_RCSR, field STOPE[30] (RW)
bogdanm	82:6473597d706e	2133	*
bogdanm	82:6473597d706e	2134	* Configures receiver operation in Stop mode. This bit is ignored and the
bogdanm	82:6473597d706e	2135	* receiver is disabled in all low-leakage stop modes.
bogdanm	82:6473597d706e	2136	*
bogdanm	82:6473597d706e	2137	* Values:
bogdanm	82:6473597d706e	2138	* - 0 - Receiver disabled in Stop mode.
bogdanm	82:6473597d706e	2139	* - 1 - Receiver enabled in Stop mode.
bogdanm	82:6473597d706e	2140	*/
bogdanm	82:6473597d706e	2141	//@{
bogdanm	82:6473597d706e	2142	#define BP_I2S_RCSR_STOPE (30U) //!< Bit position for I2S_RCSR_STOPE.
bogdanm	82:6473597d706e	2143	#define BM_I2S_RCSR_STOPE (0x40000000U) //!< Bit mask for I2S_RCSR_STOPE.
bogdanm	82:6473597d706e	2144	#define BS_I2S_RCSR_STOPE (1U) //!< Bit field size in bits for I2S_RCSR_STOPE.
bogdanm	82:6473597d706e	2145
bogdanm	82:6473597d706e	2146	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2147	//! @brief Read current value of the I2S_RCSR_STOPE field.
bogdanm	82:6473597d706e	2148	#define BR_I2S_RCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE))
bogdanm	82:6473597d706e	2149	#endif
bogdanm	82:6473597d706e	2150
bogdanm	82:6473597d706e	2151	//! @brief Format value for bitfield I2S_RCSR_STOPE.
bogdanm	82:6473597d706e	2152	#define BF_I2S_RCSR_STOPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_STOPE), uint32_t) & BM_I2S_RCSR_STOPE)
bogdanm	82:6473597d706e	2153
bogdanm	82:6473597d706e	2154	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2155	//! @brief Set the STOPE field to a new value.
bogdanm	82:6473597d706e	2156	#define BW_I2S_RCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE) = (v))
bogdanm	82:6473597d706e	2157	#endif
bogdanm	82:6473597d706e	2158	//@}
bogdanm	82:6473597d706e	2159
bogdanm	82:6473597d706e	2160	/*!
bogdanm	82:6473597d706e	2161	* @name Register I2S_RCSR, field RE[31] (RW)
bogdanm	82:6473597d706e	2162	*
bogdanm	82:6473597d706e	2163	* Enables/disables the receiver. When software clears this field, the receiver
bogdanm	82:6473597d706e	2164	* remains enabled, and this bit remains set, until the end of the current frame.
bogdanm	82:6473597d706e	2165	*
bogdanm	82:6473597d706e	2166	* Values:
bogdanm	82:6473597d706e	2167	* - 0 - Receiver is disabled.
bogdanm	82:6473597d706e	2168	* - 1 - Receiver is enabled, or receiver has been disabled and has not yet
bogdanm	82:6473597d706e	2169	* reached end of frame.
bogdanm	82:6473597d706e	2170	*/
bogdanm	82:6473597d706e	2171	//@{
bogdanm	82:6473597d706e	2172	#define BP_I2S_RCSR_RE (31U) //!< Bit position for I2S_RCSR_RE.
bogdanm	82:6473597d706e	2173	#define BM_I2S_RCSR_RE (0x80000000U) //!< Bit mask for I2S_RCSR_RE.
bogdanm	82:6473597d706e	2174	#define BS_I2S_RCSR_RE (1U) //!< Bit field size in bits for I2S_RCSR_RE.
bogdanm	82:6473597d706e	2175
bogdanm	82:6473597d706e	2176	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2177	//! @brief Read current value of the I2S_RCSR_RE field.
bogdanm	82:6473597d706e	2178	#define BR_I2S_RCSR_RE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE))
bogdanm	82:6473597d706e	2179	#endif
bogdanm	82:6473597d706e	2180
bogdanm	82:6473597d706e	2181	//! @brief Format value for bitfield I2S_RCSR_RE.
bogdanm	82:6473597d706e	2182	#define BF_I2S_RCSR_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_RE), uint32_t) & BM_I2S_RCSR_RE)
bogdanm	82:6473597d706e	2183
bogdanm	82:6473597d706e	2184	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2185	//! @brief Set the RE field to a new value.
bogdanm	82:6473597d706e	2186	#define BW_I2S_RCSR_RE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE) = (v))
bogdanm	82:6473597d706e	2187	#endif
bogdanm	82:6473597d706e	2188	//@}
bogdanm	82:6473597d706e	2189
bogdanm	82:6473597d706e	2190	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2191	// HW_I2S_RCR1 - SAI Receive Configuration 1 Register
bogdanm	82:6473597d706e	2192	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2193
bogdanm	82:6473597d706e	2194	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2195	/*!
bogdanm	82:6473597d706e	2196	* @brief HW_I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
bogdanm	82:6473597d706e	2197	*
bogdanm	82:6473597d706e	2198	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2199	*/
bogdanm	82:6473597d706e	2200	typedef union _hw_i2s_rcr1
bogdanm	82:6473597d706e	2201	{
bogdanm	82:6473597d706e	2202	uint32_t U;
bogdanm	82:6473597d706e	2203	struct _hw_i2s_rcr1_bitfields
bogdanm	82:6473597d706e	2204	{
bogdanm	82:6473597d706e	2205	uint32_t RFW : 3; //!< [2:0] Receive FIFO Watermark
bogdanm	82:6473597d706e	2206	uint32_t RESERVED0 : 29; //!< [31:3]
bogdanm	82:6473597d706e	2207	} B;
bogdanm	82:6473597d706e	2208	} hw_i2s_rcr1_t;
bogdanm	82:6473597d706e	2209	#endif
bogdanm	82:6473597d706e	2210
bogdanm	82:6473597d706e	2211	/*!
bogdanm	82:6473597d706e	2212	* @name Constants and macros for entire I2S_RCR1 register
bogdanm	82:6473597d706e	2213	*/
bogdanm	82:6473597d706e	2214	//@{
bogdanm	82:6473597d706e	2215	#define HW_I2S_RCR1_ADDR(x) (REGS_I2S_BASE(x) + 0x84U)
bogdanm	82:6473597d706e	2216
bogdanm	82:6473597d706e	2217	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2218	#define HW_I2S_RCR1(x) ((__IO hw_i2s_rcr1_t ) HW_I2S_RCR1_ADDR(x))
bogdanm	82:6473597d706e	2219	#define HW_I2S_RCR1_RD(x) (HW_I2S_RCR1(x).U)
bogdanm	82:6473597d706e	2220	#define HW_I2S_RCR1_WR(x, v) (HW_I2S_RCR1(x).U = (v))
bogdanm	82:6473597d706e	2221	#define HW_I2S_RCR1_SET(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) \| (v)))
bogdanm	82:6473597d706e	2222	#define HW_I2S_RCR1_CLR(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2223	#define HW_I2S_RCR1_TOG(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2224	#endif
bogdanm	82:6473597d706e	2225	//@}
bogdanm	82:6473597d706e	2226
bogdanm	82:6473597d706e	2227	/*
bogdanm	82:6473597d706e	2228	* Constants & macros for individual I2S_RCR1 bitfields
bogdanm	82:6473597d706e	2229	*/
bogdanm	82:6473597d706e	2230
bogdanm	82:6473597d706e	2231	/*!
bogdanm	82:6473597d706e	2232	* @name Register I2S_RCR1, field RFW[2:0] (RW)
bogdanm	82:6473597d706e	2233	*
bogdanm	82:6473597d706e	2234	* Configures the watermark level for all enabled receiver channels.
bogdanm	82:6473597d706e	2235	*/
bogdanm	82:6473597d706e	2236	//@{
bogdanm	82:6473597d706e	2237	#define BP_I2S_RCR1_RFW (0U) //!< Bit position for I2S_RCR1_RFW.
bogdanm	82:6473597d706e	2238	#define BM_I2S_RCR1_RFW (0x00000007U) //!< Bit mask for I2S_RCR1_RFW.
bogdanm	82:6473597d706e	2239	#define BS_I2S_RCR1_RFW (3U) //!< Bit field size in bits for I2S_RCR1_RFW.
bogdanm	82:6473597d706e	2240
bogdanm	82:6473597d706e	2241	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2242	//! @brief Read current value of the I2S_RCR1_RFW field.
bogdanm	82:6473597d706e	2243	#define BR_I2S_RCR1_RFW(x) (HW_I2S_RCR1(x).B.RFW)
bogdanm	82:6473597d706e	2244	#endif
bogdanm	82:6473597d706e	2245
bogdanm	82:6473597d706e	2246	//! @brief Format value for bitfield I2S_RCR1_RFW.
bogdanm	82:6473597d706e	2247	#define BF_I2S_RCR1_RFW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR1_RFW), uint32_t) & BM_I2S_RCR1_RFW)
bogdanm	82:6473597d706e	2248
bogdanm	82:6473597d706e	2249	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2250	//! @brief Set the RFW field to a new value.
bogdanm	82:6473597d706e	2251	#define BW_I2S_RCR1_RFW(x, v) (HW_I2S_RCR1_WR(x, (HW_I2S_RCR1_RD(x) & ~BM_I2S_RCR1_RFW) \| BF_I2S_RCR1_RFW(v)))
bogdanm	82:6473597d706e	2252	#endif
bogdanm	82:6473597d706e	2253	//@}
bogdanm	82:6473597d706e	2254
bogdanm	82:6473597d706e	2255	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2256	// HW_I2S_RCR2 - SAI Receive Configuration 2 Register
bogdanm	82:6473597d706e	2257	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2258
bogdanm	82:6473597d706e	2259	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2260	/*!
bogdanm	82:6473597d706e	2261	* @brief HW_I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
bogdanm	82:6473597d706e	2262	*
bogdanm	82:6473597d706e	2263	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2264	*
bogdanm	82:6473597d706e	2265	* This register must not be altered when RCSR[RE] is set.
bogdanm	82:6473597d706e	2266	*/
bogdanm	82:6473597d706e	2267	typedef union _hw_i2s_rcr2
bogdanm	82:6473597d706e	2268	{
bogdanm	82:6473597d706e	2269	uint32_t U;
bogdanm	82:6473597d706e	2270	struct _hw_i2s_rcr2_bitfields
bogdanm	82:6473597d706e	2271	{
bogdanm	82:6473597d706e	2272	uint32_t DIV : 8; //!< [7:0] Bit Clock Divide
bogdanm	82:6473597d706e	2273	uint32_t RESERVED0 : 16; //!< [23:8]
bogdanm	82:6473597d706e	2274	uint32_t BCD : 1; //!< [24] Bit Clock Direction
bogdanm	82:6473597d706e	2275	uint32_t BCP : 1; //!< [25] Bit Clock Polarity
bogdanm	82:6473597d706e	2276	uint32_t MSEL : 2; //!< [27:26] MCLK Select
bogdanm	82:6473597d706e	2277	uint32_t BCI : 1; //!< [28] Bit Clock Input
bogdanm	82:6473597d706e	2278	uint32_t BCS : 1; //!< [29] Bit Clock Swap
bogdanm	82:6473597d706e	2279	uint32_t SYNC : 2; //!< [31:30] Synchronous Mode
bogdanm	82:6473597d706e	2280	} B;
bogdanm	82:6473597d706e	2281	} hw_i2s_rcr2_t;
bogdanm	82:6473597d706e	2282	#endif
bogdanm	82:6473597d706e	2283
bogdanm	82:6473597d706e	2284	/*!
bogdanm	82:6473597d706e	2285	* @name Constants and macros for entire I2S_RCR2 register
bogdanm	82:6473597d706e	2286	*/
bogdanm	82:6473597d706e	2287	//@{
bogdanm	82:6473597d706e	2288	#define HW_I2S_RCR2_ADDR(x) (REGS_I2S_BASE(x) + 0x88U)
bogdanm	82:6473597d706e	2289
bogdanm	82:6473597d706e	2290	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2291	#define HW_I2S_RCR2(x) ((__IO hw_i2s_rcr2_t ) HW_I2S_RCR2_ADDR(x))
bogdanm	82:6473597d706e	2292	#define HW_I2S_RCR2_RD(x) (HW_I2S_RCR2(x).U)
bogdanm	82:6473597d706e	2293	#define HW_I2S_RCR2_WR(x, v) (HW_I2S_RCR2(x).U = (v))
bogdanm	82:6473597d706e	2294	#define HW_I2S_RCR2_SET(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) \| (v)))
bogdanm	82:6473597d706e	2295	#define HW_I2S_RCR2_CLR(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2296	#define HW_I2S_RCR2_TOG(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2297	#endif
bogdanm	82:6473597d706e	2298	//@}
bogdanm	82:6473597d706e	2299
bogdanm	82:6473597d706e	2300	/*
bogdanm	82:6473597d706e	2301	* Constants & macros for individual I2S_RCR2 bitfields
bogdanm	82:6473597d706e	2302	*/
bogdanm	82:6473597d706e	2303
bogdanm	82:6473597d706e	2304	/*!
bogdanm	82:6473597d706e	2305	* @name Register I2S_RCR2, field DIV[7:0] (RW)
bogdanm	82:6473597d706e	2306	*
bogdanm	82:6473597d706e	2307	* Divides down the audio master clock to generate the bit clock when configured
bogdanm	82:6473597d706e	2308	* for an internal bit clock. The division value is (DIV + 1) * 2.
bogdanm	82:6473597d706e	2309	*/
bogdanm	82:6473597d706e	2310	//@{
bogdanm	82:6473597d706e	2311	#define BP_I2S_RCR2_DIV (0U) //!< Bit position for I2S_RCR2_DIV.
bogdanm	82:6473597d706e	2312	#define BM_I2S_RCR2_DIV (0x000000FFU) //!< Bit mask for I2S_RCR2_DIV.
bogdanm	82:6473597d706e	2313	#define BS_I2S_RCR2_DIV (8U) //!< Bit field size in bits for I2S_RCR2_DIV.
bogdanm	82:6473597d706e	2314
bogdanm	82:6473597d706e	2315	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2316	//! @brief Read current value of the I2S_RCR2_DIV field.
bogdanm	82:6473597d706e	2317	#define BR_I2S_RCR2_DIV(x) (HW_I2S_RCR2(x).B.DIV)
bogdanm	82:6473597d706e	2318	#endif
bogdanm	82:6473597d706e	2319
bogdanm	82:6473597d706e	2320	//! @brief Format value for bitfield I2S_RCR2_DIV.
bogdanm	82:6473597d706e	2321	#define BF_I2S_RCR2_DIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_DIV), uint32_t) & BM_I2S_RCR2_DIV)
bogdanm	82:6473597d706e	2322
bogdanm	82:6473597d706e	2323	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2324	//! @brief Set the DIV field to a new value.
bogdanm	82:6473597d706e	2325	#define BW_I2S_RCR2_DIV(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_DIV) \| BF_I2S_RCR2_DIV(v)))
bogdanm	82:6473597d706e	2326	#endif
bogdanm	82:6473597d706e	2327	//@}
bogdanm	82:6473597d706e	2328
bogdanm	82:6473597d706e	2329	/*!
bogdanm	82:6473597d706e	2330	* @name Register I2S_RCR2, field BCD[24] (RW)
bogdanm	82:6473597d706e	2331	*
bogdanm	82:6473597d706e	2332	* Configures the direction of the bit clock.
bogdanm	82:6473597d706e	2333	*
bogdanm	82:6473597d706e	2334	* Values:
bogdanm	82:6473597d706e	2335	* - 0 - Bit clock is generated externally in Slave mode.
bogdanm	82:6473597d706e	2336	* - 1 - Bit clock is generated internally in Master mode.
bogdanm	82:6473597d706e	2337	*/
bogdanm	82:6473597d706e	2338	//@{
bogdanm	82:6473597d706e	2339	#define BP_I2S_RCR2_BCD (24U) //!< Bit position for I2S_RCR2_BCD.
bogdanm	82:6473597d706e	2340	#define BM_I2S_RCR2_BCD (0x01000000U) //!< Bit mask for I2S_RCR2_BCD.
bogdanm	82:6473597d706e	2341	#define BS_I2S_RCR2_BCD (1U) //!< Bit field size in bits for I2S_RCR2_BCD.
bogdanm	82:6473597d706e	2342
bogdanm	82:6473597d706e	2343	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2344	//! @brief Read current value of the I2S_RCR2_BCD field.
bogdanm	82:6473597d706e	2345	#define BR_I2S_RCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD))
bogdanm	82:6473597d706e	2346	#endif
bogdanm	82:6473597d706e	2347
bogdanm	82:6473597d706e	2348	//! @brief Format value for bitfield I2S_RCR2_BCD.
bogdanm	82:6473597d706e	2349	#define BF_I2S_RCR2_BCD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCD), uint32_t) & BM_I2S_RCR2_BCD)
bogdanm	82:6473597d706e	2350
bogdanm	82:6473597d706e	2351	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2352	//! @brief Set the BCD field to a new value.
bogdanm	82:6473597d706e	2353	#define BW_I2S_RCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD) = (v))
bogdanm	82:6473597d706e	2354	#endif
bogdanm	82:6473597d706e	2355	//@}
bogdanm	82:6473597d706e	2356
bogdanm	82:6473597d706e	2357	/*!
bogdanm	82:6473597d706e	2358	* @name Register I2S_RCR2, field BCP[25] (RW)
bogdanm	82:6473597d706e	2359	*
bogdanm	82:6473597d706e	2360	* Configures the polarity of the bit clock.
bogdanm	82:6473597d706e	2361	*
bogdanm	82:6473597d706e	2362	* Values:
bogdanm	82:6473597d706e	2363	* - 0 - Bit Clock is active high with drive outputs on rising edge and sample
bogdanm	82:6473597d706e	2364	* inputs on falling edge.
bogdanm	82:6473597d706e	2365	* - 1 - Bit Clock is active low with drive outputs on falling edge and sample
bogdanm	82:6473597d706e	2366	* inputs on rising edge.
bogdanm	82:6473597d706e	2367	*/
bogdanm	82:6473597d706e	2368	//@{
bogdanm	82:6473597d706e	2369	#define BP_I2S_RCR2_BCP (25U) //!< Bit position for I2S_RCR2_BCP.
bogdanm	82:6473597d706e	2370	#define BM_I2S_RCR2_BCP (0x02000000U) //!< Bit mask for I2S_RCR2_BCP.
bogdanm	82:6473597d706e	2371	#define BS_I2S_RCR2_BCP (1U) //!< Bit field size in bits for I2S_RCR2_BCP.
bogdanm	82:6473597d706e	2372
bogdanm	82:6473597d706e	2373	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2374	//! @brief Read current value of the I2S_RCR2_BCP field.
bogdanm	82:6473597d706e	2375	#define BR_I2S_RCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP))
bogdanm	82:6473597d706e	2376	#endif
bogdanm	82:6473597d706e	2377
bogdanm	82:6473597d706e	2378	//! @brief Format value for bitfield I2S_RCR2_BCP.
bogdanm	82:6473597d706e	2379	#define BF_I2S_RCR2_BCP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCP), uint32_t) & BM_I2S_RCR2_BCP)
bogdanm	82:6473597d706e	2380
bogdanm	82:6473597d706e	2381	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2382	//! @brief Set the BCP field to a new value.
bogdanm	82:6473597d706e	2383	#define BW_I2S_RCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP) = (v))
bogdanm	82:6473597d706e	2384	#endif
bogdanm	82:6473597d706e	2385	//@}
bogdanm	82:6473597d706e	2386
bogdanm	82:6473597d706e	2387	/*!
bogdanm	82:6473597d706e	2388	* @name Register I2S_RCR2, field MSEL[27:26] (RW)
bogdanm	82:6473597d706e	2389	*
bogdanm	82:6473597d706e	2390	* Selects the audio Master Clock option used to generate an internally
bogdanm	82:6473597d706e	2391	* generated bit clock. This field has no effect when configured for an externally
bogdanm	82:6473597d706e	2392	* generated bit clock. Depending on the device, some Master Clock options might not be
bogdanm	82:6473597d706e	2393	* available. See the chip configuration details for the availability and
bogdanm	82:6473597d706e	2394	* chip-specific meaning of each option.
bogdanm	82:6473597d706e	2395	*
bogdanm	82:6473597d706e	2396	* Values:
bogdanm	82:6473597d706e	2397	* - 00 - Bus Clock selected.
bogdanm	82:6473597d706e	2398	* - 01 - Master Clock (MCLK) 1 option selected.
bogdanm	82:6473597d706e	2399	* - 10 - Master Clock (MCLK) 2 option selected.
bogdanm	82:6473597d706e	2400	* - 11 - Master Clock (MCLK) 3 option selected.
bogdanm	82:6473597d706e	2401	*/
bogdanm	82:6473597d706e	2402	//@{
bogdanm	82:6473597d706e	2403	#define BP_I2S_RCR2_MSEL (26U) //!< Bit position for I2S_RCR2_MSEL.
bogdanm	82:6473597d706e	2404	#define BM_I2S_RCR2_MSEL (0x0C000000U) //!< Bit mask for I2S_RCR2_MSEL.
bogdanm	82:6473597d706e	2405	#define BS_I2S_RCR2_MSEL (2U) //!< Bit field size in bits for I2S_RCR2_MSEL.
bogdanm	82:6473597d706e	2406
bogdanm	82:6473597d706e	2407	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2408	//! @brief Read current value of the I2S_RCR2_MSEL field.
bogdanm	82:6473597d706e	2409	#define BR_I2S_RCR2_MSEL(x) (HW_I2S_RCR2(x).B.MSEL)
bogdanm	82:6473597d706e	2410	#endif
bogdanm	82:6473597d706e	2411
bogdanm	82:6473597d706e	2412	//! @brief Format value for bitfield I2S_RCR2_MSEL.
bogdanm	82:6473597d706e	2413	#define BF_I2S_RCR2_MSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_MSEL), uint32_t) & BM_I2S_RCR2_MSEL)
bogdanm	82:6473597d706e	2414
bogdanm	82:6473597d706e	2415	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2416	//! @brief Set the MSEL field to a new value.
bogdanm	82:6473597d706e	2417	#define BW_I2S_RCR2_MSEL(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_MSEL) \| BF_I2S_RCR2_MSEL(v)))
bogdanm	82:6473597d706e	2418	#endif
bogdanm	82:6473597d706e	2419	//@}
bogdanm	82:6473597d706e	2420
bogdanm	82:6473597d706e	2421	/*!
bogdanm	82:6473597d706e	2422	* @name Register I2S_RCR2, field BCI[28] (RW)
bogdanm	82:6473597d706e	2423	*
bogdanm	82:6473597d706e	2424	* When this field is set and using an internally generated bit clock in either
bogdanm	82:6473597d706e	2425	* synchronous or asynchronous mode, the bit clock actually used by the receiver
bogdanm	82:6473597d706e	2426	* is delayed by the pad output delay (the receiver is clocked by the pad input
bogdanm	82:6473597d706e	2427	* as if the clock was externally generated). This has the effect of decreasing
bogdanm	82:6473597d706e	2428	* the data input setup time, but increasing the data output valid time. The slave
bogdanm	82:6473597d706e	2429	* mode timing from the datasheet should be used for the receiver when this bit
bogdanm	82:6473597d706e	2430	* is set. In synchronous mode, this bit allows the receiver to use the slave mode
bogdanm	82:6473597d706e	2431	* timing from the datasheet, while the transmitter uses the master mode timing.
bogdanm	82:6473597d706e	2432	* This field has no effect when configured for an externally generated bit
bogdanm	82:6473597d706e	2433	* clock or when synchronous to another SAI peripheral .
bogdanm	82:6473597d706e	2434	*
bogdanm	82:6473597d706e	2435	* Values:
bogdanm	82:6473597d706e	2436	* - 0 - No effect.
bogdanm	82:6473597d706e	2437	* - 1 - Internal logic is clocked as if bit clock was externally generated.
bogdanm	82:6473597d706e	2438	*/
bogdanm	82:6473597d706e	2439	//@{
bogdanm	82:6473597d706e	2440	#define BP_I2S_RCR2_BCI (28U) //!< Bit position for I2S_RCR2_BCI.
bogdanm	82:6473597d706e	2441	#define BM_I2S_RCR2_BCI (0x10000000U) //!< Bit mask for I2S_RCR2_BCI.
bogdanm	82:6473597d706e	2442	#define BS_I2S_RCR2_BCI (1U) //!< Bit field size in bits for I2S_RCR2_BCI.
bogdanm	82:6473597d706e	2443
bogdanm	82:6473597d706e	2444	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2445	//! @brief Read current value of the I2S_RCR2_BCI field.
bogdanm	82:6473597d706e	2446	#define BR_I2S_RCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI))
bogdanm	82:6473597d706e	2447	#endif
bogdanm	82:6473597d706e	2448
bogdanm	82:6473597d706e	2449	//! @brief Format value for bitfield I2S_RCR2_BCI.
bogdanm	82:6473597d706e	2450	#define BF_I2S_RCR2_BCI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCI), uint32_t) & BM_I2S_RCR2_BCI)
bogdanm	82:6473597d706e	2451
bogdanm	82:6473597d706e	2452	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2453	//! @brief Set the BCI field to a new value.
bogdanm	82:6473597d706e	2454	#define BW_I2S_RCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI) = (v))
bogdanm	82:6473597d706e	2455	#endif
bogdanm	82:6473597d706e	2456	//@}
bogdanm	82:6473597d706e	2457
bogdanm	82:6473597d706e	2458	/*!
bogdanm	82:6473597d706e	2459	* @name Register I2S_RCR2, field BCS[29] (RW)
bogdanm	82:6473597d706e	2460	*
bogdanm	82:6473597d706e	2461	* This field swaps the bit clock used by the receiver. When the receiver is
bogdanm	82:6473597d706e	2462	* configured in asynchronous mode and this bit is set, the receiver is clocked by
bogdanm	82:6473597d706e	2463	* the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
bogdanm	82:6473597d706e	2464	* receiver to share the same bit clock, but the receiver continues to use the receiver
bogdanm	82:6473597d706e	2465	* frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
bogdanm	82:6473597d706e	2466	* mode, the transmitter BCS field and receiver BCS field must be set to the same
bogdanm	82:6473597d706e	2467	* value. When both are set, the transmitter and receiver are both clocked by the
bogdanm	82:6473597d706e	2468	* receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
bogdanm	82:6473597d706e	2469	* (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
bogdanm	82:6473597d706e	2470	*
bogdanm	82:6473597d706e	2471	* Values:
bogdanm	82:6473597d706e	2472	* - 0 - Use the normal bit clock source.
bogdanm	82:6473597d706e	2473	* - 1 - Swap the bit clock source.
bogdanm	82:6473597d706e	2474	*/
bogdanm	82:6473597d706e	2475	//@{
bogdanm	82:6473597d706e	2476	#define BP_I2S_RCR2_BCS (29U) //!< Bit position for I2S_RCR2_BCS.
bogdanm	82:6473597d706e	2477	#define BM_I2S_RCR2_BCS (0x20000000U) //!< Bit mask for I2S_RCR2_BCS.
bogdanm	82:6473597d706e	2478	#define BS_I2S_RCR2_BCS (1U) //!< Bit field size in bits for I2S_RCR2_BCS.
bogdanm	82:6473597d706e	2479
bogdanm	82:6473597d706e	2480	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2481	//! @brief Read current value of the I2S_RCR2_BCS field.
bogdanm	82:6473597d706e	2482	#define BR_I2S_RCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS))
bogdanm	82:6473597d706e	2483	#endif
bogdanm	82:6473597d706e	2484
bogdanm	82:6473597d706e	2485	//! @brief Format value for bitfield I2S_RCR2_BCS.
bogdanm	82:6473597d706e	2486	#define BF_I2S_RCR2_BCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCS), uint32_t) & BM_I2S_RCR2_BCS)
bogdanm	82:6473597d706e	2487
bogdanm	82:6473597d706e	2488	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2489	//! @brief Set the BCS field to a new value.
bogdanm	82:6473597d706e	2490	#define BW_I2S_RCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS) = (v))
bogdanm	82:6473597d706e	2491	#endif
bogdanm	82:6473597d706e	2492	//@}
bogdanm	82:6473597d706e	2493
bogdanm	82:6473597d706e	2494	/*!
bogdanm	82:6473597d706e	2495	* @name Register I2S_RCR2, field SYNC[31:30] (RW)
bogdanm	82:6473597d706e	2496	*
bogdanm	82:6473597d706e	2497	* Configures between asynchronous and synchronous modes of operation. When
bogdanm	82:6473597d706e	2498	* configured for a synchronous mode of operation, the transmitter or other SAI
bogdanm	82:6473597d706e	2499	* peripheral must be configured for asynchronous operation.
bogdanm	82:6473597d706e	2500	*
bogdanm	82:6473597d706e	2501	* Values:
bogdanm	82:6473597d706e	2502	* - 00 - Asynchronous mode.
bogdanm	82:6473597d706e	2503	* - 01 - Synchronous with transmitter.
bogdanm	82:6473597d706e	2504	* - 10 - Synchronous with another SAI receiver.
bogdanm	82:6473597d706e	2505	* - 11 - Synchronous with another SAI transmitter.
bogdanm	82:6473597d706e	2506	*/
bogdanm	82:6473597d706e	2507	//@{
bogdanm	82:6473597d706e	2508	#define BP_I2S_RCR2_SYNC (30U) //!< Bit position for I2S_RCR2_SYNC.
bogdanm	82:6473597d706e	2509	#define BM_I2S_RCR2_SYNC (0xC0000000U) //!< Bit mask for I2S_RCR2_SYNC.
bogdanm	82:6473597d706e	2510	#define BS_I2S_RCR2_SYNC (2U) //!< Bit field size in bits for I2S_RCR2_SYNC.
bogdanm	82:6473597d706e	2511
bogdanm	82:6473597d706e	2512	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2513	//! @brief Read current value of the I2S_RCR2_SYNC field.
bogdanm	82:6473597d706e	2514	#define BR_I2S_RCR2_SYNC(x) (HW_I2S_RCR2(x).B.SYNC)
bogdanm	82:6473597d706e	2515	#endif
bogdanm	82:6473597d706e	2516
bogdanm	82:6473597d706e	2517	//! @brief Format value for bitfield I2S_RCR2_SYNC.
bogdanm	82:6473597d706e	2518	#define BF_I2S_RCR2_SYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_SYNC), uint32_t) & BM_I2S_RCR2_SYNC)
bogdanm	82:6473597d706e	2519
bogdanm	82:6473597d706e	2520	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2521	//! @brief Set the SYNC field to a new value.
bogdanm	82:6473597d706e	2522	#define BW_I2S_RCR2_SYNC(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_SYNC) \| BF_I2S_RCR2_SYNC(v)))
bogdanm	82:6473597d706e	2523	#endif
bogdanm	82:6473597d706e	2524	//@}
bogdanm	82:6473597d706e	2525
bogdanm	82:6473597d706e	2526	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2527	// HW_I2S_RCR3 - SAI Receive Configuration 3 Register
bogdanm	82:6473597d706e	2528	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2529
bogdanm	82:6473597d706e	2530	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2531	/*!
bogdanm	82:6473597d706e	2532	* @brief HW_I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
bogdanm	82:6473597d706e	2533	*
bogdanm	82:6473597d706e	2534	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2535	*
bogdanm	82:6473597d706e	2536	* This register must not be altered when RCSR[RE] is set.
bogdanm	82:6473597d706e	2537	*/
bogdanm	82:6473597d706e	2538	typedef union _hw_i2s_rcr3
bogdanm	82:6473597d706e	2539	{
bogdanm	82:6473597d706e	2540	uint32_t U;
bogdanm	82:6473597d706e	2541	struct _hw_i2s_rcr3_bitfields
bogdanm	82:6473597d706e	2542	{
bogdanm	82:6473597d706e	2543	uint32_t WDFL : 5; //!< [4:0] Word Flag Configuration
bogdanm	82:6473597d706e	2544	uint32_t RESERVED0 : 11; //!< [15:5]
bogdanm	82:6473597d706e	2545	uint32_t RCE : 2; //!< [17:16] Receive Channel Enable
bogdanm	82:6473597d706e	2546	uint32_t RESERVED1 : 14; //!< [31:18]
bogdanm	82:6473597d706e	2547	} B;
bogdanm	82:6473597d706e	2548	} hw_i2s_rcr3_t;
bogdanm	82:6473597d706e	2549	#endif
bogdanm	82:6473597d706e	2550
bogdanm	82:6473597d706e	2551	/*!
bogdanm	82:6473597d706e	2552	* @name Constants and macros for entire I2S_RCR3 register
bogdanm	82:6473597d706e	2553	*/
bogdanm	82:6473597d706e	2554	//@{
bogdanm	82:6473597d706e	2555	#define HW_I2S_RCR3_ADDR(x) (REGS_I2S_BASE(x) + 0x8CU)
bogdanm	82:6473597d706e	2556
bogdanm	82:6473597d706e	2557	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2558	#define HW_I2S_RCR3(x) ((__IO hw_i2s_rcr3_t ) HW_I2S_RCR3_ADDR(x))
bogdanm	82:6473597d706e	2559	#define HW_I2S_RCR3_RD(x) (HW_I2S_RCR3(x).U)
bogdanm	82:6473597d706e	2560	#define HW_I2S_RCR3_WR(x, v) (HW_I2S_RCR3(x).U = (v))
bogdanm	82:6473597d706e	2561	#define HW_I2S_RCR3_SET(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) \| (v)))
bogdanm	82:6473597d706e	2562	#define HW_I2S_RCR3_CLR(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2563	#define HW_I2S_RCR3_TOG(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2564	#endif
bogdanm	82:6473597d706e	2565	//@}
bogdanm	82:6473597d706e	2566
bogdanm	82:6473597d706e	2567	/*
bogdanm	82:6473597d706e	2568	* Constants & macros for individual I2S_RCR3 bitfields
bogdanm	82:6473597d706e	2569	*/
bogdanm	82:6473597d706e	2570
bogdanm	82:6473597d706e	2571	/*!
bogdanm	82:6473597d706e	2572	* @name Register I2S_RCR3, field WDFL[4:0] (RW)
bogdanm	82:6473597d706e	2573	*
bogdanm	82:6473597d706e	2574	* Configures which word the start of word flag is set. The value written should
bogdanm	82:6473597d706e	2575	* be one less than the word number (for example, write zero to configure for
bogdanm	82:6473597d706e	2576	* the first word in the frame). When configured to a value greater than the Frame
bogdanm	82:6473597d706e	2577	* Size field, then the start of word flag is never set.
bogdanm	82:6473597d706e	2578	*/
bogdanm	82:6473597d706e	2579	//@{
bogdanm	82:6473597d706e	2580	#define BP_I2S_RCR3_WDFL (0U) //!< Bit position for I2S_RCR3_WDFL.
bogdanm	82:6473597d706e	2581	#define BM_I2S_RCR3_WDFL (0x0000001FU) //!< Bit mask for I2S_RCR3_WDFL.
bogdanm	82:6473597d706e	2582	#define BS_I2S_RCR3_WDFL (5U) //!< Bit field size in bits for I2S_RCR3_WDFL.
bogdanm	82:6473597d706e	2583
bogdanm	82:6473597d706e	2584	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2585	//! @brief Read current value of the I2S_RCR3_WDFL field.
bogdanm	82:6473597d706e	2586	#define BR_I2S_RCR3_WDFL(x) (HW_I2S_RCR3(x).B.WDFL)
bogdanm	82:6473597d706e	2587	#endif
bogdanm	82:6473597d706e	2588
bogdanm	82:6473597d706e	2589	//! @brief Format value for bitfield I2S_RCR3_WDFL.
bogdanm	82:6473597d706e	2590	#define BF_I2S_RCR3_WDFL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR3_WDFL), uint32_t) & BM_I2S_RCR3_WDFL)
bogdanm	82:6473597d706e	2591
bogdanm	82:6473597d706e	2592	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2593	//! @brief Set the WDFL field to a new value.
bogdanm	82:6473597d706e	2594	#define BW_I2S_RCR3_WDFL(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_WDFL) \| BF_I2S_RCR3_WDFL(v)))
bogdanm	82:6473597d706e	2595	#endif
bogdanm	82:6473597d706e	2596	//@}
bogdanm	82:6473597d706e	2597
bogdanm	82:6473597d706e	2598	/*!
bogdanm	82:6473597d706e	2599	* @name Register I2S_RCR3, field RCE[17:16] (RW)
bogdanm	82:6473597d706e	2600	*
bogdanm	82:6473597d706e	2601	* Enables the corresponding data channel for receive operation. A channel must
bogdanm	82:6473597d706e	2602	* be enabled before its FIFO is accessed.
bogdanm	82:6473597d706e	2603	*
bogdanm	82:6473597d706e	2604	* Values:
bogdanm	82:6473597d706e	2605	* - 0 - Receive data channel N is disabled.
bogdanm	82:6473597d706e	2606	* - 1 - Receive data channel N is enabled.
bogdanm	82:6473597d706e	2607	*/
bogdanm	82:6473597d706e	2608	//@{
bogdanm	82:6473597d706e	2609	#define BP_I2S_RCR3_RCE (16U) //!< Bit position for I2S_RCR3_RCE.
bogdanm	82:6473597d706e	2610	#define BM_I2S_RCR3_RCE (0x00030000U) //!< Bit mask for I2S_RCR3_RCE.
bogdanm	82:6473597d706e	2611	#define BS_I2S_RCR3_RCE (2U) //!< Bit field size in bits for I2S_RCR3_RCE.
bogdanm	82:6473597d706e	2612
bogdanm	82:6473597d706e	2613	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2614	//! @brief Read current value of the I2S_RCR3_RCE field.
bogdanm	82:6473597d706e	2615	#define BR_I2S_RCR3_RCE(x) (HW_I2S_RCR3(x).B.RCE)
bogdanm	82:6473597d706e	2616	#endif
bogdanm	82:6473597d706e	2617
bogdanm	82:6473597d706e	2618	//! @brief Format value for bitfield I2S_RCR3_RCE.
bogdanm	82:6473597d706e	2619	#define BF_I2S_RCR3_RCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR3_RCE), uint32_t) & BM_I2S_RCR3_RCE)
bogdanm	82:6473597d706e	2620
bogdanm	82:6473597d706e	2621	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2622	//! @brief Set the RCE field to a new value.
bogdanm	82:6473597d706e	2623	#define BW_I2S_RCR3_RCE(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_RCE) \| BF_I2S_RCR3_RCE(v)))
bogdanm	82:6473597d706e	2624	#endif
bogdanm	82:6473597d706e	2625	//@}
bogdanm	82:6473597d706e	2626
bogdanm	82:6473597d706e	2627	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2628	// HW_I2S_RCR4 - SAI Receive Configuration 4 Register
bogdanm	82:6473597d706e	2629	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2630
bogdanm	82:6473597d706e	2631	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2632	/*!
bogdanm	82:6473597d706e	2633	* @brief HW_I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
bogdanm	82:6473597d706e	2634	*
bogdanm	82:6473597d706e	2635	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2636	*
bogdanm	82:6473597d706e	2637	* This register must not be altered when RCSR[RE] is set.
bogdanm	82:6473597d706e	2638	*/
bogdanm	82:6473597d706e	2639	typedef union _hw_i2s_rcr4
bogdanm	82:6473597d706e	2640	{
bogdanm	82:6473597d706e	2641	uint32_t U;
bogdanm	82:6473597d706e	2642	struct _hw_i2s_rcr4_bitfields
bogdanm	82:6473597d706e	2643	{
bogdanm	82:6473597d706e	2644	uint32_t FSD : 1; //!< [0] Frame Sync Direction
bogdanm	82:6473597d706e	2645	uint32_t FSP : 1; //!< [1] Frame Sync Polarity
bogdanm	82:6473597d706e	2646	uint32_t RESERVED0 : 1; //!< [2]
bogdanm	82:6473597d706e	2647	uint32_t FSE : 1; //!< [3] Frame Sync Early
bogdanm	82:6473597d706e	2648	uint32_t MF : 1; //!< [4] MSB First
bogdanm	82:6473597d706e	2649	uint32_t RESERVED1 : 3; //!< [7:5]
bogdanm	82:6473597d706e	2650	uint32_t SYWD : 5; //!< [12:8] Sync Width
bogdanm	82:6473597d706e	2651	uint32_t RESERVED2 : 3; //!< [15:13]
bogdanm	82:6473597d706e	2652	uint32_t FRSZ : 5; //!< [20:16] Frame Size
bogdanm	82:6473597d706e	2653	uint32_t RESERVED3 : 11; //!< [31:21]
bogdanm	82:6473597d706e	2654	} B;
bogdanm	82:6473597d706e	2655	} hw_i2s_rcr4_t;
bogdanm	82:6473597d706e	2656	#endif
bogdanm	82:6473597d706e	2657
bogdanm	82:6473597d706e	2658	/*!
bogdanm	82:6473597d706e	2659	* @name Constants and macros for entire I2S_RCR4 register
bogdanm	82:6473597d706e	2660	*/
bogdanm	82:6473597d706e	2661	//@{
bogdanm	82:6473597d706e	2662	#define HW_I2S_RCR4_ADDR(x) (REGS_I2S_BASE(x) + 0x90U)
bogdanm	82:6473597d706e	2663
bogdanm	82:6473597d706e	2664	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2665	#define HW_I2S_RCR4(x) ((__IO hw_i2s_rcr4_t ) HW_I2S_RCR4_ADDR(x))
bogdanm	82:6473597d706e	2666	#define HW_I2S_RCR4_RD(x) (HW_I2S_RCR4(x).U)
bogdanm	82:6473597d706e	2667	#define HW_I2S_RCR4_WR(x, v) (HW_I2S_RCR4(x).U = (v))
bogdanm	82:6473597d706e	2668	#define HW_I2S_RCR4_SET(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) \| (v)))
bogdanm	82:6473597d706e	2669	#define HW_I2S_RCR4_CLR(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2670	#define HW_I2S_RCR4_TOG(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2671	#endif
bogdanm	82:6473597d706e	2672	//@}
bogdanm	82:6473597d706e	2673
bogdanm	82:6473597d706e	2674	/*
bogdanm	82:6473597d706e	2675	* Constants & macros for individual I2S_RCR4 bitfields
bogdanm	82:6473597d706e	2676	*/
bogdanm	82:6473597d706e	2677
bogdanm	82:6473597d706e	2678	/*!
bogdanm	82:6473597d706e	2679	* @name Register I2S_RCR4, field FSD[0] (RW)
bogdanm	82:6473597d706e	2680	*
bogdanm	82:6473597d706e	2681	* Configures the direction of the frame sync.
bogdanm	82:6473597d706e	2682	*
bogdanm	82:6473597d706e	2683	* Values:
bogdanm	82:6473597d706e	2684	* - 0 - Frame Sync is generated externally in Slave mode.
bogdanm	82:6473597d706e	2685	* - 1 - Frame Sync is generated internally in Master mode.
bogdanm	82:6473597d706e	2686	*/
bogdanm	82:6473597d706e	2687	//@{
bogdanm	82:6473597d706e	2688	#define BP_I2S_RCR4_FSD (0U) //!< Bit position for I2S_RCR4_FSD.
bogdanm	82:6473597d706e	2689	#define BM_I2S_RCR4_FSD (0x00000001U) //!< Bit mask for I2S_RCR4_FSD.
bogdanm	82:6473597d706e	2690	#define BS_I2S_RCR4_FSD (1U) //!< Bit field size in bits for I2S_RCR4_FSD.
bogdanm	82:6473597d706e	2691
bogdanm	82:6473597d706e	2692	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2693	//! @brief Read current value of the I2S_RCR4_FSD field.
bogdanm	82:6473597d706e	2694	#define BR_I2S_RCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD))
bogdanm	82:6473597d706e	2695	#endif
bogdanm	82:6473597d706e	2696
bogdanm	82:6473597d706e	2697	//! @brief Format value for bitfield I2S_RCR4_FSD.
bogdanm	82:6473597d706e	2698	#define BF_I2S_RCR4_FSD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSD), uint32_t) & BM_I2S_RCR4_FSD)
bogdanm	82:6473597d706e	2699
bogdanm	82:6473597d706e	2700	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2701	//! @brief Set the FSD field to a new value.
bogdanm	82:6473597d706e	2702	#define BW_I2S_RCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD) = (v))
bogdanm	82:6473597d706e	2703	#endif
bogdanm	82:6473597d706e	2704	//@}
bogdanm	82:6473597d706e	2705
bogdanm	82:6473597d706e	2706	/*!
bogdanm	82:6473597d706e	2707	* @name Register I2S_RCR4, field FSP[1] (RW)
bogdanm	82:6473597d706e	2708	*
bogdanm	82:6473597d706e	2709	* Configures the polarity of the frame sync.
bogdanm	82:6473597d706e	2710	*
bogdanm	82:6473597d706e	2711	* Values:
bogdanm	82:6473597d706e	2712	* - 0 - Frame sync is active high.
bogdanm	82:6473597d706e	2713	* - 1 - Frame sync is active low.
bogdanm	82:6473597d706e	2714	*/
bogdanm	82:6473597d706e	2715	//@{
bogdanm	82:6473597d706e	2716	#define BP_I2S_RCR4_FSP (1U) //!< Bit position for I2S_RCR4_FSP.
bogdanm	82:6473597d706e	2717	#define BM_I2S_RCR4_FSP (0x00000002U) //!< Bit mask for I2S_RCR4_FSP.
bogdanm	82:6473597d706e	2718	#define BS_I2S_RCR4_FSP (1U) //!< Bit field size in bits for I2S_RCR4_FSP.
bogdanm	82:6473597d706e	2719
bogdanm	82:6473597d706e	2720	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2721	//! @brief Read current value of the I2S_RCR4_FSP field.
bogdanm	82:6473597d706e	2722	#define BR_I2S_RCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP))
bogdanm	82:6473597d706e	2723	#endif
bogdanm	82:6473597d706e	2724
bogdanm	82:6473597d706e	2725	//! @brief Format value for bitfield I2S_RCR4_FSP.
bogdanm	82:6473597d706e	2726	#define BF_I2S_RCR4_FSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSP), uint32_t) & BM_I2S_RCR4_FSP)
bogdanm	82:6473597d706e	2727
bogdanm	82:6473597d706e	2728	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2729	//! @brief Set the FSP field to a new value.
bogdanm	82:6473597d706e	2730	#define BW_I2S_RCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP) = (v))
bogdanm	82:6473597d706e	2731	#endif
bogdanm	82:6473597d706e	2732	//@}
bogdanm	82:6473597d706e	2733
bogdanm	82:6473597d706e	2734	/*!
bogdanm	82:6473597d706e	2735	* @name Register I2S_RCR4, field FSE[3] (RW)
bogdanm	82:6473597d706e	2736	*
bogdanm	82:6473597d706e	2737	* Values:
bogdanm	82:6473597d706e	2738	* - 0 - Frame sync asserts with the first bit of the frame.
bogdanm	82:6473597d706e	2739	* - 1 - Frame sync asserts one bit before the first bit of the frame.
bogdanm	82:6473597d706e	2740	*/
bogdanm	82:6473597d706e	2741	//@{
bogdanm	82:6473597d706e	2742	#define BP_I2S_RCR4_FSE (3U) //!< Bit position for I2S_RCR4_FSE.
bogdanm	82:6473597d706e	2743	#define BM_I2S_RCR4_FSE (0x00000008U) //!< Bit mask for I2S_RCR4_FSE.
bogdanm	82:6473597d706e	2744	#define BS_I2S_RCR4_FSE (1U) //!< Bit field size in bits for I2S_RCR4_FSE.
bogdanm	82:6473597d706e	2745
bogdanm	82:6473597d706e	2746	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2747	//! @brief Read current value of the I2S_RCR4_FSE field.
bogdanm	82:6473597d706e	2748	#define BR_I2S_RCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE))
bogdanm	82:6473597d706e	2749	#endif
bogdanm	82:6473597d706e	2750
bogdanm	82:6473597d706e	2751	//! @brief Format value for bitfield I2S_RCR4_FSE.
bogdanm	82:6473597d706e	2752	#define BF_I2S_RCR4_FSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSE), uint32_t) & BM_I2S_RCR4_FSE)
bogdanm	82:6473597d706e	2753
bogdanm	82:6473597d706e	2754	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2755	//! @brief Set the FSE field to a new value.
bogdanm	82:6473597d706e	2756	#define BW_I2S_RCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE) = (v))
bogdanm	82:6473597d706e	2757	#endif
bogdanm	82:6473597d706e	2758	//@}
bogdanm	82:6473597d706e	2759
bogdanm	82:6473597d706e	2760	/*!
bogdanm	82:6473597d706e	2761	* @name Register I2S_RCR4, field MF[4] (RW)
bogdanm	82:6473597d706e	2762	*
bogdanm	82:6473597d706e	2763	* Configures whether the LSB or the MSB is received first.
bogdanm	82:6473597d706e	2764	*
bogdanm	82:6473597d706e	2765	* Values:
bogdanm	82:6473597d706e	2766	* - 0 - LSB is received first.
bogdanm	82:6473597d706e	2767	* - 1 - MSB is received first.
bogdanm	82:6473597d706e	2768	*/
bogdanm	82:6473597d706e	2769	//@{
bogdanm	82:6473597d706e	2770	#define BP_I2S_RCR4_MF (4U) //!< Bit position for I2S_RCR4_MF.
bogdanm	82:6473597d706e	2771	#define BM_I2S_RCR4_MF (0x00000010U) //!< Bit mask for I2S_RCR4_MF.
bogdanm	82:6473597d706e	2772	#define BS_I2S_RCR4_MF (1U) //!< Bit field size in bits for I2S_RCR4_MF.
bogdanm	82:6473597d706e	2773
bogdanm	82:6473597d706e	2774	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2775	//! @brief Read current value of the I2S_RCR4_MF field.
bogdanm	82:6473597d706e	2776	#define BR_I2S_RCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF))
bogdanm	82:6473597d706e	2777	#endif
bogdanm	82:6473597d706e	2778
bogdanm	82:6473597d706e	2779	//! @brief Format value for bitfield I2S_RCR4_MF.
bogdanm	82:6473597d706e	2780	#define BF_I2S_RCR4_MF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_MF), uint32_t) & BM_I2S_RCR4_MF)
bogdanm	82:6473597d706e	2781
bogdanm	82:6473597d706e	2782	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2783	//! @brief Set the MF field to a new value.
bogdanm	82:6473597d706e	2784	#define BW_I2S_RCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF) = (v))
bogdanm	82:6473597d706e	2785	#endif
bogdanm	82:6473597d706e	2786	//@}
bogdanm	82:6473597d706e	2787
bogdanm	82:6473597d706e	2788	/*!
bogdanm	82:6473597d706e	2789	* @name Register I2S_RCR4, field SYWD[12:8] (RW)
bogdanm	82:6473597d706e	2790	*
bogdanm	82:6473597d706e	2791	* Configures the length of the frame sync in number of bit clocks. The value
bogdanm	82:6473597d706e	2792	* written must be one less than the number of bit clocks. For example, write 0 for
bogdanm	82:6473597d706e	2793	* the frame sync to assert for one bit clock only. The sync width cannot be
bogdanm	82:6473597d706e	2794	* configured longer than the first word of the frame.
bogdanm	82:6473597d706e	2795	*/
bogdanm	82:6473597d706e	2796	//@{
bogdanm	82:6473597d706e	2797	#define BP_I2S_RCR4_SYWD (8U) //!< Bit position for I2S_RCR4_SYWD.
bogdanm	82:6473597d706e	2798	#define BM_I2S_RCR4_SYWD (0x00001F00U) //!< Bit mask for I2S_RCR4_SYWD.
bogdanm	82:6473597d706e	2799	#define BS_I2S_RCR4_SYWD (5U) //!< Bit field size in bits for I2S_RCR4_SYWD.
bogdanm	82:6473597d706e	2800
bogdanm	82:6473597d706e	2801	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2802	//! @brief Read current value of the I2S_RCR4_SYWD field.
bogdanm	82:6473597d706e	2803	#define BR_I2S_RCR4_SYWD(x) (HW_I2S_RCR4(x).B.SYWD)
bogdanm	82:6473597d706e	2804	#endif
bogdanm	82:6473597d706e	2805
bogdanm	82:6473597d706e	2806	//! @brief Format value for bitfield I2S_RCR4_SYWD.
bogdanm	82:6473597d706e	2807	#define BF_I2S_RCR4_SYWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_SYWD), uint32_t) & BM_I2S_RCR4_SYWD)
bogdanm	82:6473597d706e	2808
bogdanm	82:6473597d706e	2809	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2810	//! @brief Set the SYWD field to a new value.
bogdanm	82:6473597d706e	2811	#define BW_I2S_RCR4_SYWD(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_SYWD) \| BF_I2S_RCR4_SYWD(v)))
bogdanm	82:6473597d706e	2812	#endif
bogdanm	82:6473597d706e	2813	//@}
bogdanm	82:6473597d706e	2814
bogdanm	82:6473597d706e	2815	/*!
bogdanm	82:6473597d706e	2816	* @name Register I2S_RCR4, field FRSZ[20:16] (RW)
bogdanm	82:6473597d706e	2817	*
bogdanm	82:6473597d706e	2818	* Configures the number of words in each frame. The value written must be one
bogdanm	82:6473597d706e	2819	* less than the number of words in the frame. For example, write 0 for one word
bogdanm	82:6473597d706e	2820	* per frame. The maximum supported frame size is 32 words.
bogdanm	82:6473597d706e	2821	*/
bogdanm	82:6473597d706e	2822	//@{
bogdanm	82:6473597d706e	2823	#define BP_I2S_RCR4_FRSZ (16U) //!< Bit position for I2S_RCR4_FRSZ.
bogdanm	82:6473597d706e	2824	#define BM_I2S_RCR4_FRSZ (0x001F0000U) //!< Bit mask for I2S_RCR4_FRSZ.
bogdanm	82:6473597d706e	2825	#define BS_I2S_RCR4_FRSZ (5U) //!< Bit field size in bits for I2S_RCR4_FRSZ.
bogdanm	82:6473597d706e	2826
bogdanm	82:6473597d706e	2827	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2828	//! @brief Read current value of the I2S_RCR4_FRSZ field.
bogdanm	82:6473597d706e	2829	#define BR_I2S_RCR4_FRSZ(x) (HW_I2S_RCR4(x).B.FRSZ)
bogdanm	82:6473597d706e	2830	#endif
bogdanm	82:6473597d706e	2831
bogdanm	82:6473597d706e	2832	//! @brief Format value for bitfield I2S_RCR4_FRSZ.
bogdanm	82:6473597d706e	2833	#define BF_I2S_RCR4_FRSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FRSZ), uint32_t) & BM_I2S_RCR4_FRSZ)
bogdanm	82:6473597d706e	2834
bogdanm	82:6473597d706e	2835	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2836	//! @brief Set the FRSZ field to a new value.
bogdanm	82:6473597d706e	2837	#define BW_I2S_RCR4_FRSZ(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FRSZ) \| BF_I2S_RCR4_FRSZ(v)))
bogdanm	82:6473597d706e	2838	#endif
bogdanm	82:6473597d706e	2839	//@}
bogdanm	82:6473597d706e	2840
bogdanm	82:6473597d706e	2841	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2842	// HW_I2S_RCR5 - SAI Receive Configuration 5 Register
bogdanm	82:6473597d706e	2843	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2844
bogdanm	82:6473597d706e	2845	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2846	/*!
bogdanm	82:6473597d706e	2847	* @brief HW_I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
bogdanm	82:6473597d706e	2848	*
bogdanm	82:6473597d706e	2849	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2850	*
bogdanm	82:6473597d706e	2851	* This register must not be altered when RCSR[RE] is set.
bogdanm	82:6473597d706e	2852	*/
bogdanm	82:6473597d706e	2853	typedef union _hw_i2s_rcr5
bogdanm	82:6473597d706e	2854	{
bogdanm	82:6473597d706e	2855	uint32_t U;
bogdanm	82:6473597d706e	2856	struct _hw_i2s_rcr5_bitfields
bogdanm	82:6473597d706e	2857	{
bogdanm	82:6473597d706e	2858	uint32_t RESERVED0 : 8; //!< [7:0]
bogdanm	82:6473597d706e	2859	uint32_t FBT : 5; //!< [12:8] First Bit Shifted
bogdanm	82:6473597d706e	2860	uint32_t RESERVED1 : 3; //!< [15:13]
bogdanm	82:6473597d706e	2861	uint32_t W0W : 5; //!< [20:16] Word 0 Width
bogdanm	82:6473597d706e	2862	uint32_t RESERVED2 : 3; //!< [23:21]
bogdanm	82:6473597d706e	2863	uint32_t WNW : 5; //!< [28:24] Word N Width
bogdanm	82:6473597d706e	2864	uint32_t RESERVED3 : 3; //!< [31:29]
bogdanm	82:6473597d706e	2865	} B;
bogdanm	82:6473597d706e	2866	} hw_i2s_rcr5_t;
bogdanm	82:6473597d706e	2867	#endif
bogdanm	82:6473597d706e	2868
bogdanm	82:6473597d706e	2869	/*!
bogdanm	82:6473597d706e	2870	* @name Constants and macros for entire I2S_RCR5 register
bogdanm	82:6473597d706e	2871	*/
bogdanm	82:6473597d706e	2872	//@{
bogdanm	82:6473597d706e	2873	#define HW_I2S_RCR5_ADDR(x) (REGS_I2S_BASE(x) + 0x94U)
bogdanm	82:6473597d706e	2874
bogdanm	82:6473597d706e	2875	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2876	#define HW_I2S_RCR5(x) ((__IO hw_i2s_rcr5_t ) HW_I2S_RCR5_ADDR(x))
bogdanm	82:6473597d706e	2877	#define HW_I2S_RCR5_RD(x) (HW_I2S_RCR5(x).U)
bogdanm	82:6473597d706e	2878	#define HW_I2S_RCR5_WR(x, v) (HW_I2S_RCR5(x).U = (v))
bogdanm	82:6473597d706e	2879	#define HW_I2S_RCR5_SET(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) \| (v)))
bogdanm	82:6473597d706e	2880	#define HW_I2S_RCR5_CLR(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2881	#define HW_I2S_RCR5_TOG(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2882	#endif
bogdanm	82:6473597d706e	2883	//@}
bogdanm	82:6473597d706e	2884
bogdanm	82:6473597d706e	2885	/*
bogdanm	82:6473597d706e	2886	* Constants & macros for individual I2S_RCR5 bitfields
bogdanm	82:6473597d706e	2887	*/
bogdanm	82:6473597d706e	2888
bogdanm	82:6473597d706e	2889	/*!
bogdanm	82:6473597d706e	2890	* @name Register I2S_RCR5, field FBT[12:8] (RW)
bogdanm	82:6473597d706e	2891	*
bogdanm	82:6473597d706e	2892	* Configures the bit index for the first bit received for each word in the
bogdanm	82:6473597d706e	2893	* frame. If configured for MSB First, the index of the next bit received is one less
bogdanm	82:6473597d706e	2894	* than the current bit received. If configured for LSB First, the index of the
bogdanm	82:6473597d706e	2895	* next bit received is one more than the current bit received. The value written
bogdanm	82:6473597d706e	2896	* must be greater than or equal to the word width when configured for MSB
bogdanm	82:6473597d706e	2897	* First. The value written must be less than or equal to 31-word width when
bogdanm	82:6473597d706e	2898	* configured for LSB First.
bogdanm	82:6473597d706e	2899	*/
bogdanm	82:6473597d706e	2900	//@{
bogdanm	82:6473597d706e	2901	#define BP_I2S_RCR5_FBT (8U) //!< Bit position for I2S_RCR5_FBT.
bogdanm	82:6473597d706e	2902	#define BM_I2S_RCR5_FBT (0x00001F00U) //!< Bit mask for I2S_RCR5_FBT.
bogdanm	82:6473597d706e	2903	#define BS_I2S_RCR5_FBT (5U) //!< Bit field size in bits for I2S_RCR5_FBT.
bogdanm	82:6473597d706e	2904
bogdanm	82:6473597d706e	2905	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2906	//! @brief Read current value of the I2S_RCR5_FBT field.
bogdanm	82:6473597d706e	2907	#define BR_I2S_RCR5_FBT(x) (HW_I2S_RCR5(x).B.FBT)
bogdanm	82:6473597d706e	2908	#endif
bogdanm	82:6473597d706e	2909
bogdanm	82:6473597d706e	2910	//! @brief Format value for bitfield I2S_RCR5_FBT.
bogdanm	82:6473597d706e	2911	#define BF_I2S_RCR5_FBT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_FBT), uint32_t) & BM_I2S_RCR5_FBT)
bogdanm	82:6473597d706e	2912
bogdanm	82:6473597d706e	2913	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2914	//! @brief Set the FBT field to a new value.
bogdanm	82:6473597d706e	2915	#define BW_I2S_RCR5_FBT(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_FBT) \| BF_I2S_RCR5_FBT(v)))
bogdanm	82:6473597d706e	2916	#endif
bogdanm	82:6473597d706e	2917	//@}
bogdanm	82:6473597d706e	2918
bogdanm	82:6473597d706e	2919	/*!
bogdanm	82:6473597d706e	2920	* @name Register I2S_RCR5, field W0W[20:16] (RW)
bogdanm	82:6473597d706e	2921	*
bogdanm	82:6473597d706e	2922	* Configures the number of bits in the first word in each frame. The value
bogdanm	82:6473597d706e	2923	* written must be one less than the number of bits in the first word. Word width of
bogdanm	82:6473597d706e	2924	* less than 8 bits is not supported if there is only one word per frame.
bogdanm	82:6473597d706e	2925	*/
bogdanm	82:6473597d706e	2926	//@{
bogdanm	82:6473597d706e	2927	#define BP_I2S_RCR5_W0W (16U) //!< Bit position for I2S_RCR5_W0W.
bogdanm	82:6473597d706e	2928	#define BM_I2S_RCR5_W0W (0x001F0000U) //!< Bit mask for I2S_RCR5_W0W.
bogdanm	82:6473597d706e	2929	#define BS_I2S_RCR5_W0W (5U) //!< Bit field size in bits for I2S_RCR5_W0W.
bogdanm	82:6473597d706e	2930
bogdanm	82:6473597d706e	2931	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2932	//! @brief Read current value of the I2S_RCR5_W0W field.
bogdanm	82:6473597d706e	2933	#define BR_I2S_RCR5_W0W(x) (HW_I2S_RCR5(x).B.W0W)
bogdanm	82:6473597d706e	2934	#endif
bogdanm	82:6473597d706e	2935
bogdanm	82:6473597d706e	2936	//! @brief Format value for bitfield I2S_RCR5_W0W.
bogdanm	82:6473597d706e	2937	#define BF_I2S_RCR5_W0W(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_W0W), uint32_t) & BM_I2S_RCR5_W0W)
bogdanm	82:6473597d706e	2938
bogdanm	82:6473597d706e	2939	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2940	//! @brief Set the W0W field to a new value.
bogdanm	82:6473597d706e	2941	#define BW_I2S_RCR5_W0W(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_W0W) \| BF_I2S_RCR5_W0W(v)))
bogdanm	82:6473597d706e	2942	#endif
bogdanm	82:6473597d706e	2943	//@}
bogdanm	82:6473597d706e	2944
bogdanm	82:6473597d706e	2945	/*!
bogdanm	82:6473597d706e	2946	* @name Register I2S_RCR5, field WNW[28:24] (RW)
bogdanm	82:6473597d706e	2947	*
bogdanm	82:6473597d706e	2948	* Configures the number of bits in each word, for each word except the first in
bogdanm	82:6473597d706e	2949	* the frame. The value written must be one less than the number of bits per
bogdanm	82:6473597d706e	2950	* word. Word width of less than 8 bits is not supported.
bogdanm	82:6473597d706e	2951	*/
bogdanm	82:6473597d706e	2952	//@{
bogdanm	82:6473597d706e	2953	#define BP_I2S_RCR5_WNW (24U) //!< Bit position for I2S_RCR5_WNW.
bogdanm	82:6473597d706e	2954	#define BM_I2S_RCR5_WNW (0x1F000000U) //!< Bit mask for I2S_RCR5_WNW.
bogdanm	82:6473597d706e	2955	#define BS_I2S_RCR5_WNW (5U) //!< Bit field size in bits for I2S_RCR5_WNW.
bogdanm	82:6473597d706e	2956
bogdanm	82:6473597d706e	2957	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2958	//! @brief Read current value of the I2S_RCR5_WNW field.
bogdanm	82:6473597d706e	2959	#define BR_I2S_RCR5_WNW(x) (HW_I2S_RCR5(x).B.WNW)
bogdanm	82:6473597d706e	2960	#endif
bogdanm	82:6473597d706e	2961
bogdanm	82:6473597d706e	2962	//! @brief Format value for bitfield I2S_RCR5_WNW.
bogdanm	82:6473597d706e	2963	#define BF_I2S_RCR5_WNW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_WNW), uint32_t) & BM_I2S_RCR5_WNW)
bogdanm	82:6473597d706e	2964
bogdanm	82:6473597d706e	2965	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2966	//! @brief Set the WNW field to a new value.
bogdanm	82:6473597d706e	2967	#define BW_I2S_RCR5_WNW(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_WNW) \| BF_I2S_RCR5_WNW(v)))
bogdanm	82:6473597d706e	2968	#endif
bogdanm	82:6473597d706e	2969	//@}
bogdanm	82:6473597d706e	2970
bogdanm	82:6473597d706e	2971	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2972	// HW_I2S_RDRn - SAI Receive Data Register
bogdanm	82:6473597d706e	2973	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2974
bogdanm	82:6473597d706e	2975	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2976	/*!
bogdanm	82:6473597d706e	2977	* @brief HW_I2S_RDRn - SAI Receive Data Register (RO)
bogdanm	82:6473597d706e	2978	*
bogdanm	82:6473597d706e	2979	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2980	*
bogdanm	82:6473597d706e	2981	* Reading this register introduces one additional peripheral clock wait state
bogdanm	82:6473597d706e	2982	* on each read.
bogdanm	82:6473597d706e	2983	*/
bogdanm	82:6473597d706e	2984	typedef union _hw_i2s_rdrn
bogdanm	82:6473597d706e	2985	{
bogdanm	82:6473597d706e	2986	uint32_t U;
bogdanm	82:6473597d706e	2987	struct _hw_i2s_rdrn_bitfields
bogdanm	82:6473597d706e	2988	{
bogdanm	82:6473597d706e	2989	uint32_t RDR : 32; //!< [31:0] Receive Data Register
bogdanm	82:6473597d706e	2990	} B;
bogdanm	82:6473597d706e	2991	} hw_i2s_rdrn_t;
bogdanm	82:6473597d706e	2992	#endif
bogdanm	82:6473597d706e	2993
bogdanm	82:6473597d706e	2994	/*!
bogdanm	82:6473597d706e	2995	* @name Constants and macros for entire I2S_RDRn register
bogdanm	82:6473597d706e	2996	*/
bogdanm	82:6473597d706e	2997	//@{
bogdanm	82:6473597d706e	2998	#define HW_I2S_RDRn_COUNT (2U)
bogdanm	82:6473597d706e	2999
bogdanm	82:6473597d706e	3000	#define HW_I2S_RDRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0xA0U + (0x4U * n))
bogdanm	82:6473597d706e	3001
bogdanm	82:6473597d706e	3002	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3003	#define HW_I2S_RDRn(x, n) ((__I hw_i2s_rdrn_t ) HW_I2S_RDRn_ADDR(x, n))
bogdanm	82:6473597d706e	3004	#define HW_I2S_RDRn_RD(x, n) (HW_I2S_RDRn(x, n).U)
bogdanm	82:6473597d706e	3005	#endif
bogdanm	82:6473597d706e	3006	//@}
bogdanm	82:6473597d706e	3007
bogdanm	82:6473597d706e	3008	/*
bogdanm	82:6473597d706e	3009	* Constants & macros for individual I2S_RDRn bitfields
bogdanm	82:6473597d706e	3010	*/
bogdanm	82:6473597d706e	3011
bogdanm	82:6473597d706e	3012	/*!
bogdanm	82:6473597d706e	3013	* @name Register I2S_RDRn, field RDR[31:0] (RO)
bogdanm	82:6473597d706e	3014	*
bogdanm	82:6473597d706e	3015	* The corresponding RCR3[RCE] bit must be set before accessing the channel's
bogdanm	82:6473597d706e	3016	* receive data register. Reads from this register when the receive FIFO is not
bogdanm	82:6473597d706e	3017	* empty will return the data from the top of the receive FIFO. Reads from this
bogdanm	82:6473597d706e	3018	* register when the receive FIFO is empty are ignored.
bogdanm	82:6473597d706e	3019	*/
bogdanm	82:6473597d706e	3020	//@{
bogdanm	82:6473597d706e	3021	#define BP_I2S_RDRn_RDR (0U) //!< Bit position for I2S_RDRn_RDR.
bogdanm	82:6473597d706e	3022	#define BM_I2S_RDRn_RDR (0xFFFFFFFFU) //!< Bit mask for I2S_RDRn_RDR.
bogdanm	82:6473597d706e	3023	#define BS_I2S_RDRn_RDR (32U) //!< Bit field size in bits for I2S_RDRn_RDR.
bogdanm	82:6473597d706e	3024
bogdanm	82:6473597d706e	3025	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3026	//! @brief Read current value of the I2S_RDRn_RDR field.
bogdanm	82:6473597d706e	3027	#define BR_I2S_RDRn_RDR(x, n) (HW_I2S_RDRn(x, n).U)
bogdanm	82:6473597d706e	3028	#endif
bogdanm	82:6473597d706e	3029	//@}
bogdanm	82:6473597d706e	3030
bogdanm	82:6473597d706e	3031	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3032	// HW_I2S_RFRn - SAI Receive FIFO Register
bogdanm	82:6473597d706e	3033	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3034
bogdanm	82:6473597d706e	3035	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3036	/*!
bogdanm	82:6473597d706e	3037	* @brief HW_I2S_RFRn - SAI Receive FIFO Register (RO)
bogdanm	82:6473597d706e	3038	*
bogdanm	82:6473597d706e	3039	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3040	*
bogdanm	82:6473597d706e	3041	* The MSB of the read and write pointers is used to distinguish between FIFO
bogdanm	82:6473597d706e	3042	* full and empty conditions. If the read and write pointers are identical, then
bogdanm	82:6473597d706e	3043	* the FIFO is empty. If the read and write pointers are identical except for the
bogdanm	82:6473597d706e	3044	* MSB, then the FIFO is full.
bogdanm	82:6473597d706e	3045	*/
bogdanm	82:6473597d706e	3046	typedef union _hw_i2s_rfrn
bogdanm	82:6473597d706e	3047	{
bogdanm	82:6473597d706e	3048	uint32_t U;
bogdanm	82:6473597d706e	3049	struct _hw_i2s_rfrn_bitfields
bogdanm	82:6473597d706e	3050	{
bogdanm	82:6473597d706e	3051	uint32_t RFP : 4; //!< [3:0] Read FIFO Pointer
bogdanm	82:6473597d706e	3052	uint32_t RESERVED0 : 12; //!< [15:4]
bogdanm	82:6473597d706e	3053	uint32_t WFP : 4; //!< [19:16] Write FIFO Pointer
bogdanm	82:6473597d706e	3054	uint32_t RESERVED1 : 12; //!< [31:20]
bogdanm	82:6473597d706e	3055	} B;
bogdanm	82:6473597d706e	3056	} hw_i2s_rfrn_t;
bogdanm	82:6473597d706e	3057	#endif
bogdanm	82:6473597d706e	3058
bogdanm	82:6473597d706e	3059	/*!
bogdanm	82:6473597d706e	3060	* @name Constants and macros for entire I2S_RFRn register
bogdanm	82:6473597d706e	3061	*/
bogdanm	82:6473597d706e	3062	//@{
bogdanm	82:6473597d706e	3063	#define HW_I2S_RFRn_COUNT (2U)
bogdanm	82:6473597d706e	3064
bogdanm	82:6473597d706e	3065	#define HW_I2S_RFRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0xC0U + (0x4U * n))
bogdanm	82:6473597d706e	3066
bogdanm	82:6473597d706e	3067	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3068	#define HW_I2S_RFRn(x, n) ((__I hw_i2s_rfrn_t ) HW_I2S_RFRn_ADDR(x, n))
bogdanm	82:6473597d706e	3069	#define HW_I2S_RFRn_RD(x, n) (HW_I2S_RFRn(x, n).U)
bogdanm	82:6473597d706e	3070	#endif
bogdanm	82:6473597d706e	3071	//@}
bogdanm	82:6473597d706e	3072
bogdanm	82:6473597d706e	3073	/*
bogdanm	82:6473597d706e	3074	* Constants & macros for individual I2S_RFRn bitfields
bogdanm	82:6473597d706e	3075	*/
bogdanm	82:6473597d706e	3076
bogdanm	82:6473597d706e	3077	/*!
bogdanm	82:6473597d706e	3078	* @name Register I2S_RFRn, field RFP[3:0] (RO)
bogdanm	82:6473597d706e	3079	*
bogdanm	82:6473597d706e	3080	* FIFO read pointer for receive data channel.
bogdanm	82:6473597d706e	3081	*/
bogdanm	82:6473597d706e	3082	//@{
bogdanm	82:6473597d706e	3083	#define BP_I2S_RFRn_RFP (0U) //!< Bit position for I2S_RFRn_RFP.
bogdanm	82:6473597d706e	3084	#define BM_I2S_RFRn_RFP (0x0000000FU) //!< Bit mask for I2S_RFRn_RFP.
bogdanm	82:6473597d706e	3085	#define BS_I2S_RFRn_RFP (4U) //!< Bit field size in bits for I2S_RFRn_RFP.
bogdanm	82:6473597d706e	3086
bogdanm	82:6473597d706e	3087	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3088	//! @brief Read current value of the I2S_RFRn_RFP field.
bogdanm	82:6473597d706e	3089	#define BR_I2S_RFRn_RFP(x, n) (HW_I2S_RFRn(x, n).B.RFP)
bogdanm	82:6473597d706e	3090	#endif
bogdanm	82:6473597d706e	3091	//@}
bogdanm	82:6473597d706e	3092
bogdanm	82:6473597d706e	3093	/*!
bogdanm	82:6473597d706e	3094	* @name Register I2S_RFRn, field WFP[19:16] (RO)
bogdanm	82:6473597d706e	3095	*
bogdanm	82:6473597d706e	3096	* FIFO write pointer for receive data channel.
bogdanm	82:6473597d706e	3097	*/
bogdanm	82:6473597d706e	3098	//@{
bogdanm	82:6473597d706e	3099	#define BP_I2S_RFRn_WFP (16U) //!< Bit position for I2S_RFRn_WFP.
bogdanm	82:6473597d706e	3100	#define BM_I2S_RFRn_WFP (0x000F0000U) //!< Bit mask for I2S_RFRn_WFP.
bogdanm	82:6473597d706e	3101	#define BS_I2S_RFRn_WFP (4U) //!< Bit field size in bits for I2S_RFRn_WFP.
bogdanm	82:6473597d706e	3102
bogdanm	82:6473597d706e	3103	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3104	//! @brief Read current value of the I2S_RFRn_WFP field.
bogdanm	82:6473597d706e	3105	#define BR_I2S_RFRn_WFP(x, n) (HW_I2S_RFRn(x, n).B.WFP)
bogdanm	82:6473597d706e	3106	#endif
bogdanm	82:6473597d706e	3107	//@}
bogdanm	82:6473597d706e	3108
bogdanm	82:6473597d706e	3109	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3110	// HW_I2S_RMR - SAI Receive Mask Register
bogdanm	82:6473597d706e	3111	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3112
bogdanm	82:6473597d706e	3113	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3114	/*!
bogdanm	82:6473597d706e	3115	* @brief HW_I2S_RMR - SAI Receive Mask Register (RW)
bogdanm	82:6473597d706e	3116	*
bogdanm	82:6473597d706e	3117	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3118	*
bogdanm	82:6473597d706e	3119	* This register is double-buffered and updates: When RCSR[RE] is first set At
bogdanm	82:6473597d706e	3120	* the end of each frame This allows the masked words in each frame to change from
bogdanm	82:6473597d706e	3121	* frame to frame.
bogdanm	82:6473597d706e	3122	*/
bogdanm	82:6473597d706e	3123	typedef union _hw_i2s_rmr
bogdanm	82:6473597d706e	3124	{
bogdanm	82:6473597d706e	3125	uint32_t U;
bogdanm	82:6473597d706e	3126	struct _hw_i2s_rmr_bitfields
bogdanm	82:6473597d706e	3127	{
bogdanm	82:6473597d706e	3128	uint32_t RWM : 32; //!< [31:0] Receive Word Mask
bogdanm	82:6473597d706e	3129	} B;
bogdanm	82:6473597d706e	3130	} hw_i2s_rmr_t;
bogdanm	82:6473597d706e	3131	#endif
bogdanm	82:6473597d706e	3132
bogdanm	82:6473597d706e	3133	/*!
bogdanm	82:6473597d706e	3134	* @name Constants and macros for entire I2S_RMR register
bogdanm	82:6473597d706e	3135	*/
bogdanm	82:6473597d706e	3136	//@{
bogdanm	82:6473597d706e	3137	#define HW_I2S_RMR_ADDR(x) (REGS_I2S_BASE(x) + 0xE0U)
bogdanm	82:6473597d706e	3138
bogdanm	82:6473597d706e	3139	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3140	#define HW_I2S_RMR(x) ((__IO hw_i2s_rmr_t ) HW_I2S_RMR_ADDR(x))
bogdanm	82:6473597d706e	3141	#define HW_I2S_RMR_RD(x) (HW_I2S_RMR(x).U)
bogdanm	82:6473597d706e	3142	#define HW_I2S_RMR_WR(x, v) (HW_I2S_RMR(x).U = (v))
bogdanm	82:6473597d706e	3143	#define HW_I2S_RMR_SET(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) \| (v)))
bogdanm	82:6473597d706e	3144	#define HW_I2S_RMR_CLR(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3145	#define HW_I2S_RMR_TOG(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3146	#endif
bogdanm	82:6473597d706e	3147	//@}
bogdanm	82:6473597d706e	3148
bogdanm	82:6473597d706e	3149	/*
bogdanm	82:6473597d706e	3150	* Constants & macros for individual I2S_RMR bitfields
bogdanm	82:6473597d706e	3151	*/
bogdanm	82:6473597d706e	3152
bogdanm	82:6473597d706e	3153	/*!
bogdanm	82:6473597d706e	3154	* @name Register I2S_RMR, field RWM[31:0] (RW)
bogdanm	82:6473597d706e	3155	*
bogdanm	82:6473597d706e	3156	* Configures whether the receive word is masked (received data ignored and not
bogdanm	82:6473597d706e	3157	* written to receive FIFO) for the corresponding word in the frame.
bogdanm	82:6473597d706e	3158	*
bogdanm	82:6473597d706e	3159	* Values:
bogdanm	82:6473597d706e	3160	* - 0 - Word N is enabled.
bogdanm	82:6473597d706e	3161	* - 1 - Word N is masked.
bogdanm	82:6473597d706e	3162	*/
bogdanm	82:6473597d706e	3163	//@{
bogdanm	82:6473597d706e	3164	#define BP_I2S_RMR_RWM (0U) //!< Bit position for I2S_RMR_RWM.
bogdanm	82:6473597d706e	3165	#define BM_I2S_RMR_RWM (0xFFFFFFFFU) //!< Bit mask for I2S_RMR_RWM.
bogdanm	82:6473597d706e	3166	#define BS_I2S_RMR_RWM (32U) //!< Bit field size in bits for I2S_RMR_RWM.
bogdanm	82:6473597d706e	3167
bogdanm	82:6473597d706e	3168	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3169	//! @brief Read current value of the I2S_RMR_RWM field.
bogdanm	82:6473597d706e	3170	#define BR_I2S_RMR_RWM(x) (HW_I2S_RMR(x).U)
bogdanm	82:6473597d706e	3171	#endif
bogdanm	82:6473597d706e	3172
bogdanm	82:6473597d706e	3173	//! @brief Format value for bitfield I2S_RMR_RWM.
bogdanm	82:6473597d706e	3174	#define BF_I2S_RMR_RWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RMR_RWM), uint32_t) & BM_I2S_RMR_RWM)
bogdanm	82:6473597d706e	3175
bogdanm	82:6473597d706e	3176	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3177	//! @brief Set the RWM field to a new value.
bogdanm	82:6473597d706e	3178	#define BW_I2S_RMR_RWM(x, v) (HW_I2S_RMR_WR(x, v))
bogdanm	82:6473597d706e	3179	#endif
bogdanm	82:6473597d706e	3180	//@}
bogdanm	82:6473597d706e	3181
bogdanm	82:6473597d706e	3182	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3183	// HW_I2S_MCR - SAI MCLK Control Register
bogdanm	82:6473597d706e	3184	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3185
bogdanm	82:6473597d706e	3186	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3187	/*!
bogdanm	82:6473597d706e	3188	* @brief HW_I2S_MCR - SAI MCLK Control Register (RW)
bogdanm	82:6473597d706e	3189	*
bogdanm	82:6473597d706e	3190	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3191	*
bogdanm	82:6473597d706e	3192	* The MCLK Control Register (MCR) controls the clock source and direction of
bogdanm	82:6473597d706e	3193	* the audio master clock.
bogdanm	82:6473597d706e	3194	*/
bogdanm	82:6473597d706e	3195	typedef union _hw_i2s_mcr
bogdanm	82:6473597d706e	3196	{
bogdanm	82:6473597d706e	3197	uint32_t U;
bogdanm	82:6473597d706e	3198	struct _hw_i2s_mcr_bitfields
bogdanm	82:6473597d706e	3199	{
bogdanm	82:6473597d706e	3200	uint32_t RESERVED0 : 24; //!< [23:0]
bogdanm	82:6473597d706e	3201	uint32_t MICS : 2; //!< [25:24] MCLK Input Clock Select
bogdanm	82:6473597d706e	3202	uint32_t RESERVED1 : 4; //!< [29:26]
bogdanm	82:6473597d706e	3203	uint32_t MOE : 1; //!< [30] MCLK Output Enable
bogdanm	82:6473597d706e	3204	uint32_t DUF : 1; //!< [31] Divider Update Flag
bogdanm	82:6473597d706e	3205	} B;
bogdanm	82:6473597d706e	3206	} hw_i2s_mcr_t;
bogdanm	82:6473597d706e	3207	#endif
bogdanm	82:6473597d706e	3208
bogdanm	82:6473597d706e	3209	/*!
bogdanm	82:6473597d706e	3210	* @name Constants and macros for entire I2S_MCR register
bogdanm	82:6473597d706e	3211	*/
bogdanm	82:6473597d706e	3212	//@{
bogdanm	82:6473597d706e	3213	#define HW_I2S_MCR_ADDR(x) (REGS_I2S_BASE(x) + 0x100U)
bogdanm	82:6473597d706e	3214
bogdanm	82:6473597d706e	3215	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3216	#define HW_I2S_MCR(x) ((__IO hw_i2s_mcr_t ) HW_I2S_MCR_ADDR(x))
bogdanm	82:6473597d706e	3217	#define HW_I2S_MCR_RD(x) (HW_I2S_MCR(x).U)
bogdanm	82:6473597d706e	3218	#define HW_I2S_MCR_WR(x, v) (HW_I2S_MCR(x).U = (v))
bogdanm	82:6473597d706e	3219	#define HW_I2S_MCR_SET(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) \| (v)))
bogdanm	82:6473597d706e	3220	#define HW_I2S_MCR_CLR(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3221	#define HW_I2S_MCR_TOG(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3222	#endif
bogdanm	82:6473597d706e	3223	//@}
bogdanm	82:6473597d706e	3224
bogdanm	82:6473597d706e	3225	/*
bogdanm	82:6473597d706e	3226	* Constants & macros for individual I2S_MCR bitfields
bogdanm	82:6473597d706e	3227	*/
bogdanm	82:6473597d706e	3228
bogdanm	82:6473597d706e	3229	/*!
bogdanm	82:6473597d706e	3230	* @name Register I2S_MCR, field MICS[25:24] (RW)
bogdanm	82:6473597d706e	3231	*
bogdanm	82:6473597d706e	3232	* Selects the clock input to the MCLK divider. This field cannot be changed
bogdanm	82:6473597d706e	3233	* while the MCLK divider is enabled. See the chip configuration details for
bogdanm	82:6473597d706e	3234	* information about the connections to these inputs.
bogdanm	82:6473597d706e	3235	*
bogdanm	82:6473597d706e	3236	* Values:
bogdanm	82:6473597d706e	3237	* - 00 - MCLK divider input clock 0 selected.
bogdanm	82:6473597d706e	3238	* - 01 - MCLK divider input clock 1 selected.
bogdanm	82:6473597d706e	3239	* - 10 - MCLK divider input clock 2 selected.
bogdanm	82:6473597d706e	3240	* - 11 - MCLK divider input clock 3 selected.
bogdanm	82:6473597d706e	3241	*/
bogdanm	82:6473597d706e	3242	//@{
bogdanm	82:6473597d706e	3243	#define BP_I2S_MCR_MICS (24U) //!< Bit position for I2S_MCR_MICS.
bogdanm	82:6473597d706e	3244	#define BM_I2S_MCR_MICS (0x03000000U) //!< Bit mask for I2S_MCR_MICS.
bogdanm	82:6473597d706e	3245	#define BS_I2S_MCR_MICS (2U) //!< Bit field size in bits for I2S_MCR_MICS.
bogdanm	82:6473597d706e	3246
bogdanm	82:6473597d706e	3247	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3248	//! @brief Read current value of the I2S_MCR_MICS field.
bogdanm	82:6473597d706e	3249	#define BR_I2S_MCR_MICS(x) (HW_I2S_MCR(x).B.MICS)
bogdanm	82:6473597d706e	3250	#endif
bogdanm	82:6473597d706e	3251
bogdanm	82:6473597d706e	3252	//! @brief Format value for bitfield I2S_MCR_MICS.
bogdanm	82:6473597d706e	3253	#define BF_I2S_MCR_MICS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MCR_MICS), uint32_t) & BM_I2S_MCR_MICS)
bogdanm	82:6473597d706e	3254
bogdanm	82:6473597d706e	3255	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3256	//! @brief Set the MICS field to a new value.
bogdanm	82:6473597d706e	3257	#define BW_I2S_MCR_MICS(x, v) (HW_I2S_MCR_WR(x, (HW_I2S_MCR_RD(x) & ~BM_I2S_MCR_MICS) \| BF_I2S_MCR_MICS(v)))
bogdanm	82:6473597d706e	3258	#endif
bogdanm	82:6473597d706e	3259	//@}
bogdanm	82:6473597d706e	3260
bogdanm	82:6473597d706e	3261	/*!
bogdanm	82:6473597d706e	3262	* @name Register I2S_MCR, field MOE[30] (RW)
bogdanm	82:6473597d706e	3263	*
bogdanm	82:6473597d706e	3264	* Enables the MCLK divider and configures the MCLK signal pin as an output.
bogdanm	82:6473597d706e	3265	* When software clears this field, it remains set until the MCLK divider is fully
bogdanm	82:6473597d706e	3266	* disabled.
bogdanm	82:6473597d706e	3267	*
bogdanm	82:6473597d706e	3268	* Values:
bogdanm	82:6473597d706e	3269	* - 0 - MCLK signal pin is configured as an input that bypasses the MCLK
bogdanm	82:6473597d706e	3270	* divider.
bogdanm	82:6473597d706e	3271	* - 1 - MCLK signal pin is configured as an output from the MCLK divider and
bogdanm	82:6473597d706e	3272	* the MCLK divider is enabled.
bogdanm	82:6473597d706e	3273	*/
bogdanm	82:6473597d706e	3274	//@{
bogdanm	82:6473597d706e	3275	#define BP_I2S_MCR_MOE (30U) //!< Bit position for I2S_MCR_MOE.
bogdanm	82:6473597d706e	3276	#define BM_I2S_MCR_MOE (0x40000000U) //!< Bit mask for I2S_MCR_MOE.
bogdanm	82:6473597d706e	3277	#define BS_I2S_MCR_MOE (1U) //!< Bit field size in bits for I2S_MCR_MOE.
bogdanm	82:6473597d706e	3278
bogdanm	82:6473597d706e	3279	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3280	//! @brief Read current value of the I2S_MCR_MOE field.
bogdanm	82:6473597d706e	3281	#define BR_I2S_MCR_MOE(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE))
bogdanm	82:6473597d706e	3282	#endif
bogdanm	82:6473597d706e	3283
bogdanm	82:6473597d706e	3284	//! @brief Format value for bitfield I2S_MCR_MOE.
bogdanm	82:6473597d706e	3285	#define BF_I2S_MCR_MOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MCR_MOE), uint32_t) & BM_I2S_MCR_MOE)
bogdanm	82:6473597d706e	3286
bogdanm	82:6473597d706e	3287	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3288	//! @brief Set the MOE field to a new value.
bogdanm	82:6473597d706e	3289	#define BW_I2S_MCR_MOE(x, v) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE) = (v))
bogdanm	82:6473597d706e	3290	#endif
bogdanm	82:6473597d706e	3291	//@}
bogdanm	82:6473597d706e	3292
bogdanm	82:6473597d706e	3293	/*!
bogdanm	82:6473597d706e	3294	* @name Register I2S_MCR, field DUF[31] (RO)
bogdanm	82:6473597d706e	3295	*
bogdanm	82:6473597d706e	3296	* Provides the status of on-the-fly updates to the MCLK divider ratio.
bogdanm	82:6473597d706e	3297	*
bogdanm	82:6473597d706e	3298	* Values:
bogdanm	82:6473597d706e	3299	* - 0 - MCLK divider ratio is not being updated currently.
bogdanm	82:6473597d706e	3300	* - 1 - MCLK divider ratio is updating on-the-fly. Further updates to the MCLK
bogdanm	82:6473597d706e	3301	* divider ratio are blocked while this flag remains set.
bogdanm	82:6473597d706e	3302	*/
bogdanm	82:6473597d706e	3303	//@{
bogdanm	82:6473597d706e	3304	#define BP_I2S_MCR_DUF (31U) //!< Bit position for I2S_MCR_DUF.
bogdanm	82:6473597d706e	3305	#define BM_I2S_MCR_DUF (0x80000000U) //!< Bit mask for I2S_MCR_DUF.
bogdanm	82:6473597d706e	3306	#define BS_I2S_MCR_DUF (1U) //!< Bit field size in bits for I2S_MCR_DUF.
bogdanm	82:6473597d706e	3307
bogdanm	82:6473597d706e	3308	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3309	//! @brief Read current value of the I2S_MCR_DUF field.
bogdanm	82:6473597d706e	3310	#define BR_I2S_MCR_DUF(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_DUF))
bogdanm	82:6473597d706e	3311	#endif
bogdanm	82:6473597d706e	3312	//@}
bogdanm	82:6473597d706e	3313
bogdanm	82:6473597d706e	3314	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3315	// HW_I2S_MDR - SAI MCLK Divide Register
bogdanm	82:6473597d706e	3316	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3317
bogdanm	82:6473597d706e	3318	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3319	/*!
bogdanm	82:6473597d706e	3320	* @brief HW_I2S_MDR - SAI MCLK Divide Register (RW)
bogdanm	82:6473597d706e	3321	*
bogdanm	82:6473597d706e	3322	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3323	*
bogdanm	82:6473597d706e	3324	* The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
bogdanm	82:6473597d706e	3325	* MDR can be changed when the MCLK divider clock is enabled, additional writes
bogdanm	82:6473597d706e	3326	* to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
bogdanm	82:6473597d706e	3327	* divided clock is disabled do not set MCR[DUF].
bogdanm	82:6473597d706e	3328	*/
bogdanm	82:6473597d706e	3329	typedef union _hw_i2s_mdr
bogdanm	82:6473597d706e	3330	{
bogdanm	82:6473597d706e	3331	uint32_t U;
bogdanm	82:6473597d706e	3332	struct _hw_i2s_mdr_bitfields
bogdanm	82:6473597d706e	3333	{
bogdanm	82:6473597d706e	3334	uint32_t DIVIDE : 12; //!< [11:0] MCLK Divide
bogdanm	82:6473597d706e	3335	uint32_t FRACT : 8; //!< [19:12] MCLK Fraction
bogdanm	82:6473597d706e	3336	uint32_t RESERVED0 : 12; //!< [31:20]
bogdanm	82:6473597d706e	3337	} B;
bogdanm	82:6473597d706e	3338	} hw_i2s_mdr_t;
bogdanm	82:6473597d706e	3339	#endif
bogdanm	82:6473597d706e	3340
bogdanm	82:6473597d706e	3341	/*!
bogdanm	82:6473597d706e	3342	* @name Constants and macros for entire I2S_MDR register
bogdanm	82:6473597d706e	3343	*/
bogdanm	82:6473597d706e	3344	//@{
bogdanm	82:6473597d706e	3345	#define HW_I2S_MDR_ADDR(x) (REGS_I2S_BASE(x) + 0x104U)
bogdanm	82:6473597d706e	3346
bogdanm	82:6473597d706e	3347	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3348	#define HW_I2S_MDR(x) ((__IO hw_i2s_mdr_t ) HW_I2S_MDR_ADDR(x))
bogdanm	82:6473597d706e	3349	#define HW_I2S_MDR_RD(x) (HW_I2S_MDR(x).U)
bogdanm	82:6473597d706e	3350	#define HW_I2S_MDR_WR(x, v) (HW_I2S_MDR(x).U = (v))
bogdanm	82:6473597d706e	3351	#define HW_I2S_MDR_SET(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) \| (v)))
bogdanm	82:6473597d706e	3352	#define HW_I2S_MDR_CLR(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3353	#define HW_I2S_MDR_TOG(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3354	#endif
bogdanm	82:6473597d706e	3355	//@}
bogdanm	82:6473597d706e	3356
bogdanm	82:6473597d706e	3357	/*
bogdanm	82:6473597d706e	3358	* Constants & macros for individual I2S_MDR bitfields
bogdanm	82:6473597d706e	3359	*/
bogdanm	82:6473597d706e	3360
bogdanm	82:6473597d706e	3361	/*!
bogdanm	82:6473597d706e	3362	* @name Register I2S_MDR, field DIVIDE[11:0] (RW)
bogdanm	82:6473597d706e	3363	*
bogdanm	82:6473597d706e	3364	* Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
bogdanm	82:6473597d706e	3365	* 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
bogdanm	82:6473597d706e	3366	* DIVIDE field.
bogdanm	82:6473597d706e	3367	*/
bogdanm	82:6473597d706e	3368	//@{
bogdanm	82:6473597d706e	3369	#define BP_I2S_MDR_DIVIDE (0U) //!< Bit position for I2S_MDR_DIVIDE.
bogdanm	82:6473597d706e	3370	#define BM_I2S_MDR_DIVIDE (0x00000FFFU) //!< Bit mask for I2S_MDR_DIVIDE.
bogdanm	82:6473597d706e	3371	#define BS_I2S_MDR_DIVIDE (12U) //!< Bit field size in bits for I2S_MDR_DIVIDE.
bogdanm	82:6473597d706e	3372
bogdanm	82:6473597d706e	3373	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3374	//! @brief Read current value of the I2S_MDR_DIVIDE field.
bogdanm	82:6473597d706e	3375	#define BR_I2S_MDR_DIVIDE(x) (HW_I2S_MDR(x).B.DIVIDE)
bogdanm	82:6473597d706e	3376	#endif
bogdanm	82:6473597d706e	3377
bogdanm	82:6473597d706e	3378	//! @brief Format value for bitfield I2S_MDR_DIVIDE.
bogdanm	82:6473597d706e	3379	#define BF_I2S_MDR_DIVIDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MDR_DIVIDE), uint32_t) & BM_I2S_MDR_DIVIDE)
bogdanm	82:6473597d706e	3380
bogdanm	82:6473597d706e	3381	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3382	//! @brief Set the DIVIDE field to a new value.
bogdanm	82:6473597d706e	3383	#define BW_I2S_MDR_DIVIDE(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_DIVIDE) \| BF_I2S_MDR_DIVIDE(v)))
bogdanm	82:6473597d706e	3384	#endif
bogdanm	82:6473597d706e	3385	//@}
bogdanm	82:6473597d706e	3386
bogdanm	82:6473597d706e	3387	/*!
bogdanm	82:6473597d706e	3388	* @name Register I2S_MDR, field FRACT[19:12] (RW)
bogdanm	82:6473597d706e	3389	*
bogdanm	82:6473597d706e	3390	* Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
bogdanm	82:6473597d706e	3391	* 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
bogdanm	82:6473597d706e	3392	* DIVIDE field.
bogdanm	82:6473597d706e	3393	*/
bogdanm	82:6473597d706e	3394	//@{
bogdanm	82:6473597d706e	3395	#define BP_I2S_MDR_FRACT (12U) //!< Bit position for I2S_MDR_FRACT.
bogdanm	82:6473597d706e	3396	#define BM_I2S_MDR_FRACT (0x000FF000U) //!< Bit mask for I2S_MDR_FRACT.
bogdanm	82:6473597d706e	3397	#define BS_I2S_MDR_FRACT (8U) //!< Bit field size in bits for I2S_MDR_FRACT.
bogdanm	82:6473597d706e	3398
bogdanm	82:6473597d706e	3399	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3400	//! @brief Read current value of the I2S_MDR_FRACT field.
bogdanm	82:6473597d706e	3401	#define BR_I2S_MDR_FRACT(x) (HW_I2S_MDR(x).B.FRACT)
bogdanm	82:6473597d706e	3402	#endif
bogdanm	82:6473597d706e	3403
bogdanm	82:6473597d706e	3404	//! @brief Format value for bitfield I2S_MDR_FRACT.
bogdanm	82:6473597d706e	3405	#define BF_I2S_MDR_FRACT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MDR_FRACT), uint32_t) & BM_I2S_MDR_FRACT)
bogdanm	82:6473597d706e	3406
bogdanm	82:6473597d706e	3407	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3408	//! @brief Set the FRACT field to a new value.
bogdanm	82:6473597d706e	3409	#define BW_I2S_MDR_FRACT(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_FRACT) \| BF_I2S_MDR_FRACT(v)))
bogdanm	82:6473597d706e	3410	#endif
bogdanm	82:6473597d706e	3411	//@}
bogdanm	82:6473597d706e	3412
bogdanm	82:6473597d706e	3413	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3414	// hw_i2s_t - module struct
bogdanm	82:6473597d706e	3415	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3416	/*!
bogdanm	82:6473597d706e	3417	* @brief All I2S module registers.
bogdanm	82:6473597d706e	3418	*/
bogdanm	82:6473597d706e	3419	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3420	#pragma pack(1)
bogdanm	82:6473597d706e	3421	typedef struct _hw_i2s
bogdanm	82:6473597d706e	3422	{
bogdanm	82:6473597d706e	3423	__IO hw_i2s_tcsr_t TCSR; //!< [0x0] SAI Transmit Control Register
bogdanm	82:6473597d706e	3424	__IO hw_i2s_tcr1_t TCR1; //!< [0x4] SAI Transmit Configuration 1 Register
bogdanm	82:6473597d706e	3425	__IO hw_i2s_tcr2_t TCR2; //!< [0x8] SAI Transmit Configuration 2 Register
bogdanm	82:6473597d706e	3426	__IO hw_i2s_tcr3_t TCR3; //!< [0xC] SAI Transmit Configuration 3 Register
bogdanm	82:6473597d706e	3427	__IO hw_i2s_tcr4_t TCR4; //!< [0x10] SAI Transmit Configuration 4 Register
bogdanm	82:6473597d706e	3428	__IO hw_i2s_tcr5_t TCR5; //!< [0x14] SAI Transmit Configuration 5 Register
bogdanm	82:6473597d706e	3429	uint8_t _reserved0[8];
bogdanm	82:6473597d706e	3430	__O hw_i2s_tdrn_t TDRn[2]; //!< [0x20] SAI Transmit Data Register
bogdanm	82:6473597d706e	3431	uint8_t _reserved1[24];
bogdanm	82:6473597d706e	3432	__I hw_i2s_tfrn_t TFRn[2]; //!< [0x40] SAI Transmit FIFO Register
bogdanm	82:6473597d706e	3433	uint8_t _reserved2[24];
bogdanm	82:6473597d706e	3434	__IO hw_i2s_tmr_t TMR; //!< [0x60] SAI Transmit Mask Register
bogdanm	82:6473597d706e	3435	uint8_t _reserved3[28];
bogdanm	82:6473597d706e	3436	__IO hw_i2s_rcsr_t RCSR; //!< [0x80] SAI Receive Control Register
bogdanm	82:6473597d706e	3437	__IO hw_i2s_rcr1_t RCR1; //!< [0x84] SAI Receive Configuration 1 Register
bogdanm	82:6473597d706e	3438	__IO hw_i2s_rcr2_t RCR2; //!< [0x88] SAI Receive Configuration 2 Register
bogdanm	82:6473597d706e	3439	__IO hw_i2s_rcr3_t RCR3; //!< [0x8C] SAI Receive Configuration 3 Register
bogdanm	82:6473597d706e	3440	__IO hw_i2s_rcr4_t RCR4; //!< [0x90] SAI Receive Configuration 4 Register
bogdanm	82:6473597d706e	3441	__IO hw_i2s_rcr5_t RCR5; //!< [0x94] SAI Receive Configuration 5 Register
bogdanm	82:6473597d706e	3442	uint8_t _reserved4[8];
bogdanm	82:6473597d706e	3443	__I hw_i2s_rdrn_t RDRn[2]; //!< [0xA0] SAI Receive Data Register
bogdanm	82:6473597d706e	3444	uint8_t _reserved5[24];
bogdanm	82:6473597d706e	3445	__I hw_i2s_rfrn_t RFRn[2]; //!< [0xC0] SAI Receive FIFO Register
bogdanm	82:6473597d706e	3446	uint8_t _reserved6[24];
bogdanm	82:6473597d706e	3447	__IO hw_i2s_rmr_t RMR; //!< [0xE0] SAI Receive Mask Register
bogdanm	82:6473597d706e	3448	uint8_t _reserved7[28];
bogdanm	82:6473597d706e	3449	__IO hw_i2s_mcr_t MCR; //!< [0x100] SAI MCLK Control Register
bogdanm	82:6473597d706e	3450	__IO hw_i2s_mdr_t MDR; //!< [0x104] SAI MCLK Divide Register
bogdanm	82:6473597d706e	3451	} hw_i2s_t;
bogdanm	82:6473597d706e	3452	#pragma pack()
bogdanm	82:6473597d706e	3453
bogdanm	82:6473597d706e	3454	//! @brief Macro to access all I2S registers.
bogdanm	82:6473597d706e	3455	//! @param x I2S instance number.
bogdanm	82:6473597d706e	3456	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	3457	//! use the '&' operator, like <code>&HW_I2S(0)</code>.
bogdanm	82:6473597d706e	3458	#define HW_I2S(x) ((hw_i2s_t ) REGS_I2S_BASE(x))
bogdanm	82:6473597d706e	3459	#endif
bogdanm	82:6473597d706e	3460
bogdanm	82:6473597d706e	3461	#endif // __HW_I2S_REGISTERS_H__
bogdanm	82:6473597d706e	3462	// v22/130726/0.9
bogdanm	82:6473597d706e	3463	// EOF

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Type:	Library
Created:	05 Apr 2016
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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_i2s.h@82:6473597d706e, 2014-04-07 (annotated)

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