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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_cau.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:: bogdanm
Date:: Mon Apr 07 18:28:36 2014 +0100
Revision:: 82:6473597d706e

Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_CAU_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_CAU_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 CAU
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Memory Mapped Cryptographic Acceleration Unit (MMCAU)
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_CAU_DIRECT - Direct access register 0
bogdanm	82:6473597d706e	33	* - HW_CAU_LDR_CASR - Status register - Load Register command
bogdanm	82:6473597d706e	34	* - HW_CAU_LDR_CAA - Accumulator register - Load Register command
bogdanm	82:6473597d706e	35	* - HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command
bogdanm	82:6473597d706e	36	* - HW_CAU_STR_CASR - Status register - Store Register command
bogdanm	82:6473597d706e	37	* - HW_CAU_STR_CAA - Accumulator register - Store Register command
bogdanm	82:6473597d706e	38	* - HW_CAU_STR_CA - General Purpose Register 0 - Store Register command
bogdanm	82:6473597d706e	39	* - HW_CAU_ADR_CASR - Status register - Add Register command
bogdanm	82:6473597d706e	40	* - HW_CAU_ADR_CAA - Accumulator register - Add to register command
bogdanm	82:6473597d706e	41	* - HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command
bogdanm	82:6473597d706e	42	* - HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command
bogdanm	82:6473597d706e	43	* - HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
bogdanm	82:6473597d706e	44	* - HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
bogdanm	82:6473597d706e	45	* - HW_CAU_XOR_CASR - Status register - Exclusive Or command
bogdanm	82:6473597d706e	46	* - HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command
bogdanm	82:6473597d706e	47	* - HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
bogdanm	82:6473597d706e	48	* - HW_CAU_ROTL_CASR - Status register - Rotate Left command
bogdanm	82:6473597d706e	49	* - HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command
bogdanm	82:6473597d706e	50	* - HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
bogdanm	82:6473597d706e	51	* - HW_CAU_AESC_CASR - Status register - AES Column Operation command
bogdanm	82:6473597d706e	52	* - HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command
bogdanm	82:6473597d706e	53	* - HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
bogdanm	82:6473597d706e	54	* - HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
bogdanm	82:6473597d706e	55	* - HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
bogdanm	82:6473597d706e	56	* - HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
bogdanm	82:6473597d706e	57	*
bogdanm	82:6473597d706e	58	* - hw_cau_t - Struct containing all module registers.
bogdanm	82:6473597d706e	59	*/
bogdanm	82:6473597d706e	60
bogdanm	82:6473597d706e	61	//! @name Module base addresses
bogdanm	82:6473597d706e	62	//@{
bogdanm	82:6473597d706e	63	#ifndef REGS_CAU_BASE
bogdanm	82:6473597d706e	64	#define HW_CAU_INSTANCE_COUNT (1U) //!< Number of instances of the CAU module.
bogdanm	82:6473597d706e	65	#define REGS_CAU_BASE (0xE0081000U) //!< Base address for CAU.
bogdanm	82:6473597d706e	66	#endif
bogdanm	82:6473597d706e	67	//@}
bogdanm	82:6473597d706e	68
bogdanm	82:6473597d706e	69	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	70	// HW_CAU_DIRECT - Direct access register 0
bogdanm	82:6473597d706e	71	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	72
bogdanm	82:6473597d706e	73	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	74	/*!
bogdanm	82:6473597d706e	75	* @brief HW_CAU_DIRECT - Direct access register 0 (WO)
bogdanm	82:6473597d706e	76	*
bogdanm	82:6473597d706e	77	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	78	*/
bogdanm	82:6473597d706e	79	typedef union _hw_cau_direct
bogdanm	82:6473597d706e	80	{
bogdanm	82:6473597d706e	81	uint32_t U;
bogdanm	82:6473597d706e	82	struct _hw_cau_direct_bitfields
bogdanm	82:6473597d706e	83	{
bogdanm	82:6473597d706e	84	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	85	} B;
bogdanm	82:6473597d706e	86	} hw_cau_direct_t;
bogdanm	82:6473597d706e	87	#endif
bogdanm	82:6473597d706e	88
bogdanm	82:6473597d706e	89	/*!
bogdanm	82:6473597d706e	90	* @name Constants and macros for entire CAU_DIRECT register
bogdanm	82:6473597d706e	91	*/
bogdanm	82:6473597d706e	92	//@{
bogdanm	82:6473597d706e	93	#define HW_CAU_DIRECT_COUNT (16U)
bogdanm	82:6473597d706e	94
bogdanm	82:6473597d706e	95	#define HW_CAU_DIRECT_ADDR(n) (REGS_CAU_BASE + 0x0U + (0x4U * n))
bogdanm	82:6473597d706e	96
bogdanm	82:6473597d706e	97	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	98	#define HW_CAU_DIRECT(n) ((__O hw_cau_direct_t ) HW_CAU_DIRECT_ADDR(n))
bogdanm	82:6473597d706e	99	#define HW_CAU_DIRECT_WR(n, v) (HW_CAU_DIRECT(n).U = (v))
bogdanm	82:6473597d706e	100	#endif
bogdanm	82:6473597d706e	101	//@}
bogdanm	82:6473597d706e	102
bogdanm	82:6473597d706e	103	/*
bogdanm	82:6473597d706e	104	* Constants & macros for individual CAU_DIRECT bitfields
bogdanm	82:6473597d706e	105	*/
bogdanm	82:6473597d706e	106
bogdanm	82:6473597d706e	107	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	108	// HW_CAU_LDR_CASR - Status register - Load Register command
bogdanm	82:6473597d706e	109	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	110
bogdanm	82:6473597d706e	111	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	112	/*!
bogdanm	82:6473597d706e	113	* @brief HW_CAU_LDR_CASR - Status register - Load Register command (WO)
bogdanm	82:6473597d706e	114	*
bogdanm	82:6473597d706e	115	* Reset value: 0x20000000U
bogdanm	82:6473597d706e	116	*/
bogdanm	82:6473597d706e	117	typedef union _hw_cau_ldr_casr
bogdanm	82:6473597d706e	118	{
bogdanm	82:6473597d706e	119	uint32_t U;
bogdanm	82:6473597d706e	120	struct _hw_cau_ldr_casr_bitfields
bogdanm	82:6473597d706e	121	{
bogdanm	82:6473597d706e	122	uint32_t IC : 1; //!< [0]
bogdanm	82:6473597d706e	123	uint32_t DPE : 1; //!< [1]
bogdanm	82:6473597d706e	124	uint32_t RESERVED0 : 26; //!< [27:2]
bogdanm	82:6473597d706e	125	uint32_t VER : 4; //!< [31:28] CAU version
bogdanm	82:6473597d706e	126	} B;
bogdanm	82:6473597d706e	127	} hw_cau_ldr_casr_t;
bogdanm	82:6473597d706e	128	#endif
bogdanm	82:6473597d706e	129
bogdanm	82:6473597d706e	130	/*!
bogdanm	82:6473597d706e	131	* @name Constants and macros for entire CAU_LDR_CASR register
bogdanm	82:6473597d706e	132	*/
bogdanm	82:6473597d706e	133	//@{
bogdanm	82:6473597d706e	134	#define HW_CAU_LDR_CASR_ADDR (REGS_CAU_BASE + 0x840U)
bogdanm	82:6473597d706e	135
bogdanm	82:6473597d706e	136	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	137	#define HW_CAU_LDR_CASR ((__O hw_cau_ldr_casr_t ) HW_CAU_LDR_CASR_ADDR)
bogdanm	82:6473597d706e	138	#define HW_CAU_LDR_CASR_WR(v) (HW_CAU_LDR_CASR.U = (v))
bogdanm	82:6473597d706e	139	#endif
bogdanm	82:6473597d706e	140	//@}
bogdanm	82:6473597d706e	141
bogdanm	82:6473597d706e	142	/*
bogdanm	82:6473597d706e	143	* Constants & macros for individual CAU_LDR_CASR bitfields
bogdanm	82:6473597d706e	144	*/
bogdanm	82:6473597d706e	145
bogdanm	82:6473597d706e	146	/*!
bogdanm	82:6473597d706e	147	* @name Register CAU_LDR_CASR, field IC[0] (WO)
bogdanm	82:6473597d706e	148	*
bogdanm	82:6473597d706e	149	* Values:
bogdanm	82:6473597d706e	150	* - 0 - No illegal commands issued
bogdanm	82:6473597d706e	151	* - 1 - Illegal command issued
bogdanm	82:6473597d706e	152	*/
bogdanm	82:6473597d706e	153	//@{
bogdanm	82:6473597d706e	154	#define BP_CAU_LDR_CASR_IC (0U) //!< Bit position for CAU_LDR_CASR_IC.
bogdanm	82:6473597d706e	155	#define BM_CAU_LDR_CASR_IC (0x00000001U) //!< Bit mask for CAU_LDR_CASR_IC.
bogdanm	82:6473597d706e	156	#define BS_CAU_LDR_CASR_IC (1U) //!< Bit field size in bits for CAU_LDR_CASR_IC.
bogdanm	82:6473597d706e	157
bogdanm	82:6473597d706e	158	//! @brief Format value for bitfield CAU_LDR_CASR_IC.
bogdanm	82:6473597d706e	159	#define BF_CAU_LDR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_IC), uint32_t) & BM_CAU_LDR_CASR_IC)
bogdanm	82:6473597d706e	160	//@}
bogdanm	82:6473597d706e	161
bogdanm	82:6473597d706e	162	/*!
bogdanm	82:6473597d706e	163	* @name Register CAU_LDR_CASR, field DPE[1] (WO)
bogdanm	82:6473597d706e	164	*
bogdanm	82:6473597d706e	165	* Values:
bogdanm	82:6473597d706e	166	* - 0 - No error detected
bogdanm	82:6473597d706e	167	* - 1 - DES key parity error detected
bogdanm	82:6473597d706e	168	*/
bogdanm	82:6473597d706e	169	//@{
bogdanm	82:6473597d706e	170	#define BP_CAU_LDR_CASR_DPE (1U) //!< Bit position for CAU_LDR_CASR_DPE.
bogdanm	82:6473597d706e	171	#define BM_CAU_LDR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_LDR_CASR_DPE.
bogdanm	82:6473597d706e	172	#define BS_CAU_LDR_CASR_DPE (1U) //!< Bit field size in bits for CAU_LDR_CASR_DPE.
bogdanm	82:6473597d706e	173
bogdanm	82:6473597d706e	174	//! @brief Format value for bitfield CAU_LDR_CASR_DPE.
bogdanm	82:6473597d706e	175	#define BF_CAU_LDR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_DPE), uint32_t) & BM_CAU_LDR_CASR_DPE)
bogdanm	82:6473597d706e	176	//@}
bogdanm	82:6473597d706e	177
bogdanm	82:6473597d706e	178	/*!
bogdanm	82:6473597d706e	179	* @name Register CAU_LDR_CASR, field VER[31:28] (WO)
bogdanm	82:6473597d706e	180	*
bogdanm	82:6473597d706e	181	* Values:
bogdanm	82:6473597d706e	182	* - 0001 - Initial CAU version
bogdanm	82:6473597d706e	183	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
bogdanm	82:6473597d706e	184	* value on this device)
bogdanm	82:6473597d706e	185	*/
bogdanm	82:6473597d706e	186	//@{
bogdanm	82:6473597d706e	187	#define BP_CAU_LDR_CASR_VER (28U) //!< Bit position for CAU_LDR_CASR_VER.
bogdanm	82:6473597d706e	188	#define BM_CAU_LDR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_LDR_CASR_VER.
bogdanm	82:6473597d706e	189	#define BS_CAU_LDR_CASR_VER (4U) //!< Bit field size in bits for CAU_LDR_CASR_VER.
bogdanm	82:6473597d706e	190
bogdanm	82:6473597d706e	191	//! @brief Format value for bitfield CAU_LDR_CASR_VER.
bogdanm	82:6473597d706e	192	#define BF_CAU_LDR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_VER), uint32_t) & BM_CAU_LDR_CASR_VER)
bogdanm	82:6473597d706e	193	//@}
bogdanm	82:6473597d706e	194
bogdanm	82:6473597d706e	195	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	196	// HW_CAU_LDR_CAA - Accumulator register - Load Register command
bogdanm	82:6473597d706e	197	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	198
bogdanm	82:6473597d706e	199	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	200	/*!
bogdanm	82:6473597d706e	201	* @brief HW_CAU_LDR_CAA - Accumulator register - Load Register command (WO)
bogdanm	82:6473597d706e	202	*
bogdanm	82:6473597d706e	203	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	204	*/
bogdanm	82:6473597d706e	205	typedef union _hw_cau_ldr_caa
bogdanm	82:6473597d706e	206	{
bogdanm	82:6473597d706e	207	uint32_t U;
bogdanm	82:6473597d706e	208	struct _hw_cau_ldr_caa_bitfields
bogdanm	82:6473597d706e	209	{
bogdanm	82:6473597d706e	210	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	211	} B;
bogdanm	82:6473597d706e	212	} hw_cau_ldr_caa_t;
bogdanm	82:6473597d706e	213	#endif
bogdanm	82:6473597d706e	214
bogdanm	82:6473597d706e	215	/*!
bogdanm	82:6473597d706e	216	* @name Constants and macros for entire CAU_LDR_CAA register
bogdanm	82:6473597d706e	217	*/
bogdanm	82:6473597d706e	218	//@{
bogdanm	82:6473597d706e	219	#define HW_CAU_LDR_CAA_ADDR (REGS_CAU_BASE + 0x844U)
bogdanm	82:6473597d706e	220
bogdanm	82:6473597d706e	221	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	222	#define HW_CAU_LDR_CAA ((__O hw_cau_ldr_caa_t ) HW_CAU_LDR_CAA_ADDR)
bogdanm	82:6473597d706e	223	#define HW_CAU_LDR_CAA_WR(v) (HW_CAU_LDR_CAA.U = (v))
bogdanm	82:6473597d706e	224	#endif
bogdanm	82:6473597d706e	225	//@}
bogdanm	82:6473597d706e	226
bogdanm	82:6473597d706e	227	/*
bogdanm	82:6473597d706e	228	* Constants & macros for individual CAU_LDR_CAA bitfields
bogdanm	82:6473597d706e	229	*/
bogdanm	82:6473597d706e	230
bogdanm	82:6473597d706e	231	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	232	// HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command
bogdanm	82:6473597d706e	233	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	234
bogdanm	82:6473597d706e	235	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	236	/*!
bogdanm	82:6473597d706e	237	* @brief HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command (WO)
bogdanm	82:6473597d706e	238	*
bogdanm	82:6473597d706e	239	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	240	*/
bogdanm	82:6473597d706e	241	typedef union _hw_cau_ldr_ca
bogdanm	82:6473597d706e	242	{
bogdanm	82:6473597d706e	243	uint32_t U;
bogdanm	82:6473597d706e	244	struct _hw_cau_ldr_ca_bitfields
bogdanm	82:6473597d706e	245	{
bogdanm	82:6473597d706e	246	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	247	} B;
bogdanm	82:6473597d706e	248	} hw_cau_ldr_ca_t;
bogdanm	82:6473597d706e	249	#endif
bogdanm	82:6473597d706e	250
bogdanm	82:6473597d706e	251	/*!
bogdanm	82:6473597d706e	252	* @name Constants and macros for entire CAU_LDR_CA register
bogdanm	82:6473597d706e	253	*/
bogdanm	82:6473597d706e	254	//@{
bogdanm	82:6473597d706e	255	#define HW_CAU_LDR_CA_COUNT (9U)
bogdanm	82:6473597d706e	256
bogdanm	82:6473597d706e	257	#define HW_CAU_LDR_CA_ADDR(n) (REGS_CAU_BASE + 0x848U + (0x4U * n))
bogdanm	82:6473597d706e	258
bogdanm	82:6473597d706e	259	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	260	#define HW_CAU_LDR_CA(n) ((__O hw_cau_ldr_ca_t ) HW_CAU_LDR_CA_ADDR(n))
bogdanm	82:6473597d706e	261	#define HW_CAU_LDR_CA_WR(n, v) (HW_CAU_LDR_CA(n).U = (v))
bogdanm	82:6473597d706e	262	#endif
bogdanm	82:6473597d706e	263	//@}
bogdanm	82:6473597d706e	264
bogdanm	82:6473597d706e	265	/*
bogdanm	82:6473597d706e	266	* Constants & macros for individual CAU_LDR_CA bitfields
bogdanm	82:6473597d706e	267	*/
bogdanm	82:6473597d706e	268
bogdanm	82:6473597d706e	269	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	270	// HW_CAU_STR_CASR - Status register - Store Register command
bogdanm	82:6473597d706e	271	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	272
bogdanm	82:6473597d706e	273	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	274	/*!
bogdanm	82:6473597d706e	275	* @brief HW_CAU_STR_CASR - Status register - Store Register command (RO)
bogdanm	82:6473597d706e	276	*
bogdanm	82:6473597d706e	277	* Reset value: 0x20000000U
bogdanm	82:6473597d706e	278	*/
bogdanm	82:6473597d706e	279	typedef union _hw_cau_str_casr
bogdanm	82:6473597d706e	280	{
bogdanm	82:6473597d706e	281	uint32_t U;
bogdanm	82:6473597d706e	282	struct _hw_cau_str_casr_bitfields
bogdanm	82:6473597d706e	283	{
bogdanm	82:6473597d706e	284	uint32_t IC : 1; //!< [0]
bogdanm	82:6473597d706e	285	uint32_t DPE : 1; //!< [1]
bogdanm	82:6473597d706e	286	uint32_t RESERVED0 : 26; //!< [27:2]
bogdanm	82:6473597d706e	287	uint32_t VER : 4; //!< [31:28] CAU version
bogdanm	82:6473597d706e	288	} B;
bogdanm	82:6473597d706e	289	} hw_cau_str_casr_t;
bogdanm	82:6473597d706e	290	#endif
bogdanm	82:6473597d706e	291
bogdanm	82:6473597d706e	292	/*!
bogdanm	82:6473597d706e	293	* @name Constants and macros for entire CAU_STR_CASR register
bogdanm	82:6473597d706e	294	*/
bogdanm	82:6473597d706e	295	//@{
bogdanm	82:6473597d706e	296	#define HW_CAU_STR_CASR_ADDR (REGS_CAU_BASE + 0x880U)
bogdanm	82:6473597d706e	297
bogdanm	82:6473597d706e	298	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	299	#define HW_CAU_STR_CASR ((__I hw_cau_str_casr_t ) HW_CAU_STR_CASR_ADDR)
bogdanm	82:6473597d706e	300	#define HW_CAU_STR_CASR_RD() (HW_CAU_STR_CASR.U)
bogdanm	82:6473597d706e	301	#endif
bogdanm	82:6473597d706e	302	//@}
bogdanm	82:6473597d706e	303
bogdanm	82:6473597d706e	304	/*
bogdanm	82:6473597d706e	305	* Constants & macros for individual CAU_STR_CASR bitfields
bogdanm	82:6473597d706e	306	*/
bogdanm	82:6473597d706e	307
bogdanm	82:6473597d706e	308	/*!
bogdanm	82:6473597d706e	309	* @name Register CAU_STR_CASR, field IC[0] (RO)
bogdanm	82:6473597d706e	310	*
bogdanm	82:6473597d706e	311	* Values:
bogdanm	82:6473597d706e	312	* - 0 - No illegal commands issued
bogdanm	82:6473597d706e	313	* - 1 - Illegal command issued
bogdanm	82:6473597d706e	314	*/
bogdanm	82:6473597d706e	315	//@{
bogdanm	82:6473597d706e	316	#define BP_CAU_STR_CASR_IC (0U) //!< Bit position for CAU_STR_CASR_IC.
bogdanm	82:6473597d706e	317	#define BM_CAU_STR_CASR_IC (0x00000001U) //!< Bit mask for CAU_STR_CASR_IC.
bogdanm	82:6473597d706e	318	#define BS_CAU_STR_CASR_IC (1U) //!< Bit field size in bits for CAU_STR_CASR_IC.
bogdanm	82:6473597d706e	319
bogdanm	82:6473597d706e	320	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	321	//! @brief Read current value of the CAU_STR_CASR_IC field.
bogdanm	82:6473597d706e	322	#define BR_CAU_STR_CASR_IC (BITBAND_ACCESS32(HW_CAU_STR_CASR_ADDR, BP_CAU_STR_CASR_IC))
bogdanm	82:6473597d706e	323	#endif
bogdanm	82:6473597d706e	324	//@}
bogdanm	82:6473597d706e	325
bogdanm	82:6473597d706e	326	/*!
bogdanm	82:6473597d706e	327	* @name Register CAU_STR_CASR, field DPE[1] (RO)
bogdanm	82:6473597d706e	328	*
bogdanm	82:6473597d706e	329	* Values:
bogdanm	82:6473597d706e	330	* - 0 - No error detected
bogdanm	82:6473597d706e	331	* - 1 - DES key parity error detected
bogdanm	82:6473597d706e	332	*/
bogdanm	82:6473597d706e	333	//@{
bogdanm	82:6473597d706e	334	#define BP_CAU_STR_CASR_DPE (1U) //!< Bit position for CAU_STR_CASR_DPE.
bogdanm	82:6473597d706e	335	#define BM_CAU_STR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_STR_CASR_DPE.
bogdanm	82:6473597d706e	336	#define BS_CAU_STR_CASR_DPE (1U) //!< Bit field size in bits for CAU_STR_CASR_DPE.
bogdanm	82:6473597d706e	337
bogdanm	82:6473597d706e	338	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	339	//! @brief Read current value of the CAU_STR_CASR_DPE field.
bogdanm	82:6473597d706e	340	#define BR_CAU_STR_CASR_DPE (BITBAND_ACCESS32(HW_CAU_STR_CASR_ADDR, BP_CAU_STR_CASR_DPE))
bogdanm	82:6473597d706e	341	#endif
bogdanm	82:6473597d706e	342	//@}
bogdanm	82:6473597d706e	343
bogdanm	82:6473597d706e	344	/*!
bogdanm	82:6473597d706e	345	* @name Register CAU_STR_CASR, field VER[31:28] (RO)
bogdanm	82:6473597d706e	346	*
bogdanm	82:6473597d706e	347	* Values:
bogdanm	82:6473597d706e	348	* - 0001 - Initial CAU version
bogdanm	82:6473597d706e	349	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
bogdanm	82:6473597d706e	350	* value on this device)
bogdanm	82:6473597d706e	351	*/
bogdanm	82:6473597d706e	352	//@{
bogdanm	82:6473597d706e	353	#define BP_CAU_STR_CASR_VER (28U) //!< Bit position for CAU_STR_CASR_VER.
bogdanm	82:6473597d706e	354	#define BM_CAU_STR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_STR_CASR_VER.
bogdanm	82:6473597d706e	355	#define BS_CAU_STR_CASR_VER (4U) //!< Bit field size in bits for CAU_STR_CASR_VER.
bogdanm	82:6473597d706e	356
bogdanm	82:6473597d706e	357	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	358	//! @brief Read current value of the CAU_STR_CASR_VER field.
bogdanm	82:6473597d706e	359	#define BR_CAU_STR_CASR_VER (HW_CAU_STR_CASR.B.VER)
bogdanm	82:6473597d706e	360	#endif
bogdanm	82:6473597d706e	361	//@}
bogdanm	82:6473597d706e	362
bogdanm	82:6473597d706e	363	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	364	// HW_CAU_STR_CAA - Accumulator register - Store Register command
bogdanm	82:6473597d706e	365	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	366
bogdanm	82:6473597d706e	367	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	368	/*!
bogdanm	82:6473597d706e	369	* @brief HW_CAU_STR_CAA - Accumulator register - Store Register command (RO)
bogdanm	82:6473597d706e	370	*
bogdanm	82:6473597d706e	371	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	372	*/
bogdanm	82:6473597d706e	373	typedef union _hw_cau_str_caa
bogdanm	82:6473597d706e	374	{
bogdanm	82:6473597d706e	375	uint32_t U;
bogdanm	82:6473597d706e	376	struct _hw_cau_str_caa_bitfields
bogdanm	82:6473597d706e	377	{
bogdanm	82:6473597d706e	378	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	379	} B;
bogdanm	82:6473597d706e	380	} hw_cau_str_caa_t;
bogdanm	82:6473597d706e	381	#endif
bogdanm	82:6473597d706e	382
bogdanm	82:6473597d706e	383	/*!
bogdanm	82:6473597d706e	384	* @name Constants and macros for entire CAU_STR_CAA register
bogdanm	82:6473597d706e	385	*/
bogdanm	82:6473597d706e	386	//@{
bogdanm	82:6473597d706e	387	#define HW_CAU_STR_CAA_ADDR (REGS_CAU_BASE + 0x884U)
bogdanm	82:6473597d706e	388
bogdanm	82:6473597d706e	389	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	390	#define HW_CAU_STR_CAA ((__I hw_cau_str_caa_t ) HW_CAU_STR_CAA_ADDR)
bogdanm	82:6473597d706e	391	#define HW_CAU_STR_CAA_RD() (HW_CAU_STR_CAA.U)
bogdanm	82:6473597d706e	392	#endif
bogdanm	82:6473597d706e	393	//@}
bogdanm	82:6473597d706e	394
bogdanm	82:6473597d706e	395	/*
bogdanm	82:6473597d706e	396	* Constants & macros for individual CAU_STR_CAA bitfields
bogdanm	82:6473597d706e	397	*/
bogdanm	82:6473597d706e	398
bogdanm	82:6473597d706e	399	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	400	// HW_CAU_STR_CA - General Purpose Register 0 - Store Register command
bogdanm	82:6473597d706e	401	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	402
bogdanm	82:6473597d706e	403	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	404	/*!
bogdanm	82:6473597d706e	405	* @brief HW_CAU_STR_CA - General Purpose Register 0 - Store Register command (RO)
bogdanm	82:6473597d706e	406	*
bogdanm	82:6473597d706e	407	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	408	*/
bogdanm	82:6473597d706e	409	typedef union _hw_cau_str_ca
bogdanm	82:6473597d706e	410	{
bogdanm	82:6473597d706e	411	uint32_t U;
bogdanm	82:6473597d706e	412	struct _hw_cau_str_ca_bitfields
bogdanm	82:6473597d706e	413	{
bogdanm	82:6473597d706e	414	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	415	} B;
bogdanm	82:6473597d706e	416	} hw_cau_str_ca_t;
bogdanm	82:6473597d706e	417	#endif
bogdanm	82:6473597d706e	418
bogdanm	82:6473597d706e	419	/*!
bogdanm	82:6473597d706e	420	* @name Constants and macros for entire CAU_STR_CA register
bogdanm	82:6473597d706e	421	*/
bogdanm	82:6473597d706e	422	//@{
bogdanm	82:6473597d706e	423	#define HW_CAU_STR_CA_COUNT (9U)
bogdanm	82:6473597d706e	424
bogdanm	82:6473597d706e	425	#define HW_CAU_STR_CA_ADDR(n) (REGS_CAU_BASE + 0x888U + (0x4U * n))
bogdanm	82:6473597d706e	426
bogdanm	82:6473597d706e	427	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	428	#define HW_CAU_STR_CA(n) ((__I hw_cau_str_ca_t ) HW_CAU_STR_CA_ADDR(n))
bogdanm	82:6473597d706e	429	#define HW_CAU_STR_CA_RD(n) (HW_CAU_STR_CA(n).U)
bogdanm	82:6473597d706e	430	#endif
bogdanm	82:6473597d706e	431	//@}
bogdanm	82:6473597d706e	432
bogdanm	82:6473597d706e	433	/*
bogdanm	82:6473597d706e	434	* Constants & macros for individual CAU_STR_CA bitfields
bogdanm	82:6473597d706e	435	*/
bogdanm	82:6473597d706e	436
bogdanm	82:6473597d706e	437	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	438	// HW_CAU_ADR_CASR - Status register - Add Register command
bogdanm	82:6473597d706e	439	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	440
bogdanm	82:6473597d706e	441	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	442	/*!
bogdanm	82:6473597d706e	443	* @brief HW_CAU_ADR_CASR - Status register - Add Register command (WO)
bogdanm	82:6473597d706e	444	*
bogdanm	82:6473597d706e	445	* Reset value: 0x20000000U
bogdanm	82:6473597d706e	446	*/
bogdanm	82:6473597d706e	447	typedef union _hw_cau_adr_casr
bogdanm	82:6473597d706e	448	{
bogdanm	82:6473597d706e	449	uint32_t U;
bogdanm	82:6473597d706e	450	struct _hw_cau_adr_casr_bitfields
bogdanm	82:6473597d706e	451	{
bogdanm	82:6473597d706e	452	uint32_t IC : 1; //!< [0]
bogdanm	82:6473597d706e	453	uint32_t DPE : 1; //!< [1]
bogdanm	82:6473597d706e	454	uint32_t RESERVED0 : 26; //!< [27:2]
bogdanm	82:6473597d706e	455	uint32_t VER : 4; //!< [31:28] CAU version
bogdanm	82:6473597d706e	456	} B;
bogdanm	82:6473597d706e	457	} hw_cau_adr_casr_t;
bogdanm	82:6473597d706e	458	#endif
bogdanm	82:6473597d706e	459
bogdanm	82:6473597d706e	460	/*!
bogdanm	82:6473597d706e	461	* @name Constants and macros for entire CAU_ADR_CASR register
bogdanm	82:6473597d706e	462	*/
bogdanm	82:6473597d706e	463	//@{
bogdanm	82:6473597d706e	464	#define HW_CAU_ADR_CASR_ADDR (REGS_CAU_BASE + 0x8C0U)
bogdanm	82:6473597d706e	465
bogdanm	82:6473597d706e	466	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	467	#define HW_CAU_ADR_CASR ((__O hw_cau_adr_casr_t ) HW_CAU_ADR_CASR_ADDR)
bogdanm	82:6473597d706e	468	#define HW_CAU_ADR_CASR_WR(v) (HW_CAU_ADR_CASR.U = (v))
bogdanm	82:6473597d706e	469	#endif
bogdanm	82:6473597d706e	470	//@}
bogdanm	82:6473597d706e	471
bogdanm	82:6473597d706e	472	/*
bogdanm	82:6473597d706e	473	* Constants & macros for individual CAU_ADR_CASR bitfields
bogdanm	82:6473597d706e	474	*/
bogdanm	82:6473597d706e	475
bogdanm	82:6473597d706e	476	/*!
bogdanm	82:6473597d706e	477	* @name Register CAU_ADR_CASR, field IC[0] (WO)
bogdanm	82:6473597d706e	478	*
bogdanm	82:6473597d706e	479	* Values:
bogdanm	82:6473597d706e	480	* - 0 - No illegal commands issued
bogdanm	82:6473597d706e	481	* - 1 - Illegal command issued
bogdanm	82:6473597d706e	482	*/
bogdanm	82:6473597d706e	483	//@{
bogdanm	82:6473597d706e	484	#define BP_CAU_ADR_CASR_IC (0U) //!< Bit position for CAU_ADR_CASR_IC.
bogdanm	82:6473597d706e	485	#define BM_CAU_ADR_CASR_IC (0x00000001U) //!< Bit mask for CAU_ADR_CASR_IC.
bogdanm	82:6473597d706e	486	#define BS_CAU_ADR_CASR_IC (1U) //!< Bit field size in bits for CAU_ADR_CASR_IC.
bogdanm	82:6473597d706e	487
bogdanm	82:6473597d706e	488	//! @brief Format value for bitfield CAU_ADR_CASR_IC.
bogdanm	82:6473597d706e	489	#define BF_CAU_ADR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_IC), uint32_t) & BM_CAU_ADR_CASR_IC)
bogdanm	82:6473597d706e	490	//@}
bogdanm	82:6473597d706e	491
bogdanm	82:6473597d706e	492	/*!
bogdanm	82:6473597d706e	493	* @name Register CAU_ADR_CASR, field DPE[1] (WO)
bogdanm	82:6473597d706e	494	*
bogdanm	82:6473597d706e	495	* Values:
bogdanm	82:6473597d706e	496	* - 0 - No error detected
bogdanm	82:6473597d706e	497	* - 1 - DES key parity error detected
bogdanm	82:6473597d706e	498	*/
bogdanm	82:6473597d706e	499	//@{
bogdanm	82:6473597d706e	500	#define BP_CAU_ADR_CASR_DPE (1U) //!< Bit position for CAU_ADR_CASR_DPE.
bogdanm	82:6473597d706e	501	#define BM_CAU_ADR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_ADR_CASR_DPE.
bogdanm	82:6473597d706e	502	#define BS_CAU_ADR_CASR_DPE (1U) //!< Bit field size in bits for CAU_ADR_CASR_DPE.
bogdanm	82:6473597d706e	503
bogdanm	82:6473597d706e	504	//! @brief Format value for bitfield CAU_ADR_CASR_DPE.
bogdanm	82:6473597d706e	505	#define BF_CAU_ADR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_DPE), uint32_t) & BM_CAU_ADR_CASR_DPE)
bogdanm	82:6473597d706e	506	//@}
bogdanm	82:6473597d706e	507
bogdanm	82:6473597d706e	508	/*!
bogdanm	82:6473597d706e	509	* @name Register CAU_ADR_CASR, field VER[31:28] (WO)
bogdanm	82:6473597d706e	510	*
bogdanm	82:6473597d706e	511	* Values:
bogdanm	82:6473597d706e	512	* - 0001 - Initial CAU version
bogdanm	82:6473597d706e	513	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
bogdanm	82:6473597d706e	514	* value on this device)
bogdanm	82:6473597d706e	515	*/
bogdanm	82:6473597d706e	516	//@{
bogdanm	82:6473597d706e	517	#define BP_CAU_ADR_CASR_VER (28U) //!< Bit position for CAU_ADR_CASR_VER.
bogdanm	82:6473597d706e	518	#define BM_CAU_ADR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_ADR_CASR_VER.
bogdanm	82:6473597d706e	519	#define BS_CAU_ADR_CASR_VER (4U) //!< Bit field size in bits for CAU_ADR_CASR_VER.
bogdanm	82:6473597d706e	520
bogdanm	82:6473597d706e	521	//! @brief Format value for bitfield CAU_ADR_CASR_VER.
bogdanm	82:6473597d706e	522	#define BF_CAU_ADR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_VER), uint32_t) & BM_CAU_ADR_CASR_VER)
bogdanm	82:6473597d706e	523	//@}
bogdanm	82:6473597d706e	524
bogdanm	82:6473597d706e	525	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	526	// HW_CAU_ADR_CAA - Accumulator register - Add to register command
bogdanm	82:6473597d706e	527	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	528
bogdanm	82:6473597d706e	529	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	530	/*!
bogdanm	82:6473597d706e	531	* @brief HW_CAU_ADR_CAA - Accumulator register - Add to register command (WO)
bogdanm	82:6473597d706e	532	*
bogdanm	82:6473597d706e	533	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	534	*/
bogdanm	82:6473597d706e	535	typedef union _hw_cau_adr_caa
bogdanm	82:6473597d706e	536	{
bogdanm	82:6473597d706e	537	uint32_t U;
bogdanm	82:6473597d706e	538	struct _hw_cau_adr_caa_bitfields
bogdanm	82:6473597d706e	539	{
bogdanm	82:6473597d706e	540	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	541	} B;
bogdanm	82:6473597d706e	542	} hw_cau_adr_caa_t;
bogdanm	82:6473597d706e	543	#endif
bogdanm	82:6473597d706e	544
bogdanm	82:6473597d706e	545	/*!
bogdanm	82:6473597d706e	546	* @name Constants and macros for entire CAU_ADR_CAA register
bogdanm	82:6473597d706e	547	*/
bogdanm	82:6473597d706e	548	//@{
bogdanm	82:6473597d706e	549	#define HW_CAU_ADR_CAA_ADDR (REGS_CAU_BASE + 0x8C4U)
bogdanm	82:6473597d706e	550
bogdanm	82:6473597d706e	551	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	552	#define HW_CAU_ADR_CAA ((__O hw_cau_adr_caa_t ) HW_CAU_ADR_CAA_ADDR)
bogdanm	82:6473597d706e	553	#define HW_CAU_ADR_CAA_WR(v) (HW_CAU_ADR_CAA.U = (v))
bogdanm	82:6473597d706e	554	#endif
bogdanm	82:6473597d706e	555	//@}
bogdanm	82:6473597d706e	556
bogdanm	82:6473597d706e	557	/*
bogdanm	82:6473597d706e	558	* Constants & macros for individual CAU_ADR_CAA bitfields
bogdanm	82:6473597d706e	559	*/
bogdanm	82:6473597d706e	560
bogdanm	82:6473597d706e	561	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	562	// HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command
bogdanm	82:6473597d706e	563	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	564
bogdanm	82:6473597d706e	565	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	566	/*!
bogdanm	82:6473597d706e	567	* @brief HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command (WO)
bogdanm	82:6473597d706e	568	*
bogdanm	82:6473597d706e	569	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	570	*/
bogdanm	82:6473597d706e	571	typedef union _hw_cau_adr_ca
bogdanm	82:6473597d706e	572	{
bogdanm	82:6473597d706e	573	uint32_t U;
bogdanm	82:6473597d706e	574	struct _hw_cau_adr_ca_bitfields
bogdanm	82:6473597d706e	575	{
bogdanm	82:6473597d706e	576	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	577	} B;
bogdanm	82:6473597d706e	578	} hw_cau_adr_ca_t;
bogdanm	82:6473597d706e	579	#endif
bogdanm	82:6473597d706e	580
bogdanm	82:6473597d706e	581	/*!
bogdanm	82:6473597d706e	582	* @name Constants and macros for entire CAU_ADR_CA register
bogdanm	82:6473597d706e	583	*/
bogdanm	82:6473597d706e	584	//@{
bogdanm	82:6473597d706e	585	#define HW_CAU_ADR_CA_COUNT (9U)
bogdanm	82:6473597d706e	586
bogdanm	82:6473597d706e	587	#define HW_CAU_ADR_CA_ADDR(n) (REGS_CAU_BASE + 0x8C8U + (0x4U * n))
bogdanm	82:6473597d706e	588
bogdanm	82:6473597d706e	589	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	590	#define HW_CAU_ADR_CA(n) ((__O hw_cau_adr_ca_t ) HW_CAU_ADR_CA_ADDR(n))
bogdanm	82:6473597d706e	591	#define HW_CAU_ADR_CA_WR(n, v) (HW_CAU_ADR_CA(n).U = (v))
bogdanm	82:6473597d706e	592	#endif
bogdanm	82:6473597d706e	593	//@}
bogdanm	82:6473597d706e	594
bogdanm	82:6473597d706e	595	/*
bogdanm	82:6473597d706e	596	* Constants & macros for individual CAU_ADR_CA bitfields
bogdanm	82:6473597d706e	597	*/
bogdanm	82:6473597d706e	598
bogdanm	82:6473597d706e	599	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	600	// HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command
bogdanm	82:6473597d706e	601	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	602
bogdanm	82:6473597d706e	603	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	604	/*!
bogdanm	82:6473597d706e	605	* @brief HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command (WO)
bogdanm	82:6473597d706e	606	*
bogdanm	82:6473597d706e	607	* Reset value: 0x20000000U
bogdanm	82:6473597d706e	608	*/
bogdanm	82:6473597d706e	609	typedef union _hw_cau_radr_casr
bogdanm	82:6473597d706e	610	{
bogdanm	82:6473597d706e	611	uint32_t U;
bogdanm	82:6473597d706e	612	struct _hw_cau_radr_casr_bitfields
bogdanm	82:6473597d706e	613	{
bogdanm	82:6473597d706e	614	uint32_t IC : 1; //!< [0]
bogdanm	82:6473597d706e	615	uint32_t DPE : 1; //!< [1]
bogdanm	82:6473597d706e	616	uint32_t RESERVED0 : 26; //!< [27:2]
bogdanm	82:6473597d706e	617	uint32_t VER : 4; //!< [31:28] CAU version
bogdanm	82:6473597d706e	618	} B;
bogdanm	82:6473597d706e	619	} hw_cau_radr_casr_t;
bogdanm	82:6473597d706e	620	#endif
bogdanm	82:6473597d706e	621
bogdanm	82:6473597d706e	622	/*!
bogdanm	82:6473597d706e	623	* @name Constants and macros for entire CAU_RADR_CASR register
bogdanm	82:6473597d706e	624	*/
bogdanm	82:6473597d706e	625	//@{
bogdanm	82:6473597d706e	626	#define HW_CAU_RADR_CASR_ADDR (REGS_CAU_BASE + 0x900U)
bogdanm	82:6473597d706e	627
bogdanm	82:6473597d706e	628	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	629	#define HW_CAU_RADR_CASR ((__O hw_cau_radr_casr_t ) HW_CAU_RADR_CASR_ADDR)
bogdanm	82:6473597d706e	630	#define HW_CAU_RADR_CASR_WR(v) (HW_CAU_RADR_CASR.U = (v))
bogdanm	82:6473597d706e	631	#endif
bogdanm	82:6473597d706e	632	//@}
bogdanm	82:6473597d706e	633
bogdanm	82:6473597d706e	634	/*
bogdanm	82:6473597d706e	635	* Constants & macros for individual CAU_RADR_CASR bitfields
bogdanm	82:6473597d706e	636	*/
bogdanm	82:6473597d706e	637
bogdanm	82:6473597d706e	638	/*!
bogdanm	82:6473597d706e	639	* @name Register CAU_RADR_CASR, field IC[0] (WO)
bogdanm	82:6473597d706e	640	*
bogdanm	82:6473597d706e	641	* Values:
bogdanm	82:6473597d706e	642	* - 0 - No illegal commands issued
bogdanm	82:6473597d706e	643	* - 1 - Illegal command issued
bogdanm	82:6473597d706e	644	*/
bogdanm	82:6473597d706e	645	//@{
bogdanm	82:6473597d706e	646	#define BP_CAU_RADR_CASR_IC (0U) //!< Bit position for CAU_RADR_CASR_IC.
bogdanm	82:6473597d706e	647	#define BM_CAU_RADR_CASR_IC (0x00000001U) //!< Bit mask for CAU_RADR_CASR_IC.
bogdanm	82:6473597d706e	648	#define BS_CAU_RADR_CASR_IC (1U) //!< Bit field size in bits for CAU_RADR_CASR_IC.
bogdanm	82:6473597d706e	649
bogdanm	82:6473597d706e	650	//! @brief Format value for bitfield CAU_RADR_CASR_IC.
bogdanm	82:6473597d706e	651	#define BF_CAU_RADR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_IC), uint32_t) & BM_CAU_RADR_CASR_IC)
bogdanm	82:6473597d706e	652	//@}
bogdanm	82:6473597d706e	653
bogdanm	82:6473597d706e	654	/*!
bogdanm	82:6473597d706e	655	* @name Register CAU_RADR_CASR, field DPE[1] (WO)
bogdanm	82:6473597d706e	656	*
bogdanm	82:6473597d706e	657	* Values:
bogdanm	82:6473597d706e	658	* - 0 - No error detected
bogdanm	82:6473597d706e	659	* - 1 - DES key parity error detected
bogdanm	82:6473597d706e	660	*/
bogdanm	82:6473597d706e	661	//@{
bogdanm	82:6473597d706e	662	#define BP_CAU_RADR_CASR_DPE (1U) //!< Bit position for CAU_RADR_CASR_DPE.
bogdanm	82:6473597d706e	663	#define BM_CAU_RADR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_RADR_CASR_DPE.
bogdanm	82:6473597d706e	664	#define BS_CAU_RADR_CASR_DPE (1U) //!< Bit field size in bits for CAU_RADR_CASR_DPE.
bogdanm	82:6473597d706e	665
bogdanm	82:6473597d706e	666	//! @brief Format value for bitfield CAU_RADR_CASR_DPE.
bogdanm	82:6473597d706e	667	#define BF_CAU_RADR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_DPE), uint32_t) & BM_CAU_RADR_CASR_DPE)
bogdanm	82:6473597d706e	668	//@}
bogdanm	82:6473597d706e	669
bogdanm	82:6473597d706e	670	/*!
bogdanm	82:6473597d706e	671	* @name Register CAU_RADR_CASR, field VER[31:28] (WO)
bogdanm	82:6473597d706e	672	*
bogdanm	82:6473597d706e	673	* Values:
bogdanm	82:6473597d706e	674	* - 0001 - Initial CAU version
bogdanm	82:6473597d706e	675	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
bogdanm	82:6473597d706e	676	* value on this device)
bogdanm	82:6473597d706e	677	*/
bogdanm	82:6473597d706e	678	//@{
bogdanm	82:6473597d706e	679	#define BP_CAU_RADR_CASR_VER (28U) //!< Bit position for CAU_RADR_CASR_VER.
bogdanm	82:6473597d706e	680	#define BM_CAU_RADR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_RADR_CASR_VER.
bogdanm	82:6473597d706e	681	#define BS_CAU_RADR_CASR_VER (4U) //!< Bit field size in bits for CAU_RADR_CASR_VER.
bogdanm	82:6473597d706e	682
bogdanm	82:6473597d706e	683	//! @brief Format value for bitfield CAU_RADR_CASR_VER.
bogdanm	82:6473597d706e	684	#define BF_CAU_RADR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_VER), uint32_t) & BM_CAU_RADR_CASR_VER)
bogdanm	82:6473597d706e	685	//@}
bogdanm	82:6473597d706e	686
bogdanm	82:6473597d706e	687	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	688	// HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
bogdanm	82:6473597d706e	689	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	690
bogdanm	82:6473597d706e	691	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	692	/*!
bogdanm	82:6473597d706e	693	* @brief HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command (WO)
bogdanm	82:6473597d706e	694	*
bogdanm	82:6473597d706e	695	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	696	*/
bogdanm	82:6473597d706e	697	typedef union _hw_cau_radr_caa
bogdanm	82:6473597d706e	698	{
bogdanm	82:6473597d706e	699	uint32_t U;
bogdanm	82:6473597d706e	700	struct _hw_cau_radr_caa_bitfields
bogdanm	82:6473597d706e	701	{
bogdanm	82:6473597d706e	702	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	703	} B;
bogdanm	82:6473597d706e	704	} hw_cau_radr_caa_t;
bogdanm	82:6473597d706e	705	#endif
bogdanm	82:6473597d706e	706
bogdanm	82:6473597d706e	707	/*!
bogdanm	82:6473597d706e	708	* @name Constants and macros for entire CAU_RADR_CAA register
bogdanm	82:6473597d706e	709	*/
bogdanm	82:6473597d706e	710	//@{
bogdanm	82:6473597d706e	711	#define HW_CAU_RADR_CAA_ADDR (REGS_CAU_BASE + 0x904U)
bogdanm	82:6473597d706e	712
bogdanm	82:6473597d706e	713	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	714	#define HW_CAU_RADR_CAA ((__O hw_cau_radr_caa_t ) HW_CAU_RADR_CAA_ADDR)
bogdanm	82:6473597d706e	715	#define HW_CAU_RADR_CAA_WR(v) (HW_CAU_RADR_CAA.U = (v))
bogdanm	82:6473597d706e	716	#endif
bogdanm	82:6473597d706e	717	//@}
bogdanm	82:6473597d706e	718
bogdanm	82:6473597d706e	719	/*
bogdanm	82:6473597d706e	720	* Constants & macros for individual CAU_RADR_CAA bitfields
bogdanm	82:6473597d706e	721	*/
bogdanm	82:6473597d706e	722
bogdanm	82:6473597d706e	723	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	724	// HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
bogdanm	82:6473597d706e	725	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	726
bogdanm	82:6473597d706e	727	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	728	/*!
bogdanm	82:6473597d706e	729	* @brief HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command (WO)
bogdanm	82:6473597d706e	730	*
bogdanm	82:6473597d706e	731	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	732	*/
bogdanm	82:6473597d706e	733	typedef union _hw_cau_radr_ca
bogdanm	82:6473597d706e	734	{
bogdanm	82:6473597d706e	735	uint32_t U;
bogdanm	82:6473597d706e	736	struct _hw_cau_radr_ca_bitfields
bogdanm	82:6473597d706e	737	{
bogdanm	82:6473597d706e	738	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	739	} B;
bogdanm	82:6473597d706e	740	} hw_cau_radr_ca_t;
bogdanm	82:6473597d706e	741	#endif
bogdanm	82:6473597d706e	742
bogdanm	82:6473597d706e	743	/*!
bogdanm	82:6473597d706e	744	* @name Constants and macros for entire CAU_RADR_CA register
bogdanm	82:6473597d706e	745	*/
bogdanm	82:6473597d706e	746	//@{
bogdanm	82:6473597d706e	747	#define HW_CAU_RADR_CA_COUNT (9U)
bogdanm	82:6473597d706e	748
bogdanm	82:6473597d706e	749	#define HW_CAU_RADR_CA_ADDR(n) (REGS_CAU_BASE + 0x908U + (0x4U * n))
bogdanm	82:6473597d706e	750
bogdanm	82:6473597d706e	751	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	752	#define HW_CAU_RADR_CA(n) ((__O hw_cau_radr_ca_t ) HW_CAU_RADR_CA_ADDR(n))
bogdanm	82:6473597d706e	753	#define HW_CAU_RADR_CA_WR(n, v) (HW_CAU_RADR_CA(n).U = (v))
bogdanm	82:6473597d706e	754	#endif
bogdanm	82:6473597d706e	755	//@}
bogdanm	82:6473597d706e	756
bogdanm	82:6473597d706e	757	/*
bogdanm	82:6473597d706e	758	* Constants & macros for individual CAU_RADR_CA bitfields
bogdanm	82:6473597d706e	759	*/
bogdanm	82:6473597d706e	760
bogdanm	82:6473597d706e	761	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	762	// HW_CAU_XOR_CASR - Status register - Exclusive Or command
bogdanm	82:6473597d706e	763	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	764
bogdanm	82:6473597d706e	765	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	766	/*!
bogdanm	82:6473597d706e	767	* @brief HW_CAU_XOR_CASR - Status register - Exclusive Or command (WO)
bogdanm	82:6473597d706e	768	*
bogdanm	82:6473597d706e	769	* Reset value: 0x20000000U
bogdanm	82:6473597d706e	770	*/
bogdanm	82:6473597d706e	771	typedef union _hw_cau_xor_casr
bogdanm	82:6473597d706e	772	{
bogdanm	82:6473597d706e	773	uint32_t U;
bogdanm	82:6473597d706e	774	struct _hw_cau_xor_casr_bitfields
bogdanm	82:6473597d706e	775	{
bogdanm	82:6473597d706e	776	uint32_t IC : 1; //!< [0]
bogdanm	82:6473597d706e	777	uint32_t DPE : 1; //!< [1]
bogdanm	82:6473597d706e	778	uint32_t RESERVED0 : 26; //!< [27:2]
bogdanm	82:6473597d706e	779	uint32_t VER : 4; //!< [31:28] CAU version
bogdanm	82:6473597d706e	780	} B;
bogdanm	82:6473597d706e	781	} hw_cau_xor_casr_t;
bogdanm	82:6473597d706e	782	#endif
bogdanm	82:6473597d706e	783
bogdanm	82:6473597d706e	784	/*!
bogdanm	82:6473597d706e	785	* @name Constants and macros for entire CAU_XOR_CASR register
bogdanm	82:6473597d706e	786	*/
bogdanm	82:6473597d706e	787	//@{
bogdanm	82:6473597d706e	788	#define HW_CAU_XOR_CASR_ADDR (REGS_CAU_BASE + 0x980U)
bogdanm	82:6473597d706e	789
bogdanm	82:6473597d706e	790	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	791	#define HW_CAU_XOR_CASR ((__O hw_cau_xor_casr_t ) HW_CAU_XOR_CASR_ADDR)
bogdanm	82:6473597d706e	792	#define HW_CAU_XOR_CASR_WR(v) (HW_CAU_XOR_CASR.U = (v))
bogdanm	82:6473597d706e	793	#endif
bogdanm	82:6473597d706e	794	//@}
bogdanm	82:6473597d706e	795
bogdanm	82:6473597d706e	796	/*
bogdanm	82:6473597d706e	797	* Constants & macros for individual CAU_XOR_CASR bitfields
bogdanm	82:6473597d706e	798	*/
bogdanm	82:6473597d706e	799
bogdanm	82:6473597d706e	800	/*!
bogdanm	82:6473597d706e	801	* @name Register CAU_XOR_CASR, field IC[0] (WO)
bogdanm	82:6473597d706e	802	*
bogdanm	82:6473597d706e	803	* Values:
bogdanm	82:6473597d706e	804	* - 0 - No illegal commands issued
bogdanm	82:6473597d706e	805	* - 1 - Illegal command issued
bogdanm	82:6473597d706e	806	*/
bogdanm	82:6473597d706e	807	//@{
bogdanm	82:6473597d706e	808	#define BP_CAU_XOR_CASR_IC (0U) //!< Bit position for CAU_XOR_CASR_IC.
bogdanm	82:6473597d706e	809	#define BM_CAU_XOR_CASR_IC (0x00000001U) //!< Bit mask for CAU_XOR_CASR_IC.
bogdanm	82:6473597d706e	810	#define BS_CAU_XOR_CASR_IC (1U) //!< Bit field size in bits for CAU_XOR_CASR_IC.
bogdanm	82:6473597d706e	811
bogdanm	82:6473597d706e	812	//! @brief Format value for bitfield CAU_XOR_CASR_IC.
bogdanm	82:6473597d706e	813	#define BF_CAU_XOR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_IC), uint32_t) & BM_CAU_XOR_CASR_IC)
bogdanm	82:6473597d706e	814	//@}
bogdanm	82:6473597d706e	815
bogdanm	82:6473597d706e	816	/*!
bogdanm	82:6473597d706e	817	* @name Register CAU_XOR_CASR, field DPE[1] (WO)
bogdanm	82:6473597d706e	818	*
bogdanm	82:6473597d706e	819	* Values:
bogdanm	82:6473597d706e	820	* - 0 - No error detected
bogdanm	82:6473597d706e	821	* - 1 - DES key parity error detected
bogdanm	82:6473597d706e	822	*/
bogdanm	82:6473597d706e	823	//@{
bogdanm	82:6473597d706e	824	#define BP_CAU_XOR_CASR_DPE (1U) //!< Bit position for CAU_XOR_CASR_DPE.
bogdanm	82:6473597d706e	825	#define BM_CAU_XOR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_XOR_CASR_DPE.
bogdanm	82:6473597d706e	826	#define BS_CAU_XOR_CASR_DPE (1U) //!< Bit field size in bits for CAU_XOR_CASR_DPE.
bogdanm	82:6473597d706e	827
bogdanm	82:6473597d706e	828	//! @brief Format value for bitfield CAU_XOR_CASR_DPE.
bogdanm	82:6473597d706e	829	#define BF_CAU_XOR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_DPE), uint32_t) & BM_CAU_XOR_CASR_DPE)
bogdanm	82:6473597d706e	830	//@}
bogdanm	82:6473597d706e	831
bogdanm	82:6473597d706e	832	/*!
bogdanm	82:6473597d706e	833	* @name Register CAU_XOR_CASR, field VER[31:28] (WO)
bogdanm	82:6473597d706e	834	*
bogdanm	82:6473597d706e	835	* Values:
bogdanm	82:6473597d706e	836	* - 0001 - Initial CAU version
bogdanm	82:6473597d706e	837	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
bogdanm	82:6473597d706e	838	* value on this device)
bogdanm	82:6473597d706e	839	*/
bogdanm	82:6473597d706e	840	//@{
bogdanm	82:6473597d706e	841	#define BP_CAU_XOR_CASR_VER (28U) //!< Bit position for CAU_XOR_CASR_VER.
bogdanm	82:6473597d706e	842	#define BM_CAU_XOR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_XOR_CASR_VER.
bogdanm	82:6473597d706e	843	#define BS_CAU_XOR_CASR_VER (4U) //!< Bit field size in bits for CAU_XOR_CASR_VER.
bogdanm	82:6473597d706e	844
bogdanm	82:6473597d706e	845	//! @brief Format value for bitfield CAU_XOR_CASR_VER.
bogdanm	82:6473597d706e	846	#define BF_CAU_XOR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_VER), uint32_t) & BM_CAU_XOR_CASR_VER)
bogdanm	82:6473597d706e	847	//@}
bogdanm	82:6473597d706e	848
bogdanm	82:6473597d706e	849	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	850	// HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command
bogdanm	82:6473597d706e	851	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	852
bogdanm	82:6473597d706e	853	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	854	/*!
bogdanm	82:6473597d706e	855	* @brief HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command (WO)
bogdanm	82:6473597d706e	856	*
bogdanm	82:6473597d706e	857	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	858	*/
bogdanm	82:6473597d706e	859	typedef union _hw_cau_xor_caa
bogdanm	82:6473597d706e	860	{
bogdanm	82:6473597d706e	861	uint32_t U;
bogdanm	82:6473597d706e	862	struct _hw_cau_xor_caa_bitfields
bogdanm	82:6473597d706e	863	{
bogdanm	82:6473597d706e	864	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	865	} B;
bogdanm	82:6473597d706e	866	} hw_cau_xor_caa_t;
bogdanm	82:6473597d706e	867	#endif
bogdanm	82:6473597d706e	868
bogdanm	82:6473597d706e	869	/*!
bogdanm	82:6473597d706e	870	* @name Constants and macros for entire CAU_XOR_CAA register
bogdanm	82:6473597d706e	871	*/
bogdanm	82:6473597d706e	872	//@{
bogdanm	82:6473597d706e	873	#define HW_CAU_XOR_CAA_ADDR (REGS_CAU_BASE + 0x984U)
bogdanm	82:6473597d706e	874
bogdanm	82:6473597d706e	875	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	876	#define HW_CAU_XOR_CAA ((__O hw_cau_xor_caa_t ) HW_CAU_XOR_CAA_ADDR)
bogdanm	82:6473597d706e	877	#define HW_CAU_XOR_CAA_WR(v) (HW_CAU_XOR_CAA.U = (v))
bogdanm	82:6473597d706e	878	#endif
bogdanm	82:6473597d706e	879	//@}
bogdanm	82:6473597d706e	880
bogdanm	82:6473597d706e	881	/*
bogdanm	82:6473597d706e	882	* Constants & macros for individual CAU_XOR_CAA bitfields
bogdanm	82:6473597d706e	883	*/
bogdanm	82:6473597d706e	884
bogdanm	82:6473597d706e	885	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	886	// HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
bogdanm	82:6473597d706e	887	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	888
bogdanm	82:6473597d706e	889	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	890	/*!
bogdanm	82:6473597d706e	891	* @brief HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command (WO)
bogdanm	82:6473597d706e	892	*
bogdanm	82:6473597d706e	893	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	894	*/
bogdanm	82:6473597d706e	895	typedef union _hw_cau_xor_ca
bogdanm	82:6473597d706e	896	{
bogdanm	82:6473597d706e	897	uint32_t U;
bogdanm	82:6473597d706e	898	struct _hw_cau_xor_ca_bitfields
bogdanm	82:6473597d706e	899	{
bogdanm	82:6473597d706e	900	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	901	} B;
bogdanm	82:6473597d706e	902	} hw_cau_xor_ca_t;
bogdanm	82:6473597d706e	903	#endif
bogdanm	82:6473597d706e	904
bogdanm	82:6473597d706e	905	/*!
bogdanm	82:6473597d706e	906	* @name Constants and macros for entire CAU_XOR_CA register
bogdanm	82:6473597d706e	907	*/
bogdanm	82:6473597d706e	908	//@{
bogdanm	82:6473597d706e	909	#define HW_CAU_XOR_CA_COUNT (9U)
bogdanm	82:6473597d706e	910
bogdanm	82:6473597d706e	911	#define HW_CAU_XOR_CA_ADDR(n) (REGS_CAU_BASE + 0x988U + (0x4U * n))
bogdanm	82:6473597d706e	912
bogdanm	82:6473597d706e	913	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	914	#define HW_CAU_XOR_CA(n) ((__O hw_cau_xor_ca_t ) HW_CAU_XOR_CA_ADDR(n))
bogdanm	82:6473597d706e	915	#define HW_CAU_XOR_CA_WR(n, v) (HW_CAU_XOR_CA(n).U = (v))
bogdanm	82:6473597d706e	916	#endif
bogdanm	82:6473597d706e	917	//@}
bogdanm	82:6473597d706e	918
bogdanm	82:6473597d706e	919	/*
bogdanm	82:6473597d706e	920	* Constants & macros for individual CAU_XOR_CA bitfields
bogdanm	82:6473597d706e	921	*/
bogdanm	82:6473597d706e	922
bogdanm	82:6473597d706e	923	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	924	// HW_CAU_ROTL_CASR - Status register - Rotate Left command
bogdanm	82:6473597d706e	925	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	926
bogdanm	82:6473597d706e	927	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	928	/*!
bogdanm	82:6473597d706e	929	* @brief HW_CAU_ROTL_CASR - Status register - Rotate Left command (WO)
bogdanm	82:6473597d706e	930	*
bogdanm	82:6473597d706e	931	* Reset value: 0x20000000U
bogdanm	82:6473597d706e	932	*/
bogdanm	82:6473597d706e	933	typedef union _hw_cau_rotl_casr
bogdanm	82:6473597d706e	934	{
bogdanm	82:6473597d706e	935	uint32_t U;
bogdanm	82:6473597d706e	936	struct _hw_cau_rotl_casr_bitfields
bogdanm	82:6473597d706e	937	{
bogdanm	82:6473597d706e	938	uint32_t IC : 1; //!< [0]
bogdanm	82:6473597d706e	939	uint32_t DPE : 1; //!< [1]
bogdanm	82:6473597d706e	940	uint32_t RESERVED0 : 26; //!< [27:2]
bogdanm	82:6473597d706e	941	uint32_t VER : 4; //!< [31:28] CAU version
bogdanm	82:6473597d706e	942	} B;
bogdanm	82:6473597d706e	943	} hw_cau_rotl_casr_t;
bogdanm	82:6473597d706e	944	#endif
bogdanm	82:6473597d706e	945
bogdanm	82:6473597d706e	946	/*!
bogdanm	82:6473597d706e	947	* @name Constants and macros for entire CAU_ROTL_CASR register
bogdanm	82:6473597d706e	948	*/
bogdanm	82:6473597d706e	949	//@{
bogdanm	82:6473597d706e	950	#define HW_CAU_ROTL_CASR_ADDR (REGS_CAU_BASE + 0x9C0U)
bogdanm	82:6473597d706e	951
bogdanm	82:6473597d706e	952	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	953	#define HW_CAU_ROTL_CASR ((__O hw_cau_rotl_casr_t ) HW_CAU_ROTL_CASR_ADDR)
bogdanm	82:6473597d706e	954	#define HW_CAU_ROTL_CASR_WR(v) (HW_CAU_ROTL_CASR.U = (v))
bogdanm	82:6473597d706e	955	#endif
bogdanm	82:6473597d706e	956	//@}
bogdanm	82:6473597d706e	957
bogdanm	82:6473597d706e	958	/*
bogdanm	82:6473597d706e	959	* Constants & macros for individual CAU_ROTL_CASR bitfields
bogdanm	82:6473597d706e	960	*/
bogdanm	82:6473597d706e	961
bogdanm	82:6473597d706e	962	/*!
bogdanm	82:6473597d706e	963	* @name Register CAU_ROTL_CASR, field IC[0] (WO)
bogdanm	82:6473597d706e	964	*
bogdanm	82:6473597d706e	965	* Values:
bogdanm	82:6473597d706e	966	* - 0 - No illegal commands issued
bogdanm	82:6473597d706e	967	* - 1 - Illegal command issued
bogdanm	82:6473597d706e	968	*/
bogdanm	82:6473597d706e	969	//@{
bogdanm	82:6473597d706e	970	#define BP_CAU_ROTL_CASR_IC (0U) //!< Bit position for CAU_ROTL_CASR_IC.
bogdanm	82:6473597d706e	971	#define BM_CAU_ROTL_CASR_IC (0x00000001U) //!< Bit mask for CAU_ROTL_CASR_IC.
bogdanm	82:6473597d706e	972	#define BS_CAU_ROTL_CASR_IC (1U) //!< Bit field size in bits for CAU_ROTL_CASR_IC.
bogdanm	82:6473597d706e	973
bogdanm	82:6473597d706e	974	//! @brief Format value for bitfield CAU_ROTL_CASR_IC.
bogdanm	82:6473597d706e	975	#define BF_CAU_ROTL_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_IC), uint32_t) & BM_CAU_ROTL_CASR_IC)
bogdanm	82:6473597d706e	976	//@}
bogdanm	82:6473597d706e	977
bogdanm	82:6473597d706e	978	/*!
bogdanm	82:6473597d706e	979	* @name Register CAU_ROTL_CASR, field DPE[1] (WO)
bogdanm	82:6473597d706e	980	*
bogdanm	82:6473597d706e	981	* Values:
bogdanm	82:6473597d706e	982	* - 0 - No error detected
bogdanm	82:6473597d706e	983	* - 1 - DES key parity error detected
bogdanm	82:6473597d706e	984	*/
bogdanm	82:6473597d706e	985	//@{
bogdanm	82:6473597d706e	986	#define BP_CAU_ROTL_CASR_DPE (1U) //!< Bit position for CAU_ROTL_CASR_DPE.
bogdanm	82:6473597d706e	987	#define BM_CAU_ROTL_CASR_DPE (0x00000002U) //!< Bit mask for CAU_ROTL_CASR_DPE.
bogdanm	82:6473597d706e	988	#define BS_CAU_ROTL_CASR_DPE (1U) //!< Bit field size in bits for CAU_ROTL_CASR_DPE.
bogdanm	82:6473597d706e	989
bogdanm	82:6473597d706e	990	//! @brief Format value for bitfield CAU_ROTL_CASR_DPE.
bogdanm	82:6473597d706e	991	#define BF_CAU_ROTL_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_DPE), uint32_t) & BM_CAU_ROTL_CASR_DPE)
bogdanm	82:6473597d706e	992	//@}
bogdanm	82:6473597d706e	993
bogdanm	82:6473597d706e	994	/*!
bogdanm	82:6473597d706e	995	* @name Register CAU_ROTL_CASR, field VER[31:28] (WO)
bogdanm	82:6473597d706e	996	*
bogdanm	82:6473597d706e	997	* Values:
bogdanm	82:6473597d706e	998	* - 0001 - Initial CAU version
bogdanm	82:6473597d706e	999	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
bogdanm	82:6473597d706e	1000	* value on this device)
bogdanm	82:6473597d706e	1001	*/
bogdanm	82:6473597d706e	1002	//@{
bogdanm	82:6473597d706e	1003	#define BP_CAU_ROTL_CASR_VER (28U) //!< Bit position for CAU_ROTL_CASR_VER.
bogdanm	82:6473597d706e	1004	#define BM_CAU_ROTL_CASR_VER (0xF0000000U) //!< Bit mask for CAU_ROTL_CASR_VER.
bogdanm	82:6473597d706e	1005	#define BS_CAU_ROTL_CASR_VER (4U) //!< Bit field size in bits for CAU_ROTL_CASR_VER.
bogdanm	82:6473597d706e	1006
bogdanm	82:6473597d706e	1007	//! @brief Format value for bitfield CAU_ROTL_CASR_VER.
bogdanm	82:6473597d706e	1008	#define BF_CAU_ROTL_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_VER), uint32_t) & BM_CAU_ROTL_CASR_VER)
bogdanm	82:6473597d706e	1009	//@}
bogdanm	82:6473597d706e	1010
bogdanm	82:6473597d706e	1011	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1012	// HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command
bogdanm	82:6473597d706e	1013	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1014
bogdanm	82:6473597d706e	1015	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1016	/*!
bogdanm	82:6473597d706e	1017	* @brief HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command (WO)
bogdanm	82:6473597d706e	1018	*
bogdanm	82:6473597d706e	1019	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1020	*/
bogdanm	82:6473597d706e	1021	typedef union _hw_cau_rotl_caa
bogdanm	82:6473597d706e	1022	{
bogdanm	82:6473597d706e	1023	uint32_t U;
bogdanm	82:6473597d706e	1024	struct _hw_cau_rotl_caa_bitfields
bogdanm	82:6473597d706e	1025	{
bogdanm	82:6473597d706e	1026	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	1027	} B;
bogdanm	82:6473597d706e	1028	} hw_cau_rotl_caa_t;
bogdanm	82:6473597d706e	1029	#endif
bogdanm	82:6473597d706e	1030
bogdanm	82:6473597d706e	1031	/*!
bogdanm	82:6473597d706e	1032	* @name Constants and macros for entire CAU_ROTL_CAA register
bogdanm	82:6473597d706e	1033	*/
bogdanm	82:6473597d706e	1034	//@{
bogdanm	82:6473597d706e	1035	#define HW_CAU_ROTL_CAA_ADDR (REGS_CAU_BASE + 0x9C4U)
bogdanm	82:6473597d706e	1036
bogdanm	82:6473597d706e	1037	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1038	#define HW_CAU_ROTL_CAA ((__O hw_cau_rotl_caa_t ) HW_CAU_ROTL_CAA_ADDR)
bogdanm	82:6473597d706e	1039	#define HW_CAU_ROTL_CAA_WR(v) (HW_CAU_ROTL_CAA.U = (v))
bogdanm	82:6473597d706e	1040	#endif
bogdanm	82:6473597d706e	1041	//@}
bogdanm	82:6473597d706e	1042
bogdanm	82:6473597d706e	1043	/*
bogdanm	82:6473597d706e	1044	* Constants & macros for individual CAU_ROTL_CAA bitfields
bogdanm	82:6473597d706e	1045	*/
bogdanm	82:6473597d706e	1046
bogdanm	82:6473597d706e	1047	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1048	// HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
bogdanm	82:6473597d706e	1049	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1050
bogdanm	82:6473597d706e	1051	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1052	/*!
bogdanm	82:6473597d706e	1053	* @brief HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command (WO)
bogdanm	82:6473597d706e	1054	*
bogdanm	82:6473597d706e	1055	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1056	*/
bogdanm	82:6473597d706e	1057	typedef union _hw_cau_rotl_ca
bogdanm	82:6473597d706e	1058	{
bogdanm	82:6473597d706e	1059	uint32_t U;
bogdanm	82:6473597d706e	1060	struct _hw_cau_rotl_ca_bitfields
bogdanm	82:6473597d706e	1061	{
bogdanm	82:6473597d706e	1062	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	1063	} B;
bogdanm	82:6473597d706e	1064	} hw_cau_rotl_ca_t;
bogdanm	82:6473597d706e	1065	#endif
bogdanm	82:6473597d706e	1066
bogdanm	82:6473597d706e	1067	/*!
bogdanm	82:6473597d706e	1068	* @name Constants and macros for entire CAU_ROTL_CA register
bogdanm	82:6473597d706e	1069	*/
bogdanm	82:6473597d706e	1070	//@{
bogdanm	82:6473597d706e	1071	#define HW_CAU_ROTL_CA_COUNT (9U)
bogdanm	82:6473597d706e	1072
bogdanm	82:6473597d706e	1073	#define HW_CAU_ROTL_CA_ADDR(n) (REGS_CAU_BASE + 0x9C8U + (0x4U * n))
bogdanm	82:6473597d706e	1074
bogdanm	82:6473597d706e	1075	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1076	#define HW_CAU_ROTL_CA(n) ((__O hw_cau_rotl_ca_t ) HW_CAU_ROTL_CA_ADDR(n))
bogdanm	82:6473597d706e	1077	#define HW_CAU_ROTL_CA_WR(n, v) (HW_CAU_ROTL_CA(n).U = (v))
bogdanm	82:6473597d706e	1078	#endif
bogdanm	82:6473597d706e	1079	//@}
bogdanm	82:6473597d706e	1080
bogdanm	82:6473597d706e	1081	/*
bogdanm	82:6473597d706e	1082	* Constants & macros for individual CAU_ROTL_CA bitfields
bogdanm	82:6473597d706e	1083	*/
bogdanm	82:6473597d706e	1084
bogdanm	82:6473597d706e	1085	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1086	// HW_CAU_AESC_CASR - Status register - AES Column Operation command
bogdanm	82:6473597d706e	1087	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1088
bogdanm	82:6473597d706e	1089	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1090	/*!
bogdanm	82:6473597d706e	1091	* @brief HW_CAU_AESC_CASR - Status register - AES Column Operation command (WO)
bogdanm	82:6473597d706e	1092	*
bogdanm	82:6473597d706e	1093	* Reset value: 0x20000000U
bogdanm	82:6473597d706e	1094	*/
bogdanm	82:6473597d706e	1095	typedef union _hw_cau_aesc_casr
bogdanm	82:6473597d706e	1096	{
bogdanm	82:6473597d706e	1097	uint32_t U;
bogdanm	82:6473597d706e	1098	struct _hw_cau_aesc_casr_bitfields
bogdanm	82:6473597d706e	1099	{
bogdanm	82:6473597d706e	1100	uint32_t IC : 1; //!< [0]
bogdanm	82:6473597d706e	1101	uint32_t DPE : 1; //!< [1]
bogdanm	82:6473597d706e	1102	uint32_t RESERVED0 : 26; //!< [27:2]
bogdanm	82:6473597d706e	1103	uint32_t VER : 4; //!< [31:28] CAU version
bogdanm	82:6473597d706e	1104	} B;
bogdanm	82:6473597d706e	1105	} hw_cau_aesc_casr_t;
bogdanm	82:6473597d706e	1106	#endif
bogdanm	82:6473597d706e	1107
bogdanm	82:6473597d706e	1108	/*!
bogdanm	82:6473597d706e	1109	* @name Constants and macros for entire CAU_AESC_CASR register
bogdanm	82:6473597d706e	1110	*/
bogdanm	82:6473597d706e	1111	//@{
bogdanm	82:6473597d706e	1112	#define HW_CAU_AESC_CASR_ADDR (REGS_CAU_BASE + 0xB00U)
bogdanm	82:6473597d706e	1113
bogdanm	82:6473597d706e	1114	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1115	#define HW_CAU_AESC_CASR ((__O hw_cau_aesc_casr_t ) HW_CAU_AESC_CASR_ADDR)
bogdanm	82:6473597d706e	1116	#define HW_CAU_AESC_CASR_WR(v) (HW_CAU_AESC_CASR.U = (v))
bogdanm	82:6473597d706e	1117	#endif
bogdanm	82:6473597d706e	1118	//@}
bogdanm	82:6473597d706e	1119
bogdanm	82:6473597d706e	1120	/*
bogdanm	82:6473597d706e	1121	* Constants & macros for individual CAU_AESC_CASR bitfields
bogdanm	82:6473597d706e	1122	*/
bogdanm	82:6473597d706e	1123
bogdanm	82:6473597d706e	1124	/*!
bogdanm	82:6473597d706e	1125	* @name Register CAU_AESC_CASR, field IC[0] (WO)
bogdanm	82:6473597d706e	1126	*
bogdanm	82:6473597d706e	1127	* Values:
bogdanm	82:6473597d706e	1128	* - 0 - No illegal commands issued
bogdanm	82:6473597d706e	1129	* - 1 - Illegal command issued
bogdanm	82:6473597d706e	1130	*/
bogdanm	82:6473597d706e	1131	//@{
bogdanm	82:6473597d706e	1132	#define BP_CAU_AESC_CASR_IC (0U) //!< Bit position for CAU_AESC_CASR_IC.
bogdanm	82:6473597d706e	1133	#define BM_CAU_AESC_CASR_IC (0x00000001U) //!< Bit mask for CAU_AESC_CASR_IC.
bogdanm	82:6473597d706e	1134	#define BS_CAU_AESC_CASR_IC (1U) //!< Bit field size in bits for CAU_AESC_CASR_IC.
bogdanm	82:6473597d706e	1135
bogdanm	82:6473597d706e	1136	//! @brief Format value for bitfield CAU_AESC_CASR_IC.
bogdanm	82:6473597d706e	1137	#define BF_CAU_AESC_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_IC), uint32_t) & BM_CAU_AESC_CASR_IC)
bogdanm	82:6473597d706e	1138	//@}
bogdanm	82:6473597d706e	1139
bogdanm	82:6473597d706e	1140	/*!
bogdanm	82:6473597d706e	1141	* @name Register CAU_AESC_CASR, field DPE[1] (WO)
bogdanm	82:6473597d706e	1142	*
bogdanm	82:6473597d706e	1143	* Values:
bogdanm	82:6473597d706e	1144	* - 0 - No error detected
bogdanm	82:6473597d706e	1145	* - 1 - DES key parity error detected
bogdanm	82:6473597d706e	1146	*/
bogdanm	82:6473597d706e	1147	//@{
bogdanm	82:6473597d706e	1148	#define BP_CAU_AESC_CASR_DPE (1U) //!< Bit position for CAU_AESC_CASR_DPE.
bogdanm	82:6473597d706e	1149	#define BM_CAU_AESC_CASR_DPE (0x00000002U) //!< Bit mask for CAU_AESC_CASR_DPE.
bogdanm	82:6473597d706e	1150	#define BS_CAU_AESC_CASR_DPE (1U) //!< Bit field size in bits for CAU_AESC_CASR_DPE.
bogdanm	82:6473597d706e	1151
bogdanm	82:6473597d706e	1152	//! @brief Format value for bitfield CAU_AESC_CASR_DPE.
bogdanm	82:6473597d706e	1153	#define BF_CAU_AESC_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_DPE), uint32_t) & BM_CAU_AESC_CASR_DPE)
bogdanm	82:6473597d706e	1154	//@}
bogdanm	82:6473597d706e	1155
bogdanm	82:6473597d706e	1156	/*!
bogdanm	82:6473597d706e	1157	* @name Register CAU_AESC_CASR, field VER[31:28] (WO)
bogdanm	82:6473597d706e	1158	*
bogdanm	82:6473597d706e	1159	* Values:
bogdanm	82:6473597d706e	1160	* - 0001 - Initial CAU version
bogdanm	82:6473597d706e	1161	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
bogdanm	82:6473597d706e	1162	* value on this device)
bogdanm	82:6473597d706e	1163	*/
bogdanm	82:6473597d706e	1164	//@{
bogdanm	82:6473597d706e	1165	#define BP_CAU_AESC_CASR_VER (28U) //!< Bit position for CAU_AESC_CASR_VER.
bogdanm	82:6473597d706e	1166	#define BM_CAU_AESC_CASR_VER (0xF0000000U) //!< Bit mask for CAU_AESC_CASR_VER.
bogdanm	82:6473597d706e	1167	#define BS_CAU_AESC_CASR_VER (4U) //!< Bit field size in bits for CAU_AESC_CASR_VER.
bogdanm	82:6473597d706e	1168
bogdanm	82:6473597d706e	1169	//! @brief Format value for bitfield CAU_AESC_CASR_VER.
bogdanm	82:6473597d706e	1170	#define BF_CAU_AESC_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_VER), uint32_t) & BM_CAU_AESC_CASR_VER)
bogdanm	82:6473597d706e	1171	//@}
bogdanm	82:6473597d706e	1172
bogdanm	82:6473597d706e	1173	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1174	// HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command
bogdanm	82:6473597d706e	1175	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1176
bogdanm	82:6473597d706e	1177	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1178	/*!
bogdanm	82:6473597d706e	1179	* @brief HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command (WO)
bogdanm	82:6473597d706e	1180	*
bogdanm	82:6473597d706e	1181	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1182	*/
bogdanm	82:6473597d706e	1183	typedef union _hw_cau_aesc_caa
bogdanm	82:6473597d706e	1184	{
bogdanm	82:6473597d706e	1185	uint32_t U;
bogdanm	82:6473597d706e	1186	struct _hw_cau_aesc_caa_bitfields
bogdanm	82:6473597d706e	1187	{
bogdanm	82:6473597d706e	1188	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	1189	} B;
bogdanm	82:6473597d706e	1190	} hw_cau_aesc_caa_t;
bogdanm	82:6473597d706e	1191	#endif
bogdanm	82:6473597d706e	1192
bogdanm	82:6473597d706e	1193	/*!
bogdanm	82:6473597d706e	1194	* @name Constants and macros for entire CAU_AESC_CAA register
bogdanm	82:6473597d706e	1195	*/
bogdanm	82:6473597d706e	1196	//@{
bogdanm	82:6473597d706e	1197	#define HW_CAU_AESC_CAA_ADDR (REGS_CAU_BASE + 0xB04U)
bogdanm	82:6473597d706e	1198
bogdanm	82:6473597d706e	1199	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1200	#define HW_CAU_AESC_CAA ((__O hw_cau_aesc_caa_t ) HW_CAU_AESC_CAA_ADDR)
bogdanm	82:6473597d706e	1201	#define HW_CAU_AESC_CAA_WR(v) (HW_CAU_AESC_CAA.U = (v))
bogdanm	82:6473597d706e	1202	#endif
bogdanm	82:6473597d706e	1203	//@}
bogdanm	82:6473597d706e	1204
bogdanm	82:6473597d706e	1205	/*
bogdanm	82:6473597d706e	1206	* Constants & macros for individual CAU_AESC_CAA bitfields
bogdanm	82:6473597d706e	1207	*/
bogdanm	82:6473597d706e	1208
bogdanm	82:6473597d706e	1209	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1210	// HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
bogdanm	82:6473597d706e	1211	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1212
bogdanm	82:6473597d706e	1213	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1214	/*!
bogdanm	82:6473597d706e	1215	* @brief HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command (WO)
bogdanm	82:6473597d706e	1216	*
bogdanm	82:6473597d706e	1217	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1218	*/
bogdanm	82:6473597d706e	1219	typedef union _hw_cau_aesc_ca
bogdanm	82:6473597d706e	1220	{
bogdanm	82:6473597d706e	1221	uint32_t U;
bogdanm	82:6473597d706e	1222	struct _hw_cau_aesc_ca_bitfields
bogdanm	82:6473597d706e	1223	{
bogdanm	82:6473597d706e	1224	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	1225	} B;
bogdanm	82:6473597d706e	1226	} hw_cau_aesc_ca_t;
bogdanm	82:6473597d706e	1227	#endif
bogdanm	82:6473597d706e	1228
bogdanm	82:6473597d706e	1229	/*!
bogdanm	82:6473597d706e	1230	* @name Constants and macros for entire CAU_AESC_CA register
bogdanm	82:6473597d706e	1231	*/
bogdanm	82:6473597d706e	1232	//@{
bogdanm	82:6473597d706e	1233	#define HW_CAU_AESC_CA_COUNT (9U)
bogdanm	82:6473597d706e	1234
bogdanm	82:6473597d706e	1235	#define HW_CAU_AESC_CA_ADDR(n) (REGS_CAU_BASE + 0xB08U + (0x4U * n))
bogdanm	82:6473597d706e	1236
bogdanm	82:6473597d706e	1237	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1238	#define HW_CAU_AESC_CA(n) ((__O hw_cau_aesc_ca_t ) HW_CAU_AESC_CA_ADDR(n))
bogdanm	82:6473597d706e	1239	#define HW_CAU_AESC_CA_WR(n, v) (HW_CAU_AESC_CA(n).U = (v))
bogdanm	82:6473597d706e	1240	#endif
bogdanm	82:6473597d706e	1241	//@}
bogdanm	82:6473597d706e	1242
bogdanm	82:6473597d706e	1243	/*
bogdanm	82:6473597d706e	1244	* Constants & macros for individual CAU_AESC_CA bitfields
bogdanm	82:6473597d706e	1245	*/
bogdanm	82:6473597d706e	1246
bogdanm	82:6473597d706e	1247	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1248	// HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
bogdanm	82:6473597d706e	1249	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1250
bogdanm	82:6473597d706e	1251	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1252	/*!
bogdanm	82:6473597d706e	1253	* @brief HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command (WO)
bogdanm	82:6473597d706e	1254	*
bogdanm	82:6473597d706e	1255	* Reset value: 0x20000000U
bogdanm	82:6473597d706e	1256	*/
bogdanm	82:6473597d706e	1257	typedef union _hw_cau_aesic_casr
bogdanm	82:6473597d706e	1258	{
bogdanm	82:6473597d706e	1259	uint32_t U;
bogdanm	82:6473597d706e	1260	struct _hw_cau_aesic_casr_bitfields
bogdanm	82:6473597d706e	1261	{
bogdanm	82:6473597d706e	1262	uint32_t IC : 1; //!< [0]
bogdanm	82:6473597d706e	1263	uint32_t DPE : 1; //!< [1]
bogdanm	82:6473597d706e	1264	uint32_t RESERVED0 : 26; //!< [27:2]
bogdanm	82:6473597d706e	1265	uint32_t VER : 4; //!< [31:28] CAU version
bogdanm	82:6473597d706e	1266	} B;
bogdanm	82:6473597d706e	1267	} hw_cau_aesic_casr_t;
bogdanm	82:6473597d706e	1268	#endif
bogdanm	82:6473597d706e	1269
bogdanm	82:6473597d706e	1270	/*!
bogdanm	82:6473597d706e	1271	* @name Constants and macros for entire CAU_AESIC_CASR register
bogdanm	82:6473597d706e	1272	*/
bogdanm	82:6473597d706e	1273	//@{
bogdanm	82:6473597d706e	1274	#define HW_CAU_AESIC_CASR_ADDR (REGS_CAU_BASE + 0xB40U)
bogdanm	82:6473597d706e	1275
bogdanm	82:6473597d706e	1276	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1277	#define HW_CAU_AESIC_CASR ((__O hw_cau_aesic_casr_t ) HW_CAU_AESIC_CASR_ADDR)
bogdanm	82:6473597d706e	1278	#define HW_CAU_AESIC_CASR_WR(v) (HW_CAU_AESIC_CASR.U = (v))
bogdanm	82:6473597d706e	1279	#endif
bogdanm	82:6473597d706e	1280	//@}
bogdanm	82:6473597d706e	1281
bogdanm	82:6473597d706e	1282	/*
bogdanm	82:6473597d706e	1283	* Constants & macros for individual CAU_AESIC_CASR bitfields
bogdanm	82:6473597d706e	1284	*/
bogdanm	82:6473597d706e	1285
bogdanm	82:6473597d706e	1286	/*!
bogdanm	82:6473597d706e	1287	* @name Register CAU_AESIC_CASR, field IC[0] (WO)
bogdanm	82:6473597d706e	1288	*
bogdanm	82:6473597d706e	1289	* Values:
bogdanm	82:6473597d706e	1290	* - 0 - No illegal commands issued
bogdanm	82:6473597d706e	1291	* - 1 - Illegal command issued
bogdanm	82:6473597d706e	1292	*/
bogdanm	82:6473597d706e	1293	//@{
bogdanm	82:6473597d706e	1294	#define BP_CAU_AESIC_CASR_IC (0U) //!< Bit position for CAU_AESIC_CASR_IC.
bogdanm	82:6473597d706e	1295	#define BM_CAU_AESIC_CASR_IC (0x00000001U) //!< Bit mask for CAU_AESIC_CASR_IC.
bogdanm	82:6473597d706e	1296	#define BS_CAU_AESIC_CASR_IC (1U) //!< Bit field size in bits for CAU_AESIC_CASR_IC.
bogdanm	82:6473597d706e	1297
bogdanm	82:6473597d706e	1298	//! @brief Format value for bitfield CAU_AESIC_CASR_IC.
bogdanm	82:6473597d706e	1299	#define BF_CAU_AESIC_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_IC), uint32_t) & BM_CAU_AESIC_CASR_IC)
bogdanm	82:6473597d706e	1300	//@}
bogdanm	82:6473597d706e	1301
bogdanm	82:6473597d706e	1302	/*!
bogdanm	82:6473597d706e	1303	* @name Register CAU_AESIC_CASR, field DPE[1] (WO)
bogdanm	82:6473597d706e	1304	*
bogdanm	82:6473597d706e	1305	* Values:
bogdanm	82:6473597d706e	1306	* - 0 - No error detected
bogdanm	82:6473597d706e	1307	* - 1 - DES key parity error detected
bogdanm	82:6473597d706e	1308	*/
bogdanm	82:6473597d706e	1309	//@{
bogdanm	82:6473597d706e	1310	#define BP_CAU_AESIC_CASR_DPE (1U) //!< Bit position for CAU_AESIC_CASR_DPE.
bogdanm	82:6473597d706e	1311	#define BM_CAU_AESIC_CASR_DPE (0x00000002U) //!< Bit mask for CAU_AESIC_CASR_DPE.
bogdanm	82:6473597d706e	1312	#define BS_CAU_AESIC_CASR_DPE (1U) //!< Bit field size in bits for CAU_AESIC_CASR_DPE.
bogdanm	82:6473597d706e	1313
bogdanm	82:6473597d706e	1314	//! @brief Format value for bitfield CAU_AESIC_CASR_DPE.
bogdanm	82:6473597d706e	1315	#define BF_CAU_AESIC_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_DPE), uint32_t) & BM_CAU_AESIC_CASR_DPE)
bogdanm	82:6473597d706e	1316	//@}
bogdanm	82:6473597d706e	1317
bogdanm	82:6473597d706e	1318	/*!
bogdanm	82:6473597d706e	1319	* @name Register CAU_AESIC_CASR, field VER[31:28] (WO)
bogdanm	82:6473597d706e	1320	*
bogdanm	82:6473597d706e	1321	* Values:
bogdanm	82:6473597d706e	1322	* - 0001 - Initial CAU version
bogdanm	82:6473597d706e	1323	* - 0010 - Second version, added support for SHA-256 algorithm.(This is the
bogdanm	82:6473597d706e	1324	* value on this device)
bogdanm	82:6473597d706e	1325	*/
bogdanm	82:6473597d706e	1326	//@{
bogdanm	82:6473597d706e	1327	#define BP_CAU_AESIC_CASR_VER (28U) //!< Bit position for CAU_AESIC_CASR_VER.
bogdanm	82:6473597d706e	1328	#define BM_CAU_AESIC_CASR_VER (0xF0000000U) //!< Bit mask for CAU_AESIC_CASR_VER.
bogdanm	82:6473597d706e	1329	#define BS_CAU_AESIC_CASR_VER (4U) //!< Bit field size in bits for CAU_AESIC_CASR_VER.
bogdanm	82:6473597d706e	1330
bogdanm	82:6473597d706e	1331	//! @brief Format value for bitfield CAU_AESIC_CASR_VER.
bogdanm	82:6473597d706e	1332	#define BF_CAU_AESIC_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_VER), uint32_t) & BM_CAU_AESIC_CASR_VER)
bogdanm	82:6473597d706e	1333	//@}
bogdanm	82:6473597d706e	1334
bogdanm	82:6473597d706e	1335	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1336	// HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
bogdanm	82:6473597d706e	1337	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1338
bogdanm	82:6473597d706e	1339	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1340	/*!
bogdanm	82:6473597d706e	1341	* @brief HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command (WO)
bogdanm	82:6473597d706e	1342	*
bogdanm	82:6473597d706e	1343	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1344	*/
bogdanm	82:6473597d706e	1345	typedef union _hw_cau_aesic_caa
bogdanm	82:6473597d706e	1346	{
bogdanm	82:6473597d706e	1347	uint32_t U;
bogdanm	82:6473597d706e	1348	struct _hw_cau_aesic_caa_bitfields
bogdanm	82:6473597d706e	1349	{
bogdanm	82:6473597d706e	1350	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	1351	} B;
bogdanm	82:6473597d706e	1352	} hw_cau_aesic_caa_t;
bogdanm	82:6473597d706e	1353	#endif
bogdanm	82:6473597d706e	1354
bogdanm	82:6473597d706e	1355	/*!
bogdanm	82:6473597d706e	1356	* @name Constants and macros for entire CAU_AESIC_CAA register
bogdanm	82:6473597d706e	1357	*/
bogdanm	82:6473597d706e	1358	//@{
bogdanm	82:6473597d706e	1359	#define HW_CAU_AESIC_CAA_ADDR (REGS_CAU_BASE + 0xB44U)
bogdanm	82:6473597d706e	1360
bogdanm	82:6473597d706e	1361	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1362	#define HW_CAU_AESIC_CAA ((__O hw_cau_aesic_caa_t ) HW_CAU_AESIC_CAA_ADDR)
bogdanm	82:6473597d706e	1363	#define HW_CAU_AESIC_CAA_WR(v) (HW_CAU_AESIC_CAA.U = (v))
bogdanm	82:6473597d706e	1364	#endif
bogdanm	82:6473597d706e	1365	//@}
bogdanm	82:6473597d706e	1366
bogdanm	82:6473597d706e	1367	/*
bogdanm	82:6473597d706e	1368	* Constants & macros for individual CAU_AESIC_CAA bitfields
bogdanm	82:6473597d706e	1369	*/
bogdanm	82:6473597d706e	1370
bogdanm	82:6473597d706e	1371	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1372	// HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
bogdanm	82:6473597d706e	1373	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1374
bogdanm	82:6473597d706e	1375	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1376	/*!
bogdanm	82:6473597d706e	1377	* @brief HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command (WO)
bogdanm	82:6473597d706e	1378	*
bogdanm	82:6473597d706e	1379	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1380	*/
bogdanm	82:6473597d706e	1381	typedef union _hw_cau_aesic_ca
bogdanm	82:6473597d706e	1382	{
bogdanm	82:6473597d706e	1383	uint32_t U;
bogdanm	82:6473597d706e	1384	struct _hw_cau_aesic_ca_bitfields
bogdanm	82:6473597d706e	1385	{
bogdanm	82:6473597d706e	1386	uint32_t RESERVED0 : 32; //!< [31:0]
bogdanm	82:6473597d706e	1387	} B;
bogdanm	82:6473597d706e	1388	} hw_cau_aesic_ca_t;
bogdanm	82:6473597d706e	1389	#endif
bogdanm	82:6473597d706e	1390
bogdanm	82:6473597d706e	1391	/*!
bogdanm	82:6473597d706e	1392	* @name Constants and macros for entire CAU_AESIC_CA register
bogdanm	82:6473597d706e	1393	*/
bogdanm	82:6473597d706e	1394	//@{
bogdanm	82:6473597d706e	1395	#define HW_CAU_AESIC_CA_COUNT (9U)
bogdanm	82:6473597d706e	1396
bogdanm	82:6473597d706e	1397	#define HW_CAU_AESIC_CA_ADDR(n) (REGS_CAU_BASE + 0xB48U + (0x4U * n))
bogdanm	82:6473597d706e	1398
bogdanm	82:6473597d706e	1399	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1400	#define HW_CAU_AESIC_CA(n) ((__O hw_cau_aesic_ca_t ) HW_CAU_AESIC_CA_ADDR(n))
bogdanm	82:6473597d706e	1401	#define HW_CAU_AESIC_CA_WR(n, v) (HW_CAU_AESIC_CA(n).U = (v))
bogdanm	82:6473597d706e	1402	#endif
bogdanm	82:6473597d706e	1403	//@}
bogdanm	82:6473597d706e	1404
bogdanm	82:6473597d706e	1405	/*
bogdanm	82:6473597d706e	1406	* Constants & macros for individual CAU_AESIC_CA bitfields
bogdanm	82:6473597d706e	1407	*/
bogdanm	82:6473597d706e	1408
bogdanm	82:6473597d706e	1409	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1410	// hw_cau_t - module struct
bogdanm	82:6473597d706e	1411	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1412	/*!
bogdanm	82:6473597d706e	1413	* @brief All CAU module registers.
bogdanm	82:6473597d706e	1414	*/
bogdanm	82:6473597d706e	1415	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1416	#pragma pack(1)
bogdanm	82:6473597d706e	1417	typedef struct _hw_cau
bogdanm	82:6473597d706e	1418	{
bogdanm	82:6473597d706e	1419	__O hw_cau_direct_t DIRECT[16]; //!< [0x0] Direct access register 0
bogdanm	82:6473597d706e	1420	uint8_t _reserved0[2048];
bogdanm	82:6473597d706e	1421	__O hw_cau_ldr_casr_t LDR_CASR; //!< [0x840] Status register - Load Register command
bogdanm	82:6473597d706e	1422	__O hw_cau_ldr_caa_t LDR_CAA; //!< [0x844] Accumulator register - Load Register command
bogdanm	82:6473597d706e	1423	__O hw_cau_ldr_ca_t LDR_CA[9]; //!< [0x848] General Purpose Register 0 - Load Register command
bogdanm	82:6473597d706e	1424	uint8_t _reserved1[20];
bogdanm	82:6473597d706e	1425	__I hw_cau_str_casr_t STR_CASR; //!< [0x880] Status register - Store Register command
bogdanm	82:6473597d706e	1426	__I hw_cau_str_caa_t STR_CAA; //!< [0x884] Accumulator register - Store Register command
bogdanm	82:6473597d706e	1427	__I hw_cau_str_ca_t STR_CA[9]; //!< [0x888] General Purpose Register 0 - Store Register command
bogdanm	82:6473597d706e	1428	uint8_t _reserved2[20];
bogdanm	82:6473597d706e	1429	__O hw_cau_adr_casr_t ADR_CASR; //!< [0x8C0] Status register - Add Register command
bogdanm	82:6473597d706e	1430	__O hw_cau_adr_caa_t ADR_CAA; //!< [0x8C4] Accumulator register - Add to register command
bogdanm	82:6473597d706e	1431	__O hw_cau_adr_ca_t ADR_CA[9]; //!< [0x8C8] General Purpose Register 0 - Add to register command
bogdanm	82:6473597d706e	1432	uint8_t _reserved3[20];
bogdanm	82:6473597d706e	1433	__O hw_cau_radr_casr_t RADR_CASR; //!< [0x900] Status register - Reverse and Add to Register command
bogdanm	82:6473597d706e	1434	__O hw_cau_radr_caa_t RADR_CAA; //!< [0x904] Accumulator register - Reverse and Add to Register command
bogdanm	82:6473597d706e	1435	__O hw_cau_radr_ca_t RADR_CA[9]; //!< [0x908] General Purpose Register 0 - Reverse and Add to Register command
bogdanm	82:6473597d706e	1436	uint8_t _reserved4[84];
bogdanm	82:6473597d706e	1437	__O hw_cau_xor_casr_t XOR_CASR; //!< [0x980] Status register - Exclusive Or command
bogdanm	82:6473597d706e	1438	__O hw_cau_xor_caa_t XOR_CAA; //!< [0x984] Accumulator register - Exclusive Or command
bogdanm	82:6473597d706e	1439	__O hw_cau_xor_ca_t XOR_CA[9]; //!< [0x988] General Purpose Register 0 - Exclusive Or command
bogdanm	82:6473597d706e	1440	uint8_t _reserved5[20];
bogdanm	82:6473597d706e	1441	__O hw_cau_rotl_casr_t ROTL_CASR; //!< [0x9C0] Status register - Rotate Left command
bogdanm	82:6473597d706e	1442	__O hw_cau_rotl_caa_t ROTL_CAA; //!< [0x9C4] Accumulator register - Rotate Left command
bogdanm	82:6473597d706e	1443	__O hw_cau_rotl_ca_t ROTL_CA[9]; //!< [0x9C8] General Purpose Register 0 - Rotate Left command
bogdanm	82:6473597d706e	1444	uint8_t _reserved6[276];
bogdanm	82:6473597d706e	1445	__O hw_cau_aesc_casr_t AESC_CASR; //!< [0xB00] Status register - AES Column Operation command
bogdanm	82:6473597d706e	1446	__O hw_cau_aesc_caa_t AESC_CAA; //!< [0xB04] Accumulator register - AES Column Operation command
bogdanm	82:6473597d706e	1447	__O hw_cau_aesc_ca_t AESC_CA[9]; //!< [0xB08] General Purpose Register 0 - AES Column Operation command
bogdanm	82:6473597d706e	1448	uint8_t _reserved7[20];
bogdanm	82:6473597d706e	1449	__O hw_cau_aesic_casr_t AESIC_CASR; //!< [0xB40] Status register - AES Inverse Column Operation command
bogdanm	82:6473597d706e	1450	__O hw_cau_aesic_caa_t AESIC_CAA; //!< [0xB44] Accumulator register - AES Inverse Column Operation command
bogdanm	82:6473597d706e	1451	__O hw_cau_aesic_ca_t AESIC_CA[9]; //!< [0xB48] General Purpose Register 0 - AES Inverse Column Operation command
bogdanm	82:6473597d706e	1452	} hw_cau_t;
bogdanm	82:6473597d706e	1453	#pragma pack()
bogdanm	82:6473597d706e	1454
bogdanm	82:6473597d706e	1455	//! @brief Macro to access all CAU registers.
bogdanm	82:6473597d706e	1456	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	1457	//! use the '&' operator, like <code>&HW_CAU</code>.
bogdanm	82:6473597d706e	1458	#define HW_CAU ((hw_cau_t ) REGS_CAU_BASE)
bogdanm	82:6473597d706e	1459	#endif
bogdanm	82:6473597d706e	1460
bogdanm	82:6473597d706e	1461	#endif // __HW_CAU_REGISTERS_H__
bogdanm	82:6473597d706e	1462	// v22/130726/0.9
bogdanm	82:6473597d706e	1463	// EOF

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Type:	Library
Created:	05 Apr 2016
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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_cau.h@82:6473597d706e, 2014-04-07 (annotated)

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