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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_axbs.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_AXBS_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_AXBS_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 AXBS
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * Crossbar switch
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_AXBS_PRSn - Priority Registers Slave
bogdanm 82:6473597d706e 33 * - HW_AXBS_CRSn - Control Register
bogdanm 82:6473597d706e 34 * - HW_AXBS_MGPCR0 - Master General Purpose Control Register
bogdanm 82:6473597d706e 35 * - HW_AXBS_MGPCR1 - Master General Purpose Control Register
bogdanm 82:6473597d706e 36 * - HW_AXBS_MGPCR2 - Master General Purpose Control Register
bogdanm 82:6473597d706e 37 * - HW_AXBS_MGPCR3 - Master General Purpose Control Register
bogdanm 82:6473597d706e 38 * - HW_AXBS_MGPCR4 - Master General Purpose Control Register
bogdanm 82:6473597d706e 39 * - HW_AXBS_MGPCR5 - Master General Purpose Control Register
bogdanm 82:6473597d706e 40 *
bogdanm 82:6473597d706e 41 * - hw_axbs_t - Struct containing all module registers.
bogdanm 82:6473597d706e 42 */
bogdanm 82:6473597d706e 43
bogdanm 82:6473597d706e 44 //! @name Module base addresses
bogdanm 82:6473597d706e 45 //@{
bogdanm 82:6473597d706e 46 #ifndef REGS_AXBS_BASE
bogdanm 82:6473597d706e 47 #define HW_AXBS_INSTANCE_COUNT (1U) //!< Number of instances of the AXBS module.
bogdanm 82:6473597d706e 48 #define REGS_AXBS_BASE (0x40004000U) //!< Base address for AXBS.
bogdanm 82:6473597d706e 49 #endif
bogdanm 82:6473597d706e 50 //@}
bogdanm 82:6473597d706e 51
bogdanm 82:6473597d706e 52 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 53 // HW_AXBS_PRSn - Priority Registers Slave
bogdanm 82:6473597d706e 54 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 55
bogdanm 82:6473597d706e 56 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 57 /*!
bogdanm 82:6473597d706e 58 * @brief HW_AXBS_PRSn - Priority Registers Slave (RW)
bogdanm 82:6473597d706e 59 *
bogdanm 82:6473597d706e 60 * Reset value: 0x00543210U
bogdanm 82:6473597d706e 61 *
bogdanm 82:6473597d706e 62 * The priority registers (PRSn) set the priority of each master port on a per
bogdanm 82:6473597d706e 63 * slave port basis and reside in each slave port. The priority register can be
bogdanm 82:6473597d706e 64 * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
bogdanm 82:6473597d706e 65 * register can only be read; attempts to write to it have no effect on PRSn and
bogdanm 82:6473597d706e 66 * result in a bus-error response to the master initiating the write. Two available
bogdanm 82:6473597d706e 67 * masters must not be programmed with the same priority level. Attempts to
bogdanm 82:6473597d706e 68 * program two or more masters with the same priority level result in a bus-error
bogdanm 82:6473597d706e 69 * response and the PRSn is not updated. Valid values for the Mn priority fields
bogdanm 82:6473597d706e 70 * depend on which masters are available on the chip. This information can be found in
bogdanm 82:6473597d706e 71 * the chip-specific information for the crossbar. If the chip contains less
bogdanm 82:6473597d706e 72 * than five masters, values 0 to 3 are valid. Writing other values will result in
bogdanm 82:6473597d706e 73 * an error. If the chip contains five or more masters, valid values are 0 to n-1,
bogdanm 82:6473597d706e 74 * where n is the number of masters attached to the AXBS module. Other values
bogdanm 82:6473597d706e 75 * will result in an error.
bogdanm 82:6473597d706e 76 */
bogdanm 82:6473597d706e 77 typedef union _hw_axbs_prsn
bogdanm 82:6473597d706e 78 {
bogdanm 82:6473597d706e 79 uint32_t U;
bogdanm 82:6473597d706e 80 struct _hw_axbs_prsn_bitfields
bogdanm 82:6473597d706e 81 {
bogdanm 82:6473597d706e 82 uint32_t M0 : 3; //!< [2:0] Master 0 Priority. Sets the arbitration
bogdanm 82:6473597d706e 83 //! priority for this port on the associated slave port.
bogdanm 82:6473597d706e 84 uint32_t RESERVED0 : 1; //!< [3]
bogdanm 82:6473597d706e 85 uint32_t M1 : 3; //!< [6:4] Master 1 Priority. Sets the arbitration
bogdanm 82:6473597d706e 86 //! priority for this port on the associated slave port.
bogdanm 82:6473597d706e 87 uint32_t RESERVED1 : 1; //!< [7]
bogdanm 82:6473597d706e 88 uint32_t M2 : 3; //!< [10:8] Master 2 Priority. Sets the arbitration
bogdanm 82:6473597d706e 89 //! priority for this port on the associated slave port.
bogdanm 82:6473597d706e 90 uint32_t RESERVED2 : 1; //!< [11]
bogdanm 82:6473597d706e 91 uint32_t M3 : 3; //!< [14:12] Master 3 Priority. Sets the arbitration
bogdanm 82:6473597d706e 92 //! priority for this port on the associated slave port.
bogdanm 82:6473597d706e 93 uint32_t RESERVED3 : 1; //!< [15]
bogdanm 82:6473597d706e 94 uint32_t M4 : 3; //!< [18:16] Master 4 Priority. Sets the arbitration
bogdanm 82:6473597d706e 95 //! priority for this port on the associated slave port.
bogdanm 82:6473597d706e 96 uint32_t RESERVED4 : 1; //!< [19]
bogdanm 82:6473597d706e 97 uint32_t M5 : 3; //!< [22:20] Master 5 Priority. Sets the arbitration
bogdanm 82:6473597d706e 98 //! priority for this port on the associated slave port.
bogdanm 82:6473597d706e 99 uint32_t RESERVED5 : 9; //!< [31:23]
bogdanm 82:6473597d706e 100 } B;
bogdanm 82:6473597d706e 101 } hw_axbs_prsn_t;
bogdanm 82:6473597d706e 102 #endif
bogdanm 82:6473597d706e 103
bogdanm 82:6473597d706e 104 /*!
bogdanm 82:6473597d706e 105 * @name Constants and macros for entire AXBS_PRSn register
bogdanm 82:6473597d706e 106 */
bogdanm 82:6473597d706e 107 //@{
bogdanm 82:6473597d706e 108 #define HW_AXBS_PRSn_COUNT (5U)
bogdanm 82:6473597d706e 109
bogdanm 82:6473597d706e 110 #define HW_AXBS_PRSn_ADDR(n) (REGS_AXBS_BASE + 0x0U + (0x100U * n))
bogdanm 82:6473597d706e 111
bogdanm 82:6473597d706e 112 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 113 #define HW_AXBS_PRSn(n) (*(__IO hw_axbs_prsn_t *) HW_AXBS_PRSn_ADDR(n))
bogdanm 82:6473597d706e 114 #define HW_AXBS_PRSn_RD(n) (HW_AXBS_PRSn(n).U)
bogdanm 82:6473597d706e 115 #define HW_AXBS_PRSn_WR(n, v) (HW_AXBS_PRSn(n).U = (v))
bogdanm 82:6473597d706e 116 #define HW_AXBS_PRSn_SET(n, v) (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) | (v)))
bogdanm 82:6473597d706e 117 #define HW_AXBS_PRSn_CLR(n, v) (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) & ~(v)))
bogdanm 82:6473597d706e 118 #define HW_AXBS_PRSn_TOG(n, v) (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) ^ (v)))
bogdanm 82:6473597d706e 119 #endif
bogdanm 82:6473597d706e 120 //@}
bogdanm 82:6473597d706e 121
bogdanm 82:6473597d706e 122 /*
bogdanm 82:6473597d706e 123 * Constants & macros for individual AXBS_PRSn bitfields
bogdanm 82:6473597d706e 124 */
bogdanm 82:6473597d706e 125
bogdanm 82:6473597d706e 126 /*!
bogdanm 82:6473597d706e 127 * @name Register AXBS_PRSn, field M0[2:0] (RW)
bogdanm 82:6473597d706e 128 *
bogdanm 82:6473597d706e 129 * Values:
bogdanm 82:6473597d706e 130 * - 000 - This master has level 1, or highest, priority when accessing the
bogdanm 82:6473597d706e 131 * slave port.
bogdanm 82:6473597d706e 132 * - 001 - This master has level 2 priority when accessing the slave port.
bogdanm 82:6473597d706e 133 * - 010 - This master has level 3 priority when accessing the slave port.
bogdanm 82:6473597d706e 134 * - 011 - This master has level 4 priority when accessing the slave port.
bogdanm 82:6473597d706e 135 * - 100 - This master has level 5 priority when accessing the slave port.
bogdanm 82:6473597d706e 136 * - 101 - This master has level 6 priority when accessing the slave port.
bogdanm 82:6473597d706e 137 * - 110 - This master has level 7 priority when accessing the slave port.
bogdanm 82:6473597d706e 138 * - 111 - This master has level 8, or lowest, priority when accessing the slave
bogdanm 82:6473597d706e 139 * port.
bogdanm 82:6473597d706e 140 */
bogdanm 82:6473597d706e 141 //@{
bogdanm 82:6473597d706e 142 #define BP_AXBS_PRSn_M0 (0U) //!< Bit position for AXBS_PRSn_M0.
bogdanm 82:6473597d706e 143 #define BM_AXBS_PRSn_M0 (0x00000007U) //!< Bit mask for AXBS_PRSn_M0.
bogdanm 82:6473597d706e 144 #define BS_AXBS_PRSn_M0 (3U) //!< Bit field size in bits for AXBS_PRSn_M0.
bogdanm 82:6473597d706e 145
bogdanm 82:6473597d706e 146 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 147 //! @brief Read current value of the AXBS_PRSn_M0 field.
bogdanm 82:6473597d706e 148 #define BR_AXBS_PRSn_M0(n) (HW_AXBS_PRSn(n).B.M0)
bogdanm 82:6473597d706e 149 #endif
bogdanm 82:6473597d706e 150
bogdanm 82:6473597d706e 151 //! @brief Format value for bitfield AXBS_PRSn_M0.
bogdanm 82:6473597d706e 152 #define BF_AXBS_PRSn_M0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M0), uint32_t) & BM_AXBS_PRSn_M0)
bogdanm 82:6473597d706e 153
bogdanm 82:6473597d706e 154 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 155 //! @brief Set the M0 field to a new value.
bogdanm 82:6473597d706e 156 #define BW_AXBS_PRSn_M0(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M0) | BF_AXBS_PRSn_M0(v)))
bogdanm 82:6473597d706e 157 #endif
bogdanm 82:6473597d706e 158 //@}
bogdanm 82:6473597d706e 159
bogdanm 82:6473597d706e 160 /*!
bogdanm 82:6473597d706e 161 * @name Register AXBS_PRSn, field M1[6:4] (RW)
bogdanm 82:6473597d706e 162 *
bogdanm 82:6473597d706e 163 * Values:
bogdanm 82:6473597d706e 164 * - 000 - This master has level 1, or highest, priority when accessing the
bogdanm 82:6473597d706e 165 * slave port.
bogdanm 82:6473597d706e 166 * - 001 - This master has level 2 priority when accessing the slave port.
bogdanm 82:6473597d706e 167 * - 010 - This master has level 3 priority when accessing the slave port.
bogdanm 82:6473597d706e 168 * - 011 - This master has level 4 priority when accessing the slave port.
bogdanm 82:6473597d706e 169 * - 100 - This master has level 5 priority when accessing the slave port.
bogdanm 82:6473597d706e 170 * - 101 - This master has level 6 priority when accessing the slave port.
bogdanm 82:6473597d706e 171 * - 110 - This master has level 7 priority when accessing the slave port.
bogdanm 82:6473597d706e 172 * - 111 - This master has level 8, or lowest, priority when accessing the slave
bogdanm 82:6473597d706e 173 * port.
bogdanm 82:6473597d706e 174 */
bogdanm 82:6473597d706e 175 //@{
bogdanm 82:6473597d706e 176 #define BP_AXBS_PRSn_M1 (4U) //!< Bit position for AXBS_PRSn_M1.
bogdanm 82:6473597d706e 177 #define BM_AXBS_PRSn_M1 (0x00000070U) //!< Bit mask for AXBS_PRSn_M1.
bogdanm 82:6473597d706e 178 #define BS_AXBS_PRSn_M1 (3U) //!< Bit field size in bits for AXBS_PRSn_M1.
bogdanm 82:6473597d706e 179
bogdanm 82:6473597d706e 180 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 181 //! @brief Read current value of the AXBS_PRSn_M1 field.
bogdanm 82:6473597d706e 182 #define BR_AXBS_PRSn_M1(n) (HW_AXBS_PRSn(n).B.M1)
bogdanm 82:6473597d706e 183 #endif
bogdanm 82:6473597d706e 184
bogdanm 82:6473597d706e 185 //! @brief Format value for bitfield AXBS_PRSn_M1.
bogdanm 82:6473597d706e 186 #define BF_AXBS_PRSn_M1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M1), uint32_t) & BM_AXBS_PRSn_M1)
bogdanm 82:6473597d706e 187
bogdanm 82:6473597d706e 188 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 189 //! @brief Set the M1 field to a new value.
bogdanm 82:6473597d706e 190 #define BW_AXBS_PRSn_M1(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M1) | BF_AXBS_PRSn_M1(v)))
bogdanm 82:6473597d706e 191 #endif
bogdanm 82:6473597d706e 192 //@}
bogdanm 82:6473597d706e 193
bogdanm 82:6473597d706e 194 /*!
bogdanm 82:6473597d706e 195 * @name Register AXBS_PRSn, field M2[10:8] (RW)
bogdanm 82:6473597d706e 196 *
bogdanm 82:6473597d706e 197 * Values:
bogdanm 82:6473597d706e 198 * - 000 - This master has level 1, or highest, priority when accessing the
bogdanm 82:6473597d706e 199 * slave port.
bogdanm 82:6473597d706e 200 * - 001 - This master has level 2 priority when accessing the slave port.
bogdanm 82:6473597d706e 201 * - 010 - This master has level 3 priority when accessing the slave port.
bogdanm 82:6473597d706e 202 * - 011 - This master has level 4 priority when accessing the slave port.
bogdanm 82:6473597d706e 203 * - 100 - This master has level 5 priority when accessing the slave port.
bogdanm 82:6473597d706e 204 * - 101 - This master has level 6 priority when accessing the slave port.
bogdanm 82:6473597d706e 205 * - 110 - This master has level 7 priority when accessing the slave port.
bogdanm 82:6473597d706e 206 * - 111 - This master has level 8, or lowest, priority when accessing the slave
bogdanm 82:6473597d706e 207 * port.
bogdanm 82:6473597d706e 208 */
bogdanm 82:6473597d706e 209 //@{
bogdanm 82:6473597d706e 210 #define BP_AXBS_PRSn_M2 (8U) //!< Bit position for AXBS_PRSn_M2.
bogdanm 82:6473597d706e 211 #define BM_AXBS_PRSn_M2 (0x00000700U) //!< Bit mask for AXBS_PRSn_M2.
bogdanm 82:6473597d706e 212 #define BS_AXBS_PRSn_M2 (3U) //!< Bit field size in bits for AXBS_PRSn_M2.
bogdanm 82:6473597d706e 213
bogdanm 82:6473597d706e 214 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 215 //! @brief Read current value of the AXBS_PRSn_M2 field.
bogdanm 82:6473597d706e 216 #define BR_AXBS_PRSn_M2(n) (HW_AXBS_PRSn(n).B.M2)
bogdanm 82:6473597d706e 217 #endif
bogdanm 82:6473597d706e 218
bogdanm 82:6473597d706e 219 //! @brief Format value for bitfield AXBS_PRSn_M2.
bogdanm 82:6473597d706e 220 #define BF_AXBS_PRSn_M2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M2), uint32_t) & BM_AXBS_PRSn_M2)
bogdanm 82:6473597d706e 221
bogdanm 82:6473597d706e 222 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 223 //! @brief Set the M2 field to a new value.
bogdanm 82:6473597d706e 224 #define BW_AXBS_PRSn_M2(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M2) | BF_AXBS_PRSn_M2(v)))
bogdanm 82:6473597d706e 225 #endif
bogdanm 82:6473597d706e 226 //@}
bogdanm 82:6473597d706e 227
bogdanm 82:6473597d706e 228 /*!
bogdanm 82:6473597d706e 229 * @name Register AXBS_PRSn, field M3[14:12] (RW)
bogdanm 82:6473597d706e 230 *
bogdanm 82:6473597d706e 231 * Values:
bogdanm 82:6473597d706e 232 * - 000 - This master has level 1, or highest, priority when accessing the
bogdanm 82:6473597d706e 233 * slave port.
bogdanm 82:6473597d706e 234 * - 001 - This master has level 2 priority when accessing the slave port.
bogdanm 82:6473597d706e 235 * - 010 - This master has level 3 priority when accessing the slave port.
bogdanm 82:6473597d706e 236 * - 011 - This master has level 4 priority when accessing the slave port.
bogdanm 82:6473597d706e 237 * - 100 - This master has level 5 priority when accessing the slave port.
bogdanm 82:6473597d706e 238 * - 101 - This master has level 6 priority when accessing the slave port.
bogdanm 82:6473597d706e 239 * - 110 - This master has level 7 priority when accessing the slave port.
bogdanm 82:6473597d706e 240 * - 111 - This master has level 8, or lowest, priority when accessing the slave
bogdanm 82:6473597d706e 241 * port.
bogdanm 82:6473597d706e 242 */
bogdanm 82:6473597d706e 243 //@{
bogdanm 82:6473597d706e 244 #define BP_AXBS_PRSn_M3 (12U) //!< Bit position for AXBS_PRSn_M3.
bogdanm 82:6473597d706e 245 #define BM_AXBS_PRSn_M3 (0x00007000U) //!< Bit mask for AXBS_PRSn_M3.
bogdanm 82:6473597d706e 246 #define BS_AXBS_PRSn_M3 (3U) //!< Bit field size in bits for AXBS_PRSn_M3.
bogdanm 82:6473597d706e 247
bogdanm 82:6473597d706e 248 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 249 //! @brief Read current value of the AXBS_PRSn_M3 field.
bogdanm 82:6473597d706e 250 #define BR_AXBS_PRSn_M3(n) (HW_AXBS_PRSn(n).B.M3)
bogdanm 82:6473597d706e 251 #endif
bogdanm 82:6473597d706e 252
bogdanm 82:6473597d706e 253 //! @brief Format value for bitfield AXBS_PRSn_M3.
bogdanm 82:6473597d706e 254 #define BF_AXBS_PRSn_M3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M3), uint32_t) & BM_AXBS_PRSn_M3)
bogdanm 82:6473597d706e 255
bogdanm 82:6473597d706e 256 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 257 //! @brief Set the M3 field to a new value.
bogdanm 82:6473597d706e 258 #define BW_AXBS_PRSn_M3(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M3) | BF_AXBS_PRSn_M3(v)))
bogdanm 82:6473597d706e 259 #endif
bogdanm 82:6473597d706e 260 //@}
bogdanm 82:6473597d706e 261
bogdanm 82:6473597d706e 262 /*!
bogdanm 82:6473597d706e 263 * @name Register AXBS_PRSn, field M4[18:16] (RW)
bogdanm 82:6473597d706e 264 *
bogdanm 82:6473597d706e 265 * Values:
bogdanm 82:6473597d706e 266 * - 000 - This master has level 1, or highest, priority when accessing the
bogdanm 82:6473597d706e 267 * slave port.
bogdanm 82:6473597d706e 268 * - 001 - This master has level 2 priority when accessing the slave port.
bogdanm 82:6473597d706e 269 * - 010 - This master has level 3 priority when accessing the slave port.
bogdanm 82:6473597d706e 270 * - 011 - This master has level 4 priority when accessing the slave port.
bogdanm 82:6473597d706e 271 * - 100 - This master has level 5 priority when accessing the slave port.
bogdanm 82:6473597d706e 272 * - 101 - This master has level 6 priority when accessing the slave port.
bogdanm 82:6473597d706e 273 * - 110 - This master has level 7 priority when accessing the slave port.
bogdanm 82:6473597d706e 274 * - 111 - This master has level 8, or lowest, priority when accessing the slave
bogdanm 82:6473597d706e 275 * port.
bogdanm 82:6473597d706e 276 */
bogdanm 82:6473597d706e 277 //@{
bogdanm 82:6473597d706e 278 #define BP_AXBS_PRSn_M4 (16U) //!< Bit position for AXBS_PRSn_M4.
bogdanm 82:6473597d706e 279 #define BM_AXBS_PRSn_M4 (0x00070000U) //!< Bit mask for AXBS_PRSn_M4.
bogdanm 82:6473597d706e 280 #define BS_AXBS_PRSn_M4 (3U) //!< Bit field size in bits for AXBS_PRSn_M4.
bogdanm 82:6473597d706e 281
bogdanm 82:6473597d706e 282 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 283 //! @brief Read current value of the AXBS_PRSn_M4 field.
bogdanm 82:6473597d706e 284 #define BR_AXBS_PRSn_M4(n) (HW_AXBS_PRSn(n).B.M4)
bogdanm 82:6473597d706e 285 #endif
bogdanm 82:6473597d706e 286
bogdanm 82:6473597d706e 287 //! @brief Format value for bitfield AXBS_PRSn_M4.
bogdanm 82:6473597d706e 288 #define BF_AXBS_PRSn_M4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M4), uint32_t) & BM_AXBS_PRSn_M4)
bogdanm 82:6473597d706e 289
bogdanm 82:6473597d706e 290 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 291 //! @brief Set the M4 field to a new value.
bogdanm 82:6473597d706e 292 #define BW_AXBS_PRSn_M4(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M4) | BF_AXBS_PRSn_M4(v)))
bogdanm 82:6473597d706e 293 #endif
bogdanm 82:6473597d706e 294 //@}
bogdanm 82:6473597d706e 295
bogdanm 82:6473597d706e 296 /*!
bogdanm 82:6473597d706e 297 * @name Register AXBS_PRSn, field M5[22:20] (RW)
bogdanm 82:6473597d706e 298 *
bogdanm 82:6473597d706e 299 * Values:
bogdanm 82:6473597d706e 300 * - 000 - This master has level 1, or highest, priority when accessing the
bogdanm 82:6473597d706e 301 * slave port.
bogdanm 82:6473597d706e 302 * - 001 - This master has level 2 priority when accessing the slave port.
bogdanm 82:6473597d706e 303 * - 010 - This master has level 3 priority when accessing the slave port.
bogdanm 82:6473597d706e 304 * - 011 - This master has level 4 priority when accessing the slave port.
bogdanm 82:6473597d706e 305 * - 100 - This master has level 5 priority when accessing the slave port.
bogdanm 82:6473597d706e 306 * - 101 - This master has level 6 priority when accessing the slave port.
bogdanm 82:6473597d706e 307 * - 110 - This master has level 7 priority when accessing the slave port.
bogdanm 82:6473597d706e 308 * - 111 - This master has level 8, or lowest, priority when accessing the slave
bogdanm 82:6473597d706e 309 * port.
bogdanm 82:6473597d706e 310 */
bogdanm 82:6473597d706e 311 //@{
bogdanm 82:6473597d706e 312 #define BP_AXBS_PRSn_M5 (20U) //!< Bit position for AXBS_PRSn_M5.
bogdanm 82:6473597d706e 313 #define BM_AXBS_PRSn_M5 (0x00700000U) //!< Bit mask for AXBS_PRSn_M5.
bogdanm 82:6473597d706e 314 #define BS_AXBS_PRSn_M5 (3U) //!< Bit field size in bits for AXBS_PRSn_M5.
bogdanm 82:6473597d706e 315
bogdanm 82:6473597d706e 316 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 317 //! @brief Read current value of the AXBS_PRSn_M5 field.
bogdanm 82:6473597d706e 318 #define BR_AXBS_PRSn_M5(n) (HW_AXBS_PRSn(n).B.M5)
bogdanm 82:6473597d706e 319 #endif
bogdanm 82:6473597d706e 320
bogdanm 82:6473597d706e 321 //! @brief Format value for bitfield AXBS_PRSn_M5.
bogdanm 82:6473597d706e 322 #define BF_AXBS_PRSn_M5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M5), uint32_t) & BM_AXBS_PRSn_M5)
bogdanm 82:6473597d706e 323
bogdanm 82:6473597d706e 324 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 325 //! @brief Set the M5 field to a new value.
bogdanm 82:6473597d706e 326 #define BW_AXBS_PRSn_M5(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M5) | BF_AXBS_PRSn_M5(v)))
bogdanm 82:6473597d706e 327 #endif
bogdanm 82:6473597d706e 328 //@}
bogdanm 82:6473597d706e 329 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 330 // HW_AXBS_CRSn - Control Register
bogdanm 82:6473597d706e 331 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 332
bogdanm 82:6473597d706e 333 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 334 /*!
bogdanm 82:6473597d706e 335 * @brief HW_AXBS_CRSn - Control Register (RW)
bogdanm 82:6473597d706e 336 *
bogdanm 82:6473597d706e 337 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 338 *
bogdanm 82:6473597d706e 339 * These registers control several features of each slave port and must be
bogdanm 82:6473597d706e 340 * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
bogdanm 82:6473597d706e 341 * attempts to write to it have no effect and result in an error response.
bogdanm 82:6473597d706e 342 */
bogdanm 82:6473597d706e 343 typedef union _hw_axbs_crsn
bogdanm 82:6473597d706e 344 {
bogdanm 82:6473597d706e 345 uint32_t U;
bogdanm 82:6473597d706e 346 struct _hw_axbs_crsn_bitfields
bogdanm 82:6473597d706e 347 {
bogdanm 82:6473597d706e 348 uint32_t PARK : 3; //!< [2:0] Park
bogdanm 82:6473597d706e 349 uint32_t RESERVED0 : 1; //!< [3]
bogdanm 82:6473597d706e 350 uint32_t PCTL : 2; //!< [5:4] Parking Control
bogdanm 82:6473597d706e 351 uint32_t RESERVED1 : 2; //!< [7:6]
bogdanm 82:6473597d706e 352 uint32_t ARB : 2; //!< [9:8] Arbitration Mode
bogdanm 82:6473597d706e 353 uint32_t RESERVED2 : 20; //!< [29:10]
bogdanm 82:6473597d706e 354 uint32_t HLP : 1; //!< [30] Halt Low Priority
bogdanm 82:6473597d706e 355 uint32_t RO : 1; //!< [31] Read Only
bogdanm 82:6473597d706e 356 } B;
bogdanm 82:6473597d706e 357 } hw_axbs_crsn_t;
bogdanm 82:6473597d706e 358 #endif
bogdanm 82:6473597d706e 359
bogdanm 82:6473597d706e 360 /*!
bogdanm 82:6473597d706e 361 * @name Constants and macros for entire AXBS_CRSn register
bogdanm 82:6473597d706e 362 */
bogdanm 82:6473597d706e 363 //@{
bogdanm 82:6473597d706e 364 #define HW_AXBS_CRSn_COUNT (5U)
bogdanm 82:6473597d706e 365
bogdanm 82:6473597d706e 366 #define HW_AXBS_CRSn_ADDR(n) (REGS_AXBS_BASE + 0x10U + (0x100U * n))
bogdanm 82:6473597d706e 367
bogdanm 82:6473597d706e 368 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 369 #define HW_AXBS_CRSn(n) (*(__IO hw_axbs_crsn_t *) HW_AXBS_CRSn_ADDR(n))
bogdanm 82:6473597d706e 370 #define HW_AXBS_CRSn_RD(n) (HW_AXBS_CRSn(n).U)
bogdanm 82:6473597d706e 371 #define HW_AXBS_CRSn_WR(n, v) (HW_AXBS_CRSn(n).U = (v))
bogdanm 82:6473597d706e 372 #define HW_AXBS_CRSn_SET(n, v) (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) | (v)))
bogdanm 82:6473597d706e 373 #define HW_AXBS_CRSn_CLR(n, v) (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) & ~(v)))
bogdanm 82:6473597d706e 374 #define HW_AXBS_CRSn_TOG(n, v) (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) ^ (v)))
bogdanm 82:6473597d706e 375 #endif
bogdanm 82:6473597d706e 376 //@}
bogdanm 82:6473597d706e 377
bogdanm 82:6473597d706e 378 /*
bogdanm 82:6473597d706e 379 * Constants & macros for individual AXBS_CRSn bitfields
bogdanm 82:6473597d706e 380 */
bogdanm 82:6473597d706e 381
bogdanm 82:6473597d706e 382 /*!
bogdanm 82:6473597d706e 383 * @name Register AXBS_CRSn, field PARK[2:0] (RW)
bogdanm 82:6473597d706e 384 *
bogdanm 82:6473597d706e 385 * Determines which master port the current slave port parks on when no masters
bogdanm 82:6473597d706e 386 * are actively making requests and the PCTL bits are cleared. Select only master
bogdanm 82:6473597d706e 387 * ports that are present on the chip. Otherwise, undefined behavior might occur.
bogdanm 82:6473597d706e 388 *
bogdanm 82:6473597d706e 389 * Values:
bogdanm 82:6473597d706e 390 * - 000 - Park on master port M0
bogdanm 82:6473597d706e 391 * - 001 - Park on master port M1
bogdanm 82:6473597d706e 392 * - 010 - Park on master port M2
bogdanm 82:6473597d706e 393 * - 011 - Park on master port M3
bogdanm 82:6473597d706e 394 * - 100 - Park on master port M4
bogdanm 82:6473597d706e 395 * - 101 - Park on master port M5
bogdanm 82:6473597d706e 396 * - 110 - Park on master port M6
bogdanm 82:6473597d706e 397 * - 111 - Park on master port M7
bogdanm 82:6473597d706e 398 */
bogdanm 82:6473597d706e 399 //@{
bogdanm 82:6473597d706e 400 #define BP_AXBS_CRSn_PARK (0U) //!< Bit position for AXBS_CRSn_PARK.
bogdanm 82:6473597d706e 401 #define BM_AXBS_CRSn_PARK (0x00000007U) //!< Bit mask for AXBS_CRSn_PARK.
bogdanm 82:6473597d706e 402 #define BS_AXBS_CRSn_PARK (3U) //!< Bit field size in bits for AXBS_CRSn_PARK.
bogdanm 82:6473597d706e 403
bogdanm 82:6473597d706e 404 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 405 //! @brief Read current value of the AXBS_CRSn_PARK field.
bogdanm 82:6473597d706e 406 #define BR_AXBS_CRSn_PARK(n) (HW_AXBS_CRSn(n).B.PARK)
bogdanm 82:6473597d706e 407 #endif
bogdanm 82:6473597d706e 408
bogdanm 82:6473597d706e 409 //! @brief Format value for bitfield AXBS_CRSn_PARK.
bogdanm 82:6473597d706e 410 #define BF_AXBS_CRSn_PARK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_PARK), uint32_t) & BM_AXBS_CRSn_PARK)
bogdanm 82:6473597d706e 411
bogdanm 82:6473597d706e 412 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 413 //! @brief Set the PARK field to a new value.
bogdanm 82:6473597d706e 414 #define BW_AXBS_CRSn_PARK(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_PARK) | BF_AXBS_CRSn_PARK(v)))
bogdanm 82:6473597d706e 415 #endif
bogdanm 82:6473597d706e 416 //@}
bogdanm 82:6473597d706e 417
bogdanm 82:6473597d706e 418 /*!
bogdanm 82:6473597d706e 419 * @name Register AXBS_CRSn, field PCTL[5:4] (RW)
bogdanm 82:6473597d706e 420 *
bogdanm 82:6473597d706e 421 * Determines the slave port's parking control. The low-power park feature
bogdanm 82:6473597d706e 422 * results in an overall power savings if the slave port is not saturated. However,
bogdanm 82:6473597d706e 423 * this forces an extra latency clock when any master tries to access the slave
bogdanm 82:6473597d706e 424 * port while not in use because it is not parked on any master.
bogdanm 82:6473597d706e 425 *
bogdanm 82:6473597d706e 426 * Values:
bogdanm 82:6473597d706e 427 * - 00 - When no master makes a request, the arbiter parks the slave port on
bogdanm 82:6473597d706e 428 * the master port defined by the PARK field
bogdanm 82:6473597d706e 429 * - 01 - When no master makes a request, the arbiter parks the slave port on
bogdanm 82:6473597d706e 430 * the last master to be in control of the slave port
bogdanm 82:6473597d706e 431 * - 10 - When no master makes a request, the slave port is not parked on a
bogdanm 82:6473597d706e 432 * master and the arbiter drives all outputs to a constant safe state
bogdanm 82:6473597d706e 433 * - 11 - Reserved
bogdanm 82:6473597d706e 434 */
bogdanm 82:6473597d706e 435 //@{
bogdanm 82:6473597d706e 436 #define BP_AXBS_CRSn_PCTL (4U) //!< Bit position for AXBS_CRSn_PCTL.
bogdanm 82:6473597d706e 437 #define BM_AXBS_CRSn_PCTL (0x00000030U) //!< Bit mask for AXBS_CRSn_PCTL.
bogdanm 82:6473597d706e 438 #define BS_AXBS_CRSn_PCTL (2U) //!< Bit field size in bits for AXBS_CRSn_PCTL.
bogdanm 82:6473597d706e 439
bogdanm 82:6473597d706e 440 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 441 //! @brief Read current value of the AXBS_CRSn_PCTL field.
bogdanm 82:6473597d706e 442 #define BR_AXBS_CRSn_PCTL(n) (HW_AXBS_CRSn(n).B.PCTL)
bogdanm 82:6473597d706e 443 #endif
bogdanm 82:6473597d706e 444
bogdanm 82:6473597d706e 445 //! @brief Format value for bitfield AXBS_CRSn_PCTL.
bogdanm 82:6473597d706e 446 #define BF_AXBS_CRSn_PCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_PCTL), uint32_t) & BM_AXBS_CRSn_PCTL)
bogdanm 82:6473597d706e 447
bogdanm 82:6473597d706e 448 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 449 //! @brief Set the PCTL field to a new value.
bogdanm 82:6473597d706e 450 #define BW_AXBS_CRSn_PCTL(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_PCTL) | BF_AXBS_CRSn_PCTL(v)))
bogdanm 82:6473597d706e 451 #endif
bogdanm 82:6473597d706e 452 //@}
bogdanm 82:6473597d706e 453
bogdanm 82:6473597d706e 454 /*!
bogdanm 82:6473597d706e 455 * @name Register AXBS_CRSn, field ARB[9:8] (RW)
bogdanm 82:6473597d706e 456 *
bogdanm 82:6473597d706e 457 * Selects the arbitration policy for the slave port.
bogdanm 82:6473597d706e 458 *
bogdanm 82:6473597d706e 459 * Values:
bogdanm 82:6473597d706e 460 * - 00 - Fixed priority
bogdanm 82:6473597d706e 461 * - 01 - Round-robin, or rotating, priority
bogdanm 82:6473597d706e 462 * - 10 - Reserved
bogdanm 82:6473597d706e 463 * - 11 - Reserved
bogdanm 82:6473597d706e 464 */
bogdanm 82:6473597d706e 465 //@{
bogdanm 82:6473597d706e 466 #define BP_AXBS_CRSn_ARB (8U) //!< Bit position for AXBS_CRSn_ARB.
bogdanm 82:6473597d706e 467 #define BM_AXBS_CRSn_ARB (0x00000300U) //!< Bit mask for AXBS_CRSn_ARB.
bogdanm 82:6473597d706e 468 #define BS_AXBS_CRSn_ARB (2U) //!< Bit field size in bits for AXBS_CRSn_ARB.
bogdanm 82:6473597d706e 469
bogdanm 82:6473597d706e 470 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 471 //! @brief Read current value of the AXBS_CRSn_ARB field.
bogdanm 82:6473597d706e 472 #define BR_AXBS_CRSn_ARB(n) (HW_AXBS_CRSn(n).B.ARB)
bogdanm 82:6473597d706e 473 #endif
bogdanm 82:6473597d706e 474
bogdanm 82:6473597d706e 475 //! @brief Format value for bitfield AXBS_CRSn_ARB.
bogdanm 82:6473597d706e 476 #define BF_AXBS_CRSn_ARB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_ARB), uint32_t) & BM_AXBS_CRSn_ARB)
bogdanm 82:6473597d706e 477
bogdanm 82:6473597d706e 478 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 479 //! @brief Set the ARB field to a new value.
bogdanm 82:6473597d706e 480 #define BW_AXBS_CRSn_ARB(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_ARB) | BF_AXBS_CRSn_ARB(v)))
bogdanm 82:6473597d706e 481 #endif
bogdanm 82:6473597d706e 482 //@}
bogdanm 82:6473597d706e 483
bogdanm 82:6473597d706e 484 /*!
bogdanm 82:6473597d706e 485 * @name Register AXBS_CRSn, field HLP[30] (RW)
bogdanm 82:6473597d706e 486 *
bogdanm 82:6473597d706e 487 * Sets the initial arbitration priority for low power mode requests . Setting
bogdanm 82:6473597d706e 488 * this bit will not affect the request for low power mode from attaining highest
bogdanm 82:6473597d706e 489 * priority once it has control of the slave ports.
bogdanm 82:6473597d706e 490 *
bogdanm 82:6473597d706e 491 * Values:
bogdanm 82:6473597d706e 492 * - 0 - The low power mode request has the highest priority for arbitration on
bogdanm 82:6473597d706e 493 * this slave port
bogdanm 82:6473597d706e 494 * - 1 - The low power mode request has the lowest initial priority for
bogdanm 82:6473597d706e 495 * arbitration on this slave port
bogdanm 82:6473597d706e 496 */
bogdanm 82:6473597d706e 497 //@{
bogdanm 82:6473597d706e 498 #define BP_AXBS_CRSn_HLP (30U) //!< Bit position for AXBS_CRSn_HLP.
bogdanm 82:6473597d706e 499 #define BM_AXBS_CRSn_HLP (0x40000000U) //!< Bit mask for AXBS_CRSn_HLP.
bogdanm 82:6473597d706e 500 #define BS_AXBS_CRSn_HLP (1U) //!< Bit field size in bits for AXBS_CRSn_HLP.
bogdanm 82:6473597d706e 501
bogdanm 82:6473597d706e 502 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 503 //! @brief Read current value of the AXBS_CRSn_HLP field.
bogdanm 82:6473597d706e 504 #define BR_AXBS_CRSn_HLP(n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_HLP))
bogdanm 82:6473597d706e 505 #endif
bogdanm 82:6473597d706e 506
bogdanm 82:6473597d706e 507 //! @brief Format value for bitfield AXBS_CRSn_HLP.
bogdanm 82:6473597d706e 508 #define BF_AXBS_CRSn_HLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_HLP), uint32_t) & BM_AXBS_CRSn_HLP)
bogdanm 82:6473597d706e 509
bogdanm 82:6473597d706e 510 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 511 //! @brief Set the HLP field to a new value.
bogdanm 82:6473597d706e 512 #define BW_AXBS_CRSn_HLP(n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_HLP) = (v))
bogdanm 82:6473597d706e 513 #endif
bogdanm 82:6473597d706e 514 //@}
bogdanm 82:6473597d706e 515
bogdanm 82:6473597d706e 516 /*!
bogdanm 82:6473597d706e 517 * @name Register AXBS_CRSn, field RO[31] (RW)
bogdanm 82:6473597d706e 518 *
bogdanm 82:6473597d706e 519 * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
bogdanm 82:6473597d706e 520 * only a hardware reset clears it.
bogdanm 82:6473597d706e 521 *
bogdanm 82:6473597d706e 522 * Values:
bogdanm 82:6473597d706e 523 * - 0 - The slave port's registers are writeable
bogdanm 82:6473597d706e 524 * - 1 - The slave port's registers are read-only and cannot be written.
bogdanm 82:6473597d706e 525 * Attempted writes have no effect on the registers and result in a bus error
bogdanm 82:6473597d706e 526 * response.
bogdanm 82:6473597d706e 527 */
bogdanm 82:6473597d706e 528 //@{
bogdanm 82:6473597d706e 529 #define BP_AXBS_CRSn_RO (31U) //!< Bit position for AXBS_CRSn_RO.
bogdanm 82:6473597d706e 530 #define BM_AXBS_CRSn_RO (0x80000000U) //!< Bit mask for AXBS_CRSn_RO.
bogdanm 82:6473597d706e 531 #define BS_AXBS_CRSn_RO (1U) //!< Bit field size in bits for AXBS_CRSn_RO.
bogdanm 82:6473597d706e 532
bogdanm 82:6473597d706e 533 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 534 //! @brief Read current value of the AXBS_CRSn_RO field.
bogdanm 82:6473597d706e 535 #define BR_AXBS_CRSn_RO(n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_RO))
bogdanm 82:6473597d706e 536 #endif
bogdanm 82:6473597d706e 537
bogdanm 82:6473597d706e 538 //! @brief Format value for bitfield AXBS_CRSn_RO.
bogdanm 82:6473597d706e 539 #define BF_AXBS_CRSn_RO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_RO), uint32_t) & BM_AXBS_CRSn_RO)
bogdanm 82:6473597d706e 540
bogdanm 82:6473597d706e 541 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 542 //! @brief Set the RO field to a new value.
bogdanm 82:6473597d706e 543 #define BW_AXBS_CRSn_RO(n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_RO) = (v))
bogdanm 82:6473597d706e 544 #endif
bogdanm 82:6473597d706e 545 //@}
bogdanm 82:6473597d706e 546
bogdanm 82:6473597d706e 547 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 548 // HW_AXBS_MGPCR0 - Master General Purpose Control Register
bogdanm 82:6473597d706e 549 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 550
bogdanm 82:6473597d706e 551 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 552 /*!
bogdanm 82:6473597d706e 553 * @brief HW_AXBS_MGPCR0 - Master General Purpose Control Register (RW)
bogdanm 82:6473597d706e 554 *
bogdanm 82:6473597d706e 555 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 556 *
bogdanm 82:6473597d706e 557 * The MGPCR controls only whether the master's undefined length burst accesses
bogdanm 82:6473597d706e 558 * are allowed to complete uninterrupted or whether they can be broken by
bogdanm 82:6473597d706e 559 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
bogdanm 82:6473597d706e 560 * mode with 32-bit accesses.
bogdanm 82:6473597d706e 561 */
bogdanm 82:6473597d706e 562 typedef union _hw_axbs_mgpcr0
bogdanm 82:6473597d706e 563 {
bogdanm 82:6473597d706e 564 uint32_t U;
bogdanm 82:6473597d706e 565 struct _hw_axbs_mgpcr0_bitfields
bogdanm 82:6473597d706e 566 {
bogdanm 82:6473597d706e 567 uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
bogdanm 82:6473597d706e 568 uint32_t RESERVED0 : 29; //!< [31:3]
bogdanm 82:6473597d706e 569 } B;
bogdanm 82:6473597d706e 570 } hw_axbs_mgpcr0_t;
bogdanm 82:6473597d706e 571 #endif
bogdanm 82:6473597d706e 572
bogdanm 82:6473597d706e 573 /*!
bogdanm 82:6473597d706e 574 * @name Constants and macros for entire AXBS_MGPCR0 register
bogdanm 82:6473597d706e 575 */
bogdanm 82:6473597d706e 576 //@{
bogdanm 82:6473597d706e 577 #define HW_AXBS_MGPCR0_ADDR (REGS_AXBS_BASE + 0x800U)
bogdanm 82:6473597d706e 578
bogdanm 82:6473597d706e 579 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 580 #define HW_AXBS_MGPCR0 (*(__IO hw_axbs_mgpcr0_t *) HW_AXBS_MGPCR0_ADDR)
bogdanm 82:6473597d706e 581 #define HW_AXBS_MGPCR0_RD() (HW_AXBS_MGPCR0.U)
bogdanm 82:6473597d706e 582 #define HW_AXBS_MGPCR0_WR(v) (HW_AXBS_MGPCR0.U = (v))
bogdanm 82:6473597d706e 583 #define HW_AXBS_MGPCR0_SET(v) (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() | (v)))
bogdanm 82:6473597d706e 584 #define HW_AXBS_MGPCR0_CLR(v) (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() & ~(v)))
bogdanm 82:6473597d706e 585 #define HW_AXBS_MGPCR0_TOG(v) (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() ^ (v)))
bogdanm 82:6473597d706e 586 #endif
bogdanm 82:6473597d706e 587 //@}
bogdanm 82:6473597d706e 588
bogdanm 82:6473597d706e 589 /*
bogdanm 82:6473597d706e 590 * Constants & macros for individual AXBS_MGPCR0 bitfields
bogdanm 82:6473597d706e 591 */
bogdanm 82:6473597d706e 592
bogdanm 82:6473597d706e 593 /*!
bogdanm 82:6473597d706e 594 * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
bogdanm 82:6473597d706e 595 *
bogdanm 82:6473597d706e 596 * Determines whether, and when, the crossbar switch arbitrates away the slave
bogdanm 82:6473597d706e 597 * port the master owns when the master is performing undefined length burst
bogdanm 82:6473597d706e 598 * accesses.
bogdanm 82:6473597d706e 599 *
bogdanm 82:6473597d706e 600 * Values:
bogdanm 82:6473597d706e 601 * - 000 - No arbitration is allowed during an undefined length burst
bogdanm 82:6473597d706e 602 * - 001 - Arbitration is allowed at any time during an undefined length burst
bogdanm 82:6473597d706e 603 * - 010 - Arbitration is allowed after four beats of an undefined length burst
bogdanm 82:6473597d706e 604 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
bogdanm 82:6473597d706e 605 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
bogdanm 82:6473597d706e 606 * - 101 - Reserved
bogdanm 82:6473597d706e 607 * - 110 - Reserved
bogdanm 82:6473597d706e 608 * - 111 - Reserved
bogdanm 82:6473597d706e 609 */
bogdanm 82:6473597d706e 610 //@{
bogdanm 82:6473597d706e 611 #define BP_AXBS_MGPCR0_AULB (0U) //!< Bit position for AXBS_MGPCR0_AULB.
bogdanm 82:6473597d706e 612 #define BM_AXBS_MGPCR0_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR0_AULB.
bogdanm 82:6473597d706e 613 #define BS_AXBS_MGPCR0_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR0_AULB.
bogdanm 82:6473597d706e 614
bogdanm 82:6473597d706e 615 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 616 //! @brief Read current value of the AXBS_MGPCR0_AULB field.
bogdanm 82:6473597d706e 617 #define BR_AXBS_MGPCR0_AULB (HW_AXBS_MGPCR0.B.AULB)
bogdanm 82:6473597d706e 618 #endif
bogdanm 82:6473597d706e 619
bogdanm 82:6473597d706e 620 //! @brief Format value for bitfield AXBS_MGPCR0_AULB.
bogdanm 82:6473597d706e 621 #define BF_AXBS_MGPCR0_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR0_AULB), uint32_t) & BM_AXBS_MGPCR0_AULB)
bogdanm 82:6473597d706e 622
bogdanm 82:6473597d706e 623 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 624 //! @brief Set the AULB field to a new value.
bogdanm 82:6473597d706e 625 #define BW_AXBS_MGPCR0_AULB(v) (HW_AXBS_MGPCR0_WR((HW_AXBS_MGPCR0_RD() & ~BM_AXBS_MGPCR0_AULB) | BF_AXBS_MGPCR0_AULB(v)))
bogdanm 82:6473597d706e 626 #endif
bogdanm 82:6473597d706e 627 //@}
bogdanm 82:6473597d706e 628
bogdanm 82:6473597d706e 629 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 630 // HW_AXBS_MGPCR1 - Master General Purpose Control Register
bogdanm 82:6473597d706e 631 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 632
bogdanm 82:6473597d706e 633 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 634 /*!
bogdanm 82:6473597d706e 635 * @brief HW_AXBS_MGPCR1 - Master General Purpose Control Register (RW)
bogdanm 82:6473597d706e 636 *
bogdanm 82:6473597d706e 637 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 638 *
bogdanm 82:6473597d706e 639 * The MGPCR controls only whether the master's undefined length burst accesses
bogdanm 82:6473597d706e 640 * are allowed to complete uninterrupted or whether they can be broken by
bogdanm 82:6473597d706e 641 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
bogdanm 82:6473597d706e 642 * mode with 32-bit accesses.
bogdanm 82:6473597d706e 643 */
bogdanm 82:6473597d706e 644 typedef union _hw_axbs_mgpcr1
bogdanm 82:6473597d706e 645 {
bogdanm 82:6473597d706e 646 uint32_t U;
bogdanm 82:6473597d706e 647 struct _hw_axbs_mgpcr1_bitfields
bogdanm 82:6473597d706e 648 {
bogdanm 82:6473597d706e 649 uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
bogdanm 82:6473597d706e 650 uint32_t RESERVED0 : 29; //!< [31:3]
bogdanm 82:6473597d706e 651 } B;
bogdanm 82:6473597d706e 652 } hw_axbs_mgpcr1_t;
bogdanm 82:6473597d706e 653 #endif
bogdanm 82:6473597d706e 654
bogdanm 82:6473597d706e 655 /*!
bogdanm 82:6473597d706e 656 * @name Constants and macros for entire AXBS_MGPCR1 register
bogdanm 82:6473597d706e 657 */
bogdanm 82:6473597d706e 658 //@{
bogdanm 82:6473597d706e 659 #define HW_AXBS_MGPCR1_ADDR (REGS_AXBS_BASE + 0x900U)
bogdanm 82:6473597d706e 660
bogdanm 82:6473597d706e 661 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 662 #define HW_AXBS_MGPCR1 (*(__IO hw_axbs_mgpcr1_t *) HW_AXBS_MGPCR1_ADDR)
bogdanm 82:6473597d706e 663 #define HW_AXBS_MGPCR1_RD() (HW_AXBS_MGPCR1.U)
bogdanm 82:6473597d706e 664 #define HW_AXBS_MGPCR1_WR(v) (HW_AXBS_MGPCR1.U = (v))
bogdanm 82:6473597d706e 665 #define HW_AXBS_MGPCR1_SET(v) (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() | (v)))
bogdanm 82:6473597d706e 666 #define HW_AXBS_MGPCR1_CLR(v) (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() & ~(v)))
bogdanm 82:6473597d706e 667 #define HW_AXBS_MGPCR1_TOG(v) (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() ^ (v)))
bogdanm 82:6473597d706e 668 #endif
bogdanm 82:6473597d706e 669 //@}
bogdanm 82:6473597d706e 670
bogdanm 82:6473597d706e 671 /*
bogdanm 82:6473597d706e 672 * Constants & macros for individual AXBS_MGPCR1 bitfields
bogdanm 82:6473597d706e 673 */
bogdanm 82:6473597d706e 674
bogdanm 82:6473597d706e 675 /*!
bogdanm 82:6473597d706e 676 * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
bogdanm 82:6473597d706e 677 *
bogdanm 82:6473597d706e 678 * Determines whether, and when, the crossbar switch arbitrates away the slave
bogdanm 82:6473597d706e 679 * port the master owns when the master is performing undefined length burst
bogdanm 82:6473597d706e 680 * accesses.
bogdanm 82:6473597d706e 681 *
bogdanm 82:6473597d706e 682 * Values:
bogdanm 82:6473597d706e 683 * - 000 - No arbitration is allowed during an undefined length burst
bogdanm 82:6473597d706e 684 * - 001 - Arbitration is allowed at any time during an undefined length burst
bogdanm 82:6473597d706e 685 * - 010 - Arbitration is allowed after four beats of an undefined length burst
bogdanm 82:6473597d706e 686 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
bogdanm 82:6473597d706e 687 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
bogdanm 82:6473597d706e 688 * - 101 - Reserved
bogdanm 82:6473597d706e 689 * - 110 - Reserved
bogdanm 82:6473597d706e 690 * - 111 - Reserved
bogdanm 82:6473597d706e 691 */
bogdanm 82:6473597d706e 692 //@{
bogdanm 82:6473597d706e 693 #define BP_AXBS_MGPCR1_AULB (0U) //!< Bit position for AXBS_MGPCR1_AULB.
bogdanm 82:6473597d706e 694 #define BM_AXBS_MGPCR1_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR1_AULB.
bogdanm 82:6473597d706e 695 #define BS_AXBS_MGPCR1_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR1_AULB.
bogdanm 82:6473597d706e 696
bogdanm 82:6473597d706e 697 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 698 //! @brief Read current value of the AXBS_MGPCR1_AULB field.
bogdanm 82:6473597d706e 699 #define BR_AXBS_MGPCR1_AULB (HW_AXBS_MGPCR1.B.AULB)
bogdanm 82:6473597d706e 700 #endif
bogdanm 82:6473597d706e 701
bogdanm 82:6473597d706e 702 //! @brief Format value for bitfield AXBS_MGPCR1_AULB.
bogdanm 82:6473597d706e 703 #define BF_AXBS_MGPCR1_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR1_AULB), uint32_t) & BM_AXBS_MGPCR1_AULB)
bogdanm 82:6473597d706e 704
bogdanm 82:6473597d706e 705 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 706 //! @brief Set the AULB field to a new value.
bogdanm 82:6473597d706e 707 #define BW_AXBS_MGPCR1_AULB(v) (HW_AXBS_MGPCR1_WR((HW_AXBS_MGPCR1_RD() & ~BM_AXBS_MGPCR1_AULB) | BF_AXBS_MGPCR1_AULB(v)))
bogdanm 82:6473597d706e 708 #endif
bogdanm 82:6473597d706e 709 //@}
bogdanm 82:6473597d706e 710
bogdanm 82:6473597d706e 711 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 712 // HW_AXBS_MGPCR2 - Master General Purpose Control Register
bogdanm 82:6473597d706e 713 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 714
bogdanm 82:6473597d706e 715 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 716 /*!
bogdanm 82:6473597d706e 717 * @brief HW_AXBS_MGPCR2 - Master General Purpose Control Register (RW)
bogdanm 82:6473597d706e 718 *
bogdanm 82:6473597d706e 719 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 720 *
bogdanm 82:6473597d706e 721 * The MGPCR controls only whether the master's undefined length burst accesses
bogdanm 82:6473597d706e 722 * are allowed to complete uninterrupted or whether they can be broken by
bogdanm 82:6473597d706e 723 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
bogdanm 82:6473597d706e 724 * mode with 32-bit accesses.
bogdanm 82:6473597d706e 725 */
bogdanm 82:6473597d706e 726 typedef union _hw_axbs_mgpcr2
bogdanm 82:6473597d706e 727 {
bogdanm 82:6473597d706e 728 uint32_t U;
bogdanm 82:6473597d706e 729 struct _hw_axbs_mgpcr2_bitfields
bogdanm 82:6473597d706e 730 {
bogdanm 82:6473597d706e 731 uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
bogdanm 82:6473597d706e 732 uint32_t RESERVED0 : 29; //!< [31:3]
bogdanm 82:6473597d706e 733 } B;
bogdanm 82:6473597d706e 734 } hw_axbs_mgpcr2_t;
bogdanm 82:6473597d706e 735 #endif
bogdanm 82:6473597d706e 736
bogdanm 82:6473597d706e 737 /*!
bogdanm 82:6473597d706e 738 * @name Constants and macros for entire AXBS_MGPCR2 register
bogdanm 82:6473597d706e 739 */
bogdanm 82:6473597d706e 740 //@{
bogdanm 82:6473597d706e 741 #define HW_AXBS_MGPCR2_ADDR (REGS_AXBS_BASE + 0xA00U)
bogdanm 82:6473597d706e 742
bogdanm 82:6473597d706e 743 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 744 #define HW_AXBS_MGPCR2 (*(__IO hw_axbs_mgpcr2_t *) HW_AXBS_MGPCR2_ADDR)
bogdanm 82:6473597d706e 745 #define HW_AXBS_MGPCR2_RD() (HW_AXBS_MGPCR2.U)
bogdanm 82:6473597d706e 746 #define HW_AXBS_MGPCR2_WR(v) (HW_AXBS_MGPCR2.U = (v))
bogdanm 82:6473597d706e 747 #define HW_AXBS_MGPCR2_SET(v) (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() | (v)))
bogdanm 82:6473597d706e 748 #define HW_AXBS_MGPCR2_CLR(v) (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() & ~(v)))
bogdanm 82:6473597d706e 749 #define HW_AXBS_MGPCR2_TOG(v) (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() ^ (v)))
bogdanm 82:6473597d706e 750 #endif
bogdanm 82:6473597d706e 751 //@}
bogdanm 82:6473597d706e 752
bogdanm 82:6473597d706e 753 /*
bogdanm 82:6473597d706e 754 * Constants & macros for individual AXBS_MGPCR2 bitfields
bogdanm 82:6473597d706e 755 */
bogdanm 82:6473597d706e 756
bogdanm 82:6473597d706e 757 /*!
bogdanm 82:6473597d706e 758 * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
bogdanm 82:6473597d706e 759 *
bogdanm 82:6473597d706e 760 * Determines whether, and when, the crossbar switch arbitrates away the slave
bogdanm 82:6473597d706e 761 * port the master owns when the master is performing undefined length burst
bogdanm 82:6473597d706e 762 * accesses.
bogdanm 82:6473597d706e 763 *
bogdanm 82:6473597d706e 764 * Values:
bogdanm 82:6473597d706e 765 * - 000 - No arbitration is allowed during an undefined length burst
bogdanm 82:6473597d706e 766 * - 001 - Arbitration is allowed at any time during an undefined length burst
bogdanm 82:6473597d706e 767 * - 010 - Arbitration is allowed after four beats of an undefined length burst
bogdanm 82:6473597d706e 768 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
bogdanm 82:6473597d706e 769 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
bogdanm 82:6473597d706e 770 * - 101 - Reserved
bogdanm 82:6473597d706e 771 * - 110 - Reserved
bogdanm 82:6473597d706e 772 * - 111 - Reserved
bogdanm 82:6473597d706e 773 */
bogdanm 82:6473597d706e 774 //@{
bogdanm 82:6473597d706e 775 #define BP_AXBS_MGPCR2_AULB (0U) //!< Bit position for AXBS_MGPCR2_AULB.
bogdanm 82:6473597d706e 776 #define BM_AXBS_MGPCR2_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR2_AULB.
bogdanm 82:6473597d706e 777 #define BS_AXBS_MGPCR2_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR2_AULB.
bogdanm 82:6473597d706e 778
bogdanm 82:6473597d706e 779 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 780 //! @brief Read current value of the AXBS_MGPCR2_AULB field.
bogdanm 82:6473597d706e 781 #define BR_AXBS_MGPCR2_AULB (HW_AXBS_MGPCR2.B.AULB)
bogdanm 82:6473597d706e 782 #endif
bogdanm 82:6473597d706e 783
bogdanm 82:6473597d706e 784 //! @brief Format value for bitfield AXBS_MGPCR2_AULB.
bogdanm 82:6473597d706e 785 #define BF_AXBS_MGPCR2_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR2_AULB), uint32_t) & BM_AXBS_MGPCR2_AULB)
bogdanm 82:6473597d706e 786
bogdanm 82:6473597d706e 787 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 788 //! @brief Set the AULB field to a new value.
bogdanm 82:6473597d706e 789 #define BW_AXBS_MGPCR2_AULB(v) (HW_AXBS_MGPCR2_WR((HW_AXBS_MGPCR2_RD() & ~BM_AXBS_MGPCR2_AULB) | BF_AXBS_MGPCR2_AULB(v)))
bogdanm 82:6473597d706e 790 #endif
bogdanm 82:6473597d706e 791 //@}
bogdanm 82:6473597d706e 792
bogdanm 82:6473597d706e 793 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 794 // HW_AXBS_MGPCR3 - Master General Purpose Control Register
bogdanm 82:6473597d706e 795 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 796
bogdanm 82:6473597d706e 797 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 798 /*!
bogdanm 82:6473597d706e 799 * @brief HW_AXBS_MGPCR3 - Master General Purpose Control Register (RW)
bogdanm 82:6473597d706e 800 *
bogdanm 82:6473597d706e 801 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 802 *
bogdanm 82:6473597d706e 803 * The MGPCR controls only whether the master's undefined length burst accesses
bogdanm 82:6473597d706e 804 * are allowed to complete uninterrupted or whether they can be broken by
bogdanm 82:6473597d706e 805 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
bogdanm 82:6473597d706e 806 * mode with 32-bit accesses.
bogdanm 82:6473597d706e 807 */
bogdanm 82:6473597d706e 808 typedef union _hw_axbs_mgpcr3
bogdanm 82:6473597d706e 809 {
bogdanm 82:6473597d706e 810 uint32_t U;
bogdanm 82:6473597d706e 811 struct _hw_axbs_mgpcr3_bitfields
bogdanm 82:6473597d706e 812 {
bogdanm 82:6473597d706e 813 uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
bogdanm 82:6473597d706e 814 uint32_t RESERVED0 : 29; //!< [31:3]
bogdanm 82:6473597d706e 815 } B;
bogdanm 82:6473597d706e 816 } hw_axbs_mgpcr3_t;
bogdanm 82:6473597d706e 817 #endif
bogdanm 82:6473597d706e 818
bogdanm 82:6473597d706e 819 /*!
bogdanm 82:6473597d706e 820 * @name Constants and macros for entire AXBS_MGPCR3 register
bogdanm 82:6473597d706e 821 */
bogdanm 82:6473597d706e 822 //@{
bogdanm 82:6473597d706e 823 #define HW_AXBS_MGPCR3_ADDR (REGS_AXBS_BASE + 0xB00U)
bogdanm 82:6473597d706e 824
bogdanm 82:6473597d706e 825 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 826 #define HW_AXBS_MGPCR3 (*(__IO hw_axbs_mgpcr3_t *) HW_AXBS_MGPCR3_ADDR)
bogdanm 82:6473597d706e 827 #define HW_AXBS_MGPCR3_RD() (HW_AXBS_MGPCR3.U)
bogdanm 82:6473597d706e 828 #define HW_AXBS_MGPCR3_WR(v) (HW_AXBS_MGPCR3.U = (v))
bogdanm 82:6473597d706e 829 #define HW_AXBS_MGPCR3_SET(v) (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() | (v)))
bogdanm 82:6473597d706e 830 #define HW_AXBS_MGPCR3_CLR(v) (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() & ~(v)))
bogdanm 82:6473597d706e 831 #define HW_AXBS_MGPCR3_TOG(v) (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() ^ (v)))
bogdanm 82:6473597d706e 832 #endif
bogdanm 82:6473597d706e 833 //@}
bogdanm 82:6473597d706e 834
bogdanm 82:6473597d706e 835 /*
bogdanm 82:6473597d706e 836 * Constants & macros for individual AXBS_MGPCR3 bitfields
bogdanm 82:6473597d706e 837 */
bogdanm 82:6473597d706e 838
bogdanm 82:6473597d706e 839 /*!
bogdanm 82:6473597d706e 840 * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
bogdanm 82:6473597d706e 841 *
bogdanm 82:6473597d706e 842 * Determines whether, and when, the crossbar switch arbitrates away the slave
bogdanm 82:6473597d706e 843 * port the master owns when the master is performing undefined length burst
bogdanm 82:6473597d706e 844 * accesses.
bogdanm 82:6473597d706e 845 *
bogdanm 82:6473597d706e 846 * Values:
bogdanm 82:6473597d706e 847 * - 000 - No arbitration is allowed during an undefined length burst
bogdanm 82:6473597d706e 848 * - 001 - Arbitration is allowed at any time during an undefined length burst
bogdanm 82:6473597d706e 849 * - 010 - Arbitration is allowed after four beats of an undefined length burst
bogdanm 82:6473597d706e 850 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
bogdanm 82:6473597d706e 851 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
bogdanm 82:6473597d706e 852 * - 101 - Reserved
bogdanm 82:6473597d706e 853 * - 110 - Reserved
bogdanm 82:6473597d706e 854 * - 111 - Reserved
bogdanm 82:6473597d706e 855 */
bogdanm 82:6473597d706e 856 //@{
bogdanm 82:6473597d706e 857 #define BP_AXBS_MGPCR3_AULB (0U) //!< Bit position for AXBS_MGPCR3_AULB.
bogdanm 82:6473597d706e 858 #define BM_AXBS_MGPCR3_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR3_AULB.
bogdanm 82:6473597d706e 859 #define BS_AXBS_MGPCR3_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR3_AULB.
bogdanm 82:6473597d706e 860
bogdanm 82:6473597d706e 861 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 862 //! @brief Read current value of the AXBS_MGPCR3_AULB field.
bogdanm 82:6473597d706e 863 #define BR_AXBS_MGPCR3_AULB (HW_AXBS_MGPCR3.B.AULB)
bogdanm 82:6473597d706e 864 #endif
bogdanm 82:6473597d706e 865
bogdanm 82:6473597d706e 866 //! @brief Format value for bitfield AXBS_MGPCR3_AULB.
bogdanm 82:6473597d706e 867 #define BF_AXBS_MGPCR3_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR3_AULB), uint32_t) & BM_AXBS_MGPCR3_AULB)
bogdanm 82:6473597d706e 868
bogdanm 82:6473597d706e 869 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 870 //! @brief Set the AULB field to a new value.
bogdanm 82:6473597d706e 871 #define BW_AXBS_MGPCR3_AULB(v) (HW_AXBS_MGPCR3_WR((HW_AXBS_MGPCR3_RD() & ~BM_AXBS_MGPCR3_AULB) | BF_AXBS_MGPCR3_AULB(v)))
bogdanm 82:6473597d706e 872 #endif
bogdanm 82:6473597d706e 873 //@}
bogdanm 82:6473597d706e 874
bogdanm 82:6473597d706e 875 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 876 // HW_AXBS_MGPCR4 - Master General Purpose Control Register
bogdanm 82:6473597d706e 877 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 878
bogdanm 82:6473597d706e 879 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 880 /*!
bogdanm 82:6473597d706e 881 * @brief HW_AXBS_MGPCR4 - Master General Purpose Control Register (RW)
bogdanm 82:6473597d706e 882 *
bogdanm 82:6473597d706e 883 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 884 *
bogdanm 82:6473597d706e 885 * The MGPCR controls only whether the master's undefined length burst accesses
bogdanm 82:6473597d706e 886 * are allowed to complete uninterrupted or whether they can be broken by
bogdanm 82:6473597d706e 887 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
bogdanm 82:6473597d706e 888 * mode with 32-bit accesses.
bogdanm 82:6473597d706e 889 */
bogdanm 82:6473597d706e 890 typedef union _hw_axbs_mgpcr4
bogdanm 82:6473597d706e 891 {
bogdanm 82:6473597d706e 892 uint32_t U;
bogdanm 82:6473597d706e 893 struct _hw_axbs_mgpcr4_bitfields
bogdanm 82:6473597d706e 894 {
bogdanm 82:6473597d706e 895 uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
bogdanm 82:6473597d706e 896 uint32_t RESERVED0 : 29; //!< [31:3]
bogdanm 82:6473597d706e 897 } B;
bogdanm 82:6473597d706e 898 } hw_axbs_mgpcr4_t;
bogdanm 82:6473597d706e 899 #endif
bogdanm 82:6473597d706e 900
bogdanm 82:6473597d706e 901 /*!
bogdanm 82:6473597d706e 902 * @name Constants and macros for entire AXBS_MGPCR4 register
bogdanm 82:6473597d706e 903 */
bogdanm 82:6473597d706e 904 //@{
bogdanm 82:6473597d706e 905 #define HW_AXBS_MGPCR4_ADDR (REGS_AXBS_BASE + 0xC00U)
bogdanm 82:6473597d706e 906
bogdanm 82:6473597d706e 907 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 908 #define HW_AXBS_MGPCR4 (*(__IO hw_axbs_mgpcr4_t *) HW_AXBS_MGPCR4_ADDR)
bogdanm 82:6473597d706e 909 #define HW_AXBS_MGPCR4_RD() (HW_AXBS_MGPCR4.U)
bogdanm 82:6473597d706e 910 #define HW_AXBS_MGPCR4_WR(v) (HW_AXBS_MGPCR4.U = (v))
bogdanm 82:6473597d706e 911 #define HW_AXBS_MGPCR4_SET(v) (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() | (v)))
bogdanm 82:6473597d706e 912 #define HW_AXBS_MGPCR4_CLR(v) (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() & ~(v)))
bogdanm 82:6473597d706e 913 #define HW_AXBS_MGPCR4_TOG(v) (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() ^ (v)))
bogdanm 82:6473597d706e 914 #endif
bogdanm 82:6473597d706e 915 //@}
bogdanm 82:6473597d706e 916
bogdanm 82:6473597d706e 917 /*
bogdanm 82:6473597d706e 918 * Constants & macros for individual AXBS_MGPCR4 bitfields
bogdanm 82:6473597d706e 919 */
bogdanm 82:6473597d706e 920
bogdanm 82:6473597d706e 921 /*!
bogdanm 82:6473597d706e 922 * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
bogdanm 82:6473597d706e 923 *
bogdanm 82:6473597d706e 924 * Determines whether, and when, the crossbar switch arbitrates away the slave
bogdanm 82:6473597d706e 925 * port the master owns when the master is performing undefined length burst
bogdanm 82:6473597d706e 926 * accesses.
bogdanm 82:6473597d706e 927 *
bogdanm 82:6473597d706e 928 * Values:
bogdanm 82:6473597d706e 929 * - 000 - No arbitration is allowed during an undefined length burst
bogdanm 82:6473597d706e 930 * - 001 - Arbitration is allowed at any time during an undefined length burst
bogdanm 82:6473597d706e 931 * - 010 - Arbitration is allowed after four beats of an undefined length burst
bogdanm 82:6473597d706e 932 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
bogdanm 82:6473597d706e 933 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
bogdanm 82:6473597d706e 934 * - 101 - Reserved
bogdanm 82:6473597d706e 935 * - 110 - Reserved
bogdanm 82:6473597d706e 936 * - 111 - Reserved
bogdanm 82:6473597d706e 937 */
bogdanm 82:6473597d706e 938 //@{
bogdanm 82:6473597d706e 939 #define BP_AXBS_MGPCR4_AULB (0U) //!< Bit position for AXBS_MGPCR4_AULB.
bogdanm 82:6473597d706e 940 #define BM_AXBS_MGPCR4_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR4_AULB.
bogdanm 82:6473597d706e 941 #define BS_AXBS_MGPCR4_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR4_AULB.
bogdanm 82:6473597d706e 942
bogdanm 82:6473597d706e 943 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 944 //! @brief Read current value of the AXBS_MGPCR4_AULB field.
bogdanm 82:6473597d706e 945 #define BR_AXBS_MGPCR4_AULB (HW_AXBS_MGPCR4.B.AULB)
bogdanm 82:6473597d706e 946 #endif
bogdanm 82:6473597d706e 947
bogdanm 82:6473597d706e 948 //! @brief Format value for bitfield AXBS_MGPCR4_AULB.
bogdanm 82:6473597d706e 949 #define BF_AXBS_MGPCR4_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR4_AULB), uint32_t) & BM_AXBS_MGPCR4_AULB)
bogdanm 82:6473597d706e 950
bogdanm 82:6473597d706e 951 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 952 //! @brief Set the AULB field to a new value.
bogdanm 82:6473597d706e 953 #define BW_AXBS_MGPCR4_AULB(v) (HW_AXBS_MGPCR4_WR((HW_AXBS_MGPCR4_RD() & ~BM_AXBS_MGPCR4_AULB) | BF_AXBS_MGPCR4_AULB(v)))
bogdanm 82:6473597d706e 954 #endif
bogdanm 82:6473597d706e 955 //@}
bogdanm 82:6473597d706e 956
bogdanm 82:6473597d706e 957 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 958 // HW_AXBS_MGPCR5 - Master General Purpose Control Register
bogdanm 82:6473597d706e 959 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 960
bogdanm 82:6473597d706e 961 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 962 /*!
bogdanm 82:6473597d706e 963 * @brief HW_AXBS_MGPCR5 - Master General Purpose Control Register (RW)
bogdanm 82:6473597d706e 964 *
bogdanm 82:6473597d706e 965 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 966 *
bogdanm 82:6473597d706e 967 * The MGPCR controls only whether the master's undefined length burst accesses
bogdanm 82:6473597d706e 968 * are allowed to complete uninterrupted or whether they can be broken by
bogdanm 82:6473597d706e 969 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
bogdanm 82:6473597d706e 970 * mode with 32-bit accesses.
bogdanm 82:6473597d706e 971 */
bogdanm 82:6473597d706e 972 typedef union _hw_axbs_mgpcr5
bogdanm 82:6473597d706e 973 {
bogdanm 82:6473597d706e 974 uint32_t U;
bogdanm 82:6473597d706e 975 struct _hw_axbs_mgpcr5_bitfields
bogdanm 82:6473597d706e 976 {
bogdanm 82:6473597d706e 977 uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
bogdanm 82:6473597d706e 978 uint32_t RESERVED0 : 29; //!< [31:3]
bogdanm 82:6473597d706e 979 } B;
bogdanm 82:6473597d706e 980 } hw_axbs_mgpcr5_t;
bogdanm 82:6473597d706e 981 #endif
bogdanm 82:6473597d706e 982
bogdanm 82:6473597d706e 983 /*!
bogdanm 82:6473597d706e 984 * @name Constants and macros for entire AXBS_MGPCR5 register
bogdanm 82:6473597d706e 985 */
bogdanm 82:6473597d706e 986 //@{
bogdanm 82:6473597d706e 987 #define HW_AXBS_MGPCR5_ADDR (REGS_AXBS_BASE + 0xD00U)
bogdanm 82:6473597d706e 988
bogdanm 82:6473597d706e 989 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 990 #define HW_AXBS_MGPCR5 (*(__IO hw_axbs_mgpcr5_t *) HW_AXBS_MGPCR5_ADDR)
bogdanm 82:6473597d706e 991 #define HW_AXBS_MGPCR5_RD() (HW_AXBS_MGPCR5.U)
bogdanm 82:6473597d706e 992 #define HW_AXBS_MGPCR5_WR(v) (HW_AXBS_MGPCR5.U = (v))
bogdanm 82:6473597d706e 993 #define HW_AXBS_MGPCR5_SET(v) (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() | (v)))
bogdanm 82:6473597d706e 994 #define HW_AXBS_MGPCR5_CLR(v) (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() & ~(v)))
bogdanm 82:6473597d706e 995 #define HW_AXBS_MGPCR5_TOG(v) (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() ^ (v)))
bogdanm 82:6473597d706e 996 #endif
bogdanm 82:6473597d706e 997 //@}
bogdanm 82:6473597d706e 998
bogdanm 82:6473597d706e 999 /*
bogdanm 82:6473597d706e 1000 * Constants & macros for individual AXBS_MGPCR5 bitfields
bogdanm 82:6473597d706e 1001 */
bogdanm 82:6473597d706e 1002
bogdanm 82:6473597d706e 1003 /*!
bogdanm 82:6473597d706e 1004 * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
bogdanm 82:6473597d706e 1005 *
bogdanm 82:6473597d706e 1006 * Determines whether, and when, the crossbar switch arbitrates away the slave
bogdanm 82:6473597d706e 1007 * port the master owns when the master is performing undefined length burst
bogdanm 82:6473597d706e 1008 * accesses.
bogdanm 82:6473597d706e 1009 *
bogdanm 82:6473597d706e 1010 * Values:
bogdanm 82:6473597d706e 1011 * - 000 - No arbitration is allowed during an undefined length burst
bogdanm 82:6473597d706e 1012 * - 001 - Arbitration is allowed at any time during an undefined length burst
bogdanm 82:6473597d706e 1013 * - 010 - Arbitration is allowed after four beats of an undefined length burst
bogdanm 82:6473597d706e 1014 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
bogdanm 82:6473597d706e 1015 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
bogdanm 82:6473597d706e 1016 * - 101 - Reserved
bogdanm 82:6473597d706e 1017 * - 110 - Reserved
bogdanm 82:6473597d706e 1018 * - 111 - Reserved
bogdanm 82:6473597d706e 1019 */
bogdanm 82:6473597d706e 1020 //@{
bogdanm 82:6473597d706e 1021 #define BP_AXBS_MGPCR5_AULB (0U) //!< Bit position for AXBS_MGPCR5_AULB.
bogdanm 82:6473597d706e 1022 #define BM_AXBS_MGPCR5_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR5_AULB.
bogdanm 82:6473597d706e 1023 #define BS_AXBS_MGPCR5_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR5_AULB.
bogdanm 82:6473597d706e 1024
bogdanm 82:6473597d706e 1025 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1026 //! @brief Read current value of the AXBS_MGPCR5_AULB field.
bogdanm 82:6473597d706e 1027 #define BR_AXBS_MGPCR5_AULB (HW_AXBS_MGPCR5.B.AULB)
bogdanm 82:6473597d706e 1028 #endif
bogdanm 82:6473597d706e 1029
bogdanm 82:6473597d706e 1030 //! @brief Format value for bitfield AXBS_MGPCR5_AULB.
bogdanm 82:6473597d706e 1031 #define BF_AXBS_MGPCR5_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR5_AULB), uint32_t) & BM_AXBS_MGPCR5_AULB)
bogdanm 82:6473597d706e 1032
bogdanm 82:6473597d706e 1033 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1034 //! @brief Set the AULB field to a new value.
bogdanm 82:6473597d706e 1035 #define BW_AXBS_MGPCR5_AULB(v) (HW_AXBS_MGPCR5_WR((HW_AXBS_MGPCR5_RD() & ~BM_AXBS_MGPCR5_AULB) | BF_AXBS_MGPCR5_AULB(v)))
bogdanm 82:6473597d706e 1036 #endif
bogdanm 82:6473597d706e 1037 //@}
bogdanm 82:6473597d706e 1038
bogdanm 82:6473597d706e 1039 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1040 // hw_axbs_t - module struct
bogdanm 82:6473597d706e 1041 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1042 /*!
bogdanm 82:6473597d706e 1043 * @brief All AXBS module registers.
bogdanm 82:6473597d706e 1044 */
bogdanm 82:6473597d706e 1045 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1046 #pragma pack(1)
bogdanm 82:6473597d706e 1047 typedef struct _hw_axbs
bogdanm 82:6473597d706e 1048 {
bogdanm 82:6473597d706e 1049 struct {
bogdanm 82:6473597d706e 1050 __IO hw_axbs_prsn_t PRSn; //!< [0x0] Priority Registers Slave
bogdanm 82:6473597d706e 1051 uint8_t _reserved0[12];
bogdanm 82:6473597d706e 1052 __IO hw_axbs_crsn_t CRSn; //!< [0x10] Control Register
bogdanm 82:6473597d706e 1053 uint8_t _reserved1[236];
bogdanm 82:6473597d706e 1054 } SLAVE[5];
bogdanm 82:6473597d706e 1055 uint8_t _reserved0[768];
bogdanm 82:6473597d706e 1056 __IO hw_axbs_mgpcr0_t MGPCR0; //!< [0x800] Master General Purpose Control Register
bogdanm 82:6473597d706e 1057 uint8_t _reserved1[252];
bogdanm 82:6473597d706e 1058 __IO hw_axbs_mgpcr1_t MGPCR1; //!< [0x900] Master General Purpose Control Register
bogdanm 82:6473597d706e 1059 uint8_t _reserved2[252];
bogdanm 82:6473597d706e 1060 __IO hw_axbs_mgpcr2_t MGPCR2; //!< [0xA00] Master General Purpose Control Register
bogdanm 82:6473597d706e 1061 uint8_t _reserved3[252];
bogdanm 82:6473597d706e 1062 __IO hw_axbs_mgpcr3_t MGPCR3; //!< [0xB00] Master General Purpose Control Register
bogdanm 82:6473597d706e 1063 uint8_t _reserved4[252];
bogdanm 82:6473597d706e 1064 __IO hw_axbs_mgpcr4_t MGPCR4; //!< [0xC00] Master General Purpose Control Register
bogdanm 82:6473597d706e 1065 uint8_t _reserved5[252];
bogdanm 82:6473597d706e 1066 __IO hw_axbs_mgpcr5_t MGPCR5; //!< [0xD00] Master General Purpose Control Register
bogdanm 82:6473597d706e 1067 } hw_axbs_t;
bogdanm 82:6473597d706e 1068 #pragma pack()
bogdanm 82:6473597d706e 1069
bogdanm 82:6473597d706e 1070 //! @brief Macro to access all AXBS registers.
bogdanm 82:6473597d706e 1071 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 1072 //! use the '&' operator, like <code>&HW_AXBS</code>.
bogdanm 82:6473597d706e 1073 #define HW_AXBS (*(hw_axbs_t *) REGS_AXBS_BASE)
bogdanm 82:6473597d706e 1074 #endif
bogdanm 82:6473597d706e 1075
bogdanm 82:6473597d706e 1076 #endif // __HW_AXBS_REGISTERS_H__
bogdanm 82:6473597d706e 1077 // v22/130726/0.9
bogdanm 82:6473597d706e 1078 // EOF