p igmon / Mbed 2 deprecated DMA_I2S_Test

Simple Exmple

Dependencies:   ST_401_84MHZ mbed

http://www.geocities.jp/micro_diys/

main.cpp@0:0093b4cc5297, 2014-05-17 (annotated)

Committer:
p_igmon
Date:
Sat May 17 04:58:58 2014 +0000
Revision:
0:0093b4cc5297
Child:
1:530d6fb59a93
???

Who changed what in which revision?

UserRevisionLine numberNew contents of line
p_igmon 0:0093b4cc5297 1 #include "mbed.h"
p_igmon 0:0093b4cc5297 2 #include <math.h>
p_igmon 0:0093b4cc5297 3 #include "cmsis.h"
p_igmon 0:0093b4cc5297 4 #include "pinmap.h"
p_igmon 0:0093b4cc5297 5 #include "PinNames.h"
p_igmon 0:0093b4cc5297 6 #include "error.h"
p_igmon 0:0093b4cc5297 7 #include "stm32f4xx.h"
p_igmon 0:0093b4cc5297 8 #include "stm32f4xx_hal.h"
p_igmon 0:0093b4cc5297 9 #include "stm32f4xx_hal_dma_ex.h"
p_igmon 0:0093b4cc5297 10 #include "stm32f4xx_hal_i2s.h"
p_igmon 0:0093b4cc5297 11 #include "sine_wave.h"
p_igmon 0:0093b4cc5297 12 #include "saw_wave.h"
p_igmon 0:0093b4cc5297 13
p_igmon 0:0093b4cc5297 14 Serial pc(SERIAL_TX, SERIAL_RX);
p_igmon 0:0093b4cc5297 15
p_igmon 0:0093b4cc5297 16 DigitalOut myled(LED1);
p_igmon 0:0093b4cc5297 17 #define I2S_BUFFERSIZE 256
p_igmon 0:0093b4cc5297 18
p_igmon 0:0093b4cc5297 19 uint16_t TxBuff[I2S_BUFFERSIZE];
p_igmon 0:0093b4cc5297 20 uint32_t dmabuffer[2][256];
p_igmon 0:0093b4cc5297 21 //#define STM_PIN_DATA(MODE, FUNC) (((MODE) << 8) | (FUNC))
p_igmon 0:0093b4cc5297 22
p_igmon 0:0093b4cc5297 23 static const PinMap PinMap_I2S_MCK[] = {
p_igmon 0:0093b4cc5297 24 {PC_6, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 0:0093b4cc5297 25 {PC_7, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
p_igmon 0:0093b4cc5297 26 {NC, NC, 0}
p_igmon 0:0093b4cc5297 27 };
p_igmon 0:0093b4cc5297 28
p_igmon 0:0093b4cc5297 29 static const PinMap PinMap_I2S_CK[] = {
p_igmon 0:0093b4cc5297 30 {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 0:0093b4cc5297 31 {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 0:0093b4cc5297 32 {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 0:0093b4cc5297 33 {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
p_igmon 0:0093b4cc5297 34 {NC, NC, 0}
p_igmon 0:0093b4cc5297 35 };
p_igmon 0:0093b4cc5297 36
p_igmon 0:0093b4cc5297 37 static const PinMap PinMap_I2S_WS[] = {
p_igmon 0:0093b4cc5297 38 {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 0:0093b4cc5297 39 {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 0:0093b4cc5297 40 {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
p_igmon 0:0093b4cc5297 41 {NC, NC, 0}
p_igmon 0:0093b4cc5297 42 };
p_igmon 0:0093b4cc5297 43
p_igmon 0:0093b4cc5297 44 static const PinMap PinMap_I2S_SD[] = {
p_igmon 0:0093b4cc5297 45 {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 0:0093b4cc5297 46 {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
p_igmon 0:0093b4cc5297 47 {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
p_igmon 0:0093b4cc5297 48 {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)},
p_igmon 0:0093b4cc5297 49 {NC, NC, 0}
p_igmon 0:0093b4cc5297 50 };
p_igmon 0:0093b4cc5297 51
p_igmon 0:0093b4cc5297 52
p_igmon 0:0093b4cc5297 53 DMA_InitTypeDef DMA_InitType ={
p_igmon 0:0093b4cc5297 54 DMA_CHANNEL_0,
p_igmon 0:0093b4cc5297 55 DMA_MEMORY_TO_PERIPH,
p_igmon 0:0093b4cc5297 56 DMA_PINC_DISABLE,
p_igmon 0:0093b4cc5297 57 DMA_MINC_ENABLE,
p_igmon 0:0093b4cc5297 58 DMA_PDATAALIGN_WORD,
p_igmon 0:0093b4cc5297 59 DMA_MDATAALIGN_WORD,
p_igmon 0:0093b4cc5297 60 DMA_CIRCULAR,
p_igmon 0:0093b4cc5297 61 DMA_PRIORITY_HIGH,
p_igmon 0:0093b4cc5297 62 DMA_FIFOMODE_ENABLE,
p_igmon 0:0093b4cc5297 63 DMA_FIFO_THRESHOLD_HALFFULL,
p_igmon 0:0093b4cc5297 64 DMA_MBURST_SINGLE,
p_igmon 0:0093b4cc5297 65 DMA_PBURST_SINGLE
p_igmon 0:0093b4cc5297 66 };
p_igmon 0:0093b4cc5297 67
p_igmon 0:0093b4cc5297 68 DMA_HandleTypeDef DMA_HandleType ={
p_igmon 0:0093b4cc5297 69 DMA1_Stream4,
p_igmon 0:0093b4cc5297 70 DMA_InitType,
p_igmon 0:0093b4cc5297 71 HAL_UNLOCKED,
p_igmon 0:0093b4cc5297 72 HAL_DMA_STATE_RESET,
p_igmon 0:0093b4cc5297 73 NULL,
p_igmon 0:0093b4cc5297 74 NULL,
p_igmon 0:0093b4cc5297 75 NULL,
p_igmon 0:0093b4cc5297 76 NULL,
p_igmon 0:0093b4cc5297 77 NULL,
p_igmon 0:0093b4cc5297 78 NULL
p_igmon 0:0093b4cc5297 79 };
p_igmon 0:0093b4cc5297 80
p_igmon 0:0093b4cc5297 81 I2S_InitTypeDef my_I2S_InitType ={
p_igmon 0:0093b4cc5297 82 I2S_MODE_MASTER_TX,
p_igmon 0:0093b4cc5297 83 I2S_STANDARD_MSB,
p_igmon 0:0093b4cc5297 84 I2S_DATAFORMAT_16B,
p_igmon 0:0093b4cc5297 85 I2S_MCLKOUTPUT_ENABLE,
p_igmon 0:0093b4cc5297 86 I2S_AUDIOFREQ_44K,
p_igmon 0:0093b4cc5297 87 I2S_CPOL_LOW,
p_igmon 0:0093b4cc5297 88 I2S_CLOCK_PLL,
p_igmon 0:0093b4cc5297 89 I2S_FULLDUPLEXMODE_DISABLE
p_igmon 0:0093b4cc5297 90 };
p_igmon 0:0093b4cc5297 91
p_igmon 0:0093b4cc5297 92 HAL_I2S_StateTypeDef my_I2S_StateTypeDef={
p_igmon 0:0093b4cc5297 93 HAL_I2S_STATE_RESET
p_igmon 0:0093b4cc5297 94 };
p_igmon 0:0093b4cc5297 95
p_igmon 0:0093b4cc5297 96 HAL_I2S_ErrorTypeDef my_I2S_ErorTypeDef={
p_igmon 0:0093b4cc5297 97 HAL_I2S_ERROR_NONE
p_igmon 0:0093b4cc5297 98 };
p_igmon 0:0093b4cc5297 99
p_igmon 0:0093b4cc5297 100 I2S_HandleTypeDef my_I2S_HandleTypeDef = {
p_igmon 0:0093b4cc5297 101 SPI2,
p_igmon 0:0093b4cc5297 102 my_I2S_InitType,
p_igmon 0:0093b4cc5297 103 &TxBuff[0],
p_igmon 0:0093b4cc5297 104 I2S_BUFFERSIZE,
p_igmon 0:0093b4cc5297 105 NULL,
p_igmon 0:0093b4cc5297 106 NULL,
p_igmon 0:0093b4cc5297 107 NULL,
p_igmon 0:0093b4cc5297 108 NULL,
p_igmon 0:0093b4cc5297 109 &DMA_HandleType,//&my_DMA_HamdleType,
p_igmon 0:0093b4cc5297 110 NULL,
p_igmon 0:0093b4cc5297 111 HAL_UNLOCKED,
p_igmon 0:0093b4cc5297 112 my_I2S_StateTypeDef,
p_igmon 0:0093b4cc5297 113 my_I2S_ErorTypeDef
p_igmon 0:0093b4cc5297 114 };
p_igmon 0:0093b4cc5297 115
p_igmon 0:0093b4cc5297 116 void init_dmabuffer(void){
p_igmon 0:0093b4cc5297 117 uint32_t temp;
p_igmon 0:0093b4cc5297 118 for (int i =0;i<256;i++){
p_igmon 0:0093b4cc5297 119 temp = (uint32_t)((saw_wave[i]<<16) | sine_wave[i]);
p_igmon 0:0093b4cc5297 120 dmabuffer[0][i] = temp;
p_igmon 0:0093b4cc5297 121 dmabuffer[1][i] = temp;
p_igmon 0:0093b4cc5297 122 }
p_igmon 0:0093b4cc5297 123 }
p_igmon 0:0093b4cc5297 124
p_igmon 0:0093b4cc5297 125 int main() {
p_igmon 0:0093b4cc5297 126 pc.printf("Hello World !\n");
p_igmon 0:0093b4cc5297 127 init_dmabuffer();
p_igmon 0:0093b4cc5297 128 /// I2S_init();
p_igmon 0:0093b4cc5297 129 HAL_I2S_Init(&my_I2S_HandleTypeDef);
p_igmon 0:0093b4cc5297 130 // Configure the I2S pins
p_igmon 0:0093b4cc5297 131 pinmap_pinout(PC_6, PinMap_MCK);
p_igmon 0:0093b4cc5297 132 pinmap_pinout(PB_10, PinMap_CK);
p_igmon 0:0093b4cc5297 133 pinmap_pinout(PB_12, PinMap_WS);
p_igmon 0:0093b4cc5297 134 pinmap_pinout(PC_3, PinMap_SD);
p_igmon 0:0093b4cc5297 135 pin_mode(PC_6, PullUp);
p_igmon 0:0093b4cc5297 136 pin_mode(PB_10, PullUp);
p_igmon 0:0093b4cc5297 137 pin_mode(PB_12, PullUp);
p_igmon 0:0093b4cc5297 138 pin_mode(PC_3, PullUp);
p_igmon 0:0093b4cc5297 139
p_igmon 0:0093b4cc5297 140 // HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
p_igmon 0:0093b4cc5297 141 // HAL_I2S_IRQHandler(&my_I2S_HandleType);
p_igmon 0:0093b4cc5297 142 /// HAL_I2S_Transmit_DMA(&my_I2S_HandleTypeDef, &TxBuff[0], I2S_BUFFERSIZE);
p_igmon 0:0093b4cc5297 143
p_igmon 0:0093b4cc5297 144 HAL_DMA_Init(&DMA_HandleType);
p_igmon 0:0093b4cc5297 145 HAL_DMAEx_MultiBufferStart_IT(&DMA_HandleType ,(uint32_t)&dmabuffer[0][0] ,SPI2->DR ,(uint32_t)&dmabuffer[1][0] ,256);
p_igmon 0:0093b4cc5297 146 //HAL_DMA_IRQHandler(&my_DMA_HamdleTypeDef);
p_igmon 0:0093b4cc5297 147 //HAL_DMA_Start_IT(&my_DMA_HamdleTypeDef,NULL,NULL,256);
p_igmon 0:0093b4cc5297 148
p_igmon 0:0093b4cc5297 149 while(1) {
p_igmon 0:0093b4cc5297 150 myled = !myled;
p_igmon 0:0093b4cc5297 151 }
p_igmon 0:0093b4cc5297 152 }
p_igmon 0:0093b4cc5297 153