Suga koubou / Mbed 2 deprecated XTouch-djay-bridge

X-TOUCH to djay bridge

Dependencies:   mbed mbed-rtos FATFileSystem

USBHost/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c@1:0dac72ab5910, 2019-06-05 (annotated)

Committer:
okini3939
Date:
Wed Jun 05 04:54:37 2019 +0000
Revision:
1:0dac72ab5910
sample

Who changed what in which revision?

UserRevisionLine numberNew contents of line
okini3939 1:0dac72ab5910 1 /*******************************************************************************
okini3939 1:0dac72ab5910 2 * DISCLAIMER
okini3939 1:0dac72ab5910 3 * This software is supplied by Renesas Electronics Corporation and is only
okini3939 1:0dac72ab5910 4 * intended for use with Renesas products. No other uses are authorized. This
okini3939 1:0dac72ab5910 5 * software is owned by Renesas Electronics Corporation and is protected under
okini3939 1:0dac72ab5910 6 * all applicable laws, including copyright laws.
okini3939 1:0dac72ab5910 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
okini3939 1:0dac72ab5910 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
okini3939 1:0dac72ab5910 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
okini3939 1:0dac72ab5910 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
okini3939 1:0dac72ab5910 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
okini3939 1:0dac72ab5910 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
okini3939 1:0dac72ab5910 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
okini3939 1:0dac72ab5910 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
okini3939 1:0dac72ab5910 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
okini3939 1:0dac72ab5910 16 * Renesas reserves the right, without notice, to make changes to this software
okini3939 1:0dac72ab5910 17 * and to discontinue the availability of this software. By using this software,
okini3939 1:0dac72ab5910 18 * you agree to the additional terms and conditions found by accessing the
okini3939 1:0dac72ab5910 19 * following link:
okini3939 1:0dac72ab5910 20 * http://www.renesas.com/disclaimer
okini3939 1:0dac72ab5910 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
okini3939 1:0dac72ab5910 22 *******************************************************************************/
okini3939 1:0dac72ab5910 23 /*******************************************************************************
okini3939 1:0dac72ab5910 24 * File Name : usb0_host_dmacdrv.c
okini3939 1:0dac72ab5910 25 * $Rev: 1116 $
okini3939 1:0dac72ab5910 26 * $Date:: 2014-07-09 16:29:19 +0900#$
okini3939 1:0dac72ab5910 27 * Device(s) : RZ/A1H
okini3939 1:0dac72ab5910 28 * Tool-Chain :
okini3939 1:0dac72ab5910 29 * OS : None
okini3939 1:0dac72ab5910 30 * H/W Platform :
okini3939 1:0dac72ab5910 31 * Description : RZ/A1H R7S72100 USB Sample Program
okini3939 1:0dac72ab5910 32 * Operation :
okini3939 1:0dac72ab5910 33 * Limitations :
okini3939 1:0dac72ab5910 34 *******************************************************************************/
okini3939 1:0dac72ab5910 35
okini3939 1:0dac72ab5910 36
okini3939 1:0dac72ab5910 37 /*******************************************************************************
okini3939 1:0dac72ab5910 38 Includes <System Includes> , "Project Includes"
okini3939 1:0dac72ab5910 39 *******************************************************************************/
okini3939 1:0dac72ab5910 40 #include "r_typedefs.h"
okini3939 1:0dac72ab5910 41 #include "iodefine.h"
okini3939 1:0dac72ab5910 42 #include "rza_io_regrw.h"
okini3939 1:0dac72ab5910 43 #include "usb0_host_dmacdrv.h"
okini3939 1:0dac72ab5910 44
okini3939 1:0dac72ab5910 45
okini3939 1:0dac72ab5910 46 /*******************************************************************************
okini3939 1:0dac72ab5910 47 Typedef definitions
okini3939 1:0dac72ab5910 48 *******************************************************************************/
okini3939 1:0dac72ab5910 49
okini3939 1:0dac72ab5910 50
okini3939 1:0dac72ab5910 51 /*******************************************************************************
okini3939 1:0dac72ab5910 52 Macro definitions
okini3939 1:0dac72ab5910 53 *******************************************************************************/
okini3939 1:0dac72ab5910 54 #define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
okini3939 1:0dac72ab5910 55
okini3939 1:0dac72ab5910 56 /* ==== Request setting information for on-chip peripheral module ==== */
okini3939 1:0dac72ab5910 57 typedef enum dmac_peri_req_reg_type
okini3939 1:0dac72ab5910 58 {
okini3939 1:0dac72ab5910 59 DMAC_REQ_MID,
okini3939 1:0dac72ab5910 60 DMAC_REQ_RID,
okini3939 1:0dac72ab5910 61 DMAC_REQ_AM,
okini3939 1:0dac72ab5910 62 DMAC_REQ_LVL,
okini3939 1:0dac72ab5910 63 DMAC_REQ_REQD
okini3939 1:0dac72ab5910 64 } dmac_peri_req_reg_type_t;
okini3939 1:0dac72ab5910 65
okini3939 1:0dac72ab5910 66
okini3939 1:0dac72ab5910 67 /*******************************************************************************
okini3939 1:0dac72ab5910 68 Imported global variables and functions (from other files)
okini3939 1:0dac72ab5910 69 *******************************************************************************/
okini3939 1:0dac72ab5910 70
okini3939 1:0dac72ab5910 71
okini3939 1:0dac72ab5910 72 /*******************************************************************************
okini3939 1:0dac72ab5910 73 Exported global variables and functions (to be accessed by other files)
okini3939 1:0dac72ab5910 74 *******************************************************************************/
okini3939 1:0dac72ab5910 75
okini3939 1:0dac72ab5910 76
okini3939 1:0dac72ab5910 77 /*******************************************************************************
okini3939 1:0dac72ab5910 78 Private global variables and functions
okini3939 1:0dac72ab5910 79 *******************************************************************************/
okini3939 1:0dac72ab5910 80 /* ==== Prototype declaration ==== */
okini3939 1:0dac72ab5910 81
okini3939 1:0dac72ab5910 82 /* ==== Global variable ==== */
okini3939 1:0dac72ab5910 83 /* On-chip peripheral module request setting table */
okini3939 1:0dac72ab5910 84 static const uint8_t usb0_host_dmac_peri_req_init_table[8][5] =
okini3939 1:0dac72ab5910 85 {
okini3939 1:0dac72ab5910 86 /* MID,RID, AM,LVL,REQD */
okini3939 1:0dac72ab5910 87 { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
okini3939 1:0dac72ab5910 88 { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
okini3939 1:0dac72ab5910 89 { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
okini3939 1:0dac72ab5910 90 { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
okini3939 1:0dac72ab5910 91 { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
okini3939 1:0dac72ab5910 92 { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
okini3939 1:0dac72ab5910 93 { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
okini3939 1:0dac72ab5910 94 { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
okini3939 1:0dac72ab5910 95 };
okini3939 1:0dac72ab5910 96
okini3939 1:0dac72ab5910 97
okini3939 1:0dac72ab5910 98 /*******************************************************************************
okini3939 1:0dac72ab5910 99 * Function Name: usb0_host_DMAC1_PeriReqInit
okini3939 1:0dac72ab5910 100 * Description : Sets the register mode for DMA mode and the on-chip peripheral
okini3939 1:0dac72ab5910 101 * : module request for transfer request for DMAC channel 1.
okini3939 1:0dac72ab5910 102 * : Executes DMAC initial setting using the DMA information
okini3939 1:0dac72ab5910 103 * : specified by the argument *trans_info and the enabled/disabled
okini3939 1:0dac72ab5910 104 * : continuous transfer specified by the argument continuation.
okini3939 1:0dac72ab5910 105 * : Registers DMAC channel 1 interrupt handler function and sets
okini3939 1:0dac72ab5910 106 * : the interrupt priority level. Then enables transfer completion
okini3939 1:0dac72ab5910 107 * : interrupt.
okini3939 1:0dac72ab5910 108 * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
okini3939 1:0dac72ab5910 109 * : : register
okini3939 1:0dac72ab5910 110 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
okini3939 1:0dac72ab5910 111 * : uint32_t continuation : Set continuous transfer to be valid
okini3939 1:0dac72ab5910 112 * : : after DMA transfer has been completed
okini3939 1:0dac72ab5910 113 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
okini3939 1:0dac72ab5910 114 * : DMAC_SAMPLE_SINGLE : Do not execute continuous
okini3939 1:0dac72ab5910 115 * : : transfer
okini3939 1:0dac72ab5910 116 * : uint32_t request_factor : Factor for on-chip peripheral module
okini3939 1:0dac72ab5910 117 * : : request
okini3939 1:0dac72ab5910 118 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
okini3939 1:0dac72ab5910 119 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
okini3939 1:0dac72ab5910 120 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
okini3939 1:0dac72ab5910 121 * : :
okini3939 1:0dac72ab5910 122 * : uint32_t req_direction : Setting value of CHCFG_n register
okini3939 1:0dac72ab5910 123 * : : REQD bit
okini3939 1:0dac72ab5910 124 * Return Value : none
okini3939 1:0dac72ab5910 125 *******************************************************************************/
okini3939 1:0dac72ab5910 126 void usb0_host_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
okini3939 1:0dac72ab5910 127 uint32_t request_factor, uint32_t req_direction)
okini3939 1:0dac72ab5910 128 {
okini3939 1:0dac72ab5910 129 /* ==== Register mode ==== */
okini3939 1:0dac72ab5910 130 if (DMAC_MODE_REGISTER == dmamode)
okini3939 1:0dac72ab5910 131 {
okini3939 1:0dac72ab5910 132 /* ==== Next0 register set ==== */
okini3939 1:0dac72ab5910 133 DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
okini3939 1:0dac72ab5910 134 DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
okini3939 1:0dac72ab5910 135 DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */
okini3939 1:0dac72ab5910 136
okini3939 1:0dac72ab5910 137 /* DAD : Transfer destination address counting direction */
okini3939 1:0dac72ab5910 138 /* SAD : Transfer source address counting direction */
okini3939 1:0dac72ab5910 139 /* DDS : Transfer destination transfer size */
okini3939 1:0dac72ab5910 140 /* SDS : Transfer source transfer size */
okini3939 1:0dac72ab5910 141 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 142 trans_info->daddr_dir,
okini3939 1:0dac72ab5910 143 DMAC1_CHCFG_n_DAD_SHIFT,
okini3939 1:0dac72ab5910 144 DMAC1_CHCFG_n_DAD);
okini3939 1:0dac72ab5910 145 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 146 trans_info->saddr_dir,
okini3939 1:0dac72ab5910 147 DMAC1_CHCFG_n_SAD_SHIFT,
okini3939 1:0dac72ab5910 148 DMAC1_CHCFG_n_SAD);
okini3939 1:0dac72ab5910 149 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 150 trans_info->dst_size,
okini3939 1:0dac72ab5910 151 DMAC1_CHCFG_n_DDS_SHIFT,
okini3939 1:0dac72ab5910 152 DMAC1_CHCFG_n_DDS);
okini3939 1:0dac72ab5910 153 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 154 trans_info->src_size,
okini3939 1:0dac72ab5910 155 DMAC1_CHCFG_n_SDS_SHIFT,
okini3939 1:0dac72ab5910 156 DMAC1_CHCFG_n_SDS);
okini3939 1:0dac72ab5910 157
okini3939 1:0dac72ab5910 158 /* DMS : Register mode */
okini3939 1:0dac72ab5910 159 /* RSEL : Select Next0 register set */
okini3939 1:0dac72ab5910 160 /* SBE : No discharge of buffer data when aborted */
okini3939 1:0dac72ab5910 161 /* DEM : No DMA interrupt mask */
okini3939 1:0dac72ab5910 162 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 163 0,
okini3939 1:0dac72ab5910 164 DMAC1_CHCFG_n_DMS_SHIFT,
okini3939 1:0dac72ab5910 165 DMAC1_CHCFG_n_DMS);
okini3939 1:0dac72ab5910 166 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 167 0,
okini3939 1:0dac72ab5910 168 DMAC1_CHCFG_n_RSEL_SHIFT,
okini3939 1:0dac72ab5910 169 DMAC1_CHCFG_n_RSEL);
okini3939 1:0dac72ab5910 170 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 171 0,
okini3939 1:0dac72ab5910 172 DMAC1_CHCFG_n_SBE_SHIFT,
okini3939 1:0dac72ab5910 173 DMAC1_CHCFG_n_SBE);
okini3939 1:0dac72ab5910 174 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 175 0,
okini3939 1:0dac72ab5910 176 DMAC1_CHCFG_n_DEM_SHIFT,
okini3939 1:0dac72ab5910 177 DMAC1_CHCFG_n_DEM);
okini3939 1:0dac72ab5910 178
okini3939 1:0dac72ab5910 179 /* ---- Continuous transfer ---- */
okini3939 1:0dac72ab5910 180 if (DMAC_SAMPLE_CONTINUATION == continuation)
okini3939 1:0dac72ab5910 181 {
okini3939 1:0dac72ab5910 182 /* REN : Execute continuous transfer */
okini3939 1:0dac72ab5910 183 /* RSW : Change register set when DMA transfer is completed. */
okini3939 1:0dac72ab5910 184 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 185 1,
okini3939 1:0dac72ab5910 186 DMAC1_CHCFG_n_REN_SHIFT,
okini3939 1:0dac72ab5910 187 DMAC1_CHCFG_n_REN);
okini3939 1:0dac72ab5910 188 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 189 1,
okini3939 1:0dac72ab5910 190 DMAC1_CHCFG_n_RSW_SHIFT,
okini3939 1:0dac72ab5910 191 DMAC1_CHCFG_n_RSW);
okini3939 1:0dac72ab5910 192 }
okini3939 1:0dac72ab5910 193 /* ---- Single transfer ---- */
okini3939 1:0dac72ab5910 194 else
okini3939 1:0dac72ab5910 195 {
okini3939 1:0dac72ab5910 196 /* REN : Do not execute continuous transfer */
okini3939 1:0dac72ab5910 197 /* RSW : Do not change register set when DMA transfer is completed. */
okini3939 1:0dac72ab5910 198 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 199 0,
okini3939 1:0dac72ab5910 200 DMAC1_CHCFG_n_REN_SHIFT,
okini3939 1:0dac72ab5910 201 DMAC1_CHCFG_n_REN);
okini3939 1:0dac72ab5910 202 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 203 0,
okini3939 1:0dac72ab5910 204 DMAC1_CHCFG_n_RSW_SHIFT,
okini3939 1:0dac72ab5910 205 DMAC1_CHCFG_n_RSW);
okini3939 1:0dac72ab5910 206 }
okini3939 1:0dac72ab5910 207
okini3939 1:0dac72ab5910 208 /* TM : Single transfer */
okini3939 1:0dac72ab5910 209 /* SEL : Channel setting */
okini3939 1:0dac72ab5910 210 /* HIEN, LOEN : On-chip peripheral module request */
okini3939 1:0dac72ab5910 211 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 212 0,
okini3939 1:0dac72ab5910 213 DMAC1_CHCFG_n_TM_SHIFT,
okini3939 1:0dac72ab5910 214 DMAC1_CHCFG_n_TM);
okini3939 1:0dac72ab5910 215 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 216 1,
okini3939 1:0dac72ab5910 217 DMAC1_CHCFG_n_SEL_SHIFT,
okini3939 1:0dac72ab5910 218 DMAC1_CHCFG_n_SEL);
okini3939 1:0dac72ab5910 219 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 220 1,
okini3939 1:0dac72ab5910 221 DMAC1_CHCFG_n_HIEN_SHIFT,
okini3939 1:0dac72ab5910 222 DMAC1_CHCFG_n_HIEN);
okini3939 1:0dac72ab5910 223 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 224 0,
okini3939 1:0dac72ab5910 225 DMAC1_CHCFG_n_LOEN_SHIFT,
okini3939 1:0dac72ab5910 226 DMAC1_CHCFG_n_LOEN);
okini3939 1:0dac72ab5910 227
okini3939 1:0dac72ab5910 228 /* ---- Set factor by specified on-chip peripheral module request ---- */
okini3939 1:0dac72ab5910 229 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 230 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
okini3939 1:0dac72ab5910 231 DMAC1_CHCFG_n_AM_SHIFT,
okini3939 1:0dac72ab5910 232 DMAC1_CHCFG_n_AM);
okini3939 1:0dac72ab5910 233 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 234 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
okini3939 1:0dac72ab5910 235 DMAC1_CHCFG_n_LVL_SHIFT,
okini3939 1:0dac72ab5910 236 DMAC1_CHCFG_n_LVL);
okini3939 1:0dac72ab5910 237 if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
okini3939 1:0dac72ab5910 238 {
okini3939 1:0dac72ab5910 239 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 240 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
okini3939 1:0dac72ab5910 241 DMAC1_CHCFG_n_REQD_SHIFT,
okini3939 1:0dac72ab5910 242 DMAC1_CHCFG_n_REQD);
okini3939 1:0dac72ab5910 243 }
okini3939 1:0dac72ab5910 244 else
okini3939 1:0dac72ab5910 245 {
okini3939 1:0dac72ab5910 246 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
okini3939 1:0dac72ab5910 247 req_direction,
okini3939 1:0dac72ab5910 248 DMAC1_CHCFG_n_REQD_SHIFT,
okini3939 1:0dac72ab5910 249 DMAC1_CHCFG_n_REQD);
okini3939 1:0dac72ab5910 250 }
okini3939 1:0dac72ab5910 251 RZA_IO_RegWrite_32(&DMAC01.DMARS,
okini3939 1:0dac72ab5910 252 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
okini3939 1:0dac72ab5910 253 DMAC01_DMARS_CH1_RID_SHIFT,
okini3939 1:0dac72ab5910 254 DMAC01_DMARS_CH1_RID);
okini3939 1:0dac72ab5910 255 RZA_IO_RegWrite_32(&DMAC01.DMARS,
okini3939 1:0dac72ab5910 256 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
okini3939 1:0dac72ab5910 257 DMAC01_DMARS_CH1_MID_SHIFT,
okini3939 1:0dac72ab5910 258 DMAC01_DMARS_CH1_MID);
okini3939 1:0dac72ab5910 259
okini3939 1:0dac72ab5910 260 /* PR : Round robin mode */
okini3939 1:0dac72ab5910 261 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
okini3939 1:0dac72ab5910 262 1,
okini3939 1:0dac72ab5910 263 DMAC07_DCTRL_0_7_PR_SHIFT,
okini3939 1:0dac72ab5910 264 DMAC07_DCTRL_0_7_PR);
okini3939 1:0dac72ab5910 265 }
okini3939 1:0dac72ab5910 266 }
okini3939 1:0dac72ab5910 267
okini3939 1:0dac72ab5910 268 /*******************************************************************************
okini3939 1:0dac72ab5910 269 * Function Name: usb0_host_DMAC1_Open
okini3939 1:0dac72ab5910 270 * Description : Enables DMAC channel 1 transfer.
okini3939 1:0dac72ab5910 271 * Arguments : uint32_t req : DMAC request mode
okini3939 1:0dac72ab5910 272 * Return Value : 0 : Succeeded in enabling DMA transfer
okini3939 1:0dac72ab5910 273 * : -1 : Failed to enable DMA transfer (due to DMA operation)
okini3939 1:0dac72ab5910 274 *******************************************************************************/
okini3939 1:0dac72ab5910 275 int32_t usb0_host_DMAC1_Open (uint32_t req)
okini3939 1:0dac72ab5910 276 {
okini3939 1:0dac72ab5910 277 int32_t ret;
okini3939 1:0dac72ab5910 278 volatile uint8_t dummy;
okini3939 1:0dac72ab5910 279
okini3939 1:0dac72ab5910 280 /* Transferable? */
okini3939 1:0dac72ab5910 281 if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
okini3939 1:0dac72ab5910 282 DMAC1_CHSTAT_n_EN_SHIFT,
okini3939 1:0dac72ab5910 283 DMAC1_CHSTAT_n_EN)) &&
okini3939 1:0dac72ab5910 284 (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
okini3939 1:0dac72ab5910 285 DMAC1_CHSTAT_n_TACT_SHIFT,
okini3939 1:0dac72ab5910 286 DMAC1_CHSTAT_n_TACT)))
okini3939 1:0dac72ab5910 287 {
okini3939 1:0dac72ab5910 288 /* Clear Channel Status Register */
okini3939 1:0dac72ab5910 289 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
okini3939 1:0dac72ab5910 290 1,
okini3939 1:0dac72ab5910 291 DMAC1_CHCTRL_n_SWRST_SHIFT,
okini3939 1:0dac72ab5910 292 DMAC1_CHCTRL_n_SWRST);
okini3939 1:0dac72ab5910 293 dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
okini3939 1:0dac72ab5910 294 DMAC1_CHCTRL_n_SWRST_SHIFT,
okini3939 1:0dac72ab5910 295 DMAC1_CHCTRL_n_SWRST);
okini3939 1:0dac72ab5910 296 /* Enable DMA transfer */
okini3939 1:0dac72ab5910 297 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
okini3939 1:0dac72ab5910 298 1,
okini3939 1:0dac72ab5910 299 DMAC1_CHCTRL_n_SETEN_SHIFT,
okini3939 1:0dac72ab5910 300 DMAC1_CHCTRL_n_SETEN);
okini3939 1:0dac72ab5910 301
okini3939 1:0dac72ab5910 302 /* ---- Request by software ---- */
okini3939 1:0dac72ab5910 303 if (DMAC_REQ_MODE_SOFT == req)
okini3939 1:0dac72ab5910 304 {
okini3939 1:0dac72ab5910 305 /* DMA transfer Request by software */
okini3939 1:0dac72ab5910 306 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
okini3939 1:0dac72ab5910 307 1,
okini3939 1:0dac72ab5910 308 DMAC1_CHCTRL_n_STG_SHIFT,
okini3939 1:0dac72ab5910 309 DMAC1_CHCTRL_n_STG);
okini3939 1:0dac72ab5910 310 }
okini3939 1:0dac72ab5910 311
okini3939 1:0dac72ab5910 312 ret = 0;
okini3939 1:0dac72ab5910 313 }
okini3939 1:0dac72ab5910 314 else
okini3939 1:0dac72ab5910 315 {
okini3939 1:0dac72ab5910 316 ret = -1;
okini3939 1:0dac72ab5910 317 }
okini3939 1:0dac72ab5910 318
okini3939 1:0dac72ab5910 319 return ret;
okini3939 1:0dac72ab5910 320 }
okini3939 1:0dac72ab5910 321
okini3939 1:0dac72ab5910 322 /*******************************************************************************
okini3939 1:0dac72ab5910 323 * Function Name: usb0_host_DMAC1_Close
okini3939 1:0dac72ab5910 324 * Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer
okini3939 1:0dac72ab5910 325 * : byte count at the time of DMA transfer abort to the argument
okini3939 1:0dac72ab5910 326 * : *remain.
okini3939 1:0dac72ab5910 327 * Arguments : uint32_t * remain : Remaining transfer byte count when
okini3939 1:0dac72ab5910 328 * : : DMA transfer is aborted
okini3939 1:0dac72ab5910 329 * Return Value : none
okini3939 1:0dac72ab5910 330 *******************************************************************************/
okini3939 1:0dac72ab5910 331 void usb0_host_DMAC1_Close (uint32_t * remain)
okini3939 1:0dac72ab5910 332 {
okini3939 1:0dac72ab5910 333
okini3939 1:0dac72ab5910 334 /* ==== Abort transfer ==== */
okini3939 1:0dac72ab5910 335 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
okini3939 1:0dac72ab5910 336 1,
okini3939 1:0dac72ab5910 337 DMAC1_CHCTRL_n_CLREN_SHIFT,
okini3939 1:0dac72ab5910 338 DMAC1_CHCTRL_n_CLREN);
okini3939 1:0dac72ab5910 339
okini3939 1:0dac72ab5910 340 while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
okini3939 1:0dac72ab5910 341 DMAC1_CHSTAT_n_TACT_SHIFT,
okini3939 1:0dac72ab5910 342 DMAC1_CHSTAT_n_TACT))
okini3939 1:0dac72ab5910 343 {
okini3939 1:0dac72ab5910 344 /* Loop until transfer is aborted */
okini3939 1:0dac72ab5910 345 }
okini3939 1:0dac72ab5910 346
okini3939 1:0dac72ab5910 347 while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
okini3939 1:0dac72ab5910 348 DMAC1_CHSTAT_n_EN_SHIFT,
okini3939 1:0dac72ab5910 349 DMAC1_CHSTAT_n_EN))
okini3939 1:0dac72ab5910 350 {
okini3939 1:0dac72ab5910 351 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
okini3939 1:0dac72ab5910 352 }
okini3939 1:0dac72ab5910 353 /* ==== Obtain remaining transfer byte count ==== */
okini3939 1:0dac72ab5910 354 *remain = DMAC1.CRTB_n;
okini3939 1:0dac72ab5910 355 }
okini3939 1:0dac72ab5910 356
okini3939 1:0dac72ab5910 357 /*******************************************************************************
okini3939 1:0dac72ab5910 358 * Function Name: usb0_host_DMAC1_Load_Set
okini3939 1:0dac72ab5910 359 * Description : Sets the transfer source address, transfer destination
okini3939 1:0dac72ab5910 360 * : address, and total transfer byte count respectively
okini3939 1:0dac72ab5910 361 * : specified by the argument src_addr, dst_addr, and count to
okini3939 1:0dac72ab5910 362 * : DMAC channel 1 as DMA transfer information.
okini3939 1:0dac72ab5910 363 * : Sets the register set selected by the CHCFG_n register
okini3939 1:0dac72ab5910 364 * : RSEL bit from the Next0 or Next1 register set.
okini3939 1:0dac72ab5910 365 * : This function should be called when DMA transfer of DMAC
okini3939 1:0dac72ab5910 366 * : channel 1 is aboted.
okini3939 1:0dac72ab5910 367 * Arguments : uint32_t src_addr : Transfer source address
okini3939 1:0dac72ab5910 368 * : uint32_t dst_addr : Transfer destination address
okini3939 1:0dac72ab5910 369 * : uint32_t count : Total transfer byte count
okini3939 1:0dac72ab5910 370 * Return Value : none
okini3939 1:0dac72ab5910 371 *******************************************************************************/
okini3939 1:0dac72ab5910 372 void usb0_host_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
okini3939 1:0dac72ab5910 373 {
okini3939 1:0dac72ab5910 374 uint8_t reg_set;
okini3939 1:0dac72ab5910 375
okini3939 1:0dac72ab5910 376 /* Obtain register set in use */
okini3939 1:0dac72ab5910 377 reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
okini3939 1:0dac72ab5910 378 DMAC1_CHSTAT_n_SR_SHIFT,
okini3939 1:0dac72ab5910 379 DMAC1_CHSTAT_n_SR);
okini3939 1:0dac72ab5910 380
okini3939 1:0dac72ab5910 381 /* ==== Load ==== */
okini3939 1:0dac72ab5910 382 if (0 == reg_set)
okini3939 1:0dac72ab5910 383 {
okini3939 1:0dac72ab5910 384 /* ---- Next0 Register Set ---- */
okini3939 1:0dac72ab5910 385 DMAC1.N0SA_n = src_addr; /* Start address of transfer source */
okini3939 1:0dac72ab5910 386 DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */
okini3939 1:0dac72ab5910 387 DMAC1.N0TB_n = count; /* Total transfer byte count */
okini3939 1:0dac72ab5910 388 }
okini3939 1:0dac72ab5910 389 else
okini3939 1:0dac72ab5910 390 {
okini3939 1:0dac72ab5910 391 /* ---- Next1 Register Set ---- */
okini3939 1:0dac72ab5910 392 DMAC1.N1SA_n = src_addr; /* Start address of transfer source */
okini3939 1:0dac72ab5910 393 DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */
okini3939 1:0dac72ab5910 394 DMAC1.N1TB_n = count; /* Total transfer byte count */
okini3939 1:0dac72ab5910 395 }
okini3939 1:0dac72ab5910 396 }
okini3939 1:0dac72ab5910 397
okini3939 1:0dac72ab5910 398 /*******************************************************************************
okini3939 1:0dac72ab5910 399 * Function Name: usb0_host_DMAC2_PeriReqInit
okini3939 1:0dac72ab5910 400 * Description : Sets the register mode for DMA mode and the on-chip peripheral
okini3939 1:0dac72ab5910 401 * : module request for transfer request for DMAC channel 2.
okini3939 1:0dac72ab5910 402 * : Executes DMAC initial setting using the DMA information
okini3939 1:0dac72ab5910 403 * : specified by the argument *trans_info and the enabled/disabled
okini3939 1:0dac72ab5910 404 * : continuous transfer specified by the argument continuation.
okini3939 1:0dac72ab5910 405 * : Registers DMAC channel 2 interrupt handler function and sets
okini3939 1:0dac72ab5910 406 * : the interrupt priority level. Then enables transfer completion
okini3939 1:0dac72ab5910 407 * : interrupt.
okini3939 1:0dac72ab5910 408 * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
okini3939 1:0dac72ab5910 409 * : : register
okini3939 1:0dac72ab5910 410 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
okini3939 1:0dac72ab5910 411 * : uint32_t continuation : Set continuous transfer to be valid
okini3939 1:0dac72ab5910 412 * : : after DMA transfer has been completed
okini3939 1:0dac72ab5910 413 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
okini3939 1:0dac72ab5910 414 * : DMAC_SAMPLE_SINGLE : Do not execute continuous
okini3939 1:0dac72ab5910 415 * : : transfer
okini3939 1:0dac72ab5910 416 * : uint32_t request_factor : Factor for on-chip peripheral module
okini3939 1:0dac72ab5910 417 * : : request
okini3939 1:0dac72ab5910 418 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
okini3939 1:0dac72ab5910 419 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
okini3939 1:0dac72ab5910 420 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
okini3939 1:0dac72ab5910 421 * : :
okini3939 1:0dac72ab5910 422 * : uint32_t req_direction : Setting value of CHCFG_n register
okini3939 1:0dac72ab5910 423 * : : REQD bit
okini3939 1:0dac72ab5910 424 * Return Value : none
okini3939 1:0dac72ab5910 425 *******************************************************************************/
okini3939 1:0dac72ab5910 426 void usb0_host_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
okini3939 1:0dac72ab5910 427 uint32_t request_factor, uint32_t req_direction)
okini3939 1:0dac72ab5910 428 {
okini3939 1:0dac72ab5910 429 /* ==== Register mode ==== */
okini3939 1:0dac72ab5910 430 if (DMAC_MODE_REGISTER == dmamode)
okini3939 1:0dac72ab5910 431 {
okini3939 1:0dac72ab5910 432 /* ==== Next0 register set ==== */
okini3939 1:0dac72ab5910 433 DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
okini3939 1:0dac72ab5910 434 DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
okini3939 1:0dac72ab5910 435 DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */
okini3939 1:0dac72ab5910 436
okini3939 1:0dac72ab5910 437 /* DAD : Transfer destination address counting direction */
okini3939 1:0dac72ab5910 438 /* SAD : Transfer source address counting direction */
okini3939 1:0dac72ab5910 439 /* DDS : Transfer destination transfer size */
okini3939 1:0dac72ab5910 440 /* SDS : Transfer source transfer size */
okini3939 1:0dac72ab5910 441 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 442 trans_info->daddr_dir,
okini3939 1:0dac72ab5910 443 DMAC2_CHCFG_n_DAD_SHIFT,
okini3939 1:0dac72ab5910 444 DMAC2_CHCFG_n_DAD);
okini3939 1:0dac72ab5910 445 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 446 trans_info->saddr_dir,
okini3939 1:0dac72ab5910 447 DMAC2_CHCFG_n_SAD_SHIFT,
okini3939 1:0dac72ab5910 448 DMAC2_CHCFG_n_SAD);
okini3939 1:0dac72ab5910 449 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 450 trans_info->dst_size,
okini3939 1:0dac72ab5910 451 DMAC2_CHCFG_n_DDS_SHIFT,
okini3939 1:0dac72ab5910 452 DMAC2_CHCFG_n_DDS);
okini3939 1:0dac72ab5910 453 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 454 trans_info->src_size,
okini3939 1:0dac72ab5910 455 DMAC2_CHCFG_n_SDS_SHIFT,
okini3939 1:0dac72ab5910 456 DMAC2_CHCFG_n_SDS);
okini3939 1:0dac72ab5910 457
okini3939 1:0dac72ab5910 458 /* DMS : Register mode */
okini3939 1:0dac72ab5910 459 /* RSEL : Select Next0 register set */
okini3939 1:0dac72ab5910 460 /* SBE : No discharge of buffer data when aborted */
okini3939 1:0dac72ab5910 461 /* DEM : No DMA interrupt mask */
okini3939 1:0dac72ab5910 462 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 463 0,
okini3939 1:0dac72ab5910 464 DMAC2_CHCFG_n_DMS_SHIFT,
okini3939 1:0dac72ab5910 465 DMAC2_CHCFG_n_DMS);
okini3939 1:0dac72ab5910 466 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 467 0,
okini3939 1:0dac72ab5910 468 DMAC2_CHCFG_n_RSEL_SHIFT,
okini3939 1:0dac72ab5910 469 DMAC2_CHCFG_n_RSEL);
okini3939 1:0dac72ab5910 470 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 471 0,
okini3939 1:0dac72ab5910 472 DMAC2_CHCFG_n_SBE_SHIFT,
okini3939 1:0dac72ab5910 473 DMAC2_CHCFG_n_SBE);
okini3939 1:0dac72ab5910 474 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 475 0,
okini3939 1:0dac72ab5910 476 DMAC2_CHCFG_n_DEM_SHIFT,
okini3939 1:0dac72ab5910 477 DMAC2_CHCFG_n_DEM);
okini3939 1:0dac72ab5910 478
okini3939 1:0dac72ab5910 479 /* ---- Continuous transfer ---- */
okini3939 1:0dac72ab5910 480 if (DMAC_SAMPLE_CONTINUATION == continuation)
okini3939 1:0dac72ab5910 481 {
okini3939 1:0dac72ab5910 482 /* REN : Execute continuous transfer */
okini3939 1:0dac72ab5910 483 /* RSW : Change register set when DMA transfer is completed. */
okini3939 1:0dac72ab5910 484 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 485 1,
okini3939 1:0dac72ab5910 486 DMAC2_CHCFG_n_REN_SHIFT,
okini3939 1:0dac72ab5910 487 DMAC2_CHCFG_n_REN);
okini3939 1:0dac72ab5910 488 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 489 1,
okini3939 1:0dac72ab5910 490 DMAC2_CHCFG_n_RSW_SHIFT,
okini3939 1:0dac72ab5910 491 DMAC2_CHCFG_n_RSW);
okini3939 1:0dac72ab5910 492 }
okini3939 1:0dac72ab5910 493 /* ---- Single transfer ---- */
okini3939 1:0dac72ab5910 494 else
okini3939 1:0dac72ab5910 495 {
okini3939 1:0dac72ab5910 496 /* REN : Do not execute continuous transfer */
okini3939 1:0dac72ab5910 497 /* RSW : Do not change register set when DMA transfer is completed. */
okini3939 1:0dac72ab5910 498 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 499 0,
okini3939 1:0dac72ab5910 500 DMAC2_CHCFG_n_REN_SHIFT,
okini3939 1:0dac72ab5910 501 DMAC2_CHCFG_n_REN);
okini3939 1:0dac72ab5910 502 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 503 0,
okini3939 1:0dac72ab5910 504 DMAC2_CHCFG_n_RSW_SHIFT,
okini3939 1:0dac72ab5910 505 DMAC2_CHCFG_n_RSW);
okini3939 1:0dac72ab5910 506 }
okini3939 1:0dac72ab5910 507
okini3939 1:0dac72ab5910 508 /* TM : Single transfer */
okini3939 1:0dac72ab5910 509 /* SEL : Channel setting */
okini3939 1:0dac72ab5910 510 /* HIEN, LOEN : On-chip peripheral module request */
okini3939 1:0dac72ab5910 511 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 512 0,
okini3939 1:0dac72ab5910 513 DMAC2_CHCFG_n_TM_SHIFT,
okini3939 1:0dac72ab5910 514 DMAC2_CHCFG_n_TM);
okini3939 1:0dac72ab5910 515 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 516 2,
okini3939 1:0dac72ab5910 517 DMAC2_CHCFG_n_SEL_SHIFT,
okini3939 1:0dac72ab5910 518 DMAC2_CHCFG_n_SEL);
okini3939 1:0dac72ab5910 519 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 520 1,
okini3939 1:0dac72ab5910 521 DMAC2_CHCFG_n_HIEN_SHIFT,
okini3939 1:0dac72ab5910 522 DMAC2_CHCFG_n_HIEN);
okini3939 1:0dac72ab5910 523 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 524 0,
okini3939 1:0dac72ab5910 525 DMAC2_CHCFG_n_LOEN_SHIFT,
okini3939 1:0dac72ab5910 526 DMAC2_CHCFG_n_LOEN);
okini3939 1:0dac72ab5910 527
okini3939 1:0dac72ab5910 528 /* ---- Set factor by specified on-chip peripheral module request ---- */
okini3939 1:0dac72ab5910 529 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 530 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
okini3939 1:0dac72ab5910 531 DMAC2_CHCFG_n_AM_SHIFT,
okini3939 1:0dac72ab5910 532 DMAC2_CHCFG_n_AM);
okini3939 1:0dac72ab5910 533 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 534 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
okini3939 1:0dac72ab5910 535 DMAC2_CHCFG_n_LVL_SHIFT,
okini3939 1:0dac72ab5910 536 DMAC2_CHCFG_n_LVL);
okini3939 1:0dac72ab5910 537 if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
okini3939 1:0dac72ab5910 538 {
okini3939 1:0dac72ab5910 539 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 540 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
okini3939 1:0dac72ab5910 541 DMAC2_CHCFG_n_REQD_SHIFT,
okini3939 1:0dac72ab5910 542 DMAC2_CHCFG_n_REQD);
okini3939 1:0dac72ab5910 543 }
okini3939 1:0dac72ab5910 544 else
okini3939 1:0dac72ab5910 545 {
okini3939 1:0dac72ab5910 546 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
okini3939 1:0dac72ab5910 547 req_direction,
okini3939 1:0dac72ab5910 548 DMAC2_CHCFG_n_REQD_SHIFT,
okini3939 1:0dac72ab5910 549 DMAC2_CHCFG_n_REQD);
okini3939 1:0dac72ab5910 550 }
okini3939 1:0dac72ab5910 551 RZA_IO_RegWrite_32(&DMAC23.DMARS,
okini3939 1:0dac72ab5910 552 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
okini3939 1:0dac72ab5910 553 DMAC23_DMARS_CH2_RID_SHIFT,
okini3939 1:0dac72ab5910 554 DMAC23_DMARS_CH2_RID);
okini3939 1:0dac72ab5910 555 RZA_IO_RegWrite_32(&DMAC23.DMARS,
okini3939 1:0dac72ab5910 556 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
okini3939 1:0dac72ab5910 557 DMAC23_DMARS_CH2_MID_SHIFT,
okini3939 1:0dac72ab5910 558 DMAC23_DMARS_CH2_MID);
okini3939 1:0dac72ab5910 559
okini3939 1:0dac72ab5910 560 /* PR : Round robin mode */
okini3939 1:0dac72ab5910 561 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
okini3939 1:0dac72ab5910 562 1,
okini3939 1:0dac72ab5910 563 DMAC07_DCTRL_0_7_PR_SHIFT,
okini3939 1:0dac72ab5910 564 DMAC07_DCTRL_0_7_PR);
okini3939 1:0dac72ab5910 565 }
okini3939 1:0dac72ab5910 566 }
okini3939 1:0dac72ab5910 567
okini3939 1:0dac72ab5910 568 /*******************************************************************************
okini3939 1:0dac72ab5910 569 * Function Name: usb0_host_DMAC2_Open
okini3939 1:0dac72ab5910 570 * Description : Enables DMAC channel 2 transfer.
okini3939 1:0dac72ab5910 571 * Arguments : uint32_t req : DMAC request mode
okini3939 1:0dac72ab5910 572 * Return Value : 0 : Succeeded in enabling DMA transfer
okini3939 1:0dac72ab5910 573 * : -1 : Failed to enable DMA transfer (due to DMA operation)
okini3939 1:0dac72ab5910 574 *******************************************************************************/
okini3939 1:0dac72ab5910 575 int32_t usb0_host_DMAC2_Open (uint32_t req)
okini3939 1:0dac72ab5910 576 {
okini3939 1:0dac72ab5910 577 int32_t ret;
okini3939 1:0dac72ab5910 578 volatile uint8_t dummy;
okini3939 1:0dac72ab5910 579
okini3939 1:0dac72ab5910 580 /* Transferable? */
okini3939 1:0dac72ab5910 581 if ((0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
okini3939 1:0dac72ab5910 582 DMAC2_CHSTAT_n_EN_SHIFT,
okini3939 1:0dac72ab5910 583 DMAC2_CHSTAT_n_EN)) &&
okini3939 1:0dac72ab5910 584 (0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
okini3939 1:0dac72ab5910 585 DMAC2_CHSTAT_n_TACT_SHIFT,
okini3939 1:0dac72ab5910 586 DMAC2_CHSTAT_n_TACT)))
okini3939 1:0dac72ab5910 587 {
okini3939 1:0dac72ab5910 588 /* Clear Channel Status Register */
okini3939 1:0dac72ab5910 589 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
okini3939 1:0dac72ab5910 590 1,
okini3939 1:0dac72ab5910 591 DMAC2_CHCTRL_n_SWRST_SHIFT,
okini3939 1:0dac72ab5910 592 DMAC2_CHCTRL_n_SWRST);
okini3939 1:0dac72ab5910 593 dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
okini3939 1:0dac72ab5910 594 DMAC2_CHCTRL_n_SWRST_SHIFT,
okini3939 1:0dac72ab5910 595 DMAC2_CHCTRL_n_SWRST);
okini3939 1:0dac72ab5910 596 /* Enable DMA transfer */
okini3939 1:0dac72ab5910 597 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
okini3939 1:0dac72ab5910 598 1,
okini3939 1:0dac72ab5910 599 DMAC2_CHCTRL_n_SETEN_SHIFT,
okini3939 1:0dac72ab5910 600 DMAC2_CHCTRL_n_SETEN);
okini3939 1:0dac72ab5910 601
okini3939 1:0dac72ab5910 602 /* ---- Request by software ---- */
okini3939 1:0dac72ab5910 603 if (DMAC_REQ_MODE_SOFT == req)
okini3939 1:0dac72ab5910 604 {
okini3939 1:0dac72ab5910 605 /* DMA transfer Request by software */
okini3939 1:0dac72ab5910 606 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
okini3939 1:0dac72ab5910 607 1,
okini3939 1:0dac72ab5910 608 DMAC2_CHCTRL_n_STG_SHIFT,
okini3939 1:0dac72ab5910 609 DMAC2_CHCTRL_n_STG);
okini3939 1:0dac72ab5910 610 }
okini3939 1:0dac72ab5910 611
okini3939 1:0dac72ab5910 612 ret = 0;
okini3939 1:0dac72ab5910 613 }
okini3939 1:0dac72ab5910 614 else
okini3939 1:0dac72ab5910 615 {
okini3939 1:0dac72ab5910 616 ret = -1;
okini3939 1:0dac72ab5910 617 }
okini3939 1:0dac72ab5910 618
okini3939 1:0dac72ab5910 619 return ret;
okini3939 1:0dac72ab5910 620 }
okini3939 1:0dac72ab5910 621
okini3939 1:0dac72ab5910 622 /*******************************************************************************
okini3939 1:0dac72ab5910 623 * Function Name: usb0_host_DMAC2_Close
okini3939 1:0dac72ab5910 624 * Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer
okini3939 1:0dac72ab5910 625 * : byte count at the time of DMA transfer abort to the argument
okini3939 1:0dac72ab5910 626 * : *remain.
okini3939 1:0dac72ab5910 627 * Arguments : uint32_t * remain : Remaining transfer byte count when
okini3939 1:0dac72ab5910 628 * : : DMA transfer is aborted
okini3939 1:0dac72ab5910 629 * Return Value : none
okini3939 1:0dac72ab5910 630 *******************************************************************************/
okini3939 1:0dac72ab5910 631 void usb0_host_DMAC2_Close (uint32_t * remain)
okini3939 1:0dac72ab5910 632 {
okini3939 1:0dac72ab5910 633
okini3939 1:0dac72ab5910 634 /* ==== Abort transfer ==== */
okini3939 1:0dac72ab5910 635 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
okini3939 1:0dac72ab5910 636 1,
okini3939 1:0dac72ab5910 637 DMAC2_CHCTRL_n_CLREN_SHIFT,
okini3939 1:0dac72ab5910 638 DMAC2_CHCTRL_n_CLREN);
okini3939 1:0dac72ab5910 639
okini3939 1:0dac72ab5910 640 while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
okini3939 1:0dac72ab5910 641 DMAC2_CHSTAT_n_TACT_SHIFT,
okini3939 1:0dac72ab5910 642 DMAC2_CHSTAT_n_TACT))
okini3939 1:0dac72ab5910 643 {
okini3939 1:0dac72ab5910 644 /* Loop until transfer is aborted */
okini3939 1:0dac72ab5910 645 }
okini3939 1:0dac72ab5910 646
okini3939 1:0dac72ab5910 647 while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
okini3939 1:0dac72ab5910 648 DMAC2_CHSTAT_n_EN_SHIFT,
okini3939 1:0dac72ab5910 649 DMAC2_CHSTAT_n_EN))
okini3939 1:0dac72ab5910 650 {
okini3939 1:0dac72ab5910 651 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
okini3939 1:0dac72ab5910 652 }
okini3939 1:0dac72ab5910 653 /* ==== Obtain remaining transfer byte count ==== */
okini3939 1:0dac72ab5910 654 *remain = DMAC2.CRTB_n;
okini3939 1:0dac72ab5910 655 }
okini3939 1:0dac72ab5910 656
okini3939 1:0dac72ab5910 657 /*******************************************************************************
okini3939 1:0dac72ab5910 658 * Function Name: usb0_host_DMAC2_Load_Set
okini3939 1:0dac72ab5910 659 * Description : Sets the transfer source address, transfer destination
okini3939 1:0dac72ab5910 660 * : address, and total transfer byte count respectively
okini3939 1:0dac72ab5910 661 * : specified by the argument src_addr, dst_addr, and count to
okini3939 1:0dac72ab5910 662 * : DMAC channel 2 as DMA transfer information.
okini3939 1:0dac72ab5910 663 * : Sets the register set selected by the CHCFG_n register
okini3939 1:0dac72ab5910 664 * : RSEL bit from the Next0 or Next1 register set.
okini3939 1:0dac72ab5910 665 * : This function should be called when DMA transfer of DMAC
okini3939 1:0dac72ab5910 666 * : channel 2 is aboted.
okini3939 1:0dac72ab5910 667 * Arguments : uint32_t src_addr : Transfer source address
okini3939 1:0dac72ab5910 668 * : uint32_t dst_addr : Transfer destination address
okini3939 1:0dac72ab5910 669 * : uint32_t count : Total transfer byte count
okini3939 1:0dac72ab5910 670 * Return Value : none
okini3939 1:0dac72ab5910 671 *******************************************************************************/
okini3939 1:0dac72ab5910 672 void usb0_host_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
okini3939 1:0dac72ab5910 673 {
okini3939 1:0dac72ab5910 674 uint8_t reg_set;
okini3939 1:0dac72ab5910 675
okini3939 1:0dac72ab5910 676 /* Obtain register set in use */
okini3939 1:0dac72ab5910 677 reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
okini3939 1:0dac72ab5910 678 DMAC2_CHSTAT_n_SR_SHIFT,
okini3939 1:0dac72ab5910 679 DMAC2_CHSTAT_n_SR);
okini3939 1:0dac72ab5910 680
okini3939 1:0dac72ab5910 681 /* ==== Load ==== */
okini3939 1:0dac72ab5910 682 if (0 == reg_set)
okini3939 1:0dac72ab5910 683 {
okini3939 1:0dac72ab5910 684 /* ---- Next0 Register Set ---- */
okini3939 1:0dac72ab5910 685 DMAC2.N0SA_n = src_addr; /* Start address of transfer source */
okini3939 1:0dac72ab5910 686 DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */
okini3939 1:0dac72ab5910 687 DMAC2.N0TB_n = count; /* Total transfer byte count */
okini3939 1:0dac72ab5910 688 }
okini3939 1:0dac72ab5910 689 else
okini3939 1:0dac72ab5910 690 {
okini3939 1:0dac72ab5910 691 /* ---- Next1 Register Set ---- */
okini3939 1:0dac72ab5910 692 DMAC2.N1SA_n = src_addr; /* Start address of transfer source */
okini3939 1:0dac72ab5910 693 DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */
okini3939 1:0dac72ab5910 694 DMAC2.N1TB_n = count; /* Total transfer byte count */
okini3939 1:0dac72ab5910 695 }
okini3939 1:0dac72ab5910 696 }
okini3939 1:0dac72ab5910 697
okini3939 1:0dac72ab5910 698 /* End of File */