Shuto Naruse / Mbed 2 deprecated Eurobot2012_Beacons

Eurobot2012_Beacons

RF12B/RF_defs.h@3:bf8a2e4b8012, 2012-10-17 (annotated)

Committer:
narshu
Date:
Wed Oct 17 22:26:33 2012 +0000
Revision:
3:bf8a2e4b8012
Parent:
0:b8be0a00c4f8 
Commit before publishing

Who changed what in which revision?

UserRevisionLine numberNew contents of line
narshu 0:b8be0a00c4f8 1 /*
narshu 0:b8be0a00c4f8 2 * Open HR20
narshu 0:b8be0a00c4f8 3 *
narshu 0:b8be0a00c4f8 4 * target: ATmega169 @ 4 MHz in Honnywell Rondostat HR20E
narshu 0:b8be0a00c4f8 5 *
narshu 0:b8be0a00c4f8 6 * compiler: WinAVR-20071221
narshu 0:b8be0a00c4f8 7 * avr-libc 1.6.0
narshu 0:b8be0a00c4f8 8 * GCC 4.2.2
narshu 0:b8be0a00c4f8 9 *
narshu 0:b8be0a00c4f8 10 * copyright: 2008 Dario Carluccio (hr20-at-carluccio-dot-de)
narshu 0:b8be0a00c4f8 11 * 2008 Jiri Dobry (jdobry-at-centrum-dot-cz)
narshu 0:b8be0a00c4f8 12 * 2008 Mario Fischer (MarioFischer-at-gmx-dot-net)
narshu 0:b8be0a00c4f8 13 * 2007 Michael Smola (Michael-dot-Smola-at-gmx-dot-net)
narshu 0:b8be0a00c4f8 14 *
narshu 0:b8be0a00c4f8 15 * license: This program is free software; you can redistribute it and/or
narshu 0:b8be0a00c4f8 16 * modify it under the terms of the GNU Library General Public
narshu 0:b8be0a00c4f8 17 * License as published by the Free Software Foundation; either
narshu 0:b8be0a00c4f8 18 * version 2 of the License, or (at your option) any later version.
narshu 0:b8be0a00c4f8 19 *
narshu 0:b8be0a00c4f8 20 * This program is distributed in the hope that it will be useful,
narshu 0:b8be0a00c4f8 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
narshu 0:b8be0a00c4f8 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
narshu 0:b8be0a00c4f8 23 * GNU General Public License for more details.
narshu 0:b8be0a00c4f8 24 *
narshu 0:b8be0a00c4f8 25 * You should have received a copy of the GNU General Public License
narshu 0:b8be0a00c4f8 26 * along with this program. If not, see http:*www.gnu.org/licenses
narshu 0:b8be0a00c4f8 27 */
narshu 0:b8be0a00c4f8 28
narshu 0:b8be0a00c4f8 29 /*
narshu 0:b8be0a00c4f8 30 * \file rfm.h
narshu 0:b8be0a00c4f8 31 * \brief functions to control the RFM12 Radio Transceiver Module
narshu 0:b8be0a00c4f8 32 * \author Mario Fischer <MarioFischer-at-gmx-dot-net>; Michael Smola <Michael-dot-Smola-at-gmx-dot-net>
narshu 0:b8be0a00c4f8 33 * \date $Date: 2010/04/17 17:57:02 $
narshu 0:b8be0a00c4f8 34 * $Rev: 260 $
narshu 0:b8be0a00c4f8 35 */
narshu 0:b8be0a00c4f8 36
narshu 0:b8be0a00c4f8 37
narshu 0:b8be0a00c4f8 38 //#pragma once // multi-iclude prevention. gcc knows this pragma
narshu 0:b8be0a00c4f8 39 #ifndef rfm_H
narshu 0:b8be0a00c4f8 40 #define rfm_H
narshu 0:b8be0a00c4f8 41
narshu 0:b8be0a00c4f8 42
narshu 0:b8be0a00c4f8 43 #define RFM_SPI_16(OUTVAL) rfm_spi16(OUTVAL) //<! a function that gets a uint16_t (clocked out value) and returns a uint16_t (clocked in value)
narshu 0:b8be0a00c4f8 44
narshu 0:b8be0a00c4f8 45 #define RFM_CLK_OUTPUT 0
narshu 0:b8be0a00c4f8 46
narshu 0:b8be0a00c4f8 47 /*
narshu 0:b8be0a00c4f8 48 #define RFM_TESTPIN_INIT
narshu 0:b8be0a00c4f8 49 #define RFM_TESTPIN_ON
narshu 0:b8be0a00c4f8 50 #define RFM_TESTPIN_OFF
narshu 0:b8be0a00c4f8 51 #define RFM_TESTPIN_TOG
narshu 0:b8be0a00c4f8 52
narshu 0:b8be0a00c4f8 53 #define RFM_CONFIG_DISABLE 0x00 //<! RFM_CONFIG_*** are combinable flags, what the RFM shold do
narshu 0:b8be0a00c4f8 54 #define RFM_CONFIG_BROADCASTSTATUS 0x01 //<! Flag that enables the HR20's status broadcast every minute
narshu 0:b8be0a00c4f8 55
narshu 0:b8be0a00c4f8 56 #define RFM_CONFIG_ENABLEALL 0xff
narshu 0:b8be0a00c4f8 57 */
narshu 0:b8be0a00c4f8 58
narshu 0:b8be0a00c4f8 59 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 60 //
narshu 0:b8be0a00c4f8 61 // RFM status bits
narshu 0:b8be0a00c4f8 62 //
narshu 0:b8be0a00c4f8 63 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 64
narshu 0:b8be0a00c4f8 65 // Interrupt bits, latched ////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 66
narshu 0:b8be0a00c4f8 67 #define RFM_STATUS_FFIT 0x8000 // RX FIFO reached the progr. number of bits
narshu 0:b8be0a00c4f8 68 // Cleared by any FIFO read method
narshu 0:b8be0a00c4f8 69
narshu 0:b8be0a00c4f8 70 #define RFM_STATUS_RGIT 0x8000 // TX register is ready to receive
narshu 0:b8be0a00c4f8 71 // Cleared by TX write
narshu 0:b8be0a00c4f8 72
narshu 0:b8be0a00c4f8 73 #define RFM_STATUS_POR 0x4000 // Power On reset
narshu 0:b8be0a00c4f8 74 // Cleared by read status
narshu 0:b8be0a00c4f8 75
narshu 0:b8be0a00c4f8 76 #define RFM_STATUS_RGUR 0x2000 // TX register underrun, register over write
narshu 0:b8be0a00c4f8 77 // Cleared by read status
narshu 0:b8be0a00c4f8 78
narshu 0:b8be0a00c4f8 79 #define RFM_STATUS_FFOV 0x2000 // RX FIFO overflow
narshu 0:b8be0a00c4f8 80 // Cleared by read status
narshu 0:b8be0a00c4f8 81
narshu 0:b8be0a00c4f8 82 #define RFM_STATUS_WKUP 0x1000 // Wake up timer overflow
narshu 0:b8be0a00c4f8 83 // Cleared by read status
narshu 0:b8be0a00c4f8 84
narshu 0:b8be0a00c4f8 85 #define RFM_STATUS_EXT 0x0800 // Interupt changed to low
narshu 0:b8be0a00c4f8 86 // Cleared by read status
narshu 0:b8be0a00c4f8 87
narshu 0:b8be0a00c4f8 88 #define RFM_STATUS_LBD 0x0400 // Low battery detect
narshu 0:b8be0a00c4f8 89
narshu 0:b8be0a00c4f8 90 // Status bits ////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 91
narshu 0:b8be0a00c4f8 92 #define RFM_STATUS_FFEM 0x0200 // FIFO is empty
narshu 0:b8be0a00c4f8 93 #define RFM_STATUS_ATS 0x0100 // TX mode: Strong enough RF signal
narshu 0:b8be0a00c4f8 94 #define RFM_STATUS_RSSI 0x0100 // RX mode: signal strength above programmed limit
narshu 0:b8be0a00c4f8 95 #define RFM_STATUS_DQD 0x0080 // Data Quality detector output
narshu 0:b8be0a00c4f8 96 #define RFM_STATUS_CRL 0x0040 // Clock recovery lock
narshu 0:b8be0a00c4f8 97 #define RFM_STATUS_ATGL 0x0020 // Toggling in each AFC cycle
narshu 0:b8be0a00c4f8 98
narshu 0:b8be0a00c4f8 99 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 100 //
narshu 0:b8be0a00c4f8 101 // 1. Configuration Setting Command
narshu 0:b8be0a00c4f8 102 //
narshu 0:b8be0a00c4f8 103 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 104
narshu 0:b8be0a00c4f8 105 #define RFM_CONFIG 0x8000
narshu 0:b8be0a00c4f8 106
narshu 0:b8be0a00c4f8 107 #define RFM_CONFIG_EL 0x8080 // Enable TX Register
narshu 0:b8be0a00c4f8 108 #define RFM_CONFIG_EF 0x8040 // Enable RX FIFO buffer
narshu 0:b8be0a00c4f8 109 #define RFM_CONFIG_BAND_315 0x8000 // Frequency band
narshu 0:b8be0a00c4f8 110 #define RFM_CONFIG_BAND_433 0x8010
narshu 0:b8be0a00c4f8 111 #define RFM_CONFIG_BAND_868 0x8020
narshu 0:b8be0a00c4f8 112 #define RFM_CONFIG_BAND_915 0x8030
narshu 0:b8be0a00c4f8 113 #define RFM_CONFIG_X_8_5pf 0x8000 // Crystal Load Capacitor
narshu 0:b8be0a00c4f8 114 #define RFM_CONFIG_X_9_0pf 0x8001
narshu 0:b8be0a00c4f8 115 #define RFM_CONFIG_X_9_5pf 0x8002
narshu 0:b8be0a00c4f8 116 #define RFM_CONFIG_X_10_0pf 0x8003
narshu 0:b8be0a00c4f8 117 #define RFM_CONFIG_X_10_5pf 0x8004
narshu 0:b8be0a00c4f8 118 #define RFM_CONFIG_X_11_0pf 0x8005
narshu 0:b8be0a00c4f8 119 #define RFM_CONFIG_X_11_5pf 0x8006
narshu 0:b8be0a00c4f8 120 #define RFM_CONFIG_X_12_0pf 0x8007
narshu 0:b8be0a00c4f8 121 #define RFM_CONFIG_X_12_5pf 0x8008
narshu 0:b8be0a00c4f8 122 #define RFM_CONFIG_X_13_0pf 0x8009
narshu 0:b8be0a00c4f8 123 #define RFM_CONFIG_X_13_5pf 0x800A
narshu 0:b8be0a00c4f8 124 #define RFM_CONFIG_X_14_0pf 0x800B
narshu 0:b8be0a00c4f8 125 #define RFM_CONFIG_X_14_5pf 0x800C
narshu 0:b8be0a00c4f8 126 #define RFM_CONFIG_X_15_0pf 0x800D
narshu 0:b8be0a00c4f8 127 #define RFM_CONFIG_X_15_5pf 0x800E
narshu 0:b8be0a00c4f8 128 #define RFM_CONFIG_X_16_0pf 0x800F
narshu 0:b8be0a00c4f8 129
narshu 0:b8be0a00c4f8 130 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 131 //
narshu 0:b8be0a00c4f8 132 // 2. Power Management Command
narshu 0:b8be0a00c4f8 133 //
narshu 0:b8be0a00c4f8 134 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 135
narshu 0:b8be0a00c4f8 136 #define RFM_POWER_MANAGEMENT 0x8200
narshu 0:b8be0a00c4f8 137
narshu 0:b8be0a00c4f8 138 #define RFM_POWER_MANAGEMENT_ER 0x8280 // Enable receiver
narshu 0:b8be0a00c4f8 139 #define RFM_POWER_MANAGEMENT_EBB 0x8240 // Enable base band block
narshu 0:b8be0a00c4f8 140 #define RFM_POWER_MANAGEMENT_ET 0x8220 // Enable transmitter
narshu 0:b8be0a00c4f8 141 #define RFM_POWER_MANAGEMENT_ES 0x8210 // Enable synthesizer
narshu 0:b8be0a00c4f8 142 #define RFM_POWER_MANAGEMENT_EX 0x8208 // Enable crystal oscillator
narshu 0:b8be0a00c4f8 143 #define RFM_POWER_MANAGEMENT_EB 0x8204 // Enable low battery detector
narshu 0:b8be0a00c4f8 144 #define RFM_POWER_MANAGEMENT_EW 0x8202 // Enable wake-up timer
narshu 0:b8be0a00c4f8 145 #define RFM_POWER_MANAGEMENT_DC 0x8201 // Disable clock output of CLK pin
narshu 0:b8be0a00c4f8 146
narshu 0:b8be0a00c4f8 147 #ifndef RFM_CLK_OUTPUT
narshu 0:b8be0a00c4f8 148 #error RFM_CLK_OUTPUT must be defined to 0 or 1
narshu 0:b8be0a00c4f8 149 #endif
narshu 0:b8be0a00c4f8 150 #if RFM_CLK_OUTPUT
narshu 0:b8be0a00c4f8 151 #define RFM_TX_ON_PRE() RFM_SPI_16( \
narshu 0:b8be0a00c4f8 152 RFM_POWER_MANAGEMENT_ES | \
narshu 0:b8be0a00c4f8 153 RFM_POWER_MANAGEMENT_EX )
narshu 0:b8be0a00c4f8 154 #define RFM_TX_ON() RFM_SPI_16( \
narshu 0:b8be0a00c4f8 155 RFM_POWER_MANAGEMENT_ET | \
narshu 0:b8be0a00c4f8 156 RFM_POWER_MANAGEMENT_ES | \
narshu 0:b8be0a00c4f8 157 RFM_POWER_MANAGEMENT_EX )
narshu 0:b8be0a00c4f8 158 #define RFM_RX_ON() RFM_SPI_16( \
narshu 0:b8be0a00c4f8 159 RFM_POWER_MANAGEMENT_ER | \
narshu 0:b8be0a00c4f8 160 RFM_POWER_MANAGEMENT_EBB | \
narshu 0:b8be0a00c4f8 161 RFM_POWER_MANAGEMENT_ES | \
narshu 0:b8be0a00c4f8 162 RFM_POWER_MANAGEMENT_EX )
narshu 0:b8be0a00c4f8 163 #define RFM_OFF() RFM_SPI_16( \
narshu 0:b8be0a00c4f8 164 RFM_POWER_MANAGEMENT_EX )
narshu 0:b8be0a00c4f8 165 #else
narshu 0:b8be0a00c4f8 166 #define RFM_TX_ON_PRE() RFM_SPI_16( \
narshu 0:b8be0a00c4f8 167 RFM_POWER_MANAGEMENT_DC | \
narshu 0:b8be0a00c4f8 168 RFM_POWER_MANAGEMENT_ES | \
narshu 0:b8be0a00c4f8 169 RFM_POWER_MANAGEMENT_EX )
narshu 0:b8be0a00c4f8 170 #define RFM_TX_ON() RFM_SPI_16( \
narshu 0:b8be0a00c4f8 171 RFM_POWER_MANAGEMENT_DC | \
narshu 0:b8be0a00c4f8 172 RFM_POWER_MANAGEMENT_ET | \
narshu 0:b8be0a00c4f8 173 RFM_POWER_MANAGEMENT_ES | \
narshu 0:b8be0a00c4f8 174 RFM_POWER_MANAGEMENT_EX )
narshu 0:b8be0a00c4f8 175 #define RFM_RX_ON() RFM_SPI_16( \
narshu 0:b8be0a00c4f8 176 RFM_POWER_MANAGEMENT_DC | \
narshu 0:b8be0a00c4f8 177 RFM_POWER_MANAGEMENT_ER | \
narshu 0:b8be0a00c4f8 178 RFM_POWER_MANAGEMENT_EBB | \
narshu 0:b8be0a00c4f8 179 RFM_POWER_MANAGEMENT_ES | \
narshu 0:b8be0a00c4f8 180 RFM_POWER_MANAGEMENT_EX )
narshu 0:b8be0a00c4f8 181 #define RFM_OFF() RFM_SPI_16(RFM_POWER_MANAGEMENT_DC)
narshu 0:b8be0a00c4f8 182 #endif
narshu 0:b8be0a00c4f8 183 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 184 //
narshu 0:b8be0a00c4f8 185 // 3. Frequency Setting Command
narshu 0:b8be0a00c4f8 186 //
narshu 0:b8be0a00c4f8 187 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 188
narshu 0:b8be0a00c4f8 189 #define RFM_FREQUENCY 0xA000
narshu 0:b8be0a00c4f8 190
narshu 0:b8be0a00c4f8 191 #define RFM_FREQ_315Band(v) (uint16_t)((v/10.0-31)*4000)
narshu 0:b8be0a00c4f8 192 #define RFM_FREQ_433Band(v) (uint16_t)((v/10.0-43)*4000)
narshu 0:b8be0a00c4f8 193 #define RFM_FREQ_868Band(v) (uint16_t)((v/20.0-43)*4000)
narshu 0:b8be0a00c4f8 194 #define RFM_FREQ_915Band(v) (uint16_t)((v/30.0-30)*4000)
narshu 0:b8be0a00c4f8 195
narshu 0:b8be0a00c4f8 196 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 197 //
narshu 0:b8be0a00c4f8 198 // 4. Data Rate Command
narshu 0:b8be0a00c4f8 199 //
narshu 0:b8be0a00c4f8 200 /////////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 201
narshu 0:b8be0a00c4f8 202 #define RFM_BAUD_RATE 9600
narshu 0:b8be0a00c4f8 203
narshu 0:b8be0a00c4f8 204 #define RFM_DATA_RATE 0xC600
narshu 0:b8be0a00c4f8 205
narshu 0:b8be0a00c4f8 206 #define RFM_DATA_RATE_CS 0xC680
narshu 0:b8be0a00c4f8 207 #define RFM_DATA_RATE_4800 0xC647
narshu 0:b8be0a00c4f8 208 #define RFM_DATA_RATE_9600 0xC623
narshu 0:b8be0a00c4f8 209 #define RFM_DATA_RATE_19200 0xC611
narshu 0:b8be0a00c4f8 210 #define RFM_DATA_RATE_38400 0xC608
narshu 0:b8be0a00c4f8 211 #define RFM_DATA_RATE_57600 0xC605
narshu 0:b8be0a00c4f8 212
narshu 0:b8be0a00c4f8 213 #define RFM_SET_DATARATE(baud) ( ((baud)<5400) ? (RFM_DATA_RATE_CS|((43104/(baud))-1)) : (RFM_DATA_RATE|((344828UL/(baud))-1)) )
narshu 0:b8be0a00c4f8 214
narshu 0:b8be0a00c4f8 215 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 216 //
narshu 0:b8be0a00c4f8 217 // 5. Receiver Control Command
narshu 0:b8be0a00c4f8 218 //
narshu 0:b8be0a00c4f8 219 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 220
narshu 0:b8be0a00c4f8 221 #define RFM_RX_CONTROL 0x9000
narshu 0:b8be0a00c4f8 222
narshu 0:b8be0a00c4f8 223 #define RFM_RX_CONTROL_P20_INT 0x9000 // Pin20 = ExternalInt
narshu 0:b8be0a00c4f8 224 #define RFM_RX_CONTROL_P20_VDI 0x9400 // Pin20 = VDI out
narshu 0:b8be0a00c4f8 225
narshu 0:b8be0a00c4f8 226 #define RFM_RX_CONTROL_VDI_FAST 0x9000 // fast VDI Response time
narshu 0:b8be0a00c4f8 227 #define RFM_RX_CONTROL_VDI_MED 0x9100 // medium
narshu 0:b8be0a00c4f8 228 #define RFM_RX_CONTROL_VDI_SLOW 0x9200 // slow
narshu 0:b8be0a00c4f8 229 #define RFM_RX_CONTROL_VDI_ON 0x9300 // Always on
narshu 0:b8be0a00c4f8 230
narshu 0:b8be0a00c4f8 231 #define RFM_RX_CONTROL_BW_400 0x9020 // bandwidth 400kHz
narshu 0:b8be0a00c4f8 232 #define RFM_RX_CONTROL_BW_340 0x9040 // bandwidth 340kHz
narshu 0:b8be0a00c4f8 233 #define RFM_RX_CONTROL_BW_270 0x9060 // bandwidth 270kHz
narshu 0:b8be0a00c4f8 234 #define RFM_RX_CONTROL_BW_200 0x9080 // bandwidth 200kHz
narshu 0:b8be0a00c4f8 235 #define RFM_RX_CONTROL_BW_134 0x90A0 // bandwidth 134kHz
narshu 0:b8be0a00c4f8 236 #define RFM_RX_CONTROL_BW_67 0x90C0 // bandwidth 67kHz
narshu 0:b8be0a00c4f8 237
narshu 0:b8be0a00c4f8 238 #define RFM_RX_CONTROL_GAIN_0 0x9000 // LNA gain 0db
narshu 0:b8be0a00c4f8 239 #define RFM_RX_CONTROL_GAIN_6 0x9008 // LNA gain -6db
narshu 0:b8be0a00c4f8 240 #define RFM_RX_CONTROL_GAIN_14 0x9010 // LNA gain -14db
narshu 0:b8be0a00c4f8 241 #define RFM_RX_CONTROL_GAIN_20 0x9018 // LNA gain -20db
narshu 0:b8be0a00c4f8 242
narshu 0:b8be0a00c4f8 243 #define RFM_RX_CONTROL_RSSI_103 0x9000 // DRSSI threshold -103dbm
narshu 0:b8be0a00c4f8 244 #define RFM_RX_CONTROL_RSSI_97 0x9001 // DRSSI threshold -97dbm
narshu 0:b8be0a00c4f8 245 #define RFM_RX_CONTROL_RSSI_91 0x9002 // DRSSI threshold -91dbm
narshu 0:b8be0a00c4f8 246 #define RFM_RX_CONTROL_RSSI_85 0x9003 // DRSSI threshold -85dbm
narshu 0:b8be0a00c4f8 247 #define RFM_RX_CONTROL_RSSI_79 0x9004 // DRSSI threshold -79dbm
narshu 0:b8be0a00c4f8 248 #define RFM_RX_CONTROL_RSSI_73 0x9005 // DRSSI threshold -73dbm
narshu 0:b8be0a00c4f8 249 //#define RFM_RX_CONTROL_RSSI_67 0x9006 // DRSSI threshold -67dbm // RF12B reserved
narshu 0:b8be0a00c4f8 250 //#define RFM_RX_CONTROL_RSSI_61 0x9007 // DRSSI threshold -61dbm // RF12B reserved
narshu 0:b8be0a00c4f8 251
narshu 0:b8be0a00c4f8 252 #define RFM_RX_CONTROL_BW(baud) (((baud)<8000) ? \
narshu 0:b8be0a00c4f8 253 RFM_RX_CONTROL_BW_67 : \
narshu 0:b8be0a00c4f8 254 ( \
narshu 0:b8be0a00c4f8 255 ((baud)<30000) ? \
narshu 0:b8be0a00c4f8 256 RFM_RX_CONTROL_BW_134 : \
narshu 0:b8be0a00c4f8 257 RFM_RX_CONTROL_BW_200 \
narshu 0:b8be0a00c4f8 258 ))
narshu 0:b8be0a00c4f8 259
narshu 0:b8be0a00c4f8 260 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 261 //
narshu 0:b8be0a00c4f8 262 // 6. Data Filter Command
narshu 0:b8be0a00c4f8 263 //
narshu 0:b8be0a00c4f8 264 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 265
narshu 0:b8be0a00c4f8 266 #define RFM_DATA_FILTER 0xC228
narshu 0:b8be0a00c4f8 267
narshu 0:b8be0a00c4f8 268 #define RFM_DATA_FILTER_AL 0xC2A8 // clock recovery auto-lock
narshu 0:b8be0a00c4f8 269 #define RFM_DATA_FILTER_ML 0xC268 // clock recovery fast mode
narshu 0:b8be0a00c4f8 270 #define RFM_DATA_FILTER_DIG 0xC228 // data filter type digital
narshu 0:b8be0a00c4f8 271 #define RFM_DATA_FILTER_ANALOG 0xC238 // data filter type analog
narshu 0:b8be0a00c4f8 272 #define RFM_DATA_FILTER_DQD(level) (RFM_DATA_FILTER | (level & 0x7))
narshu 0:b8be0a00c4f8 273
narshu 0:b8be0a00c4f8 274 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 275 //
narshu 0:b8be0a00c4f8 276 // 7. FIFO and Reset Mode Command
narshu 0:b8be0a00c4f8 277 //
narshu 0:b8be0a00c4f8 278 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 279
narshu 0:b8be0a00c4f8 280 #define RFM_FIFO 0xCA00
narshu 0:b8be0a00c4f8 281
narshu 0:b8be0a00c4f8 282 #define RFM_FIFO_AL 0xCA04 // FIFO Start condition sync-word/always
narshu 0:b8be0a00c4f8 283 #define RFM_FIFO_FF 0xCA02 // Enable FIFO fill
narshu 0:b8be0a00c4f8 284 #define RFM_FIFO_DR 0xCA01 // Disable hi sens reset mode
narshu 0:b8be0a00c4f8 285 #define RFM_FIFO_IT(level) (RFM_FIFO | (( (level) & 0xF)<<4))
narshu 0:b8be0a00c4f8 286
narshu 0:b8be0a00c4f8 287 #define RFM_FIFO_OFF() RFM_SPI_16(RFM_FIFO_IT(8) | RFM_FIFO_DR)
narshu 0:b8be0a00c4f8 288 #define RFM_FIFO_ON() RFM_SPI_16(RFM_FIFO_IT(8) | RFM_FIFO_FF | RFM_FIFO_DR)
narshu 0:b8be0a00c4f8 289
narshu 0:b8be0a00c4f8 290 /////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 291 //
narshu 0:b8be0a00c4f8 292 // 8. Receiver FIFO Read
narshu 0:b8be0a00c4f8 293 //
narshu 0:b8be0a00c4f8 294 /////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 295
narshu 0:b8be0a00c4f8 296 #define RFM_READ_FIFO() (RFM_SPI_16(0xB000) & 0xFF)
narshu 0:b8be0a00c4f8 297
narshu 0:b8be0a00c4f8 298 /////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 299 //
narshu 0:b8be0a00c4f8 300 // 9. AFC Command
narshu 0:b8be0a00c4f8 301 //
narshu 0:b8be0a00c4f8 302 /////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 303
narshu 0:b8be0a00c4f8 304 #define RFM_AFC 0xC400
narshu 0:b8be0a00c4f8 305
narshu 0:b8be0a00c4f8 306 #define RFM_AFC_EN 0xC401
narshu 0:b8be0a00c4f8 307 #define RFM_AFC_OE 0xC402
narshu 0:b8be0a00c4f8 308 #define RFM_AFC_FI 0xC404
narshu 0:b8be0a00c4f8 309 #define RFM_AFC_ST 0xC408
narshu 0:b8be0a00c4f8 310
narshu 0:b8be0a00c4f8 311 // Limits the value of the frequency offset register to the next values:
narshu 0:b8be0a00c4f8 312
narshu 0:b8be0a00c4f8 313 #define RFM_AFC_RANGE_LIMIT_NO 0xC400 // 0: No restriction
narshu 0:b8be0a00c4f8 314 #define RFM_AFC_RANGE_LIMIT_15_16 0xC410 // 1: +15 fres to -16 fres
narshu 0:b8be0a00c4f8 315 #define RFM_AFC_RANGE_LIMIT_7_8 0xC420 // 2: +7 fres to -8 fres
narshu 0:b8be0a00c4f8 316 #define RFM_AFC_RANGE_LIMIT_3_4 0xC430 // 3: +3 fres to -4 fres
narshu 0:b8be0a00c4f8 317
narshu 0:b8be0a00c4f8 318 // fres=2.5 kHz in 315MHz and 433MHz Bands
narshu 0:b8be0a00c4f8 319 // fres=5.0 kHz in 868MHz Band
narshu 0:b8be0a00c4f8 320 // fres=7.5 kHz in 915MHz Band
narshu 0:b8be0a00c4f8 321
narshu 0:b8be0a00c4f8 322 #define RFM_AFC_AUTO_OFF 0xC400 // 0: Auto mode off (Strobe is controlled by microcontroller)
narshu 0:b8be0a00c4f8 323 #define RFM_AFC_AUTO_ONCE 0xC440 // 1: Runs only once after each power-up
narshu 0:b8be0a00c4f8 324 #define RFM_AFC_AUTO_VDI 0xC480 // 2: Keep the foffset only during receiving(VDI=high)
narshu 0:b8be0a00c4f8 325 #define RFM_AFC_AUTO_INDEPENDENT 0xC4C0 // 3: Keep the foffset value independently trom the state of the VDI signal
narshu 0:b8be0a00c4f8 326
narshu 0:b8be0a00c4f8 327 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 328 //
narshu 0:b8be0a00c4f8 329 // 10. TX Configuration Control Command
narshu 0:b8be0a00c4f8 330 //
narshu 0:b8be0a00c4f8 331 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 332
narshu 0:b8be0a00c4f8 333 #define RFM_TX_CONTROL 0x9800
narshu 0:b8be0a00c4f8 334
narshu 0:b8be0a00c4f8 335 #define RFM_TX_CONTROL_POW_0 0x9800
narshu 0:b8be0a00c4f8 336 #define RFM_TX_CONTROL_POW_3 0x9801
narshu 0:b8be0a00c4f8 337 #define RFM_TX_CONTROL_POW_6 0x9802
narshu 0:b8be0a00c4f8 338 #define RFM_TX_CONTROL_POW_9 0x9803
narshu 0:b8be0a00c4f8 339 #define RFM_TX_CONTROL_POW_12 0x9804
narshu 0:b8be0a00c4f8 340 #define RFM_TX_CONTROL_POW_15 0x9805
narshu 0:b8be0a00c4f8 341 #define RFM_TX_CONTROL_POW_18 0x9806
narshu 0:b8be0a00c4f8 342 #define RFM_TX_CONTROL_POW_21 0x9807
narshu 0:b8be0a00c4f8 343 #define RFM_TX_CONTROL_MOD_15 0x9800
narshu 0:b8be0a00c4f8 344 #define RFM_TX_CONTROL_MOD_30 0x9810
narshu 0:b8be0a00c4f8 345 #define RFM_TX_CONTROL_MOD_45 0x9820
narshu 0:b8be0a00c4f8 346 #define RFM_TX_CONTROL_MOD_60 0x9830
narshu 0:b8be0a00c4f8 347 #define RFM_TX_CONTROL_MOD_75 0x9840
narshu 0:b8be0a00c4f8 348 #define RFM_TX_CONTROL_MOD_90 0x9850
narshu 0:b8be0a00c4f8 349 #define RFM_TX_CONTROL_MOD_105 0x9860
narshu 0:b8be0a00c4f8 350 #define RFM_TX_CONTROL_MOD_120 0x9870
narshu 0:b8be0a00c4f8 351 #define RFM_TX_CONTROL_MOD_135 0x9880
narshu 0:b8be0a00c4f8 352 #define RFM_TX_CONTROL_MOD_150 0x9890
narshu 0:b8be0a00c4f8 353 #define RFM_TX_CONTROL_MOD_165 0x98A0
narshu 0:b8be0a00c4f8 354 #define RFM_TX_CONTROL_MOD_180 0x98B0
narshu 0:b8be0a00c4f8 355 #define RFM_TX_CONTROL_MOD_195 0x98C0
narshu 0:b8be0a00c4f8 356 #define RFM_TX_CONTROL_MOD_210 0x98D0
narshu 0:b8be0a00c4f8 357 #define RFM_TX_CONTROL_MOD_225 0x98E0
narshu 0:b8be0a00c4f8 358 #define RFM_TX_CONTROL_MOD_240 0x98F0
narshu 0:b8be0a00c4f8 359 #define RFM_TX_CONTROL_MP 0x9900
narshu 0:b8be0a00c4f8 360
narshu 0:b8be0a00c4f8 361 #define RFM_TX_CONTROL_MOD(baud) (((baud)<8000) ? \
narshu 0:b8be0a00c4f8 362 RFM_TX_CONTROL_MOD_45 : \
narshu 0:b8be0a00c4f8 363 ( \
narshu 0:b8be0a00c4f8 364 ((baud)<20000) ? \
narshu 0:b8be0a00c4f8 365 RFM_TX_CONTROL_MOD_60 : \
narshu 0:b8be0a00c4f8 366 ( \
narshu 0:b8be0a00c4f8 367 ((baud)<30000) ? \
narshu 0:b8be0a00c4f8 368 RFM_TX_CONTROL_MOD_75 : \
narshu 0:b8be0a00c4f8 369 ( \
narshu 0:b8be0a00c4f8 370 ((baud)<40000) ? \
narshu 0:b8be0a00c4f8 371 RFM_TX_CONTROL_MOD_90 : \
narshu 0:b8be0a00c4f8 372 RFM_TX_CONTROL_MOD_120 \
narshu 0:b8be0a00c4f8 373 ) \
narshu 0:b8be0a00c4f8 374 ) \
narshu 0:b8be0a00c4f8 375 ))
narshu 0:b8be0a00c4f8 376
narshu 0:b8be0a00c4f8 377 /////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 378 //
narshu 0:b8be0a00c4f8 379 // 11. Transmitter Register Write Command
narshu 0:b8be0a00c4f8 380 //
narshu 0:b8be0a00c4f8 381 /////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 382
narshu 0:b8be0a00c4f8 383 //#define RFM_WRITE(byte) RFM_SPI_16(0xB800 | ((byte) & 0xFF))
narshu 0:b8be0a00c4f8 384 #define RFM_WRITE(byte) RFM_SPI_16(0xB800 | (byte) )
narshu 0:b8be0a00c4f8 385
narshu 0:b8be0a00c4f8 386 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 387 //
narshu 0:b8be0a00c4f8 388 // 12. Wake-up Timer Command
narshu 0:b8be0a00c4f8 389 //
narshu 0:b8be0a00c4f8 390 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 391
narshu 0:b8be0a00c4f8 392 #define RFM_WAKEUP_TIMER 0xE000
narshu 0:b8be0a00c4f8 393 #define RFM_WAKEUP_SET(time) RFM_SPI_16(RFM_WAKEUP_TIMER | (time))
narshu 0:b8be0a00c4f8 394
narshu 0:b8be0a00c4f8 395 #define RFM_WAKEUP_480s (RFM_WAKEUP_TIMER |(11 << 8)| 234)
narshu 0:b8be0a00c4f8 396 #define RFM_WAKEUP_240s (RFM_WAKEUP_TIMER |(10 << 8)| 234)
narshu 0:b8be0a00c4f8 397 #define RFM_WAKEUP_120s (RFM_WAKEUP_TIMER |(9 << 8)| 234)
narshu 0:b8be0a00c4f8 398 #define RFM_WAKEUP_119s (RFM_WAKEUP_TIMER |(9 << 8)| 232)
narshu 0:b8be0a00c4f8 399
narshu 0:b8be0a00c4f8 400 #define RFM_WAKEUP_60s (RFM_WAKEUP_TIMER |(8 << 8) | 235)
narshu 0:b8be0a00c4f8 401 #define RFM_WAKEUP_59s (RFM_WAKEUP_TIMER |(8 << 8) | 230)
narshu 0:b8be0a00c4f8 402
narshu 0:b8be0a00c4f8 403 #define RFM_WAKEUP_30s (RFM_WAKEUP_TIMER |(7 << 8) | 235)
narshu 0:b8be0a00c4f8 404 #define RFM_WAKEUP_29s (RFM_WAKEUP_TIMER |(7 << 8) | 227)
narshu 0:b8be0a00c4f8 405
narshu 0:b8be0a00c4f8 406 #define RFM_WAKEUP_8s (RFM_WAKEUP_TIMER |(5 << 8) | 250)
narshu 0:b8be0a00c4f8 407 #define RFM_WAKEUP_7s (RFM_WAKEUP_TIMER |(5 << 8) | 219)
narshu 0:b8be0a00c4f8 408 #define RFM_WAKEUP_6s (RFM_WAKEUP_TIMER |(6 << 8) | 94)
narshu 0:b8be0a00c4f8 409 #define RFM_WAKEUP_5s (RFM_WAKEUP_TIMER |(5 << 8) | 156)
narshu 0:b8be0a00c4f8 410 #define RFM_WAKEUP_4s (RFM_WAKEUP_TIMER |(5 << 8) | 125)
narshu 0:b8be0a00c4f8 411 #define RFM_WAKEUP_1s (RFM_WAKEUP_TIMER |(2 << 8) | 250)
narshu 0:b8be0a00c4f8 412 #define RFM_WAKEUP_900ms (RFM_WAKEUP_TIMER |(2 << 8) | 225)
narshu 0:b8be0a00c4f8 413 #define RFM_WAKEUP_800ms (RFM_WAKEUP_TIMER |(2 << 8) | 200)
narshu 0:b8be0a00c4f8 414 #define RFM_WAKEUP_700ms (RFM_WAKEUP_TIMER |(2 << 8) | 175)
narshu 0:b8be0a00c4f8 415 #define RFM_WAKEUP_600ms (RFM_WAKEUP_TIMER |(2 << 8) | 150)
narshu 0:b8be0a00c4f8 416 #define RFM_WAKEUP_500ms (RFM_WAKEUP_TIMER |(2 << 8) | 125)
narshu 0:b8be0a00c4f8 417 #define RFM_WAKEUP_400ms (RFM_WAKEUP_TIMER |(2 << 8) | 100)
narshu 0:b8be0a00c4f8 418 #define RFM_WAKEUP_300ms (RFM_WAKEUP_TIMER |(2 << 8) | 75)
narshu 0:b8be0a00c4f8 419 #define RFM_WAKEUP_200ms (RFM_WAKEUP_TIMER |(2 << 8) | 50)
narshu 0:b8be0a00c4f8 420 #define RFM_WAKEUP_100ms (RFM_WAKEUP_TIMER |(2 << 8) | 25)
narshu 0:b8be0a00c4f8 421
narshu 0:b8be0a00c4f8 422 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 423 //
narshu 0:b8be0a00c4f8 424 // 13. Low Duty-Cycle Command
narshu 0:b8be0a00c4f8 425 //
narshu 0:b8be0a00c4f8 426 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 427
narshu 0:b8be0a00c4f8 428 #define RFM_LOW_DUTY_CYCLE 0xC800
narshu 0:b8be0a00c4f8 429
narshu 0:b8be0a00c4f8 430 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 431 //
narshu 0:b8be0a00c4f8 432 // 14. Low Battery Detector Command
narshu 0:b8be0a00c4f8 433 //
narshu 0:b8be0a00c4f8 434 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 435
narshu 0:b8be0a00c4f8 436 #define RFM_LOW_BATT_DETECT 0xC000
narshu 0:b8be0a00c4f8 437 #define RFM_LOW_BATT_DETECT_D_1MHZ 0xC000
narshu 0:b8be0a00c4f8 438 #define RFM_LOW_BATT_DETECT_D_1_25MHZ 0xC020
narshu 0:b8be0a00c4f8 439 #define RFM_LOW_BATT_DETECT_D_1_66MHZ 0xC040
narshu 0:b8be0a00c4f8 440 #define RFM_LOW_BATT_DETECT_D_2MHZ 0xC060
narshu 0:b8be0a00c4f8 441 #define RFM_LOW_BATT_DETECT_D_2_5MHZ 0xC080
narshu 0:b8be0a00c4f8 442 #define RFM_LOW_BATT_DETECT_D_3_33MHZ 0xC0A0
narshu 0:b8be0a00c4f8 443 #define RFM_LOW_BATT_DETECT_D_5MHZ 0xC0C0
narshu 0:b8be0a00c4f8 444 #define RFM_LOW_BATT_DETECT_D_10MHZ 0xC0E0
narshu 0:b8be0a00c4f8 445
narshu 0:b8be0a00c4f8 446 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 447 //
narshu 0:b8be0a00c4f8 448 // 15. Status Read Command
narshu 0:b8be0a00c4f8 449 //
narshu 0:b8be0a00c4f8 450 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 451
narshu 0:b8be0a00c4f8 452 #define RFM_READ_STATUS() RFM_SPI_16(0x0000)
narshu 0:b8be0a00c4f8 453 #define RFM_READ_STATUS_FFIT() SPI_1 (0x00)
narshu 0:b8be0a00c4f8 454 #define RFM_READ_STATUS_RGIT RFM_READ_STATUS_FFIT
narshu 0:b8be0a00c4f8 455
narshu 0:b8be0a00c4f8 456 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 457
narshu 0:b8be0a00c4f8 458 // RFM air protocol flags:
narshu 0:b8be0a00c4f8 459
narshu 0:b8be0a00c4f8 460 #define RFMPROTO_FLAGS_BITASK_PACKETTYPE 0b11000000 //!< the uppermost 2 bits of the flags field encode the packettype
narshu 0:b8be0a00c4f8 461 #define RFMPROTO_FLAGS_PACKETTYPE_BROADCAST 0b00000000 //!< broadcast packettype (message from hr20, protocol; step 1)
narshu 0:b8be0a00c4f8 462 #define RFMPROTO_FLAGS_PACKETTYPE_COMMAND 0b01000000 //!< command packettype (message to hr20, protocol; step 2)
narshu 0:b8be0a00c4f8 463 #define RFMPROTO_FLAGS_PACKETTYPE_REPLY 0b10000000 //!< reply packettype (message from hr20, protocol; step 3)
narshu 0:b8be0a00c4f8 464 #define RFMPROTO_FLAGS_PACKETTYPE_SPECIAL 0b11000000 //!< currently unused packettype
narshu 0:b8be0a00c4f8 465
narshu 0:b8be0a00c4f8 466 #define RFMPROTO_FLAGS_BITASK_DEVICETYPE 0b00011111 //!< the lowermost 5 bytes denote the device type. this way other sensors and actors may coexist
narshu 0:b8be0a00c4f8 467 #define RFMPROTO_FLAGS_DEVICETYPE_OPENHR20 0b00010100 //!< topen HR20 device type. 10100 is for decimal 20
narshu 0:b8be0a00c4f8 468
narshu 0:b8be0a00c4f8 469 #define RFMPROTO_IS_PACKETTYPE_BROADCAST(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_BROADCAST == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) )
narshu 0:b8be0a00c4f8 470 #define RFMPROTO_IS_PACKETTYPE_COMMAND(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_COMMAND == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) )
narshu 0:b8be0a00c4f8 471 #define RFMPROTO_IS_PACKETTYPE_REPLY(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_REPLY == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) )
narshu 0:b8be0a00c4f8 472 #define RFMPROTO_IS_PACKETTYPE_SPECIAL(FLAGS) ( RFMPROTO_FLAGS_PACKETTYPE_SPECIAL == ((FLAGS) & RFMPROTO_FLAGS_BITASK_PACKETTYPE) )
narshu 0:b8be0a00c4f8 473 #define RFMPROTO_IS_DEVICETYPE_OPENHR20(FLAGS) ( RFMPROTO_FLAGS_DEVICETYPE_OPENHR20 == ((FLAGS) & RFMPROTO_FLAGS_BITASK_DEVICETYPE) )
narshu 0:b8be0a00c4f8 474
narshu 0:b8be0a00c4f8 475 ///////////////////////////////////////////////////////////////////////////////
narshu 0:b8be0a00c4f8 476
narshu 0:b8be0a00c4f8 477 #endif