Sertel_Srinath Gopalan / USB_SERTEL_LOG

Soundharrajan

Fork of mbed by mbed official

TARGET_NUCLEO_F030R8/stm32f0xx_crs.h@77:869cf507173a, 2014-02-14 (annotated)

Committer:
emilmont
Date:
Fri Feb 14 14:36:43 2014 +0000
Revision:
77:869cf507173a
Child:
81:7d30d6019079
Release 77 of the mbed library



Main changes:

* Add target NUCLEO_F030R8

* Add target NUCLEO_F401RE

* Add target NUCLEO_F103RB

* Add target NUCLEO_L152RE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f0xx_crs.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V1.3.0
emilmont 77:869cf507173a 6 * @date 16-January-2014
emilmont 77:869cf507173a 7 * @brief This file contains all the functions prototypes for the CRS firmware
emilmont 77:869cf507173a 8 * library, applicable only for STM32F042 and STM32F072 devices.
emilmont 77:869cf507173a 9 ******************************************************************************
emilmont 77:869cf507173a 10 * @attention
emilmont 77:869cf507173a 11 *
emilmont 77:869cf507173a 12 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 13 *
emilmont 77:869cf507173a 14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
emilmont 77:869cf507173a 15 * You may not use this file except in compliance with the License.
emilmont 77:869cf507173a 16 * You may obtain a copy of the License at:
emilmont 77:869cf507173a 17 *
emilmont 77:869cf507173a 18 * http://www.st.com/software_license_agreement_liberty_v2
emilmont 77:869cf507173a 19 *
emilmont 77:869cf507173a 20 * Unless required by applicable law or agreed to in writing, software
emilmont 77:869cf507173a 21 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 77:869cf507173a 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 77:869cf507173a 23 * See the License for the specific language governing permissions and
emilmont 77:869cf507173a 24 * limitations under the License.
emilmont 77:869cf507173a 25 *
emilmont 77:869cf507173a 26 ******************************************************************************
emilmont 77:869cf507173a 27 */
emilmont 77:869cf507173a 28
emilmont 77:869cf507173a 29 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 30 #ifndef __STM32F0XX_CRS_H
emilmont 77:869cf507173a 31 #define __STM32F0XX_CRS_H
emilmont 77:869cf507173a 32
emilmont 77:869cf507173a 33 #ifdef __cplusplus
emilmont 77:869cf507173a 34 extern "C" {
emilmont 77:869cf507173a 35 #endif
emilmont 77:869cf507173a 36
emilmont 77:869cf507173a 37 /*!< Includes ----------------------------------------------------------------*/
emilmont 77:869cf507173a 38 #include "stm32f0xx.h"
emilmont 77:869cf507173a 39
emilmont 77:869cf507173a 40 /** @addtogroup STM32F0xx_StdPeriph_Driver
emilmont 77:869cf507173a 41 * @{
emilmont 77:869cf507173a 42 */
emilmont 77:869cf507173a 43
emilmont 77:869cf507173a 44 /** @addtogroup CRS
emilmont 77:869cf507173a 45 * @{
emilmont 77:869cf507173a 46 */
emilmont 77:869cf507173a 47
emilmont 77:869cf507173a 48 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 49 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 50
emilmont 77:869cf507173a 51 /** @defgroup CRS_Interrupt_Sources
emilmont 77:869cf507173a 52 * @{
emilmont 77:869cf507173a 53 */
emilmont 77:869cf507173a 54 #define CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
emilmont 77:869cf507173a 55 #define CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
emilmont 77:869cf507173a 56 #define CRS_IT_ERR CRS_ISR_ERRF /*!< error */
emilmont 77:869cf507173a 57 #define CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
emilmont 77:869cf507173a 58 #define CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
emilmont 77:869cf507173a 59 #define CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
emilmont 77:869cf507173a 60 #define CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
emilmont 77:869cf507173a 61
emilmont 77:869cf507173a 62 #define IS_CRS_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \
emilmont 77:869cf507173a 63 ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC))
emilmont 77:869cf507173a 64
emilmont 77:869cf507173a 65 #define IS_CRS_GET_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \
emilmont 77:869cf507173a 66 ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC) || \
emilmont 77:869cf507173a 67 ((IT) == CRS_IT_TRIMOVF) || ((IT) == CRS_IT_SYNCERR) || \
emilmont 77:869cf507173a 68 ((IT) == CRS_IT_SYNCMISS))
emilmont 77:869cf507173a 69
emilmont 77:869cf507173a 70 #define IS_CRS_CLEAR_IT(IT) ((IT) != 0x00)
emilmont 77:869cf507173a 71
emilmont 77:869cf507173a 72 /**
emilmont 77:869cf507173a 73 * @}
emilmont 77:869cf507173a 74 */
emilmont 77:869cf507173a 75
emilmont 77:869cf507173a 76 /** @defgroup CRS_Flags
emilmont 77:869cf507173a 77 * @{
emilmont 77:869cf507173a 78 */
emilmont 77:869cf507173a 79 #define CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
emilmont 77:869cf507173a 80 #define CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
emilmont 77:869cf507173a 81 #define CRS_FLAG_ERR CRS_ISR_ERRF /*!< error */
emilmont 77:869cf507173a 82 #define CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
emilmont 77:869cf507173a 83 #define CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
emilmont 77:869cf507173a 84 #define CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
emilmont 77:869cf507173a 85 #define CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
emilmont 77:869cf507173a 86
emilmont 77:869cf507173a 87 #define IS_CRS_FLAG(FLAG) (((FLAG) == CRS_FLAG_SYNCOK) || ((FLAG) == CRS_FLAG_SYNCWARN) || \
emilmont 77:869cf507173a 88 ((FLAG) == CRS_FLAG_ERR) || ((FLAG) == CRS_FLAG_ESYNC) || \
emilmont 77:869cf507173a 89 ((FLAG) == CRS_FLAG_TRIMOVF) || ((FLAG) == CRS_FLAG_SYNCERR) || \
emilmont 77:869cf507173a 90 ((FLAG) == CRS_FLAG_SYNCMISS))
emilmont 77:869cf507173a 91
emilmont 77:869cf507173a 92 /**
emilmont 77:869cf507173a 93 * @}
emilmont 77:869cf507173a 94 */
emilmont 77:869cf507173a 95
emilmont 77:869cf507173a 96 /** @defgroup CRS_Synchro_Source
emilmont 77:869cf507173a 97 * @{
emilmont 77:869cf507173a 98 */
emilmont 77:869cf507173a 99 #define CRS_SYNCSource_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */
emilmont 77:869cf507173a 100 #define CRS_SYNCSource_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
emilmont 77:869cf507173a 101 #define CRS_SYNCSource_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF */
emilmont 77:869cf507173a 102
emilmont 77:869cf507173a 103 #define IS_CRS_SYNC_SOURCE(SOURCE) (((SOURCE) == CRS_SYNCSource_GPIO) || \
emilmont 77:869cf507173a 104 ((SOURCE) == CRS_SYNCSource_LSE) ||\
emilmont 77:869cf507173a 105 ((SOURCE) == CRS_SYNCSource_USB))
emilmont 77:869cf507173a 106 /**
emilmont 77:869cf507173a 107 * @}
emilmont 77:869cf507173a 108 */
emilmont 77:869cf507173a 109
emilmont 77:869cf507173a 110 /** @defgroup CRS_SynchroDivider
emilmont 77:869cf507173a 111 * @{
emilmont 77:869cf507173a 112 */
emilmont 77:869cf507173a 113 #define CRS_SYNC_Div1 ((uint32_t)0x00) /*!< Synchro Signal not divided */
emilmont 77:869cf507173a 114 #define CRS_SYNC_Div2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
emilmont 77:869cf507173a 115 #define CRS_SYNC_Div4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
emilmont 77:869cf507173a 116 #define CRS_SYNC_Div8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
emilmont 77:869cf507173a 117 #define CRS_SYNC_Div16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
emilmont 77:869cf507173a 118 #define CRS_SYNC_Div32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
emilmont 77:869cf507173a 119 #define CRS_SYNC_Div64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
emilmont 77:869cf507173a 120 #define CRS_SYNC_Div128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
emilmont 77:869cf507173a 121
emilmont 77:869cf507173a 122 #define IS_CRS_SYNC_DIV(DIV) (((DIV) == CRS_SYNC_Div1) || ((DIV) == CRS_SYNC_Div2) ||\
emilmont 77:869cf507173a 123 ((DIV) == CRS_SYNC_Div4) || ((DIV) == CRS_SYNC_Div8) || \
emilmont 77:869cf507173a 124 ((DIV) == CRS_SYNC_Div16) || ((DIV) == CRS_SYNC_Div32) || \
emilmont 77:869cf507173a 125 ((DIV) == CRS_SYNC_Div64) || ((DIV) == CRS_SYNC_Div128))
emilmont 77:869cf507173a 126 /**
emilmont 77:869cf507173a 127 * @}
emilmont 77:869cf507173a 128 */
emilmont 77:869cf507173a 129
emilmont 77:869cf507173a 130 /** @defgroup CRS_SynchroPolarity
emilmont 77:869cf507173a 131 * @{
emilmont 77:869cf507173a 132 */
emilmont 77:869cf507173a 133 #define CRS_SYNCPolarity_Rising ((uint32_t)0x00) /*!< Synchro Active on rising edge */
emilmont 77:869cf507173a 134 #define CRS_SYNCPolarity_Falling CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
emilmont 77:869cf507173a 135
emilmont 77:869cf507173a 136 #define IS_CRS_SYNC_POLARITY(POLARITY) (((POLARITY) == CRS_SYNCPolarity_Rising) || \
emilmont 77:869cf507173a 137 ((POLARITY) == CRS_SYNCPolarity_Falling))
emilmont 77:869cf507173a 138 /**
emilmont 77:869cf507173a 139 * @}
emilmont 77:869cf507173a 140 */
emilmont 77:869cf507173a 141
emilmont 77:869cf507173a 142
emilmont 77:869cf507173a 143
emilmont 77:869cf507173a 144 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 145 /* Exported functions ------------------------------------------------------- */
emilmont 77:869cf507173a 146 /* Configuration of the CRS **********************************/
emilmont 77:869cf507173a 147 void CRS_DeInit(void);
emilmont 77:869cf507173a 148 void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue);
emilmont 77:869cf507173a 149 void CRS_FrequencyErrorCounterCmd(FunctionalState NewState);
emilmont 77:869cf507173a 150 void CRS_AutomaticCalibrationCmd(FunctionalState NewState);
emilmont 77:869cf507173a 151 void CRS_SoftwareSynchronizationGenerate(void);
emilmont 77:869cf507173a 152 void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue);
emilmont 77:869cf507173a 153 void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue);
emilmont 77:869cf507173a 154 void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler);
emilmont 77:869cf507173a 155 void CRS_SynchronizationSourceConfig(uint32_t CRS_Source);
emilmont 77:869cf507173a 156 void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity);
emilmont 77:869cf507173a 157 uint32_t CRS_GetReloadValue(void);
emilmont 77:869cf507173a 158 uint32_t CRS_GetHSI48CalibrationValue(void);
emilmont 77:869cf507173a 159 uint32_t CRS_GetFrequencyErrorValue(void);
emilmont 77:869cf507173a 160 uint32_t CRS_GetFrequencyErrorDirection(void);
emilmont 77:869cf507173a 161
emilmont 77:869cf507173a 162 /* Interrupts and flags management functions **********************************/
emilmont 77:869cf507173a 163 void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState);
emilmont 77:869cf507173a 164 FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG);
emilmont 77:869cf507173a 165 void CRS_ClearFlag(uint32_t CRS_FLAG);
emilmont 77:869cf507173a 166 ITStatus CRS_GetITStatus(uint32_t CRS_IT);
emilmont 77:869cf507173a 167 void CRS_ClearITPendingBit(uint32_t CRS_IT);
emilmont 77:869cf507173a 168
emilmont 77:869cf507173a 169 #ifdef __cplusplus
emilmont 77:869cf507173a 170 }
emilmont 77:869cf507173a 171 #endif
emilmont 77:869cf507173a 172
emilmont 77:869cf507173a 173 #endif /* __STM32F0XX_CRS_H */
emilmont 77:869cf507173a 174
emilmont 77:869cf507173a 175 /**
emilmont 77:869cf507173a 176 * @}
emilmont 77:869cf507173a 177 */
emilmont 77:869cf507173a 178
emilmont 77:869cf507173a 179 /**
emilmont 77:869cf507173a 180 * @}
emilmont 77:869cf507173a 181 */
emilmont 77:869cf507173a 182
emilmont 77:869cf507173a 183 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/