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TARGET_NUCLEO_F030R8/stm32f0xx_spi.h@78:ed8466a608b4, 2014-02-18 (annotated)
- Committer:
- emilmont
- Date:
- Tue Feb 18 15:02:39 2014 +0000
- Revision:
- 78:ed8466a608b4
- Parent:
- 77:869cf507173a
- Child:
- 81:7d30d6019079
Add KL05Z Target
Fix LPC11XX InterruptIn
Fix NUCLEO boards us_ticker
Fix NUCLEO_L152RE AnalogOut
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 77:869cf507173a | 1 | /** |
| emilmont | 77:869cf507173a | 2 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 3 | * @file stm32f0xx_spi.h |
| emilmont | 77:869cf507173a | 4 | * @author MCD Application Team |
| emilmont | 77:869cf507173a | 5 | * @version V1.3.0 |
| emilmont | 77:869cf507173a | 6 | * @date 16-January-2014 |
| emilmont | 77:869cf507173a | 7 | * @brief This file contains all the functions prototypes for the SPI |
| emilmont | 77:869cf507173a | 8 | * firmware library. |
| emilmont | 77:869cf507173a | 9 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 10 | * @attention |
| emilmont | 77:869cf507173a | 11 | * |
| emilmont | 77:869cf507173a | 12 | * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> |
| emilmont | 77:869cf507173a | 13 | * |
| emilmont | 77:869cf507173a | 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); |
| emilmont | 77:869cf507173a | 15 | * You may not use this file except in compliance with the License. |
| emilmont | 77:869cf507173a | 16 | * You may obtain a copy of the License at: |
| emilmont | 77:869cf507173a | 17 | * |
| emilmont | 77:869cf507173a | 18 | * http://www.st.com/software_license_agreement_liberty_v2 |
| emilmont | 77:869cf507173a | 19 | * |
| emilmont | 77:869cf507173a | 20 | * Unless required by applicable law or agreed to in writing, software |
| emilmont | 77:869cf507173a | 21 | * distributed under the License is distributed on an "AS IS" BASIS, |
| emilmont | 77:869cf507173a | 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| emilmont | 77:869cf507173a | 23 | * See the License for the specific language governing permissions and |
| emilmont | 77:869cf507173a | 24 | * limitations under the License. |
| emilmont | 77:869cf507173a | 25 | * |
| emilmont | 77:869cf507173a | 26 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 27 | */ |
| emilmont | 77:869cf507173a | 28 | |
| emilmont | 77:869cf507173a | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| emilmont | 77:869cf507173a | 30 | #ifndef __STM32F0XX_SPI_H |
| emilmont | 77:869cf507173a | 31 | #define __STM32F0XX_SPI_H |
| emilmont | 77:869cf507173a | 32 | |
| emilmont | 77:869cf507173a | 33 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 34 | extern "C" { |
| emilmont | 77:869cf507173a | 35 | #endif |
| emilmont | 77:869cf507173a | 36 | |
| emilmont | 77:869cf507173a | 37 | /* Includes ------------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 38 | #include "stm32f0xx.h" |
| emilmont | 77:869cf507173a | 39 | |
| emilmont | 77:869cf507173a | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver |
| emilmont | 77:869cf507173a | 41 | * @{ |
| emilmont | 77:869cf507173a | 42 | */ |
| emilmont | 77:869cf507173a | 43 | |
| emilmont | 77:869cf507173a | 44 | /** @addtogroup SPI |
| emilmont | 77:869cf507173a | 45 | * @{ |
| emilmont | 77:869cf507173a | 46 | */ |
| emilmont | 77:869cf507173a | 47 | |
| emilmont | 77:869cf507173a | 48 | /* Exported types ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 49 | |
| emilmont | 77:869cf507173a | 50 | /** |
| emilmont | 77:869cf507173a | 51 | * @brief SPI Init structure definition |
| emilmont | 77:869cf507173a | 52 | */ |
| emilmont | 77:869cf507173a | 53 | |
| emilmont | 77:869cf507173a | 54 | typedef struct |
| emilmont | 77:869cf507173a | 55 | { |
| emilmont | 77:869cf507173a | 56 | uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. |
| emilmont | 77:869cf507173a | 57 | This parameter can be a value of @ref SPI_data_direction */ |
| emilmont | 77:869cf507173a | 58 | |
| emilmont | 77:869cf507173a | 59 | uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave). |
| emilmont | 77:869cf507173a | 60 | This parameter can be a value of @ref SPI_mode */ |
| emilmont | 77:869cf507173a | 61 | |
| emilmont | 77:869cf507173a | 62 | uint16_t SPI_DataSize; /*!< Specifies the SPI data size. |
| emilmont | 77:869cf507173a | 63 | This parameter can be a value of @ref SPI_data_size */ |
| emilmont | 77:869cf507173a | 64 | |
| emilmont | 77:869cf507173a | 65 | uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. |
| emilmont | 77:869cf507173a | 66 | This parameter can be a value of @ref SPI_Clock_Polarity */ |
| emilmont | 77:869cf507173a | 67 | |
| emilmont | 77:869cf507173a | 68 | uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. |
| emilmont | 77:869cf507173a | 69 | This parameter can be a value of @ref SPI_Clock_Phase */ |
| emilmont | 77:869cf507173a | 70 | |
| emilmont | 77:869cf507173a | 71 | uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by |
| emilmont | 77:869cf507173a | 72 | hardware (NSS pin) or by software using the SSI bit. |
| emilmont | 77:869cf507173a | 73 | This parameter can be a value of @ref SPI_Slave_Select_management */ |
| emilmont | 77:869cf507173a | 74 | |
| emilmont | 77:869cf507173a | 75 | uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be |
| emilmont | 77:869cf507173a | 76 | used to configure the transmit and receive SCK clock. |
| emilmont | 77:869cf507173a | 77 | This parameter can be a value of @ref SPI_BaudRate_Prescaler |
| emilmont | 77:869cf507173a | 78 | @note The communication clock is derived from the master |
| emilmont | 77:869cf507173a | 79 | clock. The slave clock does not need to be set. */ |
| emilmont | 77:869cf507173a | 80 | |
| emilmont | 77:869cf507173a | 81 | uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. |
| emilmont | 77:869cf507173a | 82 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
| emilmont | 77:869cf507173a | 83 | |
| emilmont | 77:869cf507173a | 84 | uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ |
| emilmont | 77:869cf507173a | 85 | }SPI_InitTypeDef; |
| emilmont | 77:869cf507173a | 86 | |
| emilmont | 77:869cf507173a | 87 | |
| emilmont | 77:869cf507173a | 88 | /** |
| emilmont | 77:869cf507173a | 89 | * @brief I2S Init structure definition |
| emilmont | 77:869cf507173a | 90 | * @note These parameters are not available for STM32F030 devices. |
| emilmont | 77:869cf507173a | 91 | */ |
| emilmont | 77:869cf507173a | 92 | |
| emilmont | 77:869cf507173a | 93 | typedef struct |
| emilmont | 77:869cf507173a | 94 | { |
| emilmont | 77:869cf507173a | 95 | uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. |
| emilmont | 77:869cf507173a | 96 | This parameter can be a value of @ref SPI_I2S_Mode */ |
| emilmont | 77:869cf507173a | 97 | |
| emilmont | 77:869cf507173a | 98 | uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. |
| emilmont | 77:869cf507173a | 99 | This parameter can be a value of @ref SPI_I2S_Standard */ |
| emilmont | 77:869cf507173a | 100 | |
| emilmont | 77:869cf507173a | 101 | uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. |
| emilmont | 77:869cf507173a | 102 | This parameter can be a value of @ref SPI_I2S_Data_Format */ |
| emilmont | 77:869cf507173a | 103 | |
| emilmont | 77:869cf507173a | 104 | uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. |
| emilmont | 77:869cf507173a | 105 | This parameter can be a value of @ref SPI_I2S_MCLK_Output */ |
| emilmont | 77:869cf507173a | 106 | |
| emilmont | 77:869cf507173a | 107 | uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. |
| emilmont | 77:869cf507173a | 108 | This parameter can be a value of @ref SPI_I2S_Audio_Frequency */ |
| emilmont | 77:869cf507173a | 109 | |
| emilmont | 77:869cf507173a | 110 | uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. |
| emilmont | 77:869cf507173a | 111 | This parameter can be a value of @ref SPI_I2S_Clock_Polarity */ |
| emilmont | 77:869cf507173a | 112 | }I2S_InitTypeDef; |
| emilmont | 77:869cf507173a | 113 | |
| emilmont | 77:869cf507173a | 114 | /* Exported constants --------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 115 | |
| emilmont | 77:869cf507173a | 116 | /** @defgroup SPI_Exported_Constants |
| emilmont | 77:869cf507173a | 117 | * @{ |
| emilmont | 77:869cf507173a | 118 | */ |
| emilmont | 77:869cf507173a | 119 | |
| emilmont | 77:869cf507173a | 120 | #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ |
| emilmont | 77:869cf507173a | 121 | ((PERIPH) == SPI2)) |
| emilmont | 77:869cf507173a | 122 | |
| emilmont | 77:869cf507173a | 123 | #define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1)) |
| emilmont | 77:869cf507173a | 124 | |
| emilmont | 77:869cf507173a | 125 | /** @defgroup SPI_data_direction |
| emilmont | 77:869cf507173a | 126 | * @{ |
| emilmont | 77:869cf507173a | 127 | */ |
| emilmont | 77:869cf507173a | 128 | |
| emilmont | 77:869cf507173a | 129 | #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 130 | #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) |
| emilmont | 77:869cf507173a | 131 | #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) |
| emilmont | 77:869cf507173a | 132 | #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) |
| emilmont | 77:869cf507173a | 133 | #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ |
| emilmont | 77:869cf507173a | 134 | ((MODE) == SPI_Direction_2Lines_RxOnly) || \ |
| emilmont | 77:869cf507173a | 135 | ((MODE) == SPI_Direction_1Line_Rx) || \ |
| emilmont | 77:869cf507173a | 136 | ((MODE) == SPI_Direction_1Line_Tx)) |
| emilmont | 77:869cf507173a | 137 | /** |
| emilmont | 77:869cf507173a | 138 | * @} |
| emilmont | 77:869cf507173a | 139 | */ |
| emilmont | 77:869cf507173a | 140 | |
| emilmont | 77:869cf507173a | 141 | /** @defgroup SPI_mode |
| emilmont | 77:869cf507173a | 142 | * @{ |
| emilmont | 77:869cf507173a | 143 | */ |
| emilmont | 77:869cf507173a | 144 | |
| emilmont | 77:869cf507173a | 145 | #define SPI_Mode_Master ((uint16_t)0x0104) |
| emilmont | 77:869cf507173a | 146 | #define SPI_Mode_Slave ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 147 | #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ |
| emilmont | 77:869cf507173a | 148 | ((MODE) == SPI_Mode_Slave)) |
| emilmont | 77:869cf507173a | 149 | /** |
| emilmont | 77:869cf507173a | 150 | * @} |
| emilmont | 77:869cf507173a | 151 | */ |
| emilmont | 77:869cf507173a | 152 | |
| emilmont | 77:869cf507173a | 153 | /** @defgroup SPI_data_size |
| emilmont | 77:869cf507173a | 154 | * @{ |
| emilmont | 77:869cf507173a | 155 | */ |
| emilmont | 77:869cf507173a | 156 | |
| emilmont | 77:869cf507173a | 157 | #define SPI_DataSize_4b ((uint16_t)0x0300) |
| emilmont | 77:869cf507173a | 158 | #define SPI_DataSize_5b ((uint16_t)0x0400) |
| emilmont | 77:869cf507173a | 159 | #define SPI_DataSize_6b ((uint16_t)0x0500) |
| emilmont | 77:869cf507173a | 160 | #define SPI_DataSize_7b ((uint16_t)0x0600) |
| emilmont | 77:869cf507173a | 161 | #define SPI_DataSize_8b ((uint16_t)0x0700) |
| emilmont | 77:869cf507173a | 162 | #define SPI_DataSize_9b ((uint16_t)0x0800) |
| emilmont | 77:869cf507173a | 163 | #define SPI_DataSize_10b ((uint16_t)0x0900) |
| emilmont | 77:869cf507173a | 164 | #define SPI_DataSize_11b ((uint16_t)0x0A00) |
| emilmont | 77:869cf507173a | 165 | #define SPI_DataSize_12b ((uint16_t)0x0B00) |
| emilmont | 77:869cf507173a | 166 | #define SPI_DataSize_13b ((uint16_t)0x0C00) |
| emilmont | 77:869cf507173a | 167 | #define SPI_DataSize_14b ((uint16_t)0x0D00) |
| emilmont | 77:869cf507173a | 168 | #define SPI_DataSize_15b ((uint16_t)0x0E00) |
| emilmont | 77:869cf507173a | 169 | #define SPI_DataSize_16b ((uint16_t)0x0F00) |
| emilmont | 77:869cf507173a | 170 | #define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \ |
| emilmont | 77:869cf507173a | 171 | ((SIZE) == SPI_DataSize_5b) || \ |
| emilmont | 77:869cf507173a | 172 | ((SIZE) == SPI_DataSize_6b) || \ |
| emilmont | 77:869cf507173a | 173 | ((SIZE) == SPI_DataSize_7b) || \ |
| emilmont | 77:869cf507173a | 174 | ((SIZE) == SPI_DataSize_8b) || \ |
| emilmont | 77:869cf507173a | 175 | ((SIZE) == SPI_DataSize_9b) || \ |
| emilmont | 77:869cf507173a | 176 | ((SIZE) == SPI_DataSize_10b) || \ |
| emilmont | 77:869cf507173a | 177 | ((SIZE) == SPI_DataSize_11b) || \ |
| emilmont | 77:869cf507173a | 178 | ((SIZE) == SPI_DataSize_12b) || \ |
| emilmont | 77:869cf507173a | 179 | ((SIZE) == SPI_DataSize_13b) || \ |
| emilmont | 77:869cf507173a | 180 | ((SIZE) == SPI_DataSize_14b) || \ |
| emilmont | 77:869cf507173a | 181 | ((SIZE) == SPI_DataSize_15b) || \ |
| emilmont | 77:869cf507173a | 182 | ((SIZE) == SPI_DataSize_16b)) |
| emilmont | 77:869cf507173a | 183 | /** |
| emilmont | 77:869cf507173a | 184 | * @} |
| emilmont | 77:869cf507173a | 185 | */ |
| emilmont | 77:869cf507173a | 186 | |
| emilmont | 77:869cf507173a | 187 | /** @defgroup SPI_CRC_length |
| emilmont | 77:869cf507173a | 188 | * @{ |
| emilmont | 77:869cf507173a | 189 | */ |
| emilmont | 77:869cf507173a | 190 | |
| emilmont | 77:869cf507173a | 191 | #define SPI_CRCLength_8b ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 192 | #define SPI_CRCLength_16b SPI_CR1_CRCL |
| emilmont | 77:869cf507173a | 193 | #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \ |
| emilmont | 77:869cf507173a | 194 | ((LENGTH) == SPI_CRCLength_16b)) |
| emilmont | 77:869cf507173a | 195 | /** |
| emilmont | 77:869cf507173a | 196 | * @} |
| emilmont | 77:869cf507173a | 197 | */ |
| emilmont | 77:869cf507173a | 198 | |
| emilmont | 77:869cf507173a | 199 | /** @defgroup SPI_Clock_Polarity |
| emilmont | 77:869cf507173a | 200 | * @{ |
| emilmont | 77:869cf507173a | 201 | */ |
| emilmont | 77:869cf507173a | 202 | |
| emilmont | 77:869cf507173a | 203 | #define SPI_CPOL_Low ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 204 | #define SPI_CPOL_High SPI_CR1_CPOL |
| emilmont | 77:869cf507173a | 205 | #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ |
| emilmont | 77:869cf507173a | 206 | ((CPOL) == SPI_CPOL_High)) |
| emilmont | 77:869cf507173a | 207 | /** |
| emilmont | 77:869cf507173a | 208 | * @} |
| emilmont | 77:869cf507173a | 209 | */ |
| emilmont | 77:869cf507173a | 210 | |
| emilmont | 77:869cf507173a | 211 | /** @defgroup SPI_Clock_Phase |
| emilmont | 77:869cf507173a | 212 | * @{ |
| emilmont | 77:869cf507173a | 213 | */ |
| emilmont | 77:869cf507173a | 214 | |
| emilmont | 77:869cf507173a | 215 | #define SPI_CPHA_1Edge ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 216 | #define SPI_CPHA_2Edge SPI_CR1_CPHA |
| emilmont | 77:869cf507173a | 217 | #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ |
| emilmont | 77:869cf507173a | 218 | ((CPHA) == SPI_CPHA_2Edge)) |
| emilmont | 77:869cf507173a | 219 | /** |
| emilmont | 77:869cf507173a | 220 | * @} |
| emilmont | 77:869cf507173a | 221 | */ |
| emilmont | 77:869cf507173a | 222 | |
| emilmont | 77:869cf507173a | 223 | /** @defgroup SPI_Slave_Select_management |
| emilmont | 77:869cf507173a | 224 | * @{ |
| emilmont | 77:869cf507173a | 225 | */ |
| emilmont | 77:869cf507173a | 226 | |
| emilmont | 77:869cf507173a | 227 | #define SPI_NSS_Soft SPI_CR1_SSM |
| emilmont | 77:869cf507173a | 228 | #define SPI_NSS_Hard ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 229 | #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ |
| emilmont | 77:869cf507173a | 230 | ((NSS) == SPI_NSS_Hard)) |
| emilmont | 77:869cf507173a | 231 | /** |
| emilmont | 77:869cf507173a | 232 | * @} |
| emilmont | 77:869cf507173a | 233 | */ |
| emilmont | 77:869cf507173a | 234 | |
| emilmont | 77:869cf507173a | 235 | /** @defgroup SPI_BaudRate_Prescaler |
| emilmont | 77:869cf507173a | 236 | * @{ |
| emilmont | 77:869cf507173a | 237 | */ |
| emilmont | 77:869cf507173a | 238 | |
| emilmont | 77:869cf507173a | 239 | #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 240 | #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) |
| emilmont | 77:869cf507173a | 241 | #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) |
| emilmont | 77:869cf507173a | 242 | #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) |
| emilmont | 77:869cf507173a | 243 | #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) |
| emilmont | 77:869cf507173a | 244 | #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) |
| emilmont | 77:869cf507173a | 245 | #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) |
| emilmont | 77:869cf507173a | 246 | #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) |
| emilmont | 77:869cf507173a | 247 | #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ |
| emilmont | 77:869cf507173a | 248 | ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ |
| emilmont | 77:869cf507173a | 249 | ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ |
| emilmont | 77:869cf507173a | 250 | ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ |
| emilmont | 77:869cf507173a | 251 | ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ |
| emilmont | 77:869cf507173a | 252 | ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ |
| emilmont | 77:869cf507173a | 253 | ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ |
| emilmont | 77:869cf507173a | 254 | ((PRESCALER) == SPI_BaudRatePrescaler_256)) |
| emilmont | 77:869cf507173a | 255 | /** |
| emilmont | 77:869cf507173a | 256 | * @} |
| emilmont | 77:869cf507173a | 257 | */ |
| emilmont | 77:869cf507173a | 258 | |
| emilmont | 77:869cf507173a | 259 | /** @defgroup SPI_MSB_LSB_transmission |
| emilmont | 77:869cf507173a | 260 | * @{ |
| emilmont | 77:869cf507173a | 261 | */ |
| emilmont | 77:869cf507173a | 262 | |
| emilmont | 77:869cf507173a | 263 | #define SPI_FirstBit_MSB ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 264 | #define SPI_FirstBit_LSB SPI_CR1_LSBFIRST |
| emilmont | 77:869cf507173a | 265 | #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ |
| emilmont | 77:869cf507173a | 266 | ((BIT) == SPI_FirstBit_LSB)) |
| emilmont | 77:869cf507173a | 267 | /** |
| emilmont | 77:869cf507173a | 268 | * @} |
| emilmont | 77:869cf507173a | 269 | */ |
| emilmont | 77:869cf507173a | 270 | |
| emilmont | 77:869cf507173a | 271 | /** @defgroup SPI_I2S_Mode |
| emilmont | 77:869cf507173a | 272 | * @{ |
| emilmont | 77:869cf507173a | 273 | */ |
| emilmont | 77:869cf507173a | 274 | |
| emilmont | 77:869cf507173a | 275 | #define I2S_Mode_SlaveTx ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 276 | #define I2S_Mode_SlaveRx ((uint16_t)0x0100) |
| emilmont | 77:869cf507173a | 277 | #define I2S_Mode_MasterTx ((uint16_t)0x0200) |
| emilmont | 77:869cf507173a | 278 | #define I2S_Mode_MasterRx ((uint16_t)0x0300) |
| emilmont | 77:869cf507173a | 279 | #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ |
| emilmont | 77:869cf507173a | 280 | ((MODE) == I2S_Mode_SlaveRx) || \ |
| emilmont | 77:869cf507173a | 281 | ((MODE) == I2S_Mode_MasterTx)|| \ |
| emilmont | 77:869cf507173a | 282 | ((MODE) == I2S_Mode_MasterRx)) |
| emilmont | 77:869cf507173a | 283 | /** |
| emilmont | 77:869cf507173a | 284 | * @} |
| emilmont | 77:869cf507173a | 285 | */ |
| emilmont | 77:869cf507173a | 286 | |
| emilmont | 77:869cf507173a | 287 | /** @defgroup SPI_I2S_Standard |
| emilmont | 77:869cf507173a | 288 | * @{ |
| emilmont | 77:869cf507173a | 289 | */ |
| emilmont | 77:869cf507173a | 290 | |
| emilmont | 77:869cf507173a | 291 | #define I2S_Standard_Phillips ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 292 | #define I2S_Standard_MSB ((uint16_t)0x0010) |
| emilmont | 77:869cf507173a | 293 | #define I2S_Standard_LSB ((uint16_t)0x0020) |
| emilmont | 77:869cf507173a | 294 | #define I2S_Standard_PCMShort ((uint16_t)0x0030) |
| emilmont | 77:869cf507173a | 295 | #define I2S_Standard_PCMLong ((uint16_t)0x00B0) |
| emilmont | 77:869cf507173a | 296 | #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ |
| emilmont | 77:869cf507173a | 297 | ((STANDARD) == I2S_Standard_MSB) || \ |
| emilmont | 77:869cf507173a | 298 | ((STANDARD) == I2S_Standard_LSB) || \ |
| emilmont | 77:869cf507173a | 299 | ((STANDARD) == I2S_Standard_PCMShort) || \ |
| emilmont | 77:869cf507173a | 300 | ((STANDARD) == I2S_Standard_PCMLong)) |
| emilmont | 77:869cf507173a | 301 | /** |
| emilmont | 77:869cf507173a | 302 | * @} |
| emilmont | 77:869cf507173a | 303 | */ |
| emilmont | 77:869cf507173a | 304 | |
| emilmont | 77:869cf507173a | 305 | /** @defgroup SPI_I2S_Data_Format |
| emilmont | 77:869cf507173a | 306 | * @{ |
| emilmont | 77:869cf507173a | 307 | */ |
| emilmont | 77:869cf507173a | 308 | |
| emilmont | 77:869cf507173a | 309 | #define I2S_DataFormat_16b ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 310 | #define I2S_DataFormat_16bextended ((uint16_t)0x0001) |
| emilmont | 77:869cf507173a | 311 | #define I2S_DataFormat_24b ((uint16_t)0x0003) |
| emilmont | 77:869cf507173a | 312 | #define I2S_DataFormat_32b ((uint16_t)0x0005) |
| emilmont | 77:869cf507173a | 313 | #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ |
| emilmont | 77:869cf507173a | 314 | ((FORMAT) == I2S_DataFormat_16bextended) || \ |
| emilmont | 77:869cf507173a | 315 | ((FORMAT) == I2S_DataFormat_24b) || \ |
| emilmont | 77:869cf507173a | 316 | ((FORMAT) == I2S_DataFormat_32b)) |
| emilmont | 77:869cf507173a | 317 | /** |
| emilmont | 77:869cf507173a | 318 | * @} |
| emilmont | 77:869cf507173a | 319 | */ |
| emilmont | 77:869cf507173a | 320 | |
| emilmont | 77:869cf507173a | 321 | /** @defgroup SPI_I2S_MCLK_Output |
| emilmont | 77:869cf507173a | 322 | * @{ |
| emilmont | 77:869cf507173a | 323 | */ |
| emilmont | 77:869cf507173a | 324 | |
| emilmont | 77:869cf507173a | 325 | #define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE |
| emilmont | 77:869cf507173a | 326 | #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 327 | #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ |
| emilmont | 77:869cf507173a | 328 | ((OUTPUT) == I2S_MCLKOutput_Disable)) |
| emilmont | 77:869cf507173a | 329 | /** |
| emilmont | 77:869cf507173a | 330 | * @} |
| emilmont | 77:869cf507173a | 331 | */ |
| emilmont | 77:869cf507173a | 332 | |
| emilmont | 77:869cf507173a | 333 | /** @defgroup SPI_I2S_Audio_Frequency |
| emilmont | 77:869cf507173a | 334 | * @{ |
| emilmont | 77:869cf507173a | 335 | */ |
| emilmont | 77:869cf507173a | 336 | |
| emilmont | 77:869cf507173a | 337 | #define I2S_AudioFreq_192k ((uint32_t)192000) |
| emilmont | 77:869cf507173a | 338 | #define I2S_AudioFreq_96k ((uint32_t)96000) |
| emilmont | 77:869cf507173a | 339 | #define I2S_AudioFreq_48k ((uint32_t)48000) |
| emilmont | 77:869cf507173a | 340 | #define I2S_AudioFreq_44k ((uint32_t)44100) |
| emilmont | 77:869cf507173a | 341 | #define I2S_AudioFreq_32k ((uint32_t)32000) |
| emilmont | 77:869cf507173a | 342 | #define I2S_AudioFreq_22k ((uint32_t)22050) |
| emilmont | 77:869cf507173a | 343 | #define I2S_AudioFreq_16k ((uint32_t)16000) |
| emilmont | 77:869cf507173a | 344 | #define I2S_AudioFreq_11k ((uint32_t)11025) |
| emilmont | 77:869cf507173a | 345 | #define I2S_AudioFreq_8k ((uint32_t)8000) |
| emilmont | 77:869cf507173a | 346 | #define I2S_AudioFreq_Default ((uint32_t)2) |
| emilmont | 77:869cf507173a | 347 | |
| emilmont | 77:869cf507173a | 348 | #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ |
| emilmont | 77:869cf507173a | 349 | ((FREQ) <= I2S_AudioFreq_192k)) || \ |
| emilmont | 77:869cf507173a | 350 | ((FREQ) == I2S_AudioFreq_Default)) |
| emilmont | 77:869cf507173a | 351 | /** |
| emilmont | 77:869cf507173a | 352 | * @} |
| emilmont | 77:869cf507173a | 353 | */ |
| emilmont | 77:869cf507173a | 354 | |
| emilmont | 77:869cf507173a | 355 | /** @defgroup SPI_I2S_Clock_Polarity |
| emilmont | 77:869cf507173a | 356 | * @{ |
| emilmont | 77:869cf507173a | 357 | */ |
| emilmont | 77:869cf507173a | 358 | |
| emilmont | 77:869cf507173a | 359 | #define I2S_CPOL_Low ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 360 | #define I2S_CPOL_High SPI_I2SCFGR_CKPOL |
| emilmont | 77:869cf507173a | 361 | #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ |
| emilmont | 77:869cf507173a | 362 | ((CPOL) == I2S_CPOL_High)) |
| emilmont | 77:869cf507173a | 363 | /** |
| emilmont | 77:869cf507173a | 364 | * @} |
| emilmont | 77:869cf507173a | 365 | */ |
| emilmont | 77:869cf507173a | 366 | |
| emilmont | 77:869cf507173a | 367 | /** @defgroup SPI_FIFO_reception_threshold |
| emilmont | 77:869cf507173a | 368 | * @{ |
| emilmont | 77:869cf507173a | 369 | */ |
| emilmont | 77:869cf507173a | 370 | |
| emilmont | 77:869cf507173a | 371 | #define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 372 | #define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH |
| emilmont | 77:869cf507173a | 373 | #define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \ |
| emilmont | 77:869cf507173a | 374 | ((THRESHOLD) == SPI_RxFIFOThreshold_QF)) |
| emilmont | 77:869cf507173a | 375 | /** |
| emilmont | 77:869cf507173a | 376 | * @} |
| emilmont | 77:869cf507173a | 377 | */ |
| emilmont | 77:869cf507173a | 378 | |
| emilmont | 77:869cf507173a | 379 | /** @defgroup SPI_I2S_DMA_transfer_requests |
| emilmont | 77:869cf507173a | 380 | * @{ |
| emilmont | 77:869cf507173a | 381 | */ |
| emilmont | 77:869cf507173a | 382 | |
| emilmont | 77:869cf507173a | 383 | #define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN |
| emilmont | 77:869cf507173a | 384 | #define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN |
| emilmont | 77:869cf507173a | 385 | #define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00)) |
| emilmont | 77:869cf507173a | 386 | /** |
| emilmont | 77:869cf507173a | 387 | * @} |
| emilmont | 77:869cf507173a | 388 | */ |
| emilmont | 77:869cf507173a | 389 | |
| emilmont | 77:869cf507173a | 390 | /** @defgroup SPI_last_DMA_transfers |
| emilmont | 77:869cf507173a | 391 | * @{ |
| emilmont | 77:869cf507173a | 392 | */ |
| emilmont | 77:869cf507173a | 393 | |
| emilmont | 77:869cf507173a | 394 | #define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 395 | #define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000) |
| emilmont | 77:869cf507173a | 396 | #define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000) |
| emilmont | 77:869cf507173a | 397 | #define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000) |
| emilmont | 77:869cf507173a | 398 | #define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \ |
| emilmont | 77:869cf507173a | 399 | ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \ |
| emilmont | 77:869cf507173a | 400 | ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \ |
| emilmont | 77:869cf507173a | 401 | ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd)) |
| emilmont | 77:869cf507173a | 402 | /** |
| emilmont | 77:869cf507173a | 403 | * @} |
| emilmont | 77:869cf507173a | 404 | */ |
| emilmont | 77:869cf507173a | 405 | /** @defgroup SPI_NSS_internal_software_management |
| emilmont | 77:869cf507173a | 406 | * @{ |
| emilmont | 77:869cf507173a | 407 | */ |
| emilmont | 77:869cf507173a | 408 | |
| emilmont | 77:869cf507173a | 409 | #define SPI_NSSInternalSoft_Set SPI_CR1_SSI |
| emilmont | 77:869cf507173a | 410 | #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) |
| emilmont | 77:869cf507173a | 411 | #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ |
| emilmont | 77:869cf507173a | 412 | ((INTERNAL) == SPI_NSSInternalSoft_Reset)) |
| emilmont | 77:869cf507173a | 413 | /** |
| emilmont | 77:869cf507173a | 414 | * @} |
| emilmont | 77:869cf507173a | 415 | */ |
| emilmont | 77:869cf507173a | 416 | |
| emilmont | 77:869cf507173a | 417 | /** @defgroup SPI_CRC_Transmit_Receive |
| emilmont | 77:869cf507173a | 418 | * @{ |
| emilmont | 77:869cf507173a | 419 | */ |
| emilmont | 77:869cf507173a | 420 | |
| emilmont | 77:869cf507173a | 421 | #define SPI_CRC_Tx ((uint8_t)0x00) |
| emilmont | 77:869cf507173a | 422 | #define SPI_CRC_Rx ((uint8_t)0x01) |
| emilmont | 77:869cf507173a | 423 | #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) |
| emilmont | 77:869cf507173a | 424 | /** |
| emilmont | 77:869cf507173a | 425 | * @} |
| emilmont | 77:869cf507173a | 426 | */ |
| emilmont | 77:869cf507173a | 427 | |
| emilmont | 77:869cf507173a | 428 | /** @defgroup SPI_direction_transmit_receive |
| emilmont | 77:869cf507173a | 429 | * @{ |
| emilmont | 77:869cf507173a | 430 | */ |
| emilmont | 77:869cf507173a | 431 | |
| emilmont | 77:869cf507173a | 432 | #define SPI_Direction_Rx ((uint16_t)0xBFFF) |
| emilmont | 77:869cf507173a | 433 | #define SPI_Direction_Tx ((uint16_t)0x4000) |
| emilmont | 77:869cf507173a | 434 | #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ |
| emilmont | 77:869cf507173a | 435 | ((DIRECTION) == SPI_Direction_Tx)) |
| emilmont | 77:869cf507173a | 436 | /** |
| emilmont | 77:869cf507173a | 437 | * @} |
| emilmont | 77:869cf507173a | 438 | */ |
| emilmont | 77:869cf507173a | 439 | |
| emilmont | 77:869cf507173a | 440 | /** @defgroup SPI_I2S_interrupts_definition |
| emilmont | 77:869cf507173a | 441 | * @{ |
| emilmont | 77:869cf507173a | 442 | */ |
| emilmont | 77:869cf507173a | 443 | |
| emilmont | 77:869cf507173a | 444 | #define SPI_I2S_IT_TXE ((uint8_t)0x71) |
| emilmont | 77:869cf507173a | 445 | #define SPI_I2S_IT_RXNE ((uint8_t)0x60) |
| emilmont | 77:869cf507173a | 446 | #define SPI_I2S_IT_ERR ((uint8_t)0x50) |
| emilmont | 77:869cf507173a | 447 | |
| emilmont | 77:869cf507173a | 448 | #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ |
| emilmont | 77:869cf507173a | 449 | ((IT) == SPI_I2S_IT_RXNE) || \ |
| emilmont | 77:869cf507173a | 450 | ((IT) == SPI_I2S_IT_ERR)) |
| emilmont | 77:869cf507173a | 451 | |
| emilmont | 77:869cf507173a | 452 | #define I2S_IT_UDR ((uint8_t)0x53) |
| emilmont | 77:869cf507173a | 453 | #define SPI_IT_MODF ((uint8_t)0x55) |
| emilmont | 77:869cf507173a | 454 | #define SPI_I2S_IT_OVR ((uint8_t)0x56) |
| emilmont | 77:869cf507173a | 455 | #define SPI_I2S_IT_FRE ((uint8_t)0x58) |
| emilmont | 77:869cf507173a | 456 | |
| emilmont | 77:869cf507173a | 457 | #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ |
| emilmont | 77:869cf507173a | 458 | ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \ |
| emilmont | 77:869cf507173a | 459 | ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR)) |
| emilmont | 77:869cf507173a | 460 | /** |
| emilmont | 77:869cf507173a | 461 | * @} |
| emilmont | 77:869cf507173a | 462 | */ |
| emilmont | 77:869cf507173a | 463 | |
| emilmont | 77:869cf507173a | 464 | |
| emilmont | 77:869cf507173a | 465 | /** @defgroup SPI_transmission_fifo_status_level |
| emilmont | 77:869cf507173a | 466 | * @{ |
| emilmont | 77:869cf507173a | 467 | */ |
| emilmont | 77:869cf507173a | 468 | |
| emilmont | 77:869cf507173a | 469 | #define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 470 | #define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800) |
| emilmont | 77:869cf507173a | 471 | #define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000) |
| emilmont | 77:869cf507173a | 472 | #define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800) |
| emilmont | 77:869cf507173a | 473 | |
| emilmont | 77:869cf507173a | 474 | /** |
| emilmont | 77:869cf507173a | 475 | * @} |
| emilmont | 77:869cf507173a | 476 | */ |
| emilmont | 77:869cf507173a | 477 | |
| emilmont | 77:869cf507173a | 478 | /** @defgroup SPI_reception_fifo_status_level |
| emilmont | 77:869cf507173a | 479 | * @{ |
| emilmont | 77:869cf507173a | 480 | */ |
| emilmont | 77:869cf507173a | 481 | #define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000) |
| emilmont | 77:869cf507173a | 482 | #define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200) |
| emilmont | 77:869cf507173a | 483 | #define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400) |
| emilmont | 77:869cf507173a | 484 | #define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600) |
| emilmont | 77:869cf507173a | 485 | |
| emilmont | 77:869cf507173a | 486 | /** |
| emilmont | 77:869cf507173a | 487 | * @} |
| emilmont | 77:869cf507173a | 488 | */ |
| emilmont | 77:869cf507173a | 489 | |
| emilmont | 77:869cf507173a | 490 | |
| emilmont | 77:869cf507173a | 491 | /** @defgroup SPI_I2S_flags_definition |
| emilmont | 77:869cf507173a | 492 | * @{ |
| emilmont | 77:869cf507173a | 493 | */ |
| emilmont | 77:869cf507173a | 494 | |
| emilmont | 77:869cf507173a | 495 | #define SPI_I2S_FLAG_RXNE SPI_SR_RXNE |
| emilmont | 77:869cf507173a | 496 | #define SPI_I2S_FLAG_TXE SPI_SR_TXE |
| emilmont | 77:869cf507173a | 497 | #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE |
| emilmont | 77:869cf507173a | 498 | #define I2S_FLAG_UDR SPI_SR_UDR |
| emilmont | 77:869cf507173a | 499 | #define SPI_FLAG_CRCERR SPI_SR_CRCERR |
| emilmont | 77:869cf507173a | 500 | #define SPI_FLAG_MODF SPI_SR_MODF |
| emilmont | 77:869cf507173a | 501 | #define SPI_I2S_FLAG_OVR SPI_SR_OVR |
| emilmont | 77:869cf507173a | 502 | #define SPI_I2S_FLAG_BSY SPI_SR_BSY |
| emilmont | 77:869cf507173a | 503 | #define SPI_I2S_FLAG_FRE SPI_SR_FRE |
| emilmont | 77:869cf507173a | 504 | |
| emilmont | 77:869cf507173a | 505 | |
| emilmont | 77:869cf507173a | 506 | |
| emilmont | 77:869cf507173a | 507 | #define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) |
| emilmont | 77:869cf507173a | 508 | #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ |
| emilmont | 77:869cf507173a | 509 | ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ |
| emilmont | 77:869cf507173a | 510 | ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ |
| emilmont | 77:869cf507173a | 511 | ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \ |
| emilmont | 77:869cf507173a | 512 | ((FLAG) == I2S_FLAG_UDR)) |
| emilmont | 77:869cf507173a | 513 | /** |
| emilmont | 77:869cf507173a | 514 | * @} |
| emilmont | 77:869cf507173a | 515 | */ |
| emilmont | 77:869cf507173a | 516 | |
| emilmont | 77:869cf507173a | 517 | /** @defgroup SPI_CRC_polynomial |
| emilmont | 77:869cf507173a | 518 | * @{ |
| emilmont | 77:869cf507173a | 519 | */ |
| emilmont | 77:869cf507173a | 520 | |
| emilmont | 77:869cf507173a | 521 | #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) |
| emilmont | 77:869cf507173a | 522 | /** |
| emilmont | 77:869cf507173a | 523 | * @} |
| emilmont | 77:869cf507173a | 524 | */ |
| emilmont | 77:869cf507173a | 525 | |
| emilmont | 77:869cf507173a | 526 | /** |
| emilmont | 77:869cf507173a | 527 | * @} |
| emilmont | 77:869cf507173a | 528 | */ |
| emilmont | 77:869cf507173a | 529 | |
| emilmont | 77:869cf507173a | 530 | /* Exported macro ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 531 | /* Exported functions ------------------------------------------------------- */ |
| emilmont | 77:869cf507173a | 532 | |
| emilmont | 77:869cf507173a | 533 | /* Initialization and Configuration functions *********************************/ |
| emilmont | 77:869cf507173a | 534 | void SPI_I2S_DeInit(SPI_TypeDef* SPIx); |
| emilmont | 77:869cf507173a | 535 | void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); |
| emilmont | 77:869cf507173a | 536 | void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for STM32F030 devices */ |
| emilmont | 77:869cf507173a | 537 | void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); |
| emilmont | 77:869cf507173a | 538 | void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for STM32F030 devices */ |
| emilmont | 77:869cf507173a | 539 | void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 540 | void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 541 | void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 542 | void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); /*!< Not applicable for STM32F030 devices */ |
| emilmont | 77:869cf507173a | 543 | void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); |
| emilmont | 77:869cf507173a | 544 | void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold); |
| emilmont | 77:869cf507173a | 545 | void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); |
| emilmont | 77:869cf507173a | 546 | void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); |
| emilmont | 77:869cf507173a | 547 | void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 548 | |
| emilmont | 77:869cf507173a | 549 | /* Data transfers functions ***************************************************/ |
| emilmont | 77:869cf507173a | 550 | void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data); |
| emilmont | 77:869cf507173a | 551 | void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data); |
| emilmont | 77:869cf507173a | 552 | uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx); |
| emilmont | 77:869cf507173a | 553 | uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx); |
| emilmont | 77:869cf507173a | 554 | |
| emilmont | 77:869cf507173a | 555 | /* Hardware CRC Calculation functions *****************************************/ |
| emilmont | 77:869cf507173a | 556 | void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength); |
| emilmont | 77:869cf507173a | 557 | void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 558 | void SPI_TransmitCRC(SPI_TypeDef* SPIx); |
| emilmont | 77:869cf507173a | 559 | uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); |
| emilmont | 77:869cf507173a | 560 | uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); |
| emilmont | 77:869cf507173a | 561 | |
| emilmont | 77:869cf507173a | 562 | /* DMA transfers management functions *****************************************/ |
| emilmont | 77:869cf507173a | 563 | void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 564 | void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer); |
| emilmont | 77:869cf507173a | 565 | |
| emilmont | 77:869cf507173a | 566 | /* Interrupts and flags management functions **********************************/ |
| emilmont | 77:869cf507173a | 567 | void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 568 | uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx); |
| emilmont | 77:869cf507173a | 569 | uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx); |
| emilmont | 77:869cf507173a | 570 | FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); |
| emilmont | 77:869cf507173a | 571 | void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); |
| emilmont | 77:869cf507173a | 572 | ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); |
| emilmont | 77:869cf507173a | 573 | |
| emilmont | 77:869cf507173a | 574 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 575 | } |
| emilmont | 77:869cf507173a | 576 | #endif |
| emilmont | 77:869cf507173a | 577 | |
| emilmont | 77:869cf507173a | 578 | #endif /*__STM32F0XX_SPI_H */ |
| emilmont | 77:869cf507173a | 579 | |
| emilmont | 77:869cf507173a | 580 | /** |
| emilmont | 77:869cf507173a | 581 | * @} |
| emilmont | 77:869cf507173a | 582 | */ |
| emilmont | 77:869cf507173a | 583 | |
| emilmont | 77:869cf507173a | 584 | /** |
| emilmont | 77:869cf507173a | 585 | * @} |
| emilmont | 77:869cf507173a | 586 | */ |
| emilmont | 77:869cf507173a | 587 | |
| emilmont | 77:869cf507173a | 588 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
