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TARGET_WIZWIKI_W7500/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.h@162:dbaafcfe0e9d, 2018-03-19 (annotated)

Committer:
AnnaBridge
Date:
Mon Mar 19 15:30:13 2018 +0000
Revision:
162:dbaafcfe0e9d
Parent:
TARGET_WIZwiki_W7500/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.h@156:ff21514d8981 
mbed library. Release version 160

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file
AnnaBridge 156:ff21514d8981 4 * @author
AnnaBridge 156:ff21514d8981 5 * @version
AnnaBridge 156:ff21514d8981 6 * @date
AnnaBridge 156:ff21514d8981 7 * @brief This file contains all the functions prototypes for the UART
AnnaBridge 156:ff21514d8981 8 * firmware library.
AnnaBridge 156:ff21514d8981 9 ******************************************************************************
AnnaBridge 156:ff21514d8981 10 *
AnnaBridge 156:ff21514d8981 11 ******************************************************************************
AnnaBridge 156:ff21514d8981 12 */
AnnaBridge 156:ff21514d8981 13
AnnaBridge 156:ff21514d8981 14 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 156:ff21514d8981 15 #ifndef __W7500X_PWM_H
AnnaBridge 156:ff21514d8981 16 #define __W7500X_PWM_H
AnnaBridge 156:ff21514d8981 17
AnnaBridge 156:ff21514d8981 18 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 19 extern "C" {
AnnaBridge 156:ff21514d8981 20 #endif
AnnaBridge 156:ff21514d8981 21
AnnaBridge 156:ff21514d8981 22 /* Includes ------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 23 #include "W7500x.h"
AnnaBridge 156:ff21514d8981 24
AnnaBridge 156:ff21514d8981 25 /**********************************************************************************************/
AnnaBridge 156:ff21514d8981 26 /**********************************************************************************************/
AnnaBridge 156:ff21514d8981 27 // This structure and define must be in W7500x.h
AnnaBridge 156:ff21514d8981 28 /**********************************************************************************************/
AnnaBridge 156:ff21514d8981 29 /**********************************************************************************************/
AnnaBridge 156:ff21514d8981 30
AnnaBridge 156:ff21514d8981 31 typedef struct
AnnaBridge 156:ff21514d8981 32 {
AnnaBridge 156:ff21514d8981 33 uint32_t PWM_CHn_PEEER;
AnnaBridge 156:ff21514d8981 34 }PWM_CtrlPWMOutputTypeDef;
AnnaBridge 156:ff21514d8981 35
AnnaBridge 156:ff21514d8981 36 typedef struct
AnnaBridge 156:ff21514d8981 37 {
AnnaBridge 156:ff21514d8981 38 uint32_t PWM_CHn_PR;
AnnaBridge 156:ff21514d8981 39 uint32_t PWM_CHn_MR;
AnnaBridge 156:ff21514d8981 40 uint32_t PWM_CHn_LR;
AnnaBridge 156:ff21514d8981 41 uint32_t PWM_CHn_UDMR;
AnnaBridge 156:ff21514d8981 42 uint32_t PWM_CHn_PDMR;
AnnaBridge 156:ff21514d8981 43 uint32_t PWM_CHn_DZCR;
AnnaBridge 156:ff21514d8981 44 }PWM_DeadzoneModeInitTypDef;
AnnaBridge 156:ff21514d8981 45
AnnaBridge 156:ff21514d8981 46 #define IS_PWM_ALL_CH(CHn) ((CHn == PWM_CH0) || \
AnnaBridge 156:ff21514d8981 47 (CHn == PWM_CH1) || \
AnnaBridge 156:ff21514d8981 48 (CHn == PWM_CH2) || \
AnnaBridge 156:ff21514d8981 49 (CHn == PWM_CH3) || \
AnnaBridge 156:ff21514d8981 50 (CHn == PWM_CH4) || \
AnnaBridge 156:ff21514d8981 51 (CHn == PWM_CH5) || \
AnnaBridge 156:ff21514d8981 52 (CHn == PWM_CH6) || \
AnnaBridge 156:ff21514d8981 53 (CHn == PWM_CH7))
AnnaBridge 156:ff21514d8981 54
AnnaBridge 156:ff21514d8981 55 #define PWM_IER_IE0_Enable (0x1ul << 0)
AnnaBridge 156:ff21514d8981 56 #define PWM_IER_IE1_Enable (0x1ul << 1)
AnnaBridge 156:ff21514d8981 57 #define PWM_IER_IE2_Enable (0x1ul << 2)
AnnaBridge 156:ff21514d8981 58 #define PWM_IER_IE3_Enable (0x1ul << 3)
AnnaBridge 156:ff21514d8981 59 #define PWM_IER_IE4_Enable (0x1ul << 4)
AnnaBridge 156:ff21514d8981 60 #define PWM_IER_IE5_Enable (0x1ul << 5)
AnnaBridge 156:ff21514d8981 61 #define PWM_IER_IE6_Enable (0x1ul << 6)
AnnaBridge 156:ff21514d8981 62 #define PWM_IER_IE7_Enable (0x1ul << 7)
AnnaBridge 156:ff21514d8981 63
AnnaBridge 156:ff21514d8981 64 #define PWM_IER_IE0_Disable ~PWM_IER_IE0_Enable
AnnaBridge 156:ff21514d8981 65 #define PWM_IER_IE1_Disable ~PWM_IER_IE1_Enable
AnnaBridge 156:ff21514d8981 66 #define PWM_IER_IE2_Disable ~PWM_IER_IE2_Enable
AnnaBridge 156:ff21514d8981 67 #define PWM_IER_IE3_Disable ~PWM_IER_IE3_Enable
AnnaBridge 156:ff21514d8981 68 #define PWM_IER_IE4_Disable ~PWM_IER_IE4_Enable
AnnaBridge 156:ff21514d8981 69 #define PWM_IER_IE5_Disable ~PWM_IER_IE5_Enable
AnnaBridge 156:ff21514d8981 70 #define PWM_IER_IE6_Disable ~PWM_IER_IE6_Enable
AnnaBridge 156:ff21514d8981 71 #define PWM_IER_IE7_Disable ~PWM_IER_IE7_Enable
AnnaBridge 156:ff21514d8981 72
AnnaBridge 156:ff21514d8981 73 #define PWM_SSR_SS0_Start (0x1ul << 0)
AnnaBridge 156:ff21514d8981 74 #define PWM_SSR_SS1_Start (0x1ul << 1)
AnnaBridge 156:ff21514d8981 75 #define PWM_SSR_SS2_Start (0x1ul << 2)
AnnaBridge 156:ff21514d8981 76 #define PWM_SSR_SS3_Start (0x1ul << 3)
AnnaBridge 156:ff21514d8981 77 #define PWM_SSR_SS4_Start (0x1ul << 4)
AnnaBridge 156:ff21514d8981 78 #define PWM_SSR_SS5_Start (0x1ul << 5)
AnnaBridge 156:ff21514d8981 79 #define PWM_SSR_SS6_Start (0x1ul << 6)
AnnaBridge 156:ff21514d8981 80 #define PWM_SSR_SS7_Start (0x1ul << 7)
AnnaBridge 156:ff21514d8981 81
AnnaBridge 156:ff21514d8981 82 #define PWM_SSR_SS0_Stop ~PWM_SSR_SS0_Start
AnnaBridge 156:ff21514d8981 83 #define PWM_SSR_SS1_Stop ~PWM_SSR_SS1_Start
AnnaBridge 156:ff21514d8981 84 #define PWM_SSR_SS2_Stop ~PWM_SSR_SS2_Start
AnnaBridge 156:ff21514d8981 85 #define PWM_SSR_SS3_Stop ~PWM_SSR_SS3_Start
AnnaBridge 156:ff21514d8981 86 #define PWM_SSR_SS4_Stop ~PWM_SSR_SS4_Start
AnnaBridge 156:ff21514d8981 87 #define PWM_SSR_SS5_Stop ~PWM_SSR_SS5_Start
AnnaBridge 156:ff21514d8981 88 #define PWM_SSR_SS6_Stop ~PWM_SSR_SS6_Start
AnnaBridge 156:ff21514d8981 89 #define PWM_SSR_SS7_Stop ~PWM_SSR_SS7_Start
AnnaBridge 156:ff21514d8981 90
AnnaBridge 156:ff21514d8981 91 #define IS_SSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
AnnaBridge 156:ff21514d8981 92
AnnaBridge 156:ff21514d8981 93 #define PWM_PSR_PS0_Pause (0x1ul << 0)
AnnaBridge 156:ff21514d8981 94 #define PWM_PSR_PS1_Pause (0x1ul << 1)
AnnaBridge 156:ff21514d8981 95 #define PWM_PSR_PS2_Pause (0x1ul << 2)
AnnaBridge 156:ff21514d8981 96 #define PWM_PSR_PS3_Pause (0x1ul << 3)
AnnaBridge 156:ff21514d8981 97 #define PWM_PSR_PS4_Pause (0x1ul << 4)
AnnaBridge 156:ff21514d8981 98 #define PWM_PSR_PS5_Pause (0x1ul << 5)
AnnaBridge 156:ff21514d8981 99 #define PWM_PSR_PS6_Pause (0x1ul << 6)
AnnaBridge 156:ff21514d8981 100 #define PWM_PSR_PS7_Pause (0x1ul << 7)
AnnaBridge 156:ff21514d8981 101
AnnaBridge 156:ff21514d8981 102 #define PWM_PSR_PS0_Restart ~PWM_PSR_PS0_Pause
AnnaBridge 156:ff21514d8981 103 #define PWM_PSR_PS1_Restart ~PWM_PSR_PS1_Pause
AnnaBridge 156:ff21514d8981 104 #define PWM_PSR_PS2_Restart ~PWM_PSR_PS2_Pause
AnnaBridge 156:ff21514d8981 105 #define PWM_PSR_PS3_Restart ~PWM_PSR_PS3_Pause
AnnaBridge 156:ff21514d8981 106 #define PWM_PSR_PS4_Restart ~PWM_PSR_PS4_Pause
AnnaBridge 156:ff21514d8981 107 #define PWM_PSR_PS5_Restart ~PWM_PSR_PS5_Pause
AnnaBridge 156:ff21514d8981 108 #define PWM_PSR_PS6_Restart ~PWM_PSR_PS6_Pause
AnnaBridge 156:ff21514d8981 109 #define PWM_PSR_PS7_Restart ~PWM_PSR_PS7_Pause
AnnaBridge 156:ff21514d8981 110
AnnaBridge 156:ff21514d8981 111 #define IS_PWM_PSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
AnnaBridge 156:ff21514d8981 112
AnnaBridge 156:ff21514d8981 113 #define PWM_CHn_IER_MIE (0x1ul << 0) ///< Match Interrupt Enable
AnnaBridge 156:ff21514d8981 114 #define PWM_CHn_IER_OIE (0x1ul << 1) ///< Overflow Interrupt Enable
AnnaBridge 156:ff21514d8981 115 #define PWM_CHn_IER_CIE (0x1ul << 2) ///< Capture Interrupt Enable
AnnaBridge 156:ff21514d8981 116 #define IS_PWM_CHn_IER(FLAG) (FLAG <= 0x7)
AnnaBridge 156:ff21514d8981 117
AnnaBridge 156:ff21514d8981 118 #define PWM_CHn_IER_MI_Msk (0x1ul << 0) ///< Match Interrupt Enable Mask
AnnaBridge 156:ff21514d8981 119 #define PWM_CHn_IER_OI_Msk (0x1ul << 1) ///< Overflow Interrupt Enable Mask
AnnaBridge 156:ff21514d8981 120 #define PWM_CHn_IER_CI_Msk (0x1ul << 2) ///< Capture Interrupt Enable Mask
AnnaBridge 156:ff21514d8981 121
AnnaBridge 156:ff21514d8981 122 #define PWM_CHn_ICR_MatchInterruptClear (0x1ul << 0)
AnnaBridge 156:ff21514d8981 123 #define PWM_CHn_ICR_OverflowInterruptClear (0x1ul << 1)
AnnaBridge 156:ff21514d8981 124 #define PWM_CHn_ICR_CaptureInterruptClear (0x1ul << 2)
AnnaBridge 156:ff21514d8981 125 #define IS_PWM_CHn_IntClearFlag(FLAG) FLAG <= 0x7
AnnaBridge 156:ff21514d8981 126
AnnaBridge 156:ff21514d8981 127 /*
AnnaBridge 156:ff21514d8981 128 #define IS_PWM_STOP(CHn) (((CHn == PWM_CH0) && (PWM->SSR & PWM_SSR_SS0)) || \
AnnaBridge 156:ff21514d8981 129 ((CHn == PWM_CH1) && (PWM->SSR & PWM_SSR_SS1)) || \
AnnaBridge 156:ff21514d8981 130 ((CHn == PWM_CH2) && (PWM->SSR & PWM_SSR_SS2)) || \
AnnaBridge 156:ff21514d8981 131 ((CHn == PWM_CH3) && (PWM->SSR & PWM_SSR_SS3)) || \
AnnaBridge 156:ff21514d8981 132 ((CHn == PWM_CH4) && (PWM->SSR & PWM_SSR_SS4)) || \
AnnaBridge 156:ff21514d8981 133 ((CHn == PWM_CH5) && (PWM->SSR & PWM_SSR_SS5)) || \
AnnaBridge 156:ff21514d8981 134 ((CHn == PWM_CH6) && (PWM->SSR & PWM_SSR_SS6)) || \
AnnaBridge 156:ff21514d8981 135 ((CHn == PWM_CH7) && (PWM->SSR & PWM_SSR_SS7)))
AnnaBridge 156:ff21514d8981 136 */
AnnaBridge 156:ff21514d8981 137
AnnaBridge 156:ff21514d8981 138
AnnaBridge 156:ff21514d8981 139 #define IS_PWM_PR_FILTER(MAXVAL) (MAXVAL <= 0x1F)
AnnaBridge 156:ff21514d8981 140
AnnaBridge 156:ff21514d8981 141
AnnaBridge 156:ff21514d8981 142 #define PWM_CHn_UDMR_UpCount (0x0ul)
AnnaBridge 156:ff21514d8981 143 #define PWM_CHn_UDMR_DownCount (0x1ul)
AnnaBridge 156:ff21514d8981 144 #define IS_PWM_CHn_UDMR(MODE) ((MODE == PWM_CHn_UDMR_UpCount) || \
AnnaBridge 156:ff21514d8981 145 (MODE == PWM_CHn_UDMR_DownCount))
AnnaBridge 156:ff21514d8981 146
AnnaBridge 156:ff21514d8981 147 #define PWM_CHn_TCMR_TimerMode (0x0ul)
AnnaBridge 156:ff21514d8981 148 #define PWM_CHn_TCMR_RisingCounterMode (0x1ul)
AnnaBridge 156:ff21514d8981 149 #define PWM_CHn_TCMR_FallingCounterMode (0x2ul)
AnnaBridge 156:ff21514d8981 150 #define PWM_CHn_TCMR_BothCounterMode (0x3ul)
AnnaBridge 156:ff21514d8981 151 #define IS_PWM_CHn_TCMR(MODE) ((MODE == PWM_CHn_TCMR_RisingCounterMode) || \
AnnaBridge 156:ff21514d8981 152 (MODE == PWM_CHn_TCMR_FallingCounterMode) || \
AnnaBridge 156:ff21514d8981 153 (MODE == PWM_CHn_TCMR_BothCounterMode))
AnnaBridge 156:ff21514d8981 154
AnnaBridge 156:ff21514d8981 155 #define PWM_CHn_PEEER_Disable (0x0ul)
AnnaBridge 156:ff21514d8981 156 #define PWM_CHn_PEEER_ExtEnable (0x1ul)
AnnaBridge 156:ff21514d8981 157 #define PWM_CHn_PEEER_PWMEnable (0x2ul)
AnnaBridge 156:ff21514d8981 158 #define IS_PWM_CHn_PEEER(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
AnnaBridge 156:ff21514d8981 159 (ENABLE == PWM_CHn_PEEER_ExtEnable) || \
AnnaBridge 156:ff21514d8981 160 (ENABLE == PWM_CHn_PEEER_PWMEnable))
AnnaBridge 156:ff21514d8981 161
AnnaBridge 156:ff21514d8981 162 #define IS_PWM_Output(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
AnnaBridge 156:ff21514d8981 163 (ENABLE == PWM_CHn_PEEER_PWMEnable))
AnnaBridge 156:ff21514d8981 164
AnnaBridge 156:ff21514d8981 165 #define PWM_CHn_CMR_RisingEdge 0x0ul
AnnaBridge 156:ff21514d8981 166 #define PWM_CHn_CMR_FallingEdge 0x1ul
AnnaBridge 156:ff21514d8981 167 #define IS_PWM_CHn_CMR(MODE) ((MODE == PWM_CHn_CMR_RisingEdge) || \
AnnaBridge 156:ff21514d8981 168 (MODE == PWM_CHn_CMR_FallingEdge))
AnnaBridge 156:ff21514d8981 169
AnnaBridge 156:ff21514d8981 170 #define PWM_CHn_PDMR_Oneshot (0x0ul)
AnnaBridge 156:ff21514d8981 171 #define PWM_CHn_PDMR_Periodic (0x1ul)
AnnaBridge 156:ff21514d8981 172 #define IS_PWM_CHn_PDMR(MODE) ((MODE == PWM_CHn_PDMR_Periodic) || \
AnnaBridge 156:ff21514d8981 173 (MODE == PWM_CHn_PDMR_Oneshot))
AnnaBridge 156:ff21514d8981 174
AnnaBridge 156:ff21514d8981 175 #define PWM_CHn_DZER_Enable (0x1ul)
AnnaBridge 156:ff21514d8981 176 #define PWM_CHn_DZER_Disable (0x0ul)
AnnaBridge 156:ff21514d8981 177 #define PWM_CHn_DZER(ENABLE) ((ENABLE == PWM_CHn_DZER_Enable) || \
AnnaBridge 156:ff21514d8981 178 (ENABLE == PWM_CHn_DZER_Disable))
AnnaBridge 156:ff21514d8981 179
AnnaBridge 156:ff21514d8981 180 #define IS_PWM_Deadznoe(CHn) (((CHn == PWM_CH0) && (PWM_CH1->DZER == PWM_CHn_DZER_Disable)) || \
AnnaBridge 156:ff21514d8981 181 ((CHn == PWM_CH1) && (PWM_CH0->DZER == PWM_CHn_DZER_Disable)) || \
AnnaBridge 156:ff21514d8981 182 ((CHn == PWM_CH2) && (PWM_CH3->DZER == PWM_CHn_DZER_Disable)) || \
AnnaBridge 156:ff21514d8981 183 ((CHn == PWM_CH3) && (PWM_CH2->DZER == PWM_CHn_DZER_Disable)) || \
AnnaBridge 156:ff21514d8981 184 ((CHn == PWM_CH4) && (PWM_CH5->DZER == PWM_CHn_DZER_Disable)) || \
AnnaBridge 156:ff21514d8981 185 ((CHn == PWM_CH5) && (PWM_CH4->DZER == PWM_CHn_DZER_Disable)) || \
AnnaBridge 156:ff21514d8981 186 ((CHn == PWM_CH6) && (PWM_CH7->DZER == PWM_CHn_DZER_Disable)) || \
AnnaBridge 156:ff21514d8981 187 ((CHn == PWM_CH7) && (PWM_CH6->DZER == PWM_CHn_DZER_Disable)))
AnnaBridge 156:ff21514d8981 188
AnnaBridge 156:ff21514d8981 189 #define IS_PWM_CHn_DZCR_FILTER(MAXVAL) (MAXVAL <= 0x3FF)
AnnaBridge 156:ff21514d8981 190
AnnaBridge 156:ff21514d8981 191
AnnaBridge 156:ff21514d8981 192
AnnaBridge 156:ff21514d8981 193
AnnaBridge 156:ff21514d8981 194
AnnaBridge 156:ff21514d8981 195
AnnaBridge 156:ff21514d8981 196 void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 197 void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct);
AnnaBridge 156:ff21514d8981 198 void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct);
AnnaBridge 156:ff21514d8981 199 void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct);
AnnaBridge 156:ff21514d8981 200 void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct);
AnnaBridge 156:ff21514d8981 201 void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable );
AnnaBridge 156:ff21514d8981 202 void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) ;
AnnaBridge 156:ff21514d8981 203 void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) ;
AnnaBridge 156:ff21514d8981 204 void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state);
AnnaBridge 156:ff21514d8981 205 FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 206 void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state);
AnnaBridge 156:ff21514d8981 207 void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 208 void PWM_Multi_Start(uint32_t ssr_bit_flag);
AnnaBridge 156:ff21514d8981 209 void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 210 void PWM_Multi_Stop(uint32_t ssr_bit_flag);
AnnaBridge 156:ff21514d8981 211 void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 212 void PWM_Multi_Pause(uint32_t psr_bit_flag);
AnnaBridge 156:ff21514d8981 213 void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 214 void PWM_Multi_Restart(uint32_t psr_bit_flag);
AnnaBridge 156:ff21514d8981 215 uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 216 uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 217 void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR);
AnnaBridge 156:ff21514d8981 218 uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 219 uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 220 uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 221 void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR);
AnnaBridge 156:ff21514d8981 222 uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 223 void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR);
AnnaBridge 156:ff21514d8981 224 uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 225 void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR);
AnnaBridge 156:ff21514d8981 226 uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 227 void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR);
AnnaBridge 156:ff21514d8981 228 uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 229 void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR);
AnnaBridge 156:ff21514d8981 230 uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 231 void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER);
AnnaBridge 156:ff21514d8981 232 uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 233 void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR);
AnnaBridge 156:ff21514d8981 234 uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 235 uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 236 void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR);
AnnaBridge 156:ff21514d8981 237 void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER);
AnnaBridge 156:ff21514d8981 238 uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn);
AnnaBridge 156:ff21514d8981 239 void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR);
AnnaBridge 156:ff21514d8981 240 void PWM_CH0_ClearMatchInt(void);
AnnaBridge 156:ff21514d8981 241 void PWM_CH0_ClearOverflowInt(void);
AnnaBridge 156:ff21514d8981 242 void PWM_CH0_ClearCaptureInt(void);
AnnaBridge 156:ff21514d8981 243 void PWM_CH1_ClearMatchInt(void);
AnnaBridge 156:ff21514d8981 244 void PWM_CH1_ClearOverflowInt(void);
AnnaBridge 156:ff21514d8981 245 void PWM_CH1_ClearCaptureInt(void);
AnnaBridge 156:ff21514d8981 246 void PWM_CH2_ClearMatchInt(void);
AnnaBridge 156:ff21514d8981 247 void PWM_CH2_ClearOverflowInt(void);
AnnaBridge 156:ff21514d8981 248 void PWM_CH2_ClearCaptureInt(void);
AnnaBridge 156:ff21514d8981 249 void PWM_CH3_ClearMatchInt(void);
AnnaBridge 156:ff21514d8981 250 void PWM_CH3_ClearOverflowInt(void);
AnnaBridge 156:ff21514d8981 251 void PWM_CH3_ClearCaptureInt(void);
AnnaBridge 156:ff21514d8981 252 void PWM_CH4_ClearMatchInt(void);
AnnaBridge 156:ff21514d8981 253 void PWM_CH4_ClearOverflowInt(void);
AnnaBridge 156:ff21514d8981 254 void PWM_CH4_ClearCaptureInt(void);
AnnaBridge 156:ff21514d8981 255 void PWM_CH5_ClearMatchInt(void);
AnnaBridge 156:ff21514d8981 256 void PWM_CH5_ClearOverflowInt(void);
AnnaBridge 156:ff21514d8981 257 void PWM_CH5_ClearCaptureInt(void);
AnnaBridge 156:ff21514d8981 258 void PWM_CH6_ClearMatchInt(void);
AnnaBridge 156:ff21514d8981 259 void PWM_CH6_ClearOverflowInt(void);
AnnaBridge 156:ff21514d8981 260 void PWM_CH6_ClearCaptureInt(void);
AnnaBridge 156:ff21514d8981 261 void PWM_CH7_ClearMatchInt(void);
AnnaBridge 156:ff21514d8981 262 void PWM_CH7_ClearOverflowInt(void);
AnnaBridge 156:ff21514d8981 263 void PWM_CH7_ClearCaptureInt(void);
AnnaBridge 156:ff21514d8981 264
AnnaBridge 156:ff21514d8981 265
AnnaBridge 156:ff21514d8981 266 void PWM0_Handler(void);
AnnaBridge 156:ff21514d8981 267 void PWM1_Handler(void);
AnnaBridge 156:ff21514d8981 268 void PWM2_Handler(void);
AnnaBridge 156:ff21514d8981 269 void PWM3_Handler(void);
AnnaBridge 156:ff21514d8981 270 void PWM4_Handler(void);
AnnaBridge 156:ff21514d8981 271 void PWM5_Handler(void);
AnnaBridge 156:ff21514d8981 272 void PWM6_Handler(void);
AnnaBridge 156:ff21514d8981 273 void PWM7_Handler(void);
AnnaBridge 156:ff21514d8981 274
AnnaBridge 156:ff21514d8981 275
AnnaBridge 156:ff21514d8981 276
AnnaBridge 156:ff21514d8981 277
AnnaBridge 156:ff21514d8981 278 //Temporary macro=======
AnnaBridge 156:ff21514d8981 279 #define PWM_CH(N) ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + (N * 0x100UL)))
AnnaBridge 156:ff21514d8981 280 //======================
AnnaBridge 156:ff21514d8981 281
AnnaBridge 156:ff21514d8981 282
AnnaBridge 156:ff21514d8981 283 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 284 }
AnnaBridge 156:ff21514d8981 285 #endif
AnnaBridge 156:ff21514d8981 286
AnnaBridge 156:ff21514d8981 287
AnnaBridge 156:ff21514d8981 288 #endif //__W7500X_PWM_H
AnnaBridge 156:ff21514d8981 289