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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.h@634:ac7d6880524d, 2015-09-28 (annotated)

Committer:
mbed_official
Date:
Mon Sep 28 20:15:09 2015 +0100
Revision:
634:ac7d6880524d
Parent:
632:7687fb9c4f91 
Synchronized with git revision 9b7d23d47153c298a6d24de9a415202705889d11



Full URL: https://github.com/mbedmicro/mbed/commit/9b7d23d47153c298a6d24de9a415202705889d11/



Revert "[NUCLEO_F303K8] add support of the STM32F303K8"

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 330:c80ac197fa6a 1 /**
mbed_official 330:c80ac197fa6a 2 ******************************************************************************
mbed_official 330:c80ac197fa6a 3 * @file stm32f3xx_hal_tim_ex.h
mbed_official 330:c80ac197fa6a 4 * @author MCD Application Team
mbed_official 634:ac7d6880524d 5 * @version V1.1.0
mbed_official 634:ac7d6880524d 6 * @date 12-Sept-2014
mbed_official 330:c80ac197fa6a 7 * @brief Header file of TIM HAL Extended module.
mbed_official 330:c80ac197fa6a 8 ******************************************************************************
mbed_official 330:c80ac197fa6a 9 * @attention
mbed_official 330:c80ac197fa6a 10 *
mbed_official 634:ac7d6880524d 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 330:c80ac197fa6a 12 *
mbed_official 330:c80ac197fa6a 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 330:c80ac197fa6a 14 * are permitted provided that the following conditions are met:
mbed_official 330:c80ac197fa6a 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 330:c80ac197fa6a 16 * this list of conditions and the following disclaimer.
mbed_official 330:c80ac197fa6a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 330:c80ac197fa6a 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 330:c80ac197fa6a 19 * and/or other materials provided with the distribution.
mbed_official 330:c80ac197fa6a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 330:c80ac197fa6a 21 * may be used to endorse or promote products derived from this software
mbed_official 330:c80ac197fa6a 22 * without specific prior written permission.
mbed_official 330:c80ac197fa6a 23 *
mbed_official 330:c80ac197fa6a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 330:c80ac197fa6a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 330:c80ac197fa6a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 330:c80ac197fa6a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 330:c80ac197fa6a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 330:c80ac197fa6a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 330:c80ac197fa6a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 330:c80ac197fa6a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 330:c80ac197fa6a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 330:c80ac197fa6a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 330:c80ac197fa6a 34 *
mbed_official 330:c80ac197fa6a 35 ******************************************************************************
mbed_official 330:c80ac197fa6a 36 */
mbed_official 330:c80ac197fa6a 37
mbed_official 330:c80ac197fa6a 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 330:c80ac197fa6a 39 #ifndef __STM32F3xx_HAL_TIM_EX_H
mbed_official 330:c80ac197fa6a 40 #define __STM32F3xx_HAL_TIM_EX_H
mbed_official 330:c80ac197fa6a 41
mbed_official 330:c80ac197fa6a 42 #ifdef __cplusplus
mbed_official 330:c80ac197fa6a 43 extern "C" {
mbed_official 330:c80ac197fa6a 44 #endif
mbed_official 330:c80ac197fa6a 45
mbed_official 330:c80ac197fa6a 46 /* Includes ------------------------------------------------------------------*/
mbed_official 330:c80ac197fa6a 47 #include "stm32f3xx_hal_def.h"
mbed_official 330:c80ac197fa6a 48
mbed_official 330:c80ac197fa6a 49 /** @addtogroup STM32F3xx_HAL_Driver
mbed_official 330:c80ac197fa6a 50 * @{
mbed_official 330:c80ac197fa6a 51 */
mbed_official 330:c80ac197fa6a 52
mbed_official 330:c80ac197fa6a 53 /** @addtogroup TIMEx
mbed_official 330:c80ac197fa6a 54 * @{
mbed_official 330:c80ac197fa6a 55 */
mbed_official 330:c80ac197fa6a 56
mbed_official 330:c80ac197fa6a 57 /* Exported types ------------------------------------------------------------*/
mbed_official 330:c80ac197fa6a 58 /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
mbed_official 330:c80ac197fa6a 59 * @{
mbed_official 330:c80ac197fa6a 60 */
mbed_official 330:c80ac197fa6a 61
mbed_official 330:c80ac197fa6a 62 /**
mbed_official 330:c80ac197fa6a 63 * @brief TIM Hall sensor Configuration Structure definition
mbed_official 330:c80ac197fa6a 64 */
mbed_official 330:c80ac197fa6a 65
mbed_official 330:c80ac197fa6a 66 typedef struct
mbed_official 330:c80ac197fa6a 67 {
mbed_official 330:c80ac197fa6a 68
mbed_official 330:c80ac197fa6a 69 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
mbed_official 330:c80ac197fa6a 70 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official 330:c80ac197fa6a 71
mbed_official 330:c80ac197fa6a 72 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official 330:c80ac197fa6a 73 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official 330:c80ac197fa6a 74
mbed_official 330:c80ac197fa6a 75 uint32_t IC1Filter; /*!< Specifies the input capture filter.
mbed_official 330:c80ac197fa6a 76 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official 330:c80ac197fa6a 77 uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official 330:c80ac197fa6a 78 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official 330:c80ac197fa6a 79 } TIM_HallSensor_InitTypeDef;
mbed_official 330:c80ac197fa6a 80
mbed_official 330:c80ac197fa6a 81 #if defined(STM32F373xC) || defined(STM32F378xx)
mbed_official 330:c80ac197fa6a 82 /**
mbed_official 330:c80ac197fa6a 83 * @brief TIM Master configuration Structure definition
mbed_official 330:c80ac197fa6a 84 * @note STM32F373xC and STM32F378xx: timer instances provide a single TRGO
mbed_official 330:c80ac197fa6a 85 * output
mbed_official 330:c80ac197fa6a 86 */
mbed_official 330:c80ac197fa6a 87 typedef struct {
mbed_official 330:c80ac197fa6a 88 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
mbed_official 330:c80ac197fa6a 89 This parameter can be a value of @ref TIM_Master_Mode_Selection */
mbed_official 330:c80ac197fa6a 90 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
mbed_official 330:c80ac197fa6a 91 This parameter can be a value of @ref TIM_Master_Slave_Mode */
mbed_official 330:c80ac197fa6a 92 }TIM_MasterConfigTypeDef;
mbed_official 330:c80ac197fa6a 93
mbed_official 330:c80ac197fa6a 94 /**
mbed_official 330:c80ac197fa6a 95 * @brief TIM Break and Dead time configuration Structure definition
mbed_official 330:c80ac197fa6a 96 * @note STM32F373xC and STM32F378xx: single break input with configurable polarity.
mbed_official 330:c80ac197fa6a 97 */
mbed_official 330:c80ac197fa6a 98 typedef struct
mbed_official 330:c80ac197fa6a 99 {
mbed_official 330:c80ac197fa6a 100 uint32_t OffStateRunMode; /*!< TIM off state in run mode
mbed_official 330:c80ac197fa6a 101 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
mbed_official 330:c80ac197fa6a 102 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
mbed_official 330:c80ac197fa6a 103 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
mbed_official 330:c80ac197fa6a 104 uint32_t LockLevel; /*!< TIM Lock level
mbed_official 330:c80ac197fa6a 105 This parameter can be a value of @ref TIM_Lock_level */
mbed_official 330:c80ac197fa6a 106 uint32_t DeadTime; /*!< TIM dead Time
mbed_official 330:c80ac197fa6a 107 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
mbed_official 330:c80ac197fa6a 108 uint32_t BreakState; /*!< TIM Break State
mbed_official 330:c80ac197fa6a 109 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
mbed_official 330:c80ac197fa6a 110 uint32_t BreakPolarity; /*!< TIM Break input polarity
mbed_official 330:c80ac197fa6a 111 This parameter can be a value of @ref TIM_Break_Polarity */
mbed_official 330:c80ac197fa6a 112 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
mbed_official 330:c80ac197fa6a 113 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
mbed_official 330:c80ac197fa6a 114 } TIM_BreakDeadTimeConfigTypeDef;
mbed_official 330:c80ac197fa6a 115
mbed_official 330:c80ac197fa6a 116 #endif /* STM32F373xC || STM32F378xx */
mbed_official 330:c80ac197fa6a 117
mbed_official 330:c80ac197fa6a 118 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
mbed_official 330:c80ac197fa6a 119 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
mbed_official 330:c80ac197fa6a 120 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
mbed_official 330:c80ac197fa6a 121 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
mbed_official 330:c80ac197fa6a 122 /**
mbed_official 330:c80ac197fa6a 123 * @brief TIM Break input(s) and Dead time configuration Structure definition
mbed_official 330:c80ac197fa6a 124 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
mbed_official 330:c80ac197fa6a 125 * filter and polarity.
mbed_official 330:c80ac197fa6a 126 */
mbed_official 330:c80ac197fa6a 127 typedef struct
mbed_official 330:c80ac197fa6a 128 {
mbed_official 330:c80ac197fa6a 129 uint32_t OffStateRunMode; /*!< TIM off state in run mode
mbed_official 330:c80ac197fa6a 130 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
mbed_official 330:c80ac197fa6a 131 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
mbed_official 330:c80ac197fa6a 132 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
mbed_official 330:c80ac197fa6a 133 uint32_t LockLevel; /*!< TIM Lock level
mbed_official 330:c80ac197fa6a 134 This parameter can be a value of @ref TIM_Lock_level */
mbed_official 330:c80ac197fa6a 135 uint32_t DeadTime; /*!< TIM dead Time
mbed_official 330:c80ac197fa6a 136 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
mbed_official 330:c80ac197fa6a 137 uint32_t BreakState; /*!< TIM Break State
mbed_official 330:c80ac197fa6a 138 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
mbed_official 330:c80ac197fa6a 139 uint32_t BreakPolarity; /*!< TIM Break input polarity
mbed_official 330:c80ac197fa6a 140 This parameter can be a value of @ref TIM_Break_Polarity */
mbed_official 330:c80ac197fa6a 141 uint32_t BreakFilter; /*!< Specifies the brek input filter.
mbed_official 330:c80ac197fa6a 142 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official 330:c80ac197fa6a 143 uint32_t Break2State; /*!< TIM Break2 State
mbed_official 330:c80ac197fa6a 144 This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
mbed_official 330:c80ac197fa6a 145 uint32_t Break2Polarity; /*!< TIM Break2 input polarity
mbed_official 330:c80ac197fa6a 146 This parameter can be a value of @ref TIMEx_Break2_Polarity */
mbed_official 330:c80ac197fa6a 147 uint32_t Break2Filter; /*!< TIM break2 input filter.
mbed_official 330:c80ac197fa6a 148 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official 330:c80ac197fa6a 149 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
mbed_official 330:c80ac197fa6a 150 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
mbed_official 330:c80ac197fa6a 151 } TIM_BreakDeadTimeConfigTypeDef;
mbed_official 330:c80ac197fa6a 152
mbed_official 330:c80ac197fa6a 153 /**
mbed_official 330:c80ac197fa6a 154 * @brief TIM Master configuration Structure definition
mbed_official 330:c80ac197fa6a 155 * @note Advanced timers provide TRGO2 internal line which is redirected
mbed_official 330:c80ac197fa6a 156 * to the ADC
mbed_official 330:c80ac197fa6a 157 */
mbed_official 330:c80ac197fa6a 158 typedef struct {
mbed_official 330:c80ac197fa6a 159 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
mbed_official 330:c80ac197fa6a 160 This parameter can be a value of @ref TIM_Master_Mode_Selection */
mbed_official 330:c80ac197fa6a 161 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
mbed_official 330:c80ac197fa6a 162 This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
mbed_official 330:c80ac197fa6a 163 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
mbed_official 330:c80ac197fa6a 164 This parameter can be a value of @ref TIM_Master_Slave_Mode */
mbed_official 330:c80ac197fa6a 165 }TIM_MasterConfigTypeDef;
mbed_official 330:c80ac197fa6a 166 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
mbed_official 330:c80ac197fa6a 167 /* STM32F302xC || STM32F303xC || STM32F358xx || */
mbed_official 330:c80ac197fa6a 168 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
mbed_official 330:c80ac197fa6a 169 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
mbed_official 330:c80ac197fa6a 170 /**
mbed_official 330:c80ac197fa6a 171 * @}
mbed_official 330:c80ac197fa6a 172 */
mbed_official 330:c80ac197fa6a 173
mbed_official 330:c80ac197fa6a 174 /* Exported constants --------------------------------------------------------*/
mbed_official 330:c80ac197fa6a 175 /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
mbed_official 330:c80ac197fa6a 176 * @{
mbed_official 330:c80ac197fa6a 177 */
mbed_official 330:c80ac197fa6a 178
mbed_official 330:c80ac197fa6a 179 #if defined(STM32F373xC) || defined(STM32F378xx)
mbed_official 330:c80ac197fa6a 180 /** @defgroup TIMEx_Channel TIM Extended Channel
mbed_official 330:c80ac197fa6a 181 * @{
mbed_official 330:c80ac197fa6a 182 */
mbed_official 330:c80ac197fa6a 183 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
mbed_official 330:c80ac197fa6a 184 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
mbed_official 330:c80ac197fa6a 185 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
mbed_official 330:c80ac197fa6a 186 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
mbed_official 330:c80ac197fa6a 187 #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
mbed_official 330:c80ac197fa6a 188
mbed_official 330:c80ac197fa6a 189 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 330:c80ac197fa6a 190 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 330:c80ac197fa6a 191 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 330:c80ac197fa6a 192 ((CHANNEL) == TIM_CHANNEL_4) || \
mbed_official 330:c80ac197fa6a 193 ((CHANNEL) == TIM_CHANNEL_ALL))
mbed_official 330:c80ac197fa6a 194
mbed_official 330:c80ac197fa6a 195 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 330:c80ac197fa6a 196 ((CHANNEL) == TIM_CHANNEL_2))
mbed_official 330:c80ac197fa6a 197
mbed_official 330:c80ac197fa6a 198 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 330:c80ac197fa6a 199 ((CHANNEL) == TIM_CHANNEL_2))
mbed_official 330:c80ac197fa6a 200
mbed_official 330:c80ac197fa6a 201 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 330:c80ac197fa6a 202 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 330:c80ac197fa6a 203 ((CHANNEL) == TIM_CHANNEL_3))
mbed_official 330:c80ac197fa6a 204 /**
mbed_official 330:c80ac197fa6a 205 * @}
mbed_official 330:c80ac197fa6a 206 */
mbed_official 330:c80ac197fa6a 207
mbed_official 330:c80ac197fa6a 208 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Extended Output Compare and PWM Modes
mbed_official 330:c80ac197fa6a 209 * @{
mbed_official 330:c80ac197fa6a 210 */
mbed_official 330:c80ac197fa6a 211
mbed_official 330:c80ac197fa6a 212 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
mbed_official 330:c80ac197fa6a 213 #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
mbed_official 330:c80ac197fa6a 214 #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
mbed_official 330:c80ac197fa6a 215 #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
mbed_official 330:c80ac197fa6a 216 #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
mbed_official 330:c80ac197fa6a 217 #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M)
mbed_official 330:c80ac197fa6a 218 #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
mbed_official 330:c80ac197fa6a 219 #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
mbed_official 330:c80ac197fa6a 220
mbed_official 330:c80ac197fa6a 221 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
mbed_official 330:c80ac197fa6a 222 ((MODE) == TIM_OCMODE_PWM2))
mbed_official 330:c80ac197fa6a 223
mbed_official 330:c80ac197fa6a 224 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
mbed_official 330:c80ac197fa6a 225 ((MODE) == TIM_OCMODE_ACTIVE) || \
mbed_official 330:c80ac197fa6a 226 ((MODE) == TIM_OCMODE_INACTIVE) || \
mbed_official 330:c80ac197fa6a 227 ((MODE) == TIM_OCMODE_TOGGLE) || \
mbed_official 330:c80ac197fa6a 228 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
mbed_official 330:c80ac197fa6a 229 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
mbed_official 330:c80ac197fa6a 230 /**
mbed_official 330:c80ac197fa6a 231 * @}
mbed_official 330:c80ac197fa6a 232 */
mbed_official 330:c80ac197fa6a 233
mbed_official 330:c80ac197fa6a 234 /** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source
mbed_official 330:c80ac197fa6a 235 * @{
mbed_official 330:c80ac197fa6a 236 */
mbed_official 330:c80ac197fa6a 237 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
mbed_official 330:c80ac197fa6a 238 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
mbed_official 330:c80ac197fa6a 239
mbed_official 330:c80ac197fa6a 240 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
mbed_official 330:c80ac197fa6a 241 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
mbed_official 330:c80ac197fa6a 242 /**
mbed_official 330:c80ac197fa6a 243 * @}
mbed_official 330:c80ac197fa6a 244 */
mbed_official 330:c80ac197fa6a 245
mbed_official 330:c80ac197fa6a 246 /** @defgroup TIMEx_Slave_Mode TIM Extended Slave Mode
mbed_official 330:c80ac197fa6a 247 * @{
mbed_official 330:c80ac197fa6a 248 */
mbed_official 330:c80ac197fa6a 249
mbed_official 330:c80ac197fa6a 250 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official 330:c80ac197fa6a 251 #define TIM_SLAVEMODE_RESET ((uint16_t)0x0004)
mbed_official 330:c80ac197fa6a 252 #define TIM_SLAVEMODE_GATED ((uint16_t)0x0005)
mbed_official 330:c80ac197fa6a 253 #define TIM_SLAVEMODE_TRIGGER ((uint16_t)0x0006)
mbed_official 330:c80ac197fa6a 254 #define TIM_SLAVEMODE_EXTERNAL1 ((uint16_t)0x0007)
mbed_official 330:c80ac197fa6a 255
mbed_official 330:c80ac197fa6a 256 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
mbed_official 330:c80ac197fa6a 257 ((MODE) == TIM_SLAVEMODE_RESET) || \
mbed_official 330:c80ac197fa6a 258 ((MODE) == TIM_SLAVEMODE_GATED) || \
mbed_official 330:c80ac197fa6a 259 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
mbed_official 330:c80ac197fa6a 260 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
mbed_official 330:c80ac197fa6a 261 /**
mbed_official 330:c80ac197fa6a 262 * @}
mbed_official 330:c80ac197fa6a 263 */
mbed_official 330:c80ac197fa6a 264
mbed_official 330:c80ac197fa6a 265 /** @defgroup TIMEx_Event_Source TIM Extended Event Source
mbed_official 330:c80ac197fa6a 266 * @{
mbed_official 330:c80ac197fa6a 267 */
mbed_official 330:c80ac197fa6a 268
mbed_official 330:c80ac197fa6a 269 #define TIM_EventSource_Update TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
mbed_official 330:c80ac197fa6a 270 #define TIM_EventSource_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
mbed_official 330:c80ac197fa6a 271 #define TIM_EventSource_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
mbed_official 330:c80ac197fa6a 272 #define TIM_EventSource_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
mbed_official 330:c80ac197fa6a 273 #define TIM_EventSource_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
mbed_official 330:c80ac197fa6a 274 #define TIM_EventSource_COM TIM_EGR_COMG /*!< A commutation event is generated */
mbed_official 330:c80ac197fa6a 275 #define TIM_EventSource_Trigger TIM_EGR_TG /*!< A trigger event is generated */
mbed_official 330:c80ac197fa6a 276 #define TIM_EventSource_Break TIM_EGR_BG /*!< A break event is generated */
mbed_official 330:c80ac197fa6a 277 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official 330:c80ac197fa6a 278
mbed_official 330:c80ac197fa6a 279 /**
mbed_official 330:c80ac197fa6a 280 * @}
mbed_official 330:c80ac197fa6a 281 */
mbed_official 330:c80ac197fa6a 282
mbed_official 330:c80ac197fa6a 283 /** @defgroup TIMEx_DMA_Base_address TIM Extended DMA BAse Address
mbed_official 330:c80ac197fa6a 284 * @{
mbed_official 330:c80ac197fa6a 285 */
mbed_official 330:c80ac197fa6a 286
mbed_official 330:c80ac197fa6a 287 #define TIM_DMABase_CR1 (0x00000000)
mbed_official 330:c80ac197fa6a 288 #define TIM_DMABase_CR2 (0x00000001)
mbed_official 330:c80ac197fa6a 289 #define TIM_DMABase_SMCR (0x00000002)
mbed_official 330:c80ac197fa6a 290 #define TIM_DMABase_DIER (0x00000003)
mbed_official 330:c80ac197fa6a 291 #define TIM_DMABase_SR (0x00000004)
mbed_official 330:c80ac197fa6a 292 #define TIM_DMABase_EGR (0x00000005)
mbed_official 330:c80ac197fa6a 293 #define TIM_DMABase_CCMR1 (0x00000006)
mbed_official 330:c80ac197fa6a 294 #define TIM_DMABase_CCMR2 (0x00000007)
mbed_official 330:c80ac197fa6a 295 #define TIM_DMABase_CCER (0x00000008)
mbed_official 330:c80ac197fa6a 296 #define TIM_DMABase_CNT (0x00000009)
mbed_official 330:c80ac197fa6a 297 #define TIM_DMABase_PSC (0x0000000A)
mbed_official 330:c80ac197fa6a 298 #define TIM_DMABase_ARR (0x0000000B)
mbed_official 330:c80ac197fa6a 299 #define TIM_DMABase_RCR (0x0000000C)
mbed_official 330:c80ac197fa6a 300 #define TIM_DMABase_CCR1 (0x0000000D)
mbed_official 330:c80ac197fa6a 301 #define TIM_DMABase_CCR2 (0x0000000E)
mbed_official 330:c80ac197fa6a 302 #define TIM_DMABase_CCR3 (0x0000000F)
mbed_official 330:c80ac197fa6a 303 #define TIM_DMABase_CCR4 (0x00000010)
mbed_official 330:c80ac197fa6a 304 #define TIM_DMABase_BDTR (0x00000011)
mbed_official 330:c80ac197fa6a 305 #define TIM_DMABase_DCR (0x00000012)
mbed_official 330:c80ac197fa6a 306 #define TIM_DMABase_OR (0x00000013)
mbed_official 330:c80ac197fa6a 307 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
mbed_official 330:c80ac197fa6a 308 ((BASE) == TIM_DMABase_CR2) || \
mbed_official 330:c80ac197fa6a 309 ((BASE) == TIM_DMABase_SMCR) || \
mbed_official 330:c80ac197fa6a 310 ((BASE) == TIM_DMABase_DIER) || \
mbed_official 330:c80ac197fa6a 311 ((BASE) == TIM_DMABase_SR) || \
mbed_official 330:c80ac197fa6a 312 ((BASE) == TIM_DMABase_EGR) || \
mbed_official 330:c80ac197fa6a 313 ((BASE) == TIM_DMABase_CCMR1) || \
mbed_official 330:c80ac197fa6a 314 ((BASE) == TIM_DMABase_CCMR2) || \
mbed_official 330:c80ac197fa6a 315 ((BASE) == TIM_DMABase_CCER) || \
mbed_official 330:c80ac197fa6a 316 ((BASE) == TIM_DMABase_CNT) || \
mbed_official 330:c80ac197fa6a 317 ((BASE) == TIM_DMABase_PSC) || \
mbed_official 330:c80ac197fa6a 318 ((BASE) == TIM_DMABase_ARR) || \
mbed_official 330:c80ac197fa6a 319 ((BASE) == TIM_DMABase_RCR) || \
mbed_official 330:c80ac197fa6a 320 ((BASE) == TIM_DMABase_CCR1) || \
mbed_official 330:c80ac197fa6a 321 ((BASE) == TIM_DMABase_CCR2) || \
mbed_official 330:c80ac197fa6a 322 ((BASE) == TIM_DMABase_CCR3) || \
mbed_official 330:c80ac197fa6a 323 ((BASE) == TIM_DMABase_CCR4) || \
mbed_official 330:c80ac197fa6a 324 ((BASE) == TIM_DMABase_BDTR) || \
mbed_official 330:c80ac197fa6a 325 ((BASE) == TIM_DMABase_DCR) || \
mbed_official 330:c80ac197fa6a 326 ((BASE) == TIM_DMABase_OR))
mbed_official 330:c80ac197fa6a 327 /**
mbed_official 330:c80ac197fa6a 328 * @}
mbed_official 330:c80ac197fa6a 329 */
mbed_official 330:c80ac197fa6a 330 #endif /* STM32F373xC || STM32F378xx */
mbed_official 330:c80ac197fa6a 331
mbed_official 330:c80ac197fa6a 332 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
mbed_official 330:c80ac197fa6a 333 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
mbed_official 330:c80ac197fa6a 334 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
mbed_official 330:c80ac197fa6a 335 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
mbed_official 330:c80ac197fa6a 336 /** @defgroup TIMEx_Channel TIM Extended Channel
mbed_official 330:c80ac197fa6a 337 * @{
mbed_official 330:c80ac197fa6a 338 */
mbed_official 330:c80ac197fa6a 339
mbed_official 330:c80ac197fa6a 340 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
mbed_official 330:c80ac197fa6a 341 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
mbed_official 330:c80ac197fa6a 342 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
mbed_official 330:c80ac197fa6a 343 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
mbed_official 330:c80ac197fa6a 344 #define TIM_CHANNEL_5 ((uint32_t)0x0010)
mbed_official 330:c80ac197fa6a 345 #define TIM_CHANNEL_6 ((uint32_t)0x0014)
mbed_official 330:c80ac197fa6a 346 #define TIM_CHANNEL_ALL ((uint32_t)0x003C)
mbed_official 330:c80ac197fa6a 347
mbed_official 330:c80ac197fa6a 348 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 330:c80ac197fa6a 349 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 330:c80ac197fa6a 350 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 330:c80ac197fa6a 351 ((CHANNEL) == TIM_CHANNEL_4) || \
mbed_official 330:c80ac197fa6a 352 ((CHANNEL) == TIM_CHANNEL_5) || \
mbed_official 330:c80ac197fa6a 353 ((CHANNEL) == TIM_CHANNEL_6) || \
mbed_official 330:c80ac197fa6a 354 ((CHANNEL) == TIM_CHANNEL_ALL))
mbed_official 330:c80ac197fa6a 355
mbed_official 330:c80ac197fa6a 356 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 330:c80ac197fa6a 357 ((CHANNEL) == TIM_CHANNEL_2))
mbed_official 330:c80ac197fa6a 358
mbed_official 330:c80ac197fa6a 359 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 330:c80ac197fa6a 360 ((CHANNEL) == TIM_CHANNEL_2))
mbed_official 330:c80ac197fa6a 361
mbed_official 330:c80ac197fa6a 362 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 330:c80ac197fa6a 363 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 330:c80ac197fa6a 364 ((CHANNEL) == TIM_CHANNEL_3))
mbed_official 330:c80ac197fa6a 365 /**
mbed_official 330:c80ac197fa6a 366 * @}
mbed_official 330:c80ac197fa6a 367 */
mbed_official 330:c80ac197fa6a 368
mbed_official 330:c80ac197fa6a 369 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Extended Output Compare and PWM Modes
mbed_official 330:c80ac197fa6a 370 * @{
mbed_official 330:c80ac197fa6a 371 */
mbed_official 330:c80ac197fa6a 372 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
mbed_official 330:c80ac197fa6a 373 #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
mbed_official 330:c80ac197fa6a 374 #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
mbed_official 330:c80ac197fa6a 375 #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
mbed_official 330:c80ac197fa6a 376 #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
mbed_official 330:c80ac197fa6a 377 #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
mbed_official 330:c80ac197fa6a 378 #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
mbed_official 330:c80ac197fa6a 379 #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
mbed_official 330:c80ac197fa6a 380
mbed_official 330:c80ac197fa6a 381 #define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
mbed_official 330:c80ac197fa6a 382 #define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
mbed_official 330:c80ac197fa6a 383 #define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
mbed_official 330:c80ac197fa6a 384 #define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
mbed_official 330:c80ac197fa6a 385 #define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
mbed_official 330:c80ac197fa6a 386 #define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
mbed_official 330:c80ac197fa6a 387
mbed_official 330:c80ac197fa6a 388 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
mbed_official 330:c80ac197fa6a 389 ((MODE) == TIM_OCMODE_PWM2) || \
mbed_official 330:c80ac197fa6a 390 ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \
mbed_official 330:c80ac197fa6a 391 ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \
mbed_official 330:c80ac197fa6a 392 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
mbed_official 330:c80ac197fa6a 393 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
mbed_official 330:c80ac197fa6a 394
mbed_official 330:c80ac197fa6a 395 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
mbed_official 330:c80ac197fa6a 396 ((MODE) == TIM_OCMODE_ACTIVE) || \
mbed_official 330:c80ac197fa6a 397 ((MODE) == TIM_OCMODE_INACTIVE) || \
mbed_official 330:c80ac197fa6a 398 ((MODE) == TIM_OCMODE_TOGGLE) || \
mbed_official 330:c80ac197fa6a 399 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
mbed_official 330:c80ac197fa6a 400 ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \
mbed_official 330:c80ac197fa6a 401 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
mbed_official 330:c80ac197fa6a 402 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
mbed_official 330:c80ac197fa6a 403 /**
mbed_official 330:c80ac197fa6a 404 * @}
mbed_official 330:c80ac197fa6a 405 */
mbed_official 330:c80ac197fa6a 406
mbed_official 330:c80ac197fa6a 407 /** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source
mbed_official 330:c80ac197fa6a 408 * @{
mbed_official 330:c80ac197fa6a 409 */
mbed_official 330:c80ac197fa6a 410 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
mbed_official 330:c80ac197fa6a 411 #define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
mbed_official 330:c80ac197fa6a 412 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
mbed_official 330:c80ac197fa6a 413
mbed_official 330:c80ac197fa6a 414 #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \
mbed_official 330:c80ac197fa6a 415 ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
mbed_official 330:c80ac197fa6a 416 ((MODE) == TIM_CLEARINPUTSOURCE_NONE))
mbed_official 330:c80ac197fa6a 417 /**
mbed_official 330:c80ac197fa6a 418 * @}
mbed_official 330:c80ac197fa6a 419 */
mbed_official 330:c80ac197fa6a 420
mbed_official 330:c80ac197fa6a 421 /** @defgroup TIMEx_BreakInput_Filter TIM Extended Break Input Filter
mbed_official 330:c80ac197fa6a 422 * @{
mbed_official 330:c80ac197fa6a 423 */
mbed_official 330:c80ac197fa6a 424
mbed_official 330:c80ac197fa6a 425 #define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xF)
mbed_official 330:c80ac197fa6a 426 /**
mbed_official 330:c80ac197fa6a 427 * @}
mbed_official 330:c80ac197fa6a 428 */
mbed_official 330:c80ac197fa6a 429
mbed_official 330:c80ac197fa6a 430 /** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
mbed_official 330:c80ac197fa6a 431 * @{
mbed_official 330:c80ac197fa6a 432 */
mbed_official 330:c80ac197fa6a 433 #define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
mbed_official 330:c80ac197fa6a 434 #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
mbed_official 330:c80ac197fa6a 435
mbed_official 330:c80ac197fa6a 436 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
mbed_official 330:c80ac197fa6a 437 ((STATE) == TIM_BREAK2_DISABLE))
mbed_official 330:c80ac197fa6a 438 /**
mbed_official 330:c80ac197fa6a 439 * @}
mbed_official 330:c80ac197fa6a 440 */
mbed_official 330:c80ac197fa6a 441 /** @defgroup TIMEx_Break2_Polarity TIM Extended Break Input 2 Polarity
mbed_official 330:c80ac197fa6a 442 * @{
mbed_official 330:c80ac197fa6a 443 */
mbed_official 330:c80ac197fa6a 444 #define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
mbed_official 330:c80ac197fa6a 445 #define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
mbed_official 330:c80ac197fa6a 446
mbed_official 330:c80ac197fa6a 447 #define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_BREAK2POLARITY_LOW) || \
mbed_official 330:c80ac197fa6a 448 ((POLARITY) == TIM_BREAK2POLARITY_HIGH))
mbed_official 330:c80ac197fa6a 449 /**
mbed_official 330:c80ac197fa6a 450 * @}
mbed_official 330:c80ac197fa6a 451 */
mbed_official 330:c80ac197fa6a 452
mbed_official 330:c80ac197fa6a 453 /** @defgroup TIMEx_Master_Mode_Selection_2 TIM Extended Master Mode Selection 2 (TRGO2)
mbed_official 330:c80ac197fa6a 454 * @{
mbed_official 330:c80ac197fa6a 455 */
mbed_official 330:c80ac197fa6a 456 #define TIM_TRGO2_RESET ((uint32_t)0x00000000)
mbed_official 330:c80ac197fa6a 457 #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
mbed_official 330:c80ac197fa6a 458 #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
mbed_official 330:c80ac197fa6a 459 #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
mbed_official 330:c80ac197fa6a 460 #define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
mbed_official 330:c80ac197fa6a 461 #define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
mbed_official 330:c80ac197fa6a 462 #define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
mbed_official 330:c80ac197fa6a 463 #define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
mbed_official 330:c80ac197fa6a 464 #define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
mbed_official 330:c80ac197fa6a 465 #define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
mbed_official 330:c80ac197fa6a 466 #define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
mbed_official 330:c80ac197fa6a 467 #define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
mbed_official 330:c80ac197fa6a 468 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
mbed_official 330:c80ac197fa6a 469 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
mbed_official 330:c80ac197fa6a 470 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
mbed_official 330:c80ac197fa6a 471 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
mbed_official 330:c80ac197fa6a 472
mbed_official 330:c80ac197fa6a 473 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \
mbed_official 330:c80ac197fa6a 474 ((SOURCE) == TIM_TRGO2_ENABLE) || \
mbed_official 330:c80ac197fa6a 475 ((SOURCE) == TIM_TRGO2_UPDATE) || \
mbed_official 330:c80ac197fa6a 476 ((SOURCE) == TIM_TRGO2_OC1) || \
mbed_official 330:c80ac197fa6a 477 ((SOURCE) == TIM_TRGO2_OC1REF) || \
mbed_official 330:c80ac197fa6a 478 ((SOURCE) == TIM_TRGO2_OC2REF) || \
mbed_official 330:c80ac197fa6a 479 ((SOURCE) == TIM_TRGO2_OC3REF) || \
mbed_official 330:c80ac197fa6a 480 ((SOURCE) == TIM_TRGO2_OC3REF) || \
mbed_official 330:c80ac197fa6a 481 ((SOURCE) == TIM_TRGO2_OC4REF) || \
mbed_official 330:c80ac197fa6a 482 ((SOURCE) == TIM_TRGO2_OC5REF) || \
mbed_official 330:c80ac197fa6a 483 ((SOURCE) == TIM_TRGO2_OC6REF) || \
mbed_official 330:c80ac197fa6a 484 ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
mbed_official 330:c80ac197fa6a 485 ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
mbed_official 330:c80ac197fa6a 486 ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
mbed_official 330:c80ac197fa6a 487 ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
mbed_official 330:c80ac197fa6a 488 ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
mbed_official 330:c80ac197fa6a 489 ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
mbed_official 330:c80ac197fa6a 490 /**
mbed_official 330:c80ac197fa6a 491 * @}
mbed_official 330:c80ac197fa6a 492 */
mbed_official 330:c80ac197fa6a 493
mbed_official 330:c80ac197fa6a 494 /** @defgroup TIMEx_Slave_Mode TIM Extended Slave mode
mbed_official 330:c80ac197fa6a 495 * @{
mbed_official 330:c80ac197fa6a 496 */
mbed_official 330:c80ac197fa6a 497 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official 330:c80ac197fa6a 498 #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
mbed_official 330:c80ac197fa6a 499 #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
mbed_official 330:c80ac197fa6a 500 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
mbed_official 330:c80ac197fa6a 501 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
mbed_official 330:c80ac197fa6a 502 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
mbed_official 330:c80ac197fa6a 503
mbed_official 330:c80ac197fa6a 504 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
mbed_official 330:c80ac197fa6a 505 ((MODE) == TIM_SLAVEMODE_RESET) || \
mbed_official 330:c80ac197fa6a 506 ((MODE) == TIM_SLAVEMODE_GATED) || \
mbed_official 330:c80ac197fa6a 507 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
mbed_official 330:c80ac197fa6a 508 ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
mbed_official 330:c80ac197fa6a 509 ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
mbed_official 330:c80ac197fa6a 510 /**
mbed_official 330:c80ac197fa6a 511 * @}
mbed_official 330:c80ac197fa6a 512 */
mbed_official 330:c80ac197fa6a 513
mbed_official 330:c80ac197fa6a 514 /** @defgroup TIM_Event_Source TIM Extended Event Source
mbed_official 330:c80ac197fa6a 515 * @{
mbed_official 330:c80ac197fa6a 516 */
mbed_official 330:c80ac197fa6a 517
mbed_official 330:c80ac197fa6a 518 #define TIM_EventSource_Update TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
mbed_official 330:c80ac197fa6a 519 #define TIM_EventSource_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
mbed_official 330:c80ac197fa6a 520 #define TIM_EventSource_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
mbed_official 330:c80ac197fa6a 521 #define TIM_EventSource_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
mbed_official 330:c80ac197fa6a 522 #define TIM_EventSource_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
mbed_official 330:c80ac197fa6a 523 #define TIM_EventSource_COM TIM_EGR_COMG /*!< A commutation event is generated */
mbed_official 330:c80ac197fa6a 524 #define TIM_EventSource_Trigger TIM_EGR_TG /*!< A trigger event is generated */
mbed_official 330:c80ac197fa6a 525 #define TIM_EventSource_Break TIM_EGR_BG /*!< A break event is generated */
mbed_official 330:c80ac197fa6a 526 #define TIM_EventSource_Break2 TIM_EGR_B2G /*!< A break 2 event is generated */
mbed_official 330:c80ac197fa6a 527 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official 330:c80ac197fa6a 528
mbed_official 330:c80ac197fa6a 529 /**
mbed_official 330:c80ac197fa6a 530 * @}
mbed_official 330:c80ac197fa6a 531 */
mbed_official 330:c80ac197fa6a 532
mbed_official 330:c80ac197fa6a 533 /** @defgroup TIM_DMA_Base_address TIM Extended DMA Base Address
mbed_official 330:c80ac197fa6a 534 * @{
mbed_official 330:c80ac197fa6a 535 */
mbed_official 330:c80ac197fa6a 536
mbed_official 330:c80ac197fa6a 537 #define TIM_DMABase_CR1 (0x00000000)
mbed_official 330:c80ac197fa6a 538 #define TIM_DMABase_CR2 (0x00000001)
mbed_official 330:c80ac197fa6a 539 #define TIM_DMABase_SMCR (0x00000002)
mbed_official 330:c80ac197fa6a 540 #define TIM_DMABase_DIER (0x00000003)
mbed_official 330:c80ac197fa6a 541 #define TIM_DMABase_SR (0x00000004)
mbed_official 330:c80ac197fa6a 542 #define TIM_DMABase_EGR (0x00000005)
mbed_official 330:c80ac197fa6a 543 #define TIM_DMABase_CCMR1 (0x00000006)
mbed_official 330:c80ac197fa6a 544 #define TIM_DMABase_CCMR2 (0x00000007)
mbed_official 330:c80ac197fa6a 545 #define TIM_DMABase_CCER (0x00000008)
mbed_official 330:c80ac197fa6a 546 #define TIM_DMABase_CNT (0x00000009)
mbed_official 330:c80ac197fa6a 547 #define TIM_DMABase_PSC (0x0000000A)
mbed_official 330:c80ac197fa6a 548 #define TIM_DMABase_ARR (0x0000000B)
mbed_official 330:c80ac197fa6a 549 #define TIM_DMABase_RCR (0x0000000C)
mbed_official 330:c80ac197fa6a 550 #define TIM_DMABase_CCR1 (0x0000000D)
mbed_official 330:c80ac197fa6a 551 #define TIM_DMABase_CCR2 (0x0000000E)
mbed_official 330:c80ac197fa6a 552 #define TIM_DMABase_CCR3 (0x0000000F)
mbed_official 330:c80ac197fa6a 553 #define TIM_DMABase_CCR4 (0x00000010)
mbed_official 330:c80ac197fa6a 554 #define TIM_DMABase_BDTR (0x00000011)
mbed_official 330:c80ac197fa6a 555 #define TIM_DMABase_DCR (0x00000012)
mbed_official 330:c80ac197fa6a 556 #define TIM_DMABase_CCMR3 (0x00000015)
mbed_official 330:c80ac197fa6a 557 #define TIM_DMABase_CCR5 (0x00000016)
mbed_official 330:c80ac197fa6a 558 #define TIM_DMABase_CCR6 (0x00000017)
mbed_official 330:c80ac197fa6a 559 #define TIM_DMABase_OR (0x00000018)
mbed_official 330:c80ac197fa6a 560 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
mbed_official 330:c80ac197fa6a 561 ((BASE) == TIM_DMABase_CR2) || \
mbed_official 330:c80ac197fa6a 562 ((BASE) == TIM_DMABase_SMCR) || \
mbed_official 330:c80ac197fa6a 563 ((BASE) == TIM_DMABase_DIER) || \
mbed_official 330:c80ac197fa6a 564 ((BASE) == TIM_DMABase_SR) || \
mbed_official 330:c80ac197fa6a 565 ((BASE) == TIM_DMABase_EGR) || \
mbed_official 330:c80ac197fa6a 566 ((BASE) == TIM_DMABase_CCMR1) || \
mbed_official 330:c80ac197fa6a 567 ((BASE) == TIM_DMABase_CCMR2) || \
mbed_official 330:c80ac197fa6a 568 ((BASE) == TIM_DMABase_CCER) || \
mbed_official 330:c80ac197fa6a 569 ((BASE) == TIM_DMABase_CNT) || \
mbed_official 330:c80ac197fa6a 570 ((BASE) == TIM_DMABase_PSC) || \
mbed_official 330:c80ac197fa6a 571 ((BASE) == TIM_DMABase_ARR) || \
mbed_official 330:c80ac197fa6a 572 ((BASE) == TIM_DMABase_RCR) || \
mbed_official 330:c80ac197fa6a 573 ((BASE) == TIM_DMABase_CCR1) || \
mbed_official 330:c80ac197fa6a 574 ((BASE) == TIM_DMABase_CCR2) || \
mbed_official 330:c80ac197fa6a 575 ((BASE) == TIM_DMABase_CCR3) || \
mbed_official 330:c80ac197fa6a 576 ((BASE) == TIM_DMABase_CCR4) || \
mbed_official 330:c80ac197fa6a 577 ((BASE) == TIM_DMABase_BDTR) || \
mbed_official 330:c80ac197fa6a 578 ((BASE) == TIM_DMABase_CCMR3) || \
mbed_official 330:c80ac197fa6a 579 ((BASE) == TIM_DMABase_CCR5) || \
mbed_official 330:c80ac197fa6a 580 ((BASE) == TIM_DMABase_CCR6) || \
mbed_official 330:c80ac197fa6a 581 ((BASE) == TIM_DMABase_OR))
mbed_official 330:c80ac197fa6a 582 /**
mbed_official 330:c80ac197fa6a 583 * @}
mbed_official 330:c80ac197fa6a 584 */
mbed_official 330:c80ac197fa6a 585 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
mbed_official 330:c80ac197fa6a 586 /* STM32F302xC || STM32F303xC || STM32F358xx || */
mbed_official 330:c80ac197fa6a 587 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
mbed_official 330:c80ac197fa6a 588 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
mbed_official 330:c80ac197fa6a 589
mbed_official 330:c80ac197fa6a 590 #if defined(STM32F302xE) || \
mbed_official 330:c80ac197fa6a 591 defined(STM32F302xC) || \
mbed_official 330:c80ac197fa6a 592 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
mbed_official 330:c80ac197fa6a 593 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
mbed_official 330:c80ac197fa6a 594 /** @defgroup TIMEx_Remap TIM Extended Remapping
mbed_official 330:c80ac197fa6a 595 * @{
mbed_official 330:c80ac197fa6a 596 */
mbed_official 330:c80ac197fa6a 597 #define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
mbed_official 330:c80ac197fa6a 598 #define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
mbed_official 330:c80ac197fa6a 599 #define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
mbed_official 330:c80ac197fa6a 600 #define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
mbed_official 330:c80ac197fa6a 601 #define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
mbed_official 330:c80ac197fa6a 602 #define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
mbed_official 330:c80ac197fa6a 603 #define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
mbed_official 330:c80ac197fa6a 604 #define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
mbed_official 330:c80ac197fa6a 605
mbed_official 330:c80ac197fa6a 606 #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\
mbed_official 330:c80ac197fa6a 607 ((REMAP) == TIM_TIM1_ADC1_AWD1) ||\
mbed_official 330:c80ac197fa6a 608 ((REMAP) == TIM_TIM1_ADC1_AWD2) ||\
mbed_official 330:c80ac197fa6a 609 ((REMAP) == TIM_TIM1_ADC1_AWD3) ||\
mbed_official 330:c80ac197fa6a 610 ((REMAP) == TIM_TIM16_GPIO) ||\
mbed_official 330:c80ac197fa6a 611 ((REMAP) == TIM_TIM16_RTC) ||\
mbed_official 330:c80ac197fa6a 612 ((REMAP) == TIM_TIM16_HSE) ||\
mbed_official 330:c80ac197fa6a 613 ((REMAP) == TIM_TIM16_MCO))
mbed_official 330:c80ac197fa6a 614 /**
mbed_official 330:c80ac197fa6a 615 * @}
mbed_official 330:c80ac197fa6a 616 */
mbed_official 330:c80ac197fa6a 617 #endif /* STM32F302xE || */
mbed_official 330:c80ac197fa6a 618 /* STM32F302xC || */
mbed_official 330:c80ac197fa6a 619 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
mbed_official 330:c80ac197fa6a 620 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
mbed_official 330:c80ac197fa6a 621
mbed_official 330:c80ac197fa6a 622 #if defined(STM32F303xC) || defined(STM32F358xx)
mbed_official 330:c80ac197fa6a 623 /** @defgroup TIMEx_Remap TIM Extended Remapping 1
mbed_official 330:c80ac197fa6a 624 * @{
mbed_official 330:c80ac197fa6a 625 */
mbed_official 330:c80ac197fa6a 626 #define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
mbed_official 330:c80ac197fa6a 627 #define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
mbed_official 330:c80ac197fa6a 628 #define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
mbed_official 330:c80ac197fa6a 629 #define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
mbed_official 330:c80ac197fa6a 630 #define TIM_TIM8_ADC2_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
mbed_official 330:c80ac197fa6a 631 #define TIM_TIM8_ADC2_AWD1 (0x00000001) /* !< TIM8_ETR is connected to ADC2 AWD1 */
mbed_official 330:c80ac197fa6a 632 #define TIM_TIM8_ADC2_AWD2 (0x00000002) /* !< TIM8_ETR is connected to ADC2 AWD2 */
mbed_official 330:c80ac197fa6a 633 #define TIM_TIM8_ADC2_AWD3 (0x00000003) /* !< TIM8_ETR is connected to ADC2 AWD3 */
mbed_official 330:c80ac197fa6a 634 #define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
mbed_official 330:c80ac197fa6a 635 #define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
mbed_official 330:c80ac197fa6a 636 #define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
mbed_official 330:c80ac197fa6a 637 #define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
mbed_official 330:c80ac197fa6a 638
mbed_official 330:c80ac197fa6a 639 #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
mbed_official 330:c80ac197fa6a 640 ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
mbed_official 330:c80ac197fa6a 641 ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
mbed_official 330:c80ac197fa6a 642 ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
mbed_official 330:c80ac197fa6a 643 ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
mbed_official 330:c80ac197fa6a 644 ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
mbed_official 330:c80ac197fa6a 645 ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
mbed_official 330:c80ac197fa6a 646 ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
mbed_official 330:c80ac197fa6a 647 ((REMAP1) == TIM_TIM16_GPIO) ||\
mbed_official 330:c80ac197fa6a 648 ((REMAP1) == TIM_TIM16_RTC) ||\
mbed_official 330:c80ac197fa6a 649 ((REMAP1) == TIM_TIM16_HSE) ||\
mbed_official 330:c80ac197fa6a 650 ((REMAP1) == TIM_TIM16_MCO))
mbed_official 330:c80ac197fa6a 651 /**
mbed_official 330:c80ac197fa6a 652 * @}
mbed_official 330:c80ac197fa6a 653 */
mbed_official 330:c80ac197fa6a 654
mbed_official 330:c80ac197fa6a 655 /** @defgroup TIMEx_Remap2 TIM Extended Remapping 2
mbed_official 330:c80ac197fa6a 656 * @{
mbed_official 330:c80ac197fa6a 657 */
mbed_official 330:c80ac197fa6a 658 #define TIM_TIM1_ADC4_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
mbed_official 330:c80ac197fa6a 659 #define TIM_TIM1_ADC4_AWD1 (0x00000004) /* !< TIM1_ETR is connected to ADC4 AWD1 */
mbed_official 330:c80ac197fa6a 660 #define TIM_TIM1_ADC4_AWD2 (0x00000008) /* !< TIM1_ETR is connected to ADC4 AWD2 */
mbed_official 330:c80ac197fa6a 661 #define TIM_TIM1_ADC4_AWD3 (0x0000000C) /* !< TIM1_ETR is connected to ADC4 AWD3 */
mbed_official 330:c80ac197fa6a 662 #define TIM_TIM8_ADC3_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
mbed_official 330:c80ac197fa6a 663 #define TIM_TIM8_ADC3_AWD1 (0x00000004) /* !< TIM8_ETR is connected to ADC3 AWD1 */
mbed_official 330:c80ac197fa6a 664 #define TIM_TIM8_ADC3_AWD2 (0x00000008) /* !< TIM8_ETR is connected to ADC3 AWD2 */
mbed_official 330:c80ac197fa6a 665 #define TIM_TIM8_ADC3_AWD3 (0x0000000C) /* !< TIM8_ETR is connected to ADC3 AWD3 */
mbed_official 330:c80ac197fa6a 666 #define TIM_TIM16_NONE (0x00000000) /* !< Non significant value for TIM16 */
mbed_official 330:c80ac197fa6a 667
mbed_official 330:c80ac197fa6a 668 #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
mbed_official 330:c80ac197fa6a 669 ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
mbed_official 330:c80ac197fa6a 670 ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
mbed_official 330:c80ac197fa6a 671 ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
mbed_official 330:c80ac197fa6a 672 ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
mbed_official 330:c80ac197fa6a 673 ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
mbed_official 330:c80ac197fa6a 674 ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
mbed_official 330:c80ac197fa6a 675 ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
mbed_official 330:c80ac197fa6a 676 ((REMAP2) == TIM_TIM16_NONE))
mbed_official 330:c80ac197fa6a 677 /**
mbed_official 330:c80ac197fa6a 678 * @}
mbed_official 330:c80ac197fa6a 679 */
mbed_official 330:c80ac197fa6a 680 #endif /* STM32F303xC || STM32F358xx */
mbed_official 330:c80ac197fa6a 681
mbed_official 330:c80ac197fa6a 682 #if defined(STM32F303xE) || defined(STM32F398xx)
mbed_official 330:c80ac197fa6a 683 /** @defgroup TIMEx_Remap TIM Extended Remapping 1
mbed_official 330:c80ac197fa6a 684 * @{
mbed_official 330:c80ac197fa6a 685 */
mbed_official 330:c80ac197fa6a 686 #define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
mbed_official 330:c80ac197fa6a 687 #define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
mbed_official 330:c80ac197fa6a 688 #define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
mbed_official 330:c80ac197fa6a 689 #define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
mbed_official 330:c80ac197fa6a 690 #define TIM_TIM8_ADC2_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
mbed_official 330:c80ac197fa6a 691 #define TIM_TIM8_ADC2_AWD1 (0x00000001) /* !< TIM8_ETR is connected to ADC2 AWD1 */
mbed_official 330:c80ac197fa6a 692 #define TIM_TIM8_ADC2_AWD2 (0x00000002) /* !< TIM8_ETR is connected to ADC2 AWD2 */
mbed_official 330:c80ac197fa6a 693 #define TIM_TIM8_ADC2_AWD3 (0x00000003) /* !< TIM8_ETR is connected to ADC2 AWD3 */
mbed_official 330:c80ac197fa6a 694 #define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
mbed_official 330:c80ac197fa6a 695 #define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
mbed_official 330:c80ac197fa6a 696 #define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
mbed_official 330:c80ac197fa6a 697 #define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
mbed_official 330:c80ac197fa6a 698 #define TIM_TIM20_ADC3_NONE (0x00000000) /* !< TIM20_ETR is not connected to any AWD (analog watchdog) */
mbed_official 330:c80ac197fa6a 699 #define TIM_TIM20_ADC3_AWD1 (0x00000001) /* !< TIM20_ETR is connected to ADC3 AWD1 */
mbed_official 330:c80ac197fa6a 700 #define TIM_TIM20_ADC3_AWD2 (0x00000002) /* !< TIM20_ETR is connected to ADC3 AWD2 */
mbed_official 330:c80ac197fa6a 701 #define TIM_TIM20_ADC3_AWD3 (0x00000003) /* !< TIM20_ETR is connected to ADC3 AWD3 */
mbed_official 330:c80ac197fa6a 702
mbed_official 330:c80ac197fa6a 703 #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
mbed_official 330:c80ac197fa6a 704 ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
mbed_official 330:c80ac197fa6a 705 ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
mbed_official 330:c80ac197fa6a 706 ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
mbed_official 330:c80ac197fa6a 707 ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
mbed_official 330:c80ac197fa6a 708 ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
mbed_official 330:c80ac197fa6a 709 ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
mbed_official 330:c80ac197fa6a 710 ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
mbed_official 330:c80ac197fa6a 711 ((REMAP1) == TIM_TIM16_GPIO) ||\
mbed_official 330:c80ac197fa6a 712 ((REMAP1) == TIM_TIM16_RTC) ||\
mbed_official 330:c80ac197fa6a 713 ((REMAP1) == TIM_TIM16_HSE) ||\
mbed_official 330:c80ac197fa6a 714 ((REMAP1) == TIM_TIM16_MCO) ||\
mbed_official 330:c80ac197fa6a 715 ((REMAP1) == TIM_TIM20_ADC3_NONE) ||\
mbed_official 330:c80ac197fa6a 716 ((REMAP1) == TIM_TIM20_ADC3_AWD1) ||\
mbed_official 330:c80ac197fa6a 717 ((REMAP1) == TIM_TIM20_ADC3_AWD2) ||\
mbed_official 330:c80ac197fa6a 718 ((REMAP1) == TIM_TIM20_ADC3_AWD3))
mbed_official 330:c80ac197fa6a 719 /**
mbed_official 330:c80ac197fa6a 720 * @}
mbed_official 330:c80ac197fa6a 721 */
mbed_official 330:c80ac197fa6a 722
mbed_official 330:c80ac197fa6a 723 /** @defgroup TIMEx_Remap2 TIM Extended Remapping 2
mbed_official 330:c80ac197fa6a 724 * @{
mbed_official 330:c80ac197fa6a 725 */
mbed_official 330:c80ac197fa6a 726 #define TIM_TIM1_ADC4_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
mbed_official 330:c80ac197fa6a 727 #define TIM_TIM1_ADC4_AWD1 (0x00000004) /* !< TIM1_ETR is connected to ADC4 AWD1 */
mbed_official 330:c80ac197fa6a 728 #define TIM_TIM1_ADC4_AWD2 (0x00000008) /* !< TIM1_ETR is connected to ADC4 AWD2 */
mbed_official 330:c80ac197fa6a 729 #define TIM_TIM1_ADC4_AWD3 (0x0000000C) /* !< TIM1_ETR is connected to ADC4 AWD3 */
mbed_official 330:c80ac197fa6a 730 #define TIM_TIM8_ADC3_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
mbed_official 330:c80ac197fa6a 731 #define TIM_TIM8_ADC3_AWD1 (0x00000004) /* !< TIM8_ETR is connected to ADC3 AWD1 */
mbed_official 330:c80ac197fa6a 732 #define TIM_TIM8_ADC3_AWD2 (0x00000008) /* !< TIM8_ETR is connected to ADC3 AWD2 */
mbed_official 330:c80ac197fa6a 733 #define TIM_TIM8_ADC3_AWD3 (0x0000000C) /* !< TIM8_ETR is connected to ADC3 AWD3 */
mbed_official 330:c80ac197fa6a 734 #define TIM_TIM16_NONE (0x00000000) /* !< Non significant value for TIM16 */
mbed_official 330:c80ac197fa6a 735 #define TIM_TIM20_ADC4_NONE (0x00000000) /* !< TIM20_ETR is not connected to any AWD (analog watchdog) */
mbed_official 330:c80ac197fa6a 736 #define TIM_TIM20_ADC4_AWD1 (0x00000004) /* !< TIM20_ETR is connected to ADC4 AWD1 */
mbed_official 330:c80ac197fa6a 737 #define TIM_TIM20_ADC4_AWD2 (0x00000008) /* !< TIM20_ETR is connected to ADC4 AWD2 */
mbed_official 330:c80ac197fa6a 738 #define TIM_TIM20_ADC4_AWD3 (0x0000000C) /* !< TIM20_ETR is connected to ADC4 AWD3 */
mbed_official 330:c80ac197fa6a 739
mbed_official 330:c80ac197fa6a 740 #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
mbed_official 330:c80ac197fa6a 741 ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
mbed_official 330:c80ac197fa6a 742 ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
mbed_official 330:c80ac197fa6a 743 ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
mbed_official 330:c80ac197fa6a 744 ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
mbed_official 330:c80ac197fa6a 745 ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
mbed_official 330:c80ac197fa6a 746 ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
mbed_official 330:c80ac197fa6a 747 ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
mbed_official 330:c80ac197fa6a 748 ((REMAP2) == TIM_TIM16_NONE) ||\
mbed_official 330:c80ac197fa6a 749 ((REMAP2) == TIM_TIM20_ADC4_NONE) ||\
mbed_official 330:c80ac197fa6a 750 ((REMAP2) == TIM_TIM20_ADC4_AWD1) ||\
mbed_official 330:c80ac197fa6a 751 ((REMAP2) == TIM_TIM20_ADC4_AWD2) ||\
mbed_official 330:c80ac197fa6a 752 ((REMAP2) == TIM_TIM20_ADC4_AWD3))
mbed_official 330:c80ac197fa6a 753 /**
mbed_official 330:c80ac197fa6a 754 * @}
mbed_official 330:c80ac197fa6a 755 */
mbed_official 330:c80ac197fa6a 756 #endif /* STM32F303xE || STM32F398xx */
mbed_official 330:c80ac197fa6a 757
mbed_official 330:c80ac197fa6a 758
mbed_official 330:c80ac197fa6a 759 #if defined(STM32F373xC) || defined(STM32F378xx)
mbed_official 330:c80ac197fa6a 760 /** @defgroup TIMEx_Remap TIM Extended remapping
mbed_official 330:c80ac197fa6a 761 * @{
mbed_official 330:c80ac197fa6a 762 */
mbed_official 330:c80ac197fa6a 763
mbed_official 330:c80ac197fa6a 764 #define TIM_TIM2_TIM8_TRGO (0x00000000) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */
mbed_official 330:c80ac197fa6a 765 #define TIM_TIM2_ETH_PTP (0x00000400) /*!< PTP trigger output is connected to TIM2_ITR1 */
mbed_official 330:c80ac197fa6a 766 #define TIM_TIM2_USBFS_SOF (0x00000800) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */
mbed_official 330:c80ac197fa6a 767 #define TIM_TIM2_USBHS_SOF (0x00000C00) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */
mbed_official 330:c80ac197fa6a 768 #define TIM_TIM14_GPIO (0x00000000) /* !< TIM14 TI1 is connected to GPIO */
mbed_official 330:c80ac197fa6a 769 #define TIM_TIM14_RTC (0x00000001) /* !< TIM14 TI1 is connected to RTC_clock */
mbed_official 330:c80ac197fa6a 770 #define TIM_TIM14_HSE (0x00000002) /* !< TIM14 TI1 is connected to HSE/32 */
mbed_official 330:c80ac197fa6a 771 #define TIM_TIM14_MCO (0x00000003) /* !< TIM14 TI1 is connected to MCO */
mbed_official 330:c80ac197fa6a 772
mbed_official 330:c80ac197fa6a 773 #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM2_TIM8_TRGO) ||\
mbed_official 330:c80ac197fa6a 774 ((REMAP) == TIM_TIM2_ETH_PTP) ||\
mbed_official 330:c80ac197fa6a 775 ((REMAP) == TIM_TIM2_USBFS_SOF) ||\
mbed_official 330:c80ac197fa6a 776 ((REMAP) == TIM_TIM2_USBHS_SOF) ||\
mbed_official 330:c80ac197fa6a 777 ((REMAP) == TIM_TIM14_GPIO) ||\
mbed_official 330:c80ac197fa6a 778 ((REMAP) == TIM_TIM14_RTC) ||\
mbed_official 330:c80ac197fa6a 779 ((REMAP) == TIM_TIM14_HSE) ||\
mbed_official 330:c80ac197fa6a 780 ((REMAP) == TIM_TIM14_MCO))
mbed_official 330:c80ac197fa6a 781
mbed_official 330:c80ac197fa6a 782 /**
mbed_official 330:c80ac197fa6a 783 * @}
mbed_official 330:c80ac197fa6a 784 */
mbed_official 330:c80ac197fa6a 785 #endif /* STM32F373xC || STM32F378xx */
mbed_official 330:c80ac197fa6a 786
mbed_official 330:c80ac197fa6a 787 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
mbed_official 330:c80ac197fa6a 788 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
mbed_official 330:c80ac197fa6a 789 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
mbed_official 330:c80ac197fa6a 790 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
mbed_official 330:c80ac197fa6a 791 /** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
mbed_official 330:c80ac197fa6a 792 * @{
mbed_official 330:c80ac197fa6a 793 */
mbed_official 330:c80ac197fa6a 794 #define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
mbed_official 330:c80ac197fa6a 795 #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
mbed_official 330:c80ac197fa6a 796 #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
mbed_official 330:c80ac197fa6a 797 #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
mbed_official 330:c80ac197fa6a 798
mbed_official 330:c80ac197fa6a 799 #define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
mbed_official 330:c80ac197fa6a 800 /**
mbed_official 330:c80ac197fa6a 801 * @}
mbed_official 330:c80ac197fa6a 802 */
mbed_official 330:c80ac197fa6a 803 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
mbed_official 330:c80ac197fa6a 804 /* STM32F302xC || STM32F303xC || STM32F358xx || */
mbed_official 330:c80ac197fa6a 805 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
mbed_official 330:c80ac197fa6a 806 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
mbed_official 330:c80ac197fa6a 807
mbed_official 330:c80ac197fa6a 808 /** @defgroup TIM_Clock_Filter TIM Clock Filter
mbed_official 330:c80ac197fa6a 809 * @{
mbed_official 330:c80ac197fa6a 810 */
mbed_official 330:c80ac197fa6a 811 #define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF)
mbed_official 330:c80ac197fa6a 812 /**
mbed_official 330:c80ac197fa6a 813 * @}
mbed_official 330:c80ac197fa6a 814 */
mbed_official 330:c80ac197fa6a 815
mbed_official 330:c80ac197fa6a 816 /**
mbed_official 330:c80ac197fa6a 817 * @}
mbed_official 330:c80ac197fa6a 818 */
mbed_official 330:c80ac197fa6a 819
mbed_official 330:c80ac197fa6a 820 /* Exported macro ------------------------------------------------------------*/
mbed_official 330:c80ac197fa6a 821 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
mbed_official 330:c80ac197fa6a 822 * @{
mbed_official 330:c80ac197fa6a 823 */
mbed_official 330:c80ac197fa6a 824
mbed_official 330:c80ac197fa6a 825 #if defined(STM32F373xC) || defined(STM32F378xx)
mbed_official 330:c80ac197fa6a 826 /**
mbed_official 330:c80ac197fa6a 827 * @brief Sets the TIM Capture Compare Register value on runtime without
mbed_official 330:c80ac197fa6a 828 * calling another time ConfigChannel function.
mbed_official 330:c80ac197fa6a 829 * @param __HANDLE__: TIM handle.
mbed_official 330:c80ac197fa6a 830 * @param __CHANNEL__ : TIM Channels to be configured.
mbed_official 330:c80ac197fa6a 831 * This parameter can be one of the following values:
mbed_official 330:c80ac197fa6a 832 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 330:c80ac197fa6a 833 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 330:c80ac197fa6a 834 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 330:c80ac197fa6a 835 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 330:c80ac197fa6a 836 * @param __COMPARE__: specifies the Capture Compare register new value.
mbed_official 330:c80ac197fa6a 837 * @retval None
mbed_official 330:c80ac197fa6a 838 */
mbed_official 330:c80ac197fa6a 839 #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
mbed_official 330:c80ac197fa6a 840 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
mbed_official 330:c80ac197fa6a 841
mbed_official 330:c80ac197fa6a 842 /**
mbed_official 330:c80ac197fa6a 843 * @brief Gets the TIM Capture Compare Register value on runtime
mbed_official 330:c80ac197fa6a 844 * @param __HANDLE__: TIM handle.
mbed_official 330:c80ac197fa6a 845 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
mbed_official 330:c80ac197fa6a 846 * This parameter can be one of the following values:
mbed_official 330:c80ac197fa6a 847 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
mbed_official 330:c80ac197fa6a 848 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
mbed_official 330:c80ac197fa6a 849 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
mbed_official 330:c80ac197fa6a 850 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
mbed_official 330:c80ac197fa6a 851 * @retval None
mbed_official 330:c80ac197fa6a 852 */
mbed_official 330:c80ac197fa6a 853 #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
mbed_official 330:c80ac197fa6a 854 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
mbed_official 330:c80ac197fa6a 855 #endif /* STM32F373xC || STM32F378xx */
mbed_official 330:c80ac197fa6a 856
mbed_official 330:c80ac197fa6a 857 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
mbed_official 330:c80ac197fa6a 858 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
mbed_official 330:c80ac197fa6a 859 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
mbed_official 330:c80ac197fa6a 860 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
mbed_official 330:c80ac197fa6a 861 /**
mbed_official 330:c80ac197fa6a 862 * @brief Sets the TIM Capture Compare Register value on runtime without
mbed_official 330:c80ac197fa6a 863 * calling another time ConfigChannel function.
mbed_official 330:c80ac197fa6a 864 * @param __HANDLE__: TIM handle.
mbed_official 330:c80ac197fa6a 865 * @param __CHANNEL__ : TIM Channels to be configured.
mbed_official 330:c80ac197fa6a 866 * This parameter can be one of the following values:
mbed_official 330:c80ac197fa6a 867 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 330:c80ac197fa6a 868 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 330:c80ac197fa6a 869 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 330:c80ac197fa6a 870 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 330:c80ac197fa6a 871 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
mbed_official 330:c80ac197fa6a 872 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
mbed_official 330:c80ac197fa6a 873 * @param __COMPARE__: specifies the Capture Compare register new value.
mbed_official 330:c80ac197fa6a 874 * @retval None
mbed_official 330:c80ac197fa6a 875 */
mbed_official 330:c80ac197fa6a 876 #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
mbed_official 330:c80ac197fa6a 877 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
mbed_official 330:c80ac197fa6a 878 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
mbed_official 330:c80ac197fa6a 879 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
mbed_official 330:c80ac197fa6a 880 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
mbed_official 330:c80ac197fa6a 881 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
mbed_official 330:c80ac197fa6a 882 ((__HANDLE__)->Instance->CCR6 |= (__COMPARE__)))
mbed_official 330:c80ac197fa6a 883
mbed_official 330:c80ac197fa6a 884 /**
mbed_official 330:c80ac197fa6a 885 * @brief Gets the TIM Capture Compare Register value on runtime
mbed_official 330:c80ac197fa6a 886 * @param __HANDLE__: TIM handle.
mbed_official 330:c80ac197fa6a 887 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
mbed_official 330:c80ac197fa6a 888 * This parameter can be one of the following values:
mbed_official 330:c80ac197fa6a 889 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
mbed_official 330:c80ac197fa6a 890 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
mbed_official 330:c80ac197fa6a 891 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
mbed_official 330:c80ac197fa6a 892 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
mbed_official 330:c80ac197fa6a 893 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
mbed_official 330:c80ac197fa6a 894 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
mbed_official 330:c80ac197fa6a 895 * @retval None
mbed_official 330:c80ac197fa6a 896 */
mbed_official 330:c80ac197fa6a 897 #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
mbed_official 330:c80ac197fa6a 898 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
mbed_official 330:c80ac197fa6a 899 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
mbed_official 330:c80ac197fa6a 900 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
mbed_official 330:c80ac197fa6a 901 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
mbed_official 330:c80ac197fa6a 902 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
mbed_official 330:c80ac197fa6a 903 ((__HANDLE__)->Instance->CCR6))
mbed_official 330:c80ac197fa6a 904 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
mbed_official 330:c80ac197fa6a 905 /* STM32F302xC || STM32F303xC || STM32F358xx || */
mbed_official 330:c80ac197fa6a 906 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
mbed_official 330:c80ac197fa6a 907 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
mbed_official 330:c80ac197fa6a 908 /**
mbed_official 330:c80ac197fa6a 909 * @}
mbed_official 330:c80ac197fa6a 910 */
mbed_official 330:c80ac197fa6a 911
mbed_official 330:c80ac197fa6a 912 /* Exported functions --------------------------------------------------------*/
mbed_official 330:c80ac197fa6a 913 /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
mbed_official 330:c80ac197fa6a 914 * @{
mbed_official 330:c80ac197fa6a 915 */
mbed_official 330:c80ac197fa6a 916
mbed_official 330:c80ac197fa6a 917 /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
mbed_official 330:c80ac197fa6a 918 * @brief Timer Hall Sensor functions
mbed_official 330:c80ac197fa6a 919 * @{
mbed_official 330:c80ac197fa6a 920 */
mbed_official 330:c80ac197fa6a 921 /* Timer Hall Sensor functions **********************************************/
mbed_official 330:c80ac197fa6a 922 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
mbed_official 330:c80ac197fa6a 923 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
mbed_official 330:c80ac197fa6a 924
mbed_official 330:c80ac197fa6a 925 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
mbed_official 330:c80ac197fa6a 926 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official 330:c80ac197fa6a 927
mbed_official 330:c80ac197fa6a 928 /* Blocking mode: Polling */
mbed_official 330:c80ac197fa6a 929 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
mbed_official 330:c80ac197fa6a 930 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
mbed_official 330:c80ac197fa6a 931 /* Non-Blocking mode: Interrupt */
mbed_official 330:c80ac197fa6a 932 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
mbed_official 330:c80ac197fa6a 933 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
mbed_official 330:c80ac197fa6a 934 /* Non-Blocking mode: DMA */
mbed_official 330:c80ac197fa6a 935 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
mbed_official 330:c80ac197fa6a 936 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
mbed_official 330:c80ac197fa6a 937 /**
mbed_official 330:c80ac197fa6a 938 * @}
mbed_official 330:c80ac197fa6a 939 */
mbed_official 330:c80ac197fa6a 940
mbed_official 330:c80ac197fa6a 941 /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
mbed_official 330:c80ac197fa6a 942 * @brief Timer Complementary Output Compare functions
mbed_official 330:c80ac197fa6a 943 * @{
mbed_official 330:c80ac197fa6a 944 */
mbed_official 330:c80ac197fa6a 945 /* Timer Complementary Output Compare functions *****************************/
mbed_official 330:c80ac197fa6a 946 /* Blocking mode: Polling */
mbed_official 330:c80ac197fa6a 947 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official 330:c80ac197fa6a 948 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official 330:c80ac197fa6a 949
mbed_official 330:c80ac197fa6a 950 /* Non-Blocking mode: Interrupt */
mbed_official 330:c80ac197fa6a 951 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official 330:c80ac197fa6a 952 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official 330:c80ac197fa6a 953
mbed_official 330:c80ac197fa6a 954 /* Non-Blocking mode: DMA */
mbed_official 330:c80ac197fa6a 955 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
mbed_official 330:c80ac197fa6a 956 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official 330:c80ac197fa6a 957 /**
mbed_official 330:c80ac197fa6a 958 * @}
mbed_official 330:c80ac197fa6a 959 */
mbed_official 330:c80ac197fa6a 960
mbed_official 330:c80ac197fa6a 961 /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
mbed_official 330:c80ac197fa6a 962 * @brief Timer Complementary PWM functions
mbed_official 330:c80ac197fa6a 963 * @{
mbed_official 330:c80ac197fa6a 964 */
mbed_official 330:c80ac197fa6a 965 /* Timer Complementary PWM functions ****************************************/
mbed_official 330:c80ac197fa6a 966 /* Blocking mode: Polling */
mbed_official 330:c80ac197fa6a 967 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official 330:c80ac197fa6a 968 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official 330:c80ac197fa6a 969
mbed_official 330:c80ac197fa6a 970 /* Non-Blocking mode: Interrupt */
mbed_official 330:c80ac197fa6a 971 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official 330:c80ac197fa6a 972 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official 330:c80ac197fa6a 973 /* Non-Blocking mode: DMA */
mbed_official 330:c80ac197fa6a 974 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
mbed_official 330:c80ac197fa6a 975 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official 330:c80ac197fa6a 976 /**
mbed_official 330:c80ac197fa6a 977 * @}
mbed_official 330:c80ac197fa6a 978 */
mbed_official 330:c80ac197fa6a 979
mbed_official 330:c80ac197fa6a 980 /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
mbed_official 330:c80ac197fa6a 981 * @brief Timer Complementary One Pulse functions
mbed_official 330:c80ac197fa6a 982 * @{
mbed_official 330:c80ac197fa6a 983 */
mbed_official 330:c80ac197fa6a 984 /* Timer Complementary One Pulse functions **********************************/
mbed_official 330:c80ac197fa6a 985 /* Blocking mode: Polling */
mbed_official 330:c80ac197fa6a 986 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official 330:c80ac197fa6a 987 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official 330:c80ac197fa6a 988
mbed_official 330:c80ac197fa6a 989 /* Non-Blocking mode: Interrupt */
mbed_official 330:c80ac197fa6a 990 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official 330:c80ac197fa6a 991 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official 330:c80ac197fa6a 992 /**
mbed_official 330:c80ac197fa6a 993 * @}
mbed_official 330:c80ac197fa6a 994 */
mbed_official 330:c80ac197fa6a 995
mbed_official 330:c80ac197fa6a 996 /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
mbed_official 330:c80ac197fa6a 997 * @brief Peripheral Control functions
mbed_official 330:c80ac197fa6a 998 * @{
mbed_official 330:c80ac197fa6a 999 */
mbed_official 330:c80ac197fa6a 1000 /* Extended Control functions ************************************************/
mbed_official 330:c80ac197fa6a 1001 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
mbed_official 330:c80ac197fa6a 1002 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
mbed_official 330:c80ac197fa6a 1003 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
mbed_official 330:c80ac197fa6a 1004 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
mbed_official 330:c80ac197fa6a 1005 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
mbed_official 330:c80ac197fa6a 1006
mbed_official 330:c80ac197fa6a 1007 #if defined(STM32F303xE) || defined(STM32F398xx) || \
mbed_official 330:c80ac197fa6a 1008 defined(STM32F303xC) || defined(STM32F358xx)
mbed_official 330:c80ac197fa6a 1009 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2);
mbed_official 330:c80ac197fa6a 1010 #endif /* STM32F303xE || STM32F398xx || */
mbed_official 330:c80ac197fa6a 1011 /* STM32F303xC || STM32F358xx */
mbed_official 330:c80ac197fa6a 1012
mbed_official 330:c80ac197fa6a 1013 #if defined(STM32F302xE) || \
mbed_official 330:c80ac197fa6a 1014 defined(STM32F302xC) || \
mbed_official 330:c80ac197fa6a 1015 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
mbed_official 330:c80ac197fa6a 1016 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
mbed_official 330:c80ac197fa6a 1017 defined(STM32F373xC) || defined(STM32F378xx)
mbed_official 330:c80ac197fa6a 1018 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
mbed_official 330:c80ac197fa6a 1019 #endif /* STM32F302xE || */
mbed_official 330:c80ac197fa6a 1020 /* STM32F302xC || */
mbed_official 330:c80ac197fa6a 1021 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
mbed_official 330:c80ac197fa6a 1022 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
mbed_official 330:c80ac197fa6a 1023 /* STM32F373xC || STM32F378xx */
mbed_official 330:c80ac197fa6a 1024
mbed_official 330:c80ac197fa6a 1025 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
mbed_official 330:c80ac197fa6a 1026 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
mbed_official 330:c80ac197fa6a 1027 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
mbed_official 330:c80ac197fa6a 1028 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
mbed_official 330:c80ac197fa6a 1029 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
mbed_official 330:c80ac197fa6a 1030 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
mbed_official 330:c80ac197fa6a 1031 /* STM32F302xC || STM32F303xC || STM32F358xx || */
mbed_official 330:c80ac197fa6a 1032 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
mbed_official 330:c80ac197fa6a 1033 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
mbed_official 330:c80ac197fa6a 1034 /**
mbed_official 330:c80ac197fa6a 1035 * @}
mbed_official 330:c80ac197fa6a 1036 */
mbed_official 330:c80ac197fa6a 1037
mbed_official 330:c80ac197fa6a 1038 /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
mbed_official 330:c80ac197fa6a 1039 * @brief Extended Callbacks functions
mbed_official 330:c80ac197fa6a 1040 * @{
mbed_official 330:c80ac197fa6a 1041 */
mbed_official 330:c80ac197fa6a 1042 /* Extended Callback *********************************************************/
mbed_official 330:c80ac197fa6a 1043 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
mbed_official 330:c80ac197fa6a 1044 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
mbed_official 330:c80ac197fa6a 1045 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
mbed_official 330:c80ac197fa6a 1046 /**
mbed_official 330:c80ac197fa6a 1047 * @}
mbed_official 330:c80ac197fa6a 1048 */
mbed_official 330:c80ac197fa6a 1049
mbed_official 330:c80ac197fa6a 1050 /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
mbed_official 330:c80ac197fa6a 1051 * @brief Extended Peripheral State functions
mbed_official 330:c80ac197fa6a 1052 * @{
mbed_official 330:c80ac197fa6a 1053 */
mbed_official 330:c80ac197fa6a 1054 /* Extended Peripheral State functions **************************************/
mbed_official 330:c80ac197fa6a 1055 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
mbed_official 330:c80ac197fa6a 1056 /**
mbed_official 330:c80ac197fa6a 1057 * @}
mbed_official 330:c80ac197fa6a 1058 */
mbed_official 330:c80ac197fa6a 1059
mbed_official 330:c80ac197fa6a 1060 /**
mbed_official 330:c80ac197fa6a 1061 * @}
mbed_official 330:c80ac197fa6a 1062 */
mbed_official 330:c80ac197fa6a 1063
mbed_official 330:c80ac197fa6a 1064 /**
mbed_official 330:c80ac197fa6a 1065 * @}
mbed_official 330:c80ac197fa6a 1066 */
mbed_official 330:c80ac197fa6a 1067
mbed_official 330:c80ac197fa6a 1068 /**
mbed_official 330:c80ac197fa6a 1069 * @}
mbed_official 330:c80ac197fa6a 1070 */
mbed_official 330:c80ac197fa6a 1071
mbed_official 330:c80ac197fa6a 1072 #ifdef __cplusplus
mbed_official 330:c80ac197fa6a 1073 }
mbed_official 330:c80ac197fa6a 1074 #endif
mbed_official 330:c80ac197fa6a 1075
mbed_official 330:c80ac197fa6a 1076
mbed_official 330:c80ac197fa6a 1077 #endif /* __STM32F3xx_HAL_TIM_EX_H */
mbed_official 330:c80ac197fa6a 1078
mbed_official 330:c80ac197fa6a 1079 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/