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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h@630:825f75ca301e, 2015-09-28 (annotated)

Committer:
mbed_official
Date:
Mon Sep 28 10:45:10 2015 +0100
Revision:
630:825f75ca301e
Parent:
441:d2c15dda23c1 
Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10



Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/



NUCLEO_F031K6 : Add new target

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 340:28d1f895c6fe 1 /**
mbed_official 340:28d1f895c6fe 2 ******************************************************************************
mbed_official 340:28d1f895c6fe 3 * @file stm32f0xx_hal_dma.h
mbed_official 340:28d1f895c6fe 4 * @author MCD Application Team
mbed_official 630:825f75ca301e 5 * @version V1.3.0
mbed_official 630:825f75ca301e 6 * @date 26-June-2015
mbed_official 340:28d1f895c6fe 7 * @brief Header file of DMA HAL module.
mbed_official 340:28d1f895c6fe 8 ******************************************************************************
mbed_official 340:28d1f895c6fe 9 * @attention
mbed_official 340:28d1f895c6fe 10 *
mbed_official 630:825f75ca301e 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 340:28d1f895c6fe 12 *
mbed_official 340:28d1f895c6fe 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 340:28d1f895c6fe 14 * are permitted provided that the following conditions are met:
mbed_official 340:28d1f895c6fe 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 340:28d1f895c6fe 16 * this list of conditions and the following disclaimer.
mbed_official 340:28d1f895c6fe 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 340:28d1f895c6fe 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 340:28d1f895c6fe 19 * and/or other materials provided with the distribution.
mbed_official 340:28d1f895c6fe 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 340:28d1f895c6fe 21 * may be used to endorse or promote products derived from this software
mbed_official 340:28d1f895c6fe 22 * without specific prior written permission.
mbed_official 340:28d1f895c6fe 23 *
mbed_official 340:28d1f895c6fe 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 340:28d1f895c6fe 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 340:28d1f895c6fe 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 340:28d1f895c6fe 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 340:28d1f895c6fe 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 340:28d1f895c6fe 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 340:28d1f895c6fe 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 340:28d1f895c6fe 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 340:28d1f895c6fe 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 340:28d1f895c6fe 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 340:28d1f895c6fe 34 *
mbed_official 340:28d1f895c6fe 35 ******************************************************************************
mbed_official 340:28d1f895c6fe 36 */
mbed_official 340:28d1f895c6fe 37
mbed_official 340:28d1f895c6fe 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 340:28d1f895c6fe 39 #ifndef __STM32F0xx_HAL_DMA_H
mbed_official 340:28d1f895c6fe 40 #define __STM32F0xx_HAL_DMA_H
mbed_official 340:28d1f895c6fe 41
mbed_official 340:28d1f895c6fe 42 #ifdef __cplusplus
mbed_official 340:28d1f895c6fe 43 extern "C" {
mbed_official 340:28d1f895c6fe 44 #endif
mbed_official 340:28d1f895c6fe 45
mbed_official 340:28d1f895c6fe 46 /* Includes ------------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 47 #include "stm32f0xx_hal_def.h"
mbed_official 340:28d1f895c6fe 48
mbed_official 340:28d1f895c6fe 49 /** @addtogroup STM32F0xx_HAL_Driver
mbed_official 340:28d1f895c6fe 50 * @{
mbed_official 340:28d1f895c6fe 51 */
mbed_official 340:28d1f895c6fe 52
mbed_official 340:28d1f895c6fe 53 /** @addtogroup DMA
mbed_official 340:28d1f895c6fe 54 * @{
mbed_official 340:28d1f895c6fe 55 */
mbed_official 340:28d1f895c6fe 56
mbed_official 340:28d1f895c6fe 57 /* Exported types ------------------------------------------------------------*/
mbed_official 630:825f75ca301e 58
mbed_official 340:28d1f895c6fe 59 /** @defgroup DMA_Exported_Types DMA Exported Types
mbed_official 340:28d1f895c6fe 60 * @{
mbed_official 340:28d1f895c6fe 61 */
mbed_official 340:28d1f895c6fe 62
mbed_official 340:28d1f895c6fe 63 /**
mbed_official 340:28d1f895c6fe 64 * @brief DMA Configuration Structure definition
mbed_official 340:28d1f895c6fe 65 */
mbed_official 340:28d1f895c6fe 66 typedef struct
mbed_official 340:28d1f895c6fe 67 {
mbed_official 340:28d1f895c6fe 68 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
mbed_official 340:28d1f895c6fe 69 from memory to memory or from peripheral to memory.
mbed_official 340:28d1f895c6fe 70 This parameter can be a value of @ref DMA_Data_transfer_direction */
mbed_official 340:28d1f895c6fe 71
mbed_official 340:28d1f895c6fe 72 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
mbed_official 340:28d1f895c6fe 73 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
mbed_official 340:28d1f895c6fe 74
mbed_official 340:28d1f895c6fe 75 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
mbed_official 340:28d1f895c6fe 76 This parameter can be a value of @ref DMA_Memory_incremented_mode */
mbed_official 340:28d1f895c6fe 77
mbed_official 340:28d1f895c6fe 78 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
mbed_official 340:28d1f895c6fe 79 This parameter can be a value of @ref DMA_Peripheral_data_size */
mbed_official 340:28d1f895c6fe 80
mbed_official 340:28d1f895c6fe 81 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
mbed_official 340:28d1f895c6fe 82 This parameter can be a value of @ref DMA_Memory_data_size */
mbed_official 340:28d1f895c6fe 83
mbed_official 340:28d1f895c6fe 84 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
mbed_official 340:28d1f895c6fe 85 This parameter can be a value of @ref DMA_mode
mbed_official 340:28d1f895c6fe 86 @note The circular buffer mode cannot be used if the memory-to-memory
mbed_official 340:28d1f895c6fe 87 data transfer is configured on the selected Channel */
mbed_official 340:28d1f895c6fe 88
mbed_official 340:28d1f895c6fe 89 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
mbed_official 340:28d1f895c6fe 90 This parameter can be a value of @ref DMA_Priority_level */
mbed_official 340:28d1f895c6fe 91 } DMA_InitTypeDef;
mbed_official 340:28d1f895c6fe 92
mbed_official 340:28d1f895c6fe 93 /**
mbed_official 340:28d1f895c6fe 94 * @brief DMA Configuration enumeration values definition
mbed_official 340:28d1f895c6fe 95 */
mbed_official 340:28d1f895c6fe 96 typedef enum
mbed_official 340:28d1f895c6fe 97 {
mbed_official 340:28d1f895c6fe 98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
mbed_official 340:28d1f895c6fe 99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
mbed_official 340:28d1f895c6fe 100
mbed_official 340:28d1f895c6fe 101 } DMA_ControlTypeDef;
mbed_official 340:28d1f895c6fe 102
mbed_official 340:28d1f895c6fe 103 /**
mbed_official 340:28d1f895c6fe 104 * @brief HAL DMA State structures definition
mbed_official 340:28d1f895c6fe 105 */
mbed_official 340:28d1f895c6fe 106 typedef enum
mbed_official 340:28d1f895c6fe 107 {
mbed_official 340:28d1f895c6fe 108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
mbed_official 630:825f75ca301e 109 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
mbed_official 340:28d1f895c6fe 110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
mbed_official 340:28d1f895c6fe 111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
mbed_official 340:28d1f895c6fe 112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
mbed_official 630:825f75ca301e 113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
mbed_official 340:28d1f895c6fe 114 }HAL_DMA_StateTypeDef;
mbed_official 340:28d1f895c6fe 115
mbed_official 340:28d1f895c6fe 116 /**
mbed_official 340:28d1f895c6fe 117 * @brief HAL DMA Error Code structure definition
mbed_official 340:28d1f895c6fe 118 */
mbed_official 340:28d1f895c6fe 119 typedef enum
mbed_official 340:28d1f895c6fe 120 {
mbed_official 340:28d1f895c6fe 121 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
mbed_official 340:28d1f895c6fe 122 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
mbed_official 630:825f75ca301e 123 }HAL_DMA_LevelCompleteTypeDef;
mbed_official 340:28d1f895c6fe 124
mbed_official 340:28d1f895c6fe 125 /**
mbed_official 340:28d1f895c6fe 126 * @brief DMA handle Structure definition
mbed_official 340:28d1f895c6fe 127 */
mbed_official 340:28d1f895c6fe 128 typedef struct __DMA_HandleTypeDef
mbed_official 340:28d1f895c6fe 129 {
mbed_official 340:28d1f895c6fe 130 DMA_Channel_TypeDef *Instance; /*!< Register base address */
mbed_official 340:28d1f895c6fe 131
mbed_official 340:28d1f895c6fe 132 DMA_InitTypeDef Init; /*!< DMA communication parameters */
mbed_official 340:28d1f895c6fe 133
mbed_official 340:28d1f895c6fe 134 HAL_LockTypeDef Lock; /*!< DMA locking object */
mbed_official 340:28d1f895c6fe 135
mbed_official 630:825f75ca301e 136 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
mbed_official 340:28d1f895c6fe 137
mbed_official 340:28d1f895c6fe 138 void *Parent; /*!< Parent object state */
mbed_official 340:28d1f895c6fe 139
mbed_official 340:28d1f895c6fe 140 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
mbed_official 340:28d1f895c6fe 141
mbed_official 340:28d1f895c6fe 142 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
mbed_official 340:28d1f895c6fe 143
mbed_official 340:28d1f895c6fe 144 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
mbed_official 340:28d1f895c6fe 145
mbed_official 340:28d1f895c6fe 146 __IO uint32_t ErrorCode; /*!< DMA Error code */
mbed_official 340:28d1f895c6fe 147 } DMA_HandleTypeDef;
mbed_official 630:825f75ca301e 148
mbed_official 340:28d1f895c6fe 149 /**
mbed_official 340:28d1f895c6fe 150 * @}
mbed_official 340:28d1f895c6fe 151 */
mbed_official 340:28d1f895c6fe 152
mbed_official 340:28d1f895c6fe 153 /* Exported constants --------------------------------------------------------*/
mbed_official 630:825f75ca301e 154
mbed_official 340:28d1f895c6fe 155 /** @defgroup DMA_Exported_Constants DMA Exported Constants
mbed_official 340:28d1f895c6fe 156 * @{
mbed_official 340:28d1f895c6fe 157 */
mbed_official 340:28d1f895c6fe 158
mbed_official 340:28d1f895c6fe 159 /** @defgroup DMA_Error_Code DMA Error Code
mbed_official 340:28d1f895c6fe 160 * @{
mbed_official 340:28d1f895c6fe 161 */
mbed_official 340:28d1f895c6fe 162 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
mbed_official 340:28d1f895c6fe 163 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
mbed_official 340:28d1f895c6fe 164 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
mbed_official 340:28d1f895c6fe 165 /**
mbed_official 340:28d1f895c6fe 166 * @}
mbed_official 340:28d1f895c6fe 167 */
mbed_official 340:28d1f895c6fe 168
mbed_official 340:28d1f895c6fe 169 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
mbed_official 340:28d1f895c6fe 170 * @{
mbed_official 340:28d1f895c6fe 171 */
mbed_official 340:28d1f895c6fe 172 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
mbed_official 340:28d1f895c6fe 173 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
mbed_official 340:28d1f895c6fe 174 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
mbed_official 340:28d1f895c6fe 175
mbed_official 340:28d1f895c6fe 176 /**
mbed_official 340:28d1f895c6fe 177 * @}
mbed_official 340:28d1f895c6fe 178 */
mbed_official 630:825f75ca301e 179
mbed_official 340:28d1f895c6fe 180 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
mbed_official 340:28d1f895c6fe 181 * @{
mbed_official 340:28d1f895c6fe 182 */
mbed_official 340:28d1f895c6fe 183 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
mbed_official 340:28d1f895c6fe 184 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
mbed_official 340:28d1f895c6fe 185 /**
mbed_official 340:28d1f895c6fe 186 * @}
mbed_official 340:28d1f895c6fe 187 */
mbed_official 340:28d1f895c6fe 188
mbed_official 340:28d1f895c6fe 189 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
mbed_official 340:28d1f895c6fe 190 * @{
mbed_official 340:28d1f895c6fe 191 */
mbed_official 340:28d1f895c6fe 192 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
mbed_official 340:28d1f895c6fe 193 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
mbed_official 340:28d1f895c6fe 194 /**
mbed_official 340:28d1f895c6fe 195 * @}
mbed_official 340:28d1f895c6fe 196 */
mbed_official 340:28d1f895c6fe 197
mbed_official 340:28d1f895c6fe 198 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
mbed_official 340:28d1f895c6fe 199 * @{
mbed_official 340:28d1f895c6fe 200 */
mbed_official 340:28d1f895c6fe 201 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
mbed_official 340:28d1f895c6fe 202 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
mbed_official 340:28d1f895c6fe 203 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
mbed_official 340:28d1f895c6fe 204 /**
mbed_official 340:28d1f895c6fe 205 * @}
mbed_official 340:28d1f895c6fe 206 */
mbed_official 340:28d1f895c6fe 207
mbed_official 340:28d1f895c6fe 208 /** @defgroup DMA_Memory_data_size DMA Memory data size
mbed_official 340:28d1f895c6fe 209 * @{
mbed_official 340:28d1f895c6fe 210 */
mbed_official 340:28d1f895c6fe 211 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
mbed_official 340:28d1f895c6fe 212 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
mbed_official 340:28d1f895c6fe 213 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
mbed_official 340:28d1f895c6fe 214 /**
mbed_official 340:28d1f895c6fe 215 * @}
mbed_official 340:28d1f895c6fe 216 */
mbed_official 340:28d1f895c6fe 217
mbed_official 340:28d1f895c6fe 218 /** @defgroup DMA_mode DMA mode
mbed_official 340:28d1f895c6fe 219 * @{
mbed_official 340:28d1f895c6fe 220 */
mbed_official 340:28d1f895c6fe 221 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
mbed_official 340:28d1f895c6fe 222 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
mbed_official 340:28d1f895c6fe 223 /**
mbed_official 340:28d1f895c6fe 224 * @}
mbed_official 340:28d1f895c6fe 225 */
mbed_official 340:28d1f895c6fe 226
mbed_official 340:28d1f895c6fe 227 /** @defgroup DMA_Priority_level DMA Priority level
mbed_official 340:28d1f895c6fe 228 * @{
mbed_official 340:28d1f895c6fe 229 */
mbed_official 340:28d1f895c6fe 230 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
mbed_official 340:28d1f895c6fe 231 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
mbed_official 340:28d1f895c6fe 232 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
mbed_official 340:28d1f895c6fe 233 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
mbed_official 340:28d1f895c6fe 234 /**
mbed_official 340:28d1f895c6fe 235 * @}
mbed_official 340:28d1f895c6fe 236 */
mbed_official 340:28d1f895c6fe 237
mbed_official 340:28d1f895c6fe 238
mbed_official 340:28d1f895c6fe 239 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
mbed_official 340:28d1f895c6fe 240 * @{
mbed_official 340:28d1f895c6fe 241 */
mbed_official 340:28d1f895c6fe 242 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
mbed_official 340:28d1f895c6fe 243 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
mbed_official 340:28d1f895c6fe 244 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
mbed_official 340:28d1f895c6fe 245 /**
mbed_official 340:28d1f895c6fe 246 * @}
mbed_official 340:28d1f895c6fe 247 */
mbed_official 340:28d1f895c6fe 248
mbed_official 340:28d1f895c6fe 249 /** @defgroup DMA_flag_definitions DMA flag definitions
mbed_official 340:28d1f895c6fe 250 * @{
mbed_official 340:28d1f895c6fe 251 */
mbed_official 340:28d1f895c6fe 252
mbed_official 441:d2c15dda23c1 253 #define DMA_FLAG_GL1 ((uint32_t)0x00000001) /*!< Channel 1 global interrupt flag */
mbed_official 441:d2c15dda23c1 254 #define DMA_FLAG_TC1 ((uint32_t)0x00000002) /*!< Channel 1 transfer complete flag */
mbed_official 441:d2c15dda23c1 255 #define DMA_FLAG_HT1 ((uint32_t)0x00000004) /*!< Channel 1 half transfer flag */
mbed_official 441:d2c15dda23c1 256 #define DMA_FLAG_TE1 ((uint32_t)0x00000008) /*!< Channel 1 transfer error flag */
mbed_official 441:d2c15dda23c1 257 #define DMA_FLAG_GL2 ((uint32_t)0x00000010) /*!< Channel 2 global interrupt flag */
mbed_official 441:d2c15dda23c1 258 #define DMA_FLAG_TC2 ((uint32_t)0x00000020) /*!< Channel 2 transfer complete flag */
mbed_official 441:d2c15dda23c1 259 #define DMA_FLAG_HT2 ((uint32_t)0x00000040) /*!< Channel 2 half transfer flag */
mbed_official 441:d2c15dda23c1 260 #define DMA_FLAG_TE2 ((uint32_t)0x00000080) /*!< Channel 2 transfer error flag */
mbed_official 441:d2c15dda23c1 261 #define DMA_FLAG_GL3 ((uint32_t)0x00000100) /*!< Channel 3 global interrupt flag */
mbed_official 441:d2c15dda23c1 262 #define DMA_FLAG_TC3 ((uint32_t)0x00000200) /*!< Channel 3 transfer complete flag */
mbed_official 441:d2c15dda23c1 263 #define DMA_FLAG_HT3 ((uint32_t)0x00000400) /*!< Channel 3 half transfer flag */
mbed_official 441:d2c15dda23c1 264 #define DMA_FLAG_TE3 ((uint32_t)0x00000800) /*!< Channel 3 transfer error flag */
mbed_official 441:d2c15dda23c1 265 #define DMA_FLAG_GL4 ((uint32_t)0x00001000) /*!< Channel 4 global interrupt flag */
mbed_official 441:d2c15dda23c1 266 #define DMA_FLAG_TC4 ((uint32_t)0x00002000) /*!< Channel 4 transfer complete flag */
mbed_official 441:d2c15dda23c1 267 #define DMA_FLAG_HT4 ((uint32_t)0x00004000) /*!< Channel 4 half transfer flag */
mbed_official 441:d2c15dda23c1 268 #define DMA_FLAG_TE4 ((uint32_t)0x00008000) /*!< Channel 4 transfer error flag */
mbed_official 441:d2c15dda23c1 269 #define DMA_FLAG_GL5 ((uint32_t)0x00010000) /*!< Channel 5 global interrupt flag */
mbed_official 441:d2c15dda23c1 270 #define DMA_FLAG_TC5 ((uint32_t)0x00020000) /*!< Channel 5 transfer complete flag */
mbed_official 441:d2c15dda23c1 271 #define DMA_FLAG_HT5 ((uint32_t)0x00040000) /*!< Channel 5 half transfer flag */
mbed_official 441:d2c15dda23c1 272 #define DMA_FLAG_TE5 ((uint32_t)0x00080000) /*!< Channel 5 transfer error flag */
mbed_official 441:d2c15dda23c1 273 #define DMA_FLAG_GL6 ((uint32_t)0x00100000) /*!< Channel 6 global interrupt flag */
mbed_official 441:d2c15dda23c1 274 #define DMA_FLAG_TC6 ((uint32_t)0x00200000) /*!< Channel 6 transfer complete flag */
mbed_official 441:d2c15dda23c1 275 #define DMA_FLAG_HT6 ((uint32_t)0x00400000) /*!< Channel 6 half transfer flag */
mbed_official 441:d2c15dda23c1 276 #define DMA_FLAG_TE6 ((uint32_t)0x00800000) /*!< Channel 6 transfer error flag */
mbed_official 441:d2c15dda23c1 277 #define DMA_FLAG_GL7 ((uint32_t)0x01000000) /*!< Channel 7 global interrupt flag */
mbed_official 441:d2c15dda23c1 278 #define DMA_FLAG_TC7 ((uint32_t)0x02000000) /*!< Channel 7 transfer complete flag */
mbed_official 441:d2c15dda23c1 279 #define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */
mbed_official 441:d2c15dda23c1 280 #define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */
mbed_official 340:28d1f895c6fe 281
mbed_official 630:825f75ca301e 282 /**
mbed_official 630:825f75ca301e 283 * @}
mbed_official 630:825f75ca301e 284 */
mbed_official 630:825f75ca301e 285
mbed_official 630:825f75ca301e 286 #if defined(SYSCFG_CFGR1_DMA_RMP)
mbed_official 630:825f75ca301e 287 /** @defgroup HAL_DMA_remapping HAL DMA remapping
mbed_official 630:825f75ca301e 288 * Elements values convention: 0xYYYYYYYY
mbed_official 630:825f75ca301e 289 * - YYYYYYYY : Position in the SYSCFG register CFGR1
mbed_official 630:825f75ca301e 290 * @{
mbed_official 630:825f75ca301e 291 */
mbed_official 630:825f75ca301e 292 #define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
mbed_official 630:825f75ca301e 293 0: No remap (ADC DMA requests mapped on DMA channel 1
mbed_official 630:825f75ca301e 294 1: Remap (ADC DMA requests mapped on DMA channel 2 */
mbed_official 630:825f75ca301e 295 #define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
mbed_official 630:825f75ca301e 296 0: No remap (USART1_TX DMA request mapped on DMA channel 2
mbed_official 630:825f75ca301e 297 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
mbed_official 630:825f75ca301e 298 #define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
mbed_official 630:825f75ca301e 299 0: No remap (USART1_RX DMA request mapped on DMA channel 3
mbed_official 630:825f75ca301e 300 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
mbed_official 630:825f75ca301e 301 #define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
mbed_official 630:825f75ca301e 302 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
mbed_official 630:825f75ca301e 303 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
mbed_official 630:825f75ca301e 304 #define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
mbed_official 630:825f75ca301e 305 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
mbed_official 630:825f75ca301e 306 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
mbed_official 630:825f75ca301e 307 #if defined (STM32F070xB)
mbed_official 630:825f75ca301e 308 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only.
mbed_official 630:825f75ca301e 309 0: Disabled, need to remap before use
mbed_official 630:825f75ca301e 310 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
mbed_official 630:825f75ca301e 311
mbed_official 630:825f75ca301e 312 #endif
mbed_official 630:825f75ca301e 313
mbed_official 630:825f75ca301e 314 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
mbed_official 630:825f75ca301e 315 #define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
mbed_official 630:825f75ca301e 316 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
mbed_official 630:825f75ca301e 317 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
mbed_official 630:825f75ca301e 318 #define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
mbed_official 630:825f75ca301e 319 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
mbed_official 630:825f75ca301e 320 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
mbed_official 630:825f75ca301e 321 #define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
mbed_official 630:825f75ca301e 322 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
mbed_official 630:825f75ca301e 323 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
mbed_official 630:825f75ca301e 324 #define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
mbed_official 630:825f75ca301e 325 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
mbed_official 630:825f75ca301e 326 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
mbed_official 630:825f75ca301e 327 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
mbed_official 630:825f75ca301e 328 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
mbed_official 630:825f75ca301e 329 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
mbed_official 630:825f75ca301e 330 #define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
mbed_official 630:825f75ca301e 331 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
mbed_official 630:825f75ca301e 332 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
mbed_official 630:825f75ca301e 333 #define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
mbed_official 630:825f75ca301e 334 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
mbed_official 630:825f75ca301e 335 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
mbed_official 630:825f75ca301e 336 #define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
mbed_official 630:825f75ca301e 337 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
mbed_official 630:825f75ca301e 338 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
mbed_official 630:825f75ca301e 339 #define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
mbed_official 630:825f75ca301e 340 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
mbed_official 630:825f75ca301e 341 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
mbed_official 630:825f75ca301e 342 #endif
mbed_official 340:28d1f895c6fe 343
mbed_official 340:28d1f895c6fe 344 /**
mbed_official 340:28d1f895c6fe 345 * @}
mbed_official 340:28d1f895c6fe 346 */
mbed_official 340:28d1f895c6fe 347
mbed_official 630:825f75ca301e 348 #endif /* SYSCFG_CFGR1_DMA_RMP */
mbed_official 340:28d1f895c6fe 349 /**
mbed_official 340:28d1f895c6fe 350 * @}
mbed_official 340:28d1f895c6fe 351 */
mbed_official 340:28d1f895c6fe 352
mbed_official 630:825f75ca301e 353 /* Exported macro ------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 354 /** @defgroup DMA_Exported_Macros DMA Exported Macros
mbed_official 340:28d1f895c6fe 355 * @{
mbed_official 340:28d1f895c6fe 356 */
mbed_official 340:28d1f895c6fe 357
mbed_official 340:28d1f895c6fe 358 /** @brief Reset DMA handle state
mbed_official 340:28d1f895c6fe 359 * @param __HANDLE__: DMA handle.
mbed_official 340:28d1f895c6fe 360 * @retval None
mbed_official 340:28d1f895c6fe 361 */
mbed_official 340:28d1f895c6fe 362 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
mbed_official 340:28d1f895c6fe 363
mbed_official 340:28d1f895c6fe 364 /**
mbed_official 340:28d1f895c6fe 365 * @brief Enable the specified DMA Channel.
mbed_official 340:28d1f895c6fe 366 * @param __HANDLE__: DMA handle
mbed_official 630:825f75ca301e 367 * @retval None
mbed_official 340:28d1f895c6fe 368 */
mbed_official 340:28d1f895c6fe 369 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
mbed_official 340:28d1f895c6fe 370
mbed_official 340:28d1f895c6fe 371 /**
mbed_official 340:28d1f895c6fe 372 * @brief Disable the specified DMA Channel.
mbed_official 340:28d1f895c6fe 373 * @param __HANDLE__: DMA handle
mbed_official 630:825f75ca301e 374 * @retval None
mbed_official 340:28d1f895c6fe 375 */
mbed_official 340:28d1f895c6fe 376 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
mbed_official 340:28d1f895c6fe 377
mbed_official 340:28d1f895c6fe 378
mbed_official 340:28d1f895c6fe 379 /* Interrupt & Flag management */
mbed_official 340:28d1f895c6fe 380
mbed_official 340:28d1f895c6fe 381 /**
mbed_official 340:28d1f895c6fe 382 * @brief Enables the specified DMA Channel interrupts.
mbed_official 340:28d1f895c6fe 383 * @param __HANDLE__: DMA handle
mbed_official 340:28d1f895c6fe 384 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
mbed_official 340:28d1f895c6fe 385 * This parameter can be any combination of the following values:
mbed_official 340:28d1f895c6fe 386 * @arg DMA_IT_TC: Transfer complete interrupt mask
mbed_official 340:28d1f895c6fe 387 * @arg DMA_IT_HT: Half transfer complete interrupt mask
mbed_official 340:28d1f895c6fe 388 * @arg DMA_IT_TE: Transfer error interrupt mask
mbed_official 340:28d1f895c6fe 389 * @retval None
mbed_official 340:28d1f895c6fe 390 */
mbed_official 340:28d1f895c6fe 391 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
mbed_official 340:28d1f895c6fe 392
mbed_official 340:28d1f895c6fe 393 /**
mbed_official 340:28d1f895c6fe 394 * @brief Disables the specified DMA Channel interrupts.
mbed_official 340:28d1f895c6fe 395 * @param __HANDLE__: DMA handle
mbed_official 340:28d1f895c6fe 396 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
mbed_official 340:28d1f895c6fe 397 * This parameter can be any combination of the following values:
mbed_official 340:28d1f895c6fe 398 * @arg DMA_IT_TC: Transfer complete interrupt mask
mbed_official 340:28d1f895c6fe 399 * @arg DMA_IT_HT: Half transfer complete interrupt mask
mbed_official 340:28d1f895c6fe 400 * @arg DMA_IT_TE: Transfer error interrupt mask
mbed_official 340:28d1f895c6fe 401 * @retval None
mbed_official 340:28d1f895c6fe 402 */
mbed_official 340:28d1f895c6fe 403 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
mbed_official 340:28d1f895c6fe 404
mbed_official 340:28d1f895c6fe 405 /**
mbed_official 630:825f75ca301e 406 * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
mbed_official 340:28d1f895c6fe 407 * @param __HANDLE__: DMA handle
mbed_official 340:28d1f895c6fe 408 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
mbed_official 340:28d1f895c6fe 409 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 410 * @arg DMA_IT_TC: Transfer complete interrupt mask
mbed_official 340:28d1f895c6fe 411 * @arg DMA_IT_HT: Half transfer complete interrupt mask
mbed_official 340:28d1f895c6fe 412 * @arg DMA_IT_TE: Transfer error interrupt mask
mbed_official 340:28d1f895c6fe 413 * @retval The state of DMA_IT (SET or RESET).
mbed_official 340:28d1f895c6fe 414 */
mbed_official 340:28d1f895c6fe 415 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
mbed_official 340:28d1f895c6fe 416
mbed_official 630:825f75ca301e 417 #if defined(SYSCFG_CFGR1_DMA_RMP)
mbed_official 630:825f75ca301e 418 /** @brief DMA remapping enable/disable macros
mbed_official 630:825f75ca301e 419 * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping
mbed_official 630:825f75ca301e 420 */
mbed_official 630:825f75ca301e 421 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
mbed_official 630:825f75ca301e 422 SYSCFG->CFGR1 |= (__DMA_REMAP__); \
mbed_official 630:825f75ca301e 423 }while(0)
mbed_official 630:825f75ca301e 424 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
mbed_official 630:825f75ca301e 425 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
mbed_official 630:825f75ca301e 426 }while(0)
mbed_official 630:825f75ca301e 427 #endif /* SYSCFG_CFGR1_DMA_RMP */
mbed_official 630:825f75ca301e 428
mbed_official 340:28d1f895c6fe 429 /**
mbed_official 340:28d1f895c6fe 430 * @}
mbed_official 340:28d1f895c6fe 431 */
mbed_official 340:28d1f895c6fe 432
mbed_official 340:28d1f895c6fe 433 /* Include DMA HAL Extension module */
mbed_official 340:28d1f895c6fe 434 #include "stm32f0xx_hal_dma_ex.h"
mbed_official 340:28d1f895c6fe 435
mbed_official 340:28d1f895c6fe 436 /* Exported functions --------------------------------------------------------*/
mbed_official 630:825f75ca301e 437 /** @addtogroup DMA_Exported_Functions
mbed_official 340:28d1f895c6fe 438 * @{
mbed_official 340:28d1f895c6fe 439 */
mbed_official 630:825f75ca301e 440
mbed_official 340:28d1f895c6fe 441 /** @addtogroup DMA_Exported_Functions_Group1
mbed_official 340:28d1f895c6fe 442 * @{
mbed_official 340:28d1f895c6fe 443 */
mbed_official 340:28d1f895c6fe 444 /* Initialization and de-initialization functions *****************************/
mbed_official 340:28d1f895c6fe 445 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 446 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 447 /**
mbed_official 340:28d1f895c6fe 448 * @}
mbed_official 340:28d1f895c6fe 449 */
mbed_official 340:28d1f895c6fe 450
mbed_official 340:28d1f895c6fe 451 /** @addtogroup DMA_Exported_Functions_Group2
mbed_official 340:28d1f895c6fe 452 * @{
mbed_official 340:28d1f895c6fe 453 */
mbed_official 630:825f75ca301e 454 /* Input and Output operation functions *****************************************************/
mbed_official 340:28d1f895c6fe 455 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
mbed_official 340:28d1f895c6fe 456 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
mbed_official 340:28d1f895c6fe 457 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 458 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
mbed_official 340:28d1f895c6fe 459 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 460 /**
mbed_official 340:28d1f895c6fe 461 * @}
mbed_official 340:28d1f895c6fe 462 */
mbed_official 340:28d1f895c6fe 463
mbed_official 340:28d1f895c6fe 464 /** @addtogroup DMA_Exported_Functions_Group3
mbed_official 340:28d1f895c6fe 465 * @{
mbed_official 340:28d1f895c6fe 466 */
mbed_official 630:825f75ca301e 467 /* Peripheral State and Error functions ***************************************/
mbed_official 340:28d1f895c6fe 468 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 469 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 470 /**
mbed_official 340:28d1f895c6fe 471 * @}
mbed_official 630:825f75ca301e 472 */
mbed_official 630:825f75ca301e 473
mbed_official 630:825f75ca301e 474 /**
mbed_official 630:825f75ca301e 475 * @}
mbed_official 630:825f75ca301e 476 */
mbed_official 630:825f75ca301e 477
mbed_official 630:825f75ca301e 478 /** @addtogroup DMA_Private_Macros
mbed_official 630:825f75ca301e 479 * @{
mbed_official 340:28d1f895c6fe 480 */
mbed_official 630:825f75ca301e 481 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
mbed_official 630:825f75ca301e 482 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
mbed_official 630:825f75ca301e 483 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
mbed_official 630:825f75ca301e 484 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
mbed_official 630:825f75ca301e 485 ((STATE) == DMA_PINC_DISABLE))
mbed_official 630:825f75ca301e 486
mbed_official 630:825f75ca301e 487 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
mbed_official 630:825f75ca301e 488 ((STATE) == DMA_MINC_DISABLE))
mbed_official 630:825f75ca301e 489
mbed_official 630:825f75ca301e 490 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
mbed_official 630:825f75ca301e 491 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
mbed_official 630:825f75ca301e 492 ((SIZE) == DMA_PDATAALIGN_WORD))
mbed_official 630:825f75ca301e 493
mbed_official 630:825f75ca301e 494 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
mbed_official 630:825f75ca301e 495 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
mbed_official 630:825f75ca301e 496 ((SIZE) == DMA_MDATAALIGN_WORD ))
mbed_official 630:825f75ca301e 497
mbed_official 630:825f75ca301e 498 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
mbed_official 630:825f75ca301e 499 ((MODE) == DMA_CIRCULAR))
mbed_official 630:825f75ca301e 500 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
mbed_official 630:825f75ca301e 501 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
mbed_official 630:825f75ca301e 502 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
mbed_official 630:825f75ca301e 503 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
mbed_official 630:825f75ca301e 504 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
mbed_official 630:825f75ca301e 505
mbed_official 630:825f75ca301e 506 #if defined(SYSCFG_CFGR1_DMA_RMP)
mbed_official 630:825f75ca301e 507
mbed_official 630:825f75ca301e 508 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
mbed_official 630:825f75ca301e 509 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
mbed_official 630:825f75ca301e 510 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
mbed_official 630:825f75ca301e 511 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
mbed_official 630:825f75ca301e 512 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
mbed_official 630:825f75ca301e 513 ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \
mbed_official 630:825f75ca301e 514 ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \
mbed_official 630:825f75ca301e 515 ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \
mbed_official 630:825f75ca301e 516 ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \
mbed_official 630:825f75ca301e 517 ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \
mbed_official 630:825f75ca301e 518 ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
mbed_official 630:825f75ca301e 519 ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \
mbed_official 630:825f75ca301e 520 ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \
mbed_official 630:825f75ca301e 521 ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \
mbed_official 630:825f75ca301e 522 ((RMP) == DMA_REMAP_TIM3_DMA_CH6))
mbed_official 630:825f75ca301e 523 #elif defined (STM32F070xB)
mbed_official 630:825f75ca301e 524 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
mbed_official 630:825f75ca301e 525 ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
mbed_official 630:825f75ca301e 526 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
mbed_official 630:825f75ca301e 527 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
mbed_official 630:825f75ca301e 528 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
mbed_official 630:825f75ca301e 529 ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
mbed_official 630:825f75ca301e 530 #else
mbed_official 630:825f75ca301e 531 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
mbed_official 630:825f75ca301e 532 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
mbed_official 630:825f75ca301e 533 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
mbed_official 630:825f75ca301e 534 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
mbed_official 630:825f75ca301e 535 ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
mbed_official 630:825f75ca301e 536 #endif
mbed_official 630:825f75ca301e 537
mbed_official 630:825f75ca301e 538 #endif /* SYSCFG_CFGR1_DMA_RMP */
mbed_official 630:825f75ca301e 539
mbed_official 630:825f75ca301e 540
mbed_official 630:825f75ca301e 541 /**
mbed_official 630:825f75ca301e 542 * @}
mbed_official 630:825f75ca301e 543 */
mbed_official 340:28d1f895c6fe 544
mbed_official 340:28d1f895c6fe 545 /**
mbed_official 340:28d1f895c6fe 546 * @}
mbed_official 340:28d1f895c6fe 547 */
mbed_official 340:28d1f895c6fe 548
mbed_official 340:28d1f895c6fe 549 /**
mbed_official 340:28d1f895c6fe 550 * @}
mbed_official 340:28d1f895c6fe 551 */
mbed_official 340:28d1f895c6fe 552
mbed_official 340:28d1f895c6fe 553 #ifdef __cplusplus
mbed_official 340:28d1f895c6fe 554 }
mbed_official 340:28d1f895c6fe 555 #endif
mbed_official 340:28d1f895c6fe 556
mbed_official 340:28d1f895c6fe 557 #endif /* __STM32F0xx_HAL_DMA_H */
mbed_official 340:28d1f895c6fe 558
mbed_official 340:28d1f895c6fe 559 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 340:28d1f895c6fe 560