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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/stm32f031x6.h@630:825f75ca301e, 2015-09-28 (annotated)

Committer:
mbed_official
Date:
Mon Sep 28 10:45:10 2015 +0100
Revision:
630:825f75ca301e
Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10



Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/



NUCLEO_F031K6 : Add new target

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 630:825f75ca301e 1 /**
mbed_official 630:825f75ca301e 2 ******************************************************************************
mbed_official 630:825f75ca301e 3 * @file stm32f031x6.h
mbed_official 630:825f75ca301e 4 * @author MCD Application Team
mbed_official 630:825f75ca301e 5 * @version V2.2.2
mbed_official 630:825f75ca301e 6 * @date 26-June-2015
mbed_official 630:825f75ca301e 7 * @brief CMSIS STM32F031x4/STM32F031x6 devices Peripheral Access Layer Header File.
mbed_official 630:825f75ca301e 8 *
mbed_official 630:825f75ca301e 9 * This file contains:
mbed_official 630:825f75ca301e 10 * - Data structures and the address mapping for all peripherals
mbed_official 630:825f75ca301e 11 * - Peripheral's registers declarations and bits definition
mbed_official 630:825f75ca301e 12 * - Macros to access peripheral’s registers hardware
mbed_official 630:825f75ca301e 13 *
mbed_official 630:825f75ca301e 14 ******************************************************************************
mbed_official 630:825f75ca301e 15 * @attention
mbed_official 630:825f75ca301e 16 *
mbed_official 630:825f75ca301e 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 630:825f75ca301e 18 *
mbed_official 630:825f75ca301e 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 630:825f75ca301e 20 * are permitted provided that the following conditions are met:
mbed_official 630:825f75ca301e 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 630:825f75ca301e 22 * this list of conditions and the following disclaimer.
mbed_official 630:825f75ca301e 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 630:825f75ca301e 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 630:825f75ca301e 25 * and/or other materials provided with the distribution.
mbed_official 630:825f75ca301e 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 630:825f75ca301e 27 * may be used to endorse or promote products derived from this software
mbed_official 630:825f75ca301e 28 * without specific prior written permission.
mbed_official 630:825f75ca301e 29 *
mbed_official 630:825f75ca301e 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 630:825f75ca301e 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 630:825f75ca301e 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 630:825f75ca301e 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 630:825f75ca301e 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 630:825f75ca301e 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 630:825f75ca301e 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 630:825f75ca301e 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 630:825f75ca301e 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 630:825f75ca301e 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 630:825f75ca301e 40 *
mbed_official 630:825f75ca301e 41 ******************************************************************************
mbed_official 630:825f75ca301e 42 */
mbed_official 630:825f75ca301e 43
mbed_official 630:825f75ca301e 44 /** @addtogroup CMSIS_Device
mbed_official 630:825f75ca301e 45 * @{
mbed_official 630:825f75ca301e 46 */
mbed_official 630:825f75ca301e 47
mbed_official 630:825f75ca301e 48 /** @addtogroup stm32f031x6
mbed_official 630:825f75ca301e 49 * @{
mbed_official 630:825f75ca301e 50 */
mbed_official 630:825f75ca301e 51
mbed_official 630:825f75ca301e 52 #ifndef __STM32F031x6_H
mbed_official 630:825f75ca301e 53 #define __STM32F031x6_H
mbed_official 630:825f75ca301e 54
mbed_official 630:825f75ca301e 55 #ifdef __cplusplus
mbed_official 630:825f75ca301e 56 extern "C" {
mbed_official 630:825f75ca301e 57 #endif /* __cplusplus */
mbed_official 630:825f75ca301e 58
mbed_official 630:825f75ca301e 59 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 630:825f75ca301e 60 * @{
mbed_official 630:825f75ca301e 61 */
mbed_official 630:825f75ca301e 62 /**
mbed_official 630:825f75ca301e 63 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
mbed_official 630:825f75ca301e 64 */
mbed_official 630:825f75ca301e 65 #define __CM0_REV 0 /*!< Core Revision r0p0 */
mbed_official 630:825f75ca301e 66 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
mbed_official 630:825f75ca301e 67 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
mbed_official 630:825f75ca301e 68 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 630:825f75ca301e 69
mbed_official 630:825f75ca301e 70 /**
mbed_official 630:825f75ca301e 71 * @}
mbed_official 630:825f75ca301e 72 */
mbed_official 630:825f75ca301e 73
mbed_official 630:825f75ca301e 74 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 630:825f75ca301e 75 * @{
mbed_official 630:825f75ca301e 76 */
mbed_official 630:825f75ca301e 77
mbed_official 630:825f75ca301e 78 /**
mbed_official 630:825f75ca301e 79 * @brief STM32F031x4/STM32F031x6 device Interrupt Number Definition
mbed_official 630:825f75ca301e 80 */
mbed_official 630:825f75ca301e 81 typedef enum
mbed_official 630:825f75ca301e 82 {
mbed_official 630:825f75ca301e 83 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
mbed_official 630:825f75ca301e 84 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 630:825f75ca301e 85 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
mbed_official 630:825f75ca301e 86 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
mbed_official 630:825f75ca301e 87 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
mbed_official 630:825f75ca301e 88 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
mbed_official 630:825f75ca301e 89
mbed_official 630:825f75ca301e 90 /****** STM32F031x4/STM32F031x6 specific Interrupt Numbers **************************************************/
mbed_official 630:825f75ca301e 91 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 630:825f75ca301e 92 PVD_IRQn = 1, /*!< PVD Interrupts through EXTI Lines 16 */
mbed_official 630:825f75ca301e 93 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
mbed_official 630:825f75ca301e 94 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
mbed_official 630:825f75ca301e 95 RCC_IRQn = 4, /*!< RCC global Interrupt */
mbed_official 630:825f75ca301e 96 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
mbed_official 630:825f75ca301e 97 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
mbed_official 630:825f75ca301e 98 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
mbed_official 630:825f75ca301e 99 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
mbed_official 630:825f75ca301e 100 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
mbed_official 630:825f75ca301e 101 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
mbed_official 630:825f75ca301e 102 ADC1_IRQn = 12, /*!< ADC1 global Interrupt */
mbed_official 630:825f75ca301e 103 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
mbed_official 630:825f75ca301e 104 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
mbed_official 630:825f75ca301e 105 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
mbed_official 630:825f75ca301e 106 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
mbed_official 630:825f75ca301e 107 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
mbed_official 630:825f75ca301e 108 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
mbed_official 630:825f75ca301e 109 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
mbed_official 630:825f75ca301e 110 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
mbed_official 630:825f75ca301e 111 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
mbed_official 630:825f75ca301e 112 USART1_IRQn = 27 /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
mbed_official 630:825f75ca301e 113 } IRQn_Type;
mbed_official 630:825f75ca301e 114
mbed_official 630:825f75ca301e 115 /**
mbed_official 630:825f75ca301e 116 * @}
mbed_official 630:825f75ca301e 117 */
mbed_official 630:825f75ca301e 118
mbed_official 630:825f75ca301e 119 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
mbed_official 630:825f75ca301e 120 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
mbed_official 630:825f75ca301e 121 #include <stdint.h>
mbed_official 630:825f75ca301e 122
mbed_official 630:825f75ca301e 123 /** @addtogroup Peripheral_registers_structures
mbed_official 630:825f75ca301e 124 * @{
mbed_official 630:825f75ca301e 125 */
mbed_official 630:825f75ca301e 126
mbed_official 630:825f75ca301e 127 /**
mbed_official 630:825f75ca301e 128 * @brief Analog to Digital Converter
mbed_official 630:825f75ca301e 129 */
mbed_official 630:825f75ca301e 130
mbed_official 630:825f75ca301e 131 typedef struct
mbed_official 630:825f75ca301e 132 {
mbed_official 630:825f75ca301e 133 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
mbed_official 630:825f75ca301e 134 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
mbed_official 630:825f75ca301e 135 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
mbed_official 630:825f75ca301e 136 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
mbed_official 630:825f75ca301e 137 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
mbed_official 630:825f75ca301e 138 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
mbed_official 630:825f75ca301e 139 uint32_t RESERVED1; /*!< Reserved, 0x18 */
mbed_official 630:825f75ca301e 140 uint32_t RESERVED2; /*!< Reserved, 0x1C */
mbed_official 630:825f75ca301e 141 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
mbed_official 630:825f75ca301e 142 uint32_t RESERVED3; /*!< Reserved, 0x24 */
mbed_official 630:825f75ca301e 143 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
mbed_official 630:825f75ca301e 144 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
mbed_official 630:825f75ca301e 145 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
mbed_official 630:825f75ca301e 146 }ADC_TypeDef;
mbed_official 630:825f75ca301e 147
mbed_official 630:825f75ca301e 148 typedef struct
mbed_official 630:825f75ca301e 149 {
mbed_official 630:825f75ca301e 150 __IO uint32_t CCR;
mbed_official 630:825f75ca301e 151 }ADC_Common_TypeDef;
mbed_official 630:825f75ca301e 152
mbed_official 630:825f75ca301e 153 /**
mbed_official 630:825f75ca301e 154 * @brief CRC calculation unit
mbed_official 630:825f75ca301e 155 */
mbed_official 630:825f75ca301e 156
mbed_official 630:825f75ca301e 157 typedef struct
mbed_official 630:825f75ca301e 158 {
mbed_official 630:825f75ca301e 159 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 630:825f75ca301e 160 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 630:825f75ca301e 161 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 630:825f75ca301e 162 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 630:825f75ca301e 163 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 630:825f75ca301e 164 uint32_t RESERVED2; /*!< Reserved, 0x0C */
mbed_official 630:825f75ca301e 165 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
mbed_official 630:825f75ca301e 166 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
mbed_official 630:825f75ca301e 167 }CRC_TypeDef;
mbed_official 630:825f75ca301e 168
mbed_official 630:825f75ca301e 169 /**
mbed_official 630:825f75ca301e 170 * @brief Debug MCU
mbed_official 630:825f75ca301e 171 */
mbed_official 630:825f75ca301e 172
mbed_official 630:825f75ca301e 173 typedef struct
mbed_official 630:825f75ca301e 174 {
mbed_official 630:825f75ca301e 175 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 630:825f75ca301e 176 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 630:825f75ca301e 177 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 630:825f75ca301e 178 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 630:825f75ca301e 179 }DBGMCU_TypeDef;
mbed_official 630:825f75ca301e 180
mbed_official 630:825f75ca301e 181 /**
mbed_official 630:825f75ca301e 182 * @brief DMA Controller
mbed_official 630:825f75ca301e 183 */
mbed_official 630:825f75ca301e 184
mbed_official 630:825f75ca301e 185 typedef struct
mbed_official 630:825f75ca301e 186 {
mbed_official 630:825f75ca301e 187 __IO uint32_t CCR; /*!< DMA channel x configuration register */
mbed_official 630:825f75ca301e 188 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
mbed_official 630:825f75ca301e 189 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
mbed_official 630:825f75ca301e 190 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
mbed_official 630:825f75ca301e 191 }DMA_Channel_TypeDef;
mbed_official 630:825f75ca301e 192
mbed_official 630:825f75ca301e 193 typedef struct
mbed_official 630:825f75ca301e 194 {
mbed_official 630:825f75ca301e 195 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
mbed_official 630:825f75ca301e 196 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
mbed_official 630:825f75ca301e 197 }DMA_TypeDef;
mbed_official 630:825f75ca301e 198
mbed_official 630:825f75ca301e 199 /**
mbed_official 630:825f75ca301e 200 * @brief External Interrupt/Event Controller
mbed_official 630:825f75ca301e 201 */
mbed_official 630:825f75ca301e 202
mbed_official 630:825f75ca301e 203 typedef struct
mbed_official 630:825f75ca301e 204 {
mbed_official 630:825f75ca301e 205 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 630:825f75ca301e 206 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
mbed_official 630:825f75ca301e 207 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
mbed_official 630:825f75ca301e 208 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 630:825f75ca301e 209 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 630:825f75ca301e 210 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
mbed_official 630:825f75ca301e 211 }EXTI_TypeDef;
mbed_official 630:825f75ca301e 212
mbed_official 630:825f75ca301e 213 /**
mbed_official 630:825f75ca301e 214 * @brief FLASH Registers
mbed_official 630:825f75ca301e 215 */
mbed_official 630:825f75ca301e 216 typedef struct
mbed_official 630:825f75ca301e 217 {
mbed_official 630:825f75ca301e 218 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
mbed_official 630:825f75ca301e 219 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
mbed_official 630:825f75ca301e 220 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
mbed_official 630:825f75ca301e 221 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
mbed_official 630:825f75ca301e 222 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
mbed_official 630:825f75ca301e 223 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
mbed_official 630:825f75ca301e 224 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
mbed_official 630:825f75ca301e 225 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
mbed_official 630:825f75ca301e 226 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
mbed_official 630:825f75ca301e 227 }FLASH_TypeDef;
mbed_official 630:825f75ca301e 228
mbed_official 630:825f75ca301e 229
mbed_official 630:825f75ca301e 230 /**
mbed_official 630:825f75ca301e 231 * @brief Option Bytes Registers
mbed_official 630:825f75ca301e 232 */
mbed_official 630:825f75ca301e 233 typedef struct
mbed_official 630:825f75ca301e 234 {
mbed_official 630:825f75ca301e 235 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
mbed_official 630:825f75ca301e 236 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
mbed_official 630:825f75ca301e 237 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
mbed_official 630:825f75ca301e 238 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
mbed_official 630:825f75ca301e 239 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
mbed_official 630:825f75ca301e 240 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
mbed_official 630:825f75ca301e 241 }OB_TypeDef;
mbed_official 630:825f75ca301e 242
mbed_official 630:825f75ca301e 243 /**
mbed_official 630:825f75ca301e 244 * @brief General Purpose I/O
mbed_official 630:825f75ca301e 245 */
mbed_official 630:825f75ca301e 246
mbed_official 630:825f75ca301e 247 typedef struct
mbed_official 630:825f75ca301e 248 {
mbed_official 630:825f75ca301e 249 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 630:825f75ca301e 250 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 630:825f75ca301e 251 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 630:825f75ca301e 252 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 630:825f75ca301e 253 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 630:825f75ca301e 254 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 630:825f75ca301e 255 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
mbed_official 630:825f75ca301e 256 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 630:825f75ca301e 257 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
mbed_official 630:825f75ca301e 258 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
mbed_official 630:825f75ca301e 259 }GPIO_TypeDef;
mbed_official 630:825f75ca301e 260
mbed_official 630:825f75ca301e 261 /**
mbed_official 630:825f75ca301e 262 * @brief SysTem Configuration
mbed_official 630:825f75ca301e 263 */
mbed_official 630:825f75ca301e 264
mbed_official 630:825f75ca301e 265 typedef struct
mbed_official 630:825f75ca301e 266 {
mbed_official 630:825f75ca301e 267 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
mbed_official 630:825f75ca301e 268 uint32_t RESERVED; /*!< Reserved, 0x04 */
mbed_official 630:825f75ca301e 269 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
mbed_official 630:825f75ca301e 270 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
mbed_official 630:825f75ca301e 271 }SYSCFG_TypeDef;
mbed_official 630:825f75ca301e 272
mbed_official 630:825f75ca301e 273 /**
mbed_official 630:825f75ca301e 274 * @brief Inter-integrated Circuit Interface
mbed_official 630:825f75ca301e 275 */
mbed_official 630:825f75ca301e 276
mbed_official 630:825f75ca301e 277 typedef struct
mbed_official 630:825f75ca301e 278 {
mbed_official 630:825f75ca301e 279 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 630:825f75ca301e 280 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 630:825f75ca301e 281 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
mbed_official 630:825f75ca301e 282 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
mbed_official 630:825f75ca301e 283 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
mbed_official 630:825f75ca301e 284 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
mbed_official 630:825f75ca301e 285 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
mbed_official 630:825f75ca301e 286 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
mbed_official 630:825f75ca301e 287 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
mbed_official 630:825f75ca301e 288 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
mbed_official 630:825f75ca301e 289 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
mbed_official 630:825f75ca301e 290 }I2C_TypeDef;
mbed_official 630:825f75ca301e 291
mbed_official 630:825f75ca301e 292 /**
mbed_official 630:825f75ca301e 293 * @brief Independent WATCHDOG
mbed_official 630:825f75ca301e 294 */
mbed_official 630:825f75ca301e 295
mbed_official 630:825f75ca301e 296 typedef struct
mbed_official 630:825f75ca301e 297 {
mbed_official 630:825f75ca301e 298 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 630:825f75ca301e 299 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 630:825f75ca301e 300 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 630:825f75ca301e 301 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 630:825f75ca301e 302 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
mbed_official 630:825f75ca301e 303 }IWDG_TypeDef;
mbed_official 630:825f75ca301e 304
mbed_official 630:825f75ca301e 305 /**
mbed_official 630:825f75ca301e 306 * @brief Power Control
mbed_official 630:825f75ca301e 307 */
mbed_official 630:825f75ca301e 308
mbed_official 630:825f75ca301e 309 typedef struct
mbed_official 630:825f75ca301e 310 {
mbed_official 630:825f75ca301e 311 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 630:825f75ca301e 312 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 630:825f75ca301e 313 }PWR_TypeDef;
mbed_official 630:825f75ca301e 314
mbed_official 630:825f75ca301e 315 /**
mbed_official 630:825f75ca301e 316 * @brief Reset and Clock Control
mbed_official 630:825f75ca301e 317 */
mbed_official 630:825f75ca301e 318
mbed_official 630:825f75ca301e 319 typedef struct
mbed_official 630:825f75ca301e 320 {
mbed_official 630:825f75ca301e 321 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 630:825f75ca301e 322 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
mbed_official 630:825f75ca301e 323 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
mbed_official 630:825f75ca301e 324 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
mbed_official 630:825f75ca301e 325 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
mbed_official 630:825f75ca301e 326 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
mbed_official 630:825f75ca301e 327 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
mbed_official 630:825f75ca301e 328 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
mbed_official 630:825f75ca301e 329 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
mbed_official 630:825f75ca301e 330 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
mbed_official 630:825f75ca301e 331 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
mbed_official 630:825f75ca301e 332 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
mbed_official 630:825f75ca301e 333 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
mbed_official 630:825f75ca301e 334 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
mbed_official 630:825f75ca301e 335 }RCC_TypeDef;
mbed_official 630:825f75ca301e 336
mbed_official 630:825f75ca301e 337 /**
mbed_official 630:825f75ca301e 338 * @brief Real-Time Clock
mbed_official 630:825f75ca301e 339 */
mbed_official 630:825f75ca301e 340 typedef struct
mbed_official 630:825f75ca301e 341 {
mbed_official 630:825f75ca301e 342 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 630:825f75ca301e 343 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 630:825f75ca301e 344 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 630:825f75ca301e 345 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 630:825f75ca301e 346 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 630:825f75ca301e 347 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
mbed_official 630:825f75ca301e 348 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
mbed_official 630:825f75ca301e 349 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 630:825f75ca301e 350 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
mbed_official 630:825f75ca301e 351 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 630:825f75ca301e 352 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 630:825f75ca301e 353 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 630:825f75ca301e 354 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 630:825f75ca301e 355 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 630:825f75ca301e 356 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 630:825f75ca301e 357 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 630:825f75ca301e 358 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 630:825f75ca301e 359 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 630:825f75ca301e 360 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x48 */
mbed_official 630:825f75ca301e 361 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */
mbed_official 630:825f75ca301e 362 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 630:825f75ca301e 363 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 630:825f75ca301e 364 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 630:825f75ca301e 365 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 630:825f75ca301e 366 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 630:825f75ca301e 367 }RTC_TypeDef;
mbed_official 630:825f75ca301e 368
mbed_official 630:825f75ca301e 369 /**
mbed_official 630:825f75ca301e 370 * @brief Serial Peripheral Interface
mbed_official 630:825f75ca301e 371 */
mbed_official 630:825f75ca301e 372
mbed_official 630:825f75ca301e 373 typedef struct
mbed_official 630:825f75ca301e 374 {
mbed_official 630:825f75ca301e 375 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 630:825f75ca301e 376 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
mbed_official 630:825f75ca301e 377 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
mbed_official 630:825f75ca301e 378 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 630:825f75ca301e 379 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 630:825f75ca301e 380 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 630:825f75ca301e 381 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 630:825f75ca301e 382 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 630:825f75ca301e 383 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 630:825f75ca301e 384 }SPI_TypeDef;
mbed_official 630:825f75ca301e 385
mbed_official 630:825f75ca301e 386 /**
mbed_official 630:825f75ca301e 387 * @brief TIM
mbed_official 630:825f75ca301e 388 */
mbed_official 630:825f75ca301e 389 typedef struct
mbed_official 630:825f75ca301e 390 {
mbed_official 630:825f75ca301e 391 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 630:825f75ca301e 392 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 630:825f75ca301e 393 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
mbed_official 630:825f75ca301e 394 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 630:825f75ca301e 395 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 630:825f75ca301e 396 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 630:825f75ca301e 397 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 630:825f75ca301e 398 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 630:825f75ca301e 399 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 630:825f75ca301e 400 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 630:825f75ca301e 401 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
mbed_official 630:825f75ca301e 402 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 630:825f75ca301e 403 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 630:825f75ca301e 404 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 630:825f75ca301e 405 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 630:825f75ca301e 406 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 630:825f75ca301e 407 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 630:825f75ca301e 408 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 630:825f75ca301e 409 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 630:825f75ca301e 410 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
mbed_official 630:825f75ca301e 411 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 630:825f75ca301e 412 }TIM_TypeDef;
mbed_official 630:825f75ca301e 413
mbed_official 630:825f75ca301e 414 /**
mbed_official 630:825f75ca301e 415 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 630:825f75ca301e 416 */
mbed_official 630:825f75ca301e 417
mbed_official 630:825f75ca301e 418 typedef struct
mbed_official 630:825f75ca301e 419 {
mbed_official 630:825f75ca301e 420 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
mbed_official 630:825f75ca301e 421 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
mbed_official 630:825f75ca301e 422 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
mbed_official 630:825f75ca301e 423 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
mbed_official 630:825f75ca301e 424 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
mbed_official 630:825f75ca301e 425 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
mbed_official 630:825f75ca301e 426 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
mbed_official 630:825f75ca301e 427 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
mbed_official 630:825f75ca301e 428 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
mbed_official 630:825f75ca301e 429 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
mbed_official 630:825f75ca301e 430 uint16_t RESERVED1; /*!< Reserved, 0x26 */
mbed_official 630:825f75ca301e 431 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
mbed_official 630:825f75ca301e 432 uint16_t RESERVED2; /*!< Reserved, 0x2A */
mbed_official 630:825f75ca301e 433 }USART_TypeDef;
mbed_official 630:825f75ca301e 434
mbed_official 630:825f75ca301e 435 /**
mbed_official 630:825f75ca301e 436 * @brief Window WATCHDOG
mbed_official 630:825f75ca301e 437 */
mbed_official 630:825f75ca301e 438 typedef struct
mbed_official 630:825f75ca301e 439 {
mbed_official 630:825f75ca301e 440 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 630:825f75ca301e 441 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 630:825f75ca301e 442 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 630:825f75ca301e 443 }WWDG_TypeDef;
mbed_official 630:825f75ca301e 444
mbed_official 630:825f75ca301e 445 /**
mbed_official 630:825f75ca301e 446 * @}
mbed_official 630:825f75ca301e 447 */
mbed_official 630:825f75ca301e 448
mbed_official 630:825f75ca301e 449 /** @addtogroup Peripheral_memory_map
mbed_official 630:825f75ca301e 450 * @{
mbed_official 630:825f75ca301e 451 */
mbed_official 630:825f75ca301e 452
mbed_official 630:825f75ca301e 453 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
mbed_official 630:825f75ca301e 454 #define FLASH_BANK1_END ((uint32_t)0x08007FFF) /*!< FLASH END address of bank1 */
mbed_official 630:825f75ca301e 455 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
mbed_official 630:825f75ca301e 456 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 630:825f75ca301e 457
mbed_official 630:825f75ca301e 458 /*!< Peripheral memory map */
mbed_official 630:825f75ca301e 459 #define APBPERIPH_BASE PERIPH_BASE
mbed_official 630:825f75ca301e 460 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 630:825f75ca301e 461 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
mbed_official 630:825f75ca301e 462
mbed_official 630:825f75ca301e 463 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
mbed_official 630:825f75ca301e 464 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
mbed_official 630:825f75ca301e 465 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
mbed_official 630:825f75ca301e 466 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
mbed_official 630:825f75ca301e 467 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
mbed_official 630:825f75ca301e 468 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
mbed_official 630:825f75ca301e 469 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
mbed_official 630:825f75ca301e 470 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
mbed_official 630:825f75ca301e 471 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
mbed_official 630:825f75ca301e 472 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
mbed_official 630:825f75ca301e 473 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
mbed_official 630:825f75ca301e 474 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
mbed_official 630:825f75ca301e 475 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
mbed_official 630:825f75ca301e 476 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
mbed_official 630:825f75ca301e 477 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
mbed_official 630:825f75ca301e 478 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
mbed_official 630:825f75ca301e 479 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
mbed_official 630:825f75ca301e 480 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
mbed_official 630:825f75ca301e 481
mbed_official 630:825f75ca301e 482 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
mbed_official 630:825f75ca301e 483 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
mbed_official 630:825f75ca301e 484 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
mbed_official 630:825f75ca301e 485 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
mbed_official 630:825f75ca301e 486 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
mbed_official 630:825f75ca301e 487 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
mbed_official 630:825f75ca301e 488
mbed_official 630:825f75ca301e 489 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
mbed_official 630:825f75ca301e 490 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
mbed_official 630:825f75ca301e 491 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
mbed_official 630:825f75ca301e 492 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
mbed_official 630:825f75ca301e 493
mbed_official 630:825f75ca301e 494 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
mbed_official 630:825f75ca301e 495 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
mbed_official 630:825f75ca301e 496 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
mbed_official 630:825f75ca301e 497 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
mbed_official 630:825f75ca301e 498
mbed_official 630:825f75ca301e 499 /**
mbed_official 630:825f75ca301e 500 * @}
mbed_official 630:825f75ca301e 501 */
mbed_official 630:825f75ca301e 502
mbed_official 630:825f75ca301e 503 /** @addtogroup Peripheral_declaration
mbed_official 630:825f75ca301e 504 * @{
mbed_official 630:825f75ca301e 505 */
mbed_official 630:825f75ca301e 506
mbed_official 630:825f75ca301e 507 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 630:825f75ca301e 508 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 630:825f75ca301e 509 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
mbed_official 630:825f75ca301e 510 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 630:825f75ca301e 511 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 630:825f75ca301e 512 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 630:825f75ca301e 513 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 630:825f75ca301e 514 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 630:825f75ca301e 515 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 630:825f75ca301e 516 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 630:825f75ca301e 517 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 630:825f75ca301e 518 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 630:825f75ca301e 519 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 630:825f75ca301e 520 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 630:825f75ca301e 521 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 630:825f75ca301e 522 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
mbed_official 630:825f75ca301e 523 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
mbed_official 630:825f75ca301e 524 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 630:825f75ca301e 525 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 630:825f75ca301e 526 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official 630:825f75ca301e 527 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official 630:825f75ca301e 528 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official 630:825f75ca301e 529 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official 630:825f75ca301e 530 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official 630:825f75ca301e 531 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 630:825f75ca301e 532 #define OB ((OB_TypeDef *) OB_BASE)
mbed_official 630:825f75ca301e 533 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 630:825f75ca301e 534 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 630:825f75ca301e 535 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 630:825f75ca301e 536 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 630:825f75ca301e 537 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 630:825f75ca301e 538 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 630:825f75ca301e 539 /**
mbed_official 630:825f75ca301e 540 * @}
mbed_official 630:825f75ca301e 541 */
mbed_official 630:825f75ca301e 542
mbed_official 630:825f75ca301e 543 /** @addtogroup Exported_constants
mbed_official 630:825f75ca301e 544 * @{
mbed_official 630:825f75ca301e 545 */
mbed_official 630:825f75ca301e 546
mbed_official 630:825f75ca301e 547 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 630:825f75ca301e 548 * @{
mbed_official 630:825f75ca301e 549 */
mbed_official 630:825f75ca301e 550
mbed_official 630:825f75ca301e 551 /******************************************************************************/
mbed_official 630:825f75ca301e 552 /* Peripheral Registers Bits Definition */
mbed_official 630:825f75ca301e 553 /******************************************************************************/
mbed_official 630:825f75ca301e 554 /******************************************************************************/
mbed_official 630:825f75ca301e 555 /* */
mbed_official 630:825f75ca301e 556 /* Analog to Digital Converter (ADC) */
mbed_official 630:825f75ca301e 557 /* */
mbed_official 630:825f75ca301e 558 /******************************************************************************/
mbed_official 630:825f75ca301e 559 /******************** Bits definition for ADC_ISR register ******************/
mbed_official 630:825f75ca301e 560 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
mbed_official 630:825f75ca301e 561 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
mbed_official 630:825f75ca301e 562 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
mbed_official 630:825f75ca301e 563 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
mbed_official 630:825f75ca301e 564 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
mbed_official 630:825f75ca301e 565 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
mbed_official 630:825f75ca301e 566
mbed_official 630:825f75ca301e 567 /* Old EOSEQ bit definition, maintained for legacy purpose */
mbed_official 630:825f75ca301e 568 #define ADC_ISR_EOS ADC_ISR_EOSEQ
mbed_official 630:825f75ca301e 569
mbed_official 630:825f75ca301e 570 /******************** Bits definition for ADC_IER register ******************/
mbed_official 630:825f75ca301e 571 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
mbed_official 630:825f75ca301e 572 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
mbed_official 630:825f75ca301e 573 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
mbed_official 630:825f75ca301e 574 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
mbed_official 630:825f75ca301e 575 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
mbed_official 630:825f75ca301e 576 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
mbed_official 630:825f75ca301e 577
mbed_official 630:825f75ca301e 578 /* Old EOSEQIE bit definition, maintained for legacy purpose */
mbed_official 630:825f75ca301e 579 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
mbed_official 630:825f75ca301e 580
mbed_official 630:825f75ca301e 581 /******************** Bits definition for ADC_CR register *******************/
mbed_official 630:825f75ca301e 582 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
mbed_official 630:825f75ca301e 583 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
mbed_official 630:825f75ca301e 584 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
mbed_official 630:825f75ca301e 585 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
mbed_official 630:825f75ca301e 586 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
mbed_official 630:825f75ca301e 587
mbed_official 630:825f75ca301e 588 /******************* Bits definition for ADC_CFGR1 register *****************/
mbed_official 630:825f75ca301e 589 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 630:825f75ca301e 590 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 630:825f75ca301e 591 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 630:825f75ca301e 592 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 630:825f75ca301e 593 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 630:825f75ca301e 594 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 630:825f75ca301e 595 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
mbed_official 630:825f75ca301e 596 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
mbed_official 630:825f75ca301e 597 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
mbed_official 630:825f75ca301e 598 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
mbed_official 630:825f75ca301e 599 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
mbed_official 630:825f75ca301e 600 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
mbed_official 630:825f75ca301e 601 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
mbed_official 630:825f75ca301e 602 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
mbed_official 630:825f75ca301e 603 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 630:825f75ca301e 604 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 630:825f75ca301e 605 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
mbed_official 630:825f75ca301e 606 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 630:825f75ca301e 607 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 630:825f75ca301e 608 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
mbed_official 630:825f75ca301e 609 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
mbed_official 630:825f75ca301e 610 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
mbed_official 630:825f75ca301e 611 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 630:825f75ca301e 612 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 630:825f75ca301e 613 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
mbed_official 630:825f75ca301e 614 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
mbed_official 630:825f75ca301e 615 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
mbed_official 630:825f75ca301e 616
mbed_official 630:825f75ca301e 617 /* Old WAIT bit definition, maintained for legacy purpose */
mbed_official 630:825f75ca301e 618 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
mbed_official 630:825f75ca301e 619
mbed_official 630:825f75ca301e 620 /******************* Bits definition for ADC_CFGR2 register *****************/
mbed_official 630:825f75ca301e 621 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
mbed_official 630:825f75ca301e 622 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
mbed_official 630:825f75ca301e 623 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
mbed_official 630:825f75ca301e 624
mbed_official 630:825f75ca301e 625 /* Old bit definition, maintained for legacy purpose */
mbed_official 630:825f75ca301e 626 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
mbed_official 630:825f75ca301e 627 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
mbed_official 630:825f75ca301e 628
mbed_official 630:825f75ca301e 629 /****************** Bit definition for ADC_SMPR register ********************/
mbed_official 630:825f75ca301e 630 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
mbed_official 630:825f75ca301e 631 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 630:825f75ca301e 632 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 630:825f75ca301e 633 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 630:825f75ca301e 634
mbed_official 630:825f75ca301e 635 /* Old bit definition, maintained for legacy purpose */
mbed_official 630:825f75ca301e 636 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
mbed_official 630:825f75ca301e 637 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
mbed_official 630:825f75ca301e 638 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
mbed_official 630:825f75ca301e 639 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
mbed_official 630:825f75ca301e 640
mbed_official 630:825f75ca301e 641 /******************* Bit definition for ADC_TR register ********************/
mbed_official 630:825f75ca301e 642 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
mbed_official 630:825f75ca301e 643 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
mbed_official 630:825f75ca301e 644
mbed_official 630:825f75ca301e 645 /* Old bit definition, maintained for legacy purpose */
mbed_official 630:825f75ca301e 646 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
mbed_official 630:825f75ca301e 647 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
mbed_official 630:825f75ca301e 648
mbed_official 630:825f75ca301e 649 /****************** Bit definition for ADC_CHSELR register ******************/
mbed_official 630:825f75ca301e 650 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
mbed_official 630:825f75ca301e 651 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
mbed_official 630:825f75ca301e 652 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
mbed_official 630:825f75ca301e 653 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
mbed_official 630:825f75ca301e 654 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
mbed_official 630:825f75ca301e 655 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
mbed_official 630:825f75ca301e 656 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
mbed_official 630:825f75ca301e 657 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
mbed_official 630:825f75ca301e 658 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
mbed_official 630:825f75ca301e 659 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
mbed_official 630:825f75ca301e 660 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
mbed_official 630:825f75ca301e 661 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
mbed_official 630:825f75ca301e 662 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
mbed_official 630:825f75ca301e 663 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
mbed_official 630:825f75ca301e 664 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
mbed_official 630:825f75ca301e 665 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
mbed_official 630:825f75ca301e 666 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
mbed_official 630:825f75ca301e 667 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
mbed_official 630:825f75ca301e 668 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
mbed_official 630:825f75ca301e 669
mbed_official 630:825f75ca301e 670 /******************** Bit definition for ADC_DR register ********************/
mbed_official 630:825f75ca301e 671 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
mbed_official 630:825f75ca301e 672
mbed_official 630:825f75ca301e 673 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 630:825f75ca301e 674 #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
mbed_official 630:825f75ca301e 675 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
mbed_official 630:825f75ca301e 676 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
mbed_official 630:825f75ca301e 677
mbed_official 630:825f75ca301e 678 /******************************************************************************/
mbed_official 630:825f75ca301e 679 /* */
mbed_official 630:825f75ca301e 680 /* CRC calculation unit (CRC) */
mbed_official 630:825f75ca301e 681 /* */
mbed_official 630:825f75ca301e 682 /******************************************************************************/
mbed_official 630:825f75ca301e 683 /******************* Bit definition for CRC_DR register *********************/
mbed_official 630:825f75ca301e 684 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 630:825f75ca301e 685
mbed_official 630:825f75ca301e 686 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 630:825f75ca301e 687 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 630:825f75ca301e 688
mbed_official 630:825f75ca301e 689 /******************** Bit definition for CRC_CR register ********************/
mbed_official 630:825f75ca301e 690 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
mbed_official 630:825f75ca301e 691 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
mbed_official 630:825f75ca301e 692 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
mbed_official 630:825f75ca301e 693 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
mbed_official 630:825f75ca301e 694 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
mbed_official 630:825f75ca301e 695
mbed_official 630:825f75ca301e 696 /******************* Bit definition for CRC_INIT register *******************/
mbed_official 630:825f75ca301e 697 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
mbed_official 630:825f75ca301e 698
mbed_official 630:825f75ca301e 699 /******************************************************************************/
mbed_official 630:825f75ca301e 700 /* */
mbed_official 630:825f75ca301e 701 /* Debug MCU (DBGMCU) */
mbed_official 630:825f75ca301e 702 /* */
mbed_official 630:825f75ca301e 703 /******************************************************************************/
mbed_official 630:825f75ca301e 704
mbed_official 630:825f75ca301e 705 /**************** Bit definition for DBGMCU_IDCODE register *****************/
mbed_official 630:825f75ca301e 706 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
mbed_official 630:825f75ca301e 707
mbed_official 630:825f75ca301e 708 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
mbed_official 630:825f75ca301e 709 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 630:825f75ca301e 710 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 630:825f75ca301e 711 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 630:825f75ca301e 712 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 630:825f75ca301e 713 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 630:825f75ca301e 714 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
mbed_official 630:825f75ca301e 715 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
mbed_official 630:825f75ca301e 716 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
mbed_official 630:825f75ca301e 717 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
mbed_official 630:825f75ca301e 718 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
mbed_official 630:825f75ca301e 719 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
mbed_official 630:825f75ca301e 720 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
mbed_official 630:825f75ca301e 721 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
mbed_official 630:825f75ca301e 722 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
mbed_official 630:825f75ca301e 723 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
mbed_official 630:825f75ca301e 724 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
mbed_official 630:825f75ca301e 725
mbed_official 630:825f75ca301e 726 /****************** Bit definition for DBGMCU_CR register *******************/
mbed_official 630:825f75ca301e 727 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
mbed_official 630:825f75ca301e 728 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
mbed_official 630:825f75ca301e 729
mbed_official 630:825f75ca301e 730 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
mbed_official 630:825f75ca301e 731 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
mbed_official 630:825f75ca301e 732 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
mbed_official 630:825f75ca301e 733 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
mbed_official 630:825f75ca301e 734 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
mbed_official 630:825f75ca301e 735 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
mbed_official 630:825f75ca301e 736 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
mbed_official 630:825f75ca301e 737 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
mbed_official 630:825f75ca301e 738
mbed_official 630:825f75ca301e 739 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
mbed_official 630:825f75ca301e 740 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
mbed_official 630:825f75ca301e 741 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
mbed_official 630:825f75ca301e 742 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
mbed_official 630:825f75ca301e 743
mbed_official 630:825f75ca301e 744 /******************************************************************************/
mbed_official 630:825f75ca301e 745 /* */
mbed_official 630:825f75ca301e 746 /* DMA Controller (DMA) */
mbed_official 630:825f75ca301e 747 /* */
mbed_official 630:825f75ca301e 748 /******************************************************************************/
mbed_official 630:825f75ca301e 749 /******************* Bit definition for DMA_ISR register ********************/
mbed_official 630:825f75ca301e 750 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
mbed_official 630:825f75ca301e 751 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
mbed_official 630:825f75ca301e 752 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
mbed_official 630:825f75ca301e 753 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
mbed_official 630:825f75ca301e 754 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
mbed_official 630:825f75ca301e 755 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
mbed_official 630:825f75ca301e 756 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
mbed_official 630:825f75ca301e 757 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
mbed_official 630:825f75ca301e 758 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
mbed_official 630:825f75ca301e 759 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
mbed_official 630:825f75ca301e 760 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
mbed_official 630:825f75ca301e 761 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
mbed_official 630:825f75ca301e 762 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
mbed_official 630:825f75ca301e 763 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
mbed_official 630:825f75ca301e 764 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
mbed_official 630:825f75ca301e 765 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
mbed_official 630:825f75ca301e 766 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
mbed_official 630:825f75ca301e 767 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
mbed_official 630:825f75ca301e 768 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
mbed_official 630:825f75ca301e 769 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
mbed_official 630:825f75ca301e 770
mbed_official 630:825f75ca301e 771 /******************* Bit definition for DMA_IFCR register *******************/
mbed_official 630:825f75ca301e 772 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
mbed_official 630:825f75ca301e 773 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
mbed_official 630:825f75ca301e 774 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
mbed_official 630:825f75ca301e 775 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
mbed_official 630:825f75ca301e 776 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
mbed_official 630:825f75ca301e 777 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
mbed_official 630:825f75ca301e 778 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
mbed_official 630:825f75ca301e 779 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
mbed_official 630:825f75ca301e 780 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
mbed_official 630:825f75ca301e 781 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
mbed_official 630:825f75ca301e 782 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
mbed_official 630:825f75ca301e 783 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
mbed_official 630:825f75ca301e 784 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
mbed_official 630:825f75ca301e 785 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
mbed_official 630:825f75ca301e 786 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
mbed_official 630:825f75ca301e 787 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
mbed_official 630:825f75ca301e 788 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
mbed_official 630:825f75ca301e 789 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
mbed_official 630:825f75ca301e 790 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
mbed_official 630:825f75ca301e 791 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
mbed_official 630:825f75ca301e 792
mbed_official 630:825f75ca301e 793 /******************* Bit definition for DMA_CCR register ********************/
mbed_official 630:825f75ca301e 794 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
mbed_official 630:825f75ca301e 795 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
mbed_official 630:825f75ca301e 796 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
mbed_official 630:825f75ca301e 797 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
mbed_official 630:825f75ca301e 798 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
mbed_official 630:825f75ca301e 799 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
mbed_official 630:825f75ca301e 800 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
mbed_official 630:825f75ca301e 801 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
mbed_official 630:825f75ca301e 802
mbed_official 630:825f75ca301e 803 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
mbed_official 630:825f75ca301e 804 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 630:825f75ca301e 805 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 630:825f75ca301e 806
mbed_official 630:825f75ca301e 807 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
mbed_official 630:825f75ca301e 808 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 630:825f75ca301e 809 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 630:825f75ca301e 810
mbed_official 630:825f75ca301e 811 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
mbed_official 630:825f75ca301e 812 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 630:825f75ca301e 813 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 630:825f75ca301e 814
mbed_official 630:825f75ca301e 815 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
mbed_official 630:825f75ca301e 816
mbed_official 630:825f75ca301e 817 /****************** Bit definition for DMA_CNDTR register *******************/
mbed_official 630:825f75ca301e 818 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 630:825f75ca301e 819
mbed_official 630:825f75ca301e 820 /****************** Bit definition for DMA_CPAR register ********************/
mbed_official 630:825f75ca301e 821 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 630:825f75ca301e 822
mbed_official 630:825f75ca301e 823 /****************** Bit definition for DMA_CMAR register ********************/
mbed_official 630:825f75ca301e 824 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 630:825f75ca301e 825
mbed_official 630:825f75ca301e 826 /******************************************************************************/
mbed_official 630:825f75ca301e 827 /* */
mbed_official 630:825f75ca301e 828 /* External Interrupt/Event Controller (EXTI) */
mbed_official 630:825f75ca301e 829 /* */
mbed_official 630:825f75ca301e 830 /******************************************************************************/
mbed_official 630:825f75ca301e 831 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 630:825f75ca301e 832 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 630:825f75ca301e 833 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 630:825f75ca301e 834 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 630:825f75ca301e 835 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 630:825f75ca301e 836 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 630:825f75ca301e 837 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 630:825f75ca301e 838 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 630:825f75ca301e 839 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 630:825f75ca301e 840 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 630:825f75ca301e 841 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 630:825f75ca301e 842 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 630:825f75ca301e 843 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 630:825f75ca301e 844 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 630:825f75ca301e 845 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 630:825f75ca301e 846 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 630:825f75ca301e 847 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 630:825f75ca301e 848 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 630:825f75ca301e 849 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 630:825f75ca301e 850 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 630:825f75ca301e 851 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 630:825f75ca301e 852 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 630:825f75ca301e 853 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
mbed_official 630:825f75ca301e 854 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
mbed_official 630:825f75ca301e 855 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
mbed_official 630:825f75ca301e 856
mbed_official 630:825f75ca301e 857 /****************** Bit definition for EXTI_EMR register ********************/
mbed_official 630:825f75ca301e 858 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 630:825f75ca301e 859 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 630:825f75ca301e 860 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 630:825f75ca301e 861 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 630:825f75ca301e 862 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 630:825f75ca301e 863 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 630:825f75ca301e 864 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 630:825f75ca301e 865 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 630:825f75ca301e 866 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 630:825f75ca301e 867 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 630:825f75ca301e 868 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 630:825f75ca301e 869 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 630:825f75ca301e 870 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 630:825f75ca301e 871 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 630:825f75ca301e 872 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 630:825f75ca301e 873 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 630:825f75ca301e 874 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 630:825f75ca301e 875 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 630:825f75ca301e 876 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 630:825f75ca301e 877 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 630:825f75ca301e 878 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 630:825f75ca301e 879 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
mbed_official 630:825f75ca301e 880 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
mbed_official 630:825f75ca301e 881 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
mbed_official 630:825f75ca301e 882
mbed_official 630:825f75ca301e 883 /******************* Bit definition for EXTI_RTSR register ******************/
mbed_official 630:825f75ca301e 884 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 630:825f75ca301e 885 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 630:825f75ca301e 886 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 630:825f75ca301e 887 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 630:825f75ca301e 888 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 630:825f75ca301e 889 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 630:825f75ca301e 890 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 630:825f75ca301e 891 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 630:825f75ca301e 892 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 630:825f75ca301e 893 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 630:825f75ca301e 894 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 630:825f75ca301e 895 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 630:825f75ca301e 896 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 630:825f75ca301e 897 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 630:825f75ca301e 898 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 630:825f75ca301e 899 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 630:825f75ca301e 900 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 630:825f75ca301e 901 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 630:825f75ca301e 902 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 630:825f75ca301e 903
mbed_official 630:825f75ca301e 904 /******************* Bit definition for EXTI_FTSR register *******************/
mbed_official 630:825f75ca301e 905 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 630:825f75ca301e 906 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 630:825f75ca301e 907 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 630:825f75ca301e 908 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 630:825f75ca301e 909 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 630:825f75ca301e 910 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 630:825f75ca301e 911 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 630:825f75ca301e 912 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 630:825f75ca301e 913 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 630:825f75ca301e 914 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 630:825f75ca301e 915 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 630:825f75ca301e 916 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 630:825f75ca301e 917 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 630:825f75ca301e 918 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 630:825f75ca301e 919 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 630:825f75ca301e 920 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 630:825f75ca301e 921 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 630:825f75ca301e 922 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 630:825f75ca301e 923 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 630:825f75ca301e 924
mbed_official 630:825f75ca301e 925 /******************* Bit definition for EXTI_SWIER register *******************/
mbed_official 630:825f75ca301e 926 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 630:825f75ca301e 927 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 630:825f75ca301e 928 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 630:825f75ca301e 929 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 630:825f75ca301e 930 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 630:825f75ca301e 931 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 630:825f75ca301e 932 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 630:825f75ca301e 933 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 630:825f75ca301e 934 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 630:825f75ca301e 935 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 630:825f75ca301e 936 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 630:825f75ca301e 937 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 630:825f75ca301e 938 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 630:825f75ca301e 939 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 630:825f75ca301e 940 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 630:825f75ca301e 941 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 630:825f75ca301e 942 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 630:825f75ca301e 943 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 630:825f75ca301e 944 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 630:825f75ca301e 945
mbed_official 630:825f75ca301e 946 /****************** Bit definition for EXTI_PR register *********************/
mbed_official 630:825f75ca301e 947 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
mbed_official 630:825f75ca301e 948 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
mbed_official 630:825f75ca301e 949 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
mbed_official 630:825f75ca301e 950 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
mbed_official 630:825f75ca301e 951 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
mbed_official 630:825f75ca301e 952 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
mbed_official 630:825f75ca301e 953 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
mbed_official 630:825f75ca301e 954 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
mbed_official 630:825f75ca301e 955 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
mbed_official 630:825f75ca301e 956 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
mbed_official 630:825f75ca301e 957 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
mbed_official 630:825f75ca301e 958 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
mbed_official 630:825f75ca301e 959 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
mbed_official 630:825f75ca301e 960 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
mbed_official 630:825f75ca301e 961 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
mbed_official 630:825f75ca301e 962 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
mbed_official 630:825f75ca301e 963 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
mbed_official 630:825f75ca301e 964 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
mbed_official 630:825f75ca301e 965 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
mbed_official 630:825f75ca301e 966
mbed_official 630:825f75ca301e 967 /******************************************************************************/
mbed_official 630:825f75ca301e 968 /* */
mbed_official 630:825f75ca301e 969 /* FLASH and Option Bytes Registers */
mbed_official 630:825f75ca301e 970 /* */
mbed_official 630:825f75ca301e 971 /******************************************************************************/
mbed_official 630:825f75ca301e 972
mbed_official 630:825f75ca301e 973 /******************* Bit definition for FLASH_ACR register ******************/
mbed_official 630:825f75ca301e 974 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
mbed_official 630:825f75ca301e 975
mbed_official 630:825f75ca301e 976 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
mbed_official 630:825f75ca301e 977 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
mbed_official 630:825f75ca301e 978
mbed_official 630:825f75ca301e 979 /****************** Bit definition for FLASH_KEYR register ******************/
mbed_official 630:825f75ca301e 980 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
mbed_official 630:825f75ca301e 981
mbed_official 630:825f75ca301e 982 /***************** Bit definition for FLASH_OPTKEYR register ****************/
mbed_official 630:825f75ca301e 983 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
mbed_official 630:825f75ca301e 984
mbed_official 630:825f75ca301e 985 /****************** FLASH Keys **********************************************/
mbed_official 630:825f75ca301e 986 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
mbed_official 630:825f75ca301e 987 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
mbed_official 630:825f75ca301e 988 to unlock the write access to the FPEC. */
mbed_official 630:825f75ca301e 989
mbed_official 630:825f75ca301e 990 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
mbed_official 630:825f75ca301e 991 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
mbed_official 630:825f75ca301e 992 unlock the write access to the option byte block */
mbed_official 630:825f75ca301e 993
mbed_official 630:825f75ca301e 994 /****************** Bit definition for FLASH_SR register *******************/
mbed_official 630:825f75ca301e 995 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
mbed_official 630:825f75ca301e 996 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
mbed_official 630:825f75ca301e 997 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
mbed_official 630:825f75ca301e 998 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
mbed_official 630:825f75ca301e 999 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
mbed_official 630:825f75ca301e 1000
mbed_official 630:825f75ca301e 1001 /******************* Bit definition for FLASH_CR register *******************/
mbed_official 630:825f75ca301e 1002 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
mbed_official 630:825f75ca301e 1003 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
mbed_official 630:825f75ca301e 1004 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
mbed_official 630:825f75ca301e 1005 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
mbed_official 630:825f75ca301e 1006 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
mbed_official 630:825f75ca301e 1007 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
mbed_official 630:825f75ca301e 1008 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
mbed_official 630:825f75ca301e 1009 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
mbed_official 630:825f75ca301e 1010 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
mbed_official 630:825f75ca301e 1011 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
mbed_official 630:825f75ca301e 1012 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
mbed_official 630:825f75ca301e 1013
mbed_official 630:825f75ca301e 1014 /******************* Bit definition for FLASH_AR register *******************/
mbed_official 630:825f75ca301e 1015 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
mbed_official 630:825f75ca301e 1016
mbed_official 630:825f75ca301e 1017 /****************** Bit definition for FLASH_OBR register *******************/
mbed_official 630:825f75ca301e 1018 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
mbed_official 630:825f75ca301e 1019 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
mbed_official 630:825f75ca301e 1020 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
mbed_official 630:825f75ca301e 1021
mbed_official 630:825f75ca301e 1022 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
mbed_official 630:825f75ca301e 1023 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
mbed_official 630:825f75ca301e 1024 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
mbed_official 630:825f75ca301e 1025 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
mbed_official 630:825f75ca301e 1026 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
mbed_official 630:825f75ca301e 1027 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
mbed_official 630:825f75ca301e 1028 #define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
mbed_official 630:825f75ca301e 1029
mbed_official 630:825f75ca301e 1030 /* Old BOOT1 bit definition, maintained for legacy purpose */
mbed_official 630:825f75ca301e 1031 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
mbed_official 630:825f75ca301e 1032
mbed_official 630:825f75ca301e 1033 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
mbed_official 630:825f75ca301e 1034 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
mbed_official 630:825f75ca301e 1035
mbed_official 630:825f75ca301e 1036 /****************** Bit definition for FLASH_WRPR register ******************/
mbed_official 630:825f75ca301e 1037 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
mbed_official 630:825f75ca301e 1038
mbed_official 630:825f75ca301e 1039 /*----------------------------------------------------------------------------*/
mbed_official 630:825f75ca301e 1040
mbed_official 630:825f75ca301e 1041 /****************** Bit definition for OB_RDP register **********************/
mbed_official 630:825f75ca301e 1042 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
mbed_official 630:825f75ca301e 1043 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
mbed_official 630:825f75ca301e 1044
mbed_official 630:825f75ca301e 1045 /****************** Bit definition for OB_USER register *********************/
mbed_official 630:825f75ca301e 1046 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
mbed_official 630:825f75ca301e 1047 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
mbed_official 630:825f75ca301e 1048
mbed_official 630:825f75ca301e 1049 /****************** Bit definition for OB_WRP0 register *********************/
mbed_official 630:825f75ca301e 1050 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 630:825f75ca301e 1051 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 630:825f75ca301e 1052
mbed_official 630:825f75ca301e 1053 /******************************************************************************/
mbed_official 630:825f75ca301e 1054 /* */
mbed_official 630:825f75ca301e 1055 /* General Purpose IOs (GPIO) */
mbed_official 630:825f75ca301e 1056 /* */
mbed_official 630:825f75ca301e 1057 /******************************************************************************/
mbed_official 630:825f75ca301e 1058 /******************* Bit definition for GPIO_MODER register *****************/
mbed_official 630:825f75ca301e 1059 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 630:825f75ca301e 1060 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 1061 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 1062 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 630:825f75ca301e 1063 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 1064 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 1065 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 630:825f75ca301e 1066 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 1067 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 1068 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 630:825f75ca301e 1069 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 1070 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 630:825f75ca301e 1071 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 630:825f75ca301e 1072 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 1073 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 1074 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 630:825f75ca301e 1075 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 1076 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 1077 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 630:825f75ca301e 1078 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 1079 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 1080 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 630:825f75ca301e 1081 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 1082 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 1083 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 630:825f75ca301e 1084 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 630:825f75ca301e 1085 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 630:825f75ca301e 1086 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 630:825f75ca301e 1087 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 630:825f75ca301e 1088 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 630:825f75ca301e 1089 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 630:825f75ca301e 1090 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 630:825f75ca301e 1091 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 630:825f75ca301e 1092 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 630:825f75ca301e 1093 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 630:825f75ca301e 1094 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 630:825f75ca301e 1095 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 630:825f75ca301e 1096 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 630:825f75ca301e 1097 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 630:825f75ca301e 1098 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 630:825f75ca301e 1099 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 630:825f75ca301e 1100 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 630:825f75ca301e 1101 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 630:825f75ca301e 1102 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 630:825f75ca301e 1103 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 630:825f75ca301e 1104 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 630:825f75ca301e 1105 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 630:825f75ca301e 1106 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 630:825f75ca301e 1107
mbed_official 630:825f75ca301e 1108 /****************** Bit definition for GPIO_OTYPER register *****************/
mbed_official 630:825f75ca301e 1109 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 1110 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 1111 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 1112 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 1113 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 1114 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 1115 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 1116 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 630:825f75ca301e 1117 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 1118 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 1119 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 1120 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 1121 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 1122 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 1123 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 1124 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 1125
mbed_official 630:825f75ca301e 1126 /**************** Bit definition for GPIO_OSPEEDR register ******************/
mbed_official 630:825f75ca301e 1127 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 630:825f75ca301e 1128 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 1129 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 1130 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 630:825f75ca301e 1131 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 1132 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 1133 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 630:825f75ca301e 1134 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 1135 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 1136 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 630:825f75ca301e 1137 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 1138 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 630:825f75ca301e 1139 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 630:825f75ca301e 1140 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 1141 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 1142 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 630:825f75ca301e 1143 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 1144 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 1145 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 630:825f75ca301e 1146 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 1147 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 1148 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 630:825f75ca301e 1149 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 1150 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 1151 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 630:825f75ca301e 1152 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 630:825f75ca301e 1153 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 630:825f75ca301e 1154 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 630:825f75ca301e 1155 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 630:825f75ca301e 1156 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 630:825f75ca301e 1157 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 630:825f75ca301e 1158 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 630:825f75ca301e 1159 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 630:825f75ca301e 1160 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 630:825f75ca301e 1161 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 630:825f75ca301e 1162 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 630:825f75ca301e 1163 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 630:825f75ca301e 1164 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 630:825f75ca301e 1165 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 630:825f75ca301e 1166 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 630:825f75ca301e 1167 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 630:825f75ca301e 1168 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 630:825f75ca301e 1169 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 630:825f75ca301e 1170 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 630:825f75ca301e 1171 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 630:825f75ca301e 1172 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 630:825f75ca301e 1173 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 630:825f75ca301e 1174 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 630:825f75ca301e 1175
mbed_official 630:825f75ca301e 1176 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
mbed_official 630:825f75ca301e 1177 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
mbed_official 630:825f75ca301e 1178 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
mbed_official 630:825f75ca301e 1179 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
mbed_official 630:825f75ca301e 1180 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
mbed_official 630:825f75ca301e 1181 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
mbed_official 630:825f75ca301e 1182 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
mbed_official 630:825f75ca301e 1183 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
mbed_official 630:825f75ca301e 1184 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
mbed_official 630:825f75ca301e 1185 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
mbed_official 630:825f75ca301e 1186 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
mbed_official 630:825f75ca301e 1187 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
mbed_official 630:825f75ca301e 1188 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
mbed_official 630:825f75ca301e 1189 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
mbed_official 630:825f75ca301e 1190 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
mbed_official 630:825f75ca301e 1191 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
mbed_official 630:825f75ca301e 1192 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
mbed_official 630:825f75ca301e 1193 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
mbed_official 630:825f75ca301e 1194 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
mbed_official 630:825f75ca301e 1195 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
mbed_official 630:825f75ca301e 1196 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
mbed_official 630:825f75ca301e 1197 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
mbed_official 630:825f75ca301e 1198 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
mbed_official 630:825f75ca301e 1199 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
mbed_official 630:825f75ca301e 1200 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
mbed_official 630:825f75ca301e 1201 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
mbed_official 630:825f75ca301e 1202 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
mbed_official 630:825f75ca301e 1203 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
mbed_official 630:825f75ca301e 1204 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
mbed_official 630:825f75ca301e 1205 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
mbed_official 630:825f75ca301e 1206 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
mbed_official 630:825f75ca301e 1207 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
mbed_official 630:825f75ca301e 1208 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
mbed_official 630:825f75ca301e 1209 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
mbed_official 630:825f75ca301e 1210 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
mbed_official 630:825f75ca301e 1211 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
mbed_official 630:825f75ca301e 1212 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
mbed_official 630:825f75ca301e 1213 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
mbed_official 630:825f75ca301e 1214 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
mbed_official 630:825f75ca301e 1215 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
mbed_official 630:825f75ca301e 1216 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
mbed_official 630:825f75ca301e 1217 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
mbed_official 630:825f75ca301e 1218 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
mbed_official 630:825f75ca301e 1219 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
mbed_official 630:825f75ca301e 1220 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
mbed_official 630:825f75ca301e 1221 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
mbed_official 630:825f75ca301e 1222 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
mbed_official 630:825f75ca301e 1223 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
mbed_official 630:825f75ca301e 1224 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
mbed_official 630:825f75ca301e 1225
mbed_official 630:825f75ca301e 1226 /******************* Bit definition for GPIO_PUPDR register ******************/
mbed_official 630:825f75ca301e 1227 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 630:825f75ca301e 1228 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 1229 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 1230 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 630:825f75ca301e 1231 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 1232 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 1233 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 630:825f75ca301e 1234 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 1235 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 1236 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 630:825f75ca301e 1237 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 1238 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 630:825f75ca301e 1239 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 630:825f75ca301e 1240 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 1241 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 1242 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 630:825f75ca301e 1243 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 1244 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 1245 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 630:825f75ca301e 1246 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 1247 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 1248 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 630:825f75ca301e 1249 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 1250 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 1251 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 630:825f75ca301e 1252 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 630:825f75ca301e 1253 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 630:825f75ca301e 1254 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 630:825f75ca301e 1255 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 630:825f75ca301e 1256 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 630:825f75ca301e 1257 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 630:825f75ca301e 1258 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 630:825f75ca301e 1259 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 630:825f75ca301e 1260 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 630:825f75ca301e 1261 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 630:825f75ca301e 1262 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 630:825f75ca301e 1263 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 630:825f75ca301e 1264 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 630:825f75ca301e 1265 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 630:825f75ca301e 1266 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 630:825f75ca301e 1267 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 630:825f75ca301e 1268 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 630:825f75ca301e 1269 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 630:825f75ca301e 1270 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 630:825f75ca301e 1271 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 630:825f75ca301e 1272 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 630:825f75ca301e 1273 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 630:825f75ca301e 1274 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 630:825f75ca301e 1275
mbed_official 630:825f75ca301e 1276 /******************* Bit definition for GPIO_IDR register *******************/
mbed_official 630:825f75ca301e 1277 #define GPIO_IDR_0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 1278 #define GPIO_IDR_1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 1279 #define GPIO_IDR_2 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 1280 #define GPIO_IDR_3 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 1281 #define GPIO_IDR_4 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 1282 #define GPIO_IDR_5 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 1283 #define GPIO_IDR_6 ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 1284 #define GPIO_IDR_7 ((uint32_t)0x00000080)
mbed_official 630:825f75ca301e 1285 #define GPIO_IDR_8 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 1286 #define GPIO_IDR_9 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 1287 #define GPIO_IDR_10 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 1288 #define GPIO_IDR_11 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 1289 #define GPIO_IDR_12 ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 1290 #define GPIO_IDR_13 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 1291 #define GPIO_IDR_14 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 1292 #define GPIO_IDR_15 ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 1293
mbed_official 630:825f75ca301e 1294 /****************** Bit definition for GPIO_ODR register ********************/
mbed_official 630:825f75ca301e 1295 #define GPIO_ODR_0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 1296 #define GPIO_ODR_1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 1297 #define GPIO_ODR_2 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 1298 #define GPIO_ODR_3 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 1299 #define GPIO_ODR_4 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 1300 #define GPIO_ODR_5 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 1301 #define GPIO_ODR_6 ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 1302 #define GPIO_ODR_7 ((uint32_t)0x00000080)
mbed_official 630:825f75ca301e 1303 #define GPIO_ODR_8 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 1304 #define GPIO_ODR_9 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 1305 #define GPIO_ODR_10 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 1306 #define GPIO_ODR_11 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 1307 #define GPIO_ODR_12 ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 1308 #define GPIO_ODR_13 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 1309 #define GPIO_ODR_14 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 1310 #define GPIO_ODR_15 ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 1311
mbed_official 630:825f75ca301e 1312 /****************** Bit definition for GPIO_BSRR register ********************/
mbed_official 630:825f75ca301e 1313 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 1314 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 1315 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 1316 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 1317 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 1318 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 1319 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 1320 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 630:825f75ca301e 1321 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 1322 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 1323 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 1324 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 1325 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 1326 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 1327 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 1328 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 1329 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 630:825f75ca301e 1330 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 630:825f75ca301e 1331 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 630:825f75ca301e 1332 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 630:825f75ca301e 1333 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 630:825f75ca301e 1334 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 630:825f75ca301e 1335 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 630:825f75ca301e 1336 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 630:825f75ca301e 1337 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 630:825f75ca301e 1338 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 630:825f75ca301e 1339 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 630:825f75ca301e 1340 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 630:825f75ca301e 1341 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 630:825f75ca301e 1342 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 630:825f75ca301e 1343 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 630:825f75ca301e 1344 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 630:825f75ca301e 1345
mbed_official 630:825f75ca301e 1346 /****************** Bit definition for GPIO_LCKR register ********************/
mbed_official 630:825f75ca301e 1347 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 1348 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 1349 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 1350 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 1351 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 1352 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 1353 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 1354 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 630:825f75ca301e 1355 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 1356 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 1357 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 1358 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 1359 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 1360 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 1361 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 1362 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 1363 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 630:825f75ca301e 1364
mbed_official 630:825f75ca301e 1365 /****************** Bit definition for GPIO_AFRL register ********************/
mbed_official 630:825f75ca301e 1366 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
mbed_official 630:825f75ca301e 1367 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
mbed_official 630:825f75ca301e 1368 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
mbed_official 630:825f75ca301e 1369 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
mbed_official 630:825f75ca301e 1370 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
mbed_official 630:825f75ca301e 1371 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
mbed_official 630:825f75ca301e 1372 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
mbed_official 630:825f75ca301e 1373 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
mbed_official 630:825f75ca301e 1374
mbed_official 630:825f75ca301e 1375 /****************** Bit definition for GPIO_AFRH register ********************/
mbed_official 630:825f75ca301e 1376 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
mbed_official 630:825f75ca301e 1377 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
mbed_official 630:825f75ca301e 1378 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
mbed_official 630:825f75ca301e 1379 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
mbed_official 630:825f75ca301e 1380 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
mbed_official 630:825f75ca301e 1381 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
mbed_official 630:825f75ca301e 1382 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
mbed_official 630:825f75ca301e 1383 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
mbed_official 630:825f75ca301e 1384
mbed_official 630:825f75ca301e 1385 /****************** Bit definition for GPIO_BRR register *********************/
mbed_official 630:825f75ca301e 1386 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 1387 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 1388 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 1389 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 1390 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 1391 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 1392 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 1393 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
mbed_official 630:825f75ca301e 1394 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 1395 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 1396 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 1397 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 1398 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 1399 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 1400 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 1401 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 1402
mbed_official 630:825f75ca301e 1403 /******************************************************************************/
mbed_official 630:825f75ca301e 1404 /* */
mbed_official 630:825f75ca301e 1405 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 630:825f75ca301e 1406 /* */
mbed_official 630:825f75ca301e 1407 /******************************************************************************/
mbed_official 630:825f75ca301e 1408
mbed_official 630:825f75ca301e 1409 /******************* Bit definition for I2C_CR1 register *******************/
mbed_official 630:825f75ca301e 1410 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
mbed_official 630:825f75ca301e 1411 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
mbed_official 630:825f75ca301e 1412 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
mbed_official 630:825f75ca301e 1413 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
mbed_official 630:825f75ca301e 1414 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
mbed_official 630:825f75ca301e 1415 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
mbed_official 630:825f75ca301e 1416 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
mbed_official 630:825f75ca301e 1417 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
mbed_official 630:825f75ca301e 1418 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
mbed_official 630:825f75ca301e 1419 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
mbed_official 630:825f75ca301e 1420 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
mbed_official 630:825f75ca301e 1421 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
mbed_official 630:825f75ca301e 1422 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
mbed_official 630:825f75ca301e 1423 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
mbed_official 630:825f75ca301e 1424 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
mbed_official 630:825f75ca301e 1425 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
mbed_official 630:825f75ca301e 1426 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
mbed_official 630:825f75ca301e 1427 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
mbed_official 630:825f75ca301e 1428 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
mbed_official 630:825f75ca301e 1429 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
mbed_official 630:825f75ca301e 1430 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
mbed_official 630:825f75ca301e 1431
mbed_official 630:825f75ca301e 1432 /****************** Bit definition for I2C_CR2 register ********************/
mbed_official 630:825f75ca301e 1433 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
mbed_official 630:825f75ca301e 1434 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
mbed_official 630:825f75ca301e 1435 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
mbed_official 630:825f75ca301e 1436 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
mbed_official 630:825f75ca301e 1437 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
mbed_official 630:825f75ca301e 1438 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
mbed_official 630:825f75ca301e 1439 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
mbed_official 630:825f75ca301e 1440 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
mbed_official 630:825f75ca301e 1441 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
mbed_official 630:825f75ca301e 1442 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
mbed_official 630:825f75ca301e 1443 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
mbed_official 630:825f75ca301e 1444
mbed_official 630:825f75ca301e 1445 /******************* Bit definition for I2C_OAR1 register ******************/
mbed_official 630:825f75ca301e 1446 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
mbed_official 630:825f75ca301e 1447 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
mbed_official 630:825f75ca301e 1448 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
mbed_official 630:825f75ca301e 1449
mbed_official 630:825f75ca301e 1450 /******************* Bit definition for I2C_OAR2 register ******************/
mbed_official 630:825f75ca301e 1451 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
mbed_official 630:825f75ca301e 1452 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
mbed_official 630:825f75ca301e 1453 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
mbed_official 630:825f75ca301e 1454
mbed_official 630:825f75ca301e 1455 /******************* Bit definition for I2C_TIMINGR register ****************/
mbed_official 630:825f75ca301e 1456 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
mbed_official 630:825f75ca301e 1457 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
mbed_official 630:825f75ca301e 1458 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
mbed_official 630:825f75ca301e 1459 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
mbed_official 630:825f75ca301e 1460 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
mbed_official 630:825f75ca301e 1461
mbed_official 630:825f75ca301e 1462 /******************* Bit definition for I2C_TIMEOUTR register ****************/
mbed_official 630:825f75ca301e 1463 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
mbed_official 630:825f75ca301e 1464 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
mbed_official 630:825f75ca301e 1465 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
mbed_official 630:825f75ca301e 1466 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
mbed_official 630:825f75ca301e 1467 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
mbed_official 630:825f75ca301e 1468
mbed_official 630:825f75ca301e 1469 /****************** Bit definition for I2C_ISR register ********************/
mbed_official 630:825f75ca301e 1470 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
mbed_official 630:825f75ca301e 1471 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
mbed_official 630:825f75ca301e 1472 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
mbed_official 630:825f75ca301e 1473 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
mbed_official 630:825f75ca301e 1474 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
mbed_official 630:825f75ca301e 1475 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
mbed_official 630:825f75ca301e 1476 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
mbed_official 630:825f75ca301e 1477 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
mbed_official 630:825f75ca301e 1478 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
mbed_official 630:825f75ca301e 1479 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
mbed_official 630:825f75ca301e 1480 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
mbed_official 630:825f75ca301e 1481 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
mbed_official 630:825f75ca301e 1482 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
mbed_official 630:825f75ca301e 1483 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
mbed_official 630:825f75ca301e 1484 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
mbed_official 630:825f75ca301e 1485 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
mbed_official 630:825f75ca301e 1486 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
mbed_official 630:825f75ca301e 1487
mbed_official 630:825f75ca301e 1488 /****************** Bit definition for I2C_ICR register ********************/
mbed_official 630:825f75ca301e 1489 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
mbed_official 630:825f75ca301e 1490 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
mbed_official 630:825f75ca301e 1491 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
mbed_official 630:825f75ca301e 1492 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
mbed_official 630:825f75ca301e 1493 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
mbed_official 630:825f75ca301e 1494 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
mbed_official 630:825f75ca301e 1495 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
mbed_official 630:825f75ca301e 1496 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
mbed_official 630:825f75ca301e 1497 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
mbed_official 630:825f75ca301e 1498
mbed_official 630:825f75ca301e 1499 /****************** Bit definition for I2C_PECR register *******************/
mbed_official 630:825f75ca301e 1500 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
mbed_official 630:825f75ca301e 1501
mbed_official 630:825f75ca301e 1502 /****************** Bit definition for I2C_RXDR register *********************/
mbed_official 630:825f75ca301e 1503 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
mbed_official 630:825f75ca301e 1504
mbed_official 630:825f75ca301e 1505 /****************** Bit definition for I2C_TXDR register *******************/
mbed_official 630:825f75ca301e 1506 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
mbed_official 630:825f75ca301e 1507
mbed_official 630:825f75ca301e 1508 /*****************************************************************************/
mbed_official 630:825f75ca301e 1509 /* */
mbed_official 630:825f75ca301e 1510 /* Independent WATCHDOG (IWDG) */
mbed_official 630:825f75ca301e 1511 /* */
mbed_official 630:825f75ca301e 1512 /*****************************************************************************/
mbed_official 630:825f75ca301e 1513 /******************* Bit definition for IWDG_KR register *******************/
mbed_official 630:825f75ca301e 1514 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
mbed_official 630:825f75ca301e 1515
mbed_official 630:825f75ca301e 1516 /******************* Bit definition for IWDG_PR register *******************/
mbed_official 630:825f75ca301e 1517 #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
mbed_official 630:825f75ca301e 1518 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
mbed_official 630:825f75ca301e 1519 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
mbed_official 630:825f75ca301e 1520 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
mbed_official 630:825f75ca301e 1521
mbed_official 630:825f75ca301e 1522 /******************* Bit definition for IWDG_RLR register ******************/
mbed_official 630:825f75ca301e 1523 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
mbed_official 630:825f75ca301e 1524
mbed_official 630:825f75ca301e 1525 /******************* Bit definition for IWDG_SR register *******************/
mbed_official 630:825f75ca301e 1526 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
mbed_official 630:825f75ca301e 1527 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
mbed_official 630:825f75ca301e 1528 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
mbed_official 630:825f75ca301e 1529
mbed_official 630:825f75ca301e 1530 /******************* Bit definition for IWDG_KR register *******************/
mbed_official 630:825f75ca301e 1531 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
mbed_official 630:825f75ca301e 1532
mbed_official 630:825f75ca301e 1533 /*****************************************************************************/
mbed_official 630:825f75ca301e 1534 /* */
mbed_official 630:825f75ca301e 1535 /* Power Control (PWR) */
mbed_official 630:825f75ca301e 1536 /* */
mbed_official 630:825f75ca301e 1537 /*****************************************************************************/
mbed_official 630:825f75ca301e 1538
mbed_official 630:825f75ca301e 1539 /******************** Bit definition for PWR_CR register *******************/
mbed_official 630:825f75ca301e 1540 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
mbed_official 630:825f75ca301e 1541 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 630:825f75ca301e 1542 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 630:825f75ca301e 1543 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 630:825f75ca301e 1544 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 630:825f75ca301e 1545
mbed_official 630:825f75ca301e 1546 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 630:825f75ca301e 1547 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 630:825f75ca301e 1548 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 630:825f75ca301e 1549 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 630:825f75ca301e 1550
mbed_official 630:825f75ca301e 1551 /*!< PVD level configuration */
mbed_official 630:825f75ca301e 1552 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 630:825f75ca301e 1553 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 630:825f75ca301e 1554 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 630:825f75ca301e 1555 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 630:825f75ca301e 1556 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 630:825f75ca301e 1557 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 630:825f75ca301e 1558 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 630:825f75ca301e 1559 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 630:825f75ca301e 1560
mbed_official 630:825f75ca301e 1561 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 630:825f75ca301e 1562
mbed_official 630:825f75ca301e 1563 /******************* Bit definition for PWR_CSR register *******************/
mbed_official 630:825f75ca301e 1564 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 630:825f75ca301e 1565 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 630:825f75ca301e 1566 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 630:825f75ca301e 1567 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
mbed_official 630:825f75ca301e 1568
mbed_official 630:825f75ca301e 1569 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
mbed_official 630:825f75ca301e 1570 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
mbed_official 630:825f75ca301e 1571
mbed_official 630:825f75ca301e 1572 /*****************************************************************************/
mbed_official 630:825f75ca301e 1573 /* */
mbed_official 630:825f75ca301e 1574 /* Reset and Clock Control */
mbed_official 630:825f75ca301e 1575 /* */
mbed_official 630:825f75ca301e 1576 /*****************************************************************************/
mbed_official 630:825f75ca301e 1577
mbed_official 630:825f75ca301e 1578 /******************** Bit definition for RCC_CR register *******************/
mbed_official 630:825f75ca301e 1579 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
mbed_official 630:825f75ca301e 1580 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
mbed_official 630:825f75ca301e 1581
mbed_official 630:825f75ca301e 1582 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
mbed_official 630:825f75ca301e 1583 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 630:825f75ca301e 1584 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 630:825f75ca301e 1585 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 630:825f75ca301e 1586 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
mbed_official 630:825f75ca301e 1587 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
mbed_official 630:825f75ca301e 1588
mbed_official 630:825f75ca301e 1589 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
mbed_official 630:825f75ca301e 1590 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 630:825f75ca301e 1591 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 630:825f75ca301e 1592 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 630:825f75ca301e 1593 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 630:825f75ca301e 1594 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 630:825f75ca301e 1595 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 630:825f75ca301e 1596 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 630:825f75ca301e 1597 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 630:825f75ca301e 1598
mbed_official 630:825f75ca301e 1599 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
mbed_official 630:825f75ca301e 1600 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
mbed_official 630:825f75ca301e 1601 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
mbed_official 630:825f75ca301e 1602 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
mbed_official 630:825f75ca301e 1603 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
mbed_official 630:825f75ca301e 1604 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
mbed_official 630:825f75ca301e 1605
mbed_official 630:825f75ca301e 1606 /******************** Bit definition for RCC_CFGR register *****************/
mbed_official 630:825f75ca301e 1607 /*!< SW configuration */
mbed_official 630:825f75ca301e 1608 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 630:825f75ca301e 1609 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 630:825f75ca301e 1610 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 630:825f75ca301e 1611
mbed_official 630:825f75ca301e 1612 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 630:825f75ca301e 1613 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 630:825f75ca301e 1614 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 630:825f75ca301e 1615
mbed_official 630:825f75ca301e 1616 /*!< SWS configuration */
mbed_official 630:825f75ca301e 1617 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 630:825f75ca301e 1618 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 630:825f75ca301e 1619 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 630:825f75ca301e 1620
mbed_official 630:825f75ca301e 1621 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 630:825f75ca301e 1622 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 630:825f75ca301e 1623 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 630:825f75ca301e 1624
mbed_official 630:825f75ca301e 1625 /*!< HPRE configuration */
mbed_official 630:825f75ca301e 1626 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 630:825f75ca301e 1627 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 630:825f75ca301e 1628 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 630:825f75ca301e 1629 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 630:825f75ca301e 1630 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 630:825f75ca301e 1631
mbed_official 630:825f75ca301e 1632 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 630:825f75ca301e 1633 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 630:825f75ca301e 1634 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 630:825f75ca301e 1635 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 630:825f75ca301e 1636 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 630:825f75ca301e 1637 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 630:825f75ca301e 1638 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 630:825f75ca301e 1639 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 630:825f75ca301e 1640 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 630:825f75ca301e 1641
mbed_official 630:825f75ca301e 1642 /*!< PPRE configuration */
mbed_official 630:825f75ca301e 1643 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
mbed_official 630:825f75ca301e 1644 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 630:825f75ca301e 1645 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 630:825f75ca301e 1646 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 630:825f75ca301e 1647
mbed_official 630:825f75ca301e 1648 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 630:825f75ca301e 1649 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
mbed_official 630:825f75ca301e 1650 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
mbed_official 630:825f75ca301e 1651 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
mbed_official 630:825f75ca301e 1652 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
mbed_official 630:825f75ca301e 1653
mbed_official 630:825f75ca301e 1654 /*!< ADCPPRE configuration */
mbed_official 630:825f75ca301e 1655 #define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
mbed_official 630:825f75ca301e 1656
mbed_official 630:825f75ca301e 1657 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
mbed_official 630:825f75ca301e 1658 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
mbed_official 630:825f75ca301e 1659
mbed_official 630:825f75ca301e 1660 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
mbed_official 630:825f75ca301e 1661 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
mbed_official 630:825f75ca301e 1662 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
mbed_official 630:825f75ca301e 1663
mbed_official 630:825f75ca301e 1664 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
mbed_official 630:825f75ca301e 1665 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
mbed_official 630:825f75ca301e 1666 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
mbed_official 630:825f75ca301e 1667
mbed_official 630:825f75ca301e 1668 /*!< PLLMUL configuration */
mbed_official 630:825f75ca301e 1669 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
mbed_official 630:825f75ca301e 1670 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 630:825f75ca301e 1671 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 630:825f75ca301e 1672 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 630:825f75ca301e 1673 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
mbed_official 630:825f75ca301e 1674
mbed_official 630:825f75ca301e 1675 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
mbed_official 630:825f75ca301e 1676 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
mbed_official 630:825f75ca301e 1677 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
mbed_official 630:825f75ca301e 1678 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
mbed_official 630:825f75ca301e 1679 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
mbed_official 630:825f75ca301e 1680 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
mbed_official 630:825f75ca301e 1681 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
mbed_official 630:825f75ca301e 1682 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
mbed_official 630:825f75ca301e 1683 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
mbed_official 630:825f75ca301e 1684 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
mbed_official 630:825f75ca301e 1685 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
mbed_official 630:825f75ca301e 1686 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
mbed_official 630:825f75ca301e 1687 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
mbed_official 630:825f75ca301e 1688 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
mbed_official 630:825f75ca301e 1689 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
mbed_official 630:825f75ca301e 1690
mbed_official 630:825f75ca301e 1691 /*!< MCO configuration */
mbed_official 630:825f75ca301e 1692 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
mbed_official 630:825f75ca301e 1693 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 630:825f75ca301e 1694 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 630:825f75ca301e 1695 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 630:825f75ca301e 1696 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 630:825f75ca301e 1697
mbed_official 630:825f75ca301e 1698 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 630:825f75ca301e 1699 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
mbed_official 630:825f75ca301e 1700 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
mbed_official 630:825f75ca301e 1701 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
mbed_official 630:825f75ca301e 1702 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
mbed_official 630:825f75ca301e 1703 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
mbed_official 630:825f75ca301e 1704 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
mbed_official 630:825f75ca301e 1705 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
mbed_official 630:825f75ca301e 1706
mbed_official 630:825f75ca301e 1707 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
mbed_official 630:825f75ca301e 1708 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
mbed_official 630:825f75ca301e 1709 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
mbed_official 630:825f75ca301e 1710 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
mbed_official 630:825f75ca301e 1711 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
mbed_official 630:825f75ca301e 1712 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
mbed_official 630:825f75ca301e 1713 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
mbed_official 630:825f75ca301e 1714 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
mbed_official 630:825f75ca301e 1715 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
mbed_official 630:825f75ca301e 1716
mbed_official 630:825f75ca301e 1717 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
mbed_official 630:825f75ca301e 1718
mbed_official 630:825f75ca301e 1719 /*!<****************** Bit definition for RCC_CIR register *****************/
mbed_official 630:825f75ca301e 1720 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
mbed_official 630:825f75ca301e 1721 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
mbed_official 630:825f75ca301e 1722 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
mbed_official 630:825f75ca301e 1723 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
mbed_official 630:825f75ca301e 1724 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
mbed_official 630:825f75ca301e 1725 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
mbed_official 630:825f75ca301e 1726 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
mbed_official 630:825f75ca301e 1727 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
mbed_official 630:825f75ca301e 1728 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
mbed_official 630:825f75ca301e 1729 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
mbed_official 630:825f75ca301e 1730 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
mbed_official 630:825f75ca301e 1731 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
mbed_official 630:825f75ca301e 1732 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
mbed_official 630:825f75ca301e 1733 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
mbed_official 630:825f75ca301e 1734 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
mbed_official 630:825f75ca301e 1735 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
mbed_official 630:825f75ca301e 1736 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
mbed_official 630:825f75ca301e 1737 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
mbed_official 630:825f75ca301e 1738 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
mbed_official 630:825f75ca301e 1739 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
mbed_official 630:825f75ca301e 1740
mbed_official 630:825f75ca301e 1741 /***************** Bit definition for RCC_APB2RSTR register ****************/
mbed_official 630:825f75ca301e 1742 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
mbed_official 630:825f75ca301e 1743 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
mbed_official 630:825f75ca301e 1744 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
mbed_official 630:825f75ca301e 1745 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
mbed_official 630:825f75ca301e 1746 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
mbed_official 630:825f75ca301e 1747 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
mbed_official 630:825f75ca301e 1748 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
mbed_official 630:825f75ca301e 1749 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
mbed_official 630:825f75ca301e 1750
mbed_official 630:825f75ca301e 1751 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
mbed_official 630:825f75ca301e 1752 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
mbed_official 630:825f75ca301e 1753
mbed_official 630:825f75ca301e 1754 /***************** Bit definition for RCC_APB1RSTR register ****************/
mbed_official 630:825f75ca301e 1755 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
mbed_official 630:825f75ca301e 1756 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
mbed_official 630:825f75ca301e 1757 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
mbed_official 630:825f75ca301e 1758 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
mbed_official 630:825f75ca301e 1759 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
mbed_official 630:825f75ca301e 1760 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
mbed_official 630:825f75ca301e 1761
mbed_official 630:825f75ca301e 1762 /****************** Bit definition for RCC_AHBENR register *****************/
mbed_official 630:825f75ca301e 1763 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
mbed_official 630:825f75ca301e 1764 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
mbed_official 630:825f75ca301e 1765 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
mbed_official 630:825f75ca301e 1766 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
mbed_official 630:825f75ca301e 1767 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
mbed_official 630:825f75ca301e 1768 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
mbed_official 630:825f75ca301e 1769 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
mbed_official 630:825f75ca301e 1770 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
mbed_official 630:825f75ca301e 1771 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
mbed_official 630:825f75ca301e 1772
mbed_official 630:825f75ca301e 1773 /* Old Bit definition maintained for legacy purpose */
mbed_official 630:825f75ca301e 1774 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
mbed_official 630:825f75ca301e 1775 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
mbed_official 630:825f75ca301e 1776
mbed_official 630:825f75ca301e 1777 /***************** Bit definition for RCC_APB2ENR register *****************/
mbed_official 630:825f75ca301e 1778 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
mbed_official 630:825f75ca301e 1779 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
mbed_official 630:825f75ca301e 1780 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
mbed_official 630:825f75ca301e 1781 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
mbed_official 630:825f75ca301e 1782 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
mbed_official 630:825f75ca301e 1783 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
mbed_official 630:825f75ca301e 1784 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
mbed_official 630:825f75ca301e 1785 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
mbed_official 630:825f75ca301e 1786
mbed_official 630:825f75ca301e 1787 /* Old Bit definition maintained for legacy purpose */
mbed_official 630:825f75ca301e 1788 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
mbed_official 630:825f75ca301e 1789 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
mbed_official 630:825f75ca301e 1790
mbed_official 630:825f75ca301e 1791 /***************** Bit definition for RCC_APB1ENR register *****************/
mbed_official 630:825f75ca301e 1792 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
mbed_official 630:825f75ca301e 1793 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
mbed_official 630:825f75ca301e 1794 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
mbed_official 630:825f75ca301e 1795 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
mbed_official 630:825f75ca301e 1796 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
mbed_official 630:825f75ca301e 1797 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
mbed_official 630:825f75ca301e 1798
mbed_official 630:825f75ca301e 1799 /******************* Bit definition for RCC_BDCR register ******************/
mbed_official 630:825f75ca301e 1800 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
mbed_official 630:825f75ca301e 1801 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
mbed_official 630:825f75ca301e 1802 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
mbed_official 630:825f75ca301e 1803
mbed_official 630:825f75ca301e 1804 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
mbed_official 630:825f75ca301e 1805 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 630:825f75ca301e 1806 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 630:825f75ca301e 1807
mbed_official 630:825f75ca301e 1808 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
mbed_official 630:825f75ca301e 1809 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 630:825f75ca301e 1810 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 630:825f75ca301e 1811
mbed_official 630:825f75ca301e 1812 /*!< RTC configuration */
mbed_official 630:825f75ca301e 1813 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 630:825f75ca301e 1814 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
mbed_official 630:825f75ca301e 1815 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
mbed_official 630:825f75ca301e 1816 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
mbed_official 630:825f75ca301e 1817
mbed_official 630:825f75ca301e 1818 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
mbed_official 630:825f75ca301e 1819 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
mbed_official 630:825f75ca301e 1820
mbed_official 630:825f75ca301e 1821 /******************* Bit definition for RCC_CSR register *******************/
mbed_official 630:825f75ca301e 1822 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
mbed_official 630:825f75ca301e 1823 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
mbed_official 630:825f75ca301e 1824 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
mbed_official 630:825f75ca301e 1825 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
mbed_official 630:825f75ca301e 1826 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
mbed_official 630:825f75ca301e 1827 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
mbed_official 630:825f75ca301e 1828 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
mbed_official 630:825f75ca301e 1829 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
mbed_official 630:825f75ca301e 1830 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
mbed_official 630:825f75ca301e 1831 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
mbed_official 630:825f75ca301e 1832 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
mbed_official 630:825f75ca301e 1833
mbed_official 630:825f75ca301e 1834 /* Old Bit definition maintained for legacy purpose */
mbed_official 630:825f75ca301e 1835 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
mbed_official 630:825f75ca301e 1836
mbed_official 630:825f75ca301e 1837 /******************* Bit definition for RCC_AHBRSTR register ***************/
mbed_official 630:825f75ca301e 1838 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
mbed_official 630:825f75ca301e 1839 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
mbed_official 630:825f75ca301e 1840 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
mbed_official 630:825f75ca301e 1841 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
mbed_official 630:825f75ca301e 1842 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
mbed_official 630:825f75ca301e 1843
mbed_official 630:825f75ca301e 1844 /******************* Bit definition for RCC_CFGR2 register *****************/
mbed_official 630:825f75ca301e 1845 /*!< PREDIV configuration */
mbed_official 630:825f75ca301e 1846 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
mbed_official 630:825f75ca301e 1847 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 630:825f75ca301e 1848 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 630:825f75ca301e 1849 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 630:825f75ca301e 1850 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 630:825f75ca301e 1851
mbed_official 630:825f75ca301e 1852 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
mbed_official 630:825f75ca301e 1853 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
mbed_official 630:825f75ca301e 1854 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
mbed_official 630:825f75ca301e 1855 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
mbed_official 630:825f75ca301e 1856 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
mbed_official 630:825f75ca301e 1857 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
mbed_official 630:825f75ca301e 1858 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
mbed_official 630:825f75ca301e 1859 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
mbed_official 630:825f75ca301e 1860 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
mbed_official 630:825f75ca301e 1861 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
mbed_official 630:825f75ca301e 1862 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
mbed_official 630:825f75ca301e 1863 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
mbed_official 630:825f75ca301e 1864 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
mbed_official 630:825f75ca301e 1865 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
mbed_official 630:825f75ca301e 1866 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
mbed_official 630:825f75ca301e 1867 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
mbed_official 630:825f75ca301e 1868
mbed_official 630:825f75ca301e 1869 /******************* Bit definition for RCC_CFGR3 register *****************/
mbed_official 630:825f75ca301e 1870 /*!< USART1 Clock source selection */
mbed_official 630:825f75ca301e 1871 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
mbed_official 630:825f75ca301e 1872 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 630:825f75ca301e 1873 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 630:825f75ca301e 1874
mbed_official 630:825f75ca301e 1875 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
mbed_official 630:825f75ca301e 1876 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
mbed_official 630:825f75ca301e 1877 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
mbed_official 630:825f75ca301e 1878 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
mbed_official 630:825f75ca301e 1879
mbed_official 630:825f75ca301e 1880 /*!< I2C1 Clock source selection */
mbed_official 630:825f75ca301e 1881 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
mbed_official 630:825f75ca301e 1882
mbed_official 630:825f75ca301e 1883 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
mbed_official 630:825f75ca301e 1884 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
mbed_official 630:825f75ca301e 1885
mbed_official 630:825f75ca301e 1886 /******************* Bit definition for RCC_CR2 register *******************/
mbed_official 630:825f75ca301e 1887 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
mbed_official 630:825f75ca301e 1888 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
mbed_official 630:825f75ca301e 1889 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
mbed_official 630:825f75ca301e 1890 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
mbed_official 630:825f75ca301e 1891 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
mbed_official 630:825f75ca301e 1892
mbed_official 630:825f75ca301e 1893 /*****************************************************************************/
mbed_official 630:825f75ca301e 1894 /* */
mbed_official 630:825f75ca301e 1895 /* Real-Time Clock (RTC) */
mbed_official 630:825f75ca301e 1896 /* */
mbed_official 630:825f75ca301e 1897 /*****************************************************************************/
mbed_official 630:825f75ca301e 1898 /******************** Bits definition for RTC_TR register ******************/
mbed_official 630:825f75ca301e 1899 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 630:825f75ca301e 1900 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 630:825f75ca301e 1901 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 630:825f75ca301e 1902 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 630:825f75ca301e 1903 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 630:825f75ca301e 1904 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 630:825f75ca301e 1905 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 630:825f75ca301e 1906 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 630:825f75ca301e 1907 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 630:825f75ca301e 1908 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 630:825f75ca301e 1909 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 1910 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 1911 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 1912 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 630:825f75ca301e 1913 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 1914 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 1915 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 1916 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 1917 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 630:825f75ca301e 1918 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 1919 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 1920 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 1921 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 630:825f75ca301e 1922 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 1923 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 1924 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 1925 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 1926
mbed_official 630:825f75ca301e 1927 /******************** Bits definition for RTC_DR register ******************/
mbed_official 630:825f75ca301e 1928 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 630:825f75ca301e 1929 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 630:825f75ca301e 1930 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 630:825f75ca301e 1931 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 630:825f75ca301e 1932 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 630:825f75ca301e 1933 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 630:825f75ca301e 1934 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 630:825f75ca301e 1935 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 630:825f75ca301e 1936 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 630:825f75ca301e 1937 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 630:825f75ca301e 1938 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 630:825f75ca301e 1939 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 1940 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 1941 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 1942 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 1943 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 630:825f75ca301e 1944 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 1945 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 1946 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 1947 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 1948 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 630:825f75ca301e 1949 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 1950 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 1951 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 630:825f75ca301e 1952 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 1953 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 1954 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 1955 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 1956
mbed_official 630:825f75ca301e 1957 /******************** Bits definition for RTC_CR register ******************/
mbed_official 630:825f75ca301e 1958 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 630:825f75ca301e 1959 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 630:825f75ca301e 1960 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 630:825f75ca301e 1961 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 630:825f75ca301e 1962 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 630:825f75ca301e 1963 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 630:825f75ca301e 1964 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 630:825f75ca301e 1965 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 630:825f75ca301e 1966 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 630:825f75ca301e 1967 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 1968 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 1969 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 1970 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 1971 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 1972 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 1973 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 1974 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 1975
mbed_official 630:825f75ca301e 1976 /******************** Bits definition for RTC_ISR register *****************/
mbed_official 630:825f75ca301e 1977 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 630:825f75ca301e 1978 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 1979 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 1980 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 1981 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 1982 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 1983 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 630:825f75ca301e 1984 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 1985 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 1986 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 1987 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 1988 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 1989
mbed_official 630:825f75ca301e 1990 /******************** Bits definition for RTC_PRER register ****************/
mbed_official 630:825f75ca301e 1991 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 630:825f75ca301e 1992 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 630:825f75ca301e 1993
mbed_official 630:825f75ca301e 1994 /******************** Bits definition for RTC_ALRMAR register **************/
mbed_official 630:825f75ca301e 1995 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 630:825f75ca301e 1996 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 630:825f75ca301e 1997 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 630:825f75ca301e 1998 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 630:825f75ca301e 1999 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 630:825f75ca301e 2000 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 630:825f75ca301e 2001 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 630:825f75ca301e 2002 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 630:825f75ca301e 2003 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 630:825f75ca301e 2004 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 630:825f75ca301e 2005 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 630:825f75ca301e 2006 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 630:825f75ca301e 2007 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 630:825f75ca301e 2008 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 630:825f75ca301e 2009 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 630:825f75ca301e 2010 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 630:825f75ca301e 2011 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 630:825f75ca301e 2012 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 630:825f75ca301e 2013 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 630:825f75ca301e 2014 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 630:825f75ca301e 2015 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 2016 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 630:825f75ca301e 2017 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 2018 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 2019 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 2020 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 630:825f75ca301e 2021 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 2022 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 2023 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 2024 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 2025 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 630:825f75ca301e 2026 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 630:825f75ca301e 2027 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 2028 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 2029 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 2030 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 630:825f75ca301e 2031 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 2032 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 2033 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 2034 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 2035
mbed_official 630:825f75ca301e 2036 /******************** Bits definition for RTC_WPR register *****************/
mbed_official 630:825f75ca301e 2037 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 630:825f75ca301e 2038
mbed_official 630:825f75ca301e 2039 /******************** Bits definition for RTC_SSR register *****************/
mbed_official 630:825f75ca301e 2040 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 630:825f75ca301e 2041
mbed_official 630:825f75ca301e 2042 /******************** Bits definition for RTC_SHIFTR register **************/
mbed_official 630:825f75ca301e 2043 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 630:825f75ca301e 2044 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 630:825f75ca301e 2045
mbed_official 630:825f75ca301e 2046 /******************** Bits definition for RTC_TSTR register ****************/
mbed_official 630:825f75ca301e 2047 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 630:825f75ca301e 2048 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 630:825f75ca301e 2049 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 630:825f75ca301e 2050 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 630:825f75ca301e 2051 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 630:825f75ca301e 2052 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 630:825f75ca301e 2053 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 630:825f75ca301e 2054 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 630:825f75ca301e 2055 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 630:825f75ca301e 2056 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 630:825f75ca301e 2057 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 2058 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 2059 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 2060 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 630:825f75ca301e 2061 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 2062 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 2063 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 2064 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 2065 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 630:825f75ca301e 2066 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 2067 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 2068 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 2069 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 630:825f75ca301e 2070 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 2071 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 2072 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 2073 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 2074
mbed_official 630:825f75ca301e 2075 /******************** Bits definition for RTC_TSDR register ****************/
mbed_official 630:825f75ca301e 2076 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 630:825f75ca301e 2077 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 2078 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 2079 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 2080 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 2081 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 630:825f75ca301e 2082 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 2083 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 2084 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 2085 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 2086 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 630:825f75ca301e 2087 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 2088 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 2089 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 630:825f75ca301e 2090 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 2091 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 2092 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 2093 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 2094
mbed_official 630:825f75ca301e 2095 /******************** Bits definition for RTC_TSSSR register ***************/
mbed_official 630:825f75ca301e 2096 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 630:825f75ca301e 2097
mbed_official 630:825f75ca301e 2098 /******************** Bits definition for RTC_CALR register ****************/
mbed_official 630:825f75ca301e 2099 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 2100 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 2101 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 2102 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 630:825f75ca301e 2103 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 2104 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 2105 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 2106 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 2107 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 2108 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 630:825f75ca301e 2109 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 630:825f75ca301e 2110 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 630:825f75ca301e 2111 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 2112
mbed_official 630:825f75ca301e 2113 /******************** Bits definition for RTC_TAFCR register ***************/
mbed_official 630:825f75ca301e 2114 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 630:825f75ca301e 2115 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 630:825f75ca301e 2116 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 630:825f75ca301e 2117 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 630:825f75ca301e 2118 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 630:825f75ca301e 2119 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 630:825f75ca301e 2120 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 630:825f75ca301e 2121 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 630:825f75ca301e 2122 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 630:825f75ca301e 2123 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 630:825f75ca301e 2124 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 630:825f75ca301e 2125 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 630:825f75ca301e 2126 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 630:825f75ca301e 2127 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 630:825f75ca301e 2128 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 630:825f75ca301e 2129 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 630:825f75ca301e 2130 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 630:825f75ca301e 2131 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 630:825f75ca301e 2132
mbed_official 630:825f75ca301e 2133 /******************** Bits definition for RTC_ALRMASSR register ************/
mbed_official 630:825f75ca301e 2134 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 630:825f75ca301e 2135 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 630:825f75ca301e 2136 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 630:825f75ca301e 2137 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 630:825f75ca301e 2138 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 630:825f75ca301e 2139 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 630:825f75ca301e 2140
mbed_official 630:825f75ca301e 2141 /******************** Bits definition for RTC_BKP0R register ***************/
mbed_official 630:825f75ca301e 2142 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 630:825f75ca301e 2143
mbed_official 630:825f75ca301e 2144 /******************** Bits definition for RTC_BKP1R register ***************/
mbed_official 630:825f75ca301e 2145 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 630:825f75ca301e 2146
mbed_official 630:825f75ca301e 2147 /******************** Bits definition for RTC_BKP2R register ***************/
mbed_official 630:825f75ca301e 2148 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 630:825f75ca301e 2149
mbed_official 630:825f75ca301e 2150 /******************** Bits definition for RTC_BKP3R register ***************/
mbed_official 630:825f75ca301e 2151 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 630:825f75ca301e 2152
mbed_official 630:825f75ca301e 2153 /******************** Bits definition for RTC_BKP4R register ***************/
mbed_official 630:825f75ca301e 2154 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 630:825f75ca301e 2155
mbed_official 630:825f75ca301e 2156 /******************** Number of backup registers ******************************/
mbed_official 630:825f75ca301e 2157 #define RTC_BKP_NUMBER ((uint32_t)0x00000005)
mbed_official 630:825f75ca301e 2158
mbed_official 630:825f75ca301e 2159 /*****************************************************************************/
mbed_official 630:825f75ca301e 2160 /* */
mbed_official 630:825f75ca301e 2161 /* Serial Peripheral Interface (SPI) */
mbed_official 630:825f75ca301e 2162 /* */
mbed_official 630:825f75ca301e 2163 /*****************************************************************************/
mbed_official 630:825f75ca301e 2164 /******************* Bit definition for SPI_CR1 register *******************/
mbed_official 630:825f75ca301e 2165 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
mbed_official 630:825f75ca301e 2166 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
mbed_official 630:825f75ca301e 2167 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
mbed_official 630:825f75ca301e 2168 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
mbed_official 630:825f75ca301e 2169 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 630:825f75ca301e 2170 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 630:825f75ca301e 2171 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 630:825f75ca301e 2172 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
mbed_official 630:825f75ca301e 2173 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
mbed_official 630:825f75ca301e 2174 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
mbed_official 630:825f75ca301e 2175 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
mbed_official 630:825f75ca301e 2176 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
mbed_official 630:825f75ca301e 2177 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
mbed_official 630:825f75ca301e 2178 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
mbed_official 630:825f75ca301e 2179 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
mbed_official 630:825f75ca301e 2180 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
mbed_official 630:825f75ca301e 2181 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
mbed_official 630:825f75ca301e 2182
mbed_official 630:825f75ca301e 2183 /******************* Bit definition for SPI_CR2 register *******************/
mbed_official 630:825f75ca301e 2184 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
mbed_official 630:825f75ca301e 2185 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
mbed_official 630:825f75ca301e 2186 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
mbed_official 630:825f75ca301e 2187 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
mbed_official 630:825f75ca301e 2188 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
mbed_official 630:825f75ca301e 2189 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
mbed_official 630:825f75ca301e 2190 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
mbed_official 630:825f75ca301e 2191 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
mbed_official 630:825f75ca301e 2192 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
mbed_official 630:825f75ca301e 2193 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 630:825f75ca301e 2194 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 630:825f75ca301e 2195 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 630:825f75ca301e 2196 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 630:825f75ca301e 2197 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
mbed_official 630:825f75ca301e 2198 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
mbed_official 630:825f75ca301e 2199 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
mbed_official 630:825f75ca301e 2200
mbed_official 630:825f75ca301e 2201 /******************** Bit definition for SPI_SR register *******************/
mbed_official 630:825f75ca301e 2202 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
mbed_official 630:825f75ca301e 2203 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
mbed_official 630:825f75ca301e 2204 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
mbed_official 630:825f75ca301e 2205 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
mbed_official 630:825f75ca301e 2206 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
mbed_official 630:825f75ca301e 2207 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
mbed_official 630:825f75ca301e 2208 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
mbed_official 630:825f75ca301e 2209 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
mbed_official 630:825f75ca301e 2210 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
mbed_official 630:825f75ca301e 2211 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
mbed_official 630:825f75ca301e 2212 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 630:825f75ca301e 2213 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 630:825f75ca301e 2214 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
mbed_official 630:825f75ca301e 2215 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 630:825f75ca301e 2216 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 630:825f75ca301e 2217
mbed_official 630:825f75ca301e 2218 /******************** Bit definition for SPI_DR register *******************/
mbed_official 630:825f75ca301e 2219 #define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
mbed_official 630:825f75ca301e 2220
mbed_official 630:825f75ca301e 2221 /******************* Bit definition for SPI_CRCPR register *****************/
mbed_official 630:825f75ca301e 2222 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
mbed_official 630:825f75ca301e 2223
mbed_official 630:825f75ca301e 2224 /****************** Bit definition for SPI_RXCRCR register *****************/
mbed_official 630:825f75ca301e 2225 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
mbed_official 630:825f75ca301e 2226
mbed_official 630:825f75ca301e 2227 /****************** Bit definition for SPI_TXCRCR register *****************/
mbed_official 630:825f75ca301e 2228 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
mbed_official 630:825f75ca301e 2229
mbed_official 630:825f75ca301e 2230 /****************** Bit definition for SPI_I2SCFGR register ****************/
mbed_official 630:825f75ca301e 2231 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
mbed_official 630:825f75ca301e 2232 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 630:825f75ca301e 2233 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2234 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2235 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
mbed_official 630:825f75ca301e 2236 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 630:825f75ca301e 2237 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2238 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2239 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
mbed_official 630:825f75ca301e 2240 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 630:825f75ca301e 2241 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2242 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2243 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
mbed_official 630:825f75ca301e 2244 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
mbed_official 630:825f75ca301e 2245
mbed_official 630:825f75ca301e 2246 /****************** Bit definition for SPI_I2SPR register ******************/
mbed_official 630:825f75ca301e 2247 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
mbed_official 630:825f75ca301e 2248 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
mbed_official 630:825f75ca301e 2249 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
mbed_official 630:825f75ca301e 2250
mbed_official 630:825f75ca301e 2251 /*****************************************************************************/
mbed_official 630:825f75ca301e 2252 /* */
mbed_official 630:825f75ca301e 2253 /* System Configuration (SYSCFG) */
mbed_official 630:825f75ca301e 2254 /* */
mbed_official 630:825f75ca301e 2255 /*****************************************************************************/
mbed_official 630:825f75ca301e 2256 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
mbed_official 630:825f75ca301e 2257 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
mbed_official 630:825f75ca301e 2258 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
mbed_official 630:825f75ca301e 2259 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
mbed_official 630:825f75ca301e 2260
mbed_official 630:825f75ca301e 2261
mbed_official 630:825f75ca301e 2262 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
mbed_official 630:825f75ca301e 2263 #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
mbed_official 630:825f75ca301e 2264 #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
mbed_official 630:825f75ca301e 2265 #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
mbed_official 630:825f75ca301e 2266 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
mbed_official 630:825f75ca301e 2267 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
mbed_official 630:825f75ca301e 2268
mbed_official 630:825f75ca301e 2269 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
mbed_official 630:825f75ca301e 2270 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
mbed_official 630:825f75ca301e 2271 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
mbed_official 630:825f75ca301e 2272 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
mbed_official 630:825f75ca301e 2273 #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
mbed_official 630:825f75ca301e 2274 #define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 */
mbed_official 630:825f75ca301e 2275 #define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10 */
mbed_official 630:825f75ca301e 2276
mbed_official 630:825f75ca301e 2277
mbed_official 630:825f75ca301e 2278 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
mbed_official 630:825f75ca301e 2279 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
mbed_official 630:825f75ca301e 2280 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
mbed_official 630:825f75ca301e 2281 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
mbed_official 630:825f75ca301e 2282 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
mbed_official 630:825f75ca301e 2283
mbed_official 630:825f75ca301e 2284 /**
mbed_official 630:825f75ca301e 2285 * @brief EXTI0 configuration
mbed_official 630:825f75ca301e 2286 */
mbed_official 630:825f75ca301e 2287 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
mbed_official 630:825f75ca301e 2288 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
mbed_official 630:825f75ca301e 2289 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
mbed_official 630:825f75ca301e 2290 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
mbed_official 630:825f75ca301e 2291 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
mbed_official 630:825f75ca301e 2292
mbed_official 630:825f75ca301e 2293 /**
mbed_official 630:825f75ca301e 2294 * @brief EXTI1 configuration
mbed_official 630:825f75ca301e 2295 */
mbed_official 630:825f75ca301e 2296 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
mbed_official 630:825f75ca301e 2297 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
mbed_official 630:825f75ca301e 2298 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
mbed_official 630:825f75ca301e 2299 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
mbed_official 630:825f75ca301e 2300 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
mbed_official 630:825f75ca301e 2301
mbed_official 630:825f75ca301e 2302 /**
mbed_official 630:825f75ca301e 2303 * @brief EXTI2 configuration
mbed_official 630:825f75ca301e 2304 */
mbed_official 630:825f75ca301e 2305 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
mbed_official 630:825f75ca301e 2306 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
mbed_official 630:825f75ca301e 2307 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
mbed_official 630:825f75ca301e 2308 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
mbed_official 630:825f75ca301e 2309 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
mbed_official 630:825f75ca301e 2310
mbed_official 630:825f75ca301e 2311 /**
mbed_official 630:825f75ca301e 2312 * @brief EXTI3 configuration
mbed_official 630:825f75ca301e 2313 */
mbed_official 630:825f75ca301e 2314 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
mbed_official 630:825f75ca301e 2315 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
mbed_official 630:825f75ca301e 2316 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
mbed_official 630:825f75ca301e 2317 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
mbed_official 630:825f75ca301e 2318 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
mbed_official 630:825f75ca301e 2319
mbed_official 630:825f75ca301e 2320 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
mbed_official 630:825f75ca301e 2321 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
mbed_official 630:825f75ca301e 2322 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
mbed_official 630:825f75ca301e 2323 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
mbed_official 630:825f75ca301e 2324 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
mbed_official 630:825f75ca301e 2325
mbed_official 630:825f75ca301e 2326 /**
mbed_official 630:825f75ca301e 2327 * @brief EXTI4 configuration
mbed_official 630:825f75ca301e 2328 */
mbed_official 630:825f75ca301e 2329 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
mbed_official 630:825f75ca301e 2330 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
mbed_official 630:825f75ca301e 2331 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
mbed_official 630:825f75ca301e 2332 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
mbed_official 630:825f75ca301e 2333 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
mbed_official 630:825f75ca301e 2334
mbed_official 630:825f75ca301e 2335 /**
mbed_official 630:825f75ca301e 2336 * @brief EXTI5 configuration
mbed_official 630:825f75ca301e 2337 */
mbed_official 630:825f75ca301e 2338 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
mbed_official 630:825f75ca301e 2339 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
mbed_official 630:825f75ca301e 2340 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
mbed_official 630:825f75ca301e 2341 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
mbed_official 630:825f75ca301e 2342 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
mbed_official 630:825f75ca301e 2343
mbed_official 630:825f75ca301e 2344 /**
mbed_official 630:825f75ca301e 2345 * @brief EXTI6 configuration
mbed_official 630:825f75ca301e 2346 */
mbed_official 630:825f75ca301e 2347 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
mbed_official 630:825f75ca301e 2348 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
mbed_official 630:825f75ca301e 2349 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
mbed_official 630:825f75ca301e 2350 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
mbed_official 630:825f75ca301e 2351 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
mbed_official 630:825f75ca301e 2352
mbed_official 630:825f75ca301e 2353 /**
mbed_official 630:825f75ca301e 2354 * @brief EXTI7 configuration
mbed_official 630:825f75ca301e 2355 */
mbed_official 630:825f75ca301e 2356 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
mbed_official 630:825f75ca301e 2357 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
mbed_official 630:825f75ca301e 2358 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
mbed_official 630:825f75ca301e 2359 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
mbed_official 630:825f75ca301e 2360 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
mbed_official 630:825f75ca301e 2361
mbed_official 630:825f75ca301e 2362 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
mbed_official 630:825f75ca301e 2363 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
mbed_official 630:825f75ca301e 2364 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
mbed_official 630:825f75ca301e 2365 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
mbed_official 630:825f75ca301e 2366 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
mbed_official 630:825f75ca301e 2367
mbed_official 630:825f75ca301e 2368 /**
mbed_official 630:825f75ca301e 2369 * @brief EXTI8 configuration
mbed_official 630:825f75ca301e 2370 */
mbed_official 630:825f75ca301e 2371 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
mbed_official 630:825f75ca301e 2372 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
mbed_official 630:825f75ca301e 2373 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
mbed_official 630:825f75ca301e 2374 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
mbed_official 630:825f75ca301e 2375 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
mbed_official 630:825f75ca301e 2376
mbed_official 630:825f75ca301e 2377 /**
mbed_official 630:825f75ca301e 2378 * @brief EXTI9 configuration
mbed_official 630:825f75ca301e 2379 */
mbed_official 630:825f75ca301e 2380 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
mbed_official 630:825f75ca301e 2381 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
mbed_official 630:825f75ca301e 2382 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
mbed_official 630:825f75ca301e 2383 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
mbed_official 630:825f75ca301e 2384 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
mbed_official 630:825f75ca301e 2385
mbed_official 630:825f75ca301e 2386 /**
mbed_official 630:825f75ca301e 2387 * @brief EXTI10 configuration
mbed_official 630:825f75ca301e 2388 */
mbed_official 630:825f75ca301e 2389 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
mbed_official 630:825f75ca301e 2390 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
mbed_official 630:825f75ca301e 2391 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
mbed_official 630:825f75ca301e 2392 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
mbed_official 630:825f75ca301e 2393 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
mbed_official 630:825f75ca301e 2394
mbed_official 630:825f75ca301e 2395 /**
mbed_official 630:825f75ca301e 2396 * @brief EXTI11 configuration
mbed_official 630:825f75ca301e 2397 */
mbed_official 630:825f75ca301e 2398 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
mbed_official 630:825f75ca301e 2399 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
mbed_official 630:825f75ca301e 2400 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
mbed_official 630:825f75ca301e 2401 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
mbed_official 630:825f75ca301e 2402 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
mbed_official 630:825f75ca301e 2403
mbed_official 630:825f75ca301e 2404 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
mbed_official 630:825f75ca301e 2405 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
mbed_official 630:825f75ca301e 2406 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
mbed_official 630:825f75ca301e 2407 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
mbed_official 630:825f75ca301e 2408 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
mbed_official 630:825f75ca301e 2409
mbed_official 630:825f75ca301e 2410 /**
mbed_official 630:825f75ca301e 2411 * @brief EXTI12 configuration
mbed_official 630:825f75ca301e 2412 */
mbed_official 630:825f75ca301e 2413 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
mbed_official 630:825f75ca301e 2414 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
mbed_official 630:825f75ca301e 2415 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
mbed_official 630:825f75ca301e 2416 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
mbed_official 630:825f75ca301e 2417 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
mbed_official 630:825f75ca301e 2418
mbed_official 630:825f75ca301e 2419 /**
mbed_official 630:825f75ca301e 2420 * @brief EXTI13 configuration
mbed_official 630:825f75ca301e 2421 */
mbed_official 630:825f75ca301e 2422 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
mbed_official 630:825f75ca301e 2423 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
mbed_official 630:825f75ca301e 2424 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
mbed_official 630:825f75ca301e 2425 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
mbed_official 630:825f75ca301e 2426 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
mbed_official 630:825f75ca301e 2427
mbed_official 630:825f75ca301e 2428 /**
mbed_official 630:825f75ca301e 2429 * @brief EXTI14 configuration
mbed_official 630:825f75ca301e 2430 */
mbed_official 630:825f75ca301e 2431 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
mbed_official 630:825f75ca301e 2432 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
mbed_official 630:825f75ca301e 2433 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
mbed_official 630:825f75ca301e 2434 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
mbed_official 630:825f75ca301e 2435 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
mbed_official 630:825f75ca301e 2436
mbed_official 630:825f75ca301e 2437 /**
mbed_official 630:825f75ca301e 2438 * @brief EXTI15 configuration
mbed_official 630:825f75ca301e 2439 */
mbed_official 630:825f75ca301e 2440 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
mbed_official 630:825f75ca301e 2441 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
mbed_official 630:825f75ca301e 2442 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
mbed_official 630:825f75ca301e 2443 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
mbed_official 630:825f75ca301e 2444 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
mbed_official 630:825f75ca301e 2445
mbed_official 630:825f75ca301e 2446 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
mbed_official 630:825f75ca301e 2447 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
mbed_official 630:825f75ca301e 2448 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
mbed_official 630:825f75ca301e 2449 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
mbed_official 630:825f75ca301e 2450 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
mbed_official 630:825f75ca301e 2451 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
mbed_official 630:825f75ca301e 2452
mbed_official 630:825f75ca301e 2453 /*****************************************************************************/
mbed_official 630:825f75ca301e 2454 /* */
mbed_official 630:825f75ca301e 2455 /* Timers (TIM) */
mbed_official 630:825f75ca301e 2456 /* */
mbed_official 630:825f75ca301e 2457 /*****************************************************************************/
mbed_official 630:825f75ca301e 2458 /******************* Bit definition for TIM_CR1 register *******************/
mbed_official 630:825f75ca301e 2459 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
mbed_official 630:825f75ca301e 2460 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
mbed_official 630:825f75ca301e 2461 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
mbed_official 630:825f75ca301e 2462 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
mbed_official 630:825f75ca301e 2463 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
mbed_official 630:825f75ca301e 2464
mbed_official 630:825f75ca301e 2465 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 630:825f75ca301e 2466 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2467 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2468
mbed_official 630:825f75ca301e 2469 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
mbed_official 630:825f75ca301e 2470
mbed_official 630:825f75ca301e 2471 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
mbed_official 630:825f75ca301e 2472 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2473 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2474
mbed_official 630:825f75ca301e 2475 /******************* Bit definition for TIM_CR2 register *******************/
mbed_official 630:825f75ca301e 2476 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
mbed_official 630:825f75ca301e 2477 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
mbed_official 630:825f75ca301e 2478 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
mbed_official 630:825f75ca301e 2479
mbed_official 630:825f75ca301e 2480 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 630:825f75ca301e 2481 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2482 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2483 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2484
mbed_official 630:825f75ca301e 2485 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
mbed_official 630:825f75ca301e 2486 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 630:825f75ca301e 2487 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 630:825f75ca301e 2488 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 630:825f75ca301e 2489 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 630:825f75ca301e 2490 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 630:825f75ca301e 2491 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 630:825f75ca301e 2492 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 630:825f75ca301e 2493
mbed_official 630:825f75ca301e 2494 /******************* Bit definition for TIM_SMCR register ******************/
mbed_official 630:825f75ca301e 2495 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 630:825f75ca301e 2496 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2497 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2498 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2499
mbed_official 630:825f75ca301e 2500 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
mbed_official 630:825f75ca301e 2501
mbed_official 630:825f75ca301e 2502 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 630:825f75ca301e 2503 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2504 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2505 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2506
mbed_official 630:825f75ca301e 2507 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
mbed_official 630:825f75ca301e 2508
mbed_official 630:825f75ca301e 2509 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 630:825f75ca301e 2510 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2511 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2512 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2513 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 630:825f75ca301e 2514
mbed_official 630:825f75ca301e 2515 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 630:825f75ca301e 2516 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2517 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2518
mbed_official 630:825f75ca301e 2519 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
mbed_official 630:825f75ca301e 2520 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
mbed_official 630:825f75ca301e 2521
mbed_official 630:825f75ca301e 2522 /******************* Bit definition for TIM_DIER register ******************/
mbed_official 630:825f75ca301e 2523 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
mbed_official 630:825f75ca301e 2524 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 630:825f75ca301e 2525 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 630:825f75ca301e 2526 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 630:825f75ca301e 2527 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 630:825f75ca301e 2528 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
mbed_official 630:825f75ca301e 2529 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
mbed_official 630:825f75ca301e 2530 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
mbed_official 630:825f75ca301e 2531 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
mbed_official 630:825f75ca301e 2532 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 630:825f75ca301e 2533 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 630:825f75ca301e 2534 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 630:825f75ca301e 2535 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 630:825f75ca301e 2536 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
mbed_official 630:825f75ca301e 2537 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
mbed_official 630:825f75ca301e 2538
mbed_official 630:825f75ca301e 2539 /******************** Bit definition for TIM_SR register *******************/
mbed_official 630:825f75ca301e 2540 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
mbed_official 630:825f75ca301e 2541 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 630:825f75ca301e 2542 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 630:825f75ca301e 2543 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 630:825f75ca301e 2544 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 630:825f75ca301e 2545 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
mbed_official 630:825f75ca301e 2546 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
mbed_official 630:825f75ca301e 2547 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
mbed_official 630:825f75ca301e 2548 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 630:825f75ca301e 2549 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 630:825f75ca301e 2550 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 630:825f75ca301e 2551 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 630:825f75ca301e 2552
mbed_official 630:825f75ca301e 2553 /******************* Bit definition for TIM_EGR register *******************/
mbed_official 630:825f75ca301e 2554 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
mbed_official 630:825f75ca301e 2555 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
mbed_official 630:825f75ca301e 2556 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
mbed_official 630:825f75ca301e 2557 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
mbed_official 630:825f75ca301e 2558 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
mbed_official 630:825f75ca301e 2559 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
mbed_official 630:825f75ca301e 2560 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
mbed_official 630:825f75ca301e 2561 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
mbed_official 630:825f75ca301e 2562
mbed_official 630:825f75ca301e 2563 /****************** Bit definition for TIM_CCMR1 register ******************/
mbed_official 630:825f75ca301e 2564 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 630:825f75ca301e 2565 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2566 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2567
mbed_official 630:825f75ca301e 2568 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
mbed_official 630:825f75ca301e 2569 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
mbed_official 630:825f75ca301e 2570
mbed_official 630:825f75ca301e 2571 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 630:825f75ca301e 2572 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2573 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2574 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2575
mbed_official 630:825f75ca301e 2576 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
mbed_official 630:825f75ca301e 2577
mbed_official 630:825f75ca301e 2578 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 630:825f75ca301e 2579 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2580 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2581
mbed_official 630:825f75ca301e 2582 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
mbed_official 630:825f75ca301e 2583 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
mbed_official 630:825f75ca301e 2584
mbed_official 630:825f75ca301e 2585 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 630:825f75ca301e 2586 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2587 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2588 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2589
mbed_official 630:825f75ca301e 2590 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
mbed_official 630:825f75ca301e 2591
mbed_official 630:825f75ca301e 2592 /*---------------------------------------------------------------------------*/
mbed_official 630:825f75ca301e 2593
mbed_official 630:825f75ca301e 2594 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 630:825f75ca301e 2595 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2596 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2597
mbed_official 630:825f75ca301e 2598 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 630:825f75ca301e 2599 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2600 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2601 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2602 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 630:825f75ca301e 2603
mbed_official 630:825f75ca301e 2604 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 630:825f75ca301e 2605 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2606 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2607
mbed_official 630:825f75ca301e 2608 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 630:825f75ca301e 2609 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2610 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2611 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2612 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 630:825f75ca301e 2613
mbed_official 630:825f75ca301e 2614 /****************** Bit definition for TIM_CCMR2 register ******************/
mbed_official 630:825f75ca301e 2615 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 630:825f75ca301e 2616 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2617 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2618
mbed_official 630:825f75ca301e 2619 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
mbed_official 630:825f75ca301e 2620 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
mbed_official 630:825f75ca301e 2621
mbed_official 630:825f75ca301e 2622 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 630:825f75ca301e 2623 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2624 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2625 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2626
mbed_official 630:825f75ca301e 2627 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
mbed_official 630:825f75ca301e 2628
mbed_official 630:825f75ca301e 2629 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 630:825f75ca301e 2630 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2631 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2632
mbed_official 630:825f75ca301e 2633 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
mbed_official 630:825f75ca301e 2634 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
mbed_official 630:825f75ca301e 2635
mbed_official 630:825f75ca301e 2636 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 630:825f75ca301e 2637 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2638 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2639 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2640
mbed_official 630:825f75ca301e 2641 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
mbed_official 630:825f75ca301e 2642
mbed_official 630:825f75ca301e 2643 /*---------------------------------------------------------------------------*/
mbed_official 630:825f75ca301e 2644
mbed_official 630:825f75ca301e 2645 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 630:825f75ca301e 2646 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2647 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2648
mbed_official 630:825f75ca301e 2649 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 630:825f75ca301e 2650 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2651 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2652 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2653 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 630:825f75ca301e 2654
mbed_official 630:825f75ca301e 2655 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 630:825f75ca301e 2656 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2657 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2658
mbed_official 630:825f75ca301e 2659 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 630:825f75ca301e 2660 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2661 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2662 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2663 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 630:825f75ca301e 2664
mbed_official 630:825f75ca301e 2665 /******************* Bit definition for TIM_CCER register ******************/
mbed_official 630:825f75ca301e 2666 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
mbed_official 630:825f75ca301e 2667 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
mbed_official 630:825f75ca301e 2668 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 630:825f75ca301e 2669 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 630:825f75ca301e 2670 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
mbed_official 630:825f75ca301e 2671 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
mbed_official 630:825f75ca301e 2672 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 630:825f75ca301e 2673 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 630:825f75ca301e 2674 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
mbed_official 630:825f75ca301e 2675 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
mbed_official 630:825f75ca301e 2676 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 630:825f75ca301e 2677 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 630:825f75ca301e 2678 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
mbed_official 630:825f75ca301e 2679 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
mbed_official 630:825f75ca301e 2680 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 630:825f75ca301e 2681
mbed_official 630:825f75ca301e 2682 /******************* Bit definition for TIM_CNT register *******************/
mbed_official 630:825f75ca301e 2683 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
mbed_official 630:825f75ca301e 2684
mbed_official 630:825f75ca301e 2685 /******************* Bit definition for TIM_PSC register *******************/
mbed_official 630:825f75ca301e 2686 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
mbed_official 630:825f75ca301e 2687
mbed_official 630:825f75ca301e 2688 /******************* Bit definition for TIM_ARR register *******************/
mbed_official 630:825f75ca301e 2689 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
mbed_official 630:825f75ca301e 2690
mbed_official 630:825f75ca301e 2691 /******************* Bit definition for TIM_RCR register *******************/
mbed_official 630:825f75ca301e 2692 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
mbed_official 630:825f75ca301e 2693
mbed_official 630:825f75ca301e 2694 /******************* Bit definition for TIM_CCR1 register ******************/
mbed_official 630:825f75ca301e 2695 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
mbed_official 630:825f75ca301e 2696
mbed_official 630:825f75ca301e 2697 /******************* Bit definition for TIM_CCR2 register ******************/
mbed_official 630:825f75ca301e 2698 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
mbed_official 630:825f75ca301e 2699
mbed_official 630:825f75ca301e 2700 /******************* Bit definition for TIM_CCR3 register ******************/
mbed_official 630:825f75ca301e 2701 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
mbed_official 630:825f75ca301e 2702
mbed_official 630:825f75ca301e 2703 /******************* Bit definition for TIM_CCR4 register ******************/
mbed_official 630:825f75ca301e 2704 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
mbed_official 630:825f75ca301e 2705
mbed_official 630:825f75ca301e 2706 /******************* Bit definition for TIM_BDTR register ******************/
mbed_official 630:825f75ca301e 2707 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 630:825f75ca301e 2708 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2709 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2710 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2711 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 630:825f75ca301e 2712 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 630:825f75ca301e 2713 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 630:825f75ca301e 2714 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 630:825f75ca301e 2715 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 630:825f75ca301e 2716
mbed_official 630:825f75ca301e 2717 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 630:825f75ca301e 2718 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2719 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2720
mbed_official 630:825f75ca301e 2721 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
mbed_official 630:825f75ca301e 2722 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
mbed_official 630:825f75ca301e 2723 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
mbed_official 630:825f75ca301e 2724 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
mbed_official 630:825f75ca301e 2725 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
mbed_official 630:825f75ca301e 2726 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
mbed_official 630:825f75ca301e 2727
mbed_official 630:825f75ca301e 2728 /******************* Bit definition for TIM_DCR register *******************/
mbed_official 630:825f75ca301e 2729 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 630:825f75ca301e 2730 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2731 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2732 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2733 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 630:825f75ca301e 2734 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 630:825f75ca301e 2735
mbed_official 630:825f75ca301e 2736 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 630:825f75ca301e 2737 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2738 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2739 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2740 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 630:825f75ca301e 2741 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 630:825f75ca301e 2742
mbed_official 630:825f75ca301e 2743 /******************* Bit definition for TIM_DMAR register ******************/
mbed_official 630:825f75ca301e 2744 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
mbed_official 630:825f75ca301e 2745
mbed_official 630:825f75ca301e 2746 /******************* Bit definition for TIM14_OR register ********************/
mbed_official 630:825f75ca301e 2747 #define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
mbed_official 630:825f75ca301e 2748 #define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2749 #define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2750
mbed_official 630:825f75ca301e 2751 /******************************************************************************/
mbed_official 630:825f75ca301e 2752 /* */
mbed_official 630:825f75ca301e 2753 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 630:825f75ca301e 2754 /* */
mbed_official 630:825f75ca301e 2755 /******************************************************************************/
mbed_official 630:825f75ca301e 2756 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 630:825f75ca301e 2757 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
mbed_official 630:825f75ca301e 2758 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
mbed_official 630:825f75ca301e 2759 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
mbed_official 630:825f75ca301e 2760 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
mbed_official 630:825f75ca301e 2761 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
mbed_official 630:825f75ca301e 2762 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
mbed_official 630:825f75ca301e 2763 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
mbed_official 630:825f75ca301e 2764 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
mbed_official 630:825f75ca301e 2765 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
mbed_official 630:825f75ca301e 2766 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
mbed_official 630:825f75ca301e 2767 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
mbed_official 630:825f75ca301e 2768 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
mbed_official 630:825f75ca301e 2769 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
mbed_official 630:825f75ca301e 2770 #define USART_CR1_M ((uint32_t)0x00001000) /*!< SmartCard Length */
mbed_official 630:825f75ca301e 2771 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
mbed_official 630:825f75ca301e 2772 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
mbed_official 630:825f75ca301e 2773 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
mbed_official 630:825f75ca301e 2774 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
mbed_official 630:825f75ca301e 2775 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 630:825f75ca301e 2776 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 630:825f75ca301e 2777 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 630:825f75ca301e 2778 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 630:825f75ca301e 2779 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 630:825f75ca301e 2780 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
mbed_official 630:825f75ca301e 2781 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 630:825f75ca301e 2782 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 630:825f75ca301e 2783 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 630:825f75ca301e 2784 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
mbed_official 630:825f75ca301e 2785 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
mbed_official 630:825f75ca301e 2786 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
mbed_official 630:825f75ca301e 2787 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
mbed_official 630:825f75ca301e 2788
mbed_official 630:825f75ca301e 2789 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 630:825f75ca301e 2790 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
mbed_official 630:825f75ca301e 2791 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
mbed_official 630:825f75ca301e 2792 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
mbed_official 630:825f75ca301e 2793 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
mbed_official 630:825f75ca301e 2794 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
mbed_official 630:825f75ca301e 2795 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
mbed_official 630:825f75ca301e 2796 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
mbed_official 630:825f75ca301e 2797 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
mbed_official 630:825f75ca301e 2798 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 630:825f75ca301e 2799 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 630:825f75ca301e 2800 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
mbed_official 630:825f75ca301e 2801 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
mbed_official 630:825f75ca301e 2802 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
mbed_official 630:825f75ca301e 2803 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
mbed_official 630:825f75ca301e 2804 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
mbed_official 630:825f75ca301e 2805 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
mbed_official 630:825f75ca301e 2806 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
mbed_official 630:825f75ca301e 2807 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
mbed_official 630:825f75ca301e 2808 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 630:825f75ca301e 2809 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 630:825f75ca301e 2810 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
mbed_official 630:825f75ca301e 2811 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
mbed_official 630:825f75ca301e 2812
mbed_official 630:825f75ca301e 2813 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 630:825f75ca301e 2814 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
mbed_official 630:825f75ca301e 2815 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
mbed_official 630:825f75ca301e 2816 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
mbed_official 630:825f75ca301e 2817 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
mbed_official 630:825f75ca301e 2818 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
mbed_official 630:825f75ca301e 2819 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
mbed_official 630:825f75ca301e 2820 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
mbed_official 630:825f75ca301e 2821 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
mbed_official 630:825f75ca301e 2822 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
mbed_official 630:825f75ca301e 2823 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
mbed_official 630:825f75ca301e 2824 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
mbed_official 630:825f75ca301e 2825 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
mbed_official 630:825f75ca301e 2826 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
mbed_official 630:825f75ca301e 2827 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
mbed_official 630:825f75ca301e 2828 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
mbed_official 630:825f75ca301e 2829 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
mbed_official 630:825f75ca301e 2830 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
mbed_official 630:825f75ca301e 2831 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
mbed_official 630:825f75ca301e 2832 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
mbed_official 630:825f75ca301e 2833 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
mbed_official 630:825f75ca301e 2834 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
mbed_official 630:825f75ca301e 2835 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 630:825f75ca301e 2836 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 630:825f75ca301e 2837 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
mbed_official 630:825f75ca301e 2838
mbed_official 630:825f75ca301e 2839 /****************** Bit definition for USART_BRR register *******************/
mbed_official 630:825f75ca301e 2840 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
mbed_official 630:825f75ca301e 2841 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
mbed_official 630:825f75ca301e 2842
mbed_official 630:825f75ca301e 2843 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 630:825f75ca301e 2844 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
mbed_official 630:825f75ca301e 2845 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
mbed_official 630:825f75ca301e 2846
mbed_official 630:825f75ca301e 2847
mbed_official 630:825f75ca301e 2848 /******************* Bit definition for USART_RTOR register *****************/
mbed_official 630:825f75ca301e 2849 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
mbed_official 630:825f75ca301e 2850 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
mbed_official 630:825f75ca301e 2851
mbed_official 630:825f75ca301e 2852 /******************* Bit definition for USART_RQR register ******************/
mbed_official 630:825f75ca301e 2853 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
mbed_official 630:825f75ca301e 2854 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
mbed_official 630:825f75ca301e 2855 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
mbed_official 630:825f75ca301e 2856 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
mbed_official 630:825f75ca301e 2857 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
mbed_official 630:825f75ca301e 2858
mbed_official 630:825f75ca301e 2859 /******************* Bit definition for USART_ISR register ******************/
mbed_official 630:825f75ca301e 2860 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
mbed_official 630:825f75ca301e 2861 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
mbed_official 630:825f75ca301e 2862 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
mbed_official 630:825f75ca301e 2863 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
mbed_official 630:825f75ca301e 2864 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
mbed_official 630:825f75ca301e 2865 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
mbed_official 630:825f75ca301e 2866 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
mbed_official 630:825f75ca301e 2867 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
mbed_official 630:825f75ca301e 2868 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
mbed_official 630:825f75ca301e 2869 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
mbed_official 630:825f75ca301e 2870 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
mbed_official 630:825f75ca301e 2871 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
mbed_official 630:825f75ca301e 2872 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
mbed_official 630:825f75ca301e 2873 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
mbed_official 630:825f75ca301e 2874 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
mbed_official 630:825f75ca301e 2875 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
mbed_official 630:825f75ca301e 2876 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
mbed_official 630:825f75ca301e 2877 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
mbed_official 630:825f75ca301e 2878 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
mbed_official 630:825f75ca301e 2879 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
mbed_official 630:825f75ca301e 2880 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
mbed_official 630:825f75ca301e 2881 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
mbed_official 630:825f75ca301e 2882
mbed_official 630:825f75ca301e 2883 /******************* Bit definition for USART_ICR register ******************/
mbed_official 630:825f75ca301e 2884 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
mbed_official 630:825f75ca301e 2885 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
mbed_official 630:825f75ca301e 2886 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
mbed_official 630:825f75ca301e 2887 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
mbed_official 630:825f75ca301e 2888 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
mbed_official 630:825f75ca301e 2889 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
mbed_official 630:825f75ca301e 2890 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
mbed_official 630:825f75ca301e 2891 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
mbed_official 630:825f75ca301e 2892 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
mbed_official 630:825f75ca301e 2893 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
mbed_official 630:825f75ca301e 2894 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
mbed_official 630:825f75ca301e 2895 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
mbed_official 630:825f75ca301e 2896
mbed_official 630:825f75ca301e 2897 /******************* Bit definition for USART_RDR register ******************/
mbed_official 630:825f75ca301e 2898 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
mbed_official 630:825f75ca301e 2899
mbed_official 630:825f75ca301e 2900 /******************* Bit definition for USART_TDR register ******************/
mbed_official 630:825f75ca301e 2901 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
mbed_official 630:825f75ca301e 2902
mbed_official 630:825f75ca301e 2903 /******************************************************************************/
mbed_official 630:825f75ca301e 2904 /* */
mbed_official 630:825f75ca301e 2905 /* Window WATCHDOG (WWDG) */
mbed_official 630:825f75ca301e 2906 /* */
mbed_official 630:825f75ca301e 2907 /******************************************************************************/
mbed_official 630:825f75ca301e 2908 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 630:825f75ca301e 2909 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 630:825f75ca301e 2910 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2911 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2912 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2913 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
mbed_official 630:825f75ca301e 2914 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
mbed_official 630:825f75ca301e 2915 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
mbed_official 630:825f75ca301e 2916 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
mbed_official 630:825f75ca301e 2917
mbed_official 630:825f75ca301e 2918 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
mbed_official 630:825f75ca301e 2919
mbed_official 630:825f75ca301e 2920 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 630:825f75ca301e 2921 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 630:825f75ca301e 2922 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2923 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2924 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 630:825f75ca301e 2925 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 630:825f75ca301e 2926 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 630:825f75ca301e 2927 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 630:825f75ca301e 2928 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 630:825f75ca301e 2929
mbed_official 630:825f75ca301e 2930 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 630:825f75ca301e 2931 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
mbed_official 630:825f75ca301e 2932 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
mbed_official 630:825f75ca301e 2933
mbed_official 630:825f75ca301e 2934 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
mbed_official 630:825f75ca301e 2935
mbed_official 630:825f75ca301e 2936 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 630:825f75ca301e 2937 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
mbed_official 630:825f75ca301e 2938
mbed_official 630:825f75ca301e 2939 /**
mbed_official 630:825f75ca301e 2940 * @}
mbed_official 630:825f75ca301e 2941 */
mbed_official 630:825f75ca301e 2942
mbed_official 630:825f75ca301e 2943 /**
mbed_official 630:825f75ca301e 2944 * @}
mbed_official 630:825f75ca301e 2945 */
mbed_official 630:825f75ca301e 2946
mbed_official 630:825f75ca301e 2947
mbed_official 630:825f75ca301e 2948 /** @addtogroup Exported_macro
mbed_official 630:825f75ca301e 2949 * @{
mbed_official 630:825f75ca301e 2950 */
mbed_official 630:825f75ca301e 2951
mbed_official 630:825f75ca301e 2952 /****************************** ADC Instances *********************************/
mbed_official 630:825f75ca301e 2953 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official 630:825f75ca301e 2954
mbed_official 630:825f75ca301e 2955 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
mbed_official 630:825f75ca301e 2956
mbed_official 630:825f75ca301e 2957 /****************************** CRC Instances *********************************/
mbed_official 630:825f75ca301e 2958 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 630:825f75ca301e 2959
mbed_official 630:825f75ca301e 2960 /******************************* DMA Instances ******************************/
mbed_official 630:825f75ca301e 2961 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
mbed_official 630:825f75ca301e 2962 ((INSTANCE) == DMA1_Channel2) || \
mbed_official 630:825f75ca301e 2963 ((INSTANCE) == DMA1_Channel3) || \
mbed_official 630:825f75ca301e 2964 ((INSTANCE) == DMA1_Channel4) || \
mbed_official 630:825f75ca301e 2965 ((INSTANCE) == DMA1_Channel5))
mbed_official 630:825f75ca301e 2966
mbed_official 630:825f75ca301e 2967 /****************************** GPIO Instances ********************************/
mbed_official 630:825f75ca301e 2968 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 630:825f75ca301e 2969 ((INSTANCE) == GPIOB) || \
mbed_official 630:825f75ca301e 2970 ((INSTANCE) == GPIOC) || \
mbed_official 630:825f75ca301e 2971 ((INSTANCE) == GPIOF))
mbed_official 630:825f75ca301e 2972
mbed_official 630:825f75ca301e 2973 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 630:825f75ca301e 2974 ((INSTANCE) == GPIOB))
mbed_official 630:825f75ca301e 2975
mbed_official 630:825f75ca301e 2976 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 630:825f75ca301e 2977 ((INSTANCE) == GPIOB))
mbed_official 630:825f75ca301e 2978
mbed_official 630:825f75ca301e 2979 /****************************** I2C Instances *********************************/
mbed_official 630:825f75ca301e 2980 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
mbed_official 630:825f75ca301e 2981
mbed_official 630:825f75ca301e 2982 /****************************** I2S Instances *********************************/
mbed_official 630:825f75ca301e 2983 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
mbed_official 630:825f75ca301e 2984
mbed_official 630:825f75ca301e 2985 /****************************** IWDG Instances ********************************/
mbed_official 630:825f75ca301e 2986 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 630:825f75ca301e 2987
mbed_official 630:825f75ca301e 2988 /****************************** RTC Instances *********************************/
mbed_official 630:825f75ca301e 2989 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 630:825f75ca301e 2990
mbed_official 630:825f75ca301e 2991 /****************************** SMBUS Instances *********************************/
mbed_official 630:825f75ca301e 2992 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
mbed_official 630:825f75ca301e 2993
mbed_official 630:825f75ca301e 2994 /****************************** SPI Instances *********************************/
mbed_official 630:825f75ca301e 2995 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
mbed_official 630:825f75ca301e 2996
mbed_official 630:825f75ca301e 2997 /****************************** TIM Instances *********************************/
mbed_official 630:825f75ca301e 2998 #define IS_TIM_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 2999 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3000 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3001 ((INSTANCE) == TIM3) || \
mbed_official 630:825f75ca301e 3002 ((INSTANCE) == TIM14) || \
mbed_official 630:825f75ca301e 3003 ((INSTANCE) == TIM16) || \
mbed_official 630:825f75ca301e 3004 ((INSTANCE) == TIM17))
mbed_official 630:825f75ca301e 3005
mbed_official 630:825f75ca301e 3006 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3007 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3008 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3009 ((INSTANCE) == TIM3) || \
mbed_official 630:825f75ca301e 3010 ((INSTANCE) == TIM14) || \
mbed_official 630:825f75ca301e 3011 ((INSTANCE) == TIM16) || \
mbed_official 630:825f75ca301e 3012 ((INSTANCE) == TIM17))
mbed_official 630:825f75ca301e 3013
mbed_official 630:825f75ca301e 3014 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3015 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3016 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3017 ((INSTANCE) == TIM3))
mbed_official 630:825f75ca301e 3018
mbed_official 630:825f75ca301e 3019 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3020 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3021 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3022 ((INSTANCE) == TIM3))
mbed_official 630:825f75ca301e 3023
mbed_official 630:825f75ca301e 3024 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3025 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3026 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3027 ((INSTANCE) == TIM3))
mbed_official 630:825f75ca301e 3028
mbed_official 630:825f75ca301e 3029
mbed_official 630:825f75ca301e 3030 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3031 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3032 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3033 ((INSTANCE) == TIM3))
mbed_official 630:825f75ca301e 3034
mbed_official 630:825f75ca301e 3035 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3036 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3037 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3038 ((INSTANCE) == TIM3))
mbed_official 630:825f75ca301e 3039
mbed_official 630:825f75ca301e 3040 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3041 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3042 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3043 ((INSTANCE) == TIM3))
mbed_official 630:825f75ca301e 3044
mbed_official 630:825f75ca301e 3045 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3046 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3047 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3048 ((INSTANCE) == TIM3))
mbed_official 630:825f75ca301e 3049
mbed_official 630:825f75ca301e 3050 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3051 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3052 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3053 ((INSTANCE) == TIM3))
mbed_official 630:825f75ca301e 3054
mbed_official 630:825f75ca301e 3055 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3056 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3057 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3058 ((INSTANCE) == TIM3))
mbed_official 630:825f75ca301e 3059
mbed_official 630:825f75ca301e 3060 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3061 (((INSTANCE) == TIM1))
mbed_official 630:825f75ca301e 3062
mbed_official 630:825f75ca301e 3063 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3064 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3065 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3066 ((INSTANCE) == TIM3))
mbed_official 630:825f75ca301e 3067
mbed_official 630:825f75ca301e 3068 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3069 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3070 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3071 ((INSTANCE) == TIM3))
mbed_official 630:825f75ca301e 3072
mbed_official 630:825f75ca301e 3073 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3074 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3075 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3076 ((INSTANCE) == TIM3))
mbed_official 630:825f75ca301e 3077
mbed_official 630:825f75ca301e 3078 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3079 ((INSTANCE) == TIM2)
mbed_official 630:825f75ca301e 3080
mbed_official 630:825f75ca301e 3081 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3082 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3083 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3084 ((INSTANCE) == TIM3) || \
mbed_official 630:825f75ca301e 3085 ((INSTANCE) == TIM16) || \
mbed_official 630:825f75ca301e 3086 ((INSTANCE) == TIM17))
mbed_official 630:825f75ca301e 3087
mbed_official 630:825f75ca301e 3088 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3089 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3090 ((INSTANCE) == TIM16) || \
mbed_official 630:825f75ca301e 3091 ((INSTANCE) == TIM17))
mbed_official 630:825f75ca301e 3092
mbed_official 630:825f75ca301e 3093 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 630:825f75ca301e 3094 ((((INSTANCE) == TIM1) && \
mbed_official 630:825f75ca301e 3095 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 630:825f75ca301e 3096 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 630:825f75ca301e 3097 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 630:825f75ca301e 3098 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 630:825f75ca301e 3099 || \
mbed_official 630:825f75ca301e 3100 (((INSTANCE) == TIM2) && \
mbed_official 630:825f75ca301e 3101 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 630:825f75ca301e 3102 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 630:825f75ca301e 3103 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 630:825f75ca301e 3104 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 630:825f75ca301e 3105 || \
mbed_official 630:825f75ca301e 3106 (((INSTANCE) == TIM3) && \
mbed_official 630:825f75ca301e 3107 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 630:825f75ca301e 3108 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 630:825f75ca301e 3109 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 630:825f75ca301e 3110 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 630:825f75ca301e 3111 || \
mbed_official 630:825f75ca301e 3112 (((INSTANCE) == TIM14) && \
mbed_official 630:825f75ca301e 3113 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 630:825f75ca301e 3114 || \
mbed_official 630:825f75ca301e 3115 (((INSTANCE) == TIM16) && \
mbed_official 630:825f75ca301e 3116 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 630:825f75ca301e 3117 || \
mbed_official 630:825f75ca301e 3118 (((INSTANCE) == TIM17) && \
mbed_official 630:825f75ca301e 3119 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 630:825f75ca301e 3120
mbed_official 630:825f75ca301e 3121 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 630:825f75ca301e 3122 ((((INSTANCE) == TIM1) && \
mbed_official 630:825f75ca301e 3123 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 630:825f75ca301e 3124 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 630:825f75ca301e 3125 ((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official 630:825f75ca301e 3126 || \
mbed_official 630:825f75ca301e 3127 (((INSTANCE) == TIM16) && \
mbed_official 630:825f75ca301e 3128 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 630:825f75ca301e 3129 || \
mbed_official 630:825f75ca301e 3130 (((INSTANCE) == TIM17) && \
mbed_official 630:825f75ca301e 3131 ((CHANNEL) == TIM_CHANNEL_1)))
mbed_official 630:825f75ca301e 3132
mbed_official 630:825f75ca301e 3133 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3134 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3135 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3136 ((INSTANCE) == TIM3))
mbed_official 630:825f75ca301e 3137
mbed_official 630:825f75ca301e 3138 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3139 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3140 ((INSTANCE) == TIM16) || \
mbed_official 630:825f75ca301e 3141 ((INSTANCE) == TIM17))
mbed_official 630:825f75ca301e 3142
mbed_official 630:825f75ca301e 3143 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3144 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3145 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3146 ((INSTANCE) == TIM3) || \
mbed_official 630:825f75ca301e 3147 ((INSTANCE) == TIM14) || \
mbed_official 630:825f75ca301e 3148 ((INSTANCE) == TIM16) || \
mbed_official 630:825f75ca301e 3149 ((INSTANCE) == TIM17))
mbed_official 630:825f75ca301e 3150
mbed_official 630:825f75ca301e 3151 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3152 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3153 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3154 ((INSTANCE) == TIM3) || \
mbed_official 630:825f75ca301e 3155 ((INSTANCE) == TIM16) || \
mbed_official 630:825f75ca301e 3156 ((INSTANCE) == TIM17))
mbed_official 630:825f75ca301e 3157
mbed_official 630:825f75ca301e 3158 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3159 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3160 ((INSTANCE) == TIM2) || \
mbed_official 630:825f75ca301e 3161 ((INSTANCE) == TIM3) || \
mbed_official 630:825f75ca301e 3162 ((INSTANCE) == TIM16) || \
mbed_official 630:825f75ca301e 3163 ((INSTANCE) == TIM17))
mbed_official 630:825f75ca301e 3164
mbed_official 630:825f75ca301e 3165 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3166 (((INSTANCE) == TIM1) || \
mbed_official 630:825f75ca301e 3167 ((INSTANCE) == TIM16) || \
mbed_official 630:825f75ca301e 3168 ((INSTANCE) == TIM17))
mbed_official 630:825f75ca301e 3169
mbed_official 630:825f75ca301e 3170 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
mbed_official 630:825f75ca301e 3171 ((INSTANCE) == TIM14)
mbed_official 630:825f75ca301e 3172
mbed_official 630:825f75ca301e 3173 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 630:825f75ca301e 3174 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
mbed_official 630:825f75ca301e 3175
mbed_official 630:825f75ca301e 3176 /********************* UART Instances : Smard card mode ***********************/
mbed_official 630:825f75ca301e 3177 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
mbed_official 630:825f75ca301e 3178
mbed_official 630:825f75ca301e 3179 /******************** USART Instances : Synchronous mode **********************/
mbed_official 630:825f75ca301e 3180 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
mbed_official 630:825f75ca301e 3181
mbed_official 630:825f75ca301e 3182 /******************** USART Instances : auto Baud rate detection **************/
mbed_official 630:825f75ca301e 3183 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
mbed_official 630:825f75ca301e 3184
mbed_official 630:825f75ca301e 3185 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 630:825f75ca301e 3186 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
mbed_official 630:825f75ca301e 3187
mbed_official 630:825f75ca301e 3188 /******************** UART Instances : Half-Duplex mode **********************/
mbed_official 630:825f75ca301e 3189 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official 630:825f75ca301e 3190
mbed_official 630:825f75ca301e 3191 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 630:825f75ca301e 3192 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
mbed_official 630:825f75ca301e 3193
mbed_official 630:825f75ca301e 3194 /****************** UART Instances : LIN mode ********************/
mbed_official 630:825f75ca301e 3195 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official 630:825f75ca301e 3196
mbed_official 630:825f75ca301e 3197 /****************** UART Instances : wakeup from stop mode ********************/
mbed_official 630:825f75ca301e 3198 #define IS_UART_WAKEUP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official 630:825f75ca301e 3199
mbed_official 630:825f75ca301e 3200 /****************** UART Instances : Auto Baud Rate detection ********************/
mbed_official 630:825f75ca301e 3201 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
mbed_official 630:825f75ca301e 3202
mbed_official 630:825f75ca301e 3203 /****************** UART Instances : Driver enable detection ********************/
mbed_official 630:825f75ca301e 3204 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
mbed_official 630:825f75ca301e 3205
mbed_official 630:825f75ca301e 3206 /****************************** WWDG Instances ********************************/
mbed_official 630:825f75ca301e 3207 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 630:825f75ca301e 3208
mbed_official 630:825f75ca301e 3209 /**
mbed_official 630:825f75ca301e 3210 * @}
mbed_official 630:825f75ca301e 3211 */
mbed_official 630:825f75ca301e 3212
mbed_official 630:825f75ca301e 3213
mbed_official 630:825f75ca301e 3214 /******************************************************************************/
mbed_official 630:825f75ca301e 3215 /* For a painless codes migration between the STM32F0xx device product */
mbed_official 630:825f75ca301e 3216 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 630:825f75ca301e 3217 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 630:825f75ca301e 3218 /* No need to update developed interrupt code when moving across */
mbed_official 630:825f75ca301e 3219 /* product lines within the same STM32F0 Family */
mbed_official 630:825f75ca301e 3220 /******************************************************************************/
mbed_official 630:825f75ca301e 3221
mbed_official 630:825f75ca301e 3222 /* Aliases for __IRQn */
mbed_official 630:825f75ca301e 3223 #define PVD_VDDIO2_IRQn PVD_IRQn
mbed_official 630:825f75ca301e 3224 #define RCC_CRS_IRQn RCC_IRQn
mbed_official 630:825f75ca301e 3225 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
mbed_official 630:825f75ca301e 3226 #define ADC1_COMP_IRQn ADC1_IRQn
mbed_official 630:825f75ca301e 3227
mbed_official 630:825f75ca301e 3228 /* Aliases for __IRQHandler */
mbed_official 630:825f75ca301e 3229 #define PVD_VDDIO2_IRQHandler PVD_IRQHandler
mbed_official 630:825f75ca301e 3230 #define RCC_CRS_IRQHandler RCC_IRQHandler
mbed_official 630:825f75ca301e 3231 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
mbed_official 630:825f75ca301e 3232 #define ADC1_COMP_IRQHandler ADC1_IRQHandler
mbed_official 630:825f75ca301e 3233
mbed_official 630:825f75ca301e 3234 #ifdef __cplusplus
mbed_official 630:825f75ca301e 3235 }
mbed_official 630:825f75ca301e 3236 #endif /* __cplusplus */
mbed_official 630:825f75ca301e 3237
mbed_official 630:825f75ca301e 3238 #endif /* __STM32F031x6_H */
mbed_official 630:825f75ca301e 3239
mbed_official 630:825f75ca301e 3240 /**
mbed_official 630:825f75ca301e 3241 * @}
mbed_official 630:825f75ca301e 3242 */
mbed_official 630:825f75ca301e 3243
mbed_official 630:825f75ca301e 3244 /**
mbed_official 630:825f75ca301e 3245 * @}
mbed_official 630:825f75ca301e 3246 */
mbed_official 630:825f75ca301e 3247
mbed_official 630:825f75ca301e 3248 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/