mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/W7500x.h@597:47bdd20c4d41, 2015-07-27 (annotated)

Committer:
mbed_official
Date:
Mon Jul 27 09:45:08 2015 +0100
Revision:
597:47bdd20c4d41
Parent:
567:a97fd0eca828 
Synchronized with git revision 9b9bab51e568581a2a896967a707d3b5aeda3f17



Full URL: https://github.com/mbedmicro/mbed/commit/9b9bab51e568581a2a896967a707d3b5aeda3f17/



Change us_ticker - one dual timer + one pwm timer

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 558:0880f51c4036 1 /**************************************************************************//**
mbed_official 558:0880f51c4036 2 * @file W7500x.h
mbed_official 558:0880f51c4036 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
mbed_official 558:0880f51c4036 4 * Device W7500x
mbed_official 558:0880f51c4036 5 * @version V3.01
mbed_official 558:0880f51c4036 6 * @date 06. March 2012
mbed_official 558:0880f51c4036 7 *
mbed_official 558:0880f51c4036 8 * @note
mbed_official 558:0880f51c4036 9 * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
mbed_official 558:0880f51c4036 10 *
mbed_official 558:0880f51c4036 11 * @par
mbed_official 558:0880f51c4036 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
mbed_official 558:0880f51c4036 13 * processor based microcontrollers. This file can be freely distributed
mbed_official 558:0880f51c4036 14 * within development tools that are supporting such ARM based processors.
mbed_official 558:0880f51c4036 15 *
mbed_official 558:0880f51c4036 16 * @par
mbed_official 558:0880f51c4036 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
mbed_official 558:0880f51c4036 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
mbed_official 558:0880f51c4036 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
mbed_official 558:0880f51c4036 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
mbed_official 558:0880f51c4036 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
mbed_official 558:0880f51c4036 22 *
mbed_official 558:0880f51c4036 23 ******************************************************************************/
mbed_official 558:0880f51c4036 24
mbed_official 558:0880f51c4036 25
mbed_official 558:0880f51c4036 26 #ifndef W7500x_H
mbed_official 558:0880f51c4036 27 #define W7500x_H
mbed_official 558:0880f51c4036 28
mbed_official 558:0880f51c4036 29 #ifdef __cplusplus
mbed_official 558:0880f51c4036 30 extern "C" {
mbed_official 558:0880f51c4036 31 #endif
mbed_official 558:0880f51c4036 32
mbed_official 558:0880f51c4036 33 /** @addtogroup W7500x_Definitions W7500x Definitions
mbed_official 558:0880f51c4036 34 This file defines all structures and symbols for W7500x:
mbed_official 558:0880f51c4036 35 - registers and bitfields
mbed_official 558:0880f51c4036 36 - peripheral base address
mbed_official 558:0880f51c4036 37 - peripheral ID
mbed_official 558:0880f51c4036 38 - Peripheral definitions
mbed_official 558:0880f51c4036 39 @{
mbed_official 558:0880f51c4036 40 */
mbed_official 558:0880f51c4036 41
mbed_official 558:0880f51c4036 42
mbed_official 558:0880f51c4036 43 /******************************************************************************/
mbed_official 558:0880f51c4036 44 /* Processor and Core Peripherals */
mbed_official 558:0880f51c4036 45 /******************************************************************************/
mbed_official 558:0880f51c4036 46 /** @addtogroup W7500x_CMSIS Device CMSIS Definitions
mbed_official 558:0880f51c4036 47 Configuration of the Cortex-M0 Processor and Core Peripherals
mbed_official 558:0880f51c4036 48 @{
mbed_official 558:0880f51c4036 49 */
mbed_official 558:0880f51c4036 50
mbed_official 558:0880f51c4036 51 /*
mbed_official 558:0880f51c4036 52 * ==========================================================================
mbed_official 558:0880f51c4036 53 * ---------- Interrupt Number Definition -----------------------------------
mbed_official 558:0880f51c4036 54 * ==========================================================================
mbed_official 558:0880f51c4036 55 */
mbed_official 558:0880f51c4036 56
mbed_official 558:0880f51c4036 57 typedef enum IRQn
mbed_official 558:0880f51c4036 58 {
mbed_official 558:0880f51c4036 59 /****** Cortex-M0 Processor Exceptions Numbers **************************************************/
mbed_official 558:0880f51c4036 60
mbed_official 558:0880f51c4036 61 /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
mbed_official 558:0880f51c4036 62 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
mbed_official 558:0880f51c4036 63 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
mbed_official 558:0880f51c4036 64 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
mbed_official 558:0880f51c4036 65 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
mbed_official 558:0880f51c4036 66 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
mbed_official 558:0880f51c4036 67 /****** W7500x Specific Interrupt Numbers *********************************************************/
mbed_official 558:0880f51c4036 68 SSP0_IRQn = 0, /*!< SSP 0 Interrupt */
mbed_official 558:0880f51c4036 69 SSP1_IRQn = 1, /*!< SSP 1 Interrupt */
mbed_official 558:0880f51c4036 70 UART0_IRQn = 2, /*!< UART 0 Interrupt */
mbed_official 558:0880f51c4036 71 UART1_IRQn = 3, /*!< UART 1 Interrupt */
mbed_official 558:0880f51c4036 72 UART2_IRQn = 4, /*!< UART 2 Interrupt */
mbed_official 558:0880f51c4036 73 I2C0_IRQn = 5, /*!< I2C 0 Interrupt */
mbed_official 558:0880f51c4036 74 I2C1_IRQn = 6, /*!< I2C 1 Interrupt */
mbed_official 558:0880f51c4036 75 PORT0_IRQn = 7, /*!< Port 1 combined Interrupt */
mbed_official 558:0880f51c4036 76 PORT1_IRQn = 8, /*!< Port 2 combined Interrupt */
mbed_official 558:0880f51c4036 77 PORT2_IRQn = 9, /*!< Port 2 combined Interrupt */
mbed_official 558:0880f51c4036 78 PORT3_IRQn = 10, /*!< Port 2 combined Interrupt */
mbed_official 558:0880f51c4036 79 DMA_IRQn = 11, /*!< DMA combined Interrupt */
mbed_official 558:0880f51c4036 80 DUALTIMER0_IRQn = 12, /*!< Dual Timer 0 Interrupt */
mbed_official 558:0880f51c4036 81 DUALTIMER1_IRQn = 13, /*!< Dual Timer 1 Interrupt */
mbed_official 558:0880f51c4036 82 PWM0_IRQn = 14, /*!< PWM 0 Interrupt */
mbed_official 558:0880f51c4036 83 PWM1_IRQn = 15, /*!< PWM 1 Interrupt */
mbed_official 558:0880f51c4036 84 PWM2_IRQn = 16, /*!< PWM 2 Interrupt */
mbed_official 558:0880f51c4036 85 PWM3_IRQn = 17, /*!< PWM 3 Interrupt */
mbed_official 558:0880f51c4036 86 PWM4_IRQn = 18, /*!< PWM 4 Interrupt */
mbed_official 558:0880f51c4036 87 PWM5_IRQn = 19, /*!< PWM 5 Interrupt */
mbed_official 558:0880f51c4036 88 PWM6_IRQn = 20, /*!< PWM 6 Interrupt */
mbed_official 558:0880f51c4036 89 PWM7_IRQn = 21, /*!< PWM 7 Interrupt */
mbed_official 558:0880f51c4036 90 RTC_IRQn = 22, /*!< RTC Interrupt */
mbed_official 558:0880f51c4036 91 ADC_IRQn = 23, /*!< ADC Interrupt */
mbed_official 558:0880f51c4036 92 WZTOE_IRQn = 24, /*!< WZTOE Interrupt */
mbed_official 558:0880f51c4036 93 EXTI_IRQn = 25 /*!< EXTI Interrupt */
mbed_official 558:0880f51c4036 94 } IRQn_Type;
mbed_official 558:0880f51c4036 95
mbed_official 558:0880f51c4036 96 /*
mbed_official 558:0880f51c4036 97 * ==========================================================================
mbed_official 558:0880f51c4036 98 * ----------- Processor and Core Peripheral Section ------------------------
mbed_official 558:0880f51c4036 99 * ==========================================================================
mbed_official 558:0880f51c4036 100 */
mbed_official 558:0880f51c4036 101
mbed_official 558:0880f51c4036 102 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
mbed_official 558:0880f51c4036 103 #define __CM0_REV 0x0000 /*!< Core Revision r0p0 */
mbed_official 558:0880f51c4036 104 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
mbed_official 558:0880f51c4036 105 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 558:0880f51c4036 106 #define __MPU_PRESENT 0 /*!< MPU present or not */
mbed_official 558:0880f51c4036 107
mbed_official 558:0880f51c4036 108 /*@}*/ /* end of group W7500x_CMSIS */
mbed_official 558:0880f51c4036 109
mbed_official 558:0880f51c4036 110
mbed_official 558:0880f51c4036 111 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
mbed_official 558:0880f51c4036 112 #include "system_W7500x.h" /* W7500x System include file */
mbed_official 558:0880f51c4036 113
mbed_official 558:0880f51c4036 114
mbed_official 558:0880f51c4036 115 /** @addtogroup Exported_types
mbed_official 558:0880f51c4036 116 * @{
mbed_official 558:0880f51c4036 117 */
mbed_official 558:0880f51c4036 118
mbed_official 558:0880f51c4036 119 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
mbed_official 558:0880f51c4036 120 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
mbed_official 558:0880f51c4036 121 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
mbed_official 558:0880f51c4036 122
mbed_official 558:0880f51c4036 123 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
mbed_official 558:0880f51c4036 124
mbed_official 558:0880f51c4036 125
mbed_official 558:0880f51c4036 126
mbed_official 558:0880f51c4036 127
mbed_official 558:0880f51c4036 128
mbed_official 558:0880f51c4036 129 /**
mbed_official 558:0880f51c4036 130 * @}
mbed_official 558:0880f51c4036 131 */
mbed_official 558:0880f51c4036 132
mbed_official 558:0880f51c4036 133
mbed_official 558:0880f51c4036 134
mbed_official 558:0880f51c4036 135
mbed_official 558:0880f51c4036 136 /** @addtogroup Peripheral_registers_structures
mbed_official 558:0880f51c4036 137 * @{
mbed_official 558:0880f51c4036 138 */
mbed_official 558:0880f51c4036 139
mbed_official 558:0880f51c4036 140 /**
mbed_official 558:0880f51c4036 141 * @brief Clock Reset Generator
mbed_official 558:0880f51c4036 142 */
mbed_official 558:0880f51c4036 143 typedef struct
mbed_official 558:0880f51c4036 144 {
mbed_official 558:0880f51c4036 145 __IO uint32_t OSC_PDR; /*!< Oscillator power down register, Address offset : 0x00 */
mbed_official 558:0880f51c4036 146 uint32_t RESERVED0[3];
mbed_official 558:0880f51c4036 147 __IO uint32_t PLL_PDR; /*!< PLL power down register, Address offset : 0x10 */
mbed_official 558:0880f51c4036 148 __IO uint32_t PLL_FCR; /*!< PLL frequency calculating register, Address offset : 0x14 */
mbed_official 558:0880f51c4036 149 __IO uint32_t PLL_OER; /*!< PLL output enable register, Address offset : 0x18 */
mbed_official 558:0880f51c4036 150 __IO uint32_t PLL_BPR; /*!< PLL bypass register, Address offset : 0x1c */
mbed_official 558:0880f51c4036 151 __IO uint32_t PLL_IFSR; /*!< PLL input frequency select register, Address offset : 0x20 */
mbed_official 558:0880f51c4036 152 uint32_t RESERVED1[3];
mbed_official 558:0880f51c4036 153 __IO uint32_t FCLK_SSR; /*!< FCLK source select register, Address offset : 0x30 */
mbed_official 558:0880f51c4036 154 __IO uint32_t FCLK_PVSR; /*!< FCLK prescale value select register, Address offset : 0x34 */
mbed_official 558:0880f51c4036 155 uint32_t RESERVED2[2];
mbed_official 558:0880f51c4036 156 __IO uint32_t SSPCLK_SSR; /*!< SSPCLK source select register, Address offset : 0x40 */
mbed_official 558:0880f51c4036 157 __IO uint32_t SSPCLK_PVSR; /*!< SSPCLK prescale value select register, Address offset : 0x44 */
mbed_official 558:0880f51c4036 158 uint32_t RESERVED3[6];
mbed_official 558:0880f51c4036 159 __IO uint32_t ADCCLK_SSR; /*!< ADCCLK source select register, Address offset : 0x60 */
mbed_official 558:0880f51c4036 160 __IO uint32_t ADCCLK_PVSR; /*!< ADCCLK prescale value select register, Address offset : 0x64 */
mbed_official 558:0880f51c4036 161 uint32_t RESERVED4[2];
mbed_official 558:0880f51c4036 162 __IO uint32_t TIMER0CLK_SSR; /*!< TIMER0CLK source select register, Address offset : 0x70 */
mbed_official 558:0880f51c4036 163 __IO uint32_t TIMER0CLK_PVSR; /*!< TIMER0CLK prescale value select register, Address offset : 0x74 */
mbed_official 558:0880f51c4036 164 uint32_t RESERVED5[2];
mbed_official 558:0880f51c4036 165 __IO uint32_t TIMER1CLK_SSR; /*!< TIMER1CLK source select register, Address offset : 0x80 */
mbed_official 558:0880f51c4036 166 __IO uint32_t TIMER1CLK_PVSR; /*!< TIMER1CLK prescale value select register, Address offset : 0x84 */
mbed_official 558:0880f51c4036 167 uint32_t RESERVED6[10];
mbed_official 558:0880f51c4036 168 __IO uint32_t PWM0CLK_SSR; /*!< PWM0CLK source select register, Address offset : 0xb0 */
mbed_official 558:0880f51c4036 169 __IO uint32_t PWM0CLK_PVSR; /*!< PWM0CLK prescale value select register, Address offset : 0xb4 */
mbed_official 558:0880f51c4036 170 uint32_t RESERVED7[2];
mbed_official 558:0880f51c4036 171 __IO uint32_t PWM1CLK_SSR; /*!< PWM1CLK source select register, Address offset : 0xc0 */
mbed_official 558:0880f51c4036 172 __IO uint32_t PWM1CLK_PVSR; /*!< PWM1CLK prescale value select register, Address offset : 0xc4 */
mbed_official 558:0880f51c4036 173 uint32_t RESERVED8[2];
mbed_official 558:0880f51c4036 174 __IO uint32_t PWM2CLK_SSR; /*!< PWM2CLK source select register, Address offset : 0xd0 */
mbed_official 558:0880f51c4036 175 __IO uint32_t PWM2CLK_PVSR; /*!< PWM2CLK prescale value select register, Address offset : 0xd4 */
mbed_official 558:0880f51c4036 176 uint32_t RESERVED9[2];
mbed_official 558:0880f51c4036 177 __IO uint32_t PWM3CLK_SSR; /*!< PWM3CLK source select register, Address offset : 0xe0 */
mbed_official 558:0880f51c4036 178 __IO uint32_t PWM3CLK_PVSR; /*!< PWM3CLK prescale value select register, Address offset : 0xe4 */
mbed_official 558:0880f51c4036 179 uint32_t RESERVED10[2];
mbed_official 558:0880f51c4036 180 __IO uint32_t PWM4CLK_SSR; /*!< PWM4CLK source select register, Address offset : 0xf0 */
mbed_official 558:0880f51c4036 181 __IO uint32_t PWM4CLK_PVSR; /*!< PWM4CLK prescale value select register, Address offset : 0xf4 */
mbed_official 558:0880f51c4036 182 uint32_t RESERVED11[2];
mbed_official 558:0880f51c4036 183 __IO uint32_t PWM5CLK_SSR; /*!< PWM5CLK source select register, Address offset : 0x100 */
mbed_official 558:0880f51c4036 184 __IO uint32_t PWM5LK_PVSR; /*!< PWM5CLK prescale value select register, Address offset : 0x104 */
mbed_official 558:0880f51c4036 185 uint32_t RESERVED12[2];
mbed_official 558:0880f51c4036 186 __IO uint32_t PWM6CLK_SSR; /*!< PWM6CLK source select register, Address offset : 0x110 */
mbed_official 558:0880f51c4036 187 __IO uint32_t PWM6CLK_PVSR; /*!< PWM6CLK prescale value select register, Address offset : 0x114 */
mbed_official 558:0880f51c4036 188 uint32_t RESERVED13[2];
mbed_official 558:0880f51c4036 189 __IO uint32_t PWM7CLK_SSR; /*!< PWM7CLK source select register, Address offset : 0x120 */
mbed_official 558:0880f51c4036 190 __IO uint32_t PWM7CLK_PVSR; /*!< PWM7CLK prescale value select register, Address offset : 0x124 */
mbed_official 558:0880f51c4036 191 uint32_t RESERVED14[2];
mbed_official 558:0880f51c4036 192 __IO uint32_t RTC_HS_SSR; /*!< RTC High Speed source select register, Address offset : 0x130 */
mbed_official 558:0880f51c4036 193 __IO uint32_t RTC_HS_PVSR; /*!< RTC High Speed prescale value select register, Address offset : 0x134 */
mbed_official 558:0880f51c4036 194 uint32_t RESERVED15;
mbed_official 558:0880f51c4036 195 __IO uint32_t RTC_SSR; /*!< RTC source select register, Address offset : 0x13c */
mbed_official 558:0880f51c4036 196
mbed_official 558:0880f51c4036 197 __IO uint32_t WDOGCLK_HS_SSR; /*!< WDOGCLK High Speed source select register, Address offset : 0x140 */
mbed_official 558:0880f51c4036 198 __IO uint32_t WDOGCLK_HS_PVSR; /*!< WDOGCLK High Speed prescale value select register, Address offset : 0x144 */
mbed_official 558:0880f51c4036 199 uint32_t RESERVED16;
mbed_official 558:0880f51c4036 200 __IO uint32_t WDOGCLK_SSR; /*!< WDOGCLK source select register, Address offset : 0x14c */
mbed_official 558:0880f51c4036 201
mbed_official 558:0880f51c4036 202 __IO uint32_t UARTCLK_SSR; /*!< UARTCLK source select register, Address offset : 0x150 */
mbed_official 558:0880f51c4036 203 __IO uint32_t UARTCLK_PVSR; /*!< UARTCLK prescale value select register, Address offset : 0x154 */
mbed_official 558:0880f51c4036 204 uint32_t RESERVED17[2];
mbed_official 558:0880f51c4036 205 __IO uint32_t MIICLK_ECR; /*!< MII clock enable control register, Address offset : 0x160 */
mbed_official 558:0880f51c4036 206 uint32_t RESERVED18[3];
mbed_official 558:0880f51c4036 207 __IO uint32_t MONCLK_SSR; /*!< Monitoring clock source select I found Treasure was IoT Base Station in March.register, Address offset : 0x170 */
mbed_official 558:0880f51c4036 208 }CRG_TypeDef;
mbed_official 558:0880f51c4036 209
mbed_official 558:0880f51c4036 210
mbed_official 558:0880f51c4036 211 /**
mbed_official 558:0880f51c4036 212 * @brief UART
mbed_official 558:0880f51c4036 213 */
mbed_official 558:0880f51c4036 214 typedef struct
mbed_official 558:0880f51c4036 215 {
mbed_official 558:0880f51c4036 216 __IO uint32_t DR; /*!< Data, Address offset : 0x00 */
mbed_official 558:0880f51c4036 217 union {
mbed_official 558:0880f51c4036 218 __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */
mbed_official 558:0880f51c4036 219 __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */
mbed_official 558:0880f51c4036 220 } STATUS;
mbed_official 558:0880f51c4036 221 uint32_t RESERVED0[4];
mbed_official 558:0880f51c4036 222 __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */
mbed_official 558:0880f51c4036 223 uint32_t RESERVED1;
mbed_official 558:0880f51c4036 224 __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */
mbed_official 558:0880f51c4036 225 __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */
mbed_official 558:0880f51c4036 226 __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */
mbed_official 558:0880f51c4036 227 __IO uint32_t LCR_H; /*!< Line Control, Address offset : 0x2C */
mbed_official 558:0880f51c4036 228 __IO uint32_t CR; /*!< Control, Address offset : 0x30 */
mbed_official 558:0880f51c4036 229 __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */
mbed_official 558:0880f51c4036 230 __IO uint32_t IMSC; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */
mbed_official 558:0880f51c4036 231 __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */
mbed_official 558:0880f51c4036 232 __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */
mbed_official 558:0880f51c4036 233 __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */
mbed_official 558:0880f51c4036 234 __IO uint32_t DMACR; /*!< DMA Control, Address offset : 0x48 */
mbed_official 558:0880f51c4036 235 } UART_TypeDef;
mbed_official 558:0880f51c4036 236
mbed_official 558:0880f51c4036 237
mbed_official 558:0880f51c4036 238 /**
mbed_official 558:0880f51c4036 239 * @brief Simple UART
mbed_official 558:0880f51c4036 240 */
mbed_official 558:0880f51c4036 241 typedef struct
mbed_official 558:0880f51c4036 242 {
mbed_official 558:0880f51c4036 243 __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
mbed_official 558:0880f51c4036 244 __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
mbed_official 558:0880f51c4036 245 __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
mbed_official 558:0880f51c4036 246 union {
mbed_official 558:0880f51c4036 247 __I uint32_t STATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
mbed_official 558:0880f51c4036 248 __O uint32_t CLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
mbed_official 558:0880f51c4036 249 }INT;
mbed_official 558:0880f51c4036 250 __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
mbed_official 558:0880f51c4036 251
mbed_official 558:0880f51c4036 252 } S_UART_TypeDef;
mbed_official 558:0880f51c4036 253
mbed_official 558:0880f51c4036 254 /**
mbed_official 558:0880f51c4036 255 * @brief Analog Digital Converter
mbed_official 558:0880f51c4036 256 */
mbed_official 558:0880f51c4036 257
mbed_official 558:0880f51c4036 258 typedef struct
mbed_official 558:0880f51c4036 259 {
mbed_official 558:0880f51c4036 260 __IO uint32_t ADC_CTR; /* ADC control register, Address offset : 0x000 */
mbed_official 558:0880f51c4036 261 __IO uint32_t ADC_CHSEL; /* ADC channel select register, Address offset : 0x004 */
mbed_official 558:0880f51c4036 262 __IO uint32_t ADC_START; /* ADC start register, Address offset : 0x008 */
mbed_official 558:0880f51c4036 263 __I uint32_t ADC_DATA; /* ADC conversion data register, Address offset : 0x00c */
mbed_official 558:0880f51c4036 264 __IO uint32_t ADC_INT; /* ADC interrupt register, Address offset : 0x010 */
mbed_official 558:0880f51c4036 265 uint32_t RESERVED0[2];
mbed_official 558:0880f51c4036 266 __IO uint32_t ADC_INTCLR; /* ADC interrupt clear register, Address offset : 0x01c */
mbed_official 558:0880f51c4036 267 }ADC_TypeDef;
mbed_official 558:0880f51c4036 268
mbed_official 558:0880f51c4036 269 /**
mbed_official 558:0880f51c4036 270 * @brief dualtimer
mbed_official 558:0880f51c4036 271 */
mbed_official 558:0880f51c4036 272 typedef struct
mbed_official 558:0880f51c4036 273 {
mbed_official 558:0880f51c4036 274 __IO uint32_t TimerLoad; // <h> Timer Load </h>
mbed_official 558:0880f51c4036 275 __I uint32_t TimerValue; // <h> Timer Counter Current Value <r></h>
mbed_official 558:0880f51c4036 276 __IO uint32_t TimerControl; // <h> Timer Control
mbed_official 558:0880f51c4036 277 // <o.7> TimerEn: Timer Enable
mbed_official 558:0880f51c4036 278 // <o.6> TimerMode: Timer Mode
mbed_official 558:0880f51c4036 279 // <0=> Freerunning-mode
mbed_official 558:0880f51c4036 280 // <1=> Periodic mode
mbed_official 558:0880f51c4036 281 // <o.5> IntEnable: Interrupt Enable
mbed_official 558:0880f51c4036 282 // <o.2..3> TimerPre: Timer Prescale
mbed_official 558:0880f51c4036 283 // <0=> / 1
mbed_official 558:0880f51c4036 284 // <1=> / 16
mbed_official 558:0880f51c4036 285 // <2=> / 256
mbed_official 558:0880f51c4036 286 // <3=> Undefined!
mbed_official 558:0880f51c4036 287 // <o.1> TimerSize: Timer Size
mbed_official 558:0880f51c4036 288 // <0=> 16-bit counter
mbed_official 558:0880f51c4036 289 // <1=> 32-bit counter
mbed_official 558:0880f51c4036 290 // <o.0> OneShot: One-shoot mode
mbed_official 558:0880f51c4036 291 // <0=> Wrapping mode
mbed_official 558:0880f51c4036 292 // <1=> One-shot mode
mbed_official 558:0880f51c4036 293 // </h>
mbed_official 558:0880f51c4036 294 __O uint32_t TimerIntClr; // <h> Timer Interrupt Clear <w></h>
mbed_official 558:0880f51c4036 295 __I uint32_t TimerRIS; // <h> Timer Raw Interrupt Status <r></h>
mbed_official 558:0880f51c4036 296 __I uint32_t TimerMIS; // <h> Timer Masked Interrupt Status <r></h>
mbed_official 558:0880f51c4036 297 __IO uint32_t TimerBGLoad; // <h> Background Load Register </h>
mbed_official 558:0880f51c4036 298 } DUALTIMER_TypeDef;
mbed_official 558:0880f51c4036 299
mbed_official 558:0880f51c4036 300 /**
mbed_official 558:0880f51c4036 301 * @brief GPIO
mbed_official 558:0880f51c4036 302 */
mbed_official 558:0880f51c4036 303 typedef struct
mbed_official 558:0880f51c4036 304 {
mbed_official 558:0880f51c4036 305 __IO uint32_t DATA; /* DATA Register (R/W), offset : 0x000 */
mbed_official 558:0880f51c4036 306 __IO uint32_t DATAOUT; /* Data Output Latch Register (R/W), offset : 0x004 */
mbed_official 558:0880f51c4036 307 uint32_t RESERVED0[2];
mbed_official 558:0880f51c4036 308 __IO uint32_t OUTENSET; /* Output Enable Set Register (R/W) offset : 0x010 */
mbed_official 558:0880f51c4036 309 __IO uint32_t OUTENCLR; /* Output Enable Clear Register (R/W) offset : 0x014 */
mbed_official 558:0880f51c4036 310 __IO uint32_t RESERVED1; /* Alternate Function Set Register (R/W) offset : 0x018 */
mbed_official 558:0880f51c4036 311 __IO uint32_t RESERVED2; /* Alternate Function Clear Register (R/W) offset : 0x01C */
mbed_official 558:0880f51c4036 312 __IO uint32_t INTENSET; /* Interrupt Enable Set Register (R/W) offset : 0x020 */
mbed_official 558:0880f51c4036 313 __IO uint32_t INTENCLR; /* Interrupt Enable Clear Register (R/W) offset : 0x024 */
mbed_official 558:0880f51c4036 314 __IO uint32_t INTTYPESET; /* Interrupt Type Set Register (R/W) offset : 0x028 */
mbed_official 558:0880f51c4036 315 __IO uint32_t INTTYPECLR; /* Interrupt Type Clear Register (R/W) offset : 0x02C */
mbed_official 558:0880f51c4036 316 __IO uint32_t INTPOLSET; /* Interrupt Polarity Set Register (R/W) offset : 0x030 */
mbed_official 558:0880f51c4036 317 __IO uint32_t INTPOLCLR; /* Interrupt Polarity Clear Register (R/W) offset : 0x034 */
mbed_official 558:0880f51c4036 318 union {
mbed_official 558:0880f51c4036 319 __I uint32_t INTSTATUS; /* Interrupt Status Register (R/ ) offset : 0x038 */
mbed_official 558:0880f51c4036 320 __O uint32_t INTCLEAR; /* Interrupt Clear Register ( /W) offset : 0x038 */
mbed_official 558:0880f51c4036 321 }Interrupt;
mbed_official 558:0880f51c4036 322 uint32_t RESERVED3[241];
mbed_official 558:0880f51c4036 323 __IO uint32_t LB_MASKED[256]; /* Lower byte Masked Access Register (R/W) offset : 0x400 - 0x7FC */
mbed_official 558:0880f51c4036 324 __IO uint32_t UB_MASKED[256]; /* Upper byte Masked Access Register (R/W) offset : 0x800 - 0xBFC */
mbed_official 558:0880f51c4036 325 } GPIO_TypeDef;
mbed_official 558:0880f51c4036 326
mbed_official 558:0880f51c4036 327 typedef struct
mbed_official 558:0880f51c4036 328 {
mbed_official 558:0880f51c4036 329 __IO uint32_t Port[16]; /* Port_00, offset : 0x00 */
mbed_official 558:0880f51c4036 330 /* Port_01, offset : 0x04 */
mbed_official 558:0880f51c4036 331 /* Port_02, offset : 0x08 */
mbed_official 558:0880f51c4036 332 /* Port_03, offset : 0x0C */
mbed_official 558:0880f51c4036 333 /* Port_04, offset : 0x10 */
mbed_official 558:0880f51c4036 334 /* Port_05, offset : 0x14 */
mbed_official 558:0880f51c4036 335 /* Port_06, offset : 0x18 */
mbed_official 558:0880f51c4036 336 /* Port_07, offset : 0x1C */
mbed_official 558:0880f51c4036 337 /* Port_08, offset : 0x20 */
mbed_official 558:0880f51c4036 338 /* Port_09, offset : 0x24 */
mbed_official 558:0880f51c4036 339 /* Port_10, offset : 0x28 */
mbed_official 558:0880f51c4036 340 /* Port_11, offset : 0x2C */
mbed_official 558:0880f51c4036 341 /* Port_12, offset : 0x30 */
mbed_official 558:0880f51c4036 342 /* Port_13, offset : 0x34 */
mbed_official 558:0880f51c4036 343 /* Port_14, offset : 0x38 */
mbed_official 558:0880f51c4036 344 /* Port_15, offset : 0x3C */
mbed_official 558:0880f51c4036 345 } P_Port_Def;
mbed_official 558:0880f51c4036 346
mbed_official 558:0880f51c4036 347 typedef struct
mbed_official 558:0880f51c4036 348 {
mbed_official 558:0880f51c4036 349 __IO uint32_t Port[5]; /* Port_00, offset : 0x00 */
mbed_official 558:0880f51c4036 350 /* Port_01, offset : 0x04 */
mbed_official 558:0880f51c4036 351 /* Port_02, offset : 0x08 */
mbed_official 558:0880f51c4036 352 /* Port_03, offset : 0x0C */
mbed_official 558:0880f51c4036 353 /* Port_04, offset : 0x10 */
mbed_official 558:0880f51c4036 354 } P_Port_D_Def;
mbed_official 558:0880f51c4036 355
mbed_official 558:0880f51c4036 356 /**
mbed_official 558:0880f51c4036 357 * @brief I2C Register structure definition
mbed_official 558:0880f51c4036 358 */
mbed_official 558:0880f51c4036 359 typedef struct
mbed_official 558:0880f51c4036 360 {
mbed_official 558:0880f51c4036 361 __IO uint32_t PRER; //0x00
mbed_official 558:0880f51c4036 362 __IO uint32_t CTR; //0x04
mbed_official 558:0880f51c4036 363 __IO uint32_t CMDR; //0x08
mbed_official 558:0880f51c4036 364 __I uint32_t SR; //0x0C
mbed_official 558:0880f51c4036 365 __IO uint32_t TSR; //0x10
mbed_official 558:0880f51c4036 366 __IO uint32_t SADDR; //0x14
mbed_official 558:0880f51c4036 367 __IO uint32_t TXR; //0x18
mbed_official 558:0880f51c4036 368 __I uint32_t RXR; //0x1C
mbed_official 558:0880f51c4036 369 __I uint32_t ISR; //0x20
mbed_official 558:0880f51c4036 370 __IO uint32_t ISCR; //0x24
mbed_official 558:0880f51c4036 371 __IO uint32_t ISMR; //0x28
mbed_official 558:0880f51c4036 372 }I2C_TypeDef;
mbed_official 558:0880f51c4036 373
mbed_official 558:0880f51c4036 374 /**
mbed_official 558:0880f51c4036 375 * @brief PWM Register structure definition
mbed_official 558:0880f51c4036 376 */
mbed_official 558:0880f51c4036 377 typedef struct
mbed_official 558:0880f51c4036 378 {
mbed_official 558:0880f51c4036 379 __IO uint32_t IER; //Interrupt enable register
mbed_official 558:0880f51c4036 380 // <7> IE7 : Channel 7 interrupt enable <R/W>
mbed_official 558:0880f51c4036 381 // <6> IE6 : Channel 6 interrupt enable <R/W>
mbed_official 558:0880f51c4036 382 // <5> IE5 : Channel 5 interrupt enable <R/W>
mbed_official 558:0880f51c4036 383 // <4> IE4 : Channel 4 interrupt enable <R/W>
mbed_official 558:0880f51c4036 384 // <3> IE3 : Channel 3 interrupt enable <R/W>
mbed_official 558:0880f51c4036 385 // <2> IE2 : Channel 2 interrupt enable <R/W>
mbed_official 558:0880f51c4036 386 // <1> IE1 : Channel 1 interrupt enable <R/W>
mbed_official 558:0880f51c4036 387 // <0> IE0 : Channel 0 interrupt enable <R/W>
mbed_official 558:0880f51c4036 388
mbed_official 558:0880f51c4036 389 __IO uint32_t SSR; //Start Stop register
mbed_official 558:0880f51c4036 390 // <7> SS7 : Channel 7 TC start or stop <R/W>
mbed_official 558:0880f51c4036 391 // <6> SS6 : Channel 6 TC start or stop <R/W>
mbed_official 558:0880f51c4036 392 // <5> SS5 : Channel 5 TC start or stop <R/W>
mbed_official 558:0880f51c4036 393 // <4> SS4 : Channel 4 TC start or stop <R/W>
mbed_official 558:0880f51c4036 394 // <3> SS3 : Channel 3 TC start or stop <R/W>
mbed_official 558:0880f51c4036 395 // <2> SS2 : Channel 2 TC start or stop <R/W>
mbed_official 558:0880f51c4036 396 // <1> SS1 : Channel 1 TC start or stop <R/W>
mbed_official 558:0880f51c4036 397 // <0> SS0 : Channel 0 TC start or stop <R/W>
mbed_official 558:0880f51c4036 398
mbed_official 558:0880f51c4036 399 __IO uint32_t PSR; //Pause register
mbed_official 558:0880f51c4036 400 // <7> PS7 : Channel 7 TC pasue <R/W>
mbed_official 558:0880f51c4036 401 // <6> PS6 : Channel 6 TC pasue <R/W>
mbed_official 558:0880f51c4036 402 // <5> PS5 : Channel 5 TC pasue <R/W>
mbed_official 558:0880f51c4036 403 // <4> PS4 : Channel 4 TC pasue <R/W>
mbed_official 558:0880f51c4036 404 // <3> PS3 : Channel 3 TC pasue <R/W>
mbed_official 558:0880f51c4036 405 // <2> PS2 : Channel 2 TC pasue <R/W>
mbed_official 558:0880f51c4036 406 // <1> PS1 : Channel 1 TC pasue <R/W>
mbed_official 558:0880f51c4036 407 // <0> PS0 : Channel 0 TC pasue <R/W>
mbed_official 558:0880f51c4036 408 } PWM_TypeDef;
mbed_official 558:0880f51c4036 409
mbed_official 558:0880f51c4036 410 typedef struct
mbed_official 558:0880f51c4036 411 {
mbed_official 558:0880f51c4036 412 __I uint32_t IR; //Interrupt register
mbed_official 558:0880f51c4036 413 // <2> CI : Capture interrupt <R>
mbed_official 558:0880f51c4036 414 // <1> OI : Overflow interrupt <R>
mbed_official 558:0880f51c4036 415 // <0> MI : Match interrupt <R>
mbed_official 558:0880f51c4036 416
mbed_official 558:0880f51c4036 417 __IO uint32_t IER; //Interrupt enable register
mbed_official 558:0880f51c4036 418 // <2> CIE : Capture interrupt enable <R/W>
mbed_official 558:0880f51c4036 419 // <1> OIE : Overflow interrupt enable <R/W>
mbed_official 558:0880f51c4036 420 // <0> MIE : Match interrupt enable <R/W>
mbed_official 558:0880f51c4036 421
mbed_official 558:0880f51c4036 422 __O uint32_t ICR; //Interrupt clear register
mbed_official 558:0880f51c4036 423 // <2> CIC : Capture interrupt clear <W>
mbed_official 558:0880f51c4036 424 // <1> OIC : Overflow interrupt clear <W>
mbed_official 558:0880f51c4036 425 // <0> MIC : Match interrupt clear <W>
mbed_official 558:0880f51c4036 426
mbed_official 558:0880f51c4036 427 __I uint32_t TCR; //Timer/Counter register
mbed_official 558:0880f51c4036 428 // <0..31> TCR : Timer/Counter register <R>
mbed_official 558:0880f51c4036 429
mbed_official 558:0880f51c4036 430 __I uint32_t PCR; //Prescale counter register
mbed_official 558:0880f51c4036 431 // <0..5> PCR : Prescale Counter register <R>
mbed_official 558:0880f51c4036 432
mbed_official 558:0880f51c4036 433 __IO uint32_t PR; //Prescale register
mbed_official 558:0880f51c4036 434 // <0..5> PR : prescale register <R/W>
mbed_official 558:0880f51c4036 435
mbed_official 558:0880f51c4036 436 __IO uint32_t MR; //Match register
mbed_official 558:0880f51c4036 437 // <0..31> MR : Match register <R/W>
mbed_official 558:0880f51c4036 438
mbed_official 558:0880f51c4036 439 __IO uint32_t LR; //Limit register
mbed_official 558:0880f51c4036 440 // <0..31> LR : Limit register <R/W>
mbed_official 558:0880f51c4036 441 __IO uint32_t UDMR; //Up-Down mode register
mbed_official 558:0880f51c4036 442 // <0> UDM : Up-down mode <R/W>
mbed_official 558:0880f51c4036 443
mbed_official 558:0880f51c4036 444 __IO uint32_t TCMR; //Timer/Counter mode register
mbed_official 558:0880f51c4036 445 // <0> TCM : Timer/Counter mode <R/W>
mbed_official 558:0880f51c4036 446
mbed_official 558:0880f51c4036 447 __IO uint32_t PEEER; //PWM output enable and external input enable register
mbed_official 558:0880f51c4036 448 // <0..1> PEEE : PWM output enable and external input enable <R/W>
mbed_official 558:0880f51c4036 449
mbed_official 558:0880f51c4036 450 __IO uint32_t CMR; //Capture mode register
mbed_official 558:0880f51c4036 451 // <0> CM : Capture mode <R/W>
mbed_official 558:0880f51c4036 452
mbed_official 558:0880f51c4036 453 __IO uint32_t CR; //Capture register
mbed_official 558:0880f51c4036 454 // <0..31> CR : Capture register <R>
mbed_official 558:0880f51c4036 455
mbed_official 558:0880f51c4036 456 __IO uint32_t PDMR; //Periodic mode register
mbed_official 558:0880f51c4036 457 // <0> PDM : Periodic mode <R/W>
mbed_official 558:0880f51c4036 458
mbed_official 558:0880f51c4036 459 __IO uint32_t DZER; //Dead-zone enable register
mbed_official 558:0880f51c4036 460 // <0> DZE : Dead-zone enable <R/W>
mbed_official 558:0880f51c4036 461
mbed_official 558:0880f51c4036 462 __IO uint32_t DZCR; //Dead-zone counter register
mbed_official 558:0880f51c4036 463 // <0..9> DZC : Dead-zone counter <R/W>
mbed_official 558:0880f51c4036 464 } PWM_CHn_TypeDef;
mbed_official 558:0880f51c4036 465
mbed_official 558:0880f51c4036 466 typedef struct
mbed_official 558:0880f51c4036 467 {
mbed_official 558:0880f51c4036 468 __IO uint32_t PWM_CHn_PR; //Prescale register
mbed_official 558:0880f51c4036 469 // <0..5> PR : prescale register <R/W>
mbed_official 558:0880f51c4036 470 __IO uint32_t PWM_CHn_MR; //Match register
mbed_official 558:0880f51c4036 471 // <0..31> MR : Match register <R/W>
mbed_official 558:0880f51c4036 472 __IO uint32_t PWM_CHn_LR; //Limit register
mbed_official 558:0880f51c4036 473 // <0..31> LR : Limit register <R/W>
mbed_official 558:0880f51c4036 474 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
mbed_official 558:0880f51c4036 475 // <0> UDM : Up-down mode <R/W>
mbed_official 558:0880f51c4036 476 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
mbed_official 558:0880f51c4036 477 // <0> PDM : Periodic mode <R/W>
mbed_official 558:0880f51c4036 478 }PWM_TimerModeInitTypeDef;
mbed_official 558:0880f51c4036 479
mbed_official 558:0880f51c4036 480 typedef struct
mbed_official 558:0880f51c4036 481 {
mbed_official 558:0880f51c4036 482 __IO uint32_t PWM_CHn_PR; //Prescale register
mbed_official 558:0880f51c4036 483 // <0..5> PR : prescale register <R/W>
mbed_official 558:0880f51c4036 484 __IO uint32_t PWM_CHn_MR; //Match register
mbed_official 558:0880f51c4036 485 // <0..31> MR : Match register <R/W>
mbed_official 558:0880f51c4036 486 __IO uint32_t PWM_CHn_LR; //Limit register
mbed_official 558:0880f51c4036 487 // <0..31> LR : Limit register <R/W>
mbed_official 558:0880f51c4036 488 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
mbed_official 558:0880f51c4036 489 // <0> UDM : Up-down mode <R/W>
mbed_official 558:0880f51c4036 490 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
mbed_official 558:0880f51c4036 491 // <0> PDM : Peiodic mode <R/W>
mbed_official 558:0880f51c4036 492 __IO uint32_t PWM_CHn_CMR; //Capture mode register
mbed_official 558:0880f51c4036 493 // <0> CM : Capture mode <R/W>
mbed_official 558:0880f51c4036 494 }PWM_CaptureModeInitTypeDef;
mbed_official 558:0880f51c4036 495
mbed_official 558:0880f51c4036 496 typedef struct
mbed_official 558:0880f51c4036 497 {
mbed_official 558:0880f51c4036 498 __IO uint32_t PWM_CHn_MR;
mbed_official 558:0880f51c4036 499 __IO uint32_t PWM_CHn_LR;
mbed_official 558:0880f51c4036 500 __IO uint32_t PWM_CHn_UDMR;
mbed_official 558:0880f51c4036 501 __IO uint32_t PWM_CHn_PDMR;
mbed_official 558:0880f51c4036 502 __IO uint32_t PWM_CHn_TCMR;
mbed_official 558:0880f51c4036 503 }PWM_CounterModeInitTypeDef;
mbed_official 558:0880f51c4036 504
mbed_official 558:0880f51c4036 505
mbed_official 558:0880f51c4036 506 /**
mbed_official 558:0880f51c4036 507 * @brief Random Number generator
mbed_official 558:0880f51c4036 508 */
mbed_official 558:0880f51c4036 509 typedef struct
mbed_official 558:0880f51c4036 510 {
mbed_official 558:0880f51c4036 511 __IO uint32_t RNG_RUN; /* RNG run register, Address offset : 0x000 */
mbed_official 558:0880f51c4036 512 __IO uint32_t RNG_SEED; /* RNG seed value register, Address offset : 0x004 */
mbed_official 558:0880f51c4036 513 __IO uint32_t RNG_CLKSEL; /* RNG Clock source select register, Address offset : 0x008 */
mbed_official 558:0880f51c4036 514 __IO uint32_t RNG_MODE; /* RNG MODE select register, Address offset : 0x00c */
mbed_official 558:0880f51c4036 515 __I uint32_t RNG_RN; /* RNG random number value register, Address offset : 0x010 */
mbed_official 558:0880f51c4036 516 __IO uint32_t RNG_POLY; /* RNG polynomial register, Address offset : 0x014 */
mbed_official 558:0880f51c4036 517 }RNG_TypeDef;
mbed_official 558:0880f51c4036 518
mbed_official 558:0880f51c4036 519 /**
mbed_official 558:0880f51c4036 520 * @brief Serial Peripheral Interface
mbed_official 558:0880f51c4036 521 */
mbed_official 558:0880f51c4036 522 typedef struct
mbed_official 558:0880f51c4036 523 {
mbed_official 558:0880f51c4036 524 __IO uint32_t CR0;
mbed_official 558:0880f51c4036 525 __IO uint32_t CR1;
mbed_official 558:0880f51c4036 526 __IO uint32_t DR;
mbed_official 558:0880f51c4036 527 __IO uint32_t SR;
mbed_official 558:0880f51c4036 528 __IO uint32_t CPSR;
mbed_official 558:0880f51c4036 529 __IO uint32_t IMSC;
mbed_official 558:0880f51c4036 530 __IO uint32_t RIS;
mbed_official 558:0880f51c4036 531 __IO uint32_t MIS;
mbed_official 558:0880f51c4036 532 __IO uint32_t ICR;
mbed_official 558:0880f51c4036 533 __IO uint32_t DMACR;
mbed_official 558:0880f51c4036 534 } SSP_TypeDef;
mbed_official 558:0880f51c4036 535
mbed_official 558:0880f51c4036 536 typedef struct
mbed_official 558:0880f51c4036 537 {
mbed_official 558:0880f51c4036 538 __IO uint32_t WatchdogLoad; // <h> Watchdog Load Register </h>
mbed_official 558:0880f51c4036 539 __I uint32_t WatchdogValue; // <h> Watchdog Value Register </h>
mbed_official 558:0880f51c4036 540 __IO uint32_t WatchdogControl; // <h> Watchdog Control Register
mbed_official 558:0880f51c4036 541 // <o.1> RESEN: Reset enable
mbed_official 558:0880f51c4036 542 // <o.0> INTEN: Interrupt enable
mbed_official 558:0880f51c4036 543 // </h>
mbed_official 558:0880f51c4036 544 __O uint32_t WatchdogIntClr; // <h> Watchdog Clear Interrupt Register </h>
mbed_official 558:0880f51c4036 545 __I uint32_t WatchdogRIS; // <h> Watchdog Raw Interrupt Status Register </h>
mbed_official 558:0880f51c4036 546 __I uint32_t WatchdogMIS; // <h> Watchdog Interrupt Status Register </h>
mbed_official 558:0880f51c4036 547 uint32_t RESERVED[762];
mbed_official 558:0880f51c4036 548 __IO uint32_t WatchdogLock; // <h> Watchdog Lock Register </h>
mbed_official 558:0880f51c4036 549 }WATCHDOG_TypeDef;
mbed_official 558:0880f51c4036 550
mbed_official 558:0880f51c4036 551 /** @addtogroup Peripheral_memory_map
mbed_official 558:0880f51c4036 552 * @{
mbed_official 558:0880f51c4036 553 */
mbed_official 558:0880f51c4036 554
mbed_official 558:0880f51c4036 555 /* Peripheral and SRAM base address */
mbed_official 558:0880f51c4036 556 #define W7500x_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
mbed_official 558:0880f51c4036 557 #define W7500x_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
mbed_official 558:0880f51c4036 558 #define W7500x_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
mbed_official 558:0880f51c4036 559
mbed_official 558:0880f51c4036 560 #define W7500x_RAM_BASE (0x20000000UL)
mbed_official 558:0880f51c4036 561 #define W7500x_APB1_BASE (0x40000000UL)
mbed_official 558:0880f51c4036 562 #define W7500x_APB2_BASE (0x41000000UL)
mbed_official 558:0880f51c4036 563 #define W7500x_AHB_BASE (0x42000000UL)
mbed_official 558:0880f51c4036 564
mbed_official 558:0880f51c4036 565 #define W7500x_UART0_BASE (W7500x_APB1_BASE + 0x0000C000UL)
mbed_official 558:0880f51c4036 566 #define W7500x_UART1_BASE (W7500x_APB1_BASE + 0x0000D000UL)
mbed_official 558:0880f51c4036 567 #define W7500x_UART2_BASE (W7500x_APB1_BASE + 0x00006000UL)
mbed_official 558:0880f51c4036 568
mbed_official 558:0880f51c4036 569 #define W7500x_CRG_BASE (W7500x_APB2_BASE + 0x00001000UL)
mbed_official 558:0880f51c4036 570 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
mbed_official 558:0880f51c4036 571
mbed_official 558:0880f51c4036 572 #define W7500x_INFO_BGT (0x0003FDB8)
mbed_official 558:0880f51c4036 573 #define W7500x_INFO_OSC (0x0003FDBC)
mbed_official 558:0880f51c4036 574
mbed_official 558:0880f51c4036 575 #define W7500x_TRIM_BGT (0x41001210)
mbed_official 558:0880f51c4036 576 #define W7500x_TRIM_OSC (0x41001004)
mbed_official 558:0880f51c4036 577
mbed_official 558:0880f51c4036 578 #define W7500x_DUALTIMER0_BASE (W7500x_APB1_BASE + 0x00001000ul)
mbed_official 558:0880f51c4036 579 #define W7500x_DUALTIMER1_BASE (W7500x_APB1_BASE + 0x00002000ul)
mbed_official 558:0880f51c4036 580
mbed_official 558:0880f51c4036 581 #define EXTI_Px_BASE (W7500x_APB2_BASE + 0x00002200UL)
mbed_official 558:0880f51c4036 582
mbed_official 558:0880f51c4036 583 #define GPIOA_BASE (W7500x_AHB_BASE + 0x00000000UL) // W7500x_AHB_BASE : 0x42000000UL
mbed_official 558:0880f51c4036 584 #define GPIOB_BASE (W7500x_AHB_BASE + 0x01000000UL)
mbed_official 558:0880f51c4036 585 #define GPIOC_BASE (W7500x_AHB_BASE + 0x02000000UL)
mbed_official 558:0880f51c4036 586 #define GPIOD_BASE (W7500x_AHB_BASE + 0x03000000UL)
mbed_official 558:0880f51c4036 587
mbed_official 558:0880f51c4036 588 #define P_AFSR_BASE (W7500x_APB2_BASE + 0x00002000UL)
mbed_official 558:0880f51c4036 589
mbed_official 558:0880f51c4036 590 #define P_PCR_BASE (W7500x_APB2_BASE + 0x00003000UL)
mbed_official 558:0880f51c4036 591
mbed_official 558:0880f51c4036 592 #define I2C0_BASE (W7500x_APB1_BASE + 0x8000)
mbed_official 558:0880f51c4036 593 #define I2C1_BASE (W7500x_APB1_BASE + 0x9000)
mbed_official 558:0880f51c4036 594
mbed_official 558:0880f51c4036 595 #define W7500x_PWM_BASE (W7500x_APB1_BASE + 0x00005000UL)
mbed_official 558:0880f51c4036 596
mbed_official 558:0880f51c4036 597 #define W7500x_RNG_BASE (W7500x_APB1_BASE + 0x00007000UL)
mbed_official 558:0880f51c4036 598
mbed_official 558:0880f51c4036 599 #define SSP0_BASE (0x4000A000)
mbed_official 558:0880f51c4036 600 #define SSP1_BASE (0x4000B000)
mbed_official 558:0880f51c4036 601
mbed_official 558:0880f51c4036 602 #define W7500x_WATCHDOG_BASE (W7500x_APB1_BASE + 0x0000UL)
mbed_official 558:0880f51c4036 603
mbed_official 558:0880f51c4036 604 /**
mbed_official 558:0880f51c4036 605 * @}
mbed_official 558:0880f51c4036 606 */
mbed_official 558:0880f51c4036 607
mbed_official 558:0880f51c4036 608
mbed_official 558:0880f51c4036 609 /** @addtogroup Peripheral_declaration
mbed_official 558:0880f51c4036 610 * @{
mbed_official 558:0880f51c4036 611 */
mbed_official 558:0880f51c4036 612 #define CRG ((CRG_TypeDef *) W7500x_CRG_BASE)
mbed_official 558:0880f51c4036 613
mbed_official 558:0880f51c4036 614 #define UART0 ((UART_TypeDef *) W7500x_UART0_BASE)
mbed_official 558:0880f51c4036 615 #define UART1 ((UART_TypeDef *) W7500x_UART1_BASE)
mbed_official 558:0880f51c4036 616 #define UART2 ((S_UART_TypeDef *) W7500x_UART2_BASE)
mbed_official 558:0880f51c4036 617
mbed_official 558:0880f51c4036 618 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
mbed_official 558:0880f51c4036 619
mbed_official 558:0880f51c4036 620 #define DUALTIMER0_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE) )
mbed_official 558:0880f51c4036 621 #define DUALTIMER0_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE + 0x20ul))
mbed_official 558:0880f51c4036 622 #define DUALTIMER1_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE) )
mbed_official 558:0880f51c4036 623 #define DUALTIMER1_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE + 0x20ul))
mbed_official 558:0880f51c4036 624
mbed_official 558:0880f51c4036 625 #define EXTI_PA ((P_Port_Def *) (EXTI_Px_BASE + 0x00000000UL)) /* PA_XX External interrupt Enable Register */
mbed_official 558:0880f51c4036 626 #define EXTI_PB ((P_Port_Def *) (EXTI_Px_BASE + 0x00000040UL)) /* PB_XX External interrupt Enable Register */
mbed_official 558:0880f51c4036 627 #define EXTI_PC ((P_Port_Def *) (EXTI_Px_BASE + 0x00000080UL)) /* PC_XX External interrupt Enable Register */
mbed_official 558:0880f51c4036 628 #define EXTI_PD ((P_Port_D_Def *) (EXTI_Px_BASE + 0x000000C0UL)) /* PD_XX External interrupt Enable Register */
mbed_official 558:0880f51c4036 629
mbed_official 558:0880f51c4036 630 #define GPIOA ((GPIO_TypeDef *) (GPIOA_BASE) )
mbed_official 558:0880f51c4036 631 #define GPIOB ((GPIO_TypeDef *) (GPIOB_BASE) )
mbed_official 558:0880f51c4036 632 #define GPIOC ((GPIO_TypeDef *) (GPIOC_BASE) )
mbed_official 558:0880f51c4036 633 #define GPIOD ((GPIO_TypeDef *) (GPIOD_BASE) )
mbed_official 558:0880f51c4036 634
mbed_official 558:0880f51c4036 635 #define PA_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000000UL)) /* PA_XX Pad Alternate Function Select Register */
mbed_official 558:0880f51c4036 636 #define PB_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000040UL)) /* PB_XX Pad Alternate Function Select Register */
mbed_official 558:0880f51c4036 637 #define PC_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000080UL)) /* PC_XX Pad Alternate Function Select Register */
mbed_official 558:0880f51c4036 638 #define PD_AFSR ((P_Port_D_Def *) (P_AFSR_BASE + 0x000000C0UL)) /* PD_XX Pad Alternate Function Select Register */
mbed_official 558:0880f51c4036 639
mbed_official 558:0880f51c4036 640 #define PA_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000000UL)) /* PA_XX Pad Control Register */
mbed_official 558:0880f51c4036 641 #define PB_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000040UL)) /* PB_XX Pad Control Register */
mbed_official 558:0880f51c4036 642 #define PC_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000080UL)) /* PC_XX Pad Control Register */
mbed_official 558:0880f51c4036 643 #define PD_PCR ((P_Port_D_Def *) (P_PCR_BASE + 0x000000C0UL)) /* PD_XX Pad Control Register */
mbed_official 558:0880f51c4036 644
mbed_official 558:0880f51c4036 645 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
mbed_official 558:0880f51c4036 646 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 558:0880f51c4036 647
mbed_official 558:0880f51c4036 648
mbed_official 558:0880f51c4036 649 #define TIMCLKEN0_0 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0x80ul)
mbed_official 558:0880f51c4036 650 #define TIMCLKEN0_1 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0xA0ul)
mbed_official 558:0880f51c4036 651 #define TIMCLKEN1_0 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0x80ul)
mbed_official 558:0880f51c4036 652 #define TIMCLKEN1_1 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0xA0ul)
mbed_official 558:0880f51c4036 653
mbed_official 558:0880f51c4036 654 #define PWM ((PWM_TypeDef *) (W7500x_PWM_BASE + 0x800UL ))
mbed_official 558:0880f51c4036 655 #define PWM_CH0 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE))
mbed_official 558:0880f51c4036 656 #define PWM_CH1 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x100UL))
mbed_official 558:0880f51c4036 657 #define PWM_CH2 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x200UL))
mbed_official 558:0880f51c4036 658 #define PWM_CH3 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x300UL))
mbed_official 558:0880f51c4036 659 #define PWM_CH4 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x400UL))
mbed_official 558:0880f51c4036 660 #define PWM_CH5 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x500UL))
mbed_official 558:0880f51c4036 661 #define PWM_CH6 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x600UL))
mbed_official 558:0880f51c4036 662 #define PWM_CH7 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x700UL))
mbed_official 558:0880f51c4036 663
mbed_official 567:a97fd0eca828 664 #define PWM_CH0_BASE (W7500x_PWM_BASE)
mbed_official 567:a97fd0eca828 665 #define PWM_CH1_BASE (W7500x_PWM_BASE + 0x100UL)
mbed_official 567:a97fd0eca828 666 #define PWM_CH2_BASE (W7500x_PWM_BASE + 0x200UL)
mbed_official 567:a97fd0eca828 667 #define PWM_CH3_BASE (W7500x_PWM_BASE + 0x300UL)
mbed_official 567:a97fd0eca828 668 #define PWM_CH4_BASE (W7500x_PWM_BASE + 0x400UL)
mbed_official 567:a97fd0eca828 669 #define PWM_CH5_BASE (W7500x_PWM_BASE + 0x500UL)
mbed_official 567:a97fd0eca828 670 #define PWM_CH6_BASE (W7500x_PWM_BASE + 0x600UL)
mbed_official 567:a97fd0eca828 671 #define PWM_CH7_BASE (W7500x_PWM_BASE + 0x700UL)
mbed_official 567:a97fd0eca828 672
mbed_official 558:0880f51c4036 673 #define RNG ((RNG_TypeDef *) W7500x_RNG_BASE)
mbed_official 558:0880f51c4036 674
mbed_official 558:0880f51c4036 675 #define SSP0 ((SSP_TypeDef*) (SSP0_BASE))
mbed_official 558:0880f51c4036 676 #define SSP1 ((SSP_TypeDef*) (SSP1_BASE))
mbed_official 558:0880f51c4036 677
mbed_official 558:0880f51c4036 678 #define WATCHDOG ((WATCHDOG_TypeDef *) W7500x_WATCHDOG_BASE)
mbed_official 558:0880f51c4036 679
mbed_official 558:0880f51c4036 680 /**
mbed_official 558:0880f51c4036 681 * @}
mbed_official 558:0880f51c4036 682 */
mbed_official 558:0880f51c4036 683
mbed_official 558:0880f51c4036 684
mbed_official 558:0880f51c4036 685
mbed_official 558:0880f51c4036 686 /******************************************************************************/
mbed_official 558:0880f51c4036 687 /* */
mbed_official 558:0880f51c4036 688 /* Clock Reset Generator */
mbed_official 558:0880f51c4036 689 /* */
mbed_official 558:0880f51c4036 690 /******************************************************************************/
mbed_official 558:0880f51c4036 691 /**************** Bit definition for CRG_OSC_PDR **************************/
mbed_official 558:0880f51c4036 692 #define CRG_OSC_PDR_NRMLOP (0x0ul) // Normal Operation
mbed_official 558:0880f51c4036 693 #define CRG_OSC_PDR_PD (0x1ul) // Power Down
mbed_official 558:0880f51c4036 694 /**************** Bit definition for CRG_PLL_PDR **************************/
mbed_official 558:0880f51c4036 695 #define CRG_PLL_PDR_PD (0x0ul) // Power Down
mbed_official 558:0880f51c4036 696 #define CRG_PLL_PDR_NRMLOP (0x1ul) // Normal Operation
mbed_official 558:0880f51c4036 697 /**************** Bit definition for CRG_PLL_FCR **************************/
mbed_official 558:0880f51c4036 698 //ToDo
mbed_official 558:0880f51c4036 699 /**************** Bit definition for CRG_PLL_OER **************************/
mbed_official 558:0880f51c4036 700 #define CRG_PLL_OER_DIS (0x0ul) // Clock out is disable
mbed_official 558:0880f51c4036 701 #define CRG_PLL_OER_EN (0x1ul) // Clock out is enable
mbed_official 558:0880f51c4036 702 /**************** Bit definition for CRG_PLL_BPR **************************/
mbed_official 558:0880f51c4036 703 #define CRG_PLL_BPR_DIS (0x0ul) // Bypass disable. Normal operation
mbed_official 558:0880f51c4036 704 #define CRG_PLL_BPR_EN (0x1ul) // Bypass enable. Clock will be set to external clock
mbed_official 558:0880f51c4036 705 /**************** Bit definition for CRG_PLL_IFSR **************************/
mbed_official 558:0880f51c4036 706 #define CRG_PLL_IFSR_RCLK (0x0ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 558:0880f51c4036 707 #define CRG_PLL_IFSR_OCLK (0x1ul) // External oscillator clock (OCLK, 8MHz ~ 24MHz)
mbed_official 558:0880f51c4036 708 /**************** Bit definition for CRG_FCLK_SSR **************************/
mbed_official 558:0880f51c4036 709 #define CRG_FCLK_SSR_MCLK (0x01ul) // 00,01 Output clock of PLL(MCLK)
mbed_official 558:0880f51c4036 710 #define CRG_FCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 558:0880f51c4036 711 #define CRG_FCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 558:0880f51c4036 712 /**************** Bit definition for CRG_FCLK_PVSR **************************/
mbed_official 558:0880f51c4036 713 #define CRG_FCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 558:0880f51c4036 714 #define CRG_FCLK_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 558:0880f51c4036 715 #define CRG_FCLK_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 558:0880f51c4036 716 #define CRG_FCLK_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 558:0880f51c4036 717 /**************** Bit definition for CRG_SSPCLK_SSR **************************/
mbed_official 558:0880f51c4036 718 #define CRG_SSPCLK_SSR_DIS (0x00ul) // Disable clock
mbed_official 558:0880f51c4036 719 #define CRG_SSPCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
mbed_official 558:0880f51c4036 720 #define CRG_SSPCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 558:0880f51c4036 721 #define CRG_SSPCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 558:0880f51c4036 722 /**************** Bit definition for CRG_SSPCLK_PVSR **************************/
mbed_official 558:0880f51c4036 723 #define CRG_SSPCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 558:0880f51c4036 724 #define CRG_SSPCLK_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 558:0880f51c4036 725 #define CRG_SSPCLK_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 558:0880f51c4036 726 #define CRG_SSPCLK_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 558:0880f51c4036 727 /**************** Bit definition for CRG_ADCCLK_SSR **************************/
mbed_official 558:0880f51c4036 728 #define CRG_ADCCLK_SSR_DIS (0x00ul) // Disable clock
mbed_official 558:0880f51c4036 729 #define CRG_ADCCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
mbed_official 558:0880f51c4036 730 #define CRG_ADCCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 558:0880f51c4036 731 #define CRG_ADCCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 558:0880f51c4036 732 /**************** Bit definition for CRG_ADCCLK_PVSR **************************/
mbed_official 558:0880f51c4036 733 #define CRG_ADCCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 558:0880f51c4036 734 #define CRG_ADCCLK_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 558:0880f51c4036 735 #define CRG_ADCCLK_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 558:0880f51c4036 736 #define CRG_ADCCLK_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 558:0880f51c4036 737 /**************** Bit definition for CRG_TIMER0/1CLK_SSR **************************/
mbed_official 558:0880f51c4036 738 #define CRG_TIMERCLK_SSR_DIS (0x00ul) // Disable clock
mbed_official 558:0880f51c4036 739 #define CRG_TIMERCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
mbed_official 558:0880f51c4036 740 #define CRG_TIMERCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 558:0880f51c4036 741 #define CRG_TIMERCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 558:0880f51c4036 742 /**************** Bit definition for CRG_TIMER0/1CLK_PVSR **************************/
mbed_official 558:0880f51c4036 743 #define CRG_TIMERCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 558:0880f51c4036 744 #define CRG_TIMERCLK_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 558:0880f51c4036 745 #define CRG_TIMERCLK_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 558:0880f51c4036 746 #define CRG_TIMERCLK_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 558:0880f51c4036 747 #define CRG_TIMERCLK_PVSR_DIV16 (0x04ul) // 1/16
mbed_official 558:0880f51c4036 748 #define CRG_TIMERCLK_PVSR_DIV32 (0x05ul) // 1/32
mbed_official 558:0880f51c4036 749 #define CRG_TIMERCLK_PVSR_DIV64 (0x06ul) // 1/64
mbed_official 558:0880f51c4036 750 #define CRG_TIMERCLK_PVSR_DIV128 (0x07ul) // 1/128
mbed_official 558:0880f51c4036 751 /**************** Bit definition for CRG_PWMnCLK_SSR **************************/
mbed_official 558:0880f51c4036 752 #define CRG_PWMCLK_SSR_DIS (0x00ul) // Disable clock
mbed_official 558:0880f51c4036 753 #define CRG_PWMCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
mbed_official 558:0880f51c4036 754 #define CRG_PWMCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 558:0880f51c4036 755 #define CRG_PWMCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 558:0880f51c4036 756 /**************** Bit definition for CRG_PWMnCLK_PVSR **************************/
mbed_official 558:0880f51c4036 757 #define CRG_PWMCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 558:0880f51c4036 758 #define CRG_PWMCLK_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 558:0880f51c4036 759 #define CRG_PWMCLK_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 558:0880f51c4036 760 #define CRG_PWMCLK_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 558:0880f51c4036 761 #define CRG_PWMCLK_PVSR_DIV16 (0x04ul) // 1/16
mbed_official 558:0880f51c4036 762 #define CRG_PWMCLK_PVSR_DIV32 (0x05ul) // 1/32
mbed_official 558:0880f51c4036 763 #define CRG_PWMCLK_PVSR_DIV64 (0x06ul) // 1/64
mbed_official 558:0880f51c4036 764 #define CRG_PWMCLK_PVSR_DIV128 (0x07ul) // 1/128
mbed_official 558:0880f51c4036 765 /**************** Bit definition for CRG_RTC_HS_SSR **************************/
mbed_official 558:0880f51c4036 766 #define CRG_RTC_HS_SSR_DIS (0x00ul) // Disable clock
mbed_official 558:0880f51c4036 767 #define CRG_RTC_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
mbed_official 558:0880f51c4036 768 #define CRG_RTC_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 558:0880f51c4036 769 #define CRG_RTC_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 558:0880f51c4036 770 /**************** Bit definition for CRG_RTC_HS_PVSR **************************/
mbed_official 558:0880f51c4036 771 #define CRG_RTC_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 558:0880f51c4036 772 #define CRG_RTC_HS_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 558:0880f51c4036 773 #define CRG_RTC_HS_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 558:0880f51c4036 774 #define CRG_RTC_HS_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 558:0880f51c4036 775 #define CRG_RTC_HS_PVSR_DIV16 (0x04ul) // 1/16
mbed_official 558:0880f51c4036 776 #define CRG_RTC_HS_PVSR_DIV32 (0x05ul) // 1/32
mbed_official 558:0880f51c4036 777 #define CRG_RTC_HS_PVSR_DIV64 (0x06ul) // 1/64
mbed_official 558:0880f51c4036 778 #define CRG_RTC_HS_PVSR_DIV128 (0x07ul) // 1/128
mbed_official 558:0880f51c4036 779 /**************** Bit definition for CRG_RTC_SSR **************************/
mbed_official 558:0880f51c4036 780 #define CRG_RTC_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
mbed_official 558:0880f51c4036 781 #define CRG_RTC_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
mbed_official 558:0880f51c4036 782 /**************** Bit definition for CRG_WDOGCLK_HS_SSR **************************/
mbed_official 558:0880f51c4036 783 #define CRG_WDOGCLK_HS_SSR_DIS (0x00ul) // Disable clock
mbed_official 558:0880f51c4036 784 #define CRG_WDOGCLK_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
mbed_official 558:0880f51c4036 785 #define CRG_WDOGCLK_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 558:0880f51c4036 786 #define CRG_WDOGCLK_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 558:0880f51c4036 787 /**************** Bit definition for CRG_WDOGCLK_HS_PVSR **************************/
mbed_official 558:0880f51c4036 788 #define CRG_WDOGCLK_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 558:0880f51c4036 789 #define CRG_WDOGCLK_HS_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 558:0880f51c4036 790 #define CRG_WDOGCLK_HS_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 558:0880f51c4036 791 #define CRG_WDOGCLK_HS_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 558:0880f51c4036 792 #define CRG_WDOGCLK_HS_PVSR_DIV16 (0x04ul) // 1/16
mbed_official 558:0880f51c4036 793 #define CRG_WDOGCLK_HS_PVSR_DIV32 (0x05ul) // 1/32
mbed_official 558:0880f51c4036 794 #define CRG_WDOGCLK_HS_PVSR_DIV64 (0x06ul) // 1/64
mbed_official 558:0880f51c4036 795 #define CRG_WDOGCLK_HS_PVSR_DIV128 (0x07ul) // 1/128
mbed_official 558:0880f51c4036 796 /**************** Bit definition for CRG_WDOGCLK_SSR **************************/
mbed_official 558:0880f51c4036 797 #define CRG_WDOGCLK_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
mbed_official 558:0880f51c4036 798 #define CRG_WDOGCLK_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
mbed_official 558:0880f51c4036 799 /**************** Bit definition for CRG_UARTCLK_SSR **************************/
mbed_official 558:0880f51c4036 800 #define CRG_UARTCLK_SSR_DIS (0x00ul) // Disable clock
mbed_official 558:0880f51c4036 801 #define CRG_UARTCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
mbed_official 558:0880f51c4036 802 #define CRG_UARTCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 558:0880f51c4036 803 #define CRG_UARTCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 558:0880f51c4036 804 /**************** Bit definition for CRG_UARTCLK_PVSR **************************/
mbed_official 558:0880f51c4036 805 #define CRG_UARTCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
mbed_official 558:0880f51c4036 806 #define CRG_UARTCLK_PVSR_DIV2 (0x01ul) // 1/2
mbed_official 558:0880f51c4036 807 #define CRG_UARTCLK_PVSR_DIV4 (0x02ul) // 1/4
mbed_official 558:0880f51c4036 808 #define CRG_UARTCLK_PVSR_DIV8 (0x03ul) // 1/8
mbed_official 558:0880f51c4036 809 /**************** Bit definition for CRG_MIICLK_ECR **************************/
mbed_official 558:0880f51c4036 810 #define CRG_MIICLK_ECR_EN_RXCLK (0x01ul << 0) // Enable MII_RCK and MII_RCK_N
mbed_official 558:0880f51c4036 811 #define CRG_MIICLK_ECR_EN_TXCLK (0x01ul << 1) // Enable MII_TCK and MII_TCK_N
mbed_official 558:0880f51c4036 812 /**************** Bit definition for CRG_MONCLK_SSR **************************/
mbed_official 558:0880f51c4036 813 #define CRG_MONCLK_SSR_MCLK (0x00ul) // PLL output clock (MCLK)
mbed_official 558:0880f51c4036 814 #define CRG_MONCLK_SSR_FCLK (0x01ul) // FCLK
mbed_official 558:0880f51c4036 815 #define CRG_MONCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
mbed_official 558:0880f51c4036 816 #define CRG_MONCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
mbed_official 558:0880f51c4036 817 #define CRG_MONCLK_SSR_ADCCLK (0x04ul) // ADCCLK
mbed_official 558:0880f51c4036 818 #define CRG_MONCLK_SSR_SSPCLK (0x05ul) // SSPCLK
mbed_official 558:0880f51c4036 819 #define CRG_MONCLK_SSR_TIMCLK0 (0x06ul) // TIMCLK0
mbed_official 558:0880f51c4036 820 #define CRG_MONCLK_SSR_TIMCLK1 (0x07ul) // TIMCLK1
mbed_official 558:0880f51c4036 821 #define CRG_MONCLK_SSR_PWMCLK0 (0x08ul) // PWMCLK0
mbed_official 558:0880f51c4036 822 #define CRG_MONCLK_SSR_PWMCLK1 (0x09ul) // PWMCLK1
mbed_official 558:0880f51c4036 823 #define CRG_MONCLK_SSR_PWMCLK2 (0x0Aul) // PWMCLK2
mbed_official 558:0880f51c4036 824 #define CRG_MONCLK_SSR_PWMCLK3 (0x0Bul) // PWMCLK3
mbed_official 558:0880f51c4036 825 #define CRG_MONCLK_SSR_PWMCLK4 (0x0Cul) // PWMCLK4
mbed_official 558:0880f51c4036 826 #define CRG_MONCLK_SSR_PWMCLK5 (0x0Dul) // PWMCLK5
mbed_official 558:0880f51c4036 827 #define CRG_MONCLK_SSR_PWMCLK6 (0x0Eul) // PWMCLK6
mbed_official 558:0880f51c4036 828 #define CRG_MONCLK_SSR_PWMCLK7 (0x0Ful) // PWMCLK7
mbed_official 558:0880f51c4036 829 #define CRG_MONCLK_SSR_UARTCLK (0x10ul) // UARTCLK
mbed_official 558:0880f51c4036 830 #define CRG_MONCLK_SSR_MII_RXCLK (0x11ul) // MII_RXCLK
mbed_official 558:0880f51c4036 831 #define CRG_MONCLK_SSR_MII_TXCLK (0x12ul) // MII_TXCLK
mbed_official 558:0880f51c4036 832 #define CRG_MONCLK_SSR_RTCCLK (0x13ul) // RTCCLK
mbed_official 558:0880f51c4036 833
mbed_official 558:0880f51c4036 834 /******************************************************************************/
mbed_official 558:0880f51c4036 835 /* */
mbed_official 558:0880f51c4036 836 /* UART */
mbed_official 558:0880f51c4036 837 /* */
mbed_official 558:0880f51c4036 838 /******************************************************************************/
mbed_official 558:0880f51c4036 839 /****************** Bit definition for UART Data(UARTDR) register *************************/
mbed_official 558:0880f51c4036 840 #define UART_DR_OE (0x01ul << 11) // Overrun Error
mbed_official 558:0880f51c4036 841 #define UART_DR_BE (0x01ul << 10) // Break Error
mbed_official 558:0880f51c4036 842 #define UART_DR_PE (0x01ul << 9) // Parity Error
mbed_official 558:0880f51c4036 843 #define UART_DR_FE (0x01ul << 8) // Framing Error
mbed_official 558:0880f51c4036 844 //#define UART_DR_DR // ToDo
mbed_official 558:0880f51c4036 845 /***************** Bit definition for UART Receive Status(UARTRSR) register ***************/
mbed_official 558:0880f51c4036 846 #define UARTR_SR_OE (0x01ul << 3) // Overrun Error
mbed_official 558:0880f51c4036 847 #define UARTR_SR_BE (0x01ul << 2) // Break Error
mbed_official 558:0880f51c4036 848 #define UARTR_SR_PE (0x01ul << 1) // Parity Error
mbed_official 558:0880f51c4036 849 #define UARTR_SR_FE (0x01ul << 0) // Framing Error
mbed_official 558:0880f51c4036 850 /***************** Bit definition for UART Error Clear(UARTECR) register ******************/
mbed_official 558:0880f51c4036 851 #define UARTE_CR_OE (0x01ul << 3) // Overrun Error
mbed_official 558:0880f51c4036 852 #define UARTE_CR_BE (0x01ul << 2) // Break Error
mbed_official 558:0880f51c4036 853 #define UARTE_CR_PE (0x01ul << 1) // Parity Error
mbed_official 558:0880f51c4036 854 #define UARTE_CR_FE (0x01ul << 0) // Framing Error
mbed_official 558:0880f51c4036 855 /****************** Bit definition for UART Flags(UARTFR) register ************************/
mbed_official 558:0880f51c4036 856 #define UART_FR_RI (0x01ul << 8) // Ring indicator
mbed_official 558:0880f51c4036 857 #define UART_FR_TXFE (0x01ul << 7) // Transmit FIFO empty
mbed_official 558:0880f51c4036 858 #define UART_FR_RXFF (0x01ul << 6) // Receive FIFO full
mbed_official 558:0880f51c4036 859 #define UART_FR_TXFF (0x01ul << 5) // Transmit FIFO full
mbed_official 558:0880f51c4036 860 #define UART_FR_RXFE (0x01ul << 4) // Receive FIFO empty
mbed_official 558:0880f51c4036 861 #define UART_FR_BUSY (0x01ul << 3) // UART busy
mbed_official 558:0880f51c4036 862 #define UART_FR_DCD (0x01ul << 2) // Data carrier detect
mbed_official 558:0880f51c4036 863 #define UART_FR_DSR (0x01ul << 1) // Data set ready
mbed_official 558:0880f51c4036 864 #define UART_FR_CTS (0x01ul << 0) // Clear to send
mbed_official 558:0880f51c4036 865 /********** Bit definition for UART Low-power Counter(UARTILPR) register *******************/
mbed_official 558:0880f51c4036 866 #define UARTILPR_COUNTER (0xFFul << 0) // 8-bit low-power divisor value (0..255)
mbed_official 558:0880f51c4036 867 /********************* Bit definition for Line Control(UARTLCR_H) register *****************/
mbed_official 558:0880f51c4036 868 #define UART_LCR_H_SPS (0x1ul << 7) // Stick parity select
mbed_official 558:0880f51c4036 869 #define UART_LCR_H_WLEN(n) ((n & 0x3ul) << 5) // Word length ( 0=5bits, 1=6bits, 2=7bits, 3=8bits )
mbed_official 558:0880f51c4036 870 #define UART_LCR_H_FEN (0x1ul << 4) // Enable FIFOs
mbed_official 558:0880f51c4036 871 #define UART_LCR_H_STP2 (0x1ul << 3) // Two stop bits select
mbed_official 558:0880f51c4036 872 #define UART_LCR_H_EPS (0x1ul << 2) // Even parity select
mbed_official 558:0880f51c4036 873 #define UART_LCR_H_PEN (0x1ul << 1) // Parity enable
mbed_official 558:0880f51c4036 874 #define UART_LCR_H_BRK (0x1ul << 0) // Send break
mbed_official 558:0880f51c4036 875 /********************* Bit definition for Contro(UARTCR) register *************************/
mbed_official 558:0880f51c4036 876 #define UART_CR_CTSEn (0x1ul << 15) // CTS hardware flow control enable
mbed_official 558:0880f51c4036 877 #define UART_CR_RTSEn (0x1ul << 14) // RTS hardware flow control enable
mbed_official 558:0880f51c4036 878 #define UART_CR_Out2 (0x1ul << 13) // Complement of Out2 modem status output
mbed_official 558:0880f51c4036 879 #define UART_CR_Out1 (0x1ul << 12) // Complement of Out1 modem status output
mbed_official 558:0880f51c4036 880 #define UART_CR_RTS (0x1ul << 11) // Request to send
mbed_official 558:0880f51c4036 881 #define UART_CR_DTR (0x1ul << 10) // Data transmit ready
mbed_official 558:0880f51c4036 882 #define UART_CR_RXE (0x1ul << 9) // Receive enable
mbed_official 558:0880f51c4036 883 #define UART_CR_TXE (0x1ul << 8) // Transmit enable
mbed_official 558:0880f51c4036 884 #define UART_CR_LBE (0x1ul << 7) // Loop-back enable
mbed_official 558:0880f51c4036 885 #define UART_CR_SIRLP (0x1ul << 2) // IrDA SIR low power mode
mbed_official 558:0880f51c4036 886 #define UART_CR_SIREN (0x1ul << 1) // SIR enable
mbed_official 558:0880f51c4036 887 #define UART_CR_UARTEN (0x1ul << 0) // UART enable
mbed_official 558:0880f51c4036 888 /******* Bit definition for Interrupt FIFO Level Select(UARTIFLS) register *****************/
mbed_official 558:0880f51c4036 889 #define UART_IFLS_RXIFLSEL(n) ((n & 0x7ul) << 3) // Receive interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
mbed_official 558:0880f51c4036 890 #define UART_IFLS_TXIFLSEL(n) ((n & 0x7ul) << 0) // Transmit interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
mbed_official 558:0880f51c4036 891 /******* Bit definition for Interrupt Mask Set/Clear(UARTIMSC) register ********************/
mbed_official 558:0880f51c4036 892 #define UART_IMSC_OEIM (0x1ul << 10) // Overrun error interrupt mask
mbed_official 558:0880f51c4036 893 #define UART_IMSC_BEIM (0x1ul << 9) // Break error interrupt mask
mbed_official 558:0880f51c4036 894 #define UART_IMSC_PEIM (0x1ul << 8) // Parity error interrupt mask
mbed_official 558:0880f51c4036 895 #define UART_IMSC_FEIM (0x1ul << 7) // Framing error interrupt mask
mbed_official 558:0880f51c4036 896 #define UART_IMSC_RTIM (0x1ul << 6) // Receive interrupt mask
mbed_official 558:0880f51c4036 897 #define UART_IMSC_TXIM (0x1ul << 5) // Transmit interrupt mask
mbed_official 558:0880f51c4036 898 #define UART_IMSC_RXIM (0x1ul << 4) // Receive interrupt mask
mbed_official 558:0880f51c4036 899 #define UART_IMSC_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt mask
mbed_official 558:0880f51c4036 900 #define UART_IMSC_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt mask
mbed_official 558:0880f51c4036 901 #define UART_IMSC_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt mask
mbed_official 558:0880f51c4036 902 #define UART_IMSC_RIMIM (0x1ul << 0) // nUARTRI modem interrupt mask
mbed_official 558:0880f51c4036 903 /*************** Bit definition for Raw Interrupt Status(UARTRIS) register *****************/
mbed_official 558:0880f51c4036 904 #define UART_RIS_OEIM (0x1ul << 10) // Overrun error interrupt status
mbed_official 558:0880f51c4036 905 #define UART_RIS_BEIM (0x1ul << 9) // Break error interrupt status
mbed_official 558:0880f51c4036 906 #define UART_RIS_PEIM (0x1ul << 8) // Parity error interrupt status
mbed_official 558:0880f51c4036 907 #define UART_RIS_FEIM (0x1ul << 7) // Framing error interrupt status
mbed_official 558:0880f51c4036 908 #define UART_RIS_RTIM (0x1ul << 6) // Receive interrupt status
mbed_official 558:0880f51c4036 909 #define UART_RIS_TXIM (0x1ul << 5) // Transmit interrupt status
mbed_official 558:0880f51c4036 910 #define UART_RIS_RXIM (0x1ul << 4) // Receive interrupt status
mbed_official 558:0880f51c4036 911 #define UART_RIS_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt status
mbed_official 558:0880f51c4036 912 #define UART_RIS_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt status
mbed_official 558:0880f51c4036 913 #define UART_RIS_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt status
mbed_official 558:0880f51c4036 914 #define UART_RIS_RIMIM (0x1ul << 0) // nUARTRI modem interrupt status
mbed_official 558:0880f51c4036 915 /************** Bit definition for Masked Interrupt Status(UARTMIS) register ****************/
mbed_official 558:0880f51c4036 916 #define UART_MIS_OEIM (0x1ul << 10) // Overrun error masked interrupt status
mbed_official 558:0880f51c4036 917 #define UART_MIS_BEIM (0x1ul << 9) // Break error masked interrupt status
mbed_official 558:0880f51c4036 918 #define UART_MIS_PEIM (0x1ul << 8) // Parity error masked interrupt status
mbed_official 558:0880f51c4036 919 #define UART_MIS_FEIM (0x1ul << 7) // Framing error masked interrupt status
mbed_official 558:0880f51c4036 920 #define UART_MIS_RTIM (0x1ul << 6) // Receive masked interrupt status
mbed_official 558:0880f51c4036 921 #define UART_MIS_TXIM (0x1ul << 5) // Transmit masked interrupt status
mbed_official 558:0880f51c4036 922 #define UART_MIS_RXIM (0x1ul << 4) // Receive masked interrupt status
mbed_official 558:0880f51c4036 923 #define UART_MIS_DSRMIM (0x1ul << 3) // nUARTDSR modem masked interrupt status
mbed_official 558:0880f51c4036 924 #define UART_MIS_DCDMIM (0x1ul << 2) // nUARTDCD modem masked interrupt status
mbed_official 558:0880f51c4036 925 #define UART_MIS_CTSMIM (0x1ul << 1) // nUARTCTS modem masked interrupt status
mbed_official 558:0880f51c4036 926 #define UART_MIS_RIMIM (0x1ul << 0) // nUARTRI modem masked interrupt status
mbed_official 558:0880f51c4036 927 /*************** Bit definition for Interrupt Clear(UARTICR) register ************************/
mbed_official 558:0880f51c4036 928 #define UART_ICR_OEIM (0x1ul << 10) // Overrun error interrupt clear
mbed_official 558:0880f51c4036 929 #define UART_ICR_BEIM (0x1ul << 9) // Break error interrupt clear
mbed_official 558:0880f51c4036 930 #define UART_ICR_PEIM (0x1ul << 8) // Parity error interrupt clear
mbed_official 558:0880f51c4036 931 #define UART_ICR_FEIM (0x1ul << 7) // Framing error interrupt clear
mbed_official 558:0880f51c4036 932 #define UART_ICR_RTIM (0x1ul << 6) // Receive interrupt clear
mbed_official 558:0880f51c4036 933 #define UART_ICR_TXIM (0x1ul << 5) // Transmit interrupt clear
mbed_official 558:0880f51c4036 934 #define UART_ICR_RXIM (0x1ul << 4) // Receive interrupt clear
mbed_official 558:0880f51c4036 935 #define UART_ICR_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt clear
mbed_official 558:0880f51c4036 936 #define UART_ICR_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt clear
mbed_official 558:0880f51c4036 937 #define UART_ICR_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt clear
mbed_official 558:0880f51c4036 938 #define UART_ICR_RIMIM (0x1ul << 0) // nUARTRI modem interrupt clear
mbed_official 558:0880f51c4036 939 /***************** Bit definition for DMA Control(UARTDMACR) register ************************/
mbed_official 558:0880f51c4036 940 #define UART_DMACR_DMAONERR (0x1ul << 2) // DMA on error
mbed_official 558:0880f51c4036 941 #define UART_DMACR_TXDMAE (0x1ul << 1) // Transmit DMA enable
mbed_official 558:0880f51c4036 942 #define UART_DMACR_RXDMAE (0x1ul << 0) // Receive DMA enable
mbed_official 558:0880f51c4036 943
mbed_official 558:0880f51c4036 944 /******************************************************************************/
mbed_official 558:0880f51c4036 945 /* */
mbed_official 558:0880f51c4036 946 /* Simple UART */
mbed_official 558:0880f51c4036 947 /* */
mbed_official 558:0880f51c4036 948 /******************************************************************************/
mbed_official 558:0880f51c4036 949 /***************** Bit definition for S_UART Data () register ************************/
mbed_official 558:0880f51c4036 950 #define S_UART_DATA (0xFFul << 0)
mbed_official 558:0880f51c4036 951 /***************** Bit definition for S_UART State() register ************************/
mbed_official 558:0880f51c4036 952 #define S_UART_STATE_TX_BUF_OVERRUN (0x01ul << 2) // TX buffer overrun, wirte 1 to clear.
mbed_official 558:0880f51c4036 953 #define S_UART_STATE_RX_BUF_FULL (0x01ul << 1) // RX buffer full, read only.
mbed_official 558:0880f51c4036 954 #define S_UART_STATE_TX_BUF_FULL (0x01ul << 0) // TX buffer full, read only.
mbed_official 558:0880f51c4036 955 /***************** Bit definition for S_UART Control() register ************************/
mbed_official 558:0880f51c4036 956 #define S_UART_CTRL_HIGH_SPEED_TEST (0x01ul << 6) // High-speed test mode for TX only.
mbed_official 558:0880f51c4036 957 #define S_UART_CTRL_RX_OVERRUN_EN (0x01ul << 5) // RX overrun interrupt enable.
mbed_official 558:0880f51c4036 958 #define S_UART_CTRL_TX_OVERRUN_EN (0x01ul << 4) // TX overrun interrupt enable.
mbed_official 558:0880f51c4036 959 #define S_UART_CTRL_RX_INT_EN (0x01ul << 3) // RX interrupt enable.
mbed_official 558:0880f51c4036 960 #define S_UART_CTRL_TX_INT_EN (0x01ul << 2) // TX interrupt enable.
mbed_official 558:0880f51c4036 961 #define S_UART_CTRL_RX_EN (0x01ul << 1) // RX enable.
mbed_official 558:0880f51c4036 962 #define S_UART_CTRL_TX_EN (0x01ul << 0) // TX enable.
mbed_official 558:0880f51c4036 963 /***************** Bit definition for S_UART Interrupt() register ************************/
mbed_official 558:0880f51c4036 964 #define S_UART_INT_RX_OVERRUN (0x01ul << 3) // RX overrun interrupt. Wirte 1 to clear
mbed_official 558:0880f51c4036 965 #define S_UART_INT_TX_OVERRUN (0x01ul << 2) // TX overrun interrupt. Write 1 to clear
mbed_official 558:0880f51c4036 966 #define S_UART_INT_RX (0x01ul << 1) // RX interrupt. Write 1 to clear
mbed_official 558:0880f51c4036 967 #define S_UART_INT_TX (0x01ul << 0) // TX interrupt. Write 1 to clear
mbed_official 558:0880f51c4036 968
mbed_official 558:0880f51c4036 969 /******************************************************************************/
mbed_official 558:0880f51c4036 970 /* */
mbed_official 558:0880f51c4036 971 /* Analog Digital Register */
mbed_official 558:0880f51c4036 972 /* */
mbed_official 558:0880f51c4036 973 /******************************************************************************/
mbed_official 558:0880f51c4036 974
mbed_official 558:0880f51c4036 975 /*********************** Bit definition for ADC_CTR ***********************/
mbed_official 558:0880f51c4036 976 //#define ADC_CTR_SAMSEL_ABNORMAL (0x0ul) // Abnormal Operation
mbed_official 558:0880f51c4036 977 //#define ADC_CTR_SAMSEL_NORMAL (0x1ul) // Normal Operation
mbed_official 558:0880f51c4036 978 #define ADC_CTR_PWD_NRMOP (0x1ul) // Active Operation
mbed_official 558:0880f51c4036 979 #define ADC_CTR_PWD_PD (0x3ul) // Power down
mbed_official 558:0880f51c4036 980 /*********************** Bit definition for ADC_CHSEL ***********************/
mbed_official 558:0880f51c4036 981 #define ADC_CHSEL_CH0 (0x0ul) // Channel 0
mbed_official 558:0880f51c4036 982 #define ADC_CHSEL_CH1 (0x1ul) // Channel 1
mbed_official 558:0880f51c4036 983 #define ADC_CHSEL_CH2 (0x2ul) // Channel 2
mbed_official 558:0880f51c4036 984 #define ADC_CHSEL_CH3 (0x3ul) // Channel 3
mbed_official 558:0880f51c4036 985 #define ADC_CHSEL_CH4 (0x4ul) // Channel 4
mbed_official 558:0880f51c4036 986 #define ADC_CHSEL_CH5 (0x5ul) // Channel 5
mbed_official 558:0880f51c4036 987 #define ADC_CHSEL_CH6 (0x6ul) // Channel 6
mbed_official 558:0880f51c4036 988 #define ADC_CHSEL_CH7 (0x7ul) // Channel 7
mbed_official 558:0880f51c4036 989 #define ADC_CHSEL_CH15 (0xful) // LDO output(1.5V)
mbed_official 558:0880f51c4036 990 /*********************** Bit definition for ADC_START ***********************/
mbed_official 558:0880f51c4036 991 #define ADC_START_START (0x1ul) // ADC conversion start
mbed_official 558:0880f51c4036 992 /*********************** Bit definition for ADC_DATA ***********************/
mbed_official 558:0880f51c4036 993 //ToDo (Readonly)
mbed_official 558:0880f51c4036 994
mbed_official 558:0880f51c4036 995 /*********************** Bit definition for ADC_INT ***********************/
mbed_official 558:0880f51c4036 996 #define ADC_INT_MASK_DIS (0x0ul << 1) // Interrupt disable
mbed_official 558:0880f51c4036 997 #define ADC_INT_MASK_ENA (0x1ul << 1) // Interrupt enable
mbed_official 558:0880f51c4036 998 //ToDo (Readonly)
mbed_official 558:0880f51c4036 999
mbed_official 558:0880f51c4036 1000 /*********************** Bit definition for ADC_INTCLR ***********************/
mbed_official 558:0880f51c4036 1001 #define ADC_INTCLEAR (0x1ul) // ADC Interrupt clear
mbed_official 558:0880f51c4036 1002
mbed_official 558:0880f51c4036 1003 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
mbed_official 558:0880f51c4036 1004 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
mbed_official 558:0880f51c4036 1005
mbed_official 558:0880f51c4036 1006 /******************************************************************************/
mbed_official 558:0880f51c4036 1007 /* */
mbed_official 558:0880f51c4036 1008 /* Dual Timer */
mbed_official 558:0880f51c4036 1009 /* */
mbed_official 558:0880f51c4036 1010 /******************************************************************************/
mbed_official 558:0880f51c4036 1011
mbed_official 558:0880f51c4036 1012 /*********************** Bit definition for dualtimer ***********************/
mbed_official 597:47bdd20c4d41 1013 #define DUALTIMER_TimerControl_TimerDIsable 0x0ul
mbed_official 597:47bdd20c4d41 1014 #define DUALTIMER_TimerControl_TimerEnable 0x1ul
mbed_official 597:47bdd20c4d41 1015 #define DUALTIMER_TimerControl_TimerEnable_Pos 7
mbed_official 597:47bdd20c4d41 1016
mbed_official 597:47bdd20c4d41 1017 #define DUALTIMER_TimerControl_FreeRunning 0x0ul
mbed_official 597:47bdd20c4d41 1018 #define DUALTIMER_TimerControl_Periodic 0x1ul
mbed_official 597:47bdd20c4d41 1019 #define DUALTIMER_TimerControl_TimerMode_Pos 6
mbed_official 597:47bdd20c4d41 1020
mbed_official 597:47bdd20c4d41 1021 #define DUALTIMER_TimerControl_IntDisable 0x0ul
mbed_official 597:47bdd20c4d41 1022 #define DUALTIMER_TimerControl_IntEnable 0x1ul
mbed_official 597:47bdd20c4d41 1023 #define DUALTIMER_TimerControl_IntEnable_Pos 5
mbed_official 597:47bdd20c4d41 1024
mbed_official 597:47bdd20c4d41 1025 #define DUALTIMER_TimerControl_Pre_1 0x0ul
mbed_official 597:47bdd20c4d41 1026 #define DUALTIMER_TimerControl_Pre_16 0x1ul
mbed_official 597:47bdd20c4d41 1027 #define DUALTIMER_TimerControl_Pre_256 0x2ul
mbed_official 597:47bdd20c4d41 1028 #define DUALTIMER_TimerControl_Pre_Pos 2
mbed_official 597:47bdd20c4d41 1029
mbed_official 597:47bdd20c4d41 1030 #define DUALTIMER_TimerControl_Size_16 0x0ul
mbed_official 597:47bdd20c4d41 1031 #define DUALTIMER_TimerControl_Size_32 0x1ul
mbed_official 597:47bdd20c4d41 1032 #define DUALTIMER_TimerControl_Size_Pos 1
mbed_official 597:47bdd20c4d41 1033
mbed_official 597:47bdd20c4d41 1034 #define DUALTIMER_TimerControl_Wrapping 0x0ul
mbed_official 597:47bdd20c4d41 1035 #define DUALTIMER_TimerControl_OneShot 0x1ul
mbed_official 597:47bdd20c4d41 1036 #define DUALTIMER_TimerControl_OneShot_Pos 0
mbed_official 558:0880f51c4036 1037
mbed_official 558:0880f51c4036 1038 /******************************************************************************/
mbed_official 558:0880f51c4036 1039 /* */
mbed_official 558:0880f51c4036 1040 /* External Interrupt */
mbed_official 558:0880f51c4036 1041 /* */
mbed_official 558:0880f51c4036 1042 /******************************************************************************/
mbed_official 558:0880f51c4036 1043
mbed_official 558:0880f51c4036 1044 /**************** Bit definition for Px_IER **************************/
mbed_official 558:0880f51c4036 1045 #define EXTI_Px_INTPOR_RISING_EDGE (0x00ul << 0)
mbed_official 558:0880f51c4036 1046 #define EXTI_Px_INTPOR_FALLING_EDGE (0x01ul << 0)
mbed_official 558:0880f51c4036 1047 #define EXTI_Px_INTEN_DISABLE (0x00ul << 1)
mbed_official 558:0880f51c4036 1048 #define EXTI_Px_INTEN_ENABLE (0x01ul << 1)
mbed_official 558:0880f51c4036 1049
mbed_official 558:0880f51c4036 1050 /******************************************************************************/
mbed_official 558:0880f51c4036 1051 /* */
mbed_official 558:0880f51c4036 1052 /* GPIO */
mbed_official 558:0880f51c4036 1053 /* */
mbed_official 558:0880f51c4036 1054 /******************************************************************************/
mbed_official 558:0880f51c4036 1055
mbed_official 558:0880f51c4036 1056 /**************** Bit definition for Px_AFSR **************************/
mbed_official 558:0880f51c4036 1057 #define Px_AFSR_AF0 (0x00ul)
mbed_official 558:0880f51c4036 1058 #define Px_AFSR_AF1 (0x01ul)
mbed_official 558:0880f51c4036 1059 #define Px_AFSR_AF2 (0x02ul)
mbed_official 558:0880f51c4036 1060 #define Px_AFSR_AF3 (0x03ul)
mbed_official 558:0880f51c4036 1061 /**************** Bit definition for Px_PCR **************************/
mbed_official 558:0880f51c4036 1062 #define Px_PCR_PUPD_DOWN (0x01ul << 0) // Pull Down
mbed_official 558:0880f51c4036 1063 #define Px_PCR_PUPD_UP (0x01ul << 1) // Pull Up
mbed_official 558:0880f51c4036 1064 #define Px_PCR_DS_HIGH (0x01ul << 2) // High Driving
mbed_official 558:0880f51c4036 1065 #define Px_PCR_OD (0x01ul << 3) // Open Drain
mbed_official 558:0880f51c4036 1066 #define Px_PCR_IE (0x01ul << 5) // Input Buffer Enable
mbed_official 558:0880f51c4036 1067 #define Px_PCR_CS_SUMMIT (0x01ul << 6) // Use Summit Trigger Input Buffer
mbed_official 558:0880f51c4036 1068
mbed_official 558:0880f51c4036 1069 /******************************************************************************/
mbed_official 558:0880f51c4036 1070 /* */
mbed_official 558:0880f51c4036 1071 /* I2C */
mbed_official 558:0880f51c4036 1072 /* */
mbed_official 558:0880f51c4036 1073 /******************************************************************************/
mbed_official 558:0880f51c4036 1074
mbed_official 558:0880f51c4036 1075 /**************** Bit definition for I2C_CTR **************************/
mbed_official 558:0880f51c4036 1076 #define I2C_CTR_COREEN (0x01ul << 7 ) // 0x80
mbed_official 558:0880f51c4036 1077 #define I2C_CTR_INTEREN (0x01ul << 6 ) // 0x40
mbed_official 558:0880f51c4036 1078 #define I2C_CTR_MODE (0x01ul << 5 ) // 0x20
mbed_official 558:0880f51c4036 1079 #define I2C_CTR_ADDR10 (0x01ul << 4 ) // 0x10
mbed_official 558:0880f51c4036 1080 #define I2C_CTR_CTRRWN (0x01ul << 3 ) // 0x08
mbed_official 558:0880f51c4036 1081 #define I2C_CTR_CTEN (0x01ul << 2 ) // 0x04
mbed_official 558:0880f51c4036 1082
mbed_official 558:0880f51c4036 1083 /**************** Bit definition for I2C_CMDR **************************/
mbed_official 558:0880f51c4036 1084 #define I2C_CMDR_STA (0x01ul << 7 ) // 0x80
mbed_official 558:0880f51c4036 1085 #define I2C_CMDR_STO (0x01ul << 6 ) // 0x40
mbed_official 558:0880f51c4036 1086 #define I2C_CMDR_ACK (0x01ul << 5 ) // 0x20
mbed_official 558:0880f51c4036 1087 #define I2C_CMDR_RESTA (0x01ul << 4 ) // 0x10
mbed_official 558:0880f51c4036 1088
mbed_official 558:0880f51c4036 1089 /**************** Bit definition for I2C_ISCR **************************/
mbed_official 558:0880f51c4036 1090 #define I2C_ISCR_RST (0x01ul << 1) // 0x01
mbed_official 558:0880f51c4036 1091
mbed_official 558:0880f51c4036 1092 /**************** Bit definition for I2C_SR **************************/
mbed_official 558:0880f51c4036 1093 #define I2C_SR_TX (0x01ul << 9 ) // 0x200
mbed_official 558:0880f51c4036 1094 #define I2C_SR_RX (0x01ul << 8 ) // 0x100
mbed_official 558:0880f51c4036 1095 #define I2C_SR_ACKT (0x01ul << 7 ) // 0x080
mbed_official 558:0880f51c4036 1096 #define I2C_SR_BT (0x01ul << 6 ) // 0x040
mbed_official 558:0880f51c4036 1097 #define I2C_SR_SA (0x01ul << 5 ) // 0x020
mbed_official 558:0880f51c4036 1098 #define I2C_SR_SB (0x01ul << 4 ) // 0x010
mbed_official 558:0880f51c4036 1099 #define I2C_SR_AL (0x01ul << 3 ) // 0x008
mbed_official 558:0880f51c4036 1100 #define I2C_SR_TO (0x01ul << 2 ) // 0x004
mbed_official 558:0880f51c4036 1101 #define I2C_SR_SRW (0x01ul << 1 ) // 0x002
mbed_official 558:0880f51c4036 1102 #define I2C_SR_ACKR (0x01ul << 0 ) // 0x001
mbed_official 558:0880f51c4036 1103
mbed_official 558:0880f51c4036 1104 /**************** Bit definition for I2C_ISR **************************/
mbed_official 558:0880f51c4036 1105 #define I2C_ISR_STAE (0x01ul << 4 ) // 0x010
mbed_official 558:0880f51c4036 1106 #define I2C_ISR_STOE (0x01ul << 3 ) // 0x008
mbed_official 558:0880f51c4036 1107 #define I2C_ISR_TOE (0x01ul << 2 ) // 0x004
mbed_official 558:0880f51c4036 1108 #define I2C_ISR_ACK_RXE (0x01ul << 1 ) // 0x002
mbed_official 558:0880f51c4036 1109 #define I2C_ISR_ACK_TXE (0x01ul << 0 ) // 0x001
mbed_official 558:0880f51c4036 1110
mbed_official 558:0880f51c4036 1111 /**************** Bit definition for I2C_ISMR **************************/
mbed_official 558:0880f51c4036 1112 #define I2C_ISR_STAEM (0x01ul << 4 ) // 0x010
mbed_official 558:0880f51c4036 1113 #define I2C_ISR_STOEM (0x01ul << 3 ) // 0x008
mbed_official 558:0880f51c4036 1114 #define I2C_ISR_TOEM (0x01ul << 2 ) // 0x004
mbed_official 558:0880f51c4036 1115 #define I2C_ISR_ACK_RXEM (0x01ul << 1 ) // 0x002
mbed_official 558:0880f51c4036 1116 #define I2C_ISR_ACK_TXEM (0x01ul << 0 ) // 0x001
mbed_official 558:0880f51c4036 1117
mbed_official 558:0880f51c4036 1118 /******************************************************************************/
mbed_official 558:0880f51c4036 1119 /* */
mbed_official 558:0880f51c4036 1120 /* PWM */
mbed_official 558:0880f51c4036 1121 /* */
mbed_official 558:0880f51c4036 1122 /******************************************************************************/
mbed_official 558:0880f51c4036 1123
mbed_official 558:0880f51c4036 1124 /******************************************************************************/
mbed_official 558:0880f51c4036 1125 /* */
mbed_official 558:0880f51c4036 1126 /* Random number generator Register */
mbed_official 558:0880f51c4036 1127 /* */
mbed_official 558:0880f51c4036 1128 /******************************************************************************/
mbed_official 558:0880f51c4036 1129
mbed_official 558:0880f51c4036 1130 /*********************** Bit definition for RNG_RUN ***********************/
mbed_official 558:0880f51c4036 1131 #define RNG_RUN_STOP (0x0ul) // STOP RNG shift register
mbed_official 558:0880f51c4036 1132 #define RNG_RUN_RUN (0x1ul) // RUN RNG shift register
mbed_official 558:0880f51c4036 1133 /*********************** Bit definition for RNG_SEED ***********************/
mbed_official 558:0880f51c4036 1134 //ToDo
mbed_official 558:0880f51c4036 1135
mbed_official 558:0880f51c4036 1136 /*********************** Bit definition for RNG_CLKSEL ***********************/
mbed_official 558:0880f51c4036 1137 #define RNG_CLKSEL_RNGCLK (0x0ul) // RNGCLK is source clock for rng shift register
mbed_official 558:0880f51c4036 1138 #define RNG_CLKSEL_APBCLK (0x1ul) // APBCLK is source clock for rng shift register
mbed_official 558:0880f51c4036 1139 /*********************** Bit definition for RNG_ENABLE ***********************/
mbed_official 558:0880f51c4036 1140 #define RNG_MANUAL_DISABLE (0x0ul) // RNG disble
mbed_official 558:0880f51c4036 1141 #define RNG_MANUAL_ENABLE (0x1ul) // RNG enable
mbed_official 558:0880f51c4036 1142 /*********************** Bit definition for RNG_RN ***********************/
mbed_official 558:0880f51c4036 1143 //ToDo
mbed_official 558:0880f51c4036 1144
mbed_official 558:0880f51c4036 1145 /*********************** Bit definition for RNG_POLY ***********************/
mbed_official 558:0880f51c4036 1146 //ToDo
mbed_official 558:0880f51c4036 1147
mbed_official 558:0880f51c4036 1148
mbed_official 558:0880f51c4036 1149
mbed_official 558:0880f51c4036 1150 #if !defined (USE_HAL_DRIVER)
mbed_official 558:0880f51c4036 1151 #define USE_HAL_DRIVER
mbed_official 558:0880f51c4036 1152 #endif /* USE_HAL_DRIVER */
mbed_official 558:0880f51c4036 1153
mbed_official 558:0880f51c4036 1154
mbed_official 558:0880f51c4036 1155
mbed_official 558:0880f51c4036 1156 #if defined (USE_HAL_DRIVER)
mbed_official 558:0880f51c4036 1157 #include "W7500x_conf.h"
mbed_official 558:0880f51c4036 1158 #endif
mbed_official 558:0880f51c4036 1159
mbed_official 558:0880f51c4036 1160 #ifdef __cplusplus
mbed_official 558:0880f51c4036 1161 }
mbed_official 558:0880f51c4036 1162 #endif
mbed_official 558:0880f51c4036 1163
mbed_official 558:0880f51c4036 1164 #endif /* W7500x_H */
mbed_official 558:0880f51c4036 1165
mbed_official 558:0880f51c4036 1166
mbed_official 558:0880f51c4036 1167
mbed_official 558:0880f51c4036 1168 /************************ (C) COPYRIGHT Wiznet *****END OF FILE****/