mbed official
mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
Revision 171:89b338f31ef1, committed 2017-08-16
- Comitter:
- AnnaBridge
- Date:
- Wed Aug 16 18:27:13 2017 +0100
- Parent:
- 170:19eb464bc2be
- Child:
- 172:7d866c31b3c5
- Commit message:
- This updates the lib to the mbed lib v 149
Changed in this revision
--- a/mbed.h Thu Aug 03 13:13:39 2017 +0100 +++ b/mbed.h Wed Aug 16 18:27:13 2017 +0100 @@ -16,13 +16,13 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 148 +#define MBED_LIBRARY_VERSION 149 #if MBED_CONF_RTOS_PRESENT // RTOS present, this is valid only for mbed OS 5 #define MBED_MAJOR_VERSION 5 #define MBED_MINOR_VERSION 5 -#define MBED_PATCH_VERSION 4 +#define MBED_PATCH_VERSION 5 #else // mbed 2
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/i2c_api.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/i2c_api.c Wed Aug 16 18:27:13 2017 +0100
@@ -173,7 +173,7 @@
int32_t baud_rate;
int32_t tmp_baud;
int32_t tmp_baud_hs;
- enum status_code tmp_status_code;
+ enum status_code tmp_status_code = STATUS_OK;
/* Sanity check arguments */
MBED_ASSERT(obj);
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/pwmout_api.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/pwmout_api.c Wed Aug 16 18:27:13 2017 +0100
@@ -60,7 +60,7 @@
freq_hz = system_gclk_gen_get_hz(obj->clock_source);
- for (i=0; i<sizeof(tcc_prescaler); i++) {
+ for (i=0; i<sizeof(tcc_prescaler) / sizeof(tcc_prescaler[0]); i++) {
div_freq = freq_hz >> tcc_prescaler[i];
if (!div_freq) break;
us_per_cycle = 1000000.00 / div_freq;
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi.c Wed Aug 16 18:27:13 2017 +0100
@@ -1,32 +1,32 @@
/*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-* of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-* list of conditions and the following disclaimer in the documentation and/or
-* other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-* contributors may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
#include "fsl_dspi.h"
@@ -65,27 +65,27 @@
/*!
* @brief Master fill up the TX FIFO with data.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
*/
static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle);
/*!
* @brief Master finish up a transfer.
* It would call back if there is callback function and set the state to idle.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
*/
static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle);
/*!
* @brief Slave fill up the TX FIFO with data.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
*/
static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle);
/*!
* @brief Slave finish up a transfer.
* It would call back if there is callback function and set the state to idle.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
*/
static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle);
@@ -100,7 +100,7 @@
/*!
* @brief Master prepare the transfer.
* Basically it set up dspi_master_handle .
- * This is not a public API as it is called from other driver functions. fsl_dspi_edma.c also call this function.
+ * This is not a public API.
*/
static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer);
@@ -129,7 +129,7 @@
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*! @brief Pointers to dspi handles for each instance. */
-static void *g_dspiHandle[FSL_FEATURE_SOC_DSPI_COUNT];
+static void *g_dspiHandle[ARRAY_SIZE(s_dspiBases)];
/*! @brief Pointer to master IRQ handler for each instance. */
static dspi_master_isr_t s_dspiMasterIsr;
@@ -137,6 +137,8 @@
/*! @brief Pointer to slave IRQ handler for each instance. */
static dspi_slave_isr_t s_dspiSlaveIsr;
+/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/
+volatile uint8_t s_dummyData[ARRAY_SIZE(s_dspiBases)] = {0};
/**********************************************************************************************************************
* Code
*********************************************************************************************************************/
@@ -145,7 +147,7 @@
uint32_t instance;
/* Find the instance index from base address mappings. */
- for (instance = 0; instance < FSL_FEATURE_SOC_DSPI_COUNT; instance++)
+ for (instance = 0; instance < ARRAY_SIZE(s_dspiBases); instance++)
{
if (s_dspiBases[instance] == base)
{
@@ -153,11 +155,17 @@
}
}
- assert(instance < FSL_FEATURE_SOC_DSPI_COUNT);
+ assert(instance < ARRAY_SIZE(s_dspiBases));
return instance;
}
+void DSPI_SetDummyData(SPI_Type *base, uint8_t dummyData)
+{
+ uint32_t instance = DSPI_GetInstance(base);
+ s_dummyData[instance] = dummyData;
+}
+
void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz)
{
assert(masterConfig);
@@ -202,6 +210,7 @@
DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_BetweenTransfer, srcClock_Hz,
masterConfig->ctarConfig.betweenTransferDelayInNanoSec);
+ DSPI_SetDummyData(base, DSPI_DUMMY_DATA);
DSPI_StartTransfer(base);
}
@@ -262,6 +271,8 @@
SPI_CTAR_SLAVE_CPOL(slaveConfig->ctarConfig.cpol) |
SPI_CTAR_SLAVE_CPHA(slaveConfig->ctarConfig.cpha);
+ DSPI_SetDummyData(base, DSPI_DUMMY_DATA);
+
DSPI_StartTransfer(base);
}
@@ -582,7 +593,7 @@
uint16_t wordToSend = 0;
uint16_t wordReceived = 0;
- uint8_t dummyData = DSPI_DUMMY_DATA;
+ uint8_t dummyData = s_dummyData[DSPI_GetInstance(base)];
uint8_t bitsPerFrame;
uint32_t command;
@@ -897,13 +908,10 @@
handle->state = kDSPI_Busy;
DSPI_MasterTransferPrepare(base, handle, transfer);
- DSPI_StartTransfer(base);
/* Enable the NVIC for DSPI peripheral. */
EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]);
- DSPI_MasterTransferFillUpTxFifo(base, handle);
-
/* RX FIFO Drain request: RFDF_RE to enable RFDF interrupt
* Since SPI is a synchronous interface, we only need to enable the RX interrupt.
* The IRQ handler will get the status of RX and TX interrupt flags.
@@ -911,7 +919,10 @@
s_dspiMasterIsr = DSPI_MasterTransferHandleIRQ;
DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable);
+ DSPI_StartTransfer(base);
+ /* Fill up the Tx FIFO to trigger the transfer. */
+ DSPI_MasterTransferFillUpTxFifo(base, handle);
return kStatus_Success;
}
@@ -952,13 +963,12 @@
status = kStatus_Success;
}
+ handle->state = kDSPI_Idle;
+
if (handle->callback)
{
handle->callback(base, handle, status, handle->userData);
}
-
- /* The transfer is complete.*/
- handle->state = kDSPI_Idle;
}
static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle)
@@ -966,7 +976,7 @@
assert(handle);
uint16_t wordToSend = 0;
- uint8_t dummyData = DSPI_DUMMY_DATA;
+ uint8_t dummyData = s_dummyData[DSPI_GetInstance(base)];
/* If bits/frame is greater than one byte */
if (handle->bitsPerFrame > 8)
@@ -1257,11 +1267,6 @@
DSPI_FlushFifo(base, true, true);
DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag);
- DSPI_StartTransfer(base);
-
- /* Prepare data to transmit */
- DSPI_SlaveTransferFillUpTxFifo(base, handle);
-
s_dspiSlaveIsr = DSPI_SlaveTransferHandleIRQ;
/* Enable RX FIFO drain request, the slave only use this interrupt */
@@ -1278,6 +1283,11 @@
DSPI_EnableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable);
}
+ DSPI_StartTransfer(base);
+
+ /* Prepare data to transmit */
+ DSPI_SlaveTransferFillUpTxFifo(base, handle);
+
return kStatus_Success;
}
@@ -1306,7 +1316,7 @@
assert(handle);
uint16_t transmitData = 0;
- uint8_t dummyPattern = DSPI_DUMMY_DATA;
+ uint8_t dummyPattern = s_dummyData[DSPI_GetInstance(base)];
/* Service the transmitter, if transmit buffer provided, transmit the data,
* else transmit dummy pattern
@@ -1413,12 +1423,12 @@
status = kStatus_Success;
}
+ handle->state = kDSPI_Idle;
+
if (handle->callback)
{
handle->callback(base, handle, status, handle->userData);
}
-
- handle->state = kDSPI_Idle;
}
void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle)
@@ -1440,7 +1450,7 @@
{
assert(handle);
- uint8_t dummyPattern = DSPI_DUMMY_DATA;
+ uint8_t dummyPattern = s_dummyData[DSPI_GetInstance(base)];
uint32_t dataReceived;
uint32_t dataSend = 0;
@@ -1617,7 +1627,7 @@
}
}
-#if (FSL_FEATURE_SOC_DSPI_COUNT > 0)
+#if defined(SPI0)
void SPI0_DriverIRQHandler(void)
{
assert(g_dspiHandle[0]);
@@ -1625,7 +1635,7 @@
}
#endif
-#if (FSL_FEATURE_SOC_DSPI_COUNT > 1)
+#if defined(SPI1)
void SPI1_DriverIRQHandler(void)
{
assert(g_dspiHandle[1]);
@@ -1633,7 +1643,7 @@
}
#endif
-#if (FSL_FEATURE_SOC_DSPI_COUNT > 2)
+#if defined(SPI2)
void SPI2_DriverIRQHandler(void)
{
assert(g_dspiHandle[2]);
@@ -1641,7 +1651,7 @@
}
#endif
-#if (FSL_FEATURE_SOC_DSPI_COUNT > 3)
+#if defined(SPI3)
void SPI3_DriverIRQHandler(void)
{
assert(g_dspiHandle[3]);
@@ -1649,7 +1659,7 @@
}
#endif
-#if (FSL_FEATURE_SOC_DSPI_COUNT > 4)
+#if defined(SPI4)
void SPI4_DriverIRQHandler(void)
{
assert(g_dspiHandle[4]);
@@ -1657,7 +1667,7 @@
}
#endif
-#if (FSL_FEATURE_SOC_DSPI_COUNT > 5)
+#if defined(SPI5)
void SPI5_DriverIRQHandler(void)
{
assert(g_dspiHandle[5]);
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi.h Wed Aug 16 18:27:13 2017 +0100
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
@@ -37,15 +37,14 @@
* @{
*/
-
/**********************************************************************************************************************
* Definitions
*********************************************************************************************************************/
/*! @name Driver version */
/*@{*/
-/*! @brief DSPI driver version 2.1.3. */
-#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
+/*! @brief DSPI driver version 2.2.0. */
+#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
/*@}*/
#ifndef DSPI_DUMMY_DATA
@@ -107,7 +106,8 @@
} dspi_master_slave_mode_t;
/*!
- * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is valid
+ * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is
+ * valid
* only when the CPHA bit in the CTAR register is 0.
*/
typedef enum _dspi_master_sample_point
@@ -216,8 +216,9 @@
kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */
kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */
- kDSPI_MasterPcsContinuous = 1U << 20, /*!< Indicates whether the PCS signal is continuous. */
- kDSPI_MasterActiveAfterTransfer = 1U << 21, /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
+ kDSPI_MasterPcsContinuous = 1U << 20, /*!< Indicates whether the PCS signal is continuous. */
+ kDSPI_MasterActiveAfterTransfer =
+ 1U << 21, /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
};
#define DSPI_SLAVE_CTAR_SHIFT (0U) /*!< DSPI slave CTAR shift macro; used internally. */
@@ -240,7 +241,7 @@
/*! @brief DSPI master command date configuration used for the SPIx_PUSHR.*/
typedef struct _dspi_command_data_config
{
- bool isPcsContinuous; /*!< Option to enable the continuous assertion of the chip select between transfers.*/
+ bool isPcsContinuous; /*!< Option to enable the continuous assertion of the chip select between transfers.*/
dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes
Register (CTAR) to use for CTAS.*/
dspi_which_pcs_t whichPcs; /*!< The desired PCS signal to use for the data transfer.*/
@@ -257,10 +258,10 @@
dspi_clock_phase_t cpha; /*!< Clock phase. */
dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
- uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum
- delay. It also sets the boundary value if out of range.*/
- uint32_t lastSckToPcsDelayInNanoSec; /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the
- minimum delay. It also sets the boundary value if out of range.*/
+ uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum
+ delay. It also sets the boundary value if out of range.*/
+ uint32_t lastSckToPcsDelayInNanoSec; /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the
+ minimum delay. It also sets the boundary value if out of range.*/
uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time in nanoseconds; setting to 0 sets the minimum
delay. It also sets the boundary value if out of range.*/
@@ -370,8 +371,9 @@
uint8_t fifoSize; /*!< FIFO dataSize. */
- volatile bool isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
- volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/
+ volatile bool
+ isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
+ volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/
uint8_t *volatile txData; /*!< Send buffer. */
uint8_t *volatile rxData; /*!< Receive buffer. */
@@ -575,6 +577,7 @@
*
* This function configures the various interrupt masks of the DSPI. The parameters are a base and an interrupt mask.
* Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request.
+ * Do not use this API(write to RSER register) while DSPI is in running state.
*
* @code
* DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable );
@@ -950,10 +953,12 @@
* @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data
* buffer master mode and waits till complete to return.
*
- * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total 32-bit word
+ * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total
+* 32-bit word
* as the data to send.
* The command portion provides characteristics of the data, such as the optional continuous chip select operation
- * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS
+ * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the
+* desired PCS
* signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the
* transfer count (normally needed when sending the first frame of a data packet). The user is responsible for
* appending this command with the data to send. This is an example:
@@ -1023,6 +1028,14 @@
}
/*!
+ * @brief Set up the dummy data.
+ *
+ * @param base DSPI peripheral address.
+ * @param dummyData Data to be transferred when tx buffer is NULL.
+ */
+void DSPI_SetDummyData(SPI_Type *base, uint8_t dummyData);
+
+/*!
*@}
*/
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi_edma.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi_edma.c Wed Aug 16 18:27:13 2017 +0100
@@ -1,32 +1,32 @@
/*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-* of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-* list of conditions and the following disclaimer in the documentation and/or
-* other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-* contributors may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
#include "fsl_dspi_edma.h"
@@ -57,7 +57,7 @@
***********************************************************************************************************************/
/*!
* @brief EDMA_DspiMasterCallback after the DSPI master transfer completed by using EDMA.
-* This is not a public API as it is called from other driver functions.
+* This is not a public API.
*/
static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle,
void *g_dspiEdmaPrivateHandle,
@@ -66,7 +66,7 @@
/*!
* @brief EDMA_DspiSlaveCallback after the DSPI slave transfer completed by using EDMA.
-* This is not a public API as it is called from other driver functions.
+* This is not a public API.
*/
static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle,
void *g_dspiEdmaPrivateHandle,
@@ -89,6 +89,8 @@
static dspi_master_edma_private_handle_t s_dspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT];
static dspi_slave_edma_private_handle_t s_dspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT];
+/*! @brief Global variable for dummy data value setting. */
+extern volatile uint8_t s_dummyData[];
/***********************************************************************************************************************
* Code
***********************************************************************************************************************/
@@ -103,7 +105,9 @@
{
assert(handle);
assert(edmaRxRegToRxDataHandle);
+#if (!(defined(FSL_FEATURE_DSPI_HAS_GASKET) && FSL_FEATURE_DSPI_HAS_GASKET))
assert(edmaTxDataToIntermediaryHandle);
+#endif
assert(edmaIntermediaryToTxRegHandle);
/* Zero the handle. */
@@ -145,9 +149,11 @@
return kStatus_DSPI_Busy;
}
+ handle->state = kDSPI_Busy;
+
uint32_t instance = DSPI_GetInstance(base);
uint16_t wordToSend = 0;
- uint8_t dummyData = DSPI_DUMMY_DATA;
+ uint8_t dummyData = s_dummyData[DSPI_GetInstance(base)];
uint8_t dataAlreadyFed = 0;
uint8_t dataFedMax = 2;
@@ -158,9 +164,8 @@
edma_transfer_config_t transferConfigA;
edma_transfer_config_t transferConfigB;
- edma_transfer_config_t transferConfigC;
- handle->txBuffIfNull = ((uint32_t)DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA;
+ handle->txBuffIfNull = ((uint32_t)dummyData << 8) | dummyData;
dspi_command_data_config_t commandStruct;
DSPI_StopTransfer(base);
@@ -196,20 +201,32 @@
handle->remainingReceiveByteCount = transfer->dataSize;
handle->totalByteCount = transfer->dataSize;
- /* This limits the amount of data we can transfer due to the linked channel.
- * The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
+ /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
+ * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
*/
+ uint32_t limited_size = 0;
+ if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+ {
+ limited_size = 32767u;
+ }
+ else
+ {
+ limited_size = 511u;
+ }
+
if (handle->bitsPerFrame > 8)
{
- if (transfer->dataSize > 1022)
+ if (transfer->dataSize > (limited_size << 1u))
{
+ handle->state = kDSPI_Idle;
return kStatus_DSPI_OutOfRange;
}
}
else
{
- if (transfer->dataSize > 511)
+ if (transfer->dataSize > limited_size)
{
+ handle->state = kDSPI_Idle;
return kStatus_DSPI_OutOfRange;
}
}
@@ -217,16 +234,38 @@
/*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */
if ((handle->bitsPerFrame > 8) && (transfer->dataSize & 0x1))
{
+ handle->state = kDSPI_Idle;
return kStatus_InvalidArgument;
}
- handle->state = kDSPI_Busy;
-
DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiMasterCallback,
&s_dspiMasterEdmaPrivateHandle[instance]);
+ /*
+ (1)For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C.
+ channel_A minor link to channel_B , channel_B minor link to channel_C.
+
+ Already pushed 1 or 2 data in SPI_PUSHR , then start the DMA tansfer.
+ channel_A:SPI_POPR to rxData,
+ channel_B:next txData to handle->command (low 16 bits),
+ channel_C:handle->command (32 bits) to SPI_PUSHR, and use the scatter/gather to transfer the last data
+ (handle->lastCommand to SPI_PUSHR).
+
+ (2)For DSPI instances with separate RX and TX DMA requests:
+ Rx DMA request -> channel_A
+ Tx DMA request -> channel_C -> channel_B .
+ channel_C major link to channel_B.
+ So need prepare the first data in "intermediary" before the DMA
+ transfer and then channel_B is used to prepare the next data to "intermediary"
+
+ channel_A:SPI_POPR to rxData,
+ channel_C: handle->command (32 bits) to SPI_PUSHR,
+ channel_B: next txData to handle->command (low 16 bits), and use the scatter/gather to prepare the last data
+ (handle->lastCommand to handle->Command).
+ */
+
/*If dspi has separate dma request , prepare the first data in "intermediary" .
else (dspi has shared dma request) , send first 2 data if there is fifo or send first 1 data if there is no fifo*/
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
@@ -252,6 +291,7 @@
wordToSend = ((uint32_t)dummyData << 8) | dummyData;
}
handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
+ handle->command = handle->lastCommand;
}
else /* For all words except the last word , frame > 8bits */
{
@@ -284,6 +324,7 @@
if (handle->remainingSendByteCount == 1)
{
handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
+ handle->command = handle->lastCommand;
}
else
{
@@ -293,11 +334,10 @@
}
else /*dspi has shared dma request*/
-
{
/* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
- * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
- */
+ * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
+ */
/* If bits/frame is greater than one byte */
if (handle->bitsPerFrame > 8)
@@ -388,7 +428,7 @@
}
}
- /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/
+ /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer(rxData)*/
EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
transferConfigA.srcAddr = (uint32_t)rxAddr;
@@ -428,71 +468,7 @@
EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
kEDMA_MajorInterruptEnable);
- /***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should
- write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the
- SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */
- EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel);
-
- if (handle->remainingSendByteCount > 0)
- {
- if (handle->txData)
- {
- transferConfigB.srcAddr = (uint32_t)(handle->txData);
- transferConfigB.srcOffset = 1;
- }
- else
- {
- transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull);
- transferConfigB.srcOffset = 0;
- }
-
- transferConfigB.destAddr = (uint32_t)(&handle->command);
- transferConfigB.destOffset = 0;
-
- transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes;
-
- if (handle->bitsPerFrame <= 8)
- {
- transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes;
- transferConfigB.minorLoopBytes = 1;
-
- if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
- {
- /*already prepared the first data in "intermediary" , so minus 1 */
- transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 1;
- }
- else
- {
- /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
- majorlink , the majorlink would not trigger the channel_C*/
- transferConfigB.majorLoopCounts = handle->remainingSendByteCount + 1;
- }
- }
- else
- {
- transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes;
- transferConfigB.minorLoopBytes = 2;
- if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
- {
- /*already prepared the first data in "intermediary" , so minus 1 */
- transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
- }
- else
- {
- /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
- * majorlink*/
- transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 + 1;
- }
- }
-
- EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
- handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL);
- }
-
- /***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to
- handle the last data */
- EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel);
-
+ /*Calculate the last data : handle->lastCommand*/
if (((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) ||
((((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) ||
((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8))) &&
@@ -543,8 +519,252 @@
}
}
+/* The feature of GASKET is that the SPI supports 8-bit or 16-bit writes to the PUSH TX FIFO,
+ * allowing a single write to the command word followed by multiple writes to the transmit word.
+ * The TX FIFO will save the last command word written, and convert a 8-bit/16-bit write to the
+ * transmit word into a 32-bit write that pushes both the command word and transmit word into
+ * the TX FIFO (PUSH TX FIFO Register In Master Mode)
+ * So, if this feature is supported, we can use use one channel to carry the receive data from
+ * receive regsiter to user data buffer, use the other channel to carry the data from user data buffer
+ * to transmit register,and use the scatter/gather function to prepare the last data.
+ * That is to say, if GASKET feature is supported, we can use only two channels for tansferring data.
+ */
+#if defined(FSL_FEATURE_DSPI_HAS_GASKET) && FSL_FEATURE_DSPI_HAS_GASKET
+ /* For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data
+ * (handle->lastCommand) to PUSHR register.
+ */
+
+ EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel);
+
if ((1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) ||
- ((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (handle->remainingSendByteCount > 0)))
+ ((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))))
+ {
+ transferConfigB.srcAddr = (uint32_t) & (handle->lastCommand);
+ transferConfigB.destAddr = (uint32_t)txAddr;
+ transferConfigB.srcTransferSize = kEDMA_TransferSize4Bytes;
+ transferConfigB.destTransferSize = kEDMA_TransferSize4Bytes;
+ transferConfigB.srcOffset = 0;
+ transferConfigB.destOffset = 0;
+ transferConfigB.minorLoopBytes = 4;
+ transferConfigB.majorLoopCounts = 1;
+
+ EDMA_TcdReset(softwareTCD);
+ EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigB, NULL);
+ }
+
+ /*User_Send_Buffer(txData) to PUSHR register. */
+ if (((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame <= 8)) ||
+ ((handle->remainingSendByteCount > 4) && (handle->bitsPerFrame > 8)))
+ {
+ if (handle->txData)
+ {
+ if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+ {
+ /* For DSPI with separate RX and TX DMA requests, one frame data has been carry
+ * to handle->command, so need to reduce the pointer of txData.
+ */
+ transferConfigB.srcAddr =
+ (uint32_t)((uint8_t *)(handle->txData) - ((handle->bitsPerFrame <= 8) ? (1U) : (2U)));
+ transferConfigB.srcOffset = 1;
+ }
+ else
+ {
+ /* For DSPI with shared RX and TX DMA requests, one or two frame data have been carry
+ * to PUSHR register, so no need to change the pointer of txData.
+ */
+ transferConfigB.srcAddr = (uint32_t)((uint8_t *)(handle->txData));
+ transferConfigB.srcOffset = 1;
+ }
+ }
+ else
+ {
+ transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull);
+ transferConfigB.srcOffset = 0;
+ }
+
+ transferConfigB.destAddr = (uint32_t)txAddr;
+ transferConfigB.destOffset = 0;
+
+ transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes;
+
+ if (handle->bitsPerFrame <= 8)
+ {
+ transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes;
+ transferConfigB.minorLoopBytes = 1;
+
+ transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 1;
+ }
+ else
+ {
+ transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes;
+ transferConfigB.minorLoopBytes = 2;
+ transferConfigB.majorLoopCounts = (handle->remainingSendByteCount / 2) - 1;
+ }
+
+ EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
+ handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigB, softwareTCD);
+ }
+ /* If only one word to transmit, only carry the lastcommand. */
+ else
+ {
+ EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
+ handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigB, NULL);
+ }
+
+ /*Start the EDMA channel_A , channel_C. */
+ EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
+ EDMA_StartTransfer(handle->edmaIntermediaryToTxRegHandle);
+
+ /* Set the channel link.
+ * For DSPI instances with shared TX and RX DMA requests, setup channel minor link, first receive data from the
+ * receive register, and then carry transmit data to PUSHER register.
+ * For DSPI instance with separate TX and RX DMA requests, there is no need to set up channel link.
+ */
+ if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+ {
+ /*Set channel priority*/
+ uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel;
+ uint8_t channelPriorityHigh = handle->edmaIntermediaryToTxRegHandle->channel;
+ uint8_t t = 0;
+
+ if (channelPriorityLow > channelPriorityHigh)
+ {
+ t = channelPriorityLow;
+ channelPriorityLow = channelPriorityHigh;
+ channelPriorityHigh = t;
+ }
+
+ edma_channel_Preemption_config_t preemption_config_t;
+ preemption_config_t.enableChannelPreemption = true;
+ preemption_config_t.enablePreemptAbility = true;
+ preemption_config_t.channelPriority = channelPriorityLow;
+
+ EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+ &preemption_config_t);
+
+ preemption_config_t.channelPriority = channelPriorityHigh;
+ EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base,
+ handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t);
+ /*if there is Rx DMA request , carry the 32bits data (handle->command) to user data first , then link to
+ channelC to carry the next data to PUSHER register.(txData to PUSHER) */
+ if (handle->remainingSendByteCount > 0)
+ {
+ EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+ kEDMA_MinorLink, handle->edmaIntermediaryToTxRegHandle->channel);
+ }
+ }
+
+ DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
+
+ /* Setup control info to PUSHER register. */
+ *((uint16_t *)&(base->PUSHR) + 1) = (handle->command >> 16U);
+#else
+
+ /***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should
+ write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the
+ SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */
+
+ EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel);
+
+ /*For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data
+ * (handle->lastCommand) to handle->Command*/
+ if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+ {
+ transferConfigB.srcAddr = (uint32_t) & (handle->lastCommand);
+ transferConfigB.destAddr = (uint32_t) & (handle->command);
+ transferConfigB.srcTransferSize = kEDMA_TransferSize4Bytes;
+ transferConfigB.destTransferSize = kEDMA_TransferSize4Bytes;
+ transferConfigB.srcOffset = 0;
+ transferConfigB.destOffset = 0;
+ transferConfigB.minorLoopBytes = 4;
+ transferConfigB.majorLoopCounts = 1;
+
+ EDMA_TcdReset(softwareTCD);
+ EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigB, NULL);
+ }
+
+ /*User_Send_Buffer(txData) to intermediary(handle->command)*/
+ if (((((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame <= 8)) ||
+ ((handle->remainingSendByteCount > 4) && (handle->bitsPerFrame > 8))) &&
+ (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) ||
+ (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))
+ {
+ if (handle->txData)
+ {
+ transferConfigB.srcAddr = (uint32_t)(handle->txData);
+ transferConfigB.srcOffset = 1;
+ }
+ else
+ {
+ transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull);
+ transferConfigB.srcOffset = 0;
+ }
+
+ transferConfigB.destAddr = (uint32_t)(&handle->command);
+ transferConfigB.destOffset = 0;
+
+ transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes;
+
+ if (handle->bitsPerFrame <= 8)
+ {
+ transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes;
+ transferConfigB.minorLoopBytes = 1;
+
+ if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+ {
+ transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 2;
+ }
+ else
+ {
+ /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
+ majorlink , the majorlink would not trigger the channel_C*/
+ transferConfigB.majorLoopCounts = handle->remainingSendByteCount + 1;
+ }
+ }
+ else
+ {
+ transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes;
+ transferConfigB.minorLoopBytes = 2;
+ if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+ {
+ transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 - 2;
+ }
+ else
+ {
+ /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
+ * majorlink*/
+ transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 + 1;
+ }
+ }
+
+ if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+ {
+ EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
+ handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, softwareTCD);
+ EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base,
+ handle->edmaIntermediaryToTxRegHandle->channel, false);
+ }
+ else
+ {
+ EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
+ handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL);
+ }
+ }
+ else
+ {
+ EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
+ handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL);
+ }
+
+ /***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to
+ handle the last data */
+
+ edma_transfer_config_t transferConfigC;
+ EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel);
+
+ /*For DSPI instances with shared RX/TX DMA requests: use the scatter/gather to prepare the last data
+ * (handle->lastCommand) to SPI_PUSHR*/
+ if (((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (handle->remainingSendByteCount > 0)))
{
transferConfigC.srcAddr = (uint32_t) & (handle->lastCommand);
transferConfigC.destAddr = (uint32_t)txAddr;
@@ -560,7 +780,8 @@
}
if (((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) ||
- ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8)))
+ ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8)) ||
+ (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))
{
transferConfigC.srcAddr = (uint32_t)(&(handle->command));
transferConfigC.destAddr = (uint32_t)txAddr;
@@ -570,18 +791,28 @@
transferConfigC.srcOffset = 0;
transferConfigC.destOffset = 0;
transferConfigC.minorLoopBytes = 4;
+ if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+ {
+ if (handle->bitsPerFrame <= 8)
+ {
+ transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1;
+ }
+ else
+ {
+ transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
+ }
- if (handle->bitsPerFrame <= 8)
- {
- transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1;
+ EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
+ handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, softwareTCD);
}
else
{
- transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
+ transferConfigC.majorLoopCounts = 1;
+
+ EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
+ handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, NULL);
}
- EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
- handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, softwareTCD);
EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base,
handle->edmaIntermediaryToTxRegHandle->channel, false);
}
@@ -653,20 +884,15 @@
&preemption_config_t);
}
- /*Set the channel link.
- For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C.
- For DSPI instances with separate RX and TX DMA requests:
- Rx DMA request -> channel_A
- Tx DMA request -> channel_C -> channel_B . (so need prepare the first data in "intermediary" before the DMA
- transfer and then channel_B is used to prepare the next data to "intermediary" ) */
+ /*Set the channel link.*/
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
{
/*if there is Tx DMA request , carry the 32bits data (handle->command) to PUSHR first , then link to channelB
- to prepare the next 32bits data (User_send_buffer to handle->command) */
+ to prepare the next 32bits data (txData to handle->command) */
if (handle->remainingSendByteCount > 1)
{
EDMA_SetChannelLink(handle->edmaIntermediaryToTxRegHandle->base,
- handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MinorLink,
+ handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MajorLink,
handle->edmaTxDataToIntermediaryHandle->channel);
}
@@ -686,7 +912,7 @@
DSPI_EnableDMA(base, kDSPI_RxDmaEnable);
}
-
+#endif
DSPI_StartTransfer(base);
return kStatus_Success;
@@ -805,6 +1031,8 @@
return kStatus_DSPI_Busy;
}
+ handle->state = kDSPI_Busy;
+
uint32_t instance = DSPI_GetInstance(base);
uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT;
handle->bitsPerFrame =
@@ -813,34 +1041,42 @@
/* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
* due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
*/
- if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+ uint32_t limited_size = 0;
+ if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+ {
+ limited_size = 32767u;
+ }
+ else
{
- if (handle->bitsPerFrame > 8)
+ limited_size = 511u;
+ }
+
+ if (handle->bitsPerFrame > 8)
+ {
+ if (transfer->dataSize > (limited_size << 1u))
{
- if (transfer->dataSize > 1022)
- {
- return kStatus_DSPI_OutOfRange;
- }
+ handle->state = kDSPI_Idle;
+ return kStatus_DSPI_OutOfRange;
}
- else
+ }
+ else
+ {
+ if (transfer->dataSize > limited_size)
{
- if (transfer->dataSize > 511)
- {
- return kStatus_DSPI_OutOfRange;
- }
+ handle->state = kDSPI_Idle;
+ return kStatus_DSPI_OutOfRange;
}
}
/*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */
if ((handle->bitsPerFrame > 8) && (transfer->dataSize & 0x1))
{
+ handle->state = kDSPI_Idle;
return kStatus_InvalidArgument;
}
EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiSlaveCallback, &s_dspiSlaveEdmaPrivateHandle[instance]);
- handle->state = kDSPI_Busy;
-
/* Store transfer information */
handle->txData = transfer->txData;
handle->rxData = transfer->rxData;
@@ -849,7 +1085,7 @@
handle->totalByteCount = transfer->dataSize;
uint16_t wordToSend = 0;
- uint8_t dummyData = DSPI_DUMMY_DATA;
+ uint8_t dummyData = s_dummyData[DSPI_GetInstance(base)];
uint8_t dataAlreadyFed = 0;
uint8_t dataFedMax = 2;
@@ -1003,11 +1239,11 @@
transferConfigC.srcOffset = 0;
if (handle->bitsPerFrame <= 8)
{
- handle->txBuffIfNull = DSPI_DUMMY_DATA;
+ handle->txBuffIfNull = dummyData;
}
else
{
- handle->txBuffIfNull = (DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA;
+ handle->txBuffIfNull = ((uint32_t)dummyData << 8) | dummyData;
}
}
@@ -1106,13 +1342,13 @@
DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
+ dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
+
if (dspiEdmaPrivateHandle->handle->callback)
{
dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle,
kStatus_Success, dspiEdmaPrivateHandle->handle->userData);
}
-
- dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
}
void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle)
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi_edma.h Thu Aug 03 13:13:39 2017 +0100 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi_edma.h Wed Aug 16 18:27:13 2017 +0100 @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * All rights reserved. + * Copyright 2016-2017 NXP * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -12,7 +12,7 @@ * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * o Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. *
Binary file targets/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/libexactLE.ar has changed
Binary file targets/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/libexactLE.a has changed
Binary file targets/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/libexactLE.a has changed
Binary file targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_ARM_STD/libexactLE.ar has changed
Binary file targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_GCC_ARM/libexactLE.a has changed
Binary file targets/TARGET_Maxim/TARGET_MAX32620/TOOLCHAIN_IAR/libexactLE.a has changed
--- a/targets/TARGET_Maxim/TARGET_MAX32620/sleep.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/sleep.c Wed Aug 16 18:27:13 2017 +0100
@@ -115,7 +115,7 @@
// Deep Sleep is not working properly on Revisions A3 and earlier
if (part_rev <= REVISION_A3) {
- sleep();
+ hal_sleep();
return;
}
@@ -128,7 +128,7 @@
// Do not enter Deep Sleep if connected to VBUS
if (MXC_USB->dev_intfl & MXC_F_USB_DEV_INTFL_VBUS_ST) {
__enable_irq();
- sleep();
+ hal_sleep();
return;
}
--- a/targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/PinNames.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/PinNames.h Wed Aug 16 18:27:13 2017 +0100
@@ -1,5 +1,5 @@
/*******************************************************************************
- * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ * Copyright (C) 2016-2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -144,6 +144,10 @@
OWM = P4_0,
// BTLE Module hardwired
+ BT_TX = P0_0,
+ BT_RX = P0_1,
+ BT_RTS = P0_2,
+ BT_CTS = P0_3,
BT_RST = P1_6,
BT_CLK = P1_7,
Binary file targets/TARGET_Maxim/TARGET_MAX32630/TOOLCHAIN_ARM_STD/libexactLE.ar has changed
Binary file targets/TARGET_Maxim/TARGET_MAX32630/TOOLCHAIN_GCC_ARM/libexactLE.a has changed
Binary file targets/TARGET_Maxim/TARGET_MAX32630/TOOLCHAIN_IAR/libexactLE.a has changed
--- a/targets/TARGET_Maxim/TARGET_MAX32630/gpio_api.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/gpio_api.c Wed Aug 16 18:27:13 2017 +0100
@@ -67,6 +67,13 @@
void gpio_mode(gpio_t *obj, PinMode mode)
{
+#ifdef OPEN_DRAIN_LEDS
+ if ((obj->name == LED1) || (obj->name == LED2) ||
+ (obj->name == LED3) || (obj->name == LED4)) {
+ mode = OpenDrain;
+ }
+#endif
+
obj->mode = mode;
pin_mode(obj->name, mode);
}
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/NCS36510.icf Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/NCS36510.icf Wed Aug 16 18:27:13 2017 +0100
@@ -1,49 +1,82 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_1.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00003000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x00003000; /* FLASHA program start*/
+define symbol __ICFEDIT_region_IROM1_end__ = 0x00051FFF; /* 316K = 320K - 4K(FIB table), FLASHA end */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x00102000;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x00151FFF; /* 320K */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
-/* The memory space denoting the maximum possible amount of addressable memory */
-define memory Mem with size = 4G;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x3FFFC000; /* RAMA start */
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x3FFFFFFF; /* RAMA end */
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x3FFF8000; /* RAMB start */
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x3FFFBFFF; /* RAMB end */
+define symbol __ICFEDIT_region_IRAM3_start__ = 0x3FFF4000; /* RAMC start */
+define symbol __ICFEDIT_region_IRAM3_end__ = 0x3FFF7FFF; /* RAMC end */
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
-/* Memory regions in an address space */
-define region FLASHA = Mem:[from 0x00003000 size 0x4D000]; /* 308K = 320K - 4K(FIB table) - 8K(Persistent) */
-define region FLASHB = Mem:[from 0x00100000 size 0x50000];
-define region RAMA = Mem:[from 0x3FFFC000 size 0x4000];
-define region RAMB = Mem:[from 0x3FFF8000 size 0x4000];
-/* G2H ZPRO requires RAMC to be enabled */
-define region RAMC = Mem:[from 0x3FFF4000 + 0x90 size 0x4000 - 0x90]; /* 8_byte_aligned(35 vectors * 4 bytes each) = 0x90 */
-define region RAM_ALL = Mem:[from 0x3FFF4000 + 0x90 size 0xC000 - 0x90]; /* 8_byte_aligned(35 vectors * 4 bytes each) = 0x90 */
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x200;
+define symbol __ICFEDIT_size_heap__ = 0x4000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region FLASH_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+ | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+
+define region RAM_VECTOR_region = mem:[from __ICFEDIT_region_IRAM3_start__ to __ICFEDIT_region_IRAM3_start__ + 0x90 - 1];
+
+define region RAM_region = mem:[from __ICFEDIT_region_IRAM3_start__ + 0x90 to __ICFEDIT_region_IRAM3_end__]
+ | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]
+ | mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__ - __ICFEDIT_size_cstack__ ];
+
+define region CSTACK_region = mem:[from __ICFEDIT_region_IRAM1_end__ - __ICFEDIT_size_cstack__ + 1 to __ICFEDIT_region_IRAM1_end__];
-/* Create a stack */
-define block CSTACK with size = 0x200, alignment = 8 { };
-/* No Heap is created for C library, all memory management should be handled by the application */
- define block HEAP with alignment = 8, size = 0x3000 { };
+/* Define overlays for MIB's, ths allows view of one MIB from a application level while
+ * MAC and PHY only know about their own MIB */
+define overlay MIBOVERLAY { section MIBSTARTSECTION };
+define overlay MIBOVERLAY { section MIBSECTION };
-/* Handle initialization */
-do not initialize { section .noinit };
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+define block RAM_VECTORS with alignment = 8, size = 0x90 { };
+
+initialize by copy { readwrite };
-/* Initialize RW sections, exclude zero-initialized sections */
-initialize by copy with packing = none { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
/* Initialize the code in RAM, copied over from FLASH */
initialize by copy with packing = none { readonly code section EXECINRAM };
-/*keep { readonly code section .EXECINRAM* } except { readonly code section EXECINRAM };*/
-/* Place startup code at a fixed address */
-place at start of FLASHA { readonly section .intvec, readonly section SWVERSION,readonly section FIBTABLE,readonly section .cstartup };
-
-/* Place code and data */
-
-/* Place constants and initializers in FLASHA: .rodata and .data_init */
-place in FLASHA { readonly };
-
-/* Place .data, .bss, and .noinit */
-/* and STACK */
-/* The relocatable exception table needs to be aligned at 0x0 or multiple of 0x100,
- * hence, place it as first block in RAM.
- */
-place at start of RAM_ALL { section RAM_VECTORS };
-place in RAM_ALL { readonly code section EXECINRAM };
-place at end of RAM_ALL { block CSTACK };
+/*initialize by copy { readwrite };*/
+do not initialize { section .noinit };
-place in RAM_ALL { readwrite };
-place in RAM_ALL { block HEAP };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec, readonly section SWVERSION, readonly section FIBTABLE };
+
+place in FLASH_region { readonly section .cstartup, readonly };
+
+place at start of RAM_VECTOR_region {block RAM_VECTORS};
+
+place in RAM_region { readwrite, block HEAP, section XHEAP, readonly code section EXECINRAM, overlay MIBOVERLAY, readwrite section MIBENDSECTION};
+
+place at end of CSTACK_region { block CSTACK };
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F0/analogin_api.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/analogin_api.c Wed Aug 16 18:27:13 2017 +0100
@@ -36,15 +36,13 @@
#include "PeripheralPins.h"
#include "mbed_error.h"
-ADC_HandleTypeDef AdcHandle;
-
int adc_inited = 0;
void analogin_init(analogin_t *obj, PinName pin) {
// Get the peripheral name from the pin and assign it to the object
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
- MBED_ASSERT(obj->adc != (ADCName)NC);
-
+ obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
+
// Get the functions (adc channel) from the pin and assign it to the object
uint32_t function = pinmap_function(pin, PinMap_ADC);
MBED_ASSERT(function != (uint32_t)NC);
@@ -67,25 +65,25 @@
__ADC1_CLK_ENABLE();
// Configure ADC
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
- AdcHandle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
- AdcHandle.Init.Resolution = ADC_RESOLUTION12b;
- AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
- AdcHandle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
- AdcHandle.Init.EOCSelection = EOC_SINGLE_CONV;
- AdcHandle.Init.LowPowerAutoWait = DISABLE;
- AdcHandle.Init.LowPowerAutoPowerOff = DISABLE;
- AdcHandle.Init.ContinuousConvMode = DISABLE;
- AdcHandle.Init.DiscontinuousConvMode = DISABLE;
- AdcHandle.Init.ExternalTrigConv = ADC_SOFTWARE_START;
- AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
- AdcHandle.Init.DMAContinuousRequests = DISABLE;
- AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN;
- if (HAL_ADC_Init(&AdcHandle) != HAL_OK) {
+ obj->handle.State = HAL_ADC_STATE_RESET;
+ obj->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
+ obj->handle.Init.Resolution = ADC_RESOLUTION12b;
+ obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ obj->handle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
+ obj->handle.Init.EOCSelection = EOC_SINGLE_CONV;
+ obj->handle.Init.LowPowerAutoWait = DISABLE;
+ obj->handle.Init.LowPowerAutoPowerOff = DISABLE;
+ obj->handle.Init.ContinuousConvMode = DISABLE;
+ obj->handle.Init.DiscontinuousConvMode = DISABLE;
+ obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ obj->handle.Init.DMAContinuousRequests = DISABLE;
+ obj->handle.Init.Overrun = OVR_DATA_OVERWRITTEN;
+ if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
error("Cannot initialize ADC");
}
// Run the ADC calibration
- if (HAL_ADCEx_Calibration_Start(&AdcHandle) != HAL_OK) {
+ if (HAL_ADCEx_Calibration_Start(&obj->handle) != HAL_OK) {
error("Cannot Start ADC_Calibration");
}
}
@@ -94,8 +92,6 @@
static inline uint16_t adc_read(analogin_t *obj) {
ADC_ChannelConfTypeDef sConfig;
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
// Configure ADC channel
sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
#if defined (TARGET_STM32F091RC)
@@ -169,15 +165,15 @@
}
// Clear all channels as it is not done in HAL_ADC_ConfigChannel()
- AdcHandle.Instance->CHSELR = 0;
+ obj->handle.Instance->CHSELR = 0;
- HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
+ HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
- HAL_ADC_Start(&AdcHandle); // Start conversion
+ HAL_ADC_Start(&obj->handle); // Start conversion
// Wait end of conversion and get value
- if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
- return (HAL_ADC_GetValue(&AdcHandle));
+ if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+ return (HAL_ADC_GetValue(&obj->handle));
} else {
return 0;
}
--- a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -111,6 +111,12 @@
#endif
};
+struct analogin_s {
+ ADC_HandleTypeDef handle;
+ PinName pin;
+ uint8_t channel;
+};
+
#include "gpio_object.h"
#if DEVICE_ANALOGOUT
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F1/analogin_api.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/analogin_api.c Wed Aug 16 18:27:13 2017 +0100
@@ -35,8 +35,6 @@
#include "pinmap.h"
#include "PeripheralPins.h"
-ADC_HandleTypeDef AdcHandle;
-
int adc_inited = 0;
void analogin_init(analogin_t *obj, PinName pin)
@@ -44,9 +42,9 @@
RCC_PeriphCLKInitTypeDef PeriphClkInit;
// Get the peripheral name from the pin and assign it to the object
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
- MBED_ASSERT(obj->adc != (ADCName)NC);
-
+ obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
+
// Get the functions (adc channel) from the pin and assign it to the object
uint32_t function = pinmap_function(pin, PinMap_ADC);
MBED_ASSERT(function != (uint32_t)NC);
@@ -79,15 +77,15 @@
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
// Configure ADC
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
- AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
- AdcHandle.Init.ScanConvMode = DISABLE;
- AdcHandle.Init.ContinuousConvMode = DISABLE;
- AdcHandle.Init.NbrOfConversion = 1;
- AdcHandle.Init.DiscontinuousConvMode = DISABLE;
- AdcHandle.Init.NbrOfDiscConversion = 0;
- AdcHandle.Init.ExternalTrigConv = ADC_SOFTWARE_START;
- HAL_ADC_Init(&AdcHandle);
+ obj->handle.State = HAL_ADC_STATE_RESET;
+ obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ obj->handle.Init.ScanConvMode = DISABLE;
+ obj->handle.Init.ContinuousConvMode = DISABLE;
+ obj->handle.Init.NbrOfConversion = 1;
+ obj->handle.Init.DiscontinuousConvMode = DISABLE;
+ obj->handle.Init.NbrOfDiscConversion = 0;
+ obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ HAL_ADC_Init(&obj->handle);
}
}
@@ -95,8 +93,6 @@
{
ADC_ChannelConfTypeDef sConfig;
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
// Configure ADC channel
sConfig.Rank = 1;
sConfig.SamplingTime = ADC_SAMPLETIME_7CYCLES_5;
@@ -160,13 +156,13 @@
return 0;
}
- HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
+ HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
- HAL_ADC_Start(&AdcHandle); // Start conversion
+ HAL_ADC_Start(&obj->handle); // Start conversion
// Wait end of conversion and get value
- if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
- return (HAL_ADC_GetValue(&AdcHandle));
+ if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+ return (HAL_ADC_GetValue(&obj->handle));
} else {
return 0;
}
--- a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -110,6 +110,12 @@
#endif
};
+struct analogin_s {
+ ADC_HandleTypeDef handle;
+ PinName pin;
+ uint8_t channel;
+};
+
#include "gpio_object.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F2/analogin_api.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/analogin_api.c Wed Aug 16 18:27:13 2017 +0100
@@ -36,12 +36,9 @@
#include "mbed_error.h"
#include "PeripheralPins.h"
-ADC_HandleTypeDef AdcHandle;
-
void analogin_init(analogin_t *obj, PinName pin)
{
uint32_t function = (uint32_t)NC;
- obj->adc = (ADCName)NC;
#if defined(ADC1)
static int adc1_inited = 0;
@@ -58,18 +55,18 @@
if ((pin < 0xF0) || (pin >= 0x100)) {
// Normal channels
// Get the peripheral name from the pin and assign it to the object
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+ obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
// Get the functions (adc channel) from the pin and assign it to the object
function = pinmap_function(pin, PinMap_ADC);
// Configure GPIO
pinmap_pinout(pin, PinMap_ADC);
} else {
// Internal channels
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC_Internal);
+ obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
function = pinmap_function(pin, PinMap_ADC_Internal);
// No GPIO configuration for internal channels
}
- MBED_ASSERT(obj->adc != (ADCName)NC);
+ MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
MBED_ASSERT(function != (uint32_t)NC);
obj->channel = STM_PIN_CHANNEL(function);
@@ -80,41 +77,41 @@
// Check if ADC is already initialized
// Enable ADC clock
#if defined(ADC1)
- if ((obj->adc == ADC_1) && adc1_inited) return;
- if (obj->adc == ADC_1) {
+ if (((ADCName)obj->handle.Instance == ADC_1) && adc1_inited) return;
+ if ((ADCName)obj->handle.Instance == ADC_1) {
__ADC1_CLK_ENABLE();
adc1_inited = 1;
}
#endif
#if defined(ADC2)
- if ((obj->adc == ADC_2) && adc2_inited) return;
- if (obj->adc == ADC_2) {
+ if (((ADCName)obj->handle.Instance == ADC_2) && adc2_inited) return;
+ if ((ADCName)obj->handle.Instance == ADC_2) {
__ADC2_CLK_ENABLE();
adc2_inited = 1;
}
#endif
#if defined(ADC3)
- if ((obj->adc == ADC_3) && adc3_inited) return;
- if (obj->adc == ADC_3) {
+ if (((ADCName)obj->handle.Instance == ADC_3) && adc3_inited) return;
+ if ((ADCName)obj->handle.Instance == ADC_3) {
__ADC3_CLK_ENABLE();
adc3_inited = 1;
}
#endif
// Configure ADC
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
- AdcHandle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2;
- AdcHandle.Init.Resolution = ADC_RESOLUTION12b;
- AdcHandle.Init.ScanConvMode = DISABLE;
- AdcHandle.Init.ContinuousConvMode = DISABLE;
- AdcHandle.Init.DiscontinuousConvMode = DISABLE;
- AdcHandle.Init.NbrOfDiscConversion = 0;
- AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
- AdcHandle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1;
- AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
- AdcHandle.Init.NbrOfConversion = 1;
- AdcHandle.Init.DMAContinuousRequests = DISABLE;
- AdcHandle.Init.EOCSelection = DISABLE;
- if (HAL_ADC_Init(&AdcHandle) != HAL_OK) {
+ obj->handle.State = HAL_ADC_STATE_RESET;
+ obj->handle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2;
+ obj->handle.Init.Resolution = ADC_RESOLUTION12b;
+ obj->handle.Init.ScanConvMode = DISABLE;
+ obj->handle.Init.ContinuousConvMode = DISABLE;
+ obj->handle.Init.DiscontinuousConvMode = DISABLE;
+ obj->handle.Init.NbrOfDiscConversion = 0;
+ obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1;
+ obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ obj->handle.Init.NbrOfConversion = 1;
+ obj->handle.Init.DMAContinuousRequests = DISABLE;
+ obj->handle.Init.EOCSelection = DISABLE;
+ if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
error("Cannot initialize ADC\n");
}
}
@@ -123,8 +120,6 @@
{
ADC_ChannelConfTypeDef sConfig = {0};
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
// Configure ADC channel
sConfig.Rank = 1;
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
@@ -192,13 +187,13 @@
return 0;
}
- HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
+ HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
- HAL_ADC_Start(&AdcHandle); // Start conversion
+ HAL_ADC_Start(&obj->handle); // Start conversion
// Wait end of conversion and get value
- if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
- return (HAL_ADC_GetValue(&AdcHandle));
+ if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+ return (HAL_ADC_GetValue(&obj->handle));
} else {
return 0;
}
--- a/targets/TARGET_STM/TARGET_STM32F2/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -55,7 +55,7 @@
};
struct analogin_s {
- ADCName adc;
+ ADC_HandleTypeDef handle;
PinName pin;
uint8_t channel;
};
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,13 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
- DAC_HandleTypeDef handle;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
#if defined (DEVICE_CAN)
struct can_s {
CANName can;
--- a/targets/TARGET_STM/TARGET_STM32F3/analogin_api.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/analogin_api.c Wed Aug 16 18:27:13 2017 +0100
@@ -36,7 +36,6 @@
#include "mbed_error.h"
#include "PeripheralPins.h"
-ADC_HandleTypeDef AdcHandle;
void analogin_init(analogin_t *obj, PinName pin)
{
@@ -54,8 +53,8 @@
#endif
// Get the peripheral name from the pin and assign it to the object
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
- MBED_ASSERT(obj->adc != (ADCName)NC);
+ obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
// Get the pin function and assign the used channel to the object
uint32_t function = pinmap_function(pin, PinMap_ADC);
@@ -74,56 +73,52 @@
// Check if ADC is already initialized
// Enable ADC clock
#if defined(ADC1)
- if ((obj->adc == ADC_1) && adc1_inited) return;
- if (obj->adc == ADC_1) {
- AdcHandle.State = HAL_ADC_STATE_RESET;
+ if (((ADCName)obj->handle.Instance == ADC_1) && adc1_inited) return;
+ if ((ADCName)obj->handle.Instance == ADC_1) {
__ADC1_CLK_ENABLE();
adc1_inited = 1;
}
#endif
#if defined(ADC2)
- if ((obj->adc == ADC_2) && adc2_inited) return;
- if (obj->adc == ADC_2) {
- AdcHandle.State = HAL_ADC_STATE_RESET;
+ if (((ADCName)obj->handle.Instance == ADC_2) && adc2_inited) return;
+ if ((ADCName)obj->handle.Instance == ADC_2) {
__ADC2_CLK_ENABLE();
adc2_inited = 1;
}
#endif
#if defined(ADC3)
- if ((obj->adc == ADC_3) && adc3_inited) return;
- if (obj->adc == ADC_3) {
- AdcHandle.State = HAL_ADC_STATE_RESET;
+ if (((ADCName)obj->handle.Instance == ADC_3) && adc3_inited) return;
+ if ((ADCName)obj->handle.Instance == ADC_3) {
__ADC34_CLK_ENABLE();
adc3_inited = 1;
}
#endif
#if defined(ADC4)
- if ((obj->adc == ADC_4) && adc4_inited) return;
- if (obj->adc == ADC_4) {
- AdcHandle.State = HAL_ADC_STATE_RESET;
+ if (((ADCName)obj->handle.Instance == ADC_4) && adc4_inited) return;
+ if ((ADCName)obj->handle.Instance == ADC_4) {
__ADC34_CLK_ENABLE();
adc4_inited = 1;
}
#endif
// Configure ADC
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
- AdcHandle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2;
- AdcHandle.Init.Resolution = ADC_RESOLUTION12b;
- AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
- AdcHandle.Init.ScanConvMode = DISABLE;
- AdcHandle.Init.EOCSelection = EOC_SINGLE_CONV;
- AdcHandle.Init.LowPowerAutoWait = DISABLE;
- AdcHandle.Init.ContinuousConvMode = DISABLE;
- AdcHandle.Init.NbrOfConversion = 1;
- AdcHandle.Init.DiscontinuousConvMode = DISABLE;
- AdcHandle.Init.NbrOfDiscConversion = 0;
- AdcHandle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1;
- AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
- AdcHandle.Init.DMAContinuousRequests = DISABLE;
- AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN;
+ obj->handle.State = HAL_ADC_STATE_RESET;
+ obj->handle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2;
+ obj->handle.Init.Resolution = ADC_RESOLUTION12b;
+ obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ obj->handle.Init.ScanConvMode = DISABLE;
+ obj->handle.Init.EOCSelection = EOC_SINGLE_CONV;
+ obj->handle.Init.LowPowerAutoWait = DISABLE;
+ obj->handle.Init.ContinuousConvMode = DISABLE;
+ obj->handle.Init.NbrOfConversion = 1;
+ obj->handle.Init.DiscontinuousConvMode = DISABLE;
+ obj->handle.Init.NbrOfDiscConversion = 0;
+ obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1;
+ obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ obj->handle.Init.DMAContinuousRequests = DISABLE;
+ obj->handle.Init.Overrun = OVR_DATA_OVERWRITTEN;
- if (HAL_ADC_Init(&AdcHandle) != HAL_OK) {
+ if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
error("Cannot initialize ADC");
}
}
@@ -132,8 +127,6 @@
{
ADC_ChannelConfTypeDef sConfig = {0};
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
// Configure ADC channel
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_19CYCLES_5;
@@ -200,13 +193,13 @@
return 0;
}
- HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
+ HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
- HAL_ADC_Start(&AdcHandle); // Start conversion
+ HAL_ADC_Start(&obj->handle); // Start conversion
// Wait end of conversion and get value
- if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
- return (HAL_ADC_GetValue(&AdcHandle));
+ if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+ return (HAL_ADC_GetValue(&obj->handle));
} else {
return 0;
}
--- a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -118,6 +118,12 @@
DAC_HandleTypeDef handle;
};
+struct analogin_s {
+ ADC_HandleTypeDef handle;
+ PinName pin;
+ uint8_t channel;
+};
+
#include "gpio_object.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c Wed Aug 16 18:27:13 2017 +0100
@@ -30,6 +30,7 @@
**/
#include "stm32f4xx.h"
+#include "nvic_addr.h"
#include "mbed_assert.h"
/*!< Uncomment the following line if you need to relocate your vector Table in
@@ -92,7 +93,7 @@
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
#endif
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_MICRO/stm32f412xg.sct Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_MICRO/stm32f412xg.sct Wed Aug 16 18:27:13 2017 +0100
@@ -1,6 +1,7 @@
+#! armcc -E
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2016, STMicroelectronics
+; Copyright (c) 2017, STMicroelectronics
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
@@ -27,10 +28,18 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x100000
+#endif
+
; STM32F412ZG: 1024 KB FLASH (0x100000) + 256 KB SRAM (0x40000)
-LR_IROM1 0x08000000 0x100000 { ; load region size_region
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
- ER_IROM1 0x08000000 0x100000 { ; load address = execution address
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_STD/stm32f412xg.sct Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_STD/stm32f412xg.sct Wed Aug 16 18:27:13 2017 +0100
@@ -1,6 +1,7 @@
+#! armcc -E
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2016, STMicroelectronics
+; Copyright (c) 2017, STMicroelectronics
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
@@ -27,10 +28,18 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x100000
+#endif
+
; STM32F412ZG: 1024 KB FLASH (0x100000) + 256 KB SRAM (0x40000)
-LR_IROM1 0x08000000 0x100000 { ; load region size_region
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
- ER_IROM1 0x08000000 0x100000 { ; load address = execution address
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/STM32F412xG.ld Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/STM32F412xG.ld Wed Aug 16 18:27:13 2017 +0100
@@ -1,7 +1,14 @@
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 1024K
+#endif
/* Linker script to configure memory regions. */
MEMORY
{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
RAM (rwx) : ORIGIN = 0x200001C4, LENGTH = 256K - 0x1C4
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf Wed Aug 16 18:27:13 2017 +0100
@@ -1,7 +1,10 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
+
/* [ROM = 1024kb = 0x100000] */
-define symbol __intvec_start__ = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__ = 0x080FFFFF;
+define symbol __intvec_start__ = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE;
/* [RAM = 256kb = 0x40000] Vector table dynamic copy: 113 vectors = 452 bytes (0x1C4) to be reserved in RAM */
define symbol __NVIC_start__ = 0x20000000;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/flash_data.h Wed Aug 16 18:27:13 2017 +0100 @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Flash size */ +#define FLASH_SIZE (uint32_t) 0x100000 + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ + +#endif +#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -40,12 +40,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -40,12 +40,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/flash_api.c Thu Aug 03 13:13:39 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,191 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2017, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#include "flash_api.h"
-#include "flash_data.h"
-#include "platform/mbed_critical.h"
-
-// This file is automatically generated
-
-#if DEVICE_FLASH
-
-#if defined (STM32F429xx) || defined (STM32F439xx)
-#define FLASH_SIZE (uint32_t) 0x200000
-#endif
-
-static uint32_t GetSector(uint32_t Address);
-static uint32_t GetSectorSize(uint32_t Sector);
-
-int32_t flash_init(flash_t *obj)
-{
- /* Allow Access to Flash control registers and user Falsh */
- if (HAL_FLASH_Unlock()) {
- return -1;
- } else {
- return 0;
- }
-}
-int32_t flash_free(flash_t *obj)
-{
- /* Disable the Flash option control register access (recommended to protect
- the option Bytes against possible unwanted operations) */
- if (HAL_FLASH_Lock()) {
- return -1;
- } else {
- return 0;
- }
-}
-int32_t flash_erase_sector(flash_t *obj, uint32_t address)
-{
- /*Variable used for Erase procedure*/
- static FLASH_EraseInitTypeDef EraseInitStruct;
- uint32_t FirstSector;
- uint32_t SectorError = 0;
-
- if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
-
- return -1;
- }
-
- /* Get the 1st sector to erase */
- FirstSector = GetSector(address);
-
- /* Fill EraseInit structure*/
- EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS;
- EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3;
- EraseInitStruct.Sector = FirstSector;
- EraseInitStruct.NbSectors = 1;
- if(HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK){
- return -1;
- } else {
- return 0;
- }
-}
-
-int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
-{
-
- if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
- return -1;
- }
-
- /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
- you have to make sure that these data are rewritten before they are accessed during code
- execution. If this cannot be done safely, it is recommended to flush the caches by setting the
- DCRST and ICRST bits in the FLASH_CR register. */
- __HAL_FLASH_DATA_CACHE_DISABLE();
- __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
-
- __HAL_FLASH_DATA_CACHE_RESET();
- __HAL_FLASH_INSTRUCTION_CACHE_RESET();
-
- __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
- __HAL_FLASH_DATA_CACHE_ENABLE();
-
- while (size > 0) {
- if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, address, (uint64_t)*data) != HAL_OK) {
- return -1;
- } else {
- size--;
- address++;
- data++;
- }
- }
- return 0;
-}
-
-uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
-{
-
- if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
- return MBED_FLASH_INVALID_SIZE;
- }
-
- return (GetSectorSize(GetSector(address)));
-}
-
-uint32_t flash_get_page_size(const flash_t *obj)
-{
- // not applicable for STM32F4
- return (0x4000); // minimum sector size
-}
-uint32_t flash_get_start_address(const flash_t *obj)
-{
- return FLASH_BASE;
-}
-uint32_t flash_get_size(const flash_t *obj)
-{
- return FLASH_SIZE;
-}
-
-/**
- * @brief Gets the sector of a given address
- * @param None
- * @retval The sector of a given address
- */
-static uint32_t GetSector(uint32_t address)
-{
- uint32_t sector = 0;
- uint32_t tmp = address - ADDR_FLASH_SECTOR_0;
- if (address & 0x100000) { // handle 2nd bank
- sector = FLASH_SECTOR_12;
- tmp = address - ADDR_FLASH_SECTOR_12;
- }
- if (address < ADDR_FLASH_SECTOR_4) { // 16k sectorsize
- sector += tmp >>14;
- } else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size
- sector += FLASH_SECTOR_4;
- } else {
- sector += 4 + (tmp >>17);
- }
- return sector;
-}
-
-/**
- * @brief Gets sector Size
- * @param None
- * @retval The size of a given sector
- */
-static uint32_t GetSectorSize(uint32_t Sector)
-{
- uint32_t sectorsize = 0x00;
- if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\
- (Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) ||\
- (Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) {
- sectorsize = 16 * 1024;
- } else if((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) {
- sectorsize = 64 * 1024;
- } else {
- sectorsize = 128 * 1024;
- }
- return sectorsize;
-}
-
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/flash_data.h Thu Aug 03 13:13:39 2017 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/flash_data.h Wed Aug 16 18:27:13 2017 +0100 @@ -38,6 +38,9 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ +/* FLASH SIZE */ +#define FLASH_SIZE (uint32_t) 0x200000 + /* Base address of the Flash sectors Bank 1 */ #define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ #define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/system_clock.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/system_clock.c Wed Aug 16 18:27:13 2017 +0100
@@ -34,6 +34,7 @@
#include "ublox_low_level_api.h"
#include "stm32f4xx.h"
+#include "nvic_addr.h"
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
@@ -89,7 +90,7 @@
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+ SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
ublox_board_init();
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_ARM_STD/stm32f437xx.sct Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_ARM_STD/stm32f437xx.sct Wed Aug 16 18:27:13 2017 +0100
@@ -29,9 +29,18 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; 1 MB FLASH (0x100000) + 192 KB SRAM (0x30000) + 64 KB CCBRAM (0x10000)+ 4 KB BKPSRAM
-LR_IROM1 0x08000000 0x100000 { ; load region size_region
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
- ER_IROM1 0x08000000 0x100000 { ; load address = execution address
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x100000
+#endif
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/STM32F437xx.ld Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/STM32F437xx.ld Wed Aug 16 18:27:13 2017 +0100
@@ -1,10 +1,18 @@
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 1024k
+#endif
+
/* Linker script to configure memory regions. */
MEMORY
{
RAM (xrw) : ORIGIN = 0x200001AC, LENGTH = 192K - 0x1AC /* 0x1AC is to leave room for vectors */
CCM_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K
BACKUP_SRAM (rw) : ORIGIN = 0x40024000, LENGTH = 4096
-FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
}
/* Linker script to place sections and symbol values. Should be used together
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_IAR/stm32f437xx.icf Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_IAR/stm32f437xx.icf Wed Aug 16 18:27:13 2017 +0100
@@ -1,11 +1,13 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
+define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000;
define symbol __ICFEDIT_region_NVIC_end__ = 0x200001AF;
define symbol __ICFEDIT_region_RAM_start__ = 0x200001B0;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/flash_data.h Wed Aug 16 18:27:13 2017 +0100 @@ -0,0 +1,60 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include <stdint.h> + +#if DEVICE_FLASH + +#if defined (STM32F427xx) || defined (STM32F437xx) +#define FLASH_SIZE (uint32_t) 0x100000 +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Base address of the Flash sectors */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ + +#endif +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/nvic_addr.h Wed Aug 16 18:27:13 2017 +0100
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef NVIC_ADDR_H
+#define NVIC_ADDR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__ICCARM__)
+ #pragma section=".intvec"
+ #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
+#elif defined(__CC_ARM)
+ extern uint32_t Load$$LR$$LR_IROM1$$Base[];
+ #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
+#elif defined(__GNUC__)
+ extern uint32_t g_pfnVectors[];
+ #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)g_pfnVectors)
+#else
+ #error "Flash vector address not set for this toolchain"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/flash_api.c Thu Aug 03 13:13:39 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,192 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2017, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#include "flash_api.h"
-#include "flash_data.h"
-#include "platform/mbed_critical.h"
-
-// This file is automatically generated
-
-#if DEVICE_FLASH
-
-#if defined (STM32F429xx) || defined (STM32F439xx)
-#define FLASH_SIZE (uint32_t) 0x200000
-#endif
-
-static uint32_t GetSector(uint32_t Address);
-static uint32_t GetSectorSize(uint32_t Sector);
-
-int32_t flash_init(flash_t *obj)
-{
- /* Allow Access to Flash control registers and user Falsh */
- if (HAL_FLASH_Unlock()) {
- return -1;
- } else {
- return 0;
- }
-}
-int32_t flash_free(flash_t *obj)
-{
- /* Disable the Flash option control register access (recommended to protect
- the option Bytes against possible unwanted operations) */
- if (HAL_FLASH_Lock()) {
- return -1;
- } else {
- return 0;
- }
-}
-int32_t flash_erase_sector(flash_t *obj, uint32_t address)
-{
- /*Variable used for Erase procedure*/
- static FLASH_EraseInitTypeDef EraseInitStruct;
- uint32_t FirstSector;
- uint32_t SectorError = 0;
-
- if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
-
- return -1;
- }
-
- /* Get the 1st sector to erase */
- FirstSector = GetSector(address);
-
- /* Fill EraseInit structure*/
- EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS;
- EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3;
- EraseInitStruct.Sector = FirstSector;
- EraseInitStruct.NbSectors = 1;
- if(HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK){
- return -1;
- } else {
- return 0;
- }
-}
-
-int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
-{
-
- if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
- return -1;
- }
-
- /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
- you have to make sure that these data are rewritten before they are accessed during code
- execution. If this cannot be done safely, it is recommended to flush the caches by setting the
- DCRST and ICRST bits in the FLASH_CR register. */
- __HAL_FLASH_DATA_CACHE_DISABLE();
- __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
-
- __HAL_FLASH_DATA_CACHE_RESET();
- __HAL_FLASH_INSTRUCTION_CACHE_RESET();
-
- __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
- __HAL_FLASH_DATA_CACHE_ENABLE();
-
- while (size > 0) {
- if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, address, (uint64_t)*data) != HAL_OK) {
- return -1;
- } else {
- size--;
- address++;
- data++;
- }
- }
- return 0;
-}
-
-uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
-{
-
- if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
- return MBED_FLASH_INVALID_SIZE;
- }
-
- return (GetSectorSize(GetSector(address)));
-}
-
-uint32_t flash_get_page_size(const flash_t *obj)
-{
- // not applicable for STM32F4
- return (0x4000); // minimum sector size
-}
-uint32_t flash_get_start_address(const flash_t *obj)
-{
- return FLASH_BASE;
-}
-uint32_t flash_get_size(const flash_t *obj)
-{
- return FLASH_SIZE;
-}
-
-/**
- * @brief Gets the sector of a given address
- * @param None
- * @retval The sector of a given address
- */
-static uint32_t GetSector(uint32_t address)
-{
- uint32_t sector = 0;
- uint32_t tmp = address - ADDR_FLASH_SECTOR_0;
- if (address & 0x100000) { // handle 2nd bank
- sector = FLASH_SECTOR_12;
- tmp = address - ADDR_FLASH_SECTOR_12;
- }
- if (address < ADDR_FLASH_SECTOR_4) { // 16k sectorsize
- //printf("tmp for sectors less than 4: 0X%4x")
- sector += tmp >>14;
- } else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size
- sector += FLASH_SECTOR_4;
- } else {
- sector += 4 + (tmp >>17);
- }
- return sector;
-}
-
-/**
- * @brief Gets sector Size
- * @param None
- * @retval The size of a given sector
- */
-static uint32_t GetSectorSize(uint32_t Sector)
-{
- uint32_t sectorsize = 0x00;
- if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\
- (Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) ||\
- (Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) {
- sectorsize = 16 * 1024;
- } else if((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)){
- sectorsize = 64 * 1024;
- } else {
- sectorsize = 128 * 1024;
- }
- return sectorsize;
-}
-
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/flash_data.h Thu Aug 03 13:13:39 2017 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/flash_data.h Wed Aug 16 18:27:13 2017 +0100 @@ -38,6 +38,9 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ +/* Flash Size */ +#define FLASH_SIZE (uint32_t) 0x200000 + /* Base address of the Flash sectors Bank 1 */ #define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ #define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F4/analogin_api.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/analogin_api.c Wed Aug 16 18:27:13 2017 +0100
@@ -36,12 +36,9 @@
#include "mbed_error.h"
#include "PeripheralPins.h"
-ADC_HandleTypeDef AdcHandle;
-
void analogin_init(analogin_t *obj, PinName pin)
{
uint32_t function = (uint32_t)NC;
- obj->adc = (ADCName)NC;
#if defined(ADC1)
static int adc1_inited = 0;
@@ -58,18 +55,18 @@
if (pin < 0xF0) {
// Normal channels
// Get the peripheral name from the pin and assign it to the object
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+ obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
// Get the functions (adc channel) from the pin and assign it to the object
function = pinmap_function(pin, PinMap_ADC);
// Configure GPIO
pinmap_pinout(pin, PinMap_ADC);
} else {
// Internal channels
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC_Internal);
+ obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
function = pinmap_function(pin, PinMap_ADC_Internal);
// No GPIO configuration for internal channels
}
- MBED_ASSERT(obj->adc != (ADCName)NC);
+ MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
MBED_ASSERT(function != (uint32_t)NC);
obj->channel = STM_PIN_CHANNEL(function);
@@ -80,42 +77,42 @@
// Check if ADC is already initialized
// Enable ADC clock
#if defined(ADC1)
- if ((obj->adc == ADC_1) && adc1_inited) return;
- if (obj->adc == ADC_1) {
+ if (((ADCName)obj->handle.Instance == ADC_1) && adc1_inited) return;
+ if ((ADCName)obj->handle.Instance == ADC_1) {
__HAL_RCC_ADC1_CLK_ENABLE();
adc1_inited = 1;
}
#endif
#if defined(ADC2)
- if ((obj->adc == ADC_2) && adc2_inited) return;
- if (obj->adc == ADC_2) {
+ if (((ADCName)obj->handle.Instance == ADC_2) && adc2_inited) return;
+ if ((ADCName)obj->handle.Instance == ADC_2) {
__HAL_RCC_ADC2_CLK_ENABLE();
adc2_inited = 1;
}
#endif
#if defined(ADC3)
- if ((obj->adc == ADC_3) && adc3_inited) return;
- if (obj->adc == ADC_3) {
+ if (((ADCName)obj->handle.Instance == ADC_3) && adc3_inited) return;
+ if ((ADCName)obj->handle.Instance == ADC_3) {
__HAL_RCC_ADC3_CLK_ENABLE();
adc3_inited = 1;
}
#endif
// Configure ADC
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
- AdcHandle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
- AdcHandle.Init.Resolution = ADC_RESOLUTION_12B;
- AdcHandle.Init.ScanConvMode = DISABLE;
- AdcHandle.Init.ContinuousConvMode = DISABLE;
- AdcHandle.Init.DiscontinuousConvMode = DISABLE;
- AdcHandle.Init.NbrOfDiscConversion = 0;
- AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
- AdcHandle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1;
- AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
- AdcHandle.Init.NbrOfConversion = 1;
- AdcHandle.Init.DMAContinuousRequests = DISABLE;
- AdcHandle.Init.EOCSelection = DISABLE;
+ obj->handle.State = HAL_ADC_STATE_RESET;
+ obj->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
+ obj->handle.Init.Resolution = ADC_RESOLUTION_12B;
+ obj->handle.Init.ScanConvMode = DISABLE;
+ obj->handle.Init.ContinuousConvMode = DISABLE;
+ obj->handle.Init.DiscontinuousConvMode = DISABLE;
+ obj->handle.Init.NbrOfDiscConversion = 0;
+ obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1;
+ obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ obj->handle.Init.NbrOfConversion = 1;
+ obj->handle.Init.DMAContinuousRequests = DISABLE;
+ obj->handle.Init.EOCSelection = DISABLE;
- if (HAL_ADC_Init(&AdcHandle) != HAL_OK) {
+ if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
error("Cannot initialize ADC\n");
}
}
@@ -124,8 +121,6 @@
{
ADC_ChannelConfTypeDef sConfig = {0};
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
// Configure ADC channel
sConfig.Rank = 1;
sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES;
@@ -202,13 +197,13 @@
// so VBAT readings are returned in place of temperature.
ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE);
- HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
+ HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
- HAL_ADC_Start(&AdcHandle); // Start conversion
+ HAL_ADC_Start(&obj->handle); // Start conversion
// Wait end of conversion and get value
- if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
- return (uint16_t)HAL_ADC_GetValue(&AdcHandle);
+ if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+ return (uint16_t)HAL_ADC_GetValue(&obj->handle);
} else {
return 0;
}
--- a/targets/TARGET_STM/TARGET_STM32F4/common_objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/common_objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -109,11 +109,19 @@
uint8_t available_events;
#endif
};
+
#if DEVICE_FLASH
struct flash_s {
uint32_t dummy;
};
#endif
+
+struct analogin_s {
+ ADC_HandleTypeDef handle;
+ PinName pin;
+ uint8_t channel;
+};
+
#define GPIO_IP_WITHOUT_BRR
#include "gpio_object.h"
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.c Wed Aug 16 18:27:13 2017 +0100
@@ -1316,7 +1316,7 @@
hmmc->State = HAL_MMC_STATE_BUSY;
/* Check if the card command class supports erase command */
- if((hmmc->MmcCard.Class) & SDIO_CCCC_ERASE == 0U)
+ if(((hmmc->MmcCard.Class) & SDIO_CCCC_ERASE) == 0U)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c Wed Aug 16 18:27:13 2017 +0100
@@ -0,0 +1,197 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#if DEVICE_FLASH
+#include "flash_api.h"
+#include "flash_data.h"
+#include "platform/mbed_critical.h"
+
+// This file is automatically generated
+
+
+static uint32_t GetSector(uint32_t Address);
+static uint32_t GetSectorSize(uint32_t Sector);
+
+int32_t flash_init(flash_t *obj)
+{
+ /* Allow Access to Flash control registers and user Falsh */
+ if (HAL_FLASH_Unlock()) {
+ return -1;
+ } else {
+ return 0;
+ }
+}
+int32_t flash_free(flash_t *obj)
+{
+ /* Disable the Flash option control register access (recommended to protect
+ the option Bytes against possible unwanted operations) */
+ if (HAL_FLASH_Lock()) {
+ return -1;
+ } else {
+ return 0;
+ }
+}
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+ /*Variable used for Erase procedure*/
+ static FLASH_EraseInitTypeDef EraseInitStruct;
+ uint32_t FirstSector;
+ uint32_t SectorError = 0;
+
+ if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+
+ return -1;
+ }
+
+ /* Get the 1st sector to erase */
+ FirstSector = GetSector(address);
+
+ /* Fill EraseInit structure*/
+ EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS;
+ EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3;
+ EraseInitStruct.Sector = FirstSector;
+ EraseInitStruct.NbSectors = 1;
+ if(HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK){
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+
+ if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+ return -1;
+ }
+
+ /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
+ you have to make sure that these data are rewritten before they are accessed during code
+ execution. If this cannot be done safely, it is recommended to flush the caches by setting the
+ DCRST and ICRST bits in the FLASH_CR register. */
+ __HAL_FLASH_DATA_CACHE_DISABLE();
+ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+
+ __HAL_FLASH_DATA_CACHE_RESET();
+ __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+
+ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+ __HAL_FLASH_DATA_CACHE_ENABLE();
+
+ while (size > 0) {
+ if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, address, (uint64_t)*data) != HAL_OK) {
+ return -1;
+ } else {
+ size--;
+ address++;
+ data++;
+ }
+ }
+ return 0;
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+
+ if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+ return MBED_FLASH_INVALID_SIZE;
+ }
+
+ return (GetSectorSize(GetSector(address)));
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+ // not applicable for STM32F4
+ return (0x4000); // minimum sector size
+}
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+ return FLASH_BASE;
+}
+uint32_t flash_get_size(const flash_t *obj)
+{
+ return FLASH_SIZE;
+}
+
+/**
+ * @brief Gets the sector of a given address
+ * @param None
+ * @retval The sector of a given address
+ */
+static uint32_t GetSector(uint32_t address)
+{
+ uint32_t sector = 0;
+ uint32_t tmp = address - ADDR_FLASH_SECTOR_0;
+ /* This function supports 1Mb and 2Mb flash sizes */
+#if defined(ADDR_FLASH_SECTOR_12)
+ if (address & 0x100000) { // handle 2nd bank
+ sector = FLASH_SECTOR_12;
+ tmp = address - ADDR_FLASH_SECTOR_12;
+ }
+#endif
+ if (address < ADDR_FLASH_SECTOR_4) { // 16k sectorsize
+ sector += tmp >>14;
+ } else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size
+ sector += FLASH_SECTOR_4;
+ } else {
+ sector += 4 + (tmp >>17);
+ }
+ return sector;
+}
+
+/**
+ * @brief Gets sector Size
+ * @param None
+ * @retval The size of a given sector
+ */
+static uint32_t GetSectorSize(uint32_t Sector)
+{
+ uint32_t sectorsize = 0x00;
+#if defined(FLASH_SECTOR_12)
+ if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\
+ (Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) ||\
+ (Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) {
+ sectorsize = 16 * 1024;
+ } else if((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) {
+#else
+if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\
+ (Sector == FLASH_SECTOR_3)) {
+ sectorsize = 16 * 1024;
+ } else if(Sector == FLASH_SECTOR_4) {
+#endif
+ sectorsize = 64 * 1024;
+ } else {
+ sectorsize = 128 * 1024;
+ }
+ return sectorsize;
+}
+
+#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint8_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32F7/analogin_api.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/analogin_api.c Wed Aug 16 18:27:13 2017 +0100
@@ -36,12 +36,9 @@
#include "PeripheralPins.h"
#include "mbed_error.h"
-ADC_HandleTypeDef AdcHandle;
-
void analogin_init(analogin_t *obj, PinName pin)
{
uint32_t function = (uint32_t)NC;
- obj->adc = (ADCName)NC;
#if defined(ADC1)
static int adc1_inited = 0;
@@ -58,18 +55,17 @@
if (pin < 0xF0) {
// Normal channels
// Get the peripheral name from the pin and assign it to the object
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
- // Get the functions (adc channel) from the pin and assign it to the object
+ obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
function = pinmap_function(pin, PinMap_ADC);
// Configure GPIO
pinmap_pinout(pin, PinMap_ADC);
} else {
// Internal channels
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC_Internal);
+ obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
function = pinmap_function(pin, PinMap_ADC_Internal);
// No GPIO configuration for internal channels
}
- MBED_ASSERT(obj->adc != (ADCName)NC);
+ MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
MBED_ASSERT(function != (uint32_t)NC);
obj->channel = STM_PIN_CHANNEL(function);
@@ -80,43 +76,43 @@
// Check if ADC is already initialized
// Enable ADC clock
#if defined(ADC1)
- if ((obj->adc == ADC_1) && adc1_inited) return;
- if (obj->adc == ADC_1) {
+ if (((ADCName)obj->handle.Instance == ADC_1) && adc1_inited) return;
+ if ((ADCName)obj->handle.Instance == ADC_1) {
__HAL_RCC_ADC1_CLK_ENABLE();
adc1_inited = 1;
}
#endif
#if defined(ADC2)
- if ((obj->adc == ADC_2) && adc2_inited) return;
- if (obj->adc == ADC_2) {
+ if (((ADCName)obj->handle.Instance == ADC_2) && adc2_inited) return;
+ if ((ADCName)obj->handle.Instance == ADC_2) {
__HAL_RCC_ADC2_CLK_ENABLE();
adc2_inited = 1;
}
#endif
#if defined(ADC3)
- if ((obj->adc == ADC_3) && adc3_inited) return;
- if (obj->adc == ADC_3) {
+ if (((ADCName)obj->handle.Instance == ADC_3) && adc3_inited) return;
+ if ((ADCName)obj->handle.Instance == ADC_3) {
__HAL_RCC_ADC3_CLK_ENABLE();
adc3_inited = 1;
}
#endif
// Configure ADC
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
- AdcHandle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV4;
- AdcHandle.Init.Resolution = ADC_RESOLUTION_12B;
- AdcHandle.Init.ScanConvMode = DISABLE;
- AdcHandle.Init.ContinuousConvMode = DISABLE;
- AdcHandle.Init.DiscontinuousConvMode = DISABLE;
- AdcHandle.Init.NbrOfDiscConversion = 0;
- AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
- AdcHandle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1;
- AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
- AdcHandle.Init.NbrOfConversion = 1;
- AdcHandle.Init.DMAContinuousRequests = DISABLE;
- AdcHandle.Init.EOCSelection = DISABLE;
+ obj->handle.State = HAL_ADC_STATE_RESET;
+ obj->handle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV4;
+ obj->handle.Init.Resolution = ADC_RESOLUTION_12B;
+ obj->handle.Init.ScanConvMode = DISABLE;
+ obj->handle.Init.ContinuousConvMode = DISABLE;
+ obj->handle.Init.DiscontinuousConvMode = DISABLE;
+ obj->handle.Init.NbrOfDiscConversion = 0;
+ obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1;
+ obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ obj->handle.Init.NbrOfConversion = 1;
+ obj->handle.Init.DMAContinuousRequests = DISABLE;
+ obj->handle.Init.EOCSelection = DISABLE;
- if (HAL_ADC_Init(&AdcHandle) != HAL_OK) {
+ if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
error("Cannot initialize ADC");
}
}
@@ -125,8 +121,6 @@
{
ADC_ChannelConfTypeDef sConfig = {0};
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
// Configure ADC channel
sConfig.Rank = 1;
sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES;
@@ -194,16 +188,16 @@
return 0;
}
- if (HAL_ADC_ConfigChannel(&AdcHandle, &sConfig) != HAL_OK) {
+ if (HAL_ADC_ConfigChannel(&obj->handle, &sConfig) != HAL_OK) {
error("Cannot configure ADC channel");
}
- HAL_ADC_Start(&AdcHandle); // Start conversion
+ HAL_ADC_Start(&obj->handle); // Start conversion
// Wait end of conversion and get value
- HAL_ADC_PollForConversion(&AdcHandle, 10);
- if (HAL_ADC_GetState(&AdcHandle) & HAL_ADC_STATE_EOC_REG) {
- return (HAL_ADC_GetValue(&AdcHandle));
+ HAL_ADC_PollForConversion(&obj->handle, 10);
+ if (HAL_ADC_GetState(&obj->handle) & HAL_ADC_STATE_EOC_REG) {
+ return (HAL_ADC_GetValue(&obj->handle));
} else {
return 0;
}
--- a/targets/TARGET_STM/TARGET_STM32F7/common_objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/common_objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -111,6 +111,12 @@
#endif
};
+struct analogin_s {
+ ADC_HandleTypeDef handle;
+ PinName pin;
+ uint8_t channel;
+};
+
#define GPIO_IP_WITHOUT_BRR
#include "gpio_object.h"
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
struct trng_s {
RNG_HandleTypeDef handle;
};
--- a/targets/TARGET_STM/TARGET_STM32L0/analogin_api.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/analogin_api.c Wed Aug 16 18:27:13 2017 +0100
@@ -36,14 +36,12 @@
#include "mbed_error.h"
#include "PeripheralPins.h"
-ADC_HandleTypeDef AdcHandle;
-
int adc_inited = 0;
void analogin_init(analogin_t *obj, PinName pin)
{
uint32_t function = (uint32_t)NC;
- obj->adc = (ADCName)NC;
+ obj->handle.Instance = (ADC_TypeDef *)NC;
// ADC Internal Channels "pins" (Temperature, Vref, Vbat, ...)
// are described in PinNames.h and PeripheralPins.c
@@ -51,18 +49,18 @@
if (pin < 0xF0) {
// Normal channels
// Get the peripheral name from the pin and assign it to the object
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+ obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);
// Get the functions (adc channel) from the pin and assign it to the object
function = pinmap_function(pin, PinMap_ADC);
// Configure GPIO
pinmap_pinout(pin, PinMap_ADC);
} else {
// Internal channels
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC_Internal);
+ obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal);
function = pinmap_function(pin, PinMap_ADC_Internal);
// No GPIO configuration for internal channels
}
- MBED_ASSERT(obj->adc != (ADCName)NC);
+ MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
MBED_ASSERT(function != (uint32_t)NC);
obj->channel = STM_PIN_CHANNEL(function);
@@ -74,37 +72,36 @@
if (adc_inited == 0) {
adc_inited = 1;
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
+ obj->handle.State = HAL_ADC_STATE_RESET;
// Enable ADC clock
__ADC1_CLK_ENABLE();
// Configure ADC
- AdcHandle.Init.OversamplingMode = DISABLE;
- AdcHandle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV1;
- AdcHandle.Init.Resolution = ADC_RESOLUTION12b;
- AdcHandle.Init.SamplingTime = ADC_SAMPLETIME_239CYCLES_5;
- AdcHandle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
- AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
- AdcHandle.Init.ContinuousConvMode = DISABLE;
- AdcHandle.Init.DiscontinuousConvMode = DISABLE;
- AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIG_EDGE_NONE;
- AdcHandle.Init.ExternalTrigConv = ADC_EXTERNALTRIG0_T6_TRGO; // Not used here
- AdcHandle.Init.DMAContinuousRequests = DISABLE;
- AdcHandle.Init.EOCSelection = EOC_SINGLE_CONV;
- AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN;
- AdcHandle.Init.LowPowerAutoWait = ENABLE;
- AdcHandle.Init.LowPowerFrequencyMode = DISABLE; // To be enabled only if ADC clock < 2.8 MHz
- AdcHandle.Init.LowPowerAutoPowerOff = DISABLE;
+ obj->handle.Init.OversamplingMode = DISABLE;
+ obj->handle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV1;
+ obj->handle.Init.Resolution = ADC_RESOLUTION12b;
+ obj->handle.Init.SamplingTime = ADC_SAMPLETIME_239CYCLES_5;
+ obj->handle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
+ obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ obj->handle.Init.ContinuousConvMode = DISABLE;
+ obj->handle.Init.DiscontinuousConvMode = DISABLE;
+ obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIG_EDGE_NONE;
+ obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIG0_T6_TRGO; // Not used here
+ obj->handle.Init.DMAContinuousRequests = DISABLE;
+ obj->handle.Init.EOCSelection = EOC_SINGLE_CONV;
+ obj->handle.Init.Overrun = OVR_DATA_OVERWRITTEN;
+ obj->handle.Init.LowPowerAutoWait = ENABLE;
+ obj->handle.Init.LowPowerFrequencyMode = DISABLE; // To be enabled only if ADC clock < 2.8 MHz
+ obj->handle.Init.LowPowerAutoPowerOff = DISABLE;
- if (HAL_ADC_Init(&AdcHandle) != HAL_OK) {
+ if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
error("Cannot initialize ADC");
}
// Calibration
- HAL_ADCEx_Calibration_Start(&AdcHandle, ADC_SINGLE_ENDED);
+ HAL_ADCEx_Calibration_Start(&obj->handle, ADC_SINGLE_ENDED);
- __HAL_ADC_ENABLE(&AdcHandle);
+ __HAL_ADC_ENABLE(&obj->handle);
}
}
@@ -112,8 +109,6 @@
{
ADC_ChannelConfTypeDef sConfig = {0};
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
// Configure ADC channel
sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
switch (obj->channel) {
@@ -181,13 +176,13 @@
}
ADC1->CHSELR = 0; // [TODO] Workaround. To be removed after Cube driver is corrected.
- HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
+ HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
- HAL_ADC_Start(&AdcHandle); // Start conversion
+ HAL_ADC_Start(&obj->handle); // Start conversion
// Wait end of conversion and get value
- if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
- return (HAL_ADC_GetValue(&AdcHandle));
+ if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+ return (HAL_ADC_GetValue(&obj->handle));
} else {
return 0;
}
--- a/targets/TARGET_STM/TARGET_STM32L0/common_objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/common_objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -116,6 +116,12 @@
uint32_t dummy;
};
+struct analogin_s {
+ ADC_HandleTypeDef handle;
+ PinName pin;
+ uint8_t channel;
+};
+
#include "gpio_object.h"
#if DEVICE_ANALOGOUT
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
#define GPIO_IP_WITHOUT_BRR
#include "common_objects.h"
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
#define GPIO_IP_WITHOUT_BRR
#include "common_objects.h"
--- a/targets/TARGET_STM/TARGET_STM32L1/analogin_api.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/analogin_api.c Wed Aug 16 18:27:13 2017 +0100
@@ -36,8 +36,6 @@
#include "mbed_error.h"
#include "PeripheralPins.h"
-ADC_HandleTypeDef AdcHandle;
-
int adc_inited = 0;
void analogin_init(analogin_t *obj, PinName pin)
@@ -45,8 +43,8 @@
RCC_OscInitTypeDef RCC_OscInitStruct;
// Get the peripheral name from the pin and assign it to the object
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
- MBED_ASSERT(obj->adc != (ADCName)NC);
+ obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
// Get the pin function and assign the used channel to the object
uint32_t function = pinmap_function(pin, PinMap_ADC);
@@ -73,29 +71,28 @@
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
+ obj->handle.State = HAL_ADC_STATE_RESET;
// Enable ADC clock
__ADC1_CLK_ENABLE();
// Configure ADC
- AdcHandle.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4;
- AdcHandle.Init.Resolution = ADC_RESOLUTION12b;
- AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
- AdcHandle.Init.ScanConvMode = DISABLE; // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1)
- AdcHandle.Init.EOCSelection = EOC_SINGLE_CONV; // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example).
- AdcHandle.Init.LowPowerAutoWait = ADC_AUTOWAIT_UNTIL_DATA_READ; // Enable the dynamic low power Auto Delay: new conversion start only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
- AdcHandle.Init.LowPowerAutoPowerOff = ADC_AUTOPOWEROFF_IDLE_PHASE; // Enable the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
- AdcHandle.Init.ChannelsBank = ADC_CHANNELS_BANK_A;
- AdcHandle.Init.ContinuousConvMode = DISABLE; // Continuous mode disabled to have only 1 conversion at each conversion trig
- AdcHandle.Init.NbrOfConversion = 1; // Parameter discarded because sequencer is disabled
- AdcHandle.Init.DiscontinuousConvMode = DISABLE; // Parameter discarded because sequencer is disabled
- AdcHandle.Init.NbrOfDiscConversion = 1; // Parameter discarded because sequencer is disabled
- AdcHandle.Init.ExternalTrigConv = 0; // Not used
- AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
- AdcHandle.Init.DMAContinuousRequests = DISABLE;
+ obj->handle.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4;
+ obj->handle.Init.Resolution = ADC_RESOLUTION12b;
+ obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ obj->handle.Init.ScanConvMode = DISABLE; // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1)
+ obj->handle.Init.EOCSelection = EOC_SINGLE_CONV; // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example).
+ obj->handle.Init.LowPowerAutoWait = ADC_AUTOWAIT_UNTIL_DATA_READ; // Enable the dynamic low power Auto Delay: new conversion start only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
+ obj->handle.Init.LowPowerAutoPowerOff = ADC_AUTOPOWEROFF_IDLE_PHASE; // Enable the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
+ obj->handle.Init.ChannelsBank = ADC_CHANNELS_BANK_A;
+ obj->handle.Init.ContinuousConvMode = DISABLE; // Continuous mode disabled to have only 1 conversion at each conversion trig
+ obj->handle.Init.NbrOfConversion = 1; // Parameter discarded because sequencer is disabled
+ obj->handle.Init.DiscontinuousConvMode = DISABLE; // Parameter discarded because sequencer is disabled
+ obj->handle.Init.NbrOfDiscConversion = 1; // Parameter discarded because sequencer is disabled
+ obj->handle.Init.ExternalTrigConv = 0; // Not used
+ obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ obj->handle.Init.DMAContinuousRequests = DISABLE;
- if (HAL_ADC_Init(&AdcHandle) != HAL_OK) {
+ if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
error("Cannot initialize ADC");
}
}
@@ -105,8 +102,6 @@
{
ADC_ChannelConfTypeDef sConfig = {0};
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
// Configure ADC channel
switch (obj->channel) {
case 0:
@@ -222,13 +217,13 @@
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_16CYCLES;
- HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
+ HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
- HAL_ADC_Start(&AdcHandle); // Start conversion
+ HAL_ADC_Start(&obj->handle); // Start conversion
// Wait end of conversion and get value
- if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
- return (HAL_ADC_GetValue(&AdcHandle));
+ if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+ return (HAL_ADC_GetValue(&obj->handle));
} else {
return 0;
}
--- a/targets/TARGET_STM/TARGET_STM32L1/common_objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/common_objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -122,6 +122,12 @@
DAC_HandleTypeDef handle;
};
+struct analogin_s {
+ ADC_HandleTypeDef handle;
+ PinName pin;
+ uint8_t channel;
+};
+
#include "gpio_object.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -54,12 +54,6 @@
__IO uint32_t *reg_out;
};
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
struct can_s {
CANName can;
int index;
--- a/targets/TARGET_STM/TARGET_STM32L4/analogin_api.c Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/analogin_api.c Wed Aug 16 18:27:13 2017 +0100
@@ -36,14 +36,11 @@
#include "mbed_error.h"
#include "PeripheralPins.h"
-ADC_HandleTypeDef AdcHandle;
-
int adc_inited = 0;
void analogin_init(analogin_t *obj, PinName pin)
{
uint32_t function = (uint32_t)NC;
- obj->adc = (ADCName)NC;
// ADC Internal Channels "pins" (Temperature, Vref, Vbat, ...)
// are described in PinNames.h and PeripheralPins.c
@@ -51,18 +48,18 @@
if ((pin < 0xF0) || (pin >= 0x100)) {
// Normal channels
// Get the peripheral name from the pin and assign it to the object
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+ obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
// Get the functions (adc channel) from the pin and assign it to the object
function = pinmap_function(pin, PinMap_ADC);
// Configure GPIO
pinmap_pinout(pin, PinMap_ADC);
} else {
// Internal channels
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC_Internal);
+ obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal);
function = pinmap_function(pin, PinMap_ADC_Internal);
// No GPIO configuration for internal channels
}
- MBED_ASSERT(obj->adc != (ADCName)NC);
+ MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
MBED_ASSERT(function != (uint32_t)NC);
obj->channel = STM_PIN_CHANNEL(function);
@@ -78,26 +75,25 @@
__HAL_RCC_ADC_CLK_ENABLE();
__HAL_RCC_ADC_CONFIG(RCC_ADCCLKSOURCE_SYSCLK);
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
+ obj->handle.State = HAL_ADC_STATE_RESET;
// Configure ADC
- AdcHandle.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2; // Asynchronous clock mode, input ADC clock
- AdcHandle.Init.Resolution = ADC_RESOLUTION_12B;
- AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
- AdcHandle.Init.ScanConvMode = DISABLE; // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1)
- AdcHandle.Init.EOCSelection = ADC_EOC_SINGLE_CONV; // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example).
- AdcHandle.Init.LowPowerAutoWait = DISABLE;
- AdcHandle.Init.ContinuousConvMode = DISABLE; // Continuous mode disabled to have only 1 conversion at each conversion trig
- AdcHandle.Init.NbrOfConversion = 1; // Parameter discarded because sequencer is disabled
- AdcHandle.Init.DiscontinuousConvMode = DISABLE; // Parameter discarded because sequencer is disabled
- AdcHandle.Init.NbrOfDiscConversion = 1; // Parameter discarded because sequencer is disabled
- AdcHandle.Init.ExternalTrigConv = ADC_SOFTWARE_START; // Software start to trig the 1st conversion manually, without external event
- AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
- AdcHandle.Init.DMAContinuousRequests = DISABLE;
- AdcHandle.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; // DR register is overwritten with the last conversion result in case of overrun
- AdcHandle.Init.OversamplingMode = DISABLE; // No oversampling
+ obj->handle.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2; // Asynchronous clock mode, input ADC clock
+ obj->handle.Init.Resolution = ADC_RESOLUTION_12B;
+ obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ obj->handle.Init.ScanConvMode = DISABLE; // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1)
+ obj->handle.Init.EOCSelection = ADC_EOC_SINGLE_CONV; // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example).
+ obj->handle.Init.LowPowerAutoWait = DISABLE;
+ obj->handle.Init.ContinuousConvMode = DISABLE; // Continuous mode disabled to have only 1 conversion at each conversion trig
+ obj->handle.Init.NbrOfConversion = 1; // Parameter discarded because sequencer is disabled
+ obj->handle.Init.DiscontinuousConvMode = DISABLE; // Parameter discarded because sequencer is disabled
+ obj->handle.Init.NbrOfDiscConversion = 1; // Parameter discarded because sequencer is disabled
+ obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START; // Software start to trig the 1st conversion manually, without external event
+ obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ obj->handle.Init.DMAContinuousRequests = DISABLE;
+ obj->handle.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; // DR register is overwritten with the last conversion result in case of overrun
+ obj->handle.Init.OversamplingMode = DISABLE; // No oversampling
- if (HAL_ADC_Init(&AdcHandle) != HAL_OK) {
+ if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
error("Cannot initialize ADC\n");
}
}
@@ -107,8 +103,6 @@
{
ADC_ChannelConfTypeDef sConfig = {0};
- AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
// Configure ADC channel
switch (obj->channel) {
case 0:
@@ -178,13 +172,13 @@
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
- HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
+ HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
- HAL_ADC_Start(&AdcHandle); // Start conversion
+ HAL_ADC_Start(&obj->handle); // Start conversion
// Wait end of conversion and get value
- if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
- return (HAL_ADC_GetValue(&AdcHandle));
+ if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
+ return (HAL_ADC_GetValue(&obj->handle));
} else {
return 0;
}
--- a/targets/TARGET_STM/TARGET_STM32L4/common_objects.h Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/common_objects.h Wed Aug 16 18:27:13 2017 +0100
@@ -116,6 +116,12 @@
uint32_t dummy;
};
+struct analogin_s {
+ ADC_HandleTypeDef handle;
+ PinName pin;
+ uint8_t channel;
+};
+
#include "gpio_object.h"
struct dac_s {
--- a/targets/targets.json Thu Aug 03 13:13:39 2017 +0100
+++ b/targets/targets.json Wed Aug 16 18:27:13 2017 +0100
@@ -1022,9 +1022,10 @@
},
"detect_code": ["0826"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": ["CAN", "ERROR_RED", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG"],
+ "device_has_add": ["CAN", "ERROR_RED", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
- "device_name": "STM32F412ZG"
+ "device_name": "STM32F412ZG",
+ "bootloader_supported": true
},
"DISCO_F413ZH": {
"inherits": ["FAMILY_STM32"],
@@ -1680,7 +1681,7 @@
"supported_form_factors": ["ARDUINO"],
"core": "Cortex-M4F",
"extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx", "STM32F439xI"],
- "macros": ["HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED","MBEDTLS_ARC4_C","MBEDTLS_DES_C","MBEDTLS_MD4_C","MBEDTLS_MD5_C","MBEDTLS_SHA1_C"],
+ "macros": ["MBEDTLS_CONFIG_HW_SUPPORT", "HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED","MBEDTLS_ARC4_C","MBEDTLS_DES_C","MBEDTLS_MD4_C","MBEDTLS_MD5_C","MBEDTLS_SHA1_C"],
"device_has_add": ["CAN", "EMAC", "TRNG", "FLASH"],
"device_has_remove": ["RTC", "SLEEP"],
"features": ["LWIP"],
@@ -1707,10 +1708,11 @@
}
},
"macros_add": ["RTC_LSI=1", "HSE_VALUE=12000000", "GNSSBAUD=9600"],
- "device_has_add": ["ANALOGOUT", "TRNG"],
+ "device_has_add": ["ANALOGOUT", "SERIAL_FC", "TRNG", "FLASH"],
"features": ["LWIP"],
"public": false,
- "device_name": "STM32F437VG"
+ "device_name": "STM32F437VG",
+ "bootloader_supported": true
},
"UBLOX_C030_U201": {
"inherits": ["UBLOX_C030"],
@@ -2304,10 +2306,11 @@
"MAX32630FTHR": {
"inherits": ["Target"],
"core": "Cortex-M4F",
- "macros": ["__SYSTEM_HFX=96000000", "TARGET=MAX32630", "TARGET_REV=0x4132"],
+ "macros": ["__SYSTEM_HFX=96000000", "TARGET=MAX32630", "TARGET_REV=0x4132", "BLE_HCI_UART", "OPEN_DRAIN_LEDS"],
"extra_labels": ["Maxim", "MAX32630"],
"supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
"device_has": ["ANALOGIN", "ERROR_RED", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+ "features": ["BLE"],
"release_versions": ["2", "5"]
},
"EFM32": {
@@ -3162,6 +3165,7 @@
"value": "0xFFFFFFFF"
}
},
+ "OUTPUT_EXT": "hex",
"post_binary_hook": {"function": "NCS36510TargetCode.ncs36510_addfib"},
"macros": ["CM3", "CPU_NCS36510", "TARGET_NCS36510", "LOAD_ADDRESS=0x3000"],
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
